WO2025022733A1 - 駆動回路および動作方法 - Google Patents

駆動回路および動作方法 Download PDF

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Publication number
WO2025022733A1
WO2025022733A1 PCT/JP2024/014814 JP2024014814W WO2025022733A1 WO 2025022733 A1 WO2025022733 A1 WO 2025022733A1 JP 2024014814 W JP2024014814 W JP 2024014814W WO 2025022733 A1 WO2025022733 A1 WO 2025022733A1
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Prior art keywords
terminal
voltage
circuit
switch
full
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English (en)
French (fr)
Japanese (ja)
Inventor
史人 草間
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/605—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors with galvanic isolation between the control circuit and the output circuit
    • H03K17/61—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
    • H03K17/691—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling

Definitions

  • This disclosure relates to a driving circuit for driving a transistor, etc.
  • Patent document 1 discloses a drive circuit that uses a pulse transformer.
  • the pulse transformer becomes biased, so a reset period is required for the transformer and a high duty pulse cannot be output.
  • the transformer does not become biased and a reset period is not required, but the secondary circuit is half-wave rectified, so only pulses with a duty of 50% or less can be output.
  • the present disclosure provides a drive circuit and the like that can achieve a duty ratio greater than 50% without causing bias magnetism in the transformer and can also prevent erroneous firing of the main bridge circuit.
  • the drive circuit according to the present disclosure is a drive circuit for driving a transistor having a first terminal which is a gate or base, a second terminal which is a source or emitter, and a third terminal which is a drain or collector, and includes an isolated pulse transformer, a full-wave rectifier circuit connected to a secondary winding of the pulse transformer, and an extraction circuit connected between the full-wave rectifier circuit and the transistor, connected to the first terminal and the second terminal, and for extracting current from the first terminal when the transistor is turned off, and there is a phase difference between a signal input to one terminal of the primary winding of the pulse transformer and a signal input to the other terminal.
  • the operating method is a method of operating a drive circuit for driving a transistor having a first terminal which is a gate or base, a second terminal which is a source or emitter, and a third terminal which is a drain or collector, and includes the steps of inputting signals having a phase difference to one end terminal and the other end terminal of a primary winding of an isolated pulse transformer, full-wave rectifying a signal output from a secondary winding of the pulse transformer, outputting the full-wave rectified signal to the first terminal, and drawing a current from the first terminal when the transistor is turned off.
  • the drive circuit according to one embodiment of the present disclosure can achieve a duty ratio of more than 50% without causing bias magnetism in the transformer, and can also prevent erroneous firing of the main bridge circuit.
  • FIG. 2 is a circuit diagram showing an example of a drive circuit according to the first embodiment
  • FIG. 13 is a diagram for explaining that a duty ratio of 5% can be realized.
  • FIG. 13 is a diagram for explaining that a duty ratio of 50% can be realized.
  • FIG. 13 is a diagram for explaining that a duty ratio of 95% can be realized.
  • 1 is a diagram showing an example of application of the drive circuit according to the first embodiment to a main bridge circuit
  • 4 is a diagram for explaining the operation of the drive circuit according to the first embodiment
  • FIG. 5 is a diagram for explaining the operation of the drive circuit according to the first embodiment when the FET is turned off.
  • FIG. 4 is a diagram for explaining the operation of the drive circuit according to the first embodiment when a FET is turned on;
  • FIG. 11 is a circuit diagram showing an example of a drive circuit according to a second embodiment.
  • FIG. 11 is a circuit diagram showing an example of a drive circuit according to a third embodiment.
  • FIG. 13 is a circuit diagram showing an example of a drive circuit according to a fourth embodiment.
  • FIG. 13 is a circuit diagram showing an example of a drive circuit according to a fifth embodiment.
  • FIG. 13 is a circuit diagram showing an example of a drive circuit according to a sixth embodiment.
  • 10 is a flowchart illustrating an example of an operation method according to another embodiment.
  • FIG. 1 is a circuit diagram showing an example of a drive circuit 1 according to the first embodiment.
  • the drive circuit 1 is a circuit for driving a transistor having a first terminal which is a gate or base, a second terminal which is a source or emitter, and a third terminal which is a drain or collector.
  • the transistor in question is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a GaN FET, or a bipolar transistor.
  • the transistor driven by the drive circuit 1 is referred to as a FET, with the first terminal being the gate, the second terminal being the source, and the third terminal being the drain.
  • the inter-terminal voltage between the first and second terminals is the gate-source voltage of the FET
  • the voltage of the second terminal is the source voltage of the FET.
  • transistor driven by drive circuit 1 is a bipolar transistor
  • FET can be read as “bipolar transistor”
  • FET gate can be read as “bipolar transistor base”
  • FET source can be read as “bipolar transistor emitter”
  • FET drain can be read as “bipolar transistor collector.”
  • FET gate-source voltage can be read as “bipolar transistor base-emitter voltage”
  • FET source voltage can be read as “bipolar transistor emitter voltage.”
  • terminal t5 shown in FIG. 1 is connected to the gate of the FET, and terminal t6 is connected to the source of the FET. This allows the drive circuit 1 to control the on and off of the FET.
  • the drive circuit 1 includes a power supply Bat, a phase control circuit 10, a pulse transformer T1, a resistor R10, a capacitor C10, a full-wave rectifier circuit 21, and a pull-out circuit 31.
  • the capacitor Cgs in FIG. 1 represents the gate-source capacitance of the FET connected to terminals t5 and t6.
  • the pulse transformer T1 is an isolated pulse transformer with an isolated primary winding L1 and secondary winding L2. For example, some systems use a photocoupler to transmit signals while isolating the primary and secondary sides, but this system requires a separate isolated power supply. On the other hand, the pulse transformer T1 can transmit both the power and signals to drive the FET while isolating the primary and secondary sides.
  • phase control circuit 10 can provide a phase difference between the signal Vin1 input to terminal t1 and the signal Vin2 input to terminal t2.
  • the signals Vin1 and Vin2 are each a pulse signal, and the pulse signals are generated by the voltage Vcc of the power supply Bat.
  • a voltage VT1 with the polarity shown in FIG. 1 is generated in primary winding L1.
  • a voltage VT2 with the polarity shown in FIG. 1 is generated in secondary winding L2.
  • the full-wave rectifier circuit 21 is connected to the secondary winding L2 of the pulse transformer T1.
  • the full-wave rectifier circuit 21 is connected to the secondary winding L2 via an RC circuit consisting of a resistor R10 and a capacitor C10.
  • the RC circuit consisting of the resistor R10 and the capacitor C10 is a circuit for suppressing ringing caused by the leakage inductance of the pulse transformer T1.
  • the drive circuit 1 does not need to include the resistor R10 and the capacitor C10, and a resistor R5 described below may also perform this function.
  • This RC circuit may or may not be provided, so hereinafter, descriptions such as "connected to terminal t3" also include the case where the circuit is connected to terminal t3 via such an RC circuit.
  • the full-wave rectifier circuit 21 includes two switches Q1 and Q2 connected in series to form a full-bridge circuit, and two diodes D3 and D4 connected in series to form the full-bridge circuit.
  • the node between the two switches Q1 and Q2 is connected to a terminal t3 at one end of the secondary winding L2 of the pulse transformer T1.
  • the node between the two diodes D3 and D4 is connected to a terminal t4 at the other end of the secondary winding L2 of the pulse transformer T1.
  • the switch Q1 is, for example, a P-channel MOSFET.
  • the drain of the switch Q1 is connected to the drain of the switch Q2 and the terminal t3, and the source of the switch Q1 is connected to the cathode of the diode D3 and the extraction circuit 31.
  • the gate of the switch Q1 is connected to the node between the two diodes D3 and D4.
  • FIG. 1 shows the parasitic diode of the switch Q1, and in the equivalent circuit, the anode of the diode is connected to the drain of the switch Q1 and the cathode is connected to the source of the switch Q1.
  • the switch Q2 is, for example, an N-channel MOSFET.
  • the drain of the switch Q2 is connected to the drain of the switch Q1 and to the terminal t3, and the source of the switch Q2 is connected to the terminal t6.
  • the gate of the switch Q2 is connected to the node between the two diodes D3 and D4.
  • FIG. 1 shows a parasitic diode of the switch Q2, and in the equivalent circuit, the anode of the diode is connected to the source of the switch Q2, and the cathode is connected to the drain of the switch Q2.
  • the anode of diode D3 is connected to the cathode of diode D4, the gates of switches Q1 and Q2, and terminal t4.
  • the cathode of diode D3 is connected to the source of switch Q1 and the extraction circuit 31.
  • the anode of diode D4 is connected to terminal t6.
  • the cathode of diode D4 is connected to the anode of diode D3, the gates of switches Q1 and Q2, and terminal t4.
  • terminals t3 and t4 may be interchanged. Specifically, terminal t4 may be connected to the source of switch Q1 and the drain of switch Q2, and terminal t3 may be connected to the gate of switch Q1, the gate of switch Q2, the anode of diode D3, and the cathode of diode D4.
  • the full-wave rectifier circuit 21 performs full-wave rectification on the voltage generated in the secondary winding L2 and outputs the result to the gate of the FET.
  • a voltage Vo2 is shown as the output voltage of the full-wave rectifier circuit 21.
  • voltages of different polarities are generated in the state B where a high signal is input to the terminal t1 and a low signal is input to the terminal t2, and in the state D where a low signal is input to the terminal t1 and a high signal is input to the terminal t2.
  • the full-wave rectifier circuit 21 since the full-wave rectifier circuit 21 is connected to the secondary winding L2, the full-wave rectifier circuit 21 can output the voltage Vo2 corresponding to the absolute value of the voltage generated in the secondary winding L2, regardless of the polarity of the voltage generated in the secondary winding L2 (in other words, regardless of whether the state is B or D). Therefore, the drive circuit 1 can apply a voltage Vgs corresponding to the voltage Vo2 to the FET connected between the terminals t5 and t6.
  • the extraction circuit 31 is connected between the full-wave rectifier circuit 21 and the FET, and is also connected to the gate and source of the FET, and is a circuit for extracting current from the gate of the FET when the FET is turned off. The operation of the extraction circuit 31 will be described in detail later.
  • the extraction circuit 31 includes, for example, resistors R5, R6, R7, R8, and R9, and switches Q5, Q6, and Q7.
  • Resistor R5 is an example of a first circuit that generates a voltage difference between the output voltage of the full-wave rectifier circuit 21 and the gate-source voltage of the FET.
  • Resistors R6, R7, R8, and R9, and switches Q5, Q6, and Q7 are an example of a second circuit that brings the output voltage of the full-wave rectifier circuit 21 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage at terminal t6: for example, 0 V) based on the output voltage of the full-wave rectifier circuit 21 (voltage Vo2), the gate-source voltage of the FET (voltage Vgs), or the voltage difference between the output voltage of the full-wave rectifier circuit 21 and the gate-source voltage of the FET.
  • bringing the output voltage of the full-wave rectifier circuit 21 closer to the source voltage of the FET means bringing the two output terminals of the full-wave rectifier circuit 21 into conduction with a switch, and connecting the source of the FET and both output terminals of the full-wave rectifier circuit 21 with low impedance.
  • bringing the gate-source voltage of the FET closer to the source voltage of the FET means bringing the gate-source of the FET into conduction with a switch, and connecting the source and gate of the FET with low impedance.
  • resistors R6, R7, R8, and R9, and switches Q5, Q6, and Q7 bring the output voltage of full-wave rectifier circuit 21 or the gate-source voltage of the FET closer to the source voltage of the FET based on the voltage difference between the output voltage of full-wave rectifier circuit 21 and the gate-source voltage of the FET.
  • the gate-source voltage of the FET is Vgs
  • the output voltage of full-wave rectifier circuit 21 is Vo2
  • the first threshold voltage set for the second circuit is Vth1 (e.g., 0 V or higher)
  • the source voltage of the FET is Vs
  • the second circuit brings Vo2 or Vgs closer to Vs when Vgs-Vo2>Vth1 (in other words, when Vgs-Vo2 exceeds Vth1).
  • the switch Q5 is, for example, a PNP transistor.
  • the base of the switch Q5 is connected to one end of the resistor R5, one end of the resistor R6, the source of the switch Q1, and the cathode of the diode D3.
  • the collector of the switch Q5 is connected to one end of the resistor R8.
  • the emitter of the switch Q5 is connected to the other end of the resistor R5, one end of the resistor R7, and the terminal t5.
  • the voltage VEB5 shown in FIG. 1 is the emitter-base voltage of the switch Q5.
  • the switch Q6 is, for example, an NPN transistor.
  • the base of the switch Q6 is connected to the base of the switch Q7, the other end of the resistor R8, and one end of the resistor R9.
  • the collector of the switch Q6 is connected to the other end of the resistor R6.
  • the emitter of the switch Q6 is connected to the terminal t6.
  • Switch Q7 is, for example, an NPN transistor.
  • the base of switch Q7 is connected to the base of switch Q6, the other end of resistor R8, and one end of resistor R9.
  • the collector of switch Q7 is connected to the other end of resistor R7.
  • the emitter of switch Q7 is connected to terminal t6.
  • the voltage VBE7 shown in FIG. 1 is the base-emitter voltage of switch Q7.
  • resistor R5 One end of resistor R5 is connected to one end of resistor R6, the base of switch Q5, the source of switch Q1, and the cathode of diode D3, and the other end is connected to the emitter of switch Q5, one end of resistor R7, and terminal t5.
  • resistor R6 One end of resistor R6 is connected to one end of resistor R5, the base of switch Q5, the source of switch Q1, and the cathode of diode D3, and the other end is connected to the collector of switch Q6.
  • resistor R7 One end of resistor R7 is connected to the other end of resistor R5, the emitter of switch Q5, and terminal t5, and the other end is connected to the collector of switch Q7.
  • the current Irg_dn shown in FIG. 1 is the current flowing through resistor R7.
  • resistor R8 is connected to the collector of switch Q5, and the other end is connected to the base of switch Q6, the base of switch Q7, and one end of resistor R9.
  • resistor R9 One end of resistor R9 is connected to the other end of resistor R8, the base of switch Q6, and the base of switch Q7, and the other end is connected to terminal t6.
  • Capacitor Cgs refers to the gate-source capacitance of the FET connected to terminals t5 and t6.
  • the voltage Vgs generated across capacitor Cgs is the gate-source voltage of the FET.
  • the current Ig shown in Figure 1 is the current flowing through capacitor Cgs. In other words, it is the current flowing through the gate of the FET, and the direction in which charge is drawn out is considered positive.
  • Figure 2A is a diagram to explain that a duty ratio of 5% can be achieved.
  • Figure 2B is a diagram to explain that a duty ratio of 50% can be achieved.
  • Figure 2C is a diagram to explain that a duty ratio of 95% can be achieved.
  • FIGS. 2A to 2C show, from the top, the time waveforms of signals Vin1 and Vin2, voltage VT1 and current IT1, voltage VT2 and current IT2, voltage Vgs and current Ig, and voltages VEB5 and VBE7.
  • the full-wave rectifier circuit 21 can generate the voltage Vgs during the above period, and it is possible to achieve, for example, a 5% duty ratio for the switching of the FET.
  • the duty ratio in FIG. 2C will be 47.5%.
  • a duty ratio of only up to 50% can be achieved.
  • the drive circuit 1 is provided with the full-wave rectifier circuit 21, a duty ratio greater than 50% can be achieved, for example, a duty ratio of 5% to 95% can be achieved.
  • FIG. 3 is a diagram showing an example of application of the drive circuit 1 according to the first embodiment to a main bridge circuit.
  • switches MH and ML are shown as the main bridge circuit, and the drive circuit 1 is connected to each of the switches MH and ML.
  • the switches MH and ML are connected between the terminals t5 and t6 of the drive circuit 1, and are an example of an FET driven by the drive circuit 1.
  • the switch MH is, for example, an N-channel MOSFET.
  • the drain of the switch MH is connected to the power supply of the voltage Vbus.
  • the source of the switch MH is connected to terminal t6 of the upper drive circuit 1 in FIG. 3, the drain of the switch ML, and a component (e.g., a transformer or an inductor) provided on the output side of the main bridge circuit.
  • the gate of the switch MH is connected to terminal t5 of the upper drive circuit 1 in FIG. 3.
  • FIG. 3 shows the parasitic diode of the switch MH, and in the equivalent circuit, the anode of the diode is connected to the source of the switch MH and the cathode is connected to the drain of the switch MH.
  • the switch ML is, for example, an N-channel MOSFET.
  • the drain of the switch ML is connected to the source of the switch MH and a component (such as a transformer or inductor) provided on the output side of the main bridge circuit.
  • the source of the switch ML is connected to the terminal t6 of the drive circuit 1 on the lower side of FIG. 3 and the ground terminal of the main bridge circuit.
  • the gate of the switch ML is connected to the terminal t5 of the drive circuit 1 on the lower side of FIG. 3.
  • FIG. 3 shows a parasitic diode of the switch ML, and the anode of the diode is connected to the source of the switch ML and the cathode is connected to the drain of the switch ML in the equivalent circuit.
  • the voltage Vgs shown in FIG. 3 is the gate-source voltage of the switch ML and corresponds to the voltage Vgs shown in FIG. 1.
  • the voltage Vds shown in FIG. 3 is the drain-source voltage of the switch ML.
  • the current Idg shown in FIG. 3 is the current that flows into the gate of switch ML via parasitic capacitance Cgd, and thus into terminal t5 of drive circuit 1 at the bottom of FIG. 3.
  • FIG. 4 is a diagram for explaining the operation of the drive circuit 1 (specifically, the drive circuit 1 of the switch ML) according to the first embodiment.
  • the signal Vin1 is a low signal and the signal Vin2 is a low signal, the voltages VT1 and VT2 are 0V, and the voltage Vgs is 0V.
  • the signal Vin1 is a high signal and the signal Vin2 is a low signal, the voltages VT1 and VT2 are Vcc (e.g., 15V), and the voltage Vgs is Vcc.
  • the signal Vin1 is a high signal and the signal Vin2 is a high signal, the voltages VT1 and VT2 are 0V, and the voltage Vgs is 0V.
  • the signal Vin1 is a low signal and the signal Vin2 is a high signal
  • the voltages VT1 and VT2 are -Vcc (e.g., -15V)
  • the voltage Vgs is Vcc.
  • switches MH and ML are provided with a dead time during which both switches MH and ML are in the off state, and are controlled so that outside of the dead time, switch ML is in the off state when switch MH is in the on state, and switch ML is in the on state when switch MH is in the off state.
  • the voltage Vgs of the switch ML is 0 V, so the voltage Vds of the switch ML is the voltage Vbus. Also, during periods (2) and (4), the voltage Vgs of the switch ML is Vcc, so the voltage Vds of the switch ML is 0 V.
  • FIG. 5 is a diagram for explaining the operation of the drive circuit 1 (specifically, the drive circuit 1 for the switch ML) according to the first embodiment when the FET (switch ML) is turned off.
  • FIG. 6 is a diagram for explaining the operation of the drive circuit 1 (specifically, the drive circuit 1 for the switch ML) according to the first embodiment when the FET (switch ML) is turned on.
  • the signal Vin2 switches from a high signal to a low signal, and the voltage VT2 changes from -Vcc to 0V. Since the switch Q2 is on, the gate voltage of the switch Q1 drops and the switch Q1 turns on. That is, in the period (7) shown in FIG. 5, the switches Q1 and Q2 are on, and the voltage Vo2 drops rapidly.
  • the switches Q1 and Q2 are on when the switch ML turns off (specifically, when the maximum voltage of the terminal t3 becomes smaller than the voltage Vo2, or when the minimum voltage of the terminal t4 becomes larger than 0V), and the voltage Vo2 of the full-wave rectifier circuit 21 can be shorted to the source terminal (terminal t6) of the switch ML, and erroneous firing of the switch ML can be reliably prevented.
  • the switch Q6 does not need to be provided.
  • voltage Vo2 could only be reduced to the voltage Vgs.th of switches Q1 and Q2 (i.e., a voltage of Vgs.th x 2). However, by providing switches Q6 and Q7, voltage Vo2 can be reduced to 0V.
  • switch MH turns on, causing the voltage Vds of switch ML to rise and current Idg to flow into drive circuit 1.
  • the voltage VBE7 of switch Q7 is sufficiently higher than voltage Vbe.th, and switch Q7 can be maintained in the on state. This allows switch Q7 to maintain a low impedance between terminals t5 and t6, preventing erroneous firing of switch ML.
  • the rate at which voltage VBE7 drops can be determined according to the size of resistor R9.
  • switch Q6 can maintain its on state, and current Idg flows through resistors R5 and R6 to switch Q6. At this time, a voltage is applied between the base and emitter of switch Q5, and when switch Q5 is turned on, it operates in the direction in which a voltage is applied between the base and emitter of switch Q6. Therefore, depending on the magnitude of current Idg or the setting of resistor R5, switch Q7 may not be provided.
  • switches Q5, Q6, and Q7 are circuits for drawing out current Idg, but as explained in Figure 6, they are automatically turned off when voltage Vgs rises.
  • the full-wave rectifier circuit 21 and the extraction circuit 31 can reduce the impedance between terminals t5 and t6, preventing false ignition of the main bridge circuit.
  • states B and D voltages of different polarities are generated in the secondary winding L2, but because a full-wave rectifier circuit 21 is connected to the secondary winding L2, the drive circuit 1 can apply a voltage to the switch ML regardless of the polarity of the voltage generated in the secondary winding L2 (in other words, regardless of whether the state is B or D). For example, if a voltage can be applied to the switch ML only in states B and D among states A, B, C, and D, a maximum duty ratio of only 50% can be realized. However, if a voltage can be applied to the switch ML in both states B and D among states A, B, C, and D, various duty ratios can be realized. Therefore, a duty ratio greater than 50% can be realized.
  • the drive circuit 1 is provided with an extraction circuit 31 for extracting the current Idg from the gate of the switch ML when the switch ML is turned off, which prevents erroneous firing of the switch ML and enables high-speed turn-off and turn-on.
  • the extraction circuit 31 can bring the voltage Vo2 or Vgs closer to the source voltage of the switch ML (the voltage at the terminal t6: for example, 0 V), thereby preventing erroneous firing of the switch ML.
  • Vgs-Vo2 exceeds Vth1
  • Vth1 that is, when the absolute value of the voltage generated in the secondary winding L2 becomes small and the switch ML turns off
  • FIG. 7 is a circuit diagram showing an example of a drive circuit 2 according to the second embodiment.
  • the drive circuit 2 differs from the drive circuit 1 according to the first embodiment in that it includes a full-wave rectifier circuit 22 instead of the full-wave rectifier circuit 21, and a pull-out circuit 32 instead of the pull-out circuit 31.
  • the rest of the configuration is the same as that of the first embodiment, so a description thereof will be omitted.
  • the full-wave rectifier circuit 22 is connected to the secondary winding L2 of the pulse transformer T1. Note that, in FIG. 7, an example is shown in which the full-wave rectifier circuit 22 is connected to the secondary winding L2 via an RC circuit consisting of a resistor R10 and a capacitor C10, but as in the first embodiment, this RC circuit does not have to be provided.
  • the full-wave rectifier circuit 22 includes two diodes D1 and D2 connected in series to form a full-bridge circuit, and two diodes D3 and D4 connected in series to form the full-bridge circuit.
  • the node between the two diodes D1 and D2 is connected to a terminal t3 at one end of the secondary winding L2 of the pulse transformer T1.
  • the node between the two diodes D3 and D4 is connected to a terminal t4 at the other end of the secondary winding L2 of the pulse transformer T1.
  • the full-wave rectifier circuit 22 also includes a resistor R4 connected in parallel with the diode D4.
  • the anode of diode D1 is connected to the cathode of diode D2, terminal t3, and the extraction circuit 32.
  • the cathode of diode D1 is connected to the cathode of diode D3 and the extraction circuit 32.
  • the anode of diode D3 is connected to the cathode of diode D4, terminal t4, and the extraction circuit 32.
  • the cathode of diode D3 is connected to the cathode of diode D1 and the extraction circuit 32.
  • the anode of diode D4 is connected to terminal t6.
  • the cathode of diode D4 is connected to the anode of diode D3, terminal t4, and the extraction circuit 32.
  • the full-wave rectifier circuit 22 performs full-wave rectification on the voltage generated in the secondary winding L2 and outputs the result to the gate of the FET.
  • a voltage Vo2 is shown as the output voltage of the full-wave rectifier circuit 22.
  • the secondary winding L2 voltages of different polarities are generated in the state B where a high signal is input to the terminal t1 and a low signal is input to the terminal t2, and in the state D where a low signal is input to the terminal t1 and a high signal is input to the terminal t2.
  • the full-wave rectifier circuit 22 since the full-wave rectifier circuit 22 is connected to the secondary winding L2, the full-wave rectifier circuit 22 can output the voltage Vo2 corresponding to the absolute value of the voltage generated in the secondary winding L2, regardless of the polarity of the voltage generated in the secondary winding L2 (in other words, regardless of the state B or D). Therefore, the drive circuit 2 can apply a voltage Vgs corresponding to the voltage Vo2 to the FET connected between the terminals t5 and t6.
  • the extraction circuit 32 is a circuit that extracts current from the gate of the FET when the FET is turned off. The operation of the extraction circuit 32 will be described in detail later.
  • the resistors R13, R14, and R15, and the switches Q8 and Q9 are an example of a second circuit that brings the output voltage of the full-wave rectifier circuit 22 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage of the terminal t6: for example, 0 V) based on the output voltage of the full-wave rectifier circuit 22, the gate-source voltage of the FET, or the voltage difference between the output voltage of the full-wave rectifier circuit 22 and the gate-source voltage of the FET.
  • the diodes D5 and D6 and the resistor R11 are an example of a third circuit.
  • the threshold voltage set for the third circuit is Vth2 (e.g., 0V or higher)
  • the source voltage of the FET is Vs
  • the value obtained by subtracting Vs from the higher of the voltages at one terminal and the other terminal of the secondary winding of the pulse transformer T1 i.e., the voltage based on the source voltage of the FET
  • the third circuit causes the second circuit to bring Vo2 closer to Vs when Vo2-VT2>Vth2 (in other words, when Vo2-VT2 exceeds Vth2).
  • bringing the output voltage of the full-wave rectifier circuit 22 closer to the source voltage of the FET means connecting the two output terminals of the full-wave rectifier circuit 22 with a switch to conduct electricity, and connecting the source of the FET and both output terminals of the full-wave rectifier circuit 22 with low impedance.
  • resistors R13, R14, and R15 and switches Q8 and Q9 bring the output voltage of the full-wave rectifier circuit 22 or the gate-source voltage of the FET closer to the source voltage of the FET based on the voltage difference between the output voltage of the full-wave rectifier circuit 22 and the gate-source voltage of the FET.
  • resistors R13, R14, and R15 and switches Q8 and Q9 bring the output voltage of the full-wave rectifier circuit 22 or the gate-source voltage of the FET closer to the source voltage of the FET.
  • the switch Q8 is, for example, a PNP transistor.
  • the base of the switch Q8 is connected to one end of the resistor R11, the cathode of the diode D5, and the cathode of the diode D6.
  • the collector of the switch Q8 is connected to one end of the resistor R13.
  • the emitter of the switch Q8 is connected to one end of the resistor R12, one end of the resistor R14, the base of the switch Q9, the cathode of the diode D1, and the cathode of the diode D3.
  • the switch Q9 is, for example, a PNP transistor.
  • the base of the switch Q9 is connected to the emitter of the switch Q8, one end of the resistor R12, one end of the resistor R14, the cathode of the diode D1, and the cathode of the diode D3.
  • the collector of the switch Q9 is connected to the other end of the resistor R12 and the terminal t5.
  • the emitter of the switch Q9 is connected to one end of the resistor R15.
  • the anode of diode D5 is connected to the anode of diode D1, the cathode of diode D2, and terminal t3.
  • the cathode of diode D5 is connected to the cathode of diode D6, the base of switch Q8, and one end of resistor R11.
  • Resistor R11 is connected in parallel with diode D6.
  • resistor R12 is connected to the emitter of switch Q8, the base of switch Q9, one end of resistor R14, the cathode of diode D1, and the cathode of diode D3, and the other end is connected to the emitter of switch Q9 and terminal t5.
  • resistor R13 One end of resistor R13 is connected to the collector of switch Q8, and the other end is connected to terminal t6.
  • resistor R14 One end of resistor R14 is connected to the base of switch Q9, the emitter of switch Q8, one end of resistor R12, the cathode of diode D1, and the cathode of diode D3, and the other end is connected to terminal t6.
  • resistor R15 One end of resistor R15 is connected to the collector of switch Q9, and the other end is connected to terminal t6.
  • drive circuit 2 can also achieve a duty ratio greater than 50%.
  • switch ML When switch ML turns off, for example, voltage VT2 changes from -Vcc to 0V.
  • the voltage VT2 across the secondary winding L2 approaches the voltage at terminal t6 (the source voltage of switch ML) as it is pulled down by resistor R4.
  • the base of switch Q8 approaches the voltage at terminal t6 as it is pulled down towards resistor R4 by resistor R11.
  • switch Q8 turns on.
  • switch Q8 When switch Q8 is turned on, voltage Vo2 drops and current flows through a path passing through terminal t5, resistor R12, switch Q8, resistor 13, and terminal t6, making it possible to extract current Idg from the gate of switch ML via a low impedance path.
  • the extraction circuit 32 can bring the voltage Vo2 or Vgs closer to the source voltage of the switch ML (the voltage at the terminal t6), thereby preventing erroneous firing of the switch ML.
  • the voltage Vgs is greater than the voltage Vo2
  • the resistance values of the resistors R4 and R11 must be reduced, which increases the bias power.
  • FIG. 8 is a circuit diagram showing an example of a drive circuit 3 according to embodiment 3.
  • the drive circuit 3 differs from the drive circuit 2 according to the second embodiment in that it includes a full-wave rectifier circuit 23 instead of the full-wave rectifier circuit 22, and a pull-out circuit 33 instead of the pull-out circuit 32.
  • the rest of the configuration is the same as that of the second embodiment, and therefore a description thereof will be omitted.
  • Full-wave rectifier circuit 23 differs from full-wave rectifier circuit 22 according to embodiment 2 in that it has resistor R1 instead of resistor R4. Other points are the same as those in embodiment 2, so a description is omitted. Resistor R4 is connected in parallel with diode D1.
  • Pull-out circuit 33 differs from pull-out circuit 32 in embodiment 2 in that it includes switch Q10, diodes D7, D8, and resistors R16 and R17 instead of switch Q8, diodes D5, D6, and resistors R11 and R13. Other points are the same as those in embodiment 2, so a description thereof will be omitted.
  • Resistor R12 is an example of a first circuit that generates a voltage difference between the output voltage of full-wave rectifier circuit 23 and the gate-source voltage of the FET.
  • Resistors R14, R15, and R17, and switches Q9 and Q10 are an example of a second circuit that brings the output voltage of full-wave rectifier circuit 23 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage at terminal t6: for example, 0 V) based on the output voltage of full-wave rectifier circuit 23, the gate-source voltage of the FET, or the voltage difference between the output voltage of full-wave rectifier circuit 23 and the gate-source voltage of the FET.
  • Diodes D7 and D8, and resistor R16 are an example of a fourth circuit.
  • the threshold voltage set for the fourth circuit is Vth3 (e.g., 0V or higher)
  • the source voltage of the FET is Vs
  • the value obtained by subtracting Vs from the lower of the voltages at one terminal and the other terminal of the secondary winding of the pulse transformer T1 is VT2'
  • the fourth circuit causes the second circuit to bring Vo2 closer to Vs when VT2'>Vth3 (in other words, when VT2' exceeds Vth3).
  • bringing the output voltage of the full-wave rectifier circuit 23 closer to the source voltage of the FET means connecting the two output terminals of the full-wave rectifier circuit 23 with a switch, and connecting the source of the FET and both output terminals of the full-wave rectifier circuit 23 with low impedance.
  • resistors R14, R15, and R17 and switches Q9 and Q10 bring the output voltage of full-wave rectifier circuit 23 or the gate-source voltage of the FET closer to the source voltage of the FET based on the voltage difference between the output voltage of full-wave rectifier circuit 23 and the gate-source voltage of the FET.
  • resistors R14, R15, and R17 and switches Q9 and Q10 bring the output voltage of full-wave rectifier circuit 23 or the gate-source voltage of the FET closer to the source voltage of the FET.
  • the switch Q10 is, for example, an NPN transistor.
  • the base of the switch Q10 is connected to one end of the resistor R16, the anode of the diode D7, and the anode of the diode D8.
  • the collector of the switch Q10 is connected to one end of the resistor R17.
  • the emitter of the switch Q10 is connected to the terminal t6.
  • the anode of diode D7 is connected to the anode of diode D8, the base of switch Q10, and one end of resistor R16.
  • the cathode of diode D7 is connected to the anode of diode D1, the cathode of diode D2, the other end of resistor R16, and terminal t3.
  • the anode of diode D8 is connected to the anode of diode D7, the base of switch Q10, and one end of resistor R16.
  • the cathode of diode D8 is connected to the anode of diode D3, the cathode of diode D4, and terminal t4.
  • Resistor R16 is connected in parallel with diode D7.
  • resistor R17 is connected to the collector of switch Q10, and the other end is connected to one end of resistor R12, one end of resistor R14, the base of switch Q9, the cathode of diode D1, and the cathode of diode D3.
  • drive circuit 3 can also achieve a duty ratio greater than 50%.
  • the operation of the drive circuit 3 for the switch ML when the switch ML is turned off is basically the same as that of the drive circuit 2, so a description thereof will be omitted.
  • the bridge circuit is pulled up to the high side. Also, when the voltage VT2 is Vcc and the switch ML is on, a current flows through the diode D4, so that the base of the switch Q10 is at a low level and the switch Q10 is in an off state.
  • the extraction circuit 33 can bring the voltage Vo2 or Vgs closer to the source voltage of the switch ML (the voltage at the terminal t6), thereby preventing erroneous firing of the switch ML.
  • the voltage Vgs is greater than the voltage Vo2
  • the resistance values of the resistors R1 and R16 need to be reduced, which increases the bias power.
  • FIG. 9 is a circuit diagram showing an example of a drive circuit 4 according to embodiment 4.
  • the full-wave rectifier circuit 24 is connected to the secondary winding L2 of the pulse transformer T1.
  • the full-wave rectifier circuit 24 includes two diodes D1 and D2 connected in series to form a full-bridge circuit, and two diodes D3 and D4 connected in series to form the full-bridge circuit.
  • the node between the two diodes D1 and D2 is connected to a terminal t3 at one end of the secondary winding L2 of the pulse transformer T1.
  • the node between the two diodes D3 and D4 is connected to a terminal t4 at the other end of the secondary winding L2 of the pulse transformer T1.
  • the anode of diode D1 is connected to the cathode of diode D2 and terminal t3.
  • the cathode of diode D1 is connected to the cathode of diode D3 and the extraction circuit 34.
  • the anode of diode D2 is connected to terminal t6.
  • the cathode of diode D2 is connected to the anode of diode D1 and terminal t3.
  • the anode of diode D3 is connected to the cathode of diode D4 and terminal t4.
  • the cathode of diode D3 is connected to the cathode of diode D1 and the extraction circuit 34.
  • the anode of diode D4 is connected to terminal t6.
  • the cathode of diode D4 is connected to the anode of diode D3 and terminal t4.
  • the full-wave rectifier circuit 24 performs full-wave rectification on the voltage generated in the secondary winding L2 and outputs the result to the gate of the FET.
  • a voltage Vo2 is shown as the output voltage of the full-wave rectifier circuit 24.
  • the secondary winding L2 voltages of different polarities are generated in the state B where a high signal is input to the terminal t1 and a low signal is input to the terminal t2, and in the state D where a low signal is input to the terminal t1 and a high signal is input to the terminal t2.
  • the full-wave rectifier circuit 24 since the full-wave rectifier circuit 24 is connected to the secondary winding L2, the full-wave rectifier circuit 24 can output the voltage Vo2 corresponding to the absolute value of the voltage generated in the secondary winding L2, regardless of the polarity of the voltage generated in the secondary winding L2 (in other words, regardless of the state B or D). Therefore, the drive circuit 4 can apply a voltage Vgs corresponding to the voltage Vo2 to the FET connected between the terminals t5 and t6.
  • the extraction circuit 34 is a circuit that extracts current from the gate of the FET when the FET is turned off. The operation of the extraction circuit 34 will be described in detail later.
  • the extraction circuit 34 includes, for example, resistors R18, R19, R20, R21, and R22, switches Q11 and Q12, a diode D9, and a capacitor C1.
  • the resistor R18 and the diode D9 are an example of a first circuit that generates a voltage difference between the output voltage of the full-wave rectifier circuit 24 and the gate-source voltage of the FET.
  • the resistors R19, R20, R21, and R22, switches Q11 and Q12, and the capacitor C1 are an example of a second circuit that brings the output voltage of the full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage at the terminal t6: for example, 0 V) based on the output voltage of the full-wave rectifier circuit 24, the gate-source voltage of the FET, or the voltage difference between the output voltage of the full-wave rectifier circuit 24 and the gate-source voltage of the FET.
  • bringing the output voltage of the full-wave rectifier circuit 24 closer to the source voltage of the FET means connecting the two output terminals of the full-wave rectifier circuit 24 with a switch to conduct electricity, and connecting the source of the FET and both output terminals of the full-wave rectifier circuit 24 with low impedance.
  • resistors R19, R20, R21, and R22, switches Q11 and Q12, and capacitor C1 bring the output voltage of the full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET based on the output voltage of the full-wave rectifier circuit 24 or the gate-source voltage of the FET.
  • resistors R19, R20, R21, and R22, switches Q11 and Q12, and capacitor C1 bring the gate-source voltage of the FET closer to the source voltage of the FET.
  • the predetermined value is not particularly limited as long as it is a value that can determine whether the output voltage of the full-wave rectifier circuit 24 and the gate-source voltage of the FET are at a high level or a low level.
  • resistor R18 is connected to one end of resistor R19, the cathode of diode D1, and the cathode of diode D3, and the other end is connected to the anode of diode D9.
  • resistor R19 is connected to one end of resistor R18, the cathode of diode D1, and the cathode of diode D3, and the other end is connected to one end of resistor R20 and the base of switch Q11.
  • resistor R20 One end of resistor R20 is connected to the other end of resistor R19 and the base of switch Q11, and the other end is connected to terminal t6.
  • resistor R21 One end of resistor R21 is connected to one end of resistor R22, the cathode of diode D9, and terminal t5, and the other end is connected to the collector of switch Q11, the base of switch Q12, and one end of capacitor C1.
  • capacitor C1 is connected to the other end of resistor R21, the collector of switch Q11, and the base of switch Q12, and the other end is connected to terminal t6.
  • the anode of diode D9 is connected to the other end of resistor R18.
  • the cathode of diode D9 is connected to one end of resistor R21, one end of resistor R22, and terminal t5.
  • the switch Q11 is, for example, an NPN transistor.
  • the base of the switch Q11 is connected to the other end of the resistor R19 and one end of the resistor R20.
  • the collector of the switch Q11 is connected to the other end of the resistor R21, one end of the capacitor C1, and the base of the switch Q12.
  • the emitter of the switch Q11 is connected to the terminal t6.
  • the switch Q12 is, for example, an NPN transistor.
  • the base of the switch Q12 is connected to the other end of the resistor R21, one end of the capacitor C1, and the collector of the switch Q11.
  • the collector of the switch Q12 is connected to the other end of the resistor R22.
  • the emitter of the switch Q12 is connected to the terminal t6.
  • drive circuit 4 can also achieve a duty ratio greater than 50%.
  • switch Q11 When switch Q11 turns off due to a drop in voltage Vo2, switch Q12 turns on and current Idg is drawn out at high speed via a low impedance path, preventing erroneous firing of switch ML.
  • erroneous firing of switch ML can be prevented by maintaining the base-emitter voltage of switch Q12 at a constant level or higher using capacitor C1.
  • switch ML when switch ML is turned off due to a change in voltage VT2 from Vcc to 0V, erroneous firing of switch ML can be prevented in the same way as when switch ML is turned off due to a change in voltage VT2 from -Vcc to 0V.
  • the extraction circuit 34 can bring the voltage Vo2 or Vgs closer to the source voltage of the switch ML (the voltage at the terminal t6), thereby preventing erroneous firing of the switch ML.
  • the voltage Vo2 is smaller than a predetermined value and the voltage Vgs is larger than a predetermined value, that is, when the absolute value of the voltage generated in the secondary winding L2 becomes small and the switch ML is turned off, erroneous firing of the switch ML can be prevented.
  • the resistance values of the resistors R19 and R20 need to be reduced, which increases the bias power.
  • FIG. 10 is a circuit diagram showing an example of a drive circuit 5 according to embodiment 5.
  • Drive circuit 5 differs from drive circuit 4 according to embodiment 4 in that it includes extraction circuit 35 instead of extraction circuit 34. Other points are the same as those in embodiment 4, so a description thereof will be omitted.
  • the extraction circuit 35 is a circuit that extracts current from the gate of the FET when the FET is turned off. The operation of the extraction circuit 35 will be described in detail later.
  • the extraction circuit 35 includes, for example, resistors R23, R24, R25, and R26, a switch Q13, and a diode D10.
  • the resistor R23 and the diode D10 are an example of a first circuit that generates a voltage difference between the output voltage of the full-wave rectifier circuit 24 and the gate-source voltage of the FET.
  • the resistors R24, R25, and R26 and the switch Q13 are an example of a second circuit that brings the output voltage of the full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage at the terminal t6: for example, 0 V) based on the output voltage of the full-wave rectifier circuit 24, the gate-source voltage of the FET, or the voltage difference between the output voltage of the full-wave rectifier circuit 24 and the gate-source voltage of the FET.
  • resistors R24, R25, and R26 and switch Q13 bring the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET based on the voltage difference between the output voltage of full-wave rectifier circuit 24 and the gate-source voltage of the FET.
  • resistors R24, R25, and R26 and switch Q13 bring the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET.
  • resistor R23 One end of resistor R23 is connected to one end of resistor R24, the cathode of diode D1, and the cathode of diode D3, and the other end is connected to the anode of diode D10.
  • resistor R24 is connected to one end of resistor R23, the cathode of diode D1, and the cathode of diode D3, and the other end is connected to one end of resistor R25 and the base of switch Q13.
  • resistor R25 One end of resistor R25 is connected to the other end of resistor R24 and the base of switch Q13, and the other end is connected to terminal t6.
  • resistor R26 One end of resistor R26 is connected to the collector of switch Q13, and the other end is connected to terminal t6.
  • the anode of diode D10 is connected to the other end of resistor R23.
  • the cathode of diode D10 is connected to the emitter of switch Q13 and terminal t5.
  • the switch Q13 is, for example, a PNP transistor.
  • the base of the switch Q13 is connected to the other end of the resistor R24 and one end of the resistor R25.
  • the collector of the switch Q13 is connected to one end of the resistor R26.
  • the emitter of the switch Q13 is connected to the cathode of the diode D10 and the terminal t5.
  • drive circuit 5 can also achieve a duty ratio greater than 50%.
  • switch Q13 When switch Q13 turns on due to a drop in voltage Vo2, current Idg is drawn out at high speed via a low impedance path, preventing erroneous firing of switch ML. Note that when switch ML is turned off due to a change in voltage VT2 from Vcc to 0V, erroneous firing of switch ML can also be prevented, just as when switch ML is turned off due to a change in voltage VT2 from -Vcc to 0V.
  • the extraction circuit 35 can bring the voltage Vo2 or Vgs closer to the source voltage of the switch ML (the voltage at the terminal t6), thereby preventing erroneous firing of the switch ML.
  • the voltage Vgs is greater than the voltage Vo2
  • the resistance values of the resistors R24 and R25 must be small, which increases the bias power.
  • the resistance value of the resistor R24 must be set to a value that prevents the switch Q13 from turning on when the voltage Vgs is High.
  • FIG. 11 is a circuit diagram showing an example of a drive circuit 6 according to embodiment 6.
  • Drive circuit 6 differs from drive circuit 4 according to embodiment 4 in that it has extraction circuit 36 instead of extraction circuit 34. Other points are the same as those in embodiment 4, so a description will be omitted.
  • the extraction circuit 36 differs from the extraction circuit 31 of the first embodiment in that it further includes a resistor R27, a capacitor C2, and a diode D11. The rest of the circuit is the same as in the first embodiment, so a description thereof will be omitted.
  • Resistor R5 and diode D11 are an example of a first circuit that generates a voltage difference between the output voltage of full-wave rectifier circuit 24 and the gate-source voltage of the FET.
  • Resistors R6, R7, R8, R9, and R27, capacitor C2, and switches Q5, Q6, and Q7 are an example of a second circuit that brings the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage at terminal t6: for example, 0 V) based on the output voltage of full-wave rectifier circuit 24, the gate-source voltage of the FET, or the voltage difference between the output voltage of full-wave rectifier circuit 24 and the gate-source voltage of the FET.
  • resistors R6, R7, R8, R9, and R27, capacitor C2, and switches Q5, Q6, and Q7 bring the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET based on the voltage difference between the output voltage of full-wave rectifier circuit 24 and the gate-source voltage of the FET.
  • resistors R6, R7, R8, R9, and R27, capacitor C2, and switches Q5, Q6, and Q7 bring the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET.
  • resistor R27 is connected to one end of resistor R5, one end of resistor R6, the base of switch Q5, the cathode of diode D1, and the cathode of diode D3, and the other end is connected to terminal t6.
  • capacitor C2 is connected to the other end of resistor R8, one end of resistor R9, the base of switch Q6, and the base of switch Q7, and the other end is connected to terminal t6.
  • the anode of diode D11 is connected to the other end of resistor R5.
  • the cathode of diode D11 is connected to the emitter of switch Q5, one end of resistor R7, and terminal t5.
  • the drive circuit 6 can also achieve a duty ratio greater than 50%.
  • switch Q5 When switch Q5 turns on due to a drop in voltage Vo2, switches Q6 and Q7 turn on, current Idg is drawn out at high speed through a low impedance path, and voltage Vo2 drops at high speed. This makes it possible to prevent erroneous firing of switch ML. Note that when switch ML is turned off due to a change in voltage VT2 from Vcc to 0V, erroneous firing of switch ML can also be prevented, just as when switch ML is turned off due to a change in voltage VT2 from -Vcc to 0V.
  • the pull-out circuit 36 can prevent erroneous firing of the switch ML in the same way as in the first to fifth embodiments. Note that in order to speed up the turn-on of the switch Q5, the resistance value of the resistor R27 must be reduced, which increases the bias power.
  • the first circuit in embodiments 1 to 6 may be configured with a resistor as in embodiments 1 to 3, may be configured with a series circuit of a resistor and a diode as in embodiments 4 to 6, or may be configured with a diode.
  • the first circuit is a circuit made up of a resistor, a diode, or a series circuit of a resistor and a diode.
  • a capacitor may be provided between the base and emitter of switch Q7 in embodiment 1.
  • the capacitor C1 does not need to be provided between the base and emitter of the switch Q12 in embodiment 4.
  • the capacitor C2 does not need to be provided between the base and emitter of the switch Q7 in embodiment 6.
  • the resistors R6, R7, R8, and R9 and the switches Q5, Q6, and Q7 in the first embodiment may be replaced with the resistors R19, R20, R21, and R22 and the switches Q11 and Q12 in the fourth embodiment, and further, a capacitor C1 may be provided.
  • the switch Q9 and resistors R14 and R15 in the second and third embodiments may be replaced with the resistors R19, R20, R21, and R22 and switches Q11 and Q12 in the fourth embodiment, and further, a capacitor C1 may be provided.
  • the present disclosure can be realized not only as a drive circuit, but also as a method for operating a drive circuit.
  • FIG. 12 is a flowchart showing an example of an operation method according to another embodiment.
  • the operating method of a drive circuit for driving a transistor having a first terminal which is a gate or base, a second terminal which is a source or emitter, and a third terminal which is a drain or collector includes the steps of inputting signals having a phase difference to one end terminal and the other end terminal of a primary winding of an isolated pulse transformer (step S11), full-wave rectifying the signal output from the secondary winding of the pulse transformer (step S12), outputting the full-wave rectified signal to the first terminal (step S13), and drawing current from the first terminal when the transistor turns off (step S14).
  • the present disclosure can be realized as a program for causing a computer (processor) to execute the steps included in the operating method.
  • the present disclosure can be realized as a non-transitory computer-readable recording medium, such as a CD-ROM, on which the program is recorded.
  • each step is performed by running the program using hardware resources such as a computer's CPU, memory, and input/output circuits.
  • hardware resources such as a computer's CPU, memory, and input/output circuits.
  • each step is performed by the CPU obtaining data from memory or input/output circuits, etc., performing calculations, and outputting the results of the calculations to memory or input/output circuits, etc.
  • each component included in the drive circuit may be configured with dedicated hardware, or may be realized by executing a software program suitable for each component.
  • Each component may be realized by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.
  • LSI is an integrated circuit. These may be individually integrated into a single chip, or may be integrated into a single chip that includes some or all of the functions. Furthermore, the integrated circuit is not limited to an LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after the LSI is manufactured, or a reconfigurable processor that can reconfigure the connections and settings of the circuit cells inside the LSI may also be used.
  • FPGA Field Programmable Gate Array
  • this disclosure also includes forms obtained by applying various modifications to the embodiments that a person skilled in the art may conceive, and forms realized by arbitrarily combining the components and functions of each embodiment within the scope that does not deviate from the spirit of this disclosure.
  • the full-wave rectifier circuit and the extraction circuit can prevent false ignition of the main bridge circuit.
  • the primary winding can be in state A where a high signal is input to one terminal and a high signal is input to the other terminal, state B where a high signal is input to one terminal and a low signal is input to the other terminal, state C where a low signal is input to one terminal and a low signal is input to the other terminal, and state D where a low signal is input to one terminal and a high signal is input to the other terminal.
  • states B and D voltages of different polarities are generated in the secondary winding, but because a full-wave rectifier circuit is connected to the secondary winding, the drive circuit can apply a voltage to the transistor regardless of the polarity of the voltage generated in the secondary winding (in other words, in either state B or D).
  • a voltage can be applied to a transistor only in states B and D among states A, B, C, and D, a maximum duty ratio of only 50% can be realized.
  • a voltage can be applied to a transistor in both states B and D among states A, B, C, and D, various duty ratios can be realized. Therefore, a duty ratio greater than 50% can be realized.
  • an extraction circuit is provided to extract current from the gate of the transistor when the transistor is turned off, preventing erroneous turning on of the transistor and enabling high-speed turn-off and turn-on.
  • the extraction circuit includes a first circuit that generates a voltage difference between the output voltage of the full-wave rectifier circuit and the terminal-to-terminal voltage between the first terminal and the second terminal, and a second circuit that brings the output voltage or the terminal-to-terminal voltage of the full-wave rectifier circuit closer to the voltage of the second terminal based on the output voltage, the terminal-to-terminal voltage, or the voltage difference of the full-wave rectifier circuit.
  • the extraction circuit can bring the output voltage of the full-wave rectifier circuit or the voltage between the terminals closer to the voltage at the second terminal of the transistor, thereby preventing false firing of the transistor.
  • the extraction circuit further includes a third circuit, and when Vo2 is the output voltage of the full-wave rectifier circuit, Vth2 is the threshold voltage set for the third circuit, Vs is the voltage of the second terminal, and VT2 is the higher of the voltages at one terminal and the other terminal of the secondary winding of the pulse transformer minus Vs, the third circuit causes the second circuit to bring Vo2 closer to Vs when Vo2-VT2>Vth2.
  • the operation of the extraction circuit can be started according to the voltage at the terminals on both ends of the secondary winding of the pulse transformer.
  • the extraction circuit further includes a fourth circuit, and when VT2'>Vth3, the output voltage of the full-wave rectifier circuit is Vo2, the threshold voltage set for the fourth circuit is Vth3, the voltage of the second terminal is Vs, and the value obtained by subtracting Vs from the lower of the voltages of the terminal at one end and the terminal at the other end of the secondary winding of the pulse transformer, the fourth circuit causes the second circuit to bring Vo2 closer to Vs, when VT2'>Vth3, the drive circuit described in Technology 2.
  • the operation of the extraction circuit can be started according to the voltage at the terminals on both ends of the secondary winding of the pulse transformer.
  • the first circuit can be realized.
  • the full-wave rectifier circuit may include two switches.
  • the two switches are turned on when the transistor is turned off, so that the output voltage of the full-wave rectifier circuit can be brought closer to the voltage at the second terminal of the transistor, and false firing of the transistor can be reliably prevented.
  • This disclosure can be applied to drive circuits for driving transistors such as MOSFETs, GaN FETs, or IGBTs.

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PCT/JP2024/014814 2023-07-25 2024-04-12 駆動回路および動作方法 Pending WO2025022733A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4634903A (en) * 1984-02-20 1987-01-06 Honeywell Information Systems Italia Power FET driving circuit
US8283896B1 (en) * 2009-06-03 2012-10-09 Polarity, Inc. Method and system for charging and discharging high-voltage energy storage devices
US20150333749A1 (en) * 2014-05-15 2015-11-19 Fronius International Gmbh Circuit arrangement and method for controlling semiconductor switching element
JP2016144258A (ja) * 2015-01-30 2016-08-08 株式会社京三製作所 高周波絶縁ゲートドライバ回路、及びゲート回路駆動方法
JP2018502542A (ja) * 2014-11-06 2018-01-25 アイディール パワー インコーポレイテッド ダブルベースバイポーラジャンクショントランジスタの最適化された動作を有する回路、方法、及びシステム、並びに、可変電圧自己同期整流器回路、方法、及びシステム、並びに、ダブルベースコンタクト双方向バイポーラジャンクショントランジスタ回路による動作ポイント最適化、方法、及びシステム。

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4634903A (en) * 1984-02-20 1987-01-06 Honeywell Information Systems Italia Power FET driving circuit
US8283896B1 (en) * 2009-06-03 2012-10-09 Polarity, Inc. Method and system for charging and discharging high-voltage energy storage devices
US20150333749A1 (en) * 2014-05-15 2015-11-19 Fronius International Gmbh Circuit arrangement and method for controlling semiconductor switching element
JP2018502542A (ja) * 2014-11-06 2018-01-25 アイディール パワー インコーポレイテッド ダブルベースバイポーラジャンクショントランジスタの最適化された動作を有する回路、方法、及びシステム、並びに、可変電圧自己同期整流器回路、方法、及びシステム、並びに、ダブルベースコンタクト双方向バイポーラジャンクショントランジスタ回路による動作ポイント最適化、方法、及びシステム。
JP2016144258A (ja) * 2015-01-30 2016-08-08 株式会社京三製作所 高周波絶縁ゲートドライバ回路、及びゲート回路駆動方法

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