WO2025018290A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2025018290A1
WO2025018290A1 PCT/JP2024/025243 JP2024025243W WO2025018290A1 WO 2025018290 A1 WO2025018290 A1 WO 2025018290A1 JP 2024025243 W JP2024025243 W JP 2024025243W WO 2025018290 A1 WO2025018290 A1 WO 2025018290A1
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Prior art keywords
region
contact
semiconductor substrate
contact portion
insulating film
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Pending
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PCT/JP2024/025243
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English (en)
French (fr)
Japanese (ja)
Inventor
源宜 窪内
崇一 吉田
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to JP2025534028A priority Critical patent/JPWO2025018290A1/ja
Publication of WO2025018290A1 publication Critical patent/WO2025018290A1/ja
Priority to US19/245,370 priority patent/US20250318253A1/en
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/161—IGBT having built-in components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/411—PN diodes having planar bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/415—Insulated-gate bipolar transistors [IGBT] having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/417—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/418—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/232—Emitter electrodes for IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/035—Etching a recess in the emitter region 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/20—Breakdown diodes, e.g. avalanche diodes
    • H10D8/25—Zener diodes 

Definitions

  • the present invention relates to a semiconductor device.
  • Patent Document 1 U.S. Patent Application Publication No. 2019/0172770
  • a semiconductor device in a first aspect of the present invention, includes an active portion and a temperature-sensing portion, the semiconductor device including a semiconductor substrate of a first conductivity type and an interlayer insulating film provided above the front surface of the semiconductor substrate, the active portion includes an active trench portion provided on the front surface of the semiconductor substrate and an active contact portion provided in the interlayer insulating film, the temperature-sensing portion includes a temperature-sensing diode provided above or on the front surface side of the semiconductor substrate and a temperature-sensing contact portion provided in the interlayer insulating film above the temperature-sensing diode, and the contact width of the temperature-sensing contact portion is greater than the contact width of the active contact portion.
  • the temperature-sensitive contact width where the temperature-sensitive contact portion contacts the temperature-sensitive diode may be larger than a first active contact width where the active contact portion contacts the upper surface of the mesa portion of the semiconductor substrate.
  • the temperature-sensitive contact width where the temperature-sensitive contact portion contacts the temperature-sensitive diode may be larger than the second active contact width where the active contact portion contacts the active trench portion.
  • the sidewall of the temperature-sensitive contact portion may be in contact with the interlayer insulating film from the top to the bottom.
  • the temperature sensing portion may have a recessed region in the upper surface of the semiconductor substrate.
  • the temperature sensing diode may be provided in the recessed region.
  • the height position of the upper surface of the interlayer insulating film in the active portion may be the same as the height position of the upper surface of the interlayer insulating film in the recess region.
  • the temperature sensing portion may have a housing portion provided below the temperature sensing contact portion.
  • a bottom corner of the temperature sensing contact portion may contact the temperature sensing diode.
  • the bottom surface of the temperature sensing contact portion may contact the housing portion.
  • the side of the temperature sensing diode may be in contact with the side of the housing portion.
  • the interlayer insulating film may include a first interlayer insulating film provided above the temperature-sensitive diode, and a second interlayer insulating film provided between the temperature-sensitive diode and the semiconductor substrate in the depth direction of the semiconductor substrate.
  • the upper surface of the second interlayer insulating film may be in contact with the lower surface of the temperature sensing diode and the lower surface of the housing portion.
  • the housing portion may be a region of the first interlayer insulating film that is provided below the temperature-sensitive contact portion.
  • the housing portion may be the second interlayer insulating film provided above the semiconductor substrate.
  • the housing portion may have a polycrystalline semiconductor of a different conductivity type than the contact region of the temperature sensing diode.
  • the housing portion may have a polycrystalline semiconductor having the same conductivity type as the contact region of the temperature sensing diode and a lower doping concentration than the contact region.
  • the bottom surface of the temperature-sensitive contact portion may be in contact with the temperature-sensitive diode and the housing portion.
  • the temperature-sensitive contact portion may have a barrier metal film provided at the bottom corner of the temperature-sensitive contact portion, and a plug portion provided in contact with the inside of the barrier metal film.
  • the temperature-sensing diode may contact the bottom surface of the temperature-sensing contact portion from the bottom corner to an area of 10% or more and 40% or less of the bottom surface of the temperature-sensing contact portion.
  • the sidewall of the temperature-sensitive contact portion may be in contact with the temperature-sensitive diode and the first interlayer insulating film.
  • the temperature-sensitive diode may be in contact with the sidewall of the temperature-sensitive contact portion from the bottom corner to an area of 10% or more and 90% or less of the sidewall of the temperature-sensitive contact portion.
  • the temperature sensing portion may have a temperature sensing trench contact portion extending from the upper surface of the interlayer insulating film downward in the depth direction of the semiconductor substrate below the upper surface of the temperature sensing diode.
  • the active portion may have an active trench contact portion extending from the upper surface of the interlayer insulating film downward in the depth direction of the semiconductor substrate below the front surface of the semiconductor substrate.
  • a semiconductor device in a second aspect of the present invention, includes an active section having a plurality of active trench contact sections provided on the front surface of a semiconductor substrate of a first conductivity type, and a temperature-sensing section provided above the semiconductor substrate or on the front surface side of the semiconductor substrate, the temperature-sensing section having a temperature-sensing diode provided above the semiconductor substrate, an interlayer insulating film provided above the temperature-sensing diode, and a temperature-sensing trench contact section provided extending from the upper surface of the interlayer insulating film below the upper surface of the temperature-sensing diode in the depth direction of the semiconductor substrate, and the extension depth of the temperature-sensing trench contact section extending from the upper surface of the temperature-sensing diode in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of active trench contact sections extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.
  • a semiconductor device in a third aspect of the present invention, includes a main region and a peripheral region, the semiconductor substrate having a first conductivity type and an interlayer insulating film provided above the front surface of the semiconductor substrate, the main region has a main region contact portion provided in the interlayer insulating film, the peripheral region has a polycrystalline portion provided above or on the front surface side of the semiconductor substrate, and a first peripheral region contact portion provided in the interlayer insulating film above the polycrystalline portion, and the contact width of the first peripheral region contact portion is greater than the contact width of the main region contact portion.
  • the sidewall of the first outer peripheral region contact portion may be in contact with the interlayer insulating film from the top to the bottom.
  • the peripheral region may have a recessed region in which a depression is provided in the upper surface of the semiconductor substrate.
  • the polycrystalline portion may be provided in the recessed region.
  • the height position of the upper surface of the interlayer insulating film in the main region may be the same as the height position of the upper surface of the interlayer insulating film in the recess region.
  • the peripheral region may have a housing portion provided below the first peripheral region contact portion.
  • a bottom corner of the first peripheral region contact portion may contact the polycrystalline portion.
  • a bottom surface of the first peripheral region contact portion may contact the housing portion.
  • the side of the polycrystalline portion may be in contact with the side of the housing portion.
  • the housing portion may be a region of the interlayer insulating film that is provided below the first outer peripheral region contact portion.
  • the bottom surface of the first outer peripheral region contact portion may be in contact with the polycrystalline portion and the housing portion.
  • the first peripheral region contact portion may have a barrier metal film provided at the bottom corner of the first peripheral region contact portion, and a plug portion provided in contact with the inside of the barrier metal film.
  • the polycrystalline portion may contact the bottom surface of the first peripheral region contact portion from the bottom surface corner to an area that is 10% or more and 40% or less of the bottom surface of the first peripheral region contact portion.
  • the sidewall of the first peripheral region contact portion may be in contact with the polycrystalline portion and the interlayer insulating film.
  • the polycrystalline portion may be in contact with the sidewall of the peripheral region contact portion from the bottom corner portion to an area of 10% or more and 90% or less of the sidewall of the first peripheral region contact portion.
  • the peripheral region may have a first peripheral region trench contact portion extending from the upper surface of the interlayer insulating film downward beyond the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate.
  • the main region may have a main region trench contact portion extending from the upper surface of the interlayer insulating film downward below the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.
  • any of the above semiconductor devices may include a gate trench portion provided on the front surface of the semiconductor substrate and having a gate conductive portion, and a gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion.
  • the polycrystalline portion may be connected to the gate metal layer via the first peripheral region contact portion, and may be connected to the gate conductive portion.
  • any of the above semiconductor devices may include a dummy trench portion provided on the front surface of the semiconductor substrate and having a dummy conductive portion, and an emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate.
  • the polycrystalline portion may be connected to the emitter electrode via the first outer peripheral region contact portion, and may be connected to the dummy conductive portion.
  • any of the above semiconductor devices may include a guard ring of a second conductivity type provided on the front surface of the semiconductor substrate between the main region and an edge of the semiconductor substrate, and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring.
  • the polycrystalline portion may be connected to the edge metal layer via the first peripheral region contact portion.
  • a semiconductor device having a main region and a peripheral region, the main region having a plurality of main region trench contact portions provided on a front surface of a semiconductor substrate of a first conductivity type, the peripheral region having a polycrystalline portion provided above the semiconductor substrate, an interlayer insulating film provided above the polycrystalline portion, and a peripheral region trench contact portion provided extending from an upper surface of the interlayer insulating film below an upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate, and the peripheral region trench contact portion extends from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate to a depth that is shallower than the extension depth of the plurality of main region trench contact portions extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.
  • the peripheral region may have a recessed region in which a depression is provided in the upper surface of the semiconductor substrate.
  • the polycrystalline portion may be provided in the recessed region.
  • the contact width where the peripheral region trench contact portion contacts the polycrystalline portion may be greater than the contact width of each of the multiple main region trench contact portions.
  • the contact width where the peripheral region trench contact portion contacts the polycrystalline portion may be smaller than the contact width of each of the multiple main region trench contact portions.
  • any of the above semiconductor devices may include a gate trench portion provided on the front surface of the semiconductor substrate and having a gate conductive portion, and a gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion.
  • the polycrystalline portion may be connected to the gate metal layer via the peripheral region trench contact portion, and may be connected to the gate conductive portion.
  • any of the above semiconductor devices may include a dummy trench portion provided on the front surface of the semiconductor substrate and having a dummy conductive portion, and an emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate.
  • the polycrystalline portion may be connected to the emitter electrode via the peripheral region trench contact portion and to the dummy conductive portion.
  • any of the above semiconductor devices may include a guard ring of a second conductivity type provided on the front surface of the semiconductor substrate between the main region and an edge of the semiconductor substrate, and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring.
  • the polycrystalline portion may be connected to the edge metal layer via the peripheral region trench contact portion.
  • the peripheral region may have a second peripheral region trench contact portion that extends from the upper surface of the interlayer insulating film below the upper surface of the semiconductor substrate in the depth direction of the semiconductor substrate in a region where the polycrystalline portion is not provided.
  • the extension depth of the first peripheral region trench contact portion from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate may be shallower than the extension depth of the second peripheral region trench contact portion from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.
  • the peripheral region may have a second peripheral region trench contact portion extending from the upper surface of the interlayer insulating film downward below the upper surface of the semiconductor substrate in the depth direction of the semiconductor substrate in a region where the polycrystalline portion is not provided.
  • the extension depth of the first peripheral region trench contact portion extending from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate and the extension depth of the second peripheral region trench contact portion extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate may be shallower than the extension depth of the multiple main region trench contact portions extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.
  • a semiconductor device having a main region and a pad region, the main region having a plurality of main region trench contact portions provided on a front surface of a semiconductor substrate of a first conductivity type, the pad region having a pad for connecting to an external circuit, a polycrystalline portion provided above the semiconductor substrate, an interlayer insulating film provided above the polycrystalline portion, and a pad region trench contact portion provided extending from an upper surface of the interlayer insulating film below an upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate, and the pad region trench contact portion extends from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate to a depth shallower than the extension depth of the plurality of main region trench contact portions from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.
  • FIG. 1 shows an example of an enlarged view of the top surface of the semiconductor device 100.
  • 1A shows an example of a cross section taken along line aa' in FIG. 1A.
  • 1 shows an enlarged view of the top surface of a modified example of the semiconductor device 100.
  • FIG. 2B shows an example of a cross section taken along line bb' in FIG. 2A.
  • 1 shows an example of a top view of a semiconductor device 100.
  • FIG. 1 shows an example of a cross section of a semiconductor device 100 including a temperature sensing portion 180.
  • 13 shows another example of a cross section of the semiconductor device 100 including the temperature sensing portion 180.
  • 1 shows a cross section of a modified example of the semiconductor device 100 including a temperature sensitive portion 180.
  • FIG. 1 shows a cross section of a modified example of the semiconductor device 100 including a temperature sensitive portion 180. 1 shows a cross section of a modified example of the semiconductor device 100 including a temperature sensitive portion 180. 1 shows an example of an enlarged view of a cross section of a semiconductor device 100.
  • FIG. 1 shows an enlarged cross-sectional view of a modified example of the semiconductor device 100.
  • FIG. 1 shows an enlarged cross-sectional view of a modified example of the semiconductor device 100.
  • FIG. 1 shows an enlarged cross-sectional view of a modified example of the semiconductor device 100.
  • FIG. 1 shows an enlarged cross-sectional view of a modified example of the semiconductor device 100.
  • FIG. 1 shows an enlarged cross-sectional view of a modified example of the semiconductor device 100.
  • FIG. 1 shows an enlarged cross-sectional view of a modified example of the semiconductor device 100.
  • FIG. 1 shows an enlarged cross-sectional view of a modified example of the semiconductor device 100.
  • FIG. 1 shows an
  • FIG. 1 shows a cross section of a modified example of the semiconductor device 100 including a temperature sensitive portion 180.
  • 1 shows a cross section of a modified example of the semiconductor device 100 including a temperature sensitive portion 180.
  • 1 shows a cross section of a modified example of the semiconductor device 100 including a temperature sensitive portion 180.
  • 1 shows an example of an enlarged view of the top surface of the semiconductor device 100.
  • An example of the cross section taken along line dd' in FIG. 9 is shown.
  • An example of the cross section taken along line dd' in FIG. 9 is shown.
  • An example of the cross section taken along line dd' in FIG. 9 is shown.
  • An example of the cross section taken along line dd' in FIG. 9 is shown.
  • An example of the cross section taken along line dd' in FIG. 9 is shown.
  • An example of the cross section taken along line dd' in FIG. 9 is shown.
  • An example of an enlarged view of the dd' cross section in FIG. 9 is shown.
  • An example of the cross section taken along line dd' in FIG. 9 is shown.
  • An example of an enlarged view of the dd' cross section in FIG. 9 is shown.
  • An example of the ee' cross section in FIG. 9 is shown.
  • An example of the ee' cross section in FIG. 9 is shown.
  • An example of the ee' cross section in FIG. 9 is shown.
  • An example of the ee' cross section in FIG. 9 is shown.
  • An example of the ee' cross section in FIG. 9 is shown.
  • An example of an enlarged view of the ee' cross section in FIG. 9 is shown.
  • An example of the ee' cross section in FIG. 9 is shown.
  • FIG. 1 shows an example of a top view of a semiconductor device 100.
  • FIG. An example of the region R in FIG. 18A is shown.
  • An example of the ff' cross section in FIG. 18B is shown.
  • An example of the ff' cross section in FIG. 18B is shown.
  • An example of the ff' cross section in FIG. 18B is shown.
  • An example of the ff' cross section in FIG. 18B is shown.
  • An example of the ff' cross section in FIG. 18B is shown.
  • An example of the ff' cross section in FIG. 18B is shown.
  • An example of an enlarged view of the ff' cross section in FIG. 18B is shown.
  • An example of an enlarged view of the ff' cross section in FIG. 18B is shown.
  • An example of an enlarged view of the ff' cross section in FIG. 18B is shown.
  • An example of the ff' cross section in FIG. 18B is shown.
  • An example of the ff' cross section in FIG. 18B is shown.
  • An example of an enlarged view of the ff' cross section in FIG. 18B is shown.
  • An example of an enlarged view of the ff' cross section in FIG. 18B is shown.
  • An example of an enlarged view of the ff' cross section in FIG. 18B is shown.
  • An example of the ff' cross section in FIG. 18B is shown.
  • An example of an enlarged view of the ff' cross section in FIG. 18B is shown.
  • FIG. 18B An example of an enlarged view of the ff' cross section in FIG. 18B is shown. An example of the ff' cross section in FIG. 18B is shown. An example of the ff' cross section in FIG. 18B is shown. An example of an enlarged view of the ff' cross section in FIG. 18B is shown. An example of an enlarged view of the ff' cross section in FIG. 18B is shown. 18B shows an example of a cross section taken along line gg' in FIG. 18A. 18B shows an example of a cross section taken along line gg' in FIG. 18A. 18B shows an example of a cross section taken along line gg' in FIG. 18A. 18B shows an example of a cross section taken along line gg' in FIG. 18A. 1 is an example of electrical connections between the various parts of the semiconductor device 100.
  • one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper” and the other side as “lower.”
  • the upper surface is referred to as the upper surface and the other surface is referred to as the lower surface.
  • the directions of "upper” and “lower” are not limited to the direction of gravity or the directions when the semiconductor device is mounted.
  • the orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction.
  • the Z-axis does not limit the height direction relative to the ground.
  • the +Z-axis direction and the -Z-axis direction are opposite directions.
  • the Z-axis direction is described without indicating positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.
  • the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis.
  • the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis.
  • the direction of the Z-axis may be referred to as the depth direction.
  • the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis may be referred to as the horizontal direction.
  • the conductivity type of a doped region doped with impurities is described as P type or N type.
  • impurities may specifically mean either N type donors or P type acceptors, and may be described as dopants.
  • doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor that exhibits N type conductivity or a semiconductor that exhibits P type conductivity.
  • the doping concentration refers to the donor concentration or acceptor concentration in a thermal equilibrium state.
  • the net doping concentration refers to the net concentration obtained by adding together the donor concentration, which is the concentration of positive ions, and the acceptor concentration, which is the concentration of negative ions, including the polarity of the charge.
  • the donor concentration is ND and the acceptor concentration is NA
  • the net doping concentration at any position is ND-NA.
  • the net doping concentration may be simply referred to as the doping concentration.
  • Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves.
  • VOH defects in semiconductors that combine vacancies (V), oxygen (O), and hydrogen (H) Si-i-H defects in semiconductors that combine interstitial silicon (Si-i) and hydrogen
  • CiOi-H defects in semiconductors that combine interstitial carbon (Ci), interstitial oxygen (Oi), and hydrogen function as donors that supply electrons.
  • these VOH defects may be referred to as hydrogen donors.
  • chemical concentration refers to the concentration atomic density of impurities measured regardless of the state of electrical activation.
  • the chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS).
  • the above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV method).
  • the carrier concentration measured by spreading resistance measurement (SR method) may be the net doping concentration.
  • Carriers refer to charge carriers of electrons or holes.
  • the carrier concentration measured by the CV method or SR method may be a value in a thermal equilibrium state.
  • the carrier concentration in that region may be the donor concentration.
  • the carrier concentration in that region may be the acceptor concentration.
  • the doping concentration in an N-type region may be referred to as the donor concentration
  • the doping concentration in a P-type region may be referred to as the acceptor concentration.
  • the peak value may be taken as the concentration of the donor, acceptor or net doping in the region.
  • the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping.
  • the carrier concentration measured by the SR method may be lower than the donor or acceptor concentration.
  • the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state.
  • the decrease in carrier mobility occurs when the carriers are scattered due to a disturbance (disorder) in the crystal structure caused by lattice defects, etc.
  • the reason for the decrease in carrier concentration is as follows.
  • the spreading resistance is measured and the carrier concentration is calculated from the measured value of the spreading resistance.
  • the mobility in the crystalline state is used as the carrier mobility.
  • the carrier concentration is calculated based on the carrier mobility in the crystalline state, even though the carrier mobility is decreased. Therefore, the value is lower than the actual carrier concentration, i.e., the concentration of the donor or acceptor.
  • the donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor.
  • the donor concentration of phosphorus or arsenic, which is a donor in a silicon semiconductor, or the acceptor concentration of boron, which is an acceptor is about 99% of these chemical concentrations.
  • the donor concentration of hydrogen, which is a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.
  • the SI system of units is adopted.
  • the unit of distance or length may be expressed in cm (centimeter). In this case, various calculations may be calculated by converting it to m (meter).
  • the numerical representation of powers of 10 for example, the representation of 1E+16 indicates 1 ⁇ 10 16 , and the representation of 1E-16 indicates 1 ⁇ 10 -16 .
  • FIG. 1A shows an example of an enlarged view of the top surface of a semiconductor device 100.
  • the semiconductor device 100 in this example is a semiconductor chip equipped with a transistor portion 70.
  • the semiconductor device 100 is not limited to a transistor, so long as it is a semiconductor element having a MOS gate structure on a semiconductor substrate 10.
  • the configuration in this figure may be arranged periodically or continuously in the +X-axis direction and the -X-axis direction.
  • the transistor portion 70 is a region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10.
  • the collector region 22 will be described later.
  • the transistor portion 70 includes a transistor such as an IGBT.
  • the transistor portion 70 is an IGBT.
  • the transistor portion 70 may be another type of transistor, such as a MOSFET.
  • an edge termination structure may be provided in the area on the negative side in the Y-axis direction of the semiconductor device 100 in this example.
  • the edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10.
  • the edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure that combines these. Note that in this example, for convenience, the edge on the negative side in the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100.
  • the semiconductor substrate 10 is a substrate formed of a semiconductor material.
  • the semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, another compound semiconductor substrate, or a diamond semiconductor substrate.
  • the semiconductor substrate 10 is a silicon substrate. Note that in this specification, when the term "top view” is used, it means that the semiconductor substrate 10 is viewed from the top side.
  • the semiconductor substrate 10 has a front surface 21 and a back surface 23, as described below.
  • the semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.
  • the emitter electrode 52 and the gate metal layer 50 are an example of a front surface side metal layer.
  • the gate trench portion 40 is an example of a MOS gate structure included in the semiconductor device 100. Note that the semiconductor device 100 of this example is a transistor with a MOS gate structure, but may also be a diode with a MOS gate structure.
  • the emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17.
  • the gate metal layer 50 is provided above the connection portion 25 and the well region 17.
  • the emitter electrode 52 and the gate metal layer 50 are formed of a material containing a metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al) or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al) or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal film made of titanium or a titanium compound under the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
  • the emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with the interlayer insulating film 38 in between.
  • the interlayer insulating film 38 is omitted in FIG. 1A.
  • the interlayer insulating film 38 has contact holes 54, 55, and 56 penetrating therethrough.
  • the contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 via the connection portion 25. Inside the contact hole 55, a barrier metal film made of titanium or a titanium compound and/or a plug portion made of tungsten may be formed.
  • the contact hole 56 connects the emitter electrode 52 to the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a barrier metal film made of titanium or a titanium compound and/or a plug portion made of tungsten may be formed.
  • connection portion 25 is connected to the front surface side metal layer such as the emitter electrode 52 or the gate metal layer 50.
  • the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion.
  • the connection portion 25 in this example may be provided extending in the X-axis direction and electrically connected to the gate conductive portion.
  • the connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion.
  • the connection portion 25 is a conductive material such as polysilicon doped with impurities.
  • the connection portion 25 in this example is polysilicon (N+) doped with N-type impurities.
  • the connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.
  • connection portion 43 is formed in a curved shape.
  • the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.
  • the dummy trench portion 30 is an example of an active trench portion 122 provided on the front surface 21 of the semiconductor substrate 10. That is, the active trench portion 122 may be a trench portion provided in the active portion 120.
  • the dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52.
  • the dummy trench portion 30 is arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example).
  • the dummy trench portion 30 in this example has an I-shape on the front surface 21 of the semiconductor substrate 10, but may have a U-shape on the front surface 21 of the semiconductor substrate 10 like the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions extending along the extension direction and a connection portion connecting the two extension portions.
  • the transistor section 70 in this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are arranged in a repeated manner. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extension sections 41.
  • the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example.
  • the ratio of the gate trench portions 40 may be greater than the ratio of the dummy trench portions 30, and the ratio of the dummy trench portions 30 may be greater than the ratio of the gate trench portions 40.
  • the ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4.
  • the transistor portion 70 may not have dummy trench portions 30, with all trench portions being gate trench portions 40.
  • the well region 17 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10 relative to the drift region 18 described later.
  • the well region 17 is an example of a well region provided on the peripheral side of the active section 120.
  • the well region 17 is a P+ type, for example.
  • the well region 17 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided.
  • the diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30.
  • a portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17.
  • the bottom of the end of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.
  • the contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70.
  • the contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film.
  • the one or more contact holes 54 may be provided extending in the extension direction.
  • Mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to front surface 21 of semiconductor substrate 10.
  • a mesa portion is a portion of semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from front surface 21 of semiconductor substrate 10 to the deepest bottom of each trench portion.
  • the extension portion of each trench portion may be considered as one trench portion. In other words, the area sandwiched between two extension portions may be considered as a mesa portion.
  • the mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40.
  • the mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10.
  • the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.
  • the base region 14 is a region of a second conductivity type provided on the front surface 21 side of the semiconductor substrate 10.
  • the base region 14 is, for example, a P-type.
  • the base region 14 may be provided on both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.
  • the emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18.
  • the emitter region 12 is, for example, N+ type.
  • One example of a dopant for the emitter region 12 is arsenic (As).
  • the emitter region 12 is provided in contact with the gate trench portion 40 on the front surface 21 of the mesa portion 71.
  • the emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other.
  • the emitter region 12 is also provided below the contact hole 54.
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30.
  • the emitter region 12 is in contact with the dummy trench portion 30.
  • the contact region 15 is provided above the base region 14 and is a region of a second conductivity type having a higher doping concentration than the base region 14.
  • the contact region 15 is of P+ type, for example.
  • the contact region 15 is provided on the front surface 21 of the mesa portion 71.
  • the contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other.
  • the contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30.
  • the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40.
  • the contact region 15 is also provided below the contact hole 54.
  • FIG. 1B shows an example of the a-a' cross section in FIG. 1A.
  • the a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a collector electrode 24, and an active contact section 124.
  • the collector electrode 24 is an example of a backside metal layer provided in contact with the back surface 23 of the semiconductor substrate 10.
  • the emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.
  • the drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10.
  • the drift region 18 is, as an example, N-type.
  • the drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein.
  • the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.
  • the buffer region 20 is a region of a first conductivity type provided on the back surface 23 side of the semiconductor substrate 10 relative to the drift region 18.
  • the buffer region 20 is, as an example, an N-type.
  • the doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18.
  • the buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type.
  • the buffer region 20 may be omitted.
  • the collector region 22 is provided below the buffer region 20 in the transistor section 70.
  • the collector region 22 has the second conductivity type.
  • the collector region 22 is, as an example, a P+ type.
  • the collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10.
  • the collector electrode 24 is formed of a conductive material such as a metal.
  • the material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.
  • the base region 14 is a second conductivity type region provided above the drift region 18.
  • the base region 14 is provided in contact with the gate trench portion 40.
  • the base region 14 may be provided in contact with the dummy trench portion 30.
  • the emitter region 12 is provided above the base region 14.
  • the emitter region 12 is provided between the base region 14 and the front surface 21.
  • the emitter region 12 is provided in contact with the gate trench portion 40.
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30.
  • the accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18.
  • the accumulation region 16 is an N+ type, for example.
  • the accumulation region 16 does not necessarily have to be provided.
  • the accumulation region 16 is provided in contact with the gate trench portion 40.
  • the accumulation region 16 may or may not be in contact with the dummy trench portion 30.
  • the doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18.
  • the dose of ion implantation of the accumulation region 16 may be 1.0E+12 cm ⁇ 2 or more and 1.0E+13 cm ⁇ 2 or less.
  • the dose of ion implantation of the accumulation region 16 may be 3.0E+12 cm ⁇ 2 or more and 6.0E+12 cm ⁇ 2 or less.
  • Each trench portion may be an active trench portion 122 of the active portion 120.
  • Each trench portion is provided from the front surface 21 to the drift region 18. In the region where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions to reach the drift region 18.
  • the trench portion penetrating the doping region is not limited to being manufactured in the order of forming the doping region and then the trench portion.
  • the trench portion penetrating the doping region also includes a trench portion formed after the trench portion is formed.
  • the gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21.
  • the gate insulating film 42 is formed to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is formed inside the gate trench, further inside than the gate insulating film 42.
  • the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate trench portion 40 is covered by an interlayer insulating film 38 on the front surface 21.
  • the gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer on the surface layer of the interface of the base region 14 that contacts the gate trench.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40.
  • the dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side.
  • the dummy insulating film 32 is formed to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is formed inside the dummy trench and is formed further inward than the dummy insulating film 32.
  • the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.
  • the dummy trench portion 30 may be covered by an interlayer insulating film 38 on the front surface 21.
  • the interlayer insulating film 38 is provided above the semiconductor substrate 10.
  • the interlayer insulating film 38 is provided in contact with the front surface 21.
  • An emitter electrode 52 is provided above the interlayer insulating film 38.
  • the interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10.
  • the contact holes 55 and 56 may also be provided penetrating the interlayer insulating film 38.
  • the interlayer insulating film 38 may be a boro-phospho silicate glass (BPSG) film, a boro-silicate glass (BSG) film, a phosphosilicate glass (PSG) film, an HTO film, or a laminate of these materials.
  • the thickness of the interlayer insulating film 38 is, for example, 1.0 ⁇ m, but is not limited to this.
  • the active contact portion 124 is provided in the interlayer insulating film 38 above the active trench portion 122.
  • the active contact portion 124 may include a first active contact portion 1241 and a second active contact portion 1242 described later.
  • the first active contact portion 1241 may contact the upper surface of the mesa portion of the semiconductor substrate 10.
  • the first active contact portion 1241 may have a contact hole 54 and a metal layer filled inside the contact hole 54.
  • the inside of the contact hole 54 may be filled with the same material as the emitter electrode 52, or may be filled with a material different from the emitter electrode 52.
  • the active contact portion 124 may include a barrier metal film 1243 provided in the contact hole 54 and in contact with the semiconductor substrate 10.
  • the active contact portion 124 may include a plug portion 1244 provided to contact the barrier metal film 1243 and fill the contact hole 54.
  • the barrier metal film 1243 of the active contact portion 124 may contain titanium or a titanium compound.
  • the plug portion 1244 of the active contact portion 124 may contain a plug metal such as tungsten.
  • An alloy layer may be formed in contact with the barrier metal film 1243, the alloy layer being made of an alloy of a metal contained in the barrier metal film 1243 and a layer of the semiconductor substrate 10 or the like below the contact hole 54.
  • a region of high impurity concentration may be formed in the layer of the semiconductor substrate 10 or the like below the contact hole 54 at a location in contact with the alloy layer.
  • the active contact portion 124 in this example is an example of a main region contact portion 224 provided in the main region 220 described later.
  • the back side lifetime control region 151 may be provided in the transistor section 70. However, the back side lifetime control region 151 may be omitted.
  • the back side lifetime control region 151 is a region in which a lifetime killer is intentionally formed by injecting impurities into the semiconductor substrate 10. In one example, the back side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back side lifetime control region 151 may also be formed by injecting protons.
  • the lifetime killer is a carrier recombination center.
  • the lifetime killer may be a lattice defect.
  • the lifetime killer may be a vacancy, a divacancy, a compound defect of these with the elements that make up the semiconductor substrate 10, or a dislocation.
  • the lifetime killer may also be a rare gas element such as helium or neon, or a metal element such as platinum.
  • An electron beam or protons may be used to form the lattice defect.
  • the lifetime killer concentration is the concentration of carrier recombination centers.
  • the lifetime killer concentration may be the concentration of lattice defects.
  • the lifetime killer concentration may be the concentration of vacancies such as vacancies and divacancies, or may be the concentration of complex defects between these vacancies and the elements that make up the semiconductor substrate 10, or may be the dislocation concentration.
  • the lifetime killer concentration may also be the chemical concentration of a rare gas element such as helium or neon, or may be the chemical concentration of a metal element such as platinum.
  • the back side lifetime control region 151 may be formed by injection from the back side 23. This makes it easier to avoid any effects on the front surface 21 side of the semiconductor device 100.
  • the back side lifetime control region 151 is formed by irradiating helium or protons from the back side 23.
  • whether the back side lifetime control region 151 is formed by injection from the front surface 21 side or the back surface 23 side can be determined by obtaining the state of the front surface 21 side using the SR method or by measuring leakage current.
  • FIG. 2A shows an enlarged view of the top surface of a modified example of the semiconductor device 100.
  • the semiconductor device 100 of this example includes a transistor portion 70 and a diode portion 80.
  • the configuration in this figure may be arranged periodically or continuously in the +X-axis direction and the -X-axis direction.
  • the semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 provided inside the front surface 21 side of the semiconductor substrate 10.
  • the gate trench portion 40 and the dummy trench portion 30 are each an example of an active trench portion 122.
  • the dummy trench portion 30 in this example may have a U-shape on the front surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions 31 that extend along the extension direction and a connection portion 33 that connects the two extension portions 31.
  • the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.
  • the emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
  • the transistor section 70 of this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80. However, the semiconductor device 100 does not need to include the boundary section 90.
  • the boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80.
  • the boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10.
  • the boundary portion 90 does not have an emitter region 12.
  • the trench portion of the boundary portion 90 is a dummy trench portion 30.
  • the boundary portion 90 is arranged so that both ends in the X-axis direction are dummy trench portions 30.
  • the contact holes 54 are provided above the base region 14 in the diode section 80.
  • the contact holes 54 are provided above the contact region 15 in the boundary section 90. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction.
  • the mesa portion 91 is provided in the boundary portion 90.
  • the mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10.
  • the mesa portion 91 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.
  • the mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30.
  • the mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10.
  • the mesa portion 81 has a well region 17 on the negative side in the Y-axis direction.
  • the emitter region 12 is provided in the mesa portion 71, but does not have to be provided in the mesa portion 81 and the mesa portion 91.
  • the contact region 15 is provided in the mesa portion 71 and the mesa portion 91, but does not have to be provided in the mesa portion 81.
  • FIG. 2B shows an example of the b-b' cross section in FIG. 2A.
  • the semiconductor device 100 of this example has a back surface side lifetime control region 151 and a front surface side lifetime control region 152. However, the semiconductor device 100 does not have to have either the back surface side lifetime control region 151 or the front surface side lifetime control region 152.
  • the semiconductor device 100 of this example has a collector region 22 and a cathode region 82 on the back surface 23 side of the buffer region 20.
  • the contact region 15 is provided above the base region 14 in the mesa portion 91.
  • the contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91.
  • the contact region 15 may be provided on the front surface 21 of the mesa portion 71.
  • the accumulation region 16 is provided in the transistor section 70 and the diode section 80.
  • the accumulation region 16 is provided on the entire surface of the transistor section 70 and the diode section 80.
  • the accumulation region 16 does not have to be provided in the diode section 80.
  • the cathode region 82 is provided below the buffer region 20 in the diode section 80.
  • the boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary section 90 in this example.
  • the back side lifetime control region 151 may be provided in both the transistor portion 70 and the diode portion 80, or may be provided only in the transistor portion 70, or may be provided only in the diode portion 80. This allows the semiconductor device 100 of this example to speed up the turn-off operation of the transistor portion 70 or the reverse recovery operation in the diode portion 80, thereby further improving switching loss.
  • the back side lifetime control region 151 may be formed by a method similar to that of the back side lifetime control region 151 of the other embodiments.
  • the front surface side lifetime control region 152 is provided on the front surface 21 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided in the drift region 18.
  • the front surface side lifetime control region 152 may be provided in both the transistor portion 70 and the diode portion 80, or may be provided only in the diode portion 80.
  • the front surface side lifetime control region 152 is provided in the diode portion 80 and the boundary portion 90, and may not be provided in a part of the transistor portion 70.
  • the front surface side lifetime control region 152 can suppress the injection of holes from the transistor portion 70 and the diode portion 80, thereby reducing reverse recovery loss.
  • the front surface side lifetime control region 152 may be formed by any of the methods for forming the back surface side lifetime control region 151.
  • the elements and dose amounts for forming the back surface side lifetime control region 151 and the front surface side lifetime control region 152 may be the same or different.
  • the front surface side lifetime control region 152 is provided by extending from the diode section 80 to the transistor section 70.
  • the front surface side lifetime control region 152 may be formed by introducing a lifetime killer from the front surface 21 of the semiconductor substrate 10.
  • the front surface side lifetime control region 152 may be formed by irradiation from the back surface 23 side of the semiconductor substrate 10.
  • the front surface side lifetime control region 152 is provided below the gate trench section 40.
  • the semiconductor device 100 may be a power semiconductor device for controlling power, etc.
  • the semiconductor device 100 of this example may have a vertical semiconductor structure with a backside metal layer on the backside 23 side of the semiconductor substrate 10.
  • the semiconductor device 100 may also have a horizontal semiconductor structure without a metal layer on the backside 23 side.
  • an RC-IGBT with a trench gate structure is described as an example of the semiconductor device 100.
  • the semiconductor device 100 may be a semiconductor device with a planar gate structure, or may be another semiconductor device such as a diode.
  • the semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET.
  • FIG. 3 shows an example of a top view of the semiconductor device 100.
  • the semiconductor device 100 in this example includes a temperature-sensing unit 180. In this example, only some of the components of the semiconductor device 100 are shown, and some components are omitted.
  • the semiconductor substrate 10 has end edges 102 when viewed from above.
  • the semiconductor substrate 10 has two sets of end edges 102 that face each other when viewed from above.
  • the X-axis and the Y-axis are parallel to one of the end edges 102.
  • the semiconductor substrate 10 has an active portion 120.
  • the active portion 120 is a region through which a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation.
  • An emitter electrode 52 is provided above the active portion 120, but is omitted in this figure.
  • the active section 120 may be provided with at least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD).
  • the transistor section 70 and the diode section 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface 21 of the semiconductor substrate 10.
  • the active section 120 may be provided with only one of the transistor section 70 and the diode section 80. That is, the active section 120 may be provided with only the transistor section 70 as shown in FIG. 1A, may be provided with both the transistor section 70 and the diode section 80 as shown in FIG. 2A, or may be provided with only the diode section 80.
  • the region in which the transistor section 70 is arranged is marked with the symbol "I”
  • the region in which the diode section 80 is arranged is marked with the symbol "F”.
  • the transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction.
  • the extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of the gate trench section 40 and the dummy trench section 30.
  • the diode section 80 may be a region obtained by projecting a cathode region 82 provided on the rear surface 23 side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10.
  • the region obtained by projecting the cathode region 82 onto the upper surface of the semiconductor substrate 10 may be located inside the diode section 80.
  • a P+ type collector region 22 may be provided in the region other than the cathode region 82 on the rear surface 23 of the semiconductor substrate 10.
  • the edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. When viewed from above, the edge termination structure 140 is provided between the active section 120 and the edge 102. The edge termination structure 140 relieves electric field concentration on the front surface 21 side of the semiconductor substrate 10.
  • the edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf that are provided in a ring shape surrounding the active section 120.
  • the semiconductor device 100 may have one or more pads above the semiconductor substrate 10.
  • the semiconductor device 100 of this example includes a gate pad 112, a sense electrode 114, an anode pad 116, and a cathode pad 118.
  • Each pad may be located near an edge 102 of the semiconductor substrate 10. The vicinity of the edge 102 refers to the area between the edge 102 and the emitter electrode 52 in a top view.
  • each pad may be connected to an external circuit via wiring such as a wire.
  • a gate potential is applied to the gate pad 112.
  • the gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 of the active portion 120.
  • the semiconductor device 100 may include a gate wiring that connects the gate pad 112 and the gate trench portion 40.
  • the gate wiring may be configured by appropriately combining either the gate metal layer 50 or the connection portion 25, or both.
  • the sense electrode 114 is electrically connected to a current sense section 115 provided below the sense electrode 114.
  • the sense electrode 114 detects the current flowing through the current sense section 115.
  • the current sense section 115 detects the current flowing through the transistor section 70.
  • the current sense section 115 has a structure corresponding to the transistor section 70.
  • the current flowing through the current sense section 115 is smaller than the current flowing through the transistor section 70.
  • a current proportional to the current flowing through the transistor section 70 may flow through the current sense section 115, simulating the operation of the transistor section 70.
  • the ratio of the current flowing through the current sense section 115 to the current flowing through the transistor section 70 is appropriately set.
  • the current flowing through the transistor section 70 can be monitored by using the current sense section 115.
  • the temperature sensing section 180 is provided on or inside the semiconductor substrate 10. In this example, the temperature sensing section 180 is provided between the transistor sections 70 in the center of the semiconductor device 100. The temperature sensing section 180 detects the temperature of the active section 120.
  • the temperature sensing section 180 may have a diode formed of monocrystalline or polycrystalline silicon.
  • the temperature sensing section 180 is used to detect the temperature of the semiconductor device 100 and protect the semiconductor chip (semiconductor substrate 10) from overheating.
  • the temperature sensing section 180 is connected to a constant current source. When the temperature of the semiconductor device 100 changes, the forward voltage of the current flowing through the temperature sensing section 180 changes. The semiconductor device 100 can detect the temperature based on the change in the forward voltage of the temperature sensing section 180.
  • the anode pad 116 is electrically connected to the temperature-sensitive anode region 182 of the temperature-sensitive section 180.
  • the anode pad 116 is electrically connected to the temperature-sensitive anode region 182 of the temperature-sensitive section 180 by the anode wiring section 117, which is electrically connected to the temperature-sensitive anode region 182.
  • the temperature-sensitive anode region 182 will be described later.
  • the cathode pad 118 is electrically connected to the temperature-sensing cathode region 181 of the temperature-sensing section 180.
  • the cathode pad 118 is electrically connected to the temperature-sensing cathode region 181 of the temperature-sensing section 180 by a cathode wiring section 119 that is electrically connected to the temperature-sensing cathode region 181.
  • the temperature-sensing cathode region 181 will be described later.
  • FIG. 4A shows an example of a cross section of a semiconductor device 100 including a temperature-sensing section 180.
  • the cross section in this example is a cross section taken along line c-c' in FIG. 3, and is an XZ plane passing through the contact hole 54 in the active section 120.
  • the temperature-sensing section 180 has a temperature-sensing diode 183 and a temperature-sensing contact section 188.
  • the interlayer insulating film 38 may include a first interlayer insulating film 36 and a second interlayer insulating film 37. The interlayer insulating film 38 may be thinner than the emitter electrode 52.
  • the first interlayer insulating film 36 may be thinner than the emitter electrode 52, and the second interlayer insulating film 37 may be thinner than the emitter electrode 52.
  • the temperature-sensing contact section 188 may have a barrier metal film 1882 and a plug section 1884. The barrier metal film 1882 and the plug section 1884 of the temperature-sensing contact section 188 will be described later.
  • the temperature-sensitive diode 183 is provided above the semiconductor substrate 10. Above may be the positive direction in the Z-axis direction with respect to the front surface 21 of the semiconductor substrate 10.
  • the temperature-sensitive diode 183 may be a PN diode including a temperature-sensitive anode region 182 provided above the semiconductor substrate 10 and a temperature-sensitive cathode region 181 provided above the semiconductor substrate 10 and in contact with the temperature-sensitive anode region 182.
  • the temperature-sensitive cathode region 181 may be formed of an N-type semiconductor and may function as the cathode of the PN diode.
  • the temperature-sensitive anode region 182 may be formed of a P-type semiconductor and may function as the anode of the PN diode.
  • the material of the temperature-sensitive cathode region 181 and the temperature-sensitive anode region 182 may be a polycrystalline semiconductor, and may be polysilicon, for example.
  • a well region 17 may be provided in the semiconductor substrate 10.
  • the well region 17 provided below the temperature sensing diode 183 may be the same as the well region 17 provided on the peripheral side of the active section 120 in FIG. 1A, and may be formed in the same process.
  • the temperature-sensitive contact portion 188 is provided in the interlayer insulating film 38 above the temperature-sensitive diode 183.
  • the interlayer insulating film 38 in which the temperature-sensitive contact portion 188 is provided may be the first interlayer insulating film 36.
  • the temperature-sensitive contact portion 188 may have a contact hole 58 and a metal layer filled inside the contact hole 58.
  • the sidewall of the temperature-sensitive contact portion 188 may be in contact with the interlayer insulating film 38 from the upper end to the lower end. In other words, the contact hole 58 may be provided so as to penetrate the first interlayer insulating film 36.
  • the contact width Wd at which the temperature sensitive contact portion 188 contacts the temperature sensitive diode 183 may be larger than the contact width of the active contact portion 124.
  • the contact width Wd of the temperature sensitive contact portion 188 may be larger than the first active contact width Wt1 of the first active contact portion 1241.
  • the first active contact width Wt1 may be the width at which the first active contact portion 1241 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10.
  • the active contact portion 124 in this example is an example of a main region contact portion 224 provided in the main region 220 described later.
  • the cathode wiring section 119 is electrically connected to the temperature-sensitive cathode region 181 via the contact hole 58.
  • the cathode wiring section 119 may be formed of a metal material.
  • the cathode wiring section 119 may be formed of the same material as the emitter electrode 52.
  • the temperature-sensitive cathode region 181 may be electrically connected to the cathode pad 118 by the cathode wiring section 119.
  • the anode wiring section 117 is electrically connected to the temperature-sensitive anode region 182 via the contact hole 58.
  • the anode wiring section 117 may be formed of a metal material.
  • the anode wiring section 117 may be formed of the same material as the emitter electrode 52.
  • the temperature-sensitive anode region 182 may be electrically connected to the anode pad 116 by the anode wiring section 117.
  • the first interlayer insulating film 36 may be provided above the temperature sensing diode 183.
  • the first interlayer insulating film 36 may be a BPSG film, a BSG film, a PSG film, an HTO film, or a laminate of these materials.
  • the second interlayer insulating film 37 may be provided between the temperature sensing diode 183 and the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the second interlayer insulating film 37 may be any oxide film.
  • the second interlayer insulating film 37 may be the same thermal oxide film as the gate insulating film 42 or the dummy insulating film 32.
  • the second interlayer insulating film 37 may be a BPSG film, a BSG film, a PSG film, or an HTO film.
  • FIG. 4B shows another example of a cross section of the semiconductor device 100 including the temperature sensing portion 180.
  • the cross section in this example is an XZ plane passing through the contact hole 56 in the active portion 120.
  • the active contact portion 124 may include a second active contact portion 1242.
  • the second active contact portion 1242 may be in contact with the active trench portion 122.
  • the second active contact portion 1242 is in contact with the dummy trench portion 30.
  • the second active contact portion 1242 may have a contact hole 56 and a metal layer filled inside the contact hole 56.
  • the inside of the contact hole 56 may be filled with the same material as the emitter electrode 52, or may be filled with a material different from the emitter electrode 52.
  • the contact width Wd at which the temperature sensitive contact portion 188 contacts the temperature sensitive diode 183 may be larger than the contact width of the active contact portion 124.
  • the contact width Wd of the temperature sensitive contact portion 188 may be larger than the second active contact width Wt2 of the second active contact portion 1242.
  • the second active contact width Wt2 may be the width at which the second active contact portion 1242 contacts the active trench portion 122.
  • Figure 4C shows a cross section of a modified example of the semiconductor device 100 including a temperature-sensing portion 180.
  • the semiconductor device 100 of this example differs from the embodiment of Figure 4A in that the temperature-sensing portion 180 has a temperature-sensing trench contact portion 1885, and the active portion 120 has an active trench contact portion 1245.
  • the differences from the embodiment of Figure 4A will be particularly described, and the rest may be the same as the embodiment of Figure 4A.
  • the contact width of the temperature-sensing contact portion 188 may be larger than the contact width of the active contact portion 124.
  • the active portion 120 may have a plurality of active trench contact portions 1245 extending from the upper surface of the interlayer insulating film 38 downward beyond the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the active trench contact portions 1245 are an example of active contact portions 124.
  • the active trench contact portions 1245 are portions that are deeper toward the rear surface 23 side than the front surface 21 of the semiconductor substrate 10.
  • the active contact portions 124 in this example are an example of main region contact portions 224 provided in the main region 220 described later.
  • the active trench contact portions 1245 in this example are an example of main region trench contact portions 2245.
  • the extension depth Dd of the temperature-sensitive trench contact portion 1885 extending from the upper surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate may be the same as the extension depth Dt of the multiple active trench contact portions 1245 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the contact width Wtd at which the temperature sensitive trench contact portion 1885 contacts the temperature sensitive diode 183 may be larger, the same as, or smaller than the contact width Wtt1 of the first active contact portion 1241.
  • the contact width Wtd of the temperature sensitive trench contact portion 1885 may be the width at which the temperature sensitive trench contact portion 1885 contacts the upper surface of the temperature sensitive diode 183.
  • the first active contact width Wtt1 may be the width at which the first active contact portion 1241 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10.
  • the embodiment of FIG. 4B may also have an active trench contact portion 1245 and a temperature sensitive trench contact portion 1885, as in this example.
  • FIG. 5A shows a cross section of a modified example of a semiconductor device 100 including a temperature-sensing portion 180.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 4A in that it has a recess region 194.
  • the differences from the embodiment of FIG. 4A will be particularly described, and the rest may be the same as the embodiment of FIG. 4A. That is, the contact width of the temperature-sensing contact portion 188 may be larger than the contact width of the active contact portion 124.
  • the active contact portion 124 of this example is an example of a main region contact portion 224 provided in the main region 220, which will be described later.
  • the temperature sensing portion 180 may have a recessed region 194 in which a depression is provided on the upper surface of the semiconductor substrate 10.
  • the temperature sensing diode 183 may be provided in the recessed region 194.
  • the temperature sensing diode 183 may be provided above an insulating film 196 in the recessed region 194.
  • the insulating film 196 may be any oxide film.
  • the insulating film 196 may be the same thermal oxide film as the edge termination structure portion 140, the gate insulating film 42, the dummy insulating film 32, or the like.
  • the insulating film 196 may be a BPSG film, a BSG film, a PSG film, or an HTO film.
  • the height position of the upper surface of the interlayer insulating film 38 in the active portion 120 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 194.
  • the height positions being the same may include the height positions being approximately (substantially) the same.
  • the height positions being approximately (substantially) the same may mean that the distance from the front surface 21 of the semiconductor substrate 10 in the active portion 120 to the upper surface of the interlayer insulating film 38 and the distance from the front surface 21 of the semiconductor substrate 10 in the recess region 194 to the upper surface of the interlayer insulating film 38 are within 20% of the average value of both, or may be within 10% of the average value.
  • the active contact portion 124 and the temperature-sensitive contact portion 188 can be formed simultaneously by the same etching process. That is, if the upper surfaces of the interlayer insulating film 38 in the active portion 120 and the interlayer insulating film 38 in the recessed region 194 are at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure in the photolithography process. Therefore, the dimensional tolerance of the interlayer insulating film, the emitter electrode, etc. can be reduced.
  • FIG. 5B shows a cross section of a modified example of the semiconductor device 100 including a temperature-sensing portion 180.
  • the semiconductor device 100 of this example differs from the embodiment of FIGS. 4A and 5A in that the temperature-sensing portion 180 has a housing portion 198.
  • the differences from the embodiment of FIGS. 4A and 5A will be particularly described, and the rest may be the same as the embodiment of FIGS. 4A and/or 5A. That is, the contact width of the temperature-sensing contact portion 188 may be larger than the contact width of the active contact portion 124.
  • the active contact portion 124 of this example is an example of the main region contact portion 224 provided in the main region 220 described later.
  • the housing portion 198 is provided below the temperature-sensitive contact portion 188.
  • the material of the housing portion 198 may be the same as the material of the first interlayer insulating film 36, may be the same as the material of the second interlayer insulating film 37, or may be the same as the material of the temperature-sensitive diode 183.
  • the detailed configuration of the housing portion 198 will be described later.
  • FIG. 6A shows an example of an enlarged cross-section of the semiconductor device 100. This figure shows the area of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10.
  • the bottom corner 1880 of the temperature sensitive contact portion 188 may be in contact with the temperature sensitive diode 183.
  • the bottom corner 1880 of the temperature sensitive contact portion 188 may be the intersection of the bottom surface of the temperature sensitive contact portion 188 and the side surface of the temperature sensitive contact portion 188.
  • the bottom corner 1880 in contact with the temperature sensitive diode 183 may be in contact with the temperature sensitive diode 183 on the top surface of the temperature sensitive diode 183, may be in contact with the temperature sensitive diode 183 on the side surface of the temperature sensitive diode 183, or may be in contact with the temperature sensitive diode 183 in an internal region of the temperature sensitive diode 183.
  • the bottom corner 1880 is in contact with the temperature sensitive diode 183 on the top surface of the temperature sensitive diode 183.
  • the temperature sensitive contact portion 188 in this example has two bottom corners 1880. One of the two bottom corners 1880 may contact the temperature sensitive diode 183. The other of the two bottom corners 1880 may contact the housing portion 198, or may not contact the housing portion 198.
  • the temperature sensitive contact portion 188a in this example has one bottom corner 1880a in contact with the temperature sensitive cathode region 181 of the temperature sensitive diode 183, and the other bottom corner 1880b in contact with the housing portion 198.
  • the bottom surface of the temperature sensitive contact portion 188 may be in contact with the housing portion 198.
  • the bottom surface of the temperature sensitive contact portion 188 may be the surface between the two bottom corner portions 1880 of the temperature sensitive contact portion 188.
  • the bottom surface of the temperature sensitive contact portion 188 in contact with the housing portion 198 may be in contact with the housing portion 198 at the upper surface of the housing portion 198, or in contact with the housing portion 198 in an area inside the housing portion 198.
  • the bottom surface of the temperature sensitive contact portion 188 is in contact with the housing portion 198 at the upper surface of the housing portion 198.
  • the bottom surface of the temperature-sensitive contact portion 188 may be in contact with the temperature-sensitive diode 183 and the housing portion 198.
  • one bottom corner portion 1880a of the temperature-sensitive contact portion 188a is in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183, and the other bottom corner portion 1880b is in contact with the housing portion 198, so that the bottom surface of the temperature-sensitive contact portion 188a is in contact with the temperature-sensitive diode 183 and the housing portion 198.
  • the temperature-sensitive diode 183 may contact the bottom surface of the temperature-sensitive contact portion 188 from the bottom corner 1880 to an area of 10% to 40% of the bottom surface of the temperature-sensitive contact portion 188. That is, the ratio of the area of the surface of the bottom surface of the temperature-sensitive contact portion 188 that contacts the temperature-sensitive diode 183 to the area of the bottom surface of the temperature-sensitive contact portion 188 may be 10% to 40%.
  • the length L1 is the length of the bottom surface of the temperature-sensitive contact portion 188 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10.
  • the length L2 is the length of the bottom surface of the bottom surface of the temperature-sensitive contact portion 188 that contacts the temperature-sensitive diode 183 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of the length L2 to the length L1 may be 10% to 40%.
  • the temperature sensing diode 183 contacts the bottom surface of the temperature sensing contact portion 188a from the bottom corner 1880a to 25% of the area of the bottom surface of the temperature sensing contact portion 188. In other words, the ratio of length L2 to length L1 in this example is 25%.
  • the bottom surface of the temperature-sensitive contact portion 188a in contact with the temperature-sensitive cathode region 181, the bottom corner 1880a, and the bottom corner 1880b are given as examples, but the same may be true for the temperature-sensitive contact portion 188b in contact with the temperature-sensitive anode region 182.
  • the bottom corner 1880 of the temperature-sensitive contact portion 188b may be in contact with the temperature-sensitive diode 183
  • the bottom surface of the temperature-sensitive contact portion 188b may be in contact with the housing portion 198
  • the bottom surface of the temperature-sensitive contact portion 188b may be in contact with the temperature-sensitive diode 183 and the housing portion 198
  • the temperature-sensitive diode 183 may be in contact with the bottom surface of the temperature-sensitive contact portion 188b from the bottom corner 1880 to an area of 10% to 40% of the bottom surface of the temperature-sensitive contact portion 188b.
  • the length L1 and length L2 of the temperature-sensitive contact portion 188b may be the same as those of the temperature-sensitive contact portion 188a.
  • the temperature-sensitive contact portion 188 is provided with the bottom corner portion 1880 in contact with the temperature-sensitive diode 183 and the bottom surface in contact with the housing portion 198. This ensures reliable electrical connection between the anode pad 116 and the cathode pad 118 and the temperature-sensitive diode 183. If the plug portion 1884 and the barrier metal film 1882 near the center of the bottom surface of the temperature-sensitive contact portion 188 are removed by over-etching during the etch-back process of the plug portion 1884, voids may occur inside the temperature-sensitive contact portion 188. Even in this case, the electrical connection can be ensured by the barrier metal film 1882 and/or the plug portion 1884 remaining at the bottom corner portion 1880 of the temperature-sensitive contact portion 188. The barrier metal film 1882 and the plug portion 1884 will be described later.
  • the temperature-sensitive contact portion 188 in this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the temperature-sensitive contact portion near the center of the bottom surface, the effect on the electrical connection at the bottom corner portion 1880 between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 is suppressed. This makes it possible to improve the yield of semiconductor devices 100 having desired characteristics.
  • the temperature-sensitive portion 180 in this example ensures that the electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 is made via the bottom corner portion 1880 rather than the bottom center portion of the temperature-sensitive contact portion 188. This makes it possible to obtain stable quality and improve yields, even if a void is formed in the area near the center of the temperature-sensitive contact portion 188 that contacts the housing portion 198.
  • the temperature-sensitive contact portion 188 may have a barrier metal film 1882 and a plug portion 1884.
  • the barrier metal film 1882 and the plug portion 1884 are formed of different materials, but may be formed of the same material.
  • the barrier metal film 1882 may be provided on the bottom corners 1880 of the temperature-sensitive contact portion 188. In this example, the barrier metal film 1882 is provided over the entire side and bottom surface of the temperature-sensitive contact portion 188, but is not limited to this. The barrier metal film 1882 may be provided to cover at least the bottom corners 1880, or may be provided without covering the center of the bottom surface of the temperature-sensitive contact portion 188. The barrier metal film 1882 may extend beyond the contact hole 58 and extend above the first interlayer insulating film 36.
  • the material of the barrier metal film 1882 may be titanium or a titanium compound, etc.
  • the plug portion 1884 may be provided in contact with the inner side of the barrier metal film 1882.
  • the plug portion 1884 is provided by filling the temperature-sensitive contact portion 188, but is not limited to this.
  • the plug portion 1884 may be provided in a part of the temperature-sensitive contact portion 188, and may extend beyond the contact hole 58 and be provided above the first interlayer insulating film 36.
  • the plug portion 1884 is provided in a part of the temperature-sensitive contact portion 188, the remaining area of the temperature-sensitive contact portion 188 may be filled with the same material as the anode wiring portion 117 or the cathode wiring portion 119.
  • the material of the plug portion 1884 may be a plug metal such as tungsten.
  • the side of the temperature sensing diode 183 may be in contact with the side of the housing part 198.
  • the temperature sensing diode 183 has the side of each of the temperature sensing cathode region 181 and the temperature sensing anode region 182 in contact with the side of the housing part 198.
  • the upper surface of the second interlayer insulating film 37 may be in contact with the lower surface of the temperature sensing diode 183 and the lower surface of the housing part 198.
  • the upper surface of the second interlayer insulating film 37 is in contact with the lower surface of the housing part 198 provided in contact with the temperature sensing cathode region 181, the lower surface of the temperature sensing cathode region 181, the lower surface of the temperature sensing anode region 182, and the lower surface of the housing part 198 provided in contact with the temperature sensing anode region 182.
  • the housing portion 198 may be a region of the first interlayer insulating film 36 that is provided below the temperature-sensitive contact portion 188.
  • the housing portion 198 may be formed in the process of providing the first interlayer insulating film 36, and may be formed from the same material as the first interlayer insulating film 36.
  • the housing portion 198 is a virtual region. In other words, the housing portion 198 may be formed integrally as part of the first interlayer insulating film 36.
  • FIG. 6B shows an enlarged cross-section of a modified example of the semiconductor device 100.
  • This figure shows the region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 6A in that the shapes of the first interlayer insulating film 36 and the second interlayer insulating film 37 are different. In this example, the differences from the embodiment of FIG. 6A will be particularly described, and the rest may be the same as the embodiment of FIG. 6A.
  • the second interlayer insulating film 37 may have a recess 200 on the upper surface side.
  • the temperature sensing diode 183 may be provided in the recess 200 of the second interlayer insulating film 37.
  • the recess 200 may be formed by etching the upper surface of the second interlayer insulating film 37.
  • the upper surface of the temperature sensing diode 183 in this example may be flush with the upper surface of the recess 200, and may be lower than the upper surface of the recess 200.
  • the housing portion 198 may be the second interlayer insulating film 37 provided above the semiconductor substrate 10.
  • the housing portion 198 may be formed in the process of providing the second interlayer insulating film 37, and may be formed of the same material as the second interlayer insulating film 37.
  • the housing portion 198 is a virtual region, as shown by the dotted line in FIG. 6B. That is, the housing portion 198 may be formed integrally as a part of the second interlayer insulating film 37.
  • the housing portion 198 may be considered to be a part of the first interlayer insulating film 36, or may be considered to be composed of both the first interlayer insulating film 36 and the second interlayer insulating film 37.
  • the housing portion 198 may be considered to be part of the second interlayer insulating film 37, or may be considered to be made up of both the first interlayer insulating film 36 and the second interlayer insulating film 37.
  • FIG. 6C shows an enlarged cross-sectional view of a modified example of the semiconductor device 100.
  • This figure shows the region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example differs from the embodiment of FIGS. 6A and 6B in that a housing portion 198 is provided separately from the first interlayer insulating film 36 and the second interlayer insulating film 37.
  • the housing portion 198 of this example is provided in the region of the first interlayer insulating film 36 corresponding to the housing portion 198 of FIG. 6A, but may be provided in the region of the second interlayer insulating film 37 corresponding to the housing portion 198 of FIG. 6B.
  • the housing portion 198 may have polysilicon of a different conductivity type than the contact region 300 of the temperature sensitive diode 183.
  • the contact region 300 of the temperature sensitive diode 183 may be the temperature sensitive cathode region 181 or the temperature sensitive anode region 182 of the temperature sensitive diode 183 to which the housing portion 198 is in contact.
  • the housing portion 198a in this example is in contact with the temperature sensitive cathode region 181. Therefore, the housing portion 198a may have polysilicon of a different conductivity type than the temperature sensitive cathode region 181, which is the contact region 300 of the temperature sensitive diode 183. That is, the housing portion 198a may have P-type polysilicon or non-doped polysilicon.
  • the housing portion 198b in this example is in contact with the temperature sensitive anode region 182. Therefore, the housing portion 198b may have polysilicon of a different conductivity type than the temperature sensitive anode region 182, which is the contact region 300 of the temperature sensitive diode 183. That is, the housing portion 198b may have N-type polysilicon or non-doped polysilicon.
  • the temperature sensitive contact portion 188 is provided such that the bottom corner portion 1880 of the temperature sensitive contact portion 188 contacts the temperature sensitive diode 183.
  • the temperature sensitive contact portion 188 is provided such that the bottom surface of the temperature sensitive contact portion 188 contacts the housing portion 198.
  • the housing portion 198 and the contact area 300 with the housing portion 198 of the temperature sensitive diode 183 may have the same potential.
  • the housing part 198 and the contact region 300 of the temperature sensing diode 183 are at the same potential, no current flows between the housing part 198 and the temperature sensing diode 183, and the operation of the temperature sensing diode 183 is not affected by the housing part 198.
  • the housing part 198a has P-type polysilicon, which is a different conductivity type from the temperature sensing cathode region 181
  • the housing part 198a and the temperature sensing cathode region 181 have the same potential, so that substantially no current flows through the PN junction at the contact interface. Therefore, the operation of the temperature sensing diode 183 is not affected by the housing part 198.
  • the housing part 198b has N-type polysilicon, which is a different conductivity type from the temperature sensing anode region 182, the housing part 198b and the temperature sensing anode region 182 have the same potential, so that the PN junction at the contact interface does not function and does not impede the operation of the temperature sensing diode 183.
  • the housing portion 198 may have the same conductivity type as the contact region 300 of the temperature sensitive diode 183 and may have polysilicon with a lower doping concentration than the contact region 300.
  • the housing portion 198a in this example is in contact with the temperature sensitive cathode region 181. Therefore, the housing portion 198a may have the same conductivity type as the temperature sensitive cathode region 181, which is the contact region 300 of the temperature sensitive diode 183, and may have polysilicon with a lower doping concentration than the temperature sensitive cathode region 181. In other words, the housing portion 198a may have N-type polysilicon.
  • the housing portion 198b in this example is in contact with the temperature sensitive anode region 182.
  • the housing portion 198b may have the same conductivity type as the temperature sensitive anode region 182, which is the contact region 300 of the temperature sensitive diode 183, and may have polysilicon with a lower doping concentration than the temperature sensitive anode region 182. That is, the housing portion 198b may have P-type polysilicon.
  • the housing part 198 Even if the housing part 198 has the same conductivity type as the contact region 300 of the temperature sensing diode 183, the doping concentration of the housing part 198 is lower than the doping concentration of the contact region 300, so there is little effect on the operation of the temperature sensing diode 183. Therefore, the housing part 198 is unlikely to impede the operation of the temperature sensing diode 183.
  • the housing portion 198a in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183 may have P-type, non-doped, or N-type polysilicon
  • the housing portion 198b in contact with the temperature-sensitive anode region 182 of the temperature-sensitive diode 183 may have N-type, non-doped, or P-type polysilicon. If the width of the polysilicon is narrow, a portion of the lower end of the temperature-sensitive contact portion 188 may overlap the interlayer insulating film 38.
  • the housing portion 198 can be considered to be made of a mixture of polysilicon and the first interlayer insulating film 36 and/or the second interlayer insulating film 37.
  • FIG. 7A shows an enlarged cross-sectional view of a modified example of the semiconductor device 100.
  • This figure shows the region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 6A in that the temperature-sensing portion 180 has a temperature-sensing trench contact portion 1885.
  • the differences from the embodiment of FIG. 6A will be particularly described, and the rest may be the same as the embodiment of FIG. 6A.
  • the temperature sensing portion 180 may have a temperature sensing trench contact portion 1885 extending from the upper surface of the interlayer insulating film 38 downward beyond the upper surface of the temperature sensing diode 183 in the depth direction of the semiconductor substrate 10.
  • the temperature sensing trench contact portion 1885 is an example of a temperature sensing contact portion 188.
  • the temperature sensing trench contact portion 1885 is a portion that is deeper toward the back surface 23 than the front surface of the temperature sensing diode 183.
  • the bottom corner portion 1880 of the temperature sensing contact portion 188 contacts the temperature sensing diode 183 on the side of the temperature sensing diode 183.
  • the sidewall of the temperature-sensitive contact portion 188 may be in contact with the temperature-sensitive diode 183 and the first interlayer insulating film 36.
  • the temperature-sensitive diode 183 may be in contact with the sidewall of the temperature-sensitive contact portion 188 from the bottom corner 1880 to an area of 10% to 90% of the sidewall of the temperature-sensitive contact portion. That is, the ratio of the area of the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 to the area of the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 may be 10% to 90%. Referring to FIG.
  • the length L3 is the length of the sidewall of the temperature-sensitive contact portion 188 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10
  • the length L4 is the length of the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less.
  • the temperature sensing diode 183 contacts the sidewall of the temperature sensing contact portion 188 from the bottom corner 1880 to 36% of the area of the sidewall of the temperature sensing contact portion 188. In other words, the ratio of length L4 to length L3 in this example is 36%.
  • FIG. 7B shows an enlarged cross-section of a modified example of the semiconductor device 100. This figure shows the region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 7A in that the housing portion 198 is a second interlayer insulating film 37 provided above the semiconductor substrate 10. The rest may be the same as the embodiment of FIG. 7A.
  • FIG. 7C shows an enlarged cross-sectional view of a modified example of the semiconductor device 100.
  • This figure shows the region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example differs from the embodiment of FIGS. 7A and 7B in that the housing portion 198 has polysilicon. The rest may be the same as the embodiment of FIGS. 7A and/or 7B.
  • the semiconductor device 100 of this example differs from the example of FIG. 4C in that the extension depth Dd of the temperature sensing trench contact portion 1885 extending from the upper surface of the temperature sensing diode in the depth direction of the semiconductor substrate 10 may be shallower than the extension depth Dt of the multiple active trench contact portions 1245 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the differences from the example of FIG. 4C are particularly described, and the rest may be the same as the example of FIG. 4C. That is, the contact width of the temperature sensing contact portion 188 may be larger than the contact width of the active contact portion 124.
  • the active contact portion 124 of this example is an example of the main region contact portion 224 provided in the main region 220 described later.
  • the active trench contact portion 1245 of this example is an example of the main region trench contact portion 2245.
  • the extension depth Dd of the temperature-sensitive trench contact portion 1885 from the top surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate may be shallower than the extension depth Dt of the multiple active trench contact portions 1245 from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the active trench contact portion 1245 extends deeper than the temperature-sensitive trench contact portion 1885, the active contact portion 124 is formed sufficiently deep in the contact region 15, thereby preventing latch-up.
  • the temperature sensitive trench contact portion 1885 and the active trench contact portion 1245 can be formed in the same process. However, the temperature sensitive trench contact portion 1885 and the active trench contact portion 1245 may be formed in different processes.
  • the contact width Wtd at which the temperature sensitive trench contact portion 1885 contacts the temperature sensitive diode 183 may be larger than, the same as, or smaller than the contact width Wtt1 of the first active contact portion 1241.
  • the contact width Wtd of the temperature sensitive trench contact portion 1885 may be the width at which the temperature sensitive trench contact portion 1885 contacts the upper surface of the temperature sensitive diode 183.
  • the first active contact width Wtt1 may be the width at which the first active contact portion 1241 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10.
  • FIG. 8B shows a cross section of a modified example of the semiconductor device 100 including the temperature-sensing portion 180.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 8A in that the contact width of the temperature-sensing contact portion 188 is the same as the contact width of the active contact portion 124, or the contact width of the temperature-sensing contact portion 188 is narrower than the contact width of the active contact portion 124.
  • the rest may be the same as the embodiment of FIG. 8A. That is, the extension depth Dd of the temperature-sensing trench contact portion 1885 may be shallower than the extension depth Dt of the active trench contact portion 1245.
  • the active contact portion 124 of this example is an example of the main region contact portion 224 provided in the main region 220 described later.
  • the active trench contact portion 1245 of this example is an example of the main region trench contact portion 2245.
  • FIG. 8C shows a cross section of a modified example of the semiconductor device 100 including the temperature sensitive portion 180.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 8A and FIG. 8B in that the extension depth Dd of the temperature sensitive trench contact portion 1885 is substantially 0.
  • the rest may be the same as the embodiment of FIG. 8A and/or FIG. 8B. That is, the temperature sensitive contact portion 188 does not extend to the temperature sensitive diode 183, and the active trench contact portion 1245 may extend to a depth Dt.
  • the active contact portion 124 of this example is an example of the main region contact portion 224 provided in the main region 220 described later.
  • the active trench contact portion 1245 of this example is an example of the main region trench contact portion 2245.
  • the extension depth Dd of the temperature sensitive trench contact portion 1885 may be shallower than the extension depth Dt of the active trench contact portion 1245, and in the examples shown in Figures 5A, 6A, 6B or 6C, the temperature sensitive contact portion 188 may not extend to the temperature sensitive diode 183, and the active trench contact portion 1245 may extend to a depth Dt.
  • the semiconductor device 100 of the present invention may satisfy at least one of the following conditions: the contact width of the temperature-sensitive contact portion 188 is larger than the contact width of the active contact portion 124, or the extension depth of the temperature-sensitive contact portion 188 is shallower than the extension depth of the active contact portion 124.
  • the contact width of the temperature-sensitive contact portion 188 may be larger than the contact width of the active contact portion 124, and the extension depth of the temperature-sensitive contact portion 188 and the extension depth of the active contact portion 124 may be the same.
  • the contact width of the temperature-sensitive contact portion 188 and the contact width of the active contact portion 124 may be the same, and the extension depth of the temperature-sensitive contact portion 188 may be shallower than the extension depth of the active contact portion 124.
  • the contact width of the temperature-sensitive contact portion 188 may be larger than the contact width of the active contact portion 124, and the extension depth of the temperature-sensitive contact portion 188 may be shallower than the extension depth of the active contact portion 124.
  • the temperature-sensitive contact portion 188 may not extend to the temperature-sensitive diode 183, and the active contact portion 124 may extend to the mesa portions 71, 81, and 91 or the active trench portion 122.
  • the active contact portion 124 and the temperature-sensitive contact portion 188 have different widths and/or depths, i.e., the active contact portion 124 and the temperature-sensitive contact portion 188 have different shapes, thereby ensuring stable electrical connection at each contact portion.
  • FIG. 9 shows an example of an enlarged view of the top surface of the semiconductor device 100.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 1A in that a connection portion 25 is provided between the emitter electrode 52 and the dummy conductive portion 34.
  • the differences from the embodiment of FIG. 1A will be particularly described, and the rest may be the same as the embodiment of FIG. 1A.
  • the semiconductor device 100 includes a main region 220, which is a portion through which the main current flows between the front surface 21 and the back surface 23 of the semiconductor substrate 10, and a peripheral region 230 that surrounds the main region 220.
  • the boundary between the main region 220 and the peripheral region 230 is the boundary between the base region 14 and the well region 17.
  • An interlayer insulating film 38 is provided above the front surface 21 of the semiconductor substrate 10, but the interlayer insulating film 38 is omitted in FIG. 9. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.
  • the contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion 44 in the transistor portion 70 via the connection portion 25.
  • the contact hole 56 electrically connects the emitter electrode 52 and the dummy conductive portion 34 in the dummy trench portion 30 via the connection portion 25.
  • the connection portion 25 is a conductive material such as polysilicon doped with impurities.
  • the connection portion 25 is polysilicon (N+) doped with N-type impurities.
  • Polysilicon is an example of a polycrystalline semiconductor.
  • the connection portion 25 is an example of a polycrystalline portion 232 provided above the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10.
  • the connection portion 25 is an example of a polycrystalline portion 232 that the peripheral region 230 has.
  • FIG. 10A shows an example of the dd' cross section in FIG. 9.
  • the dd' cross section is a YZ plane passing through the contact hole 56 in the peripheral region 230.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a collector electrode 24, and a first peripheral region contact portion 234.
  • the polycrystalline portion 232 is provided above the semiconductor substrate 10.
  • the polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10.
  • the polycrystalline portion 232 in this example is provided above the front surface 21 of the semiconductor substrate 10.
  • the polycrystalline portion 232 in this example is the connection portion 25.
  • the polycrystalline portion 232 may be provided above the third interlayer insulating film 238.
  • the third interlayer insulating film 238 may be, for example, the same material as the dummy insulating film 32.
  • the interlayer insulating film 38 is provided above the polycrystalline portion 232.
  • the first outer periphery region contact portion 234 is provided in the interlayer insulating film 38 above the polycrystalline portion 232.
  • the first outer periphery region contact portion 234 may have a contact hole 56 and a metal layer filled inside the contact hole 56. The detailed configuration of the first outer periphery region contact portion 234 will be described later.
  • the polycrystalline portion 232 may be connected to the emitter electrode 52 via the first outer peripheral region contact portion 234.
  • the polycrystalline portion 232 may be connected to the dummy conductive portion 34.
  • the connection portion 25 in this example is connected to the emitter electrode 52 via the first outer peripheral region contact portion 234, and is connected to the dummy conductive portion 34.
  • the main region 220 may have a main region contact portion 224 provided in the interlayer insulating film 38. Since this figure is a cross-sectional view of the peripheral region 230, the main region contact portion 224 is not shown.
  • the main region contact portion 224 is, for example, the active contact portion 124 shown in FIG. 4A.
  • the contact width Wo1 of the first peripheral region contact portion 234 may be larger than the contact width Wt1 of the main region contact portion 224.
  • the contact width Wo1 of the first peripheral region contact portion 234 may be the width at which the first peripheral region contact portion 234 contacts the polycrystalline portion 232.
  • the sidewall of the first peripheral region contact portion 234 may be the interlayer insulating film 38 from the upper end to the lower end.
  • the contact width of the first outer periphery region contact portion 234 is larger than the contact width of the main region contact portion 224.
  • the semiconductor device 100 can be manufactured stably even when miniaturized, and stable characteristics can be obtained.
  • the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed by different processes.
  • FIG. 10B shows an example of a cross section taken along line d-d' in FIG. 9.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 10A in that the peripheral region 230 has a first peripheral region trench contact portion 2345.
  • the differences from the embodiment of FIG. 10A will be particularly described, and the rest may be the same as the embodiment of FIG. 10A.
  • the peripheral region 230 may have a first peripheral region trench contact portion 2345 extending from the upper surface of the interlayer insulating film 38 downward beyond the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10.
  • the first peripheral region trench contact portion 2345 is an example of the first peripheral region contact portion 234.
  • the first peripheral region trench contact portion 2345 is a portion that is deeper toward the rear surface 23 of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 232.
  • the polycrystalline portion 232 may be connected to the emitter electrode 52 via the first outer periphery region trench contact portion 2345.
  • the polycrystalline portion 232 may be connected to the dummy conductive portion 34.
  • the connection portion 25 in this example is connected to the emitter electrode 52 via the first outer periphery region trench contact portion 2345, and is connected to the dummy conductive portion 34.
  • the main region 220 may have a main region trench contact portion 2245 extending from the upper surface of the interlayer insulating film 38 downward below the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • This figure is a cross-sectional view of the peripheral region 230, so the main region trench contact portion 2245 is not shown.
  • the main region trench contact portion 2245 is, for example, the active trench contact portion 1245 shown in FIG. 4C.
  • the main region trench contact portion 2245 is an example of the main region contact portion 224.
  • the main region trench contact portion 2245 is a portion that is deeper on the back surface 23 side than the front surface 21 of the semiconductor substrate 10.
  • the main region 220 may have a plurality of main region trench contact portions 2245 provided on the front surface 21 of the semiconductor substrate 10.
  • the extension depth Do1 of the first outer periphery region trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 is shallower than the extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the extension depth Do1 of the first outer periphery region trench contact portion 2345 may be 0, and the extension depth Dt of the main region trench contact portion 2245 may be a value of 0 or more.
  • the extension depth Do1 of the first outer periphery region trench contact portion 2345 shallower than the extension depth Dt of the main region trench contact portion 2245, it is possible to prevent the first outer periphery region contact portion 234 from penetrating the polycrystalline portion 232 and extending the third interlayer insulating film 238, thereby preventing the insulation between the polycrystalline portion 232 and the semiconductor substrate 10 from being lost.
  • insulation with the semiconductor substrate 10 is not required, but it should be noted that this may cause a problem in the first outer periphery region contact portion 234 in another region formed at the same time.
  • the main region trench contact portion 2245 extends deeper than the first outer periphery region trench contact portion 2345, latch-up can be suppressed by forming the main region contact portion 224 sufficiently deep in the contact region 15.
  • the first outer periphery region trench contact portion 2345 and the main region trench contact portion 2245 can be formed in the same process. However, the first outer periphery region trench contact portion 2345 and the main region trench contact portion 2245 may be formed in different processes.
  • the contact width Wto1 at which the first outer periphery region trench contact portion 2345 contacts the polycrystalline portion 232 may be larger than, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245.
  • the contact width Wto1 of the first outer periphery region trench contact portion 2345 may be the width at which the first outer periphery region trench contact portion 2345 contacts the upper surface of the polycrystalline portion 232.
  • the contact width Wtt1 of the main region trench contact portion 2245 may be the width at which the active trench contact portion 1245 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10, as shown in FIG. 4C.
  • FIG. 11A shows an example of the d-d' cross section in FIG. 9.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 10A in that the peripheral region 230 has a recess region 236.
  • the differences from the embodiment of FIG. 10A will be particularly described, and the rest may be the same as the embodiment of FIG. 10A.
  • the contact width Wo1 of the first peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.
  • the peripheral region 230 may have a recess region 236 in which a depression is provided on the upper surface of the semiconductor substrate 10.
  • the polycrystalline portion 232 may be provided in the recess region 236.
  • the polycrystalline portion 232 is provided on the front surface 21 side of the semiconductor substrate 10.
  • the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 236.
  • the height position being the same may include the height position being approximately (substantially) the same.
  • the height position being approximately (substantially) the same may mean that the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the main region 220 and the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the recess region 236 are within 20% of the average value of both, or may be within 10% of the average value.
  • the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed simultaneously by the same etching process.
  • the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 236 are at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure in the photolithography process. This makes it possible to reduce the dimensional tolerance of the interlayer insulating film 38, the emitter electrode 52, etc.
  • the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed with the same dimensional tolerance. This allows for easier manufacturing with fewer processes compared to the case where each contact portion is formed in a separate process. However, if the contact width of the first outer periphery region contact portion 234 is made larger than the contact width of the main region contact portion 224, the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed in different processes.
  • FIG. 11B shows an example of a cross section taken along line d-d' in FIG. 9.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 10B in that the peripheral region 230 has a recess region 236, and differs from the embodiment of FIG. 11A in that the peripheral region 230 has a first peripheral region trench contact portion 2345.
  • the rest may be the same as the embodiment of FIG. 10B and/or FIG. 11A.
  • FIG. 12A shows an example of a cross section taken along line d-d' in FIG. 9.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 10A in that the outer periphery region 230 has a housing portion 198.
  • the differences from the embodiment of FIG. 10A will be particularly described, and the rest may be the same as the embodiment of FIG. 10A.
  • the contact width Wo1 of the first outer periphery region contact portion 234 may be larger than the contact width of the main region contact portion 224.
  • the housing portion 198 is provided below the first outer peripheral region contact portion 234.
  • the material of the housing portion 198 may be the same as that of the interlayer insulating film 38.
  • FIG. 12B shows an example of an enlarged view of the d-d' cross section in FIG. 9. This view shows the area above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.
  • the bottom corner 2340 of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232.
  • the bottom corner 2340 of the first outer peripheral region contact portion 234 may be the intersection of the bottom surface of the first outer peripheral region contact portion 234 and the side surface of the first outer peripheral region contact portion 234.
  • the bottom corner 2340 in contact with the polycrystalline portion 232 may be in contact with the polycrystalline portion 232 on the top surface of the polycrystalline portion 232, may be in contact with the polycrystalline portion 232 on the side surface of the polycrystalline portion 232, or may be in contact with the polycrystalline portion 232 in an internal region of the polycrystalline portion 232.
  • the bottom corner 2340 is in contact with the polycrystalline portion 232 on the top surface of the polycrystalline portion 232.
  • the first outer peripheral region contact portion 234 in this example has two bottom corners 2340.
  • One of the two bottom corners 2340 may be in contact with the polycrystalline portion 232.
  • the other of the two bottom corners 2340 may be in contact with the housing portion 198, or may not be in contact with the housing portion 198.
  • the first outer peripheral region contact portion 234 has one bottom corner 2340a in contact with the polycrystalline portion 232, and the other bottom corner 2340b in contact with the housing portion 198.
  • the bottom surface of the first outer circumferential region contact portion 234 may be in contact with the housing portion 198.
  • the bottom surface of the first outer circumferential region contact portion 234 may be the surface between the two bottom corner portions 2340 of the first outer circumferential region contact portion 234.
  • the bottom surface of the first outer circumferential region contact portion 234 in contact with the housing portion 198 may be in contact with the housing portion 198 at the upper surface of the housing portion 198, or in contact with the housing portion 198 in an area inside the housing portion 198.
  • the bottom surface of the first outer circumferential region contact portion 234 is in contact with the housing portion 198 at the upper surface of the housing portion 198.
  • the bottom surface of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232 and the housing portion 198.
  • one bottom corner portion 2340a of the first outer peripheral region contact portion 234 is in contact with the polycrystalline portion 232
  • the other bottom corner portion 2340b is in contact with the housing portion 198, so that the bottom surface of the first outer peripheral region contact portion 234 is in contact with the polycrystalline portion 232 and the housing portion 198.
  • the polycrystalline portion 232 may contact the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340 to an area of 10% or more and 40% or less of the bottom surface of the first outer peripheral region contact portion 234.
  • the area ratio of the surface of the bottom surface of the first outer peripheral region contact portion 234 that contacts the polycrystalline portion 232 to the area of the bottom surface of the first outer peripheral region contact portion 234 may be 10% or more and 40% or less.
  • the length L1 is the length of the bottom surface of the first outer peripheral region contact portion 234 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10.
  • the length L2 is the length of the bottom surface of the first outer peripheral region contact portion 234 that contacts the polycrystalline portion 232 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of the length L2 to the length L1 may be 10% or more and 40% or less.
  • the polycrystalline portion 232 contacts the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340a to an area of 20% of the bottom surface of the first outer peripheral region contact portion 234. That is, the ratio of length L2 to length L1 in this example is 20%.
  • the first outer periphery region contact portion 234 may have a barrier metal film 2342 and a plug portion 2344.
  • the barrier metal film 2342 and the plug portion 2344 are formed of different materials, but may be formed of the same material.
  • the barrier metal film 2342 may be provided on the bottom corners 2340 of the first outer periphery region contact portion 234. In this example, the barrier metal film 2342 is provided over the entire side and bottom surface of the first outer periphery region contact portion 234, but is not limited to this. The barrier metal film 2342 may be provided to cover at least the bottom corners 2340, or may be provided without covering the center portion of the bottom surface of the first outer periphery region contact portion 234. The barrier metal film 2342 may extend beyond the contact hole 56 and extend above the interlayer insulating film 38.
  • the material of the barrier metal film 2342 may be titanium or a titanium compound, etc.
  • the plug portion 2344 may be provided in contact with the inner side of the barrier metal film 2342.
  • the plug portion 2344 is provided by filling the first outer periphery region contact portion 234, but is not limited to this.
  • the plug portion 2344 may be provided in a part of the first outer periphery region contact portion 234, and may extend beyond the contact hole 56 and be provided above the interlayer insulating film 38.
  • the plug portion 2344 is provided in a part of the first outer periphery region contact portion 234, the remaining area of the first outer periphery region contact portion 234 may be filled with the same material as the emitter electrode 52.
  • the material of the plug portion 2344 may be a plug metal such as tungsten.
  • the side of the polycrystalline portion 232 may be in contact with the side of the housing portion 198.
  • the housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the first outer peripheral region contact portion 234.
  • the housing portion 198 may be formed in the process of providing the interlayer insulating film 38, and may be formed of the same material as the interlayer insulating film 38.
  • the housing portion 198 is a virtual region. In other words, the housing portion 198 may be formed integrally as a part of the interlayer insulating film 38.
  • the housing portion 198 may be a third interlayer insulating film 238 provided above the semiconductor substrate 10.
  • the housing portion 198 may be formed in the process of providing the third interlayer insulating film 238, and may be formed of the same material as the third interlayer insulating film 238. That is, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 238.
  • the polycrystalline portion 232 may be provided in a recess formed by etching the upper surface of the thick third interlayer insulating film 238.
  • the housing portion 198 may be polysilicon having a lower impurity concentration than the polycrystalline portion 232 or non-doped polysilicon.
  • the first outer periphery region contact portion 234 is provided with the bottom corner portion 2340 in contact with the polycrystalline portion 232 and the bottom surface in contact with the housing portion 198. This ensures electrical connection between the emitter electrode 52 and the polycrystalline portion 232. If the plug portion 2344 and the barrier metal film 2342 near the center of the bottom surface of the first outer periphery region contact portion 234 are removed by over-etching during the etch-back process of the plug portion 2344, there is a risk of voids being generated inside the first outer periphery region contact portion 234. Even in this case, electrical connection can be ensured by the barrier metal film 2342 and/or the plug portion 2344 remaining at the bottom corner portion 2340 of the first outer periphery region contact portion 234.
  • the first outer peripheral region contact portion 234 in this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the first outer peripheral region contact portion 234 near the center of the bottom surface, the effect on the electrical connection at the bottom corner portion 2340 between the first outer peripheral region contact portion 234 and the polycrystalline portion 232 is suppressed. This makes it possible to improve the yield of semiconductor devices 100 having desired characteristics.
  • the outer peripheral region 230 in this example ensures electrical connection between the first outer peripheral region contact portion 234 and the polycrystalline portion 232 through the bottom corner portion 2340 rather than the bottom center portion of the first outer peripheral region contact portion 234. This makes it possible to obtain stable quality and improve yield, even if a void is formed in the area near the center of the first outer peripheral region contact portion 234 that is in contact with the housing portion 198.
  • FIG. 13A shows an example of a cross section taken along line d-d' in FIG. 9.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 10B in that the peripheral region 230 has a housing portion 198, and differs from the embodiment of FIG. 12A in that the peripheral region 230 has a first peripheral region trench contact portion 2345. The rest may be the same as the embodiment of FIG. 10B and/or FIG. 12A.
  • FIG. 13B shows an example of an enlarged view of the d-d' cross section in FIG. 9. This figure shows the region in the peripheral region 230 above the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 12B in that the peripheral region 230 has a first peripheral region trench contact portion 2345.
  • the differences from the embodiment of FIG. 12B will be particularly described, and the rest may be the same as the embodiment of FIG. 12B.
  • the sidewall of the first outer periphery region contact portion 234 may be in contact with the polycrystalline portion 232 and the interlayer insulating film 38.
  • the polycrystalline portion 232 may be in contact with the sidewall of the first outer periphery region contact portion 234 from the bottom corner portion 2340 to an area of 10% or more and 90% or less of the sidewall of the first outer periphery region contact portion 234.
  • the ratio of the area of the sidewall of the first outer periphery region contact portion 234 that is in contact with the polycrystalline portion 232 to the area of the sidewall of the first outer periphery region contact portion 234 that is in contact with the polycrystalline portion 232 may be 10% or more and 90% or less.
  • length L3 is the length of the sidewall of the first outer peripheral region contact portion 234 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10
  • length L4 is the length of the sidewall of the first outer peripheral region contact portion 234 that contacts the polycrystalline portion 232 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less.
  • the polycrystalline portion 232 contacts the sidewall of the first outer peripheral region contact portion 234 from the bottom corner 2340 to 35% of the sidewall of the first outer peripheral region contact portion 234. That is, the ratio of length L4 to length L3 in this example is 35%.
  • FIG. 14A shows an example of the ee' cross section in FIG. 9.
  • the ee' cross section is a YZ plane passing through the contact hole 55 in the peripheral region 230.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, a gate metal layer 50, a collector electrode 24, and a first peripheral region contact portion 234.
  • the polycrystalline portion 232 is provided above the semiconductor substrate 10.
  • the polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10.
  • the polycrystalline portion 232 in this example is provided above the front surface 21 of the semiconductor substrate 10.
  • the polycrystalline portion 232 in this example is the connection portion 25.
  • the polycrystalline portion 232 may be provided above the third interlayer insulating film 238.
  • the third interlayer insulating film 238 may be, for example, the same material as the gate insulating film 42.
  • the interlayer insulating film 38 is provided above the polycrystalline portion 232.
  • the first outer peripheral region contact portion 234 is provided in the interlayer insulating film 38 above the polycrystalline portion 232.
  • the first outer peripheral region contact portion 234 may have a contact hole 55 and a metal layer filled inside the contact hole 55.
  • the polycrystalline portion 232 may be connected to the gate metal layer 50 via the first outer periphery region contact portion 234.
  • the polycrystalline portion 232 may be connected to the gate conductive portion 44.
  • the connection portion 25 in this example is connected to the gate metal layer 50 via the first outer periphery region contact portion 234, and is connected to the gate conductive portion 44.
  • the contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width Wt1 of the main region contact portion 224.
  • the sidewall of the first outer peripheral region contact portion 234 may be an interlayer insulating film 38 from the top end to the bottom end.
  • the contact width of the first outer periphery region contact portion 234 is larger than the contact width of the main region contact portion 224.
  • the semiconductor device 100 can be manufactured stably even when miniaturized, and stable characteristics can be obtained.
  • the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed by different processes.
  • FIG. 14B shows an example of the e-e' cross section in FIG. 9.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 14A in that the peripheral region 230 has a first peripheral region trench contact portion 2345.
  • the differences from the embodiment of FIG. 14A will be particularly described, and the rest may be the same as the embodiment of FIG. 14A.
  • the peripheral region 230 may have a first peripheral region trench contact portion 2345 extending from the upper surface of the interlayer insulating film 38 downward beyond the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10.
  • the first peripheral region trench contact portion 2345 is an example of the first peripheral region contact portion 234.
  • the first peripheral region trench contact portion 2345 is a portion that is deeper toward the rear surface 23 of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 232.
  • the polycrystalline portion 232 may be connected to the gate metal layer 50 via the first outer periphery region trench contact portion 2345.
  • the polycrystalline portion 232 may be connected to the gate conductive portion 44.
  • the connection portion 25 in this example is connected to the gate metal layer 50 via the first outer periphery region trench contact portion 2345 and is connected to the gate conductive portion 44.
  • the extension depth Do1 of the first outer periphery region trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 is shallower than the extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the extension depth Do1 of the first outer periphery region trench contact portion 2345 may be 0, and the extension depth Dt of the main region trench contact portion 2245 may be a value of 0 or more.
  • the extension depth Do1 of the first outer periphery region trench contact portion 2345 shallower than the extension depth Dt of the main region trench contact portion 2245, it is possible to prevent the first outer periphery region contact portion 234 from penetrating the polycrystalline portion 232 and extending the third interlayer insulating film 238, thereby preventing the insulation between the polycrystalline portion 232 and the semiconductor substrate 10 from being lost.
  • the main region trench contact portion 2245 extends deeper than the first outer periphery region trench contact portion 2345, the main region contact portion 224 is formed sufficiently deep in the contact region 15, thereby suppressing latch-up. In particular, in this example, insulation between the connection portion 25 and the well region 17 can be maintained.
  • the first outer periphery region trench contact portion 2345 and the main region trench contact portion 2245 can be formed in the same process. However, the first outer periphery region trench contact portion 2345 and the main region trench contact portion 2245 may be formed in different processes.
  • the contact width Wto1 where the first outer peripheral region trench contact portion 2345 contacts the polycrystalline portion 232 may be larger than, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245.
  • FIG. 15A shows an example of the ee' cross section in FIG. 9.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 14A in that the outer periphery region 230 has a recess region 236.
  • the differences from the embodiment of FIG. 14A will be particularly described, and the rest may be the same as the embodiment of FIG. 14A.
  • the contact width Wo1 of the first outer periphery region contact portion 234 may be larger than the contact width of the main region contact portion 224.
  • the peripheral region 230 may have a recess region 236 in which a depression is provided in the upper surface of the semiconductor substrate 10.
  • the polycrystalline portion 232 may be provided in the recess region 236.
  • the polycrystalline portion 232 is provided on the front surface 21 side of the semiconductor substrate 10.
  • the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 236.
  • the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed simultaneously by the same etching process.
  • the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 236 are at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure in the photolithography process. Therefore, the dimensional tolerances of the interlayer insulating film 38, the emitter electrode 52, the gate metal layer 50, etc. can be reduced.
  • the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed with the same dimensional tolerance. This allows for easier manufacturing with fewer steps compared to the case where each contact portion is formed in a separate process. However, if the contact width of the first outer periphery region contact portion 234 is made larger than the contact width of the main region contact portion 224, the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed in different processes.
  • FIG. 15B shows an example of the e-e' cross section in FIG. 9.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 14B in that the peripheral region 230 has a recess region 236, and differs from the embodiment of FIG. 15A in that the peripheral region 230 has a first peripheral region trench contact portion 2345.
  • the rest may be the same as the embodiment of FIG. 14B and/or FIG. 15A.
  • FIG. 16A shows an example of the ee' cross section in FIG. 9.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 14A in that the outer periphery region 230 has a housing portion 198.
  • the differences from the embodiment of FIG. 14A will be particularly described, and the rest may be the same as the embodiment of FIG. 14A.
  • the contact width Wo1 of the first outer periphery region contact portion 234 may be larger than the contact width of the main region contact portion 224.
  • the housing portion 198 is provided below the first outer peripheral region contact portion 234.
  • the material of the housing portion 198 may be the same as that of the interlayer insulating film 38.
  • FIG. 16B shows an example of an enlarged view of the ee' cross section in FIG. 9. This figure shows the area above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.
  • the bottom corner 2340 of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232.
  • the bottom corner 2340 is in contact with the polycrystalline portion 232 on the top surface of the polycrystalline portion 232.
  • the bottom surface of the first outer peripheral region contact portion 234 may be in contact with the housing portion 198.
  • the bottom surface of the first outer peripheral region contact portion 234 is in contact with the upper surface of the housing portion 198.
  • the bottom surface of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232 and the housing portion 198.
  • one bottom corner portion 2340a of the first outer peripheral region contact portion 234 is in contact with the polycrystalline portion 232
  • the other bottom corner portion 2340b is in contact with the housing portion 198, so that the bottom surface of the first outer peripheral region contact portion 234 is in contact with the polycrystalline portion 232 and the housing portion 198.
  • the polycrystalline portion 232 may contact the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340 to an area of 10% to 40% of the bottom surface of the first outer peripheral region contact portion 234.
  • the polycrystalline portion 232 contacts the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340a to an area of 20% of the bottom surface of the first outer peripheral region contact portion 234.
  • the ratio of length L2 to length L1 in this example is 20%.
  • the barrier metal film 2342 may be provided on the bottom corners 2340 of the first outer periphery region contact portion 234. In this example, the barrier metal film 2342 is provided over the entire side and bottom surface of the first outer periphery region contact portion 234, but is not limited to this. The barrier metal film 2342 may be provided to cover at least the bottom corners 2340, or may be provided without covering the center portion of the bottom surface of the first outer periphery region contact portion 234. The barrier metal film 2342 may extend beyond the contact hole 55 and extend above the interlayer insulating film 38.
  • the material of the barrier metal film 2342 may be titanium or a titanium compound, etc.
  • the plug portion 2344 may be provided in contact with the inner side of the barrier metal film 2342.
  • the plug portion 2344 is provided by filling the first outer periphery region contact portion 234, but is not limited to this.
  • the plug portion 2344 may be provided in a part of the first outer periphery region contact portion 234, and may extend beyond the contact hole 55 and be provided above the interlayer insulating film 38.
  • the plug portion 2344 is provided in a part of the first outer periphery region contact portion 234, the remaining area of the first outer periphery region contact portion 234 may be filled with the same material as the gate metal layer 50.
  • the material of the plug portion 2344 may be a plug metal such as tungsten.
  • the side of the polycrystalline portion 232 may be in contact with the side of the housing portion 198.
  • the housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the first outer peripheral region contact portion 234.
  • the housing portion 198 may be formed in the process of providing the interlayer insulating film 38, and may be formed of the same material as the interlayer insulating film 38.
  • the housing portion 198 is a virtual region. In other words, the housing portion 198 may be formed integrally as a part of the interlayer insulating film 38.
  • the housing portion 198 may be a third interlayer insulating film 238 provided above the semiconductor substrate 10.
  • the housing portion 198 may be formed in the process of providing the third interlayer insulating film 238, and may be formed of the same material as the third interlayer insulating film 238. That is, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 238.
  • the housing portion 198 may be polysilicon having a lower impurity concentration than the polycrystalline portion 232 or non-doped polysilicon.
  • the first outer periphery region contact portion 234 is provided with the bottom corner portion 2340 in contact with the polycrystalline portion 232 and the bottom surface in contact with the housing portion 198. This ensures electrical connection between the gate metal layer 50 and the polycrystalline portion 232. If the plug portion 2344 and the barrier metal film 2342 near the center of the bottom surface of the first outer periphery region contact portion 234 are removed by over-etching during the etch-back process of the plug portion 2344, there is a risk of voids being generated inside the first outer periphery region contact portion 234. Even in this case, the electrical connection can be ensured by the barrier metal film 2342 and/or the plug portion 2344 remaining at the bottom corner portion 2340 of the first outer periphery region contact portion 234.
  • the first outer peripheral region contact portion 234 in this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the first outer peripheral region contact portion 234 near the center of the bottom surface, the effect on the electrical connection at the bottom corner portion 2340 between the first outer peripheral region contact portion 234 and the polycrystalline portion 232 is suppressed. This makes it possible to improve the yield of semiconductor devices 100 having desired characteristics.
  • the outer peripheral region 230 in this example ensures electrical connection between the first outer peripheral region contact portion 234 and the polycrystalline portion 232 through the bottom corner portion 2340 rather than the bottom center portion of the first outer peripheral region contact portion 234. This makes it possible to obtain stable quality and improve yield, even if a void is formed in the area near the center of the first outer peripheral region contact portion 234 that is in contact with the housing portion 198.
  • FIG. 17A shows an example of the e-e' cross section in FIG. 9.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 14B in that the outer periphery region 230 has a housing portion 198, and differs from the embodiment of FIG. 16A in that the first outer periphery region 230 has a first outer periphery region trench contact portion 2345.
  • the rest may be the same as the embodiment of FIG. 14B and/or FIG. 16A.
  • FIG. 17B shows an example of an enlarged view of the e-e' cross section in FIG. 9. This figure shows the region in the peripheral region 230 above the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 16B in that the peripheral region 230 has a first peripheral region trench contact portion 2345.
  • the differences from the embodiment of FIG. 16B will be particularly described, and the rest may be the same as the embodiment of FIG. 16B.
  • the sidewall of the first outer periphery region contact portion 234 may be in contact with the polycrystalline portion 232 and the interlayer insulating film 38.
  • the polycrystalline portion 232 may be in contact with the sidewall of the first outer periphery region contact portion 234 from the bottom corner 2340 to an area of 10% to 90% of the sidewall of the first outer periphery region contact portion 234.
  • the polycrystalline portion 232 is in contact with the sidewall of the first outer periphery region contact portion 234 from the bottom corner 2340 to an area of 35% of the sidewall of the first outer periphery region contact portion 234. That is, the ratio of length L4 to length L3 in this example is 35%.
  • FIG. 18A shows an example of a top view of the semiconductor device 100.
  • the semiconductor device 100 of this example includes a guard ring 142 in the edge termination structure 140.
  • the semiconductor device 100 may include multiple guard rings 142.
  • the guard ring 142 is a region of a second conductivity type provided between the active portion 120 and the edge 102 of the semiconductor substrate 10 on the front surface 21 of the semiconductor substrate 10.
  • the guard ring 142 is, for example, a P+ type.
  • the guard ring 142 may surround the active portion 120 in a top view.
  • the guard ring 142 arranged on the outside may surround the guard ring 142 arranged on the inside.
  • the outside refers to the side closer to the edge 102, and the inside refers to the side closer to the center in a top view of the semiconductor substrate 10.
  • the semiconductor device 100 may further include at least one of a field plate or a resurf provided to surround the active portion 120 in the edge termination structure 140.
  • semiconductor device 100 includes guard ring 142 and field plate 144 in edge termination structure 140.
  • Edge termination structure 140 is an example of peripheral region 230.
  • Semiconductor device 100 may include interlayer insulating film 38, edge metal layer 146, and field insulating film 148 in edge termination structure 140. Interlayer insulating film 38, edge metal layer 146, and field insulating film 148 are omitted in FIG. 13B. Contact holes 57 and 59 are provided through interlayer insulating film 38.
  • the field plate 144 is a conductive member provided above the semiconductor substrate 10.
  • the field plate 144 is formed of polysilicon doped with impurities.
  • the field plate 144 is an example of a polycrystalline portion 232.
  • the field plate 144 is provided above the guard ring 142.
  • the field plate 144 may be electrically connected to the corresponding guard ring 142.
  • the guard ring 142 has a non-corner region 1420 and a corner region 1422.
  • the non-corner region 1420 is, for example, a region of the guard ring 142 that extends along the edge 102 of the semiconductor substrate 10
  • the corner region 1422 is, for example, a portion that connects the regions of the guard ring 142 that extend along the edge 102 of the semiconductor substrate 10.
  • the contact hole 57 connects the edge metal layer 146 and the field plate 144. Inside the contact hole 57, a barrier metal film made of titanium or a titanium compound and/or a plug portion made of tungsten may be formed.
  • the contact hole 59 connects the edge metal layer 146 and the guard ring 142. Inside the contact hole 59, a barrier metal film made of titanium or a titanium compound and/or a plug portion made of tungsten may be formed.
  • the contact holes 57 and 59 may be provided above the corner region 1422 of the guard ring 142. However, at least one of the contact holes 57 and 59 may be provided above the non-corner region 1420 of the guard ring 142, and both the contact holes 57 and 59 may be provided above the non-corner region 1420 of the guard ring 142.
  • contact holes 57 and contact holes 59 have their length in the direction in which guard ring 142 and field plate 144 extend, and are arranged side by side from the center to edge 102.
  • contact holes 57 and contact holes 59 may be arranged in the direction in which guard ring 142 and field plate 144 extend, the length of each contact hole may be from the center to edge 102, and each contact hole may consist of multiple holes.
  • FIG. 19A shows an example of the f-f' cross section in FIG. 18B.
  • the f-f' cross section is a plane parallel to the Z-axis direction passing through contact holes 57 and 59 in the peripheral region 230.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, a field insulating film 148, an edge metal layer 146, a collector electrode 24, a first peripheral region contact portion 234, and a second peripheral region contact portion 235.
  • the field insulating film 148 is provided above the semiconductor substrate 10.
  • the field insulating film 148 may be provided to cover the drift region 18 exposed on the front surface 21 of the semiconductor substrate 10 between the well region 17 and the guard ring 142, and between the guard rings 142.
  • the field insulating film 148 may be provided to surround the main region 220 along the guard ring 142.
  • the edge metal layer 146 is provided above the semiconductor substrate 10 and is electrically connected to the guard ring 142.
  • the edge metal layer 146 is provided above the semiconductor substrate 10 with the interlayer insulating film 38 sandwiched therebetween.
  • the edge metal layer 146 may be electrically connected to the field plate 144.
  • the edge metal layer 146 may be electrically floating. For example, when a voltage V is applied to the collector electrode 24 with the gate of the semiconductor device 100 in an off state, a predetermined voltage lower than the voltage V may be applied to the edge metal layer 146.
  • the edge metal layer 146 is formed of a material containing a metal. At least a portion of the edge metal layer 146 may be formed of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu).
  • the edge metal layer 146 may have a barrier metal film formed of titanium or a titanium compound under the region formed of aluminum or the like.
  • the polycrystalline portion 232 is provided above the semiconductor substrate 10.
  • the polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10.
  • the polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10.
  • the polycrystalline portion 232 is a field plate 144.
  • the polycrystalline portion 232 may be provided above the third interlayer insulating film 238.
  • the third interlayer insulating film 238 may be, for example, the same material as the gate insulating film 42 and/or the dummy insulating film 32.
  • the third interlayer insulating film 238 may be, for example, a thermal oxide film.
  • the interlayer insulating film 38 is provided above the polycrystalline portion 232.
  • the first outer periphery region contact portion 234 is provided in the interlayer insulating film 38 above the polycrystalline portion 232.
  • the first outer periphery region contact portion 234 may have a contact hole 57 and a metal layer filled inside the contact hole 57.
  • the second outer periphery region contact portion 235 is provided in the interlayer insulating film 38 in a region where the polycrystalline portion 232 is not provided.
  • the second outer periphery region contact portion 235 may have a contact hole 59 and a metal layer filled inside the contact hole 59.
  • the second outer periphery region contact portion 235 may include a barrier metal film 2352 and a plug portion 2354.
  • the polycrystalline portion 232 may be connected to the edge metal layer 146 via the first outer periphery region contact portion 234.
  • the field plate 144 in this example is connected to the edge metal layer 146 via the first outer periphery region contact portion 234.
  • the semiconductor substrate 10 may be connected to the edge metal layer 146 via the second outer periphery region contact portion 235.
  • the guard ring 142 in this example is connected to the edge metal layer 146 via the second outer periphery region contact portion 235.
  • FIG. 19B shows an example of the f-f' cross section in FIG. 18B.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 19A in that the peripheral region 230 has a first peripheral region trench contact portion 2345 and a second peripheral region trench contact portion 2355.
  • the differences from the embodiment of FIG. 19A will be particularly described, and the rest may be the same as the embodiment of FIG. 19A.
  • the peripheral region 230 may have a first peripheral region trench contact portion 2345 extending downward from the upper surface of the interlayer insulating film 38 to the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10.
  • the first peripheral region trench contact portion 2345 is an example of the first peripheral region contact portion 234.
  • the first peripheral region trench contact portion 2345 is a portion deeper on the back surface 23 side of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 232.
  • the peripheral region 230 may have a second peripheral region trench contact portion 2355 extending downward from the upper surface of the interlayer insulating film 38 to the upper surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the second peripheral region trench contact portion 2355 is an example of the second peripheral region contact portion 235.
  • the second peripheral region trench contact portion 2355 is a portion deeper on the back surface 23 side of the semiconductor substrate 10 than the upper surface of the semiconductor substrate 10.
  • the polycrystalline portion 232 may be connected to the edge metal layer 146 via the first outer periphery region trench contact portion 2345.
  • the field plate 144 in this example is connected to the edge metal layer 146 via the first outer periphery region trench contact portion 2345.
  • the semiconductor substrate 10 may be connected to the edge metal layer 146 via the second outer periphery region trench contact portion 2355.
  • the guard ring 142 in this example is connected to the edge metal layer 146 via the second outer periphery region trench contact portion 2355.
  • the extension depth Do1 of the first outer periphery region trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 is shallower than the extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the extension depth Do1 of the first outer periphery region trench contact portion 2345 may be 0, and the extension depth Dt of the main region trench contact portion 2245 may be a value of 0 or more.
  • the main region trench contact portion 2245 extends deeper than the first outer periphery region trench contact portion 2345, latch-up can be suppressed by forming the main region contact portion 224 sufficiently deep in the contact region 15.
  • the first outer periphery region trench contact portion 2345 and the main region trench contact portion 2245 can be formed in the same process. However, the first outer periphery region trench contact portion 2345 and the main region trench contact portion 2245 may be formed in different processes.
  • the extension depth Do1 of the first outer peripheral region trench contact portion 2345 and the extension depth Do2 of the second outer peripheral region trench contact portion 2355 may both be shallower than the extension depth Dt of the main region trench contact portion 2245. That is, the extension depth Do1 of the first outer peripheral region trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 and the extension depth Do2 of the second outer peripheral region trench contact portion 2355 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10 may be shallower than the extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 can be formed in the same process.
  • the mask aperture ratio in the process of forming the main region trench contact portion 2245 differs from the mask aperture ratio in the process of forming the first outer periphery region trench contact portion 2345, so that the shapes of the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 may differ from the design.
  • the mask aperture ratio in the process of forming the main region trench contact portion 2245 is similar to the mask aperture ratio in the process of forming the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355, and the first outer periphery region trench contact portion 2345 is formed in the designed shape.
  • the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 may be formed in different processes.
  • the contact width Wto1 where the first outer periphery region trench contact portion 2345 contacts the polycrystalline portion 232 may be larger than, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245.
  • the contact width Wto2 where the second outer periphery region trench contact portion 2355 contacts the front surface 21 of the semiconductor substrate 10 may be larger than, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245.
  • FIG. 19C shows an example of the f-f' cross section in FIG. 18B.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 19B in that the extension depths of the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 are different.
  • the differences from the embodiment of FIG. 19B will be particularly described, and the rest may be the same as the embodiment of FIG. 19B.
  • the extension depth Do1 to which the first outer periphery region trench contact portion 2345 extends from the top surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 may be shallower than the extension depth Do2 to which the second outer periphery region trench contact portion 2355 extends from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 may be formed in different processes, and the second outer periphery region trench contact portion 2355 and the main region trench contact portion 2245 may be formed in the same process.
  • the height position of the upper surface of the interlayer insulating film 38 in the main region 220 is approximately the same as the height position of the upper surface of the interlayer insulating film 38 in the portion where the second peripheral region trench contact portion 2355 is provided.
  • the main region trench contact portion 2245 and the second peripheral region trench contact portion 2355 can be formed with the same dimensional tolerances.
  • FIG. 20A shows an example of the f-f' cross section in FIG. 18B.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 19A in that the peripheral region 230 has a recess region 236.
  • the differences from the embodiment of FIG. 19A will be particularly described, and the rest may be the same as the embodiment of FIG. 19A.
  • the contact width Wo1 of the first peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.
  • the peripheral region 230 may have a recess region 236 in which a depression is provided in the upper surface of the semiconductor substrate 10.
  • the polycrystalline portion 232 may be provided in the recess region 236.
  • the polycrystalline portion 232 is provided on the front surface 21 side of the semiconductor substrate 10.
  • the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 236.
  • the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed simultaneously by the same etching process.
  • the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 236 are at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure in the photolithography process. Therefore, the dimensional tolerances of the interlayer insulating film 38, the emitter electrode 52, the edge metal layer 146, etc. can be reduced.
  • the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed with the same dimensional tolerance. This allows for easier manufacturing with fewer processes compared to the case where each contact portion is formed in a separate process. However, if the contact width of the first outer periphery region contact portion 234 is made larger than the contact width of the main region contact portion 224, the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed in different processes.
  • FIG. 20B shows an example of the f-f' cross section in FIG. 18B.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 19B in that the peripheral region 230 has a recess region 236, and differs from the embodiment of FIG. 20A in that the peripheral region 230 has a first peripheral region trench contact portion 2345 and a second peripheral region trench contact portion 2355. The rest may be the same as the embodiment of FIG. 19B and/or FIG. 20A.
  • the height position of the upper surface of the interlayer insulating film 38 in the main region 220, the height position of the upper surface of the interlayer insulating film 38 in the recess region 236, and the height position of the upper surface of the interlayer insulating film 38 in the portion where the second outer periphery region trench contact portion 2355 is provided are approximately the same. Therefore, the main region trench contact portion 2245, the first outer periphery region trench contact portion 2345, and the second outer periphery region trench contact portion 2355 can be formed simultaneously by the same etching process. This allows for easy manufacturing with fewer processes compared to when each contact portion is formed in a separate process. However, each contact portion may be formed in a different process.
  • FIG. 21A shows an example of the f-f' cross section in FIG. 18B.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 19A in that the outer periphery region 230 has a housing portion 198.
  • the differences from the embodiment of FIG. 19A will be particularly described, and the rest may be the same as the embodiment of FIG. 19A.
  • the contact width Wo1 of the first outer periphery region contact portion 234 may be larger than the contact width of the main region contact portion 224.
  • the housing portion 198 is provided below the first outer peripheral region contact portion 234.
  • the material of the housing portion 198 may be the same as or different from the interlayer insulating film 38.
  • FIG. 21B shows an example of an enlarged view of the ff' cross section in FIG. 18B. This figure shows the area above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.
  • the bottom corner 2340 of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232.
  • the bottom corner 2340 is in contact with the polycrystalline portion 232 on the top surface of the polycrystalline portion 232.
  • the bottom surface of the first outer peripheral region contact portion 234 may be in contact with the housing portion 198.
  • the bottom surface of the first outer peripheral region contact portion 234 is in contact with the upper surface of the housing portion 198.
  • the bottom surface of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232 and the housing portion 198.
  • one bottom corner portion 2340a of the first outer peripheral region contact portion 234 is in contact with the polycrystalline portion 232
  • the other bottom corner portion 2340b is in contact with the housing portion 198, so that the bottom surface of the first outer peripheral region contact portion 234 is in contact with the polycrystalline portion 232 and the housing portion 198.
  • the polycrystalline portion 232 may contact the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340 to an area of 10% to 40% of the bottom surface of the first outer peripheral region contact portion 234.
  • the polycrystalline portion 232 contacts the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340a to an area of 20% of the bottom surface of the first outer peripheral region contact portion 234.
  • the ratio of length L2 to length L1 in this example is 20%.
  • the barrier metal film 2342 may be provided on the bottom corners 2340 of the first outer periphery region contact portion 234. In this example, the barrier metal film 2342 is provided over the entire side and bottom surface of the first outer periphery region contact portion 234, but is not limited to this. The barrier metal film 2342 may be provided to cover at least the bottom corners 2340, or may be provided without covering the center portion of the bottom surface of the first outer periphery region contact portion 234. The barrier metal film 2342 may extend beyond the contact hole 57 and extend above the interlayer insulating film 38.
  • the material of the barrier metal film 2342 may be titanium or a titanium compound, etc.
  • the plug portion 2344 may be provided in contact with the inner side of the barrier metal film 2342.
  • the plug portion 2344 is provided by filling the first outer periphery region contact portion 234, but is not limited to this.
  • the plug portion 2344 may be provided in a part of the first outer periphery region contact portion 234, and may extend beyond the contact hole 57 and be provided above the interlayer insulating film 38.
  • the remaining area of the first outer periphery region contact portion 234 may be filled with the same material as the edge metal layer 146.
  • the material of the plug portion 2344 may be a plug metal such as tungsten.
  • the side of the polycrystalline portion 232 may be in contact with the side of the housing portion 198.
  • the housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the first outer peripheral region contact portion 234.
  • the housing portion 198 may be formed in the process of providing the interlayer insulating film 38, and may be formed of the same material as the interlayer insulating film 38.
  • the housing portion 198 is a virtual region. In other words, the housing portion 198 may be formed integrally as a part of the interlayer insulating film 38.
  • the housing portion 198 may be a third interlayer insulating film 238 provided above the semiconductor substrate 10.
  • the housing portion 198 may be formed in the process of providing the third interlayer insulating film 238, and may be formed of the same material as the third interlayer insulating film 238. That is, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 238.
  • the first outer periphery region contact portion 234 is provided with the bottom corner portion 2340 in contact with the polycrystalline portion 232 and the bottom surface in contact with the housing portion 198. This ensures electrical connection between the edge metal layer 146 and the polycrystalline portion 232. If the plug portion 2344 and the barrier metal film 2342 near the center of the bottom surface of the first outer periphery region contact portion 234 are removed by over-etching during the etch-back process of the plug portion 2344, there is a risk of voids being generated inside the first outer periphery region contact portion 234. Even in this case, electrical connection can be ensured by the barrier metal film 2342 and/or the plug portion 2344 remaining at the bottom corner portion 2340 of the first outer periphery region contact portion 234.
  • the first outer peripheral region contact portion 234 in this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the first outer peripheral region contact portion 234 near the center of the bottom surface, the effect on the electrical connection at the bottom corner portion 2340 between the first outer peripheral region contact portion 234 and the polycrystalline portion 232 is suppressed. This makes it possible to improve the yield of semiconductor devices 100 having desired characteristics.
  • the outer peripheral region 230 in this example ensures electrical connection between the first outer peripheral region contact portion 234 and the polycrystalline portion 232 through the bottom corner portion 2340 rather than the bottom center portion of the first outer peripheral region contact portion 234. This makes it possible to obtain stable quality and improve yield, even if a void is formed in the area near the center of the first outer peripheral region contact portion 234 that is in contact with the housing portion 198.
  • FIG. 21C shows an example of an enlarged view of the f-f' cross section in FIG. 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the first outer periphery region 230.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 21B in that the housing portion 198 is a region of the field insulating film 148 that is provided below the first outer periphery region contact portion 234. The rest may be the same as the embodiment of FIG. 21B.
  • FIG. 21D shows an example of an enlarged view of the f-f' cross section in FIG. 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the first outer peripheral region 230.
  • the semiconductor device 100 of this example differs from the embodiment of FIGS. 21B and 21C in that a housing portion 198 is provided in addition to the interlayer insulating film 38 and the field insulating film 148.
  • the differences from the embodiment of FIGS. 21B and 21C will be particularly described, and the rest may be the same as the embodiment of FIGS. 21B and/or 21C.
  • the housing portion 198 may have polysilicon with a lower impurity concentration than the contact region 300 of the polycrystalline portion 232.
  • the contact region 300 of the polycrystalline portion 232 may be the region of the polycrystalline portion 232 with which the housing portion 198 is in contact.
  • the housing portion 198 has polysilicon with a lower impurity concentration than the polycrystalline portion 232 or undoped polysilicon.
  • FIG. 22A shows an example of a cross section taken along the line f-f' in FIG. 18B.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 19B in that the peripheral region 230 has a housing portion 198, and differs from the embodiment of FIG. 21A in that the peripheral region 230 has a first peripheral region trench contact portion 2345 and a second peripheral region trench contact portion 2355. The rest may be the same as the embodiment of FIG. 19B and/or FIG. 21A.
  • FIG. 22B shows an example of the f-f' cross section in FIG. 18B.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 19C in that the peripheral region 230 has a housing portion 198, and differs from the embodiment of FIG. 22A in that the extension depths of the first peripheral region trench contact portion 2345 and the second peripheral region trench contact portion 2355 are different. The rest may be the same as the embodiment of FIG. 19C and/or FIG. 22A.
  • FIG. 22C shows an example of an enlarged view of the f-f' cross section in FIG. 18B.
  • This figure shows the region in the peripheral region 230 above the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 21B in that the peripheral region 230 has a first peripheral region trench contact portion 2345.
  • the differences from the embodiment of FIG. 21B will be particularly described, and the rest may be the same as the embodiment of FIG. 21B.
  • the sidewall of the first outer periphery region contact portion 234 may be in contact with the polycrystalline portion 232 and the interlayer insulating film 38.
  • the polycrystalline portion 232 may be in contact with the sidewall of the first outer periphery region contact portion 234 from the bottom corner 2340 to an area of 10% to 90% of the sidewall of the first outer periphery region contact portion 234.
  • the polycrystalline portion 232 is in contact with the sidewall of the first outer periphery region contact portion 234 from the bottom corner 2340 to an area of 35% of the sidewall of the first outer periphery region contact portion 234. That is, the ratio of length L4 to length L3 in this example is 35%.
  • FIG. 22D shows an example of an enlarged view of the f-f' cross section in FIG. 18B.
  • This figure shows the region in the peripheral region 230 above the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 21C in that the peripheral region 230 has a first peripheral region trench contact portion 2345, and differs from the embodiment of FIG. 22C in that the housing portion 198 is a region of the field insulating film 148 that is provided below the first peripheral region contact portion 234. The rest may be the same as the embodiment of FIG. 21C and/or FIG. 22C.
  • FIG. 22E shows an example of an enlarged view of the f-f' cross section in FIG. 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 21D in that the peripheral region 230 has a first peripheral region trench contact portion 2345, and differs from the embodiments of FIG. 22C and FIG. 22D in that a housing portion 198 is provided separately from the interlayer insulating film 38 and the field insulating film 148. The rest may be the same as the embodiments of FIG. 21D, FIG. 22C and/or FIG. 22D.
  • FIG. 23A shows an example of the f-f' cross section in FIG. 18B.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 21A in that the first outer periphery region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148. The rest may be the same as the embodiment of FIG. 21A.
  • FIG. 23B shows an example of an enlarged view of the f-f' cross section in FIG. 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 21B in that the first peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148. The rest may be the same as the embodiment of FIG. 21B.
  • FIG. 23C shows an example of an enlarged view of the f-f' cross section in FIG. 18B.
  • This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 21D in that the first peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment of FIG. 23B in that a housing portion 198 is provided separately from the interlayer insulating film 38. The rest may be the same as the embodiment of FIG. 21D and/or FIG. 23B.
  • FIG. 24A shows an example of the f-f' cross section in FIG. 18B.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 22A in that the first peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment of FIG. 23A in that the peripheral region 230 has a first peripheral region trench contact portion 2345 and a second peripheral region trench contact portion 2355. The rest may be the same as the embodiment of FIG. 22A and/or FIG. 23A.
  • FIG. 24B shows an example of the f-f' cross section in FIG. 18B.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 22B in that the first outer periphery region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment of FIG. 24A in that the extension depths of the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 are different.
  • the rest may be the same as the embodiment of FIG. 22B and/or FIG. 24A.
  • FIG. 24C shows an example of an enlarged view of the f-f' cross section in FIG. 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 22C in that the first peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment of FIG. 23B in that the peripheral region 230 has a first peripheral region trench contact portion 2345. The rest may be the same as the embodiment of FIG. 22C and/or FIG. 23B.
  • FIG. 24D shows an example of an enlarged view of the f-f' cross section in FIG. 18B.
  • This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 22E in that the first peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment of FIG. 23C in that the peripheral region 230 has a first peripheral region trench contact portion 2345. The rest may be the same as the embodiment of FIG. 22E and/or FIG. 23C.
  • FIG. 25 shows an example of the g-g' cross section in FIG. 18A.
  • the g-g' cross section is an XZ plane passing through the contact hole 53 near the gate pad 112.
  • the gate pad 112 is provided in the pad region 330.
  • the pad region 330 is separated from the main region 220 by a well region 17 or the like, and has each pad.
  • the pad region 330 may be disposed near the edge 102 of the semiconductor substrate 10.
  • the vicinity of the edge 102 refers to the region between the edge 102 in a top view and the emitter electrode 52.
  • the pad region 330 may be provided in a region between the emitter electrode 52 divided into multiple parts.
  • each pad may be connected to an external circuit via wiring such as a wire.
  • the gate pad 112 is an example of a pad.
  • the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, a pad electrode 51, a collector electrode 24, and a pad region contact portion 334 in the gg' cross section.
  • the polycrystalline portion 332 is provided above the semiconductor substrate 10.
  • the polycrystalline portion 332 is provided above the front surface 21 of the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10.
  • the polycrystalline portion 332 in this example is provided above the front surface 21 of the semiconductor substrate 10.
  • the polycrystalline portion 332 in this example is the pad connection portion 125.
  • the polycrystalline portion 332 may be provided above the pad region insulating film 338.
  • the pad region insulating film 338 may be, for example, the same material as the gate insulating film 42.
  • the pad region insulating film 338 may be a thermal oxide film.
  • the interlayer insulating film 38 is provided above the polycrystalline portion 332.
  • the pad region contact portion 334 is provided in the interlayer insulating film 38 above the polycrystalline portion 332.
  • the pad region contact portion 334 may have a contact hole 53 and a metal layer filled inside the contact hole 53. The detailed configuration of the pad region contact portion 334 will be described later.
  • the polycrystalline portion 332 may be connected to the pad electrode 51 via the pad region contact portion 334.
  • the pad connection portion 125 is connected to the pad electrode 51 via the pad region contact portion 334.
  • the pad region contact portion 334 may include a barrier metal film 3342 provided in the contact hole 53 and a plug portion 3344.
  • the barrier metal film 3342 of the pad region contact portion 334 may include titanium or a titanium compound, etc.
  • the plug portion 3344 of the pad region contact portion 334 may include a plug metal such as tungsten.
  • the barrier metal film 3342 in this example is provided above the interlayer insulating film 38 and is in contact with the pad electrode 51.
  • a barrier metal film 2242, a barrier metal film 2342, and/or a barrier metal film 1882 may also be provided above the interlayer insulating film 38.
  • the plug portion 3344 in this example is provided inside the contact hole 53.
  • the plug portion 3344 may be provided above the barrier metal film 3342 outside the contact hole 53 and in contact with the pad electrode 51, and the plug portion 2244, the plug portion 2344, and/or the plug portion 1884 may be provided above the barrier metal film 2242, the barrier metal film 2342, and/or the barrier metal film 1882 outside the contact hole 54, the contact hole 55, the contact hole 56, the contact hole 57, the contact hole 58, and/or the contact hole 59 in the main region 220, the peripheral region 230, and/or the temperature sensing portion 180.
  • the barrier metal film 3342 may not be provided above the interlayer insulating film 38, but may be provided only inside the contact hole 53.
  • the pad connection portion 125 may be made of the same polycrystal as the gate conductive portion 44 and the dummy conductive portion 34.
  • the pad connection portion 125 may be made of polycrystal formed at the same time as the polycrystal constituting the temperature sensing diode 183, and may be made conductive by ion implantation or the like as necessary, and the pad region insulating film 338 below the polycrystal portion 332 may have the same configuration as the second interlayer insulating film 37 of the temperature sensing portion 180, not the same configuration as the gate insulating film 42.
  • the pad connection portion 125 may not be electrically connected to anything other than the pad electrode 51.
  • the respective pad connection portions 125 may be connected to each other at a location different from the cross section of FIG. 25, or may not be connected.
  • the pad electrode 51 may be directly connected to the gate metal layer 50.
  • the pad connection portion 125 may not be conductive.
  • the pad connection portion 125 may be electrically connected to anything other than the pad electrode 51.
  • the respective pad connection portions 125 may be connected at a location different from the cross section of FIG. 25.
  • the pad connection portion 125 may be connected to the connection portion 25.
  • the pad electrode 51 may not be directly connected to the gate metal layer 50 but may be connected via the pad connection portion 125.
  • the pad connection portion 125 may be conductive and connected to the gate metal layer 50 outside the gate pad 112 in a top view, and may be connected to the gate metal layer 50 in a manner similar to the connection to the pad electrode 51.
  • the barrier metal film 3342 may be provided up to the end of the pad electrode 51.
  • the pad electrode 51 may be provided wider than the end of the pad connection portion 125. In another example, the pad electrode 51 does not have to be provided up to the end of the pad connection portion 125.
  • the pad region 330 may have a pad region trench contact portion 3345 extending from the upper surface of the interlayer insulating film 38 downward beyond the upper surface of the polycrystalline portion 332 in the depth direction of the semiconductor substrate 10.
  • the pad region trench contact portion 3345 is an example of a pad region contact portion 334.
  • the pad region trench contact portion 3345 is a portion that is deeper toward the rear surface 23 of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 332.
  • the polycrystalline portion 332 may be connected to the pad electrode 51 via the pad region trench contact portion 3345.
  • the pad connection portion 125 is connected to the pad electrode 51 via the pad region trench contact portion 3345.
  • the main region 220 may have a main region trench contact portion 2245 extending from the upper surface of the interlayer insulating film 38 downward below the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. This figure is a cross-sectional view of the pad region 330, so the main region trench contact portion 2245 is not shown.
  • the main region trench contact portion 2245 is, for example, the active trench contact portion 1245 shown in FIG. 4C.
  • the main region trench contact portion 2245 is an example of the main region contact portion 224.
  • the main region trench contact portion 2245 is a portion that is deeper on the back surface 23 side than the front surface 21 of the semiconductor substrate 10.
  • the main region 220 may have a plurality of main region trench contact portions 2245 provided on the front surface 21 of the semiconductor substrate 10.
  • the extension depth Dp of the pad region trench contact portion 3345 extending from the upper surface of the polycrystalline portion 332 in the depth direction of the semiconductor substrate 10 is shallower than the extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • main region trench contact portion 2245 extends deeper than the pad region trench contact portion 3345, latch-up can be suppressed by forming the main region contact portion 224 sufficiently deep in the contact region 15.
  • the pad region trench contact portion 3345 and the main region trench contact portion 2245 may be formed in the same process. However, the pad region trench contact portion 3345 and the main region trench contact portion 2245 may be formed in different processes.
  • the contact width Wtp at which the pad region trench contact portion 3345 contacts the polycrystalline portion 332 may be larger than, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245.
  • the contact width Wtp of the pad region trench contact portion 3345 may be the width at which the pad region trench contact portion 3345 contacts the upper surface of the polycrystalline portion 332.
  • the contact width Wtt1 of the main region trench contact portion 2245 may be the width at which the active trench contact portion 1245 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10, as shown in FIG. 4C.
  • the extension depth Dp of the pad region trench contact portion 3345 may be substantially zero.
  • the pad region contact portion 334 may not extend to the pad connection portion 125, and the main region trench contact portion 2245 may extend to a depth Dt.
  • the configuration described for the gate pad 112 may also be applied to other pads.
  • it may be used for the anode pad 116, the cathode pad 118, the sense electrode 114, and/or any pad not shown in FIG. 18A.
  • the pad electrode 51 may be in direct contact with the anode wiring portion 117 or the cathode wiring portion 119, etc., or may be indirectly connected via the polycrystalline portion 332.
  • the pad region contact portion 334 may extend from the upper surface of the pad region insulating film 338 in the depth direction of the semiconductor substrate 10, and the thickness T of the pad region insulating film 338 below the pad region contact portion 334 may be thin, or the pad region contact portion 334 may penetrate the pad region insulating film 338 to reach the semiconductor substrate 10.
  • the longitudinal direction of the contact hole 53 does not have to be the Y-axis direction.
  • the longitudinal direction of the contact hole 53 may be the X-axis direction or any other direction, and contact holes 53 with different orientations may be used in combination.
  • FIG. 26 shows an example of the gg' cross section in FIG. 18A.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 25 in that the pad region 330 has a recess region 336.
  • the differences from the embodiment of FIG. 25 will be particularly described, and the rest may be the same as the embodiment of FIG. 25.
  • the contact depth Dp of the pad region contact portion 334 may be shallower than the contact depth of the main region contact portion 224.
  • the pad region 330 may have a recess region 336 in which a depression is provided on the upper surface of the semiconductor substrate 10.
  • the polycrystalline portion 332 may be provided in the recess region 336.
  • the polycrystalline portion 332 is provided on the front surface 21 side of the semiconductor substrate 10.
  • the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 336.
  • the height position being the same may include the height position being approximately (substantially) the same.
  • the height position being approximately (substantially) the same may mean that the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the main region 220 and the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the recess region 336 are within 20% of the average value of both, or may be within 10% of the average value.
  • the main region contact portion 224 and the pad region contact portion 334 can be formed simultaneously by the same etching process.
  • the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 336 are at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure in the photolithography process. This makes it possible to reduce the dimensional tolerance of the interlayer insulating film 38, the emitter electrode 52, etc.
  • main region contact portion 224 and the pad region contact portion 334 can be formed with the same dimensional tolerance. This allows for easier manufacturing with fewer processes compared to when each contact portion is formed in a separate process. However, the main region contact portion 224 and the pad region contact portion 334 may be formed in different processes.
  • FIG. 27 shows an example of the g-g' cross section in FIG. 18A.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 25 in that the pad region 330 has a housing portion 198. Also, in this example, the differences from the embodiment of FIG. 25 will be particularly described, and the rest may be the same as the embodiment of FIG. 25.
  • the housing portion 198 is provided below the pad region contact portion 334.
  • the material of the housing portion 198 may be the same as that of the interlayer insulating film 38.
  • the bottom corner 3340 of the pad region contact portion 334 may be in contact with the polycrystalline portion 332.
  • the bottom corner 3340 of the pad region contact portion 334 may be the intersection of the bottom surface of the pad region contact portion 334 and the side surface of the pad region contact portion 334.
  • the bottom corner 3340 in contact with the polycrystalline portion 332 may be in contact with the polycrystalline portion 332 on the top surface of the polycrystalline portion 332, may be in contact with the polycrystalline portion 332 on the side surface of the polycrystalline portion 332, or may be in contact with the polycrystalline portion 332 in an internal region of the polycrystalline portion 332.
  • the bottom corner 3340 is in contact with the polycrystalline portion 332 on the top surface of the polycrystalline portion 332.
  • the pad area contact portion 334 in this example has two bottom corners 3340.
  • One of the two bottom corners 3340 may be in contact with the polycrystalline portion 332.
  • the other of the two bottom corners 3340 may be in contact with the housing portion 198, or may not be in contact with the housing portion 198.
  • the pad area contact portion 334 has one bottom corner 3340a in contact with the polycrystalline portion 332, and the other bottom corner 3340b in contact with the housing portion 198.
  • the bottom surface of the pad area contact portion 334 may be in contact with the housing portion 198.
  • the bottom surface of the pad area contact portion 334 may be the surface between the two bottom corner portions 3340 of the pad area contact portion 334.
  • the bottom surface of the pad area contact portion 334 in contact with the housing portion 198 may be in contact with the housing portion 198 on the upper surface of the housing portion 198, or in contact with the housing portion 198 in an area inside the housing portion 198.
  • the bottom surface of the pad area contact portion 334 in this example is in contact with the housing portion 198 on the upper surface of the housing portion 198.
  • the bottom surface of the pad area contact portion 334 may be in contact with the polycrystalline portion 332 and the housing portion 198.
  • one bottom corner portion 3340a of the pad area contact portion 334 is in contact with the polycrystalline portion 332, and the other bottom corner portion 3340b is in contact with the housing portion 198, so that the bottom surface of the pad area contact portion 334 is in contact with the polycrystalline portion 332 and the housing portion 198.
  • the polycrystalline portion 332 may contact the bottom surface of the pad region contact portion 334 from the bottom surface corner 3340 to an area of 10% to 40% of the bottom surface of the pad region contact portion 334. That is, the area ratio of the surface of the bottom surface of the pad region contact portion 334 that contacts the polycrystalline portion 332 to the area of the bottom surface of the pad region contact portion 334 may be 10% to 40%.
  • the length L1 is the length of the bottom surface of the pad region contact portion 334 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10.
  • the length L2 is the length of the bottom surface of the bottom surface of the pad region contact portion 334 that contacts the polycrystalline portion 332 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10.
  • the ratio of the length L2 to the length L1 may be 10% to 40%.
  • the polycrystalline portion 332 contacts the bottom surface of the pad region contact portion 334 from the bottom surface corner 3340a to an area of 20% of the bottom surface of the pad region contact portion 334. That is, in this example, the ratio of length L2 to length L1 is 20%.
  • the pad region contact portion 334 may have a barrier metal film 3342 and a plug portion 3344.
  • the barrier metal film 3342 and the plug portion 3344 are formed of different materials, but may be formed of the same material.
  • the barrier metal film 3342 may be provided on the bottom corners 3340 of the pad region contact portion 334. In this example, the barrier metal film 3342 is provided over the entire side and bottom surface of the pad region contact portion 334, but is not limited to this. The barrier metal film 3342 may be provided to cover at least the bottom corners 3340, or may be provided without covering the center portion of the bottom surface of the pad region contact portion 334. The barrier metal film 3342 may extend beyond the contact hole 53 and extend above the interlayer insulating film 38.
  • the material of the barrier metal film 3342 may be titanium or a titanium compound, etc.
  • the plug portion 3344 may be provided in contact with the inner side of the barrier metal film 3342.
  • the plug portion 3344 is provided by filling the pad region contact portion 334, but this is not limited to this.
  • the plug portion 3344 may be provided in a part of the pad region contact portion 334, and may extend beyond the contact hole 56 and be provided above the interlayer insulating film 38.
  • the plug portion 3344 is provided in a part of the pad region contact portion 334, the remaining area of the pad region contact portion 334 may be filled with the same material as the pad electrode 51.
  • the material of the plug portion 3344 may be a plug metal such as tungsten.
  • the side of the polycrystalline portion 332 may be in contact with the side of the housing portion 198.
  • the housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the pad region contact portion 334.
  • the housing portion 198 may be formed in the process of providing the interlayer insulating film 38, and may be formed of the same material as the interlayer insulating film 38.
  • the housing portion 198 may be a virtual region.
  • the housing portion 198 may be formed integrally as a part of the interlayer insulating film 38.
  • the housing portion 198 may be polysilicon or non-doped polysilicon having a lower impurity concentration than the polycrystalline portion 332.
  • the housing portion 198 may be a pad region insulating film 338 provided above the semiconductor substrate 10.
  • the housing portion 198 may be formed in the process of providing the pad region insulating film 338, and may be formed of the same material as the pad region insulating film 338. That is, the housing portion 198 may be integrally formed as part of the pad region insulating film 338.
  • the pad region contact portion 334 is provided with the bottom corner portion 3340 in contact with the polycrystalline portion 332 and the bottom surface in contact with the housing portion 198. This ensures electrical connection between the pad electrode 51 and the polycrystalline portion 332. If the plug portion 3344 and the barrier metal film 3342 near the center of the bottom surface of the pad region contact portion 334 are removed by over-etching during the etch-back process of the plug portion 3344, there is a risk of voids being generated inside the pad region contact portion 334. Even in this case, electrical connection can be ensured by the barrier metal film 3342 and/or the plug portion 3344 remaining at the bottom corner portion 3340 of the pad region contact portion 334.
  • the pad region contact portion 334 in this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the pad region contact portion 334 near the center of the bottom surface, the effect on the electrical connection at the bottom corner portion 3340 between the pad region contact portion 334 and the polycrystalline portion 332 is suppressed. This makes it possible to improve the yield of semiconductor devices 100 having desired characteristics.
  • the pad region 330 in this example ensures electrical connection between the pad region contact portion 334 and the polycrystalline portion 332 through the bottom corner portion 3340 rather than the bottom center portion of the pad region contact portion 334. This makes it possible to obtain stable quality and improve yields, even if a void is formed in the area near the center of the pad region contact portion 334 that contacts the housing portion 198.
  • FIG. 28 shows an example of the g-g' cross section in FIG. 18A.
  • the semiconductor device 100 of this example differs from the embodiment of FIG. 27 in that the pad region 330 has a pad region trench contact portion 3345. The rest may be the same as the embodiment of FIG. 27.
  • the sidewall of the pad region contact portion 334 may be in contact with the polycrystalline portion 332 and the interlayer insulating film 38.
  • the polycrystalline portion 332 may be in contact with the sidewall of the pad region contact portion 334 from the bottom corner 3340 to an area of 10% to 90% of the sidewall of the pad region contact portion 334. That is, the ratio of the area of the sidewall of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 to the area of the sidewall of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 may be 10% to 90%. Referring to FIG.
  • the length L3 is the length of the sidewall of the pad region contact portion 334 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10
  • the length L4 is the length of the sidewall of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less.
  • the polycrystalline portion 232 contacts the sidewall of the pad region contact portion 334 from the bottom corner 3340 to 35% of the sidewall of the pad region contact portion 334. That is, the ratio of length L4 to length L3 in this example is 35%.
  • a Zener diode 170 is provided in anti-parallel between the cathode pad 118 and the anode pad 116 for voltage protection.
  • the Zener diode 170 may have a configuration similar to that of the temperature-sensitive diode 183. In this case, the forward voltage of the Zener diode 170 may be different from the forward voltage of the temperature-sensitive diode 183.
  • the Zener diode 170 may be provided between each of the temperature-sensitive cathode regions 181 and the temperature-sensitive anode regions 182.
  • the Zener diode 170 may have a configuration similar to that of the temperature-sensitive diode 183. In this case, the breakdown voltage of the Zener diode 170 may be different from the breakdown voltage of the temperature-sensitive diode 183.
  • the Zener diode 170 may be configured to be connected in series. In other examples, the Zener diode 170 may be connected in a different position, or the Zener diode 170 may not be provided.

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  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
PCT/JP2024/025243 2023-07-14 2024-07-12 半導体装置 Pending WO2025018290A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190172770A1 (en) * 2017-12-05 2019-06-06 Infineon Technologies Austria Ag Semiconductor Device with Integrated pn Diode Temperature Sensor
JP2020077674A (ja) * 2018-11-05 2020-05-21 富士電機株式会社 半導体装置および製造方法
WO2020246230A1 (ja) * 2019-06-04 2020-12-10 ローム株式会社 半導体装置
JP2022161286A (ja) * 2021-04-08 2022-10-21 富士電機株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190172770A1 (en) * 2017-12-05 2019-06-06 Infineon Technologies Austria Ag Semiconductor Device with Integrated pn Diode Temperature Sensor
JP2020077674A (ja) * 2018-11-05 2020-05-21 富士電機株式会社 半導体装置および製造方法
WO2020246230A1 (ja) * 2019-06-04 2020-12-10 ローム株式会社 半導体装置
JP2022161286A (ja) * 2021-04-08 2022-10-21 富士電機株式会社 半導体装置

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