Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0175—Coupling arrangements; Interface arrangements

Definitions

• This disclosure relates to a display device.
• Display devices use a large number of transistors in their drivers.
• a display device includes a plurality of display pixels, a plurality of scanning lines, and a first buffer circuit connected to each scanning line.
• the display device further includes a driver electrically connected to each scanning line via the first buffer circuit and capable of sequentially selecting a plurality of display pixels for each unit pixel row via the plurality of scanning lines.
• the first buffer circuit includes a plurality of first transistors and a plurality of second transistors. The plurality of first transistors are capable of changing from on to off when transitioning from a selection period in which a scanning line is selected to a non-selection period in which a scanning line is not selected.
• the plurality of second transistors are capable of changing from off to on when transitioning from a selection period to a non-selection period.
• the driver includes a second buffer circuit and a voltage adjustment circuit.
• a vertical clock signal is input to an input terminal, and an output terminal is connected to a gate of a third transistor, which is one of the plurality of second transistors.
• the voltage adjustment circuit is capable of changing the voltage at the output terminal so that the absolute value of the gate-source voltage of the third transistor becomes smaller after the third transistor changes from off to on when transitioning from a selected period to a non-selected period.
• FIG. 1 is a diagram illustrating an example of a schematic configuration of a display device 1 according to an embodiment of the present disclosure.
• FIG. 2 is a diagram showing an example of a circuit configuration of three display pixels 11, a gate driver 21, and a buffer circuit 12 connected to an arbitrary scanning line WSL in the display device 1 of FIG. 3A shows an example of the time change of the vertical synchronization signal VST and the vertical clock signal CLKV, and
• FIG. 3B shows an example of the on-period and off-period of the P-type MOS transistor P2 in the buffer circuit 12.
• FIG. 4 is a diagram showing an example of a truth table of a logic circuit formed by the gate driver 21 and the buffer circuit 12 of FIG. FIG.
• FIG. 5 is a diagram showing an example of the operation of the logic circuit when the input is "H” in the truth table of FIG.
• FIG. 6 is a diagram showing an example of the operation of the logic circuit when the input is "L” in the truth table of FIG.
• FIG. 7 is a graph showing, on a log scale, the relationship between the gate-source voltage Vgs of a transistor and the current flow time required for the ON current flowing through the transistor to decrease to 50% from the initial state.
• FIG. 8 is a diagram showing an example of various waveforms when the display device 1 of FIG. 1 transitions from the selection period T1 to the non-selection period T2.
• FIG. 9 is a diagram showing an example of a circuit configuration of three display pixels 11, a gate driver 121, and a buffer circuit 112 connected to an arbitrary scanning line WSL in a display device according to a comparative example.
• FIG. 10 is a diagram showing an example of various waveforms when the selection period T1 transitions to the non-selection period T2 in a display device including the circuit shown in FIG.
• FIG. 11 is a diagram showing a modified example of the circuit configuration of the gate driver 21 and the buffer circuit 12 in FIG.
• FIG. 12 is a diagram showing a modified example of the circuit configuration of the gate driver 21 and the buffer circuit 12 in FIG.
• FIG. 13 is a diagram showing a modified example of the schematic configuration of the display device 1 of FIG.
• FIG. 1 illustrates an example of a schematic configuration of the display device 1.
• the display device 1 includes, for example, a display panel 10 and a logic IC (Integrated Circuit) 20, as shown in Fig. 1.
• IC Integrated Circuit
• the display panel 10 has a pixel array region 10A in which a plurality of display pixels 11 are arranged two-dimensionally in the row and column directions, for example.
• the pixel array region 10A corresponds to the image display region of the display panel 10.
• the display panel 10 further has a peripheral region 10B in which a plurality of buffer circuits 12 are arranged, for example.
• the peripheral region 10B is a region that surrounds the pixel array region 10A in a plan view, and corresponds to the frame region of the display panel 10.
• the display panel 10 is capable of displaying an image based on a video signal input from outside the display device 1, for example, by the plurality of display pixels 11 being actively driven by a logic IC 20.
• the display panel 10 has, for example, a number of scanning lines WSL extending in the row direction and a number of signal lines DTL extending in the column direction.
• display pixels 11 are provided at the intersections of the signal lines DTL and the scanning lines WSL.
• Each scanning line WSL is electrically connected to an output terminal of a gate driver 21 (described later) via a buffer circuit 12.
• Each signal line DTL is connected to an output terminal of a data driver 22 (described later).
• each display pixel 11 has a transistor Tr that writes a signal voltage to the display pixel 11, a storage capacitance Cs that holds the voltage written to the display pixel 11, and an optical element OE connected in parallel to the storage capacitance Cs. The voltage held in the storage capacitance Cs is applied to the optical element OE.
• the optical element OE is an element that can perform optical modulation or emit light according to the magnitude of the voltage held in the storage capacitance Cs or the magnitude of the current flowing through the optical element OE due to the voltage held in the storage capacitance Cs, and is composed of, for example, a liquid crystal layer, an organic EL (Electro Luminescence) layer, or an electrophoretic layer.
• One end of the storage capacitance Cs and the optical element OE is connected to the scanning line WSL, and the other end of the storage capacitance Cs and the optical element OE is connected to, for example, a common potential line COM.
• the circuit block consisting of the gate driver 21 and the buffer circuit 12 is capable of outputting the vertical synchronization signal VST input from the display control circuit 23, or the vertical clock signal CLKV generated based on the vertical synchronization signal VST, as a selection pulse to the scanning line WSL.
• the gate driver 21 is capable of generating a vertical clock signal CLKV based on the vertical synchronization signal VST input from the display control circuit 23.
• the gate driver 21 is capable of performing a predetermined waveform modification on the vertical synchronization signal VST or the vertical clock signal CLKV, and outputting the signal obtained by the waveform modification (waveform-modified signal) to the buffer circuit 12.
• the gate driver 21 is capable of generating an inverted signal of the vertical synchronization signal VST or the vertical clock signal CLKV, and outputting it to the buffer circuit 12.
• the gate driver 21 is capable of performing the above-mentioned waveform modification based on a feedback signal input from the buffer circuit 12.
• the buffer circuit 12 is capable of generating a signal corresponding to the vertical synchronization signal VST or the vertical clock signal CLKV based on the waveform modification signal and the inversion signal input from the gate driver 21, and outputting the signal to the scanning line WSL.
• the buffer circuit 12 is further capable of generating the above-mentioned feedback signal, and outputting the signal to the gate driver 21.
• the buffer circuit 12 is connected to one end of the scanning line WSL and is disposed between the output terminal of the gate driver 21 and the scanning line WSL.
• the buffer circuit 12 includes a voltage conversion circuit 12A and an inverter circuit 12B.
• the voltage conversion circuit 12A is capable of generating a signal (hereinafter referred to as "inversion signal Va") corresponding to the inversion signal of the vertical synchronization signal VST or the vertical clock signal CLKV based on the waveform modification signal and the inversion signal input from the gate driver 21.
• the voltage conversion circuit 12A is capable of outputting the inversion signal Va to the input terminal (node A) of the inverter circuit 12B.
• the node A is connected to a voltage adjustment circuit 211B (described later) in the gate driver 21. Therefore, the voltage conversion circuit 12A is capable of outputting the inversion signal Va to the input terminal of the inverter circuit 12B.
• the voltage conversion circuit 12A is also capable of outputting the inversion signal Va to the voltage adjustment circuit 211B as the above-mentioned feedback signal.
• the voltage conversion circuit 12A is configured to include, for example, p-type MOS transistors P2 and P3 and n-type MOS transistors N2 and N3.
• the voltage conversion circuit 12A has, for example, a p-type MOS transistor P2 and an n-type MOS transistor N3 connected in series between the power supply potential line VDD1 and the power supply potential line VSS2, and a p-type MOS transistor P3 and an n-type MOS transistor N2 connected in series.
• the gate is connected to the output terminal of the buffer circuit 211A described below, the source is connected to the power supply line VDD1, and the drain is connected to the gate of the n-type MOS transistor N2 and the source of the n-type MOS transistor N3.
• the drain of the p-type MOS transistor P2 is further connected to node A.
• the gate is connected to node B in the buffer circuit 211A, the source is connected to the power supply line VDD1, and the drain is connected to the gate of the n-type MOS transistor N3 and the source of the n-type MOS transistor N2.
• the gate is connected to the drain of the p-type MOS transistor P2 and the drain of the n-type MOS transistor N3, and the drain is connected to the drain of the p-type MOS transistor P3 and the gate of the n-type MOS transistor N3.
• the source is connected to the power supply potential line VSS2.
• the gate of the n-type MOS transistor N2 is also connected to node A.
• the gate is connected to the drain of the p-type MOS transistor P3 and the drain of the n-type MOS transistor N2, and the drain is connected to the drain of the p-type MOS transistor P2 and the gate of the n-type MOS transistor N2.
• the source is connected to the power supply potential line VSS2.
• the drain of the n-type MOS transistor N3 is also connected to node A.
• the inverter circuit 12B is capable of generating an inverted signal (selection pulse) of the output (inverted signal Va) of the voltage conversion circuit 12A.
• the inverter circuit 12B is capable of outputting the generated selection pulse to the scanning line WSL.
• the inverter circuit 12B is, for example, an inverter circuit in which a p-type MOS transistor P1 and an n-type MOS transistor N1 are connected in series.
• the input terminal is connected to the output terminal of the voltage conversion circuit 12A, and the output terminal is connected to the scanning line WSL.
• the inverter circuit 12B has, for example, a p-type MOS transistor P1 and an n-type MOS transistor N1 connected in series between the power supply potential line VDD2 and the power supply potential line VSS2.
• the gate is connected to node A and the gate of the n-type MOS transistor N1, the source is connected to the power supply line VDD2, and the drain is connected to the drain of the n-type MOS transistor N1 and the scanning line WSL.
• the gate is connected to node A and the gate of the p-type MOS transistor P1
• the drain is connected to the drain of the p-type MOS transistor P1 and the scanning line WSL
• the source is connected to the power supply line VSS2.
• the gate driver 21 has a buffer circuit 211A and a voltage adjustment circuit 211B.
• the buffer circuit 211A is composed of two inverter circuits.
• the input terminal of the previous inverter circuit is connected to a terminal to which the vertical synchronization signal VST or the vertical clock signal CLKV is input, and the output terminal of the previous inverter circuit is connected to the input terminal of the next inverter circuit.
• the output terminal of the next inverter circuit is connected to the gate of the p-type transistor P2 in the voltage conversion circuit 12A, and the connection node (node B) between the output terminal of the previous inverter circuit and the input terminal of the next inverter circuit is connected to the gate of the p-type transistor P3 in the voltage conversion circuit 12A.
• the front-stage inverter circuit has, for example, a p-type MOS transistor P5 and an n-type MOS transistor N6 connected in series between the power supply potential line VDD1 and the power supply potential line VSS1.
• the rear-stage inverter circuit has, for example, a p-type MOS transistor P4 and an n-type MOS transistor N5 connected in series between the power supply potential line VDD1 and the connection wiring Lx.
• the gate is connected to the gate of the n-type MOS transistor N5, the source is connected to the power supply line VDD1, and the drain is connected to the drain of the n-type MOS transistor N5.
• the gate is connected to the gate of the n-type MOS transistor N6, the source is connected to the power supply line VDD1, and the drain is connected to the drain of the n-type MOS transistor N6.
• the gate is connected to the gate of the p-type MOS transistor P4, the drain is connected to the drain of the p-type MOS transistor P4, and the source is connected to the connection wiring Lx.
• the gate is connected to the gate of the p-type MOS transistor P5, the drain is connected to the drain of the p-type MOS transistor P5, and the source is connected to the power supply line VSS1.
• the gate of p-type MOS transistor P5 and the gate of n-type MOS transistor N6 are connected to a terminal to which the vertical synchronization signal VST or the vertical clock signal CLKV is input.
• the drain of p-type MOS transistor P5 and the drain of n-type MOS transistor N6 are connected to node B.
• the gate of p-type MOS transistor P4 and the gate of n-type MOS transistor N5 are connected to node B.
• Node B is connected to the gate of p-type transistor P3 in voltage conversion circuit 12A.
• the drain of p-type MOS transistor P4 and the drain of n-type MOS transistor N5 are connected to the gate of p-type transistor P2 in voltage conversion circuit 12A.
• the voltage adjustment circuit 211B is capable of changing the voltage at the output terminal of the buffer circuit 211A so that the absolute value of the gate-source voltage Vgs of the p-type transistor P2 becomes smaller after the p-type transistor P2 changes from off to on when transitioning from the selection period T1 to the non-selection period T2.
• the voltage adjustment circuit 211B is capable of changing the voltage at the output terminal of the buffer circuit 211A so that the absolute value of the gate-source voltage Vgs of the p-type transistor P2 becomes smaller after the p-type transistor P2 changes from off to on when transitioning from the selection period T1 to the non-selection period T2 based on the voltage of a node A described below.
• Vgs1 be the absolute value of the gate-source voltage Vgs of the p-type transistor P2 at the moment when the p-type transistor P2 changes from off to on.
• Vgs2 be the absolute value of the gate-source voltage Vgs of the p-type transistor P2 after the p-type transistor P2 changes from off to on.
• the voltage adjustment circuit 211B is capable of changing the voltage at the output terminal of the buffer circuit 211A so that Vgs2 is smaller than Vgs1.
• the voltage adjustment circuit 211B is capable of changing the voltage at the output terminal of the buffer circuit 211A to a value higher than the voltage of the power supply line VSS1, which is the reference voltage of the buffer circuit 211A.
• the selection period T1 refers to the period during which the scanning line WSL is selected by the circuit block consisting of the gate driver 21 and the buffer circuit 12.
• the selection period T1 refers to the period during which a selection pulse (H level signal) is applied to the scanning line WSL, for example, as shown in FIG. 3(A).
• the non-selection period T2 refers to the period during which the scanning line WSL is not selected by the circuit block consisting of the gate driver 21 and the buffer circuit 12, that is, a period other than the selection period T1.
• the non-selection period T2 refers to the period during which a non-selection pulse (L level signal) is applied to the scanning line WSL, for example, as shown in FIG. 3(A).
• the p-type transistor P2 and the n-type transistors N1 and N2 included in the buffer circuit 12 are off.
• the selection period T1 is changed to the non-selection period T2
• the p-type transistors P2 and the n-type transistors N1 and N2 included in the buffer circuit 12 change from off to on.
• the p-type transistors P1 and P3 and the n-type transistor N3 included in the buffer circuit 12 are on.
• the p-type transistors P1 and P3 and the n-type transistor N3 included in the buffer circuit 12 change from on to off.
• the voltage adjustment circuit 211B includes an n-type transistor N4 and two resistance elements R1 and R2 connected in series via the n-type transistor N4.
• the voltage adjustment circuit 211B may include three or more resistance elements.
• the voltage adjustment circuit 211B is provided between the power supply potential line VDD1 and the power supply potential line VSS1.
• the gate is connected to the node A
• the drain is connected to the power supply potential line VDD1 via the resistive element R1
• the source is connected to the power supply potential line VSS1 via the resistive element R2.
• the voltage adjustment circuit 211B includes a resistive element R1 on the drain side of the n-type transistor N4 and has a wiring that connects the drain of the n-type transistor N4 to the power supply potential line VDD1.
• the voltage adjustment circuit 211B includes a resistive element R2 on the source side of the n-type transistor N4 and has a wiring that connects the source of the n-type transistor N4 to the power supply potential line VSS1.
• the voltage adjustment circuit 211B has a wiring Ly that connects the gate of the n-type transistor N4 to the node A in the buffer circuit 12.
• the voltage adjustment circuit 211B further includes a connection line Lx connected to the source side of the n-type transistor N4 of the voltage adjustment circuit 211B, as shown in FIG. 2.
• the connection line Lx is connected to, for example, the source of the n-type transistor N4 and the inverter circuit (specifically, the source of the n-type transistor N5) in the subsequent stage of the buffer circuit 211A.
• the connection line Lx is connected to the power supply potential line VSS1 via the resistive element R2, so that the voltage of the connection line Lx is higher than the voltage of the power supply potential line VSS1.
• the logic IC 20 is configured to include, for example, one or more ICs.
• the logic IC 20 is provided, for example, in the peripheral region 10B of the display panel 10.
• the logic IC 20 may be electrically connected to the display panel 10, for example, via an FPC (Flexible Printed Circuits).
• the logic IC 20 has, for example, a gate driver 21, a data driver 22, and a display control circuit 23.
• the logic IC 20 is capable of displaying an image based on a video signal input from outside the display device 1 on the display panel 10, for example, by actively driving a plurality of display pixels 11 of the display panel 10.
• the display control circuit 23 can, for example, store and hold the input video signal in a frame memory for each screen (for each display of one frame).
• the display control circuit 23 can also, for example, control the gate driver 21 and data driver 22 that drive the display panel 10 so that they operate in conjunction with each other.
• the data driver 22 can, for example, supply a scanning timing control signal (e.g., a synchronization signal VST and a clock signal) to the gate driver 21, and supply a video signal for a unit pixel row based on the video signal held in the frame memory and a display timing control signal to the data driver 22.
• a scanning timing control signal e.g., a synchronization signal VST and a clock signal
• the data driver 22 is capable of supplying, for example, a video signal for a unit pixel row supplied from the display control circuit 23 to each display pixel 11 as a signal voltage. Specifically, the data driver 22 is capable of supplying, for example, a signal voltage corresponding to the video signal for a unit pixel row to each display pixel 11 in the unit pixel row selected by the data driver 22 via a signal line DTL.
• the gate driver 21 is connected to a plurality of scanning lines WSL via a buffer circuit 12.
• the gate driver 21 can select the display pixel 11 to be driven based on, for example, a scanning timing control signal (for example, a vertical synchronization signal VST and a clock signal) supplied from the display control circuit 23.
• the gate driver 21 can select each display pixel 11 of a unit pixel row among the plurality of display pixels 11 arranged two-dimensionally in the pixel array region 10A as a drive target by applying a selection pulse to the gate of the transistor of the display pixel 11 via the scanning line WSL.
• the unit pixel row is displayed according to the signal voltage supplied from the data driver 22.
• the gate driver 21 can sequentially scan the unit pixel row by unit pixel row in a time-division manner, for example, to cause the display panel 10 to display over the entire display area.
• the gate driver 21 has, for example, a shift register circuit.
• the shift register circuit is capable of generating a vertical clock signal CLKV that sequentially shifts the selected unit pixel row in the scanning direction based on a scanning timing control signal (for example, a vertical synchronization signal VST and a clock signal) supplied from the display control circuit 23.
• a scanning timing control signal for example, a vertical synchronization signal VST and a clock signal
• the gate driver 21 has an output circuit 211 for each unit pixel row, for example, as shown in FIG. 2, downstream of the shift register circuit.
• the output circuit 211 has a buffer circuit 211A and a voltage adjustment circuit 211B, for example, as shown in FIG. 2.
• FIG. 4 shows an example of a truth table of a logic circuit formed by output circuit 211 and buffer circuit 12.
• FIG. 5 shows an example of the operation of the logic circuit when the input is "H” in the truth table of FIG. 4.
• FIG. 6 shows an example of the operation of the logic circuit when the input is "L” in the truth table of FIG. 4.
• p-type transistor P2 When an H-level signal is input to the gate of p-type transistor P2 of voltage conversion circuit 12A, p-type transistor P2 remains OFF. On the other hand, when an L-level signal is input to the gate of p-type transistor P3 of voltage conversion circuit 12A, p-type transistor P3 turns ON. As a result, n-type MOS transistor N3 turns ON and n-type MOS transistor N2 turns OFF, so that a L-level signal is applied to node A.
• a H-level signal (i.e., a selection signal) is output from inverter circuit 12B to scanning line WSL. Therefore, when a H-level signal is input as vertical clock signal CLKV, a H-level signal is output to scanning line WSL.
• p-type transistor P2 When an L-level signal is input to the gate of p-type transistor P2 of voltage conversion circuit 12A, p-type transistor P2 turns ON. On the other hand, when an H-level signal is input to the gate of p-type transistor P3 of voltage conversion circuit 12A, p-type transistor P3 remains OFF. As a result, n-type MOS transistor N3 turns OFF and n-type MOS transistor N2 turns ON, so that an H-level signal is applied to node A.
• an L-level signal (i.e., a non-selection signal) is output from inverter circuit 12B to scanning line WSL. Therefore, when an L-level signal is input as vertical clock signal CLKV, an L-level signal is output to scanning line WSL.
• the non-selection period T2 during which an L-level signal is output to the scanning line WSL occupies approximately 99.9% of one frame period IF, as shown in FIG. 3, for example. Therefore, the p-type transistor P2 and the n-type transistors N1 and N2 included in the buffer circuit 12 continue to be on for approximately 99.9% of the period of one frame period IF.
• transistors can suffer from operational problems due to characteristic fluctuations caused by BTI during long-term continuous operation. For example, as shown in FIG. 3, the p-type transistor P2 and the n-type transistors N1 and N2 included in the buffer circuit 12 continue to be on for approximately 99.9% of the period of one frame period IF.
• a voltage adjustment circuit 211B is provided in each output circuit 21 of the gate driver 21, which changes the gate voltage Vg of the p-type transistor P2 to a voltage Vb higher than the voltage Vss1 of the power supply line VSS1, which is the reference voltage in each output circuit 21, during the non-selection period T2.
• FIG. 8 shows an example of various waveforms when the display device 1 transitions from a selection period T1 to a non-selection period T2.
• Vdd1 is the voltage of the power supply line VDD1
• Vdd2 is the voltage of the power supply line VDD2
• Vss1 is the voltage of the power supply line VSS1
• Vss2 is the voltage of the power supply line VSS2.
• Vg is the gate voltage of p-type transistor P2
• Vwsl is the voltage of the scanning line WSL
• Vgs is the gate-source voltage of p-type transistor P2
• Va is the voltage of node A
• Von is the on-voltage of n-type transistor N4.
• the voltage at the output terminal of the buffer circuit 211A also changes from H level to L level
• the gate voltage Vg of the p-type transistor P2 also changes from H level to L level.
• a large negative bias is applied to the gate-source voltage Vgs of the p-type transistor P2, and a sufficiently large current flows between the source and drain of the p-type transistor P2.
• the voltage Va of the node A rises instantaneously.
• the n-type transistor N4 turns ON, and the voltage divided by the voltage adjustment circuit 211B is input to the inverter circuit in the subsequent stage of the buffer circuit 211A via the connection wiring Lx.
• the voltage shown in the following formula (1) is applied between the gate and source of the p-type transistor P2.
• r1 resistance value of resistor element R1
• r2 resistance value of resistor element R2
• ron on-resistance of n-type transistor N4
• the absolute value of the gate-source voltage Vgs of p-type transistor P2 gradually decreases over time, as shown in FIG. 8, and becomes a constant value.
• the gate voltage Vg of p-type transistor P2 also increases, forming a feedback loop in which the absolute value of the gate-source voltage Vgs of p-type transistor P2 decreases.
• FIG. 9 shows an example of the circuit configuration of three display pixels 11 connected to an arbitrary scanning line WSL, as well as the gate driver 121 and the buffer circuit 112 in a display device according to a comparative example.
• an output circuit 212 that does not include the voltage adjustment circuit 211B is provided instead of the output circuit 211 provided with the voltage adjustment circuit 211B. Therefore, for example, as shown in FIG. 10, the absolute value of the gate-source voltage Vgs of the p-type transistor P2 remains large during the non-selection period T2. As a result, there is a high risk of characteristic fluctuation due to BTI in the p-type transistor P2.
• the absolute value of the gate-source voltage Vgs of the p-type transistor P2 is smaller than that of the comparative example.
• the risk of characteristic fluctuation due to BTI is reduced in the p-type transistor P2.
• the gate driver 21 is connected to the scanning line WSL via the buffer circuit 12.
• the gate driver 21 is provided with a buffer circuit 211A having an input terminal to which a vertical synchronization signal VST or a vertical clock signal CLKV is input and an output terminal connected to the gate of the p-type transistor P2 in the buffer circuit 12.
• the gate driver 21 is further provided with a voltage adjustment circuit 211B that can change the voltage at the output terminal of the buffer circuit 211A so that the absolute value of the gate-source voltage Vgs of the p-type transistor P2 becomes smaller after the p-type transistor P2 changes from off to on when transitioning from the selection period T1 to the non-selection period T2. This can reduce the risk of characteristic fluctuation due to BTI in the p-type transistor P2.
• a voltage adjustment circuit 211B is provided that can change the voltage at the output end of the buffer circuit 211A based on the voltage at node A so that the absolute value of the gate-to-source voltage Vgs of the p-type transistor P2 becomes smaller after the p-type transistor P2 changes from off to on when transitioning from the selection period T1 to the non-selection period T2. This can reduce the risk of characteristic fluctuations due to BTI in the p-type transistor P2.
• a voltage adjustment circuit 211B includes an n-type transistor N4 whose gate is connected to node A, and resistor elements R1 and R2 connected in series via the n-type transistor N4. Furthermore, a connection wiring Lx is provided that is connected to the wiring on the source side of the n-type transistor N4 and the inverter circuit at the rear stage in the buffer circuit 211A in the voltage adjustment circuit 211B.
• a voltage conversion circuit 12A is provided that can generate a signal corresponding to the vertical synchronization signal VST or the inverted signal of the vertical clock signal CLKV based on the waveform modified signal and the inverted signal obtained from the buffer circuit 211A and output the signal to node A. Furthermore, an inverter circuit 12B is provided that can output an inverted signal of the signal input from the voltage conversion circuit 12A to the scanning line WSL as a selection pulse. This makes it possible to provide a buffer circuit 12 with high current driving power.
• the output circuit 211 may have a voltage adjustment circuit 211C instead of the voltage adjustment circuit 211B, as shown in Fig. 11.
• the voltage adjustment circuit 211C includes an n-type transistor N4, and a p-type transistor P6 and an n-type transistor N7 connected in series via the n-type transistor N4, as shown in Fig. 11.
• the voltage adjustment circuit 211C may include further transistors in addition to the p-type transistor P6 and the n-type transistor N7.
• the voltage adjustment circuit 211C is provided between the power supply potential line VDD1 and the power supply potential line VSS1.
• the gate is connected to node A
• the drain is connected to the power supply potential line VDD1 via the p-type transistor P6, and the source is connected to the power supply potential line VSS1 via the n-type transistor N7.
• the gate is connected to the power supply potential line VSS1
• the source is connected to the power supply potential line VDD1
• the drain is connected to the drain of the n-type transistor N4. In other words, the p-type transistor P6 is always on.
• the gate is connected to the power supply potential line VDD1
• the drain is connected to the source of the n-type transistor N4, and the source is connected to the power supply potential line VSS1.
• the n-type transistor N7 is always on.
• the voltage adjustment circuit 211C further includes a connection line Lx connected to the source side of the n-type transistor N4 of the voltage adjustment circuit 211C, as shown in FIG. 11.
• the connection line Lx is connected to, for example, the source of the n-type transistor N4 and the inverter circuit (specifically, the source of the n-type transistor N5) in the subsequent stage of the buffer circuit 211A. Since the connection line Lx is connected to the power supply potential line VSS1 via the n-type transistor N7, the voltage of the connection line Lx is higher than the voltage of the power supply potential line VSS1.
• a voltage adjustment circuit 211C is provided. Even in this case, the same effects as in the above embodiment can be obtained.
• the buffer circuit 12 may have a buffer circuit 12C instead of the voltage conversion circuit 12A, for example, as shown in Fig. 12.
• the buffer circuit 12C is provided between the power supply potential line VDD1 and the power supply potential line VSS1, for example, as shown in Fig. 12.
• the buffer circuit 12 does not have a function of changing the voltage value (peak value) of the selection pulse.
• the buffer circuit 12C has a front-stage inverter circuit consisting of a p-type MOS transistor P3 and an n-type MOS transistor N3 connected in series between the power supply potential line VDD1 and the power supply potential line VSS1, and a rear-stage inverter circuit consisting of a p-type MOS transistor P2 and an n-type MOS transistor N2 connected in series.
• the input terminal of the front-stage inverter circuit is connected to node B in the buffer circuit 211A, and the output terminal of the front-stage inverter circuit is connected to the input terminal of the rear-stage inverter circuit.
• the input terminal of the rear-stage inverter circuit is also connected to the output terminal of the buffer circuit 211A, and the output terminal of the rear-stage inverter circuit is connected to the input terminal (node A) of the inverter circuit 12B.
• a buffer circuit 12C is provided between the power supply potential line VDD1 and the power supply potential line VSS1. This provides the same effect as the above embodiment, except that the buffer circuit 12 does not have the function of changing the voltage value (peak value) of the selected pulse.
• the display device 1 may have a buffer circuit 12 at each end of each scanning line WSL, for example, as shown in FIG. 13.
• the display device 1 may further include a gate driver 21 connected to each scanning line WSL via a buffer circuit 12 provided at one end edge of each scanning line WSL, and a gate driver 21 connected to each scanning line WSL via a buffer circuit 12 provided at the other end edge of each scanning line WSL, for example, as shown in FIG. 13.
• each gate driver 21 is capable of scanning a plurality of scanning lines WSL for each unit pixel row via the buffer circuit 12. Even in this case, the same effect as the above embodiment can be obtained.
• the present disclosure can have the following configuration.
• the first buffer circuit comprises: a plurality of first transistors capable of changing from on to off when a selection period in which the scanning line is selected transitions to a non-selection period in which the scanning line is not selected; a plurality of second transistors capable of changing from off to on when transitioning from the selected period to the non-selected period;
• the driver includes: a second buffer circuit having an input terminal to which a vertical clock signal is input and an output terminal connected to a gate of a third transistor which is one of the plurality of second transistors; and a voltage adjustment circuit capable of changing the voltage at the output terminal so that an absolute value of a gate-source voltage of the third transistor becomes smaller after the third transistor changes
• the display device described in (1) wherein the voltage adjustment circuit is capable of changing the voltage at the output terminal based on the voltage at the input terminal of a subsequent inverter circuit in the first buffer circuit so that an absolute value of the gate-source voltage of the third transistor becomes smaller after the third transistor changes from off to on when transitioning from the selection period to the non-selection period.
• the voltage regulation circuit includes: a fourth transistor having a gate connected to an input terminal of a subsequent inverter circuit in the first buffer circuit; a plurality of resistance elements connected in series via the fourth transistor;
• the display device according to (2) further comprising: a connection wiring connected to a wiring on a source side of the fourth transistor in the voltage adjustment circuit and a subsequent inverter circuit in the second buffer circuit.
• the voltage regulation circuit includes: a fourth transistor having a gate connected to an input terminal of a subsequent inverter circuit in the first buffer circuit; a plurality of fifth transistors connected in series via the fourth transistor;
• the display device according to (2) further comprising: a connection wiring connected to a wiring on a source side of the fourth transistor in the voltage adjustment circuit and a subsequent inverter circuit in the second buffer circuit.
• the first buffer circuit comprises: a first voltage conversion circuit including the third transistor, which generates a signal corresponding to an inverted signal of the vertical clock signal based on a plurality of control signals obtained from the second buffer circuit, and outputs the signal to an input terminal of a downstream inverter circuit;
• the display device according to (3) or (4), further comprising: a second inverter circuit as the latter stage inverter circuit, the second inverter circuit being configured with a fifth transistor which is one of the plurality of first transistors and a sixth transistor which is one of the plurality of second transistors, and capable of outputting an inverted signal of a signal input from the first voltage conversion circuit as a selection pulse to the scanning line.
• the third transistor is a p-type MOS transistor.

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• 2024
  • 2024-06-04 JP JP2025532428A patent/JPWO2025013465A1/ja active Pending
  • 2024-06-04 WO PCT/JP2024/020372 patent/WO2025013465A1/ja active Pending

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