WO2025007480A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2025007480A1
WO2025007480A1 PCT/CN2023/134006 CN2023134006W WO2025007480A1 WO 2025007480 A1 WO2025007480 A1 WO 2025007480A1 CN 2023134006 W CN2023134006 W CN 2023134006W WO 2025007480 A1 WO2025007480 A1 WO 2025007480A1
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WO
WIPO (PCT)
Prior art keywords
transistor
signal
drain
source
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/134006
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English (en)
French (fr)
Inventor
孙飞翔
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2025007480A1 publication Critical patent/WO2025007480A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel.
  • display panels are widely used in different fields, such as smart mobile terminals, notebooks, and augmented reality displays, etc.
  • the display panel may have a problem of uneven display brightness during the display process.
  • the purpose of the present application is to provide a display panel to improve the problem of uneven brightness display of the display panel.
  • the present application provides a display panel, wherein one frame time of the display panel includes a display scanning period and a scanning blank period, and the display panel includes:
  • each gate driving unit comprising:
  • An input control module used for outputting a driving signal during the display scanning period
  • a compensation detection control module configured to output a compensation detection drive signal during the scanning blank period
  • an output module connected to the input control module and the compensation detection control module, and configured to respond to the drive signal to output a display scanning signal during the display scanning period, and respond to the compensation detection drive signal to output a compensation detection scanning signal during the scanning blank period;
  • the pixel driving circuit is connected to the gate driving unit and is used for receiving the display scanning signal during the display scanning period and receiving the compensation detection scanning signal during the scanning blank period.
  • FIG1 is a schematic diagram of a display panel according to some embodiments of the present application.
  • FIG2 is a schematic diagram of a pixel driving circuit according to some embodiments of the present application.
  • FIG3 is a schematic diagram of a gate driving circuit according to some embodiments of the present application.
  • FIG4 is a circuit diagram of a (3n-1)th gate driving unit GOA (3n-1) in some embodiments of the present application;
  • FIG. 5 is a driving timing diagram of a gate driving circuit according to some embodiments of the present application.
  • Figure 1 is a schematic diagram of a display panel of some embodiments of the present application
  • Figure 2 is a schematic diagram of a pixel driving circuit of some embodiments of the present application
  • Figure 3 is a schematic diagram of a gate driving circuit of some embodiments of the present application
  • Figure 4 is a circuit schematic diagram of a (3n-1)th level gate driving unit GOA (3n-1) of some embodiments of the present application
  • Figure 5 is a driving timing diagram of the gate driving circuit of some embodiments of the present application.
  • the display panel 100 is an organic light emitting diode display panel, but is not limited thereto.
  • the display panel 100 may also be a liquid crystal display panel, a micro light emitting diode display panel, a sub-millimeter light emitting diode display panel, or a quantum dot display panel.
  • the display panel 100 includes a display area 100a and a non-display area 100b surrounding the display area 100a.
  • the display panel 100 includes a pixel driving circuit 200 located in the display area 100a, and the pixel driving circuit 200 is connected to the data signal lines DL and the scanning signal lines GL.
  • the display panel 100 further includes a gate driving circuit 20 disposed in the non-display area 100b.
  • the gate driving circuit 20 includes a first gate driving circuit 201 and a second gate driving circuit 202, which are respectively located at opposite sides of the display area 100a.
  • the gate driving circuit 20 may also be located only on one side of the display area 100a. At least a portion of the gate driving circuit 20 may also be disposed in the display area 100a.
  • the pixel driving circuit 200 includes a data writing transistor K1 , a driving transistor DT, a compensation control transistor K2 , and a storage capacitor Cst.
  • the driving transistor DT includes an N-type transistor.
  • the data writing transistor K1 and the compensation control transistor K2 both include P-type transistors, which is convenient for reducing the size of the data writing transistor K1 and the compensation control transistor K2 while meeting the charging requirements of the data writing transistor K1, so as to facilitate the display panel to achieve high-frequency driving.
  • the size of the data writing transistor K1 and the compensation control transistor K2 is reduced, which is conducive to reducing the area occupied by the pixel driving circuit, thereby increasing the number of pixel driving circuits and pixels, and meeting the display panel's demand for high-resolution display.
  • the data writing transistor K1 and the compensation control transistor K2 may also include N-type transistors.
  • both the data writing transistor K1 and the compensation control transistor K2 include N-type transistors, since the charging current of the N-type transistor is relatively small, the charging time of the N-type transistor needs to be increased, and the increase in the charging time limits the increase in the driving frequency of the display panel.
  • the gate of the data writing transistor K1 is connected to the scanning signal line GL, one of the source and the drain of the data writing transistor K1 is connected to the data signal line DL, and the other of the source and the drain of the data writing transistor K1 is connected to the gate of the driving transistor DT.
  • One of the source and drain of the driving transistor DT receives a first power signal VDD, and the other of the source and drain of the driving transistor DT receives a second power signal VSS, wherein the first power signal VDD is a high level signal, and the second power signal VSS is a low level signal.
  • the gate of the compensation control transistor K2 is connected to a compensation control signal line (not shown) located in the display area 100 a, one of the source and the drain of the compensation control transistor K2 is connected to the other of the source and the drain of the driving transistor DT and receives the second power signal VSS, and the other of the source and the drain of the compensation control transistor K2 is connected to the detection chip 30.
  • the storage capacitor Cst is connected between the other of the source and the drain of the data write transistor K1 and the other of the source and the drain of the drive transistor DT.
  • the light emitting device OLED is connected between the other of the source and the drain of the driving transistor DT and the second power signal VSS.
  • the gate driving circuit 20 includes a plurality of gate driving units.
  • the plurality of gate driving units include a first-stage gate driving unit GOA (1), a second-stage gate driving unit GOA (2), a third-stage gate driving unit GOA (3), and a (3n-1)th-stage gate driving unit GOA (3n-1), where n is an integer greater than or equal to 2.
  • a plurality of gate driving units are cascaded. Each gate driving unit outputs a level transmission signal to the gate driving unit of the next level.
  • the first-level gate driving unit GOA (1) receives the start signal STV and outputs a first-level level transmission signal ST (1) to the second-level gate driving unit GOA (2).
  • the second-level gate driving unit GOA (2) receives the first-level level transmission signal ST (1) and outputs a second-level level transmission signal ST (2).
  • the third-level gate driving unit GOA (3) receives the second-level level transmission signal ST (2) and outputs a third-level level transmission signal ST (3).
  • the (3n-1)th-level gate driving unit GOA (3n-1) receives the (3n-2)th-level level transmission signal ST (3n-2) and outputs the (3n-1)th-level level transmission signal ST (3n-1).
  • Each gate driving unit is connected to the first clock signal line CKL1 to receive the first clock signal CK1.
  • Each gate driving unit is connected to the second clock signal line CKL2 to receive the second clock signal CK2.
  • Each gate driving unit is connected to the reset signal line Reset to receive the output control signal RE.
  • Each gate driving unit is connected to the switching control signal line CKBL to receive the switching control signal CKB.
  • Each gate driving unit is connected to the first level signal line VL to receive the first level VGL, which is a low level signal.
  • Each gate driving unit is connected to the second level signal line VL to receive the second level VGH, which is a high level signal.
  • the (3n-2)th gate driving unit (not shown) is connected to the first compensation detection selection signal line LSPL1 to receive the first compensation detection selection signal LP1.
  • the first gate driving unit GOA (1) receives the first compensation detection selection signal LP1.
  • the (3n-1)th gate driving unit GOA (3n-1) is connected to the second compensation detection selection signal line LSPL2 to receive the second compensation detection selection signal LP2, for example, the second gate driving unit GOA (2) receives the second compensation detection selection signal LP2.
  • the (3n)th gate driving unit (not shown) is connected to the third compensation detection selection signal line LSPL3 to receive the third compensation detection selection signal LP3, for example, the third gate driving unit GOA (3) receives the third compensation detection selection signal LP3.
  • the output end of the first-stage gate driving unit GOA (1) is connected to the first scanning signal line GL1.
  • the output end of the second-stage gate driving unit GOA (2) is connected to the second scanning signal line GL2.
  • the output end of the third-stage gate driving unit GOA (3) is connected to the third scanning signal line GL3.
  • the output end of the (3n-1)th-stage gate driving unit GOA (3n-1) is connected to the (3n-1)th-stage scanning signal line GL (3n-1).
  • one frame time of the display panel 100 includes a display scanning period S1 and a scanning blank period S2, and the scanning blank period S2 is located between the display scanning periods S1 of two adjacent frames.
  • the display scanning period S1 corresponds to 8ms
  • the scanning blank period S2 corresponds to 0.3ms.
  • the gate driving circuit 20 sequentially outputs the display scanning signal WR1 to the multiple rows of pixel driving circuits 200.
  • the data writing transistor K1 is turned on in response to the display scanning signal WR1, and stores the display data signal transmitted by the data signal line DL in the storage capacitor Cst for display.
  • one gate driving unit GOA among all the gate driving units in the gate driving circuit 20 is randomly controlled to output the compensation detection scanning signal WR2.
  • the data writing transistor K1 receiving the compensation detection scanning signal WR2 is turned on in response to the compensation detection scanning signal WR2, and the compensation control transistor K2 is also turned on, and the detection chip 30 detects the initial threshold voltage of the driving transistor DT. After completing the detection of the initial threshold voltage, the initial threshold voltage of the driving transistor DT is externally compensated, so that the display panel can solve the problem of uneven brightness display during the display process.
  • the gate driving circuit 20 can also randomly control a gate driving unit GOA in the gate driving circuit 20 to output a compensation detection scanning signal WR2 during the scanning blank period S2 to detect the initial threshold voltage of the driving transistor DT, which is beneficial to realize external compensation of the driving voltage of the driving transistor DT while realizing display in one frame time, thereby improving the problem of uneven brightness display of the display panel during the display process.
  • the data writing transistor K1 is a P-type transistor, when the display scanning signal WR1 and the compensation detection scanning signal WR2 are both low-level signals, the data writing transistor K1 is turned on.
  • the (3n-1)th gate driving unit GOA (3n-1) includes an input control module 11 , a stage transmission module 12 , a compensation detection control module 13 , an output module 14 , a switching module 15 and a pull-down module 18 .
  • the input control module 11 is used to output a driving signal in the display scanning period S1 , where the driving signal includes a first driving signal P and a second driving signal D.
  • the input control module 11 includes a thirteenth transistor T3 and a fourteenth transistor T4.
  • the gate of the thirteenth transistor T3 receives the first clock signal CK1, one of the source and the drain of the thirteenth transistor T3 receives the previous stage transfer signal ST(3n-2), and the other of the source and the drain of the thirteenth transistor T3 outputs the second drive signal D.
  • the gate of the fourteenth transistor T4 receives the first clock signal CK1, one of the source and the drain of the fourteenth transistor T4 receives the first level VGL, and the other of the source and the drain of the fourteenth transistor T4 outputs the first drive signal P.
  • the previous stage transmission signal ST(3n-2) is a stage transmission signal output by the gate driving unit of the (3n-2)th stage, but is not limited thereto.
  • n is equal to 1
  • one of the source and the drain of the thirteenth transistor T3 receives the start signal STV.
  • the level transmission module 12 is connected to the input control module 11.
  • the level transmission module 12 is used to respond to the driving signal in the display scanning period S1 to output the current level transmission signal ST (3n-1).
  • the current level transmission signal ST (3n-1) includes a high-level current level transmission signal and a low-level current level transmission signal that is less than the high-level current level transmission signal.
  • the level transmission module 12 includes a fourth transistor T10 and a fifth transistor T9.
  • the gate of the fourth transistor T10 receives the first drive signal P, and one of the source and drain of the fourth transistor T10 receives the second level VGH.
  • the gate of the fifth transistor T9 receives the second drive signal D, and one of the source and drain of the fifth transistor T9 receives the first level VGL.
  • the other of the source and drain of the fifth transistor T9 is connected to the other of the source and drain of the fourth transistor T10. Among them, the other of the source and drain of the fourth transistor T10 outputs a high-level level transmission signal.
  • the other of the source and drain of the fifth transistor T9 outputs a low-level level transmission signal.
  • the level transmission module 12 selectively outputs one of the second level VGH and the first level VGL according to the second driving signal D and the first driving signal P.
  • the level transmission module 12 outputs the second level VGH as a high level level transmission signal according to the first driving signal P.
  • the level transmission module 12 outputs the first level VGL as a low level level transmission signal according to the second driving signal D.
  • the (3n-1)th gate driving unit GOA (3n-1) further includes a third capacitor C3, which is used to stabilize the voltage value of the first driving signal P to ensure that the other of the source and the drain of the fourth transistor T10 can stably output a high-level current transmission signal.
  • a first electrode of the third capacitor C3 receives the first driving signal P, and a second electrode of the third capacitor C3 receives the second level VGH.
  • the third capacitor C3 is connected between the gate of the fourth transistor T10 and the second level VGH.
  • the compensation detection control module 13 is used to output a compensation detection driving signal during the scanning blank period S2 .
  • the compensation detection control module 13 includes a detection selection circuit 131 and a detection control circuit 132 .
  • the detection selection circuit 131 is used for outputting a detection selection control signal in response to the previous stage transmission signal ST(3n-2) and the compensation detection selection signal during the display scanning period S1.
  • the front stage transmission signal ST(3n-2) includes a low level front stage transmission signal and a high level front stage transmission signal greater than the low level front stage transmission signal.
  • the detection selection circuit 131 is used to respond to the low level front stage transmission signal and the low level compensation detection selection signal in the display scanning period S1 to output the detection selection control signal.
  • the detection selection circuit 131 includes a first transistor T18.
  • the gate of the first transistor T18 receives the compensation detection selection signal.
  • the gate of the first transistor T18 receives the second compensation detection selection signal LP2.
  • One of the source and the drain of the first transistor T18 receives the previous stage transfer signal ST (3n-2), and the other of the source and the drain of the first transistor T18 outputs the detection selection control signal M.
  • the second compensation detection selection signal LP2 is also controlled to be a low level signal, so that the first transistor T18 outputs a low level detection selection control signal.
  • the first transistor T18 also receives the second compensation detection selection signal LP2.
  • the first transistor T18 receives the first compensation detection selection signal LP1.
  • the third compensation detection selection signal LP3 receives the three adjacent gate driving units GOA receive the first compensation detection selection signal LP1, the second compensation detection selection signal LP2, and the third compensation detection selection signal LP3, respectively, but are not limited thereto.
  • the detection control circuit 132 is connected to the detection selection circuit 131 and the output module 14.
  • the detection control circuit 132 is used to respond to the detection selection control signal and the output control signal RE during the scanning blank period S2 to output the compensation detection driving signal.
  • the detection control circuit 132 includes a second transistor T19 , a first capacitor C4 , and a third transistor T20 .
  • the gate of the second transistor T19 receives the detection selection control signal, and one of the source and the drain of the second transistor receives the first level VGL.
  • the first capacitor C4 is used to store the detection selection control signal M outputted by the detection selection circuit 131 in the display scanning period S1.
  • the first electrode of the first capacitor C4 receives the detection selection control signal M
  • the second electrode of the first capacitor C4 receives the first level VGL.
  • the first capacitor C4 is connected to the gate of the second transistor T19 and one of the source and the drain of the second transistor T19.
  • One of the source and drain of the third transistor T20 is connected to the other of the source and drain of the second transistor T19.
  • the gate of the third transistor T20 receives the output control signal RE, and the other of the source and drain of the third transistor outputs the compensation detection driving signal.
  • the output module 14 is connected to the input control module 11 and the compensation detection control module 13.
  • the output module 14 is used to respond to the driving signal to output the display scanning signal WR1 (3n-1) during the display scanning period S1, and respond to the compensation detection driving signal to output the compensation detection scanning signal WR2 (3n-1) during the scanning blank period S2.
  • the display scan signal WR1 (3n-1) includes a valid display scan signal and an invalid display scan signal.
  • the data writing transistor K1 is turned on after receiving the valid display scan signal, and remains turned off after receiving the invalid display scan signal.
  • the output module 14 includes a sixth transistor T24 and a seventh transistor T25.
  • the gate of the sixth transistor T24 receives the first drive signal P
  • one of the source and the drain of the sixth transistor T24 receives the second level VGH
  • the other of the source and the drain of the sixth transistor T24 outputs an invalid display scanning signal.
  • the gate of the seventh transistor T25 receives the second drive signal D
  • one of the source and the drain of the seventh transistor T25 receives the first level VGL
  • the other of the source and the drain of the seventh transistor T25 outputs a valid display scanning signal.
  • the invalid display scanning signal is a high level signal.
  • the first level VGL is a low level, and the valid display scanning signal is a low level signal.
  • the seventh transistor T25 receives the compensation detection driving signal, one of the source and the drain of the seventh transistor T25 receives the first level VGL, and the other of the source and the drain of the seventh transistor T25 outputs the compensation detection scanning signal WR2 (3n-1). Since the first level VGL is a low level signal, the compensation detection scanning signal WR2 (3n-1) is also a low level signal.
  • the (3n-1)th gate driving unit GOA (3n-1) further includes a fifth capacitor C5, which is used to stabilize the voltage value of the first driving signal P.
  • a first electrode of the fifth capacitor C5 receives the first driving signal P, and a second electrode of the fifth capacitor C5 receives the second level VGH.
  • the fifth capacitor C5 is connected between the second level VGH and the gate of the sixth transistor T24.
  • the (3n-1)th gate driving unit GOA (3n-1) further includes a switching module 15 connected between the input control module 11 and the output module 14.
  • the switching module 15 is used to connect the input control module 11 and the output module 14 during the display scanning period S1, and to disconnect the input control module 11 and the output module 14 during the scanning blank period S2.
  • the switching module 15 includes an eleventh transistor T22 and a twelfth transistor T21.
  • the gate of the eleventh transistor T22 receives the switching control signal CKB, and the source and drain of the eleventh transistor T22 are connected between the gate of the sixth transistor T24 and the input control module 11.
  • the gate of the twelfth transistor T21 receives the switching control signal CKB, and the source and drain of the twelfth transistor T21 are connected between the gate of the seventh transistor T25 and the input control module 11.
  • the eleventh transistor T22 is turned on and transmits the first drive signal P during the display scanning period S1, and is turned off during the scanning blank period S2.
  • the twelfth transistor T21 is turned on and transmits the second drive signal D during the display scanning period S1, and is turned off during the scanning blank period S2.
  • the gate of the eleventh transistor T22 receives the switching control signal CKB, one of the source and the drain of the eleventh transistor T22 is connected to the other of the source and the drain of the fourteenth transistor T4, and the other of the source and the drain of the eleventh transistor T22 is connected to the gate of the sixth transistor T24.
  • the gate of the twelfth transistor T21 receives the switching control signal CKB, one of the source and the drain of the twelfth transistor T21 is connected to the other of the source and the drain of the thirteenth transistor T3, and the other of the source and the drain of the twelfth transistor T21 is connected to the gate of the seventh transistor T25 and the other of the source and the drain of the third transistor T20.
  • the (3n-1)th gate driving unit GOA (3n-1) further includes a first feedback module 21 and a pull-down module 18 connected to the first feedback module 21.
  • the first feedback module 21 receives the first driving signal P and outputs a feedback signal.
  • the pull-down module 18 receives the feedback signal and outputs a pull-down signal Q1 to pull down the second driving signal D.
  • the pull-down module 18 includes an eighth transistor T16.
  • the gate of the eighth transistor T16 and one of the source and the drain of the eighth transistor T16 receive the feedback signal, and the other of the source and the drain of the eighth transistor T16 outputs a pull-down signal Q1 to the gate of the seventh transistor T25, and the pull-down signal Q1 pulls down the second driving signal D to ensure that the seventh transistor T25 stably outputs a valid display scanning signal in the display scanning period S1.
  • the pull-down module 18 further includes a fifteenth transistor T14 and a sixteenth transistor T15.
  • the gate of the fifteenth transistor T14 receives the first clock signal CK1, and one of the source and the drain of the fifteenth transistor T14 receives the previous stage transfer signal ST (3n-2).
  • the gate of the sixteenth transistor T15 receives the first level VGL, and the source and the drain of the fifteenth transistor T14 are connected between the other of the source and the drain of the fifteenth transistor T14 and the gate of the eighth transistor T16.
  • the first feedback module 21 includes a ninth transistor T1, a tenth transistor T2, and a second capacitor C1.
  • the gate of the ninth transistor T1 receives the first drive signal P, and one of the source and drain of the ninth transistor T1 receives the second level VGH.
  • one of the source and drain of the tenth transistor T2 receives the second clock signal CK2.
  • the first electrode of the second capacitor C1 is connected to the other of the source and drain of the ninth transistor T1 and the other of the source and drain of the tenth transistor T2.
  • the second electrode of the second capacitor C1 is connected to the gate of the tenth transistor T2 and the gate of the eighth transistor T16.
  • the (3n-1)th gate driving unit GOA (3n-1) further includes a second feedback module 22, which receives the first driving signal P, the second driving signal D and the first clock signal CK1.
  • the second feedback module 22 is used to control the potentials of the first driving signal P and the second driving signal D to be opposite.
  • the second feedback module 22 includes a seventeenth transistor T51 and an eighteenth transistor T52.
  • the gates of the seventeenth transistor T51 and the eighteenth transistor T52 receive the second drive signal D.
  • One of the source and the drain of the eighteenth transistor T52 receives the first clock signal CK1
  • one of the source and the drain of the eighteenth transistor T52 is connected to one of the source and the drain of the seventeenth transistor T51
  • the other of the source and the drain of the seventeenth transistor T51 receives the first drive signal P1.
  • the (3n-1)th gate driving unit GOA (3n-1) further includes a third feedback module 26, which receives the second driving signal D, the first driving signal P and the second level VGH.
  • the third feedback module 26 is used to pull up the first driving signal P according to the second driving signal D.
  • the third feedback module 26 includes a nineteenth transistor T8, a gate of the nineteenth transistor T8 receives the second driving signal D, one of a source and a drain of the nineteenth transistor T8 receives the second level VGH, and the other of a source and a drain of the nineteenth transistor T8 receives the first driving signal P.
  • the (3n-1)th gate driving unit GOA (3n-1) further includes a fourth feedback module 16, which receives the second driving signal D, the first driving signal P and the second level VGH.
  • the fourth feedback module 16 includes a twentieth transistor T26, the gate of which receives the second driving signal D, one of the source and the drain of which receives the second level VGH, and the other of the source and the drain of which receives the first driving signal P.
  • the (3n-1)th stage gate driving unit GOA (3n-1) further includes a first voltage stabilizing module 23.
  • the first voltage stabilizing module 23 includes a 21st transistor T6 and a 4th capacitor C2.
  • the gate of the 21st transistor T6 is connected to the first electrode of the 4th capacitor C2, one of the source and the drain of the 21st transistor T6 receives the second clock signal CK2, and the other of the source and the drain of the 21st transistor T6 is connected to the second electrode of the 4th capacitor C2.
  • the (3n-1)th level gate driving unit GOA (3n-1) further includes a second voltage stabilizing module 24, the second voltage stabilizing module 24 includes a twenty-second transistor T11, the gate of the twenty-second transistor T11 receives the first level VGL, and the source and drain of the twenty-second transistor T11 are connected between the gate of the twenty-first transistor T6 and the other of the source and drain of the fourteenth transistor T4.
  • the (3n-1)th stage gate driving unit GOA (3n-1) further includes a third voltage stabilizing module 25.
  • the third voltage stabilizing module 25 includes a twenty-third transistor T7, a gate of the twenty-third transistor T7 receives the second clock signal CK2, and a source and a drain of the twenty-third transistor T7 are connected between the other of the source and the drain of the twenty-first transistor T6 and the gate of the fourth transistor T10.
  • the (3n-1)th level gate driving unit GOA (3n-1) further includes a fourth voltage stabilizing module 19, which includes a twenty-fourth transistor T12, the gate of which receives the first level VGL, and the source and drain of which are connected between the gate of the fifth transistor T9 and the other of the source and drain of the thirteenth transistor T3.
  • a fourth voltage stabilizing module 19 which includes a twenty-fourth transistor T12, the gate of which receives the first level VGL, and the source and drain of which are connected between the gate of the fifth transistor T9 and the other of the source and drain of the thirteenth transistor T3.
  • the (3n-1)th level gate driving unit GOA (3n-1) further includes a fifth voltage stabilizing module 17, the fifth voltage stabilizing module 17 includes a twenty-fifth transistor T23, the gate of the twenty-fifth transistor T23 receives the first level VGL, and the source and drain of the twenty-fifth transistor T23 are connected between the gate of the seventh transistor T25 and the other of the source and drain of the third transistor T20.
  • first transistor T18 to the twenty-fifth transistor T23 are all P-type transistors.
  • the fourth transistor T10 and the fifth transistor T9 are all P-type transistors.
  • the selection of the second gate driving unit GOA (2) means that the second gate driving unit GOA (2) outputs the display scanning signal WR1 (2) in the display scanning period S1, and the second gate driving unit GOA (2) is selected in the display scanning period S1, and the second gate driving unit GOA (2) outputs the compensation detection scanning signal WR2 (2) in the scanning blank period S2.
  • the first compensation detection selection signal LP1 , the second compensation detection selection signal LP2 , and the third compensation detection selection signal LP3 are all low level signals to initialize the position of the second transistor T19 of each gate driving unit.
  • the first compensation detection selection signal LP1 and the third compensation detection selection signal LP2 are both high level signals, and the second compensation detection selection signal LP2 is a low level signal.
  • the first stage transmission signal ST(1) is a low level signal
  • the first transistor T18 of the second stage gate driving unit GOA(2) is turned on, the first transistor T18 outputs a low level detection selection control signal M(2), and the first capacitor C4 stores the detection selection control signal M(2).
  • the switching control signal CKB is switched from the low level to the high level, the eleventh transistor T22 and the twelfth transistor T21 are turned off, and the input control module 11 is disconnected from the output module 14 .
  • the second transistor T19 of the second-stage gate driving unit GOA (2) is turned on, the output control signal RE is switched to a low level, the third transistor T20 of the second-stage gate driving unit GOA (2) is turned on, the third transistor T20 outputs a low-level compensation detection driving signal, and the seventh transistor T25 outputs a low-level compensation detection scanning signal WR2 (2) according to the low-level compensation detection driving signal.
  • the second scanning signal line GL2 connected to the second-stage gate driving unit GOA (2) outputs the low-level compensation detection scanning signal WR2 (2) to the corresponding data writing transistor K1 of the pixel driving circuit 200, the data writing transistor K1 is turned on, the compensation control transistor K2 is also turned on, and the detection chip 30 detects the initial threshold voltage of the data writing transistor K1.
  • the output module is connected to the input control module and the compensation detection control module.
  • the output module responds to the drive signal to output the display scan signal during the display scan period, and responds to the compensation detection drive signal to output the compensation detection scan signal during the scan blank period.
  • the pixel driving circuit is used to receive the display scan signal during the display scan period, and receive the compensation detection scan signal during the scan blank period. Through this design, the pixel driving circuit receives the display scan signal during the display scan period to provide conditions for the display panel to display, and the pixel driving circuit receives the compensation detection scan signal during the blank period to provide conditions for realizing random compensation detection. While realizing the display in one frame time, the compensation of the pixel driving circuit is realized, thereby improving the problem of uneven brightness display of the display panel during the display process.

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Abstract

提供了一种显示面板(100)。显示面板(100)的一帧时间包括显示扫描时段(S1)和扫描空白时段(S2)，显示面板(100)包括：多个级联的栅极驱动单元(GOA)，栅极驱动单元(GOA)包括：输入控制模块(11)，用于在显示扫描时段(S1)输出驱动信号(P、D)；补偿侦测控制模块(13)，用于在扫描空白时段(S2)输出补偿侦测驱动信号；以及输出模块(14)，与输入控制模块(11)以及补偿侦测控制模块(13)连接，用于在显示扫描时段(S1)响应于驱动信号(P、D)以输出显示扫描信号(WR1(3n-1))，并在扫描空白时段(S2)响应于补偿侦测驱动信号以输出补偿侦测扫描信号(WR2(3n-1))；以及像素驱动电路(200)，与栅极驱动单元(GOA)连接，用于在显示扫描时段(S1)接收显示扫描信号(WR1(3n-1))，并在扫描空白时段(S2)接收补偿侦测扫描信号(WR2(3n-1))。

Description

显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
目前，显示面板广泛地应用于不同的领域，例如，智能移动终端、笔记本以及增强现实显示等。然而，显示面板在显示过程中会出现显示亮度不均的问题。
因此，如何改善显示面板的亮度不均是需要解决的技术问题。
 发明概述
本申请的目的在于提供一种显示面板，以改善显示面板的亮度显示不均的问题。
本申请提供一种显示面板，所述显示面板的一帧时间包括显示扫描时段和扫描空白时段，所述显示面板包括：
多个级联的栅极驱动单元，所述栅极驱动单元包括：
输入控制模块，用于在所述显示扫描时段输出驱动信号；
补偿侦测控制模块，用于在所述扫描空白时段输出补偿侦测驱动信号；以及
输出模块，与所述输入控制模块以及所述补偿侦测控制模块连接，用于在所述显示扫描时段响应于所述驱动信号以输出显示扫描信号，并在所述扫描空白时段响应于所述补偿侦测驱动信号以输出补偿侦测扫描信号；以及
像素驱动电路，与所述栅极驱动单元连接，用于在所述显示扫描时段接收所述显示扫描信号，并在所述扫描空白时段接收所述补偿侦测扫描信号。
 附图说明
图1为本申请的一些实施例的显示面板的示意图；
图2为本申请的一些实施例的像素驱动电路的示意图；
图3为本申请的一些实施例的栅极驱动电路的示意图；
图4为本申请的一些实施例的第（3n-1）级栅极驱动单元GOA（3n-1）的电路示意图；
图5为本申请的一些实施例的栅极驱动电路的驱动时序图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1至图5所示，图1为本申请的一些实施例的显示面板的示意图，图2为本申请的一些实施例的像素驱动电路的示意图，图3为本申请的一些实施例的栅极驱动电路的示意图，图4为本申请的一些实施例的第（3n-1）级栅极驱动单元GOA（3n-1）的电路示意图，图5为本申请的一些实施例的栅极驱动电路的驱动时序图。
显示面板100为有机发光二极管显示面板，但不限于此，显示面板100也可以为液晶显示面板、微型发光二极管显示面板、次毫米发光二极管显示面板或者量子点显示面板。
请参照图1所示，显示面板100包括显示区100a和围绕显示区100a设置的非显示区100b。显示面板100包括位于显示区100a的像素驱动电路200，像素驱动电路200与数据信号线DL以及扫描信号线GL连接。
显示面板100还包括栅极驱动电路20，栅极驱动电路20设置于非显示区100b。栅极驱动电路20包括第一栅极驱动电路201和第二栅极驱动电路202，第一栅极驱动电路201和第二栅极驱动电路202分别位于显示区100a的相对两侧。
可以理解的是，栅极驱动电路20也可以只位于显示区100a的一侧。栅极驱动电路20的至少部分也可以设置于显示区100a。
请参阅图2所示，像素驱动电路200包括数据写入晶体管K1、驱动晶体管DT、补偿控制晶体管K2以及存储电容器Cst。
其中，驱动晶体管DT包括N型晶体管。数据写入晶体管K1和补偿控制晶体管K2均包括P型晶体管，便于减小数据写入晶体管K1和补偿控制晶体管K2的尺寸的同时，满足数据写入晶体管K1的充电需求，便于显示面板实现高频驱动。而且，数据写入晶体管K1和补偿控制晶体管K2的尺寸减小，有利于减小像素驱动电路占用的面积，进而增加像素驱动电路和像素的数目，满足显示面板实现高分辨显示的需求。
可以理解的是，数据写入晶体管K1和补偿控制晶体管K2也可以包括N型晶体管。在数据写入晶体管K1和补偿控制晶体管K2均包括N型晶体管的情况下，由于N型晶体管的充电电流较小，对N型晶体管的充电时间需要增加，充电时间增加对显示面板的驱动频率增大造成限制。另外，为了实现对N型晶体管较好的充电效果，需要增加N型晶体管的沟道宽度与沟道长度的比值，比值增大对显示面板的分辨率增大造成限制。
数据写入晶体管K1的栅极与扫描信号线GL连接，数据写入晶体管K1的源极和漏极中的一者与数据信号线DL连接，数据写入晶体管K1的源极和漏极中的另一者与驱动晶体管DT的栅极连接。
驱动晶体管DT的源极和漏极中的一者接收第一电源信号VDD，驱动晶体管DT的源极和漏极中的另一者接收第二电源信号VSS。其中，第一电源信号VDD为高电平信号，第二电源信号VSS为低电平信号。
补偿控制晶体管K2的栅极与位于显示区100a中的补偿控制信号线（未示意出）连接，补偿控制晶体管K2的源极和漏极中的一者与驱动晶体管DT的源极和漏极中的另一者连接且接收第二电源信号VSS，补偿控制晶体管K2的源极和漏极中的另一者与侦测芯片30连接。
存储电容器Cst连接于数据写入晶体管K1的源极和漏极中的另一者以及驱动晶体管DT的源极和漏极中的另一者连接之间。
发光器件OLED连接于驱动晶体管DT的源极和漏极中的另一者与第二电源信号VSS之间。
请参阅图3所示，栅极驱动电路20包括多个栅极驱动单元。多个栅极驱动单元包括第一级栅极驱动单元GOA（1）、第二级栅极驱动单元GOA（2）、第三级栅极驱动单元GOA（3）以及第（3n-1）级栅极驱动单元GOA（3n-1），n为大于或等于2的整数。
多个栅极驱动单元是级联的。每级栅极驱动单元输出一个级传信号至下级的栅极驱动单元。具体地，第一级栅极驱动单元GOA（1）接收起始信号STV，并输出第一级级传信号ST（1）至第二级栅极驱动单元GOA（2）。第二级栅极驱动单元GOA（2）接收第一级级传信号ST（1）并输出第二级级传信号ST（2）。第三级栅极驱动单元GOA（3）接收第二级级传信号ST（2）并输出第三级级传信号ST（3）。第（3n-1）级栅极驱动单元GOA（3n-1）接收第（3n-2）级级传信号ST（3n-2）并输出第（3n-1）级级传信号ST（3n-1）。
每级栅极驱动单元均与第一时钟信号线CKL1连接，以接收第一时钟信号CK1。每级栅极驱动单元均与第二时钟信号线CKL2连接，以接收第二时钟信号CK2。每级栅极驱动单元均与复位信号线Reset连接，以接收输出控制信号RE。每级栅极驱动单元均与切换控制信号线CKBL，以接收切换控制信号CKB。每级栅极驱动单元均与第一电平信号线VL连接，以接收第一电平VGL，第一电平VGL为低电平信号。每级栅极驱动单元均与第二电平信号线VL连接，以接收第二电平VGH，第二电平VGH为高电平信号。第（3n-2）级栅极驱动单元（未示意出）与第一补偿侦测选择信号线LSPL1连接，以接收第一补偿侦测选择信号LP1，例如，第一级栅极驱动单元GOA（1）接收第一补偿侦测选择信号LP1。第（3n-1）级栅极驱动单元GOA（3n-1）与第二补偿侦测选择信号线LSPL2连接，以接收第二补偿侦测选择信号LP2，例如，第二级栅极驱动单元GOA（2）接收第二补偿侦测选择信号LP2。第（3n）级栅极驱动单元（未示意出）与第三补偿侦测选择信号线LSPL3连接，以接收第三补偿侦测选择信号LP3，例如，第三级栅极驱动单元GOA（3）接收第三补偿侦测选择信号LP3。
第一级栅极驱动单元GOA（1）的输出端与第一扫描信号线GL1连接。第二级栅极驱动单元GOA（2）的输出端与第二扫描信号线GL2连接。第三级栅极驱动单元GOA（3）的输出端与第三扫描信号线GL3连接。第（3n-1）级栅极驱动单元GOA（3n-1）的输出端与第（3n-1）扫描信号线GL（3n-1）连接。
请参照图5所示，显示面板100的一帧时间包括显示扫描时段S1和扫描空白时段S2，扫描空白时段S2位于相邻两帧的显示扫描时段S1之间。举例而言，显示面板100的刷新率为120Hz时，一帧时间为8.3ms，显示扫描时段S1对应的时间为8ms，扫描空白时段S2对应的时间为0.3ms。
在显示扫描时段S1，栅极驱动电路20依次向多行像素驱动电路200输出显示扫描信号WR1。数据写入晶体管K1响应于显示扫描信号WR1而导通，将数据信号线DL传输的显示数据信号存储在存储电容器Cst中，以用于显示。
在扫描空白时段S2，随机性地控制栅极驱动电路20中所有栅极驱动单元中的一个栅极驱动单元GOA输出补偿侦测扫描信号WR2。接收补偿侦测扫描信号WR2的数据写入晶体管K1响应于补偿侦测扫描信号WR2而导通，补偿控制晶体管K2也导通，侦测芯片30对驱动晶体管DT的初始阈值电压进行侦测。在完成初始阈值电压的侦测后，对驱动晶体管DT的初始阈值电压进行外部补偿，使得显示面板在显示过程中亮度显示不均的问题。
因此，栅极驱动电路20除了用于在显示扫描时段S1输出显示扫描信号WR1，还可以随机地控制栅极驱动电路20中一个栅极驱动单元GOA在扫描空白时段S2输出补偿侦测扫描信号WR2，以对驱动晶体管DT的初始阈值电压进行侦测，有利于在一帧时间实现显示的同时，便于实现对驱动晶体管DT的驱动电压的外部补偿，进而改善显示面板在显示过程中亮度显示不均的问题。
另外，由于数据写入晶体管K1为P型晶体管，显示扫描信号WR1和补偿侦测扫描信号WR2均为低电平信号时，数据写入晶体管K1导通。
以下对第（3n-1）级栅极驱动单元GOA（3n-1）输出低电平的显示扫描信号WR1（3n-1）和补偿侦测扫描信号WR2（3n-1）进行详述。栅极驱动电路20中的其他栅极驱动单元GOA可以依次类推，本申请不做详细说明。
请参照图4所示，第（3n-1）级栅极驱动单元GOA（3n-1）包括输入控制模块11、级传模块12、补偿侦测控制模块13、输出模块14、切换模块15以及下拉模块18。
输入控制模块11用于在显示扫描时段S1输出驱动信号，驱动信号包括第一驱动信号P和第二驱动信号D。
具体地，输入控制模块11包括第十三晶体管T3和第十四晶体管T4。第十三晶体管T3的栅极接收第一时钟信号CK1，第十三晶体管T3的源极和漏极中的一者接收前级级传信号ST(3n-2)，第十三晶体管T3的源极和漏极中的另一者输出第二驱动信号D。第十四晶体管T4的栅极接收第一时钟信号CK1，第十四晶体管T4的源极和漏极中的一者接收第一电平VGL，第十四晶体管T4的源极和漏极中的另一者输出第一驱动信号P。
其中，前级级传信号ST(3n-2)为第（3n-2）级的栅极驱动单元输出的级传信号，但不限于此。当n等于1时，第十三晶体管T3的源极和漏极中的一者接收起始信号STV。
级传模块12与输入控制模块11连接。级传模块12用于在显示扫描时段S1响应于驱动信号，以输出本级级传信号ST(3n-1)。其中，本级级传信号ST(3n-1)包括高电平本级级传信号和小于高电平本级级传信号的低电平本级级传信号。
级传模块12包括第四晶体管T10和第五晶体管T9。第四晶体管T10的栅极接收第一驱动信号P，第四晶体管T10的源极和漏极中的一者接收第二电平VGH。第五晶体管T9的栅极接收第二驱动信号D，第五晶体管T9的源极和漏极的一者接收第一电平VGL。第五晶体管T9的源极和漏极中的另一者与第四晶体管T10的源极和漏极中的另一者连接。其中，第四晶体管T10的源极和漏极中的另一者输出高电平本级级传信号。第五晶体管T9的源极和漏极中的另一者输出低电平本级级传信号。
因此，级传模块12根据第二驱动信号D和第一驱动信号P以选择性地输出第二电平VGH和第一电平VGL中的一者。级传模块12根据第一驱动信号P输出第二电平VGH以作为高电平本级级传信号。级传模块12根据第二驱动信号D输出第一电平VGL以作为低电平本级级传信号。
第（3n-1）级栅极驱动单元GOA（3n-1）还包括第三电容器C3，第三电容器C3用于稳定第一驱动信号P的电压值，保证第四晶体管T10的源极和漏极中的另一者能稳定地输出高电平本级级传信号。
第三电容器C3的第一电极接收第一驱动信号P，第三电容器C3的第二电极接收第二电平VGH。具体地，第三电容器C3连接于第四晶体管T10的栅极与第二电平VGH之间。
补偿侦测控制模块13用于在扫描空白时段S2输出补偿侦测驱动信号。具体地，补偿侦测控制模块13包括侦测选择电路131以及侦测控制电路132。
侦测选择电路131用于在显示扫描时段S1响应于前级级传信号ST（3n-2）和补偿侦测选择信号，以输出侦测选择控制信号。
进一步地，前级级传信号ST（3n-2）包括低电平前级级传信号和大于低电平前级级传信号的高电平前级级传信号。侦测选择电路131用于在显示扫描时段S1响应于低电平前级级传信号和低电平的补偿侦测选择信号，以输出侦测选择控制信号。
具体地，侦测选择电路131包括第一晶体管T18。在显示扫描时段S1，第一晶体管T18的栅极接收补偿侦测选择信号。例如，对于第（3n-1）级栅极驱动单元GOA（3n-1），第一晶体管T18的栅极接收第二补偿侦测选择信号LP2。第一晶体管T18的源极和漏极中的一者接收前级级传信号ST（3n-2），第一晶体管T18的源极和漏极中的另一者输出侦测选择控制信号M。
在前级级传信号ST（3n-2）为低电平的情况下，控制第二补偿侦测选择信号LP2也为低电平信号，以使第一晶体管T18输出低电平的侦测选择控制信号。
需要说明的是，对于第二级栅极驱动单元GOA（2），第一晶体管T18也接收第二补偿侦测选择信号LP2。对于第一级栅极驱动单元GOA（1）和第（3n-2）级栅极驱动单元，第一晶体管T18接收第一补偿侦测选择信号LP1。对于第三级栅极驱动单元GOA（3）和第（3n）级栅极驱动单元，第一晶体管T18接收第三补偿侦测选择信号LP3。因此，相邻的三级栅极驱动单元GOA分别接收第一补偿侦测选择信号LP1、第二补偿侦测选择信号LP2以及第三补偿侦测选择信号LP3，但不限于此。
侦测控制电路132与侦测选择电路131以及输出模块14连接。侦测控制电路132用于在扫描空白时段S2响应于侦测选择控制信号和输出控制信号RE，以输出补偿侦测驱动信号。
具体地，侦测控制电路132包括第二晶体管T19、第一电容器C4以及第三晶体管T20。
在显示扫描时段S1，第二晶体管T19的栅极接收侦测选择控制信号，第二晶体管的源极和漏极中的一者接收第一电平VGL。
第一电容器C4用于存储侦测选择电路131在显示扫描时段S1输出的侦测选择控制信号M。在显示扫描时段S1，第一电容器C4的第一电极接收侦测选择控制信号M，第一电容器C4的第二电极接收第一电平VGL。
具体地，第一电容器C4与第二晶体管T19的栅极和第二晶体管T19的源极和漏极中的一者连接。
第三晶体管T20的源极和漏极中的一者与第二晶体管T19的源极和漏极中的另一者连接。在扫描空白时段S2，第三晶体管T20的栅极接收输出控制信号RE，第三晶体管的源极和漏极中的另一者输出补偿侦测驱动信号。
输出模块14与输入控制模块11以及补偿侦测控制模块13连接。输出模块14用于在显示扫描时段S1响应于驱动信号以输出显示扫描信号WR1(3n-1)，并在扫描空白时段S2响应于补偿侦测驱动信号以输出补偿侦测扫描信号WR2(3n-1)。
其中，显示扫描信号WR1(3n-1)包括有效显示扫描信号和无效显示扫描信号。数据写入晶体管K1接收有效显示扫描信号后导通，数据写入晶体管K1接收无效显示扫描信号后保持关闭。
输出模块14包括第六晶体管T24和第七晶体管T25。在显示扫描时段S1，第六晶体管T24的栅极接收第一驱动信号P，第六晶体管T24的源极和漏极中的一者接收第二电平VGH，第六晶体管T24的源极和漏极中的另一者输出无效显示扫描信号。在显示扫描时段S1，第七晶体管T25的栅极接收第二驱动信号D，第七晶体管T25的源极和漏极中的一者接收第一电平VGL，第七晶体管T25的源极和漏极中的另一者输出有效显示扫描信号。
由于第二电平VGH为高电平，无效显示扫描信号为高电平信号。第一电平VGL为低电平，有效显示扫描信号为低电平信号。
在扫描空白时段S2，第七晶体管T25接收补偿侦测驱动信号，第七晶体管T25的源极和漏极中的一者接收第一电平VGL，第七晶体管T25的源极和漏极中的另一者输出补偿侦测扫描信号WR2(3n-1)。由于第一电平VGL为低电平信号，补偿侦测扫描信号WR2(3n-1)也为低电平信号。
在一些实施例中，第（3n-1）级栅极驱动单元GOA（3n-1）还包括第五电容器C5，第五电容器C5用于稳定第一驱动信号P的电压值。第五电容器C5的第一电极接收第一驱动信号P，第五电容器C5的第二电极接收第二电平VGH。
具体地，第五电容器C5连接于第二电平VGH与第六晶体管T24的栅极之间。
在一些实施例中，第（3n-1）级栅极驱动单元GOA（3n-1）还包括切换模块15，连接于输入控制模块11以及输出模块14之间。切换模块15用于在显示扫描时段S1连接输入控制模块11与输出模块14，并用于在扫描空白时段S2断开输入控制模块11与输出模块14。
切换模块15包括第十一晶体管T22和第十二晶体管T21。第十一晶体管T22的栅极接收切换控制信号CKB，第十一晶体管T22的源极和漏极连接于第六晶体管T24的栅极与输入控制模块11之间。第十二晶体管T21的栅极接收切换控制信号CKB，第十二晶体管T21的源极和漏极连接于第七晶体管T25的栅极与输入控制模块11之间。第十一晶体管T22在显示扫描时段S1导通并传输第一驱动信号P，且在扫描空白时段S2关闭。第十二晶体管T21在显示扫描时段S1导通并传输第二驱动信号D，且在扫描空白时段S2关闭。
具体地，第十一晶体管T22的栅极接收切换控制信号CKB，第十一晶体管T22的源极和漏极中的一者与第十四晶体管T4的源极和漏极中的另一者连接，第十一晶体管T22的源极和漏极中的另一者与第六晶体管T24的栅极连接。第十二晶体管T21的栅极接收切换控制信号CKB，第十二晶体管T21的源极和漏极中的一者与第十三晶体管T3的源极和漏极中的另一者连接，第十二晶体管T21的源极和漏极中的另一者与第七晶体管T25的栅极以及第三晶体管T20的源极和漏极中的另一者连接。
在一些实施例中，第（3n-1）级栅极驱动单元GOA（3n-1）还包括第一反馈模块21和与第一反馈模块21连接的下拉模块18。第一反馈模块21接收第一驱动信号P，并输出反馈信号。下拉模块18接收反馈信号，并输出下拉信号Q1，以对第二驱动信号D进行下拉。
下拉模块18包括第八晶体管T16。在显示扫描时段S1，第八晶体管T16的栅极和第八晶体管T16的源极和漏极中的一者接收反馈信号，第八晶体管T16的源极和漏极中的另一者输出下拉信号Q1至第七晶体管T25的栅极，下拉信号Q1对第二驱动信号D进行下拉，以保证第七晶体管T25在显示扫描时段S1稳定地输出有效显示扫描信号。
下拉模块18还包括第十五晶体管T14和第十六晶体管T15。第十五晶体管T14的栅极接收第一时钟信号CK1，第十五晶体管T14的源极和漏极中的一者接收前级级传信号ST（3n-2）。第十六晶体管T15的栅极接收第一电平VGL，第十五晶体管T14的源极和漏极连接于第十五晶体管T14的源极和漏极中的另一者与第八晶体管T16的栅极之间。
第一反馈模块21包括第九晶体管T1、第十晶体管T2以及第二电容器C1。在显示扫描时段S1，第九晶体管T1的栅极接收第一驱动信号P，第九晶体管T1的源极和漏极中的一者接收第二电平VGH。在显示扫描时段S1，第十晶体管T2的源极和漏极中的一者接收第二时钟信号CK2。第二电容器C1的第一电极与第九晶体管T1的源极和漏极中的另一者以及第十晶体管T2的源极和漏极中的另一者连接。第二电容器C1的第二电极与第十晶体管T2的栅极以及第八晶体管T16的栅极连接。
第（3n-1）级栅极驱动单元GOA（3n-1）还包括第二反馈模块22，第二反馈模块22接收第一驱动信号P、第二驱动信号D以及第一时钟信号CK1。在显示扫描时段S1，第二反馈模块22用于控制第一驱动信号P和第二驱动信号D的电位是相反的。
具体地，第二反馈模块22包括第十七晶体管T51和第十八晶体管T52。第十七晶体管T51和第十八晶体管T52的栅极接收第二驱动信号D。第十八晶体管T52的源极和漏极中的一者接收第一时钟信号CK1，第十八晶体管T52的源极和漏极中的一者与第十七晶体管T51的源极和漏极中的一者连接，第十七晶体管T51的源极和漏极中的另一者接收第一驱动信号P1。
第（3n-1）级栅极驱动单元GOA（3n-1）还包括第三反馈模块26，第三反馈模块26接收第二驱动信号D、第一驱动信号P以及第二电平VGH。第三反馈模块26用于根据第二驱动信号D上拉第一驱动信号P。第三反馈模块26包括第十九晶体管T8，第十九晶体管T8的栅极接收第二驱动信号D，第十九晶体管T8的源极和漏极中的一者接收第二电平VGH，第十九晶体管T8的源极和漏极中的另一者接收第一驱动信号P。
第（3n-1）级栅极驱动单元GOA（3n-1）还包括第四反馈模块16，第四反馈模块16接收第二驱动信号D、第一驱动信号P以及第二电平VGH。第四反馈模块16包括第二十晶体管T26，第二十晶体管T26的栅极接收第二驱动信号D，第二十晶体管T26的源极和漏极中的一者接收第二电平VGH，第二十晶体管T26的源极和漏极中的另一者接收第一驱动信号P。
第（3n-1）级栅极驱动单元GOA（3n-1）还包括第一稳压模块23。第一稳压模块23包括第二十一晶体管T6和第四电容器C2。第二十一晶体管T6的栅极与第四电容器C2的第一电极连接，第二十一晶体管T6的源极和漏极中的一者接收第二时钟信号CK2，第二十一晶体管T6的源极和漏极中的另一者与第四电容器C2的第二电极连接。
第（3n-1）级栅极驱动单元GOA（3n-1）还包括第二稳压模块24，第二稳压模块24包括第二十二晶体管T11，第二十二晶体管T11的栅极接收第一电平VGL，第二十二晶体管T11的源极和漏极连接于第二十一晶体管T6的栅极和第十四晶体管T4的源极和漏极中的另一者之间。
第（3n-1）级栅极驱动单元GOA（3n-1）还包括第三稳压模块25。第三稳压模块25包括第二十三晶体管T7，第二十三晶体管T7的栅极接收第二时钟信号CK2，第二十三晶体管T7的源极和漏极连接于第二十一晶体管T6的源极和漏极中的另一者与第四晶体管T10的栅极之间。
第（3n-1）级栅极驱动单元GOA（3n-1）还包括第四稳压模块19，第四稳压模块19包括第二十四晶体管T12，第二十四晶体管T12的栅极接收第一电平VGL，第二十四晶体管T12的源极和漏极连接于第五晶体管T9的栅极与第十三晶体管T3的源极和漏极中的另一者之间。
第（3n-1）级栅极驱动单元GOA（3n-1）还包括第五稳压模块17，第五稳压模块17包括第二十五晶体管T23，第二十五晶体管T23的栅极接收第一电平VGL，第二十五晶体管T23的源极和漏极连接于第七晶体管T25的栅极和第三晶体管T20的源极和漏极中的另一者之间。
需要说明的是，上述第一晶体管T18至第二十五晶体管T23均为P型晶体管。第四晶体管T10和第五晶体管T9均为P型晶体管。
请再次参照图5所示，以选中第二栅极驱动单元GOA（2）为例进行说明。其中，选中第二栅极驱动单元GOA（2）意味着，第二栅极驱动单元GOA（2）在显示扫描时段S1输出显示扫描信号WR1（2），且在显示扫描时段S1选中第二栅极驱动单元GOA（2），并使第二栅极驱动单元GOA（2）在扫描空白时段S2输出补偿侦测扫描信号WR2（2）。
在显示扫描时段S1的第一时段t1，第一补偿侦测选择信号LP1、第二补偿侦测选择信号LP2以及第三补偿侦测选择信号LP2均为低电平信号，以对每个栅极驱动单元的第二晶体管T19的点位进行初始化。
在显示扫描时段S1的第二时段t2，第一补偿侦测选择信号LP1和第三补偿侦测选择信号LP2均为高电平信号，第二补偿侦测选择信号LP2为低电平信号。在第一级级传信号ST（1）为低电平信号时，第二级栅极驱动单元GOA（2）的第一晶体管T18导通，第一晶体管T18输出低电平的侦测选择控制信号M（2），第一电容器C4存储侦测选择控制信号M（2）。
在显示扫描时段S1的第三时段t3，切换控制信号CKB从低电平切换为高电平，第十一晶体管T22和第十二晶体管T21关闭，输入控制模块11与输出模块14断开连接。
在扫描空白时段S2的第四时段t4，第二级栅极驱动单元GOA（2）的第二晶体管T19导通，输出控制信号RE切换为低电平，第二级栅极驱动单元GOA（2）的第三晶体管T20导通，第三晶体管T20输出低电平的补偿侦测驱动信号，第七晶体管T25根据低电平的补偿侦测驱动信号输出低电平的补偿侦测扫描信号WR2（2）。与第二级栅极驱动单元GOA（2）连接的第二扫描信号线GL2将低电平的补偿侦测扫描信号WR2（2）输出至对应的像素驱动电路200的数据写入晶体管K1，数据写入晶体管K1导通，补偿控制晶体管K2也导通，侦测芯片30对数据写入晶体管K1的初始阈值电压进行侦测。
本申请的一些实施例的有益效果：由于新增设一个补偿侦测控制模块，输出模块与输入控制模块以及补偿侦测控制模块连接。输出模块在显示扫描时段响应于驱动信号以输出显示扫描信号，并在扫描空白时段响应于补偿侦测驱动信号以输出补偿侦测扫描信号。像素驱动电路用于在显示扫描时段接收显示扫描信号，并在扫描空白时段接收补偿侦测扫描信号。通过这种设计，在显示扫描时段像素驱动电路接收显示扫描信号以便为显示面板进行显示提供条件，且在空白时段像素驱动电路接收补偿侦测扫描信号以便为实现随机补偿侦测提供条件。在一帧时间实现显示的同时，实现对像素驱动电路的补偿，进而改善显示面板在显示过程中亮度显示不均的问题。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其中，所述显示面板的一帧时间包括显示扫描时段和扫描空白时段，所述显示面板包括：
    多个级联的栅极驱动单元，所述栅极驱动单元包括：
    输入控制模块，用于在所述显示扫描时段输出驱动信号；
    补偿侦测控制模块，用于在所述扫描空白时段输出补偿侦测驱动信号；以及
    输出模块，与所述输入控制模块以及所述补偿侦测控制模块连接，用于在所述显示扫描时段响应于所述驱动信号以输出显示扫描信号，并在所述扫描空白时段响应于所述补偿侦测驱动信号以输出补偿侦测扫描信号；以及
    像素驱动电路，与所述栅极驱动单元连接，用于在所述显示扫描时段接收所述显示扫描信号，并在所述扫描空白时段接收所述补偿侦测扫描信号。
  2. 根据权利要求1所述的显示面板，其中，所述栅极驱动单元还包括：级传模块，用于在所述显示扫描时段响应于所述驱动信号以输出本级级传信号；
    所述补偿侦测控制模块包括：
    侦测选择电路，用于在所述显示扫描时段响应于前级级传信号和补偿侦测选择信号以输出所述侦测选择控制信号；以及
    侦测控制电路，用于在所述扫描空白时段响应于所述侦测选择控制信号和输出控制信号以输出所述补偿侦测驱动信号。
  3. 根据权利要求2所述的显示面板，其中，所述侦测选择电路包括：
    第一晶体管，在所述显示扫描时段，所述第一晶体管的栅极接收所述补偿侦测选择信号，所述第一晶体管的源极和漏极中的一者接收所述前级级传信号，所述第一晶体管的源极和漏极中的另一者输出所述侦测选择控制信号。
  4. 根据权利要求2所述的显示面板，其中，所述侦测控制电路包括：
    第二晶体管，在所述显示扫描时段所述第二晶体管的栅极接收所述侦测选择控制信号，所述第二晶体管的源极和漏极中的一者接收第一电平；
    第一电容器，在所述显示扫描时段所述第一电容器的第一电极接收所述侦测选择控制信号，所述第一电容器的第二电极接收所述第一电平；以及
    第三晶体管，所述第三晶体管的源极和漏极中的一者与所述第二晶体管的源极和漏极中的另一者连接，在所述扫描空白时段，所述第三晶体管的栅极接收所述输出控制信号，所述第三晶体管的源极和漏极中的另一者输出所述补偿侦测驱动信号。
  5. 根据权利要求3所述的显示面板，其中，所述侦测控制电路包括：
    第二晶体管，在所述显示扫描时段所述第二晶体管的栅极接收所述侦测选择控制信号，所述第二晶体管的源极和漏极中的一者接收第一电平；
    第一电容器，在所述显示扫描时段所述第一电容器的第一电极接收所述侦测选择控制信号，所述第一电容器的第二电极接收所述第一电平；以及
    第三晶体管，所述第三晶体管的源极和漏极中的一者与所述第二晶体管的源极和漏极中的另一者连接，在所述扫描空白时段，所述第三晶体管的栅极接收所述输出控制信号，所述第三晶体管的源极和漏极中的另一者输出所述补偿侦测驱动信号。
  6. 根据权利要求2所述的显示面板，其中，所述驱动信号包括第一驱动信号和第二驱动信号，所述本级级传信号包括高电平本级级传信号和小于所述高电平本级级传信号的低电平本级级传信号，所述级传模块包括：
    第四晶体管，所述第四晶体管的栅极接收所述第一驱动信号，所述第四晶体管的源极和漏极中的一者接收第二电平，所述第四晶体管的源极和漏极中的另一者输出所述高电平本级级传信号；
    第五晶体管，所述第五晶体管的栅极接收所述第二驱动信号，所述第五晶体管的源极和漏极的一者接收第一电平，所述第五晶体管的源极和漏极中的另一者输出所述低电平本级级传信号。
  7. 根据权利要求6所述的显示面板，其中，所述前级级传信号包括低电平前级级传信号，所述侦测选择电路用于在所述显示扫描时段响应于所述低电平前级级传信号和所述补偿侦测选择信号以输出所述侦测选择控制信号。
  8. 根据权利要求6所述的显示面板，其中，所述显示扫描信号包括有效显示扫描信号和无效显示扫描信号，所述输出模块包括：
    第六晶体管，在所述显示扫描时段，所述第六晶体管的栅极接收所述第一驱动信号，所述第六晶体管的源极和漏极中的一者接收第二电平，所述第六晶体管的源极和漏极中的另一者输出所述无效显示扫描信号；以及
    第七晶体管，在所述显示扫描时段，所述第七晶体管的栅极接收所述第二驱动信号，所述第七晶体管的源极和漏极中的一者接收第一电平，所述第七晶体管的源极和漏极中的另一者输出所述有效显示扫描信号。
  9. 根据权利要求8所述的显示面板，其中，所述栅极驱动单元还包括：
    反馈模块，所述反馈模块用于在所述显示扫描时段接收所述第一驱动信号和时钟信号，并输出反馈信号；以及
    下拉模块，所述下拉模块用于在所述显示扫描时段接收所述反馈信号，以对所述第七晶体管的栅极接收的所述第二驱动信号进行下拉。
  10. 根据权利要求9所述的显示面板，其中，所述下拉模块包括：
    第八晶体管，在所述显示扫描时段，所述第八晶体管的栅极、源极和漏极中的一者接收所述反馈信号，所述第八晶体管的源极和漏极中的另一者与所述第七晶体管的栅极连接。
  11. 根据权利要求10所述的显示面板，其中，所述反馈模块包括：
    第九晶体管，在所述显示扫描时段，所述第九晶体管的栅极接收所述第一驱动信号，所述第九晶体管的源极和漏极中的一者接收第二电平；
    第十晶体管，在所述显示扫描时段，所述第十晶体管的源极和漏极中的一者接收所述时钟信号；以及
    第二电容器，所述第二电容器的第一电极与所述第九晶体管的源极和漏极中的另一者以及所述第十晶体管的源极和漏极中的另一者连接，所述第二电容器的第二电极与所述第十晶体管的栅极以及所述第八晶体管的栅极连接。
  12. 根据权利要求8所述的显示面板，其中，所述栅极驱动单元还包括：切换模块，用于在所述显示扫描时段连接所述输入控制模块与所述输出模块，并用于在所述扫描空白时段断开所述输入控制模块与所述输出模块。
  13. 根据权利要求12所述的显示面板，其中，所述切换模块包括：
    第十一晶体管，所述第十一晶体管的栅极接收切换控制信号，所述第十一晶体管的源极和漏极连接于所述第六晶体管的栅极与所述输入控制模块之间；以及
    第十二晶体管，所述第十二晶体管的栅极接收切换控制信号，所述第十二晶体管的源极和漏极连接于所述第七晶体管的栅极与所述输入控制模块之间。
  14. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括：数据写入晶体管，所述数据写入晶体管的栅极在所述显示扫描时段接收所述显示扫描信号，并在所述扫描空白时段接收所述补偿侦测扫描信号，所述数据写入晶体管的源极和漏极中的一者接收数据信号；
    驱动晶体管，所述驱动晶体管的栅极与所述数据写入晶体管的源极和漏极中的另一者连接，所述驱动晶体管的源极和漏极中的一者接收第一电源信号；
    补偿控制晶体管，所述补偿控制晶体管的栅极接收补偿控制信号，所述补偿控制晶体管的源极和漏极中的一者以及所述驱动晶体管的源极和漏极中的另一者接收第二电源信号，所述补偿控制晶体管的源极和漏极中的另一者与侦测芯片连接；以及
    存储电容器，所述存储电容器连接于所述数据写入晶体管的源极和漏极中的另一者以及所述驱动晶体管的源极和漏极中的另一者连接之间。
  15. 根据权利要求14所述的显示面板，其中，所述数据写入晶体管和所述补偿控制晶体管均包括P型晶体管。
  16. 根据权利要求14所述的显示面板，其中，所述数据写入晶体管和所述补偿控制晶体管均包括N型晶体管。
  17. 根据权利要求13所述的显示面板，其中，所述输入控制模块包括：
    第十三晶体管，所述第十三晶体管的栅极接收第一时钟信号，所述第十三晶体管的源极和漏极中的一者接收所述前级级传信号，所述第十三晶体管的源极和漏极中的另一者输出所述第二驱动信号；
    第十四晶体管，所述第十四晶体管的栅极接收所述第一时钟信号，所述第十四晶体管的源极和漏极中的一者接收所述第一电平，所述第十四晶体管的源极和漏极中的另一者输出所述第一驱动信号。
  18. 根据权利要求10所述的显示面板，其中，所述下拉模块还包括：
    第十五晶体管，所述第十五晶体管的栅极接收第一时钟信号，所述第十五晶体管的源极和漏极中的一者接收所述前级级传信号；
    第十六晶体管，所述第十六晶体管的栅极接收第一电平，所述第十五晶体管的源极和漏极连接于所述第十五晶体管的源极和漏极中的另一者与所述第八晶体管的栅极之间。
  19. 根据权利要求17所述的显示面板，其中，所述栅极驱动单元还包括第一稳压模块，所述第一稳压模块包括第二十一晶体管和第四电容器，所述第二十一晶体管的栅极与所述第四电容器的第一电极连接，所述第二十一晶体管的源极和漏极中的一者接收第二时钟信号，所述第二十一晶体管的源极和漏极中的另一者与所述第四电容器的第二电极连接。
  20. 根据权利要求19所述的显示面板，其中，所述栅极驱动单元还包括第二稳压模块，所述第二稳压模块包括第二十二晶体管，所述第二十二晶体管的栅极接收第一电平，所述第二十二晶体管的源极和漏极连接于所述第二十一晶体管的栅极和所述第十四晶体管的源极和漏极中的另一者之间。
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