WO2024262609A1 - ビームフォーマ集積回路及びフェーズドアレイアンテナモジュール - Google Patents

ビームフォーマ集積回路及びフェーズドアレイアンテナモジュール Download PDF

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Publication number
WO2024262609A1
WO2024262609A1 PCT/JP2024/022560 JP2024022560W WO2024262609A1 WO 2024262609 A1 WO2024262609 A1 WO 2024262609A1 JP 2024022560 W JP2024022560 W JP 2024022560W WO 2024262609 A1 WO2024262609 A1 WO 2024262609A1
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Prior art keywords
counter
count value
beamformer
adc
signal
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English (en)
French (fr)
Japanese (ja)
Inventor
健 佐久間
幹太 廣木
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Fujikura Ltd
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Fujikura Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
    • H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits

Definitions

  • the present invention relates to a beamformer integrated circuit and a phased array antenna module.
  • a phased array antenna is an antenna that can freely change the beam pattern (antenna directivity) by adjusting at least one of the strength and phase of the signal (transmitted signal) supplied to multiple antenna elements or the signal (received signal) supplied from multiple antenna elements.
  • phased array antennas have been used in the automotive, communications, and various other fields.
  • a phased array antenna module is a module that includes multiple antenna elements and a beamformer integrated circuit.
  • the beamformer integrated circuit includes multiple phase controllers corresponding to the multiple antenna elements, and a circuit for setting phase settings for the multiple phase controllers. In addition, it may also have intensity controllers corresponding to the multiple antenna elements.
  • the required beam pattern is formed by setting appropriate settings for the phase controller and intensity controller and adjusting the phase and intensity of the multiple signals supplied from (or to) the multiple antenna elements.
  • Patent Documents 1 and 2 disclose a phased array antenna module equipped with a power detector that detects the power of the signal supplied to each antenna element.
  • the phased array antenna module disclosed in Patent Document 1 uses a power detector for self-diagnosis, and the phased array antenna module disclosed in Patent Document 2 uses a power detector (PD) for calibration.
  • PD power detector
  • the beamformer integrated circuit is provided with an analog-to-digital converter (ADC) that converts the detection signal of the power detector into a digital signal.
  • ADC analog-to-digital converter
  • the analog-to-digital converter is a complex circuit and therefore has a relatively large area. For this reason, in the phased array antenna module disclosed in the above-mentioned Patent Document 2, a single analog-to-digital converter is associated with a plurality of power detectors, and the power detector connected to the analog-to-digital converter is switched.
  • the upper control device that controls the phased array antenna module needs to repeat the following processes (1) to (3) as many times as the number of antenna elements (the number of power detectors).
  • (1) Specify a power detector to be connected to the analog-to-digital converter.
  • (2) Wait until the conversion process of the analog-to-digital converter is completed.
  • (3) Obtain the conversion result of the analog-to-digital converter.
  • the load (control communication cost) of the control communication performed between the upper control device and the phased array antenna module was large, and there was a demand for simplification of the control communication and reduction in the time required.
  • the present invention was made in consideration of the above circumstances, and aims to provide a beamformer integrated circuit and a phased array antenna module that can reduce control communication costs compared to conventional methods.
  • a first aspect of the present invention is a beamformer integrated circuit that includes a plurality of power detectors provided corresponding to a plurality of power amplifiers, a converter that converts the detection results of the power detectors into a digital signal, a counter, a selector that selects the power detector to be connected to the converter according to the count value of the counter, and a counter control circuit that controls the count value of the counter.
  • a selector is provided that selects the power detector to be connected to the converter according to the count value of a counter, and the count value of the counter is controlled by a counter control circuit. Therefore, even without instructions from a higher-level control device, the power detector to be connected to the converter can be switched by controlling the count value of the counter. This makes it possible to reduce control communication costs compared to conventional methods.
  • a second aspect of the present invention is a beamformer integrated circuit according to the first aspect, in which the counter control circuit increments the count value or sets the count value to zero when the converter outputs a signal indicating completion of conversion to the digital signal.
  • a third aspect of the present invention is a beamformer integrated circuit according to the first aspect, in which the counter control circuit increments the count value or sets the count value to zero when a request for acquiring the digital signal converted by the converter is received from a higher-level control device.
  • a fourth aspect of the present invention is a beamformer integrated circuit according to the third aspect, in which the counter control circuit transmits, when the acquisition request is received, the digital signal converted by the converter and the count value corresponding to the power detector connected to the converter to the higher-level control device.
  • the fifth aspect of the present invention is a phased array antenna module comprising a plurality of antenna elements and a beamformer integrated circuit according to any one of the first to fourth aspects connected to the plurality of antenna elements.
  • the present invention has the advantage of being able to reduce control communication costs compared to conventional methods.
  • FIG. 1 is a system configuration diagram showing a configuration of a phased array antenna module according to an embodiment of the present invention.
  • 1 is a block diagram showing a configuration of a main part of a beamformer integrated circuit according to an embodiment of the present invention
  • 2 is a block diagram showing a configuration of a main part of an analog circuit section provided in an RF front end of a beamformer IC.
  • FIG. 5 is a flowchart showing a procedure in which a control device acquires a detection signal of power detected by a phased array antenna module in one embodiment of the present invention.
  • the phased array antenna module is provided in a wireless communication device that uses, for example, millimeter wave bands and is capable of beamforming, which allows the beam pattern to be freely changed.
  • the phased array antenna module has, for example, a substrate such as a known printed circuit board, multiple ICs (Integrated Circuits) mounted on one side, and an antenna array mounted on the other side.
  • the multiple ICs and antenna array that make up the phased array antenna module are formed by using known materials and known methods. Furthermore, the electrical connection structure between the multiple ICs and the electrical connection structure between the ICs and the antenna array are not particularly limited. A known connection structure is used as the electrical connection structure.
  • Phased array antenna module 1 is a system configuration diagram showing the configuration of a phased array antenna module according to an embodiment of the present invention. As shown in Fig. 1, the phased array antenna module 1 includes eight beamformer ICs 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H (hereinafter referred to as beamformer ICs 10A to 10H), an antenna array 20, a frequency conversion IC 30, and an RF signal coupler/splitter 40.
  • the phased array antenna module 1 is connected to the control device 50 via a signal line 51, a control line 52, and a power line 53. Between the control device 50 and the phased array antenna module 1, an RF signal at an IF (intermediate frequency) signal frequency is transmitted and received via the signal line 51. Between the control device 50 and the phased array antenna module 1, communication messages related to control are transmitted and received via the control line 52. Power is supplied from the control device 50 to the phased array antenna module 1 via the power line 53.
  • IF intermediate frequency
  • Beamformer ICs 10A-10H are ICs that control the beam pattern of antenna array 20.
  • a plurality of antenna elements 21 that constitute antenna array 20 are connected to each of beamformer ICs 10A-10H.
  • antenna array 20 is composed of a total of 128 antenna elements 21, including 64 antenna elements 21 for horizontal polarization and 64 antenna elements 21 for vertical polarization. Details of beamformer ICs 10A-10H will be described later.
  • the frequency conversion IC 30 is an IC that performs frequency conversion between an RF signal at an IF signal frequency and an RF signal at a frequency transmitted and received by the beamformer ICs 10A-10H and the antenna array 20.
  • the RF signal coupler/splitter 40 distributes the RF signal output from the frequency conversion IC 30 to each of the beamformer ICs 10A-10H.
  • the RF signal coupler/splitter 40 also combines the RF signals received by each of the beamformer ICs 10A-10H and inputs them to the frequency conversion IC 30.
  • Beamformer IC> 2 is a block diagram showing the main configuration of a beamformer integrated circuit according to an embodiment of the present invention.
  • the eight beamformer ICs 10A to 10H have the same configuration. Therefore, in the following description, one of the beamformer ICs 10A to 10H, i.e., the beamformer IC 10, may be described. Descriptions of the other seven beamformer ICs may be omitted.
  • the beamformer IC 10 comprises 16 RF front ends 5A-5P and a digital circuit 6.
  • the 16 RF front ends 5A-5P have the same configuration. For this reason, in the following explanation, one of the 16 RF front ends 5A-5P, i.e., RF front end 5, may be explained. Explanations of the other 15 RF front ends may be omitted.
  • each of the 16 RF front ends 5A-5P is connected to each of the 16 antenna elements 21A-21P, so that there is a one-to-one correspondence between one antenna element 21 and one RF front end 5.
  • the 16 antenna elements 21A-21P eight antenna elements (e.g., antenna elements 21A-21H) are antenna elements for horizontal polarization, and the remaining eight antenna elements (e.g., antenna elements 21I-21P) are antenna elements for vertical polarization.
  • the 16 antenna elements 21A-21P have the same or similar configurations. For this reason, in the following description, one of the 16 antenna elements 21A-21P, i.e., antenna element 21, may be described. Descriptions of the other 15 antenna elements may be omitted.
  • the antenna elements 21A-21P may have the same configuration. For each of the antenna elements 21A-21P, the configuration of the antenna element for horizontal polarization and the configuration of the antenna element for vertical polarization may be slightly different from each other.
  • each of the 16 RF front ends 5A-5P is connected to each of the 16 antenna elements 21A-21P in a one-to-one correspondence. Therefore, in the entire phased array antenna module 1 having eight beamformer ICs 10A-10H, each of the 128 antenna elements 21 that make up the antenna array 20 is connected to each of the 16 RF front ends 5A-5P in each of the eight beamformer ICs 10A-10H.
  • the 128 antenna elements 21 that make up the antenna array 20 are divided into 64 antenna elements 21 that transmit and receive horizontally polarized radio waves, and 64 antenna elements 21 that transmit and receive vertically polarized radio waves.
  • the eight beamformer ICs 10A-10H control the transmission and reception of horizontally polarized radio waves in the 64 antenna elements 21, and also control the transmission and reception of vertically polarized radio waves in the 64 antenna elements 21.
  • the beamformer ICs 10A-10H set the gain and phase of each of the 64 antenna elements so that the direction of the composite radio waves transmitted or received from the 64 antenna elements 21 is a specified direction.
  • the RF front-end 5 includes a digital circuit section 11 and an analog circuit section 12.
  • the digital circuit section 11 transmits and receives communication messages related to control with the control device 50 via the control line 52 shown in FIG. 1.
  • the digital circuit section 11 controls the RF front-end 5 based on the communication messages transmitted from the control device 50.
  • communication messages related to control are sent and received between the phased array antenna module 1 and the control device 50 by parallel communication.
  • the digital circuit unit 11 sends and receives communication messages related to control between the control device 50 by parallel communication.
  • the communication between the phased array antenna module 1 and the control device 50 is not limited to parallel communication. It may also be serial communication such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit).
  • the digital circuit section 11 is connected to the digital circuit 6 by wiring inside the beamformer IC 10.
  • the digital circuit 6 relays communication between the digital circuit section 11 and the control device 50.
  • the digital circuit 6 communicates with the digital circuit section 11 based on the contents of a communication message sent from the control device 50.
  • a single communication transaction sent from the control device 50 to the phased array antenna module 1 includes additional information, a command, and data.
  • the communication transaction has a fixed bit length.
  • the command is a register address when instructing writing to a register or reading from a register.
  • the command is a numerical value indicating an operation instruction to the beamformer IC 10 or the RF front end 5.
  • the command and data have a fixed length. In this embodiment, the command is 8 bits and the data is 8 bits.
  • the digital circuit unit 11 has a memory area (not shown) that stores a beam table used for beamforming.
  • the beam table is a lookup table that stores multiple combinations of phase shift setting values and gain setting values that are set according to the beam pattern of the antenna array 20 to be controlled.
  • a beam table (beam table with 2048 items) that specifies 2048 combinations of phase shift setting values and gain setting values is stored in the memory area. The beam table is written to or read from the memory area using an 11-bit address.
  • the above-mentioned memory area is realized, for example, using SRAM (Static Random Access Memory). It is preferable that the memory area is realized using SRAM, but it may also be realized using a register, DRAM (Dynamic Random Access Memory), flash memory, or ROM (Read Only Memory).
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • flash memory flash memory
  • ROM Read Only Memory
  • the analog circuit unit 12 is a circuit that outputs an RF signal to the antenna element 21 connected to the RF front end 5 and receives an RF signal output from the antenna element 21. Under the control of the digital circuit unit 11, the analog circuit unit 12 adjusts the gain and phase of the RF signal transmitted and received by the antenna element 21 connected to the RF front end 5.
  • FIG. 3 is a block diagram showing the main configuration of an analog circuit section provided in the RF front end of the beamformer IC. Note that FIG. 3 also shows a detection circuit that detects the power of the signal supplied to the antenna element 21.
  • the RF front ends 5A to 5P provided in the beamformer IC 10 have the same configuration. For this reason, the following explanation may only describe one of the analog circuit sections 12 provided in the 16 RF front ends 5A to 5P, i.e., the analog circuit section 12 provided in the RF front end 5. Explanations of the analog circuit sections 12 provided in the other 15 RF front ends may be omitted.
  • the analog circuit section 12 includes a transmission circuit 61, a phase shifter 62, a variable gain amplifier 63, a power amplifier 64, a switch (SW) 65, a low noise amplifier 66, a variable gain amplifier 67, a phase shifter 68, a reception circuit 69, and a power detector (PD) 70.
  • FIG. 3 also illustrates a memory area 13 provided in the digital circuit section 11 of the RF front end 5.
  • the memory area 13 stores a beam table used for beamforming.
  • the beam table is a lookup table that stores multiple combinations of phase shift setting values and gain setting values that are set according to the beam pattern of the antenna array 20 to be controlled.
  • the transmission circuit 61, phase shifter 62, variable gain amplifier 63, and power amplifier 64 are provided on the transmission path R1, and the low noise amplifier 66, variable gain amplifier 67, phase shifter 68, and reception circuit 69 are provided on the reception path R2.
  • the transmission path R1 is a path through which an RF signal output to the antenna element 21 passes
  • the reception path R2 is a path through which an RF signal input from the antenna element 21 passes.
  • the switch 65 switches between connecting the transmission path R1 or the reception path R2 to the antenna element 21 at a specified time interval. This allows the phased array antenna module 1 to transmit and receive high frequency signals as a time division multiplexing system.
  • the transmission circuit 61 is a circuit to which the RF signal (signal transmitted as radio waves from the antenna element 21) output from the frequency conversion IC 30 (see Figure 1) is input.
  • the phase shifter 62 adjusts the phase shift amount of the RF signal passing through the transmission path R1 according to the phase shift amount setting value of the beam table read from the memory area 13.
  • the variable gain amplifier 63 adjusts the intensity of the RF signal passing through the transmission path R1 according to the gain setting value of the beam table read from the memory area 13.
  • the power amplifier 64 amplifies the RF signal passing through the transmission path R1 by a predetermined amplification factor. By adjusting the phase shift amount and intensity of the RF signal passing through the transmission path R1, the beam pattern of the radio waves transmitted from the phased array antenna module 1 can be changed.
  • the low noise amplifier 66 amplifies the RF signal input from the switch 65 at a predetermined amplification rate.
  • the variable gain amplifier 67 adjusts the intensity of the RF signal passing through the receiving path R2 according to the gain setting value of the beam table read from the memory area 13.
  • the phase shifter 68 adjusts the phase shift amount of the RF signal passing through the receiving path R2 according to the phase shift amount setting value of the beam table read from the memory area 13.
  • the receiving circuit 69 receives the RF signal passing through the receiving path R2 and outputs it to the frequency conversion IC 30 (see Figure 1). By adjusting the phase shift amount and intensity of the RF signal passing through the receiving path R2, the beam pattern of the radio waves received by the phased array antenna module 1 can be changed.
  • the power detector 70 detects the power of the signal amplified by the power amplifier 64 and supplied to the antenna element 21, and outputs a signal (analog signal) indicating the detection result.
  • a splitter BR that splits the RF signal amplified by the power amplifier 64 at a stable branching ratio is provided in the transmission path R1 between the power amplifier 64 and the switch 65.
  • One of the RF signals split by the splitter BR is supplied to the switch 65, and the other of the RF signals split by the splitter BR is supplied to the power detector 70.
  • the power detector 70 detects the power by inputting the power of the other of the RF signals split by the splitter BR, and outputs a current according to the detected power.
  • the detection circuit that detects the power of the signal supplied to the antenna elements 21 includes a power detector 70 provided in each of the RF front ends 5, an analog-to-digital converter (ADC) 71, a counter 72, a selector 73, and a counter control circuit 74.
  • the ADC 71 inputs a signal (voltage signal) in which the current output from the power detector 70 is converted into a voltage.
  • the ADC 71 is provided in the beamformer IC 10 (see FIG. 2).
  • the counter 72, the selector 73, and the counter control circuit 74 are provided, for example, in the digital circuit 6 of the beamformer IC 10, and are connected to the digital circuit section 11 of the RF front end 5 and the ADC 71.
  • the ADC 71 converts the signal (voltage signal) obtained by converting the current output from the power detector 70 into a voltage into a digital signal.
  • the ADC 71 starts the conversion process when a trigger signal instructing the start of conversion is input.
  • the ADC 71 requires a certain number of clocks from the start of the conversion process until the conversion process is completed.
  • the ADC 71 outputs a signal indicating the completion of the conversion.
  • the signal (digital signal) converted by the ADC 71 can be extracted from the ADC 71 after the signal indicating the completion of the conversion is output.
  • the frequency of the clock supplied to the ADC 71 is lower than the frequency of the clock supplied to the digital circuit 6 of the beamformer IC 10 and the digital circuit unit 11 provided in the multiple RF front ends 5.
  • the signal (digital signal) converted by the ADC 71 may be held in a register.
  • the counter 72 is, for example, a register having a predetermined bit width, and holds a count value under the control of the counter control circuit 74.
  • the bit width of the counter 72 is set according to the number of power detectors 70 that can be connected to the ADC 71. For example, if the number of power detectors 70 that can be connected to the ADC 71 is 16, the bit width of the counter 72 is 4 bits. In this case, the count value of the counter 72 can range from 0 to 15.
  • the selector 73 selects one of the power detectors 70 to be connected to the ADC 71 according to the count value held in the counter 72. For example, if the count value is "0", the power detector 70 provided in the RF front end 5A is selected, and if the count value is "15", the power detector 70 provided in the RF front end 5P is selected. Note that only one power detector 70 can be temporarily connected to the ADC 71, and multiple power detectors 70 cannot be connected to the ADC 71 at the same time.
  • the selector 73 may be configured to, for example, select one power detector 70 to be connected to the ADC 71 by enabling only one power detector 70 and disabling the remaining power detectors 70 among the multiple power detectors 70 physically connected to the ADC 71.
  • the selector 73 may be configured to select one power detector 70 to be connected to the ADC 71 by controlling a switch having multiple input ports and one output port to select detection signals output from the multiple power detectors 70 connected to the ADC 71.
  • the selector 73 may include a register that holds a count value indicating the number of the selected power detector 70 when a trigger signal instructing the ADC 71 to start conversion is input.
  • the counter control circuit 74 controls the count value of the counter 72. Specifically, the counter control circuit 74 increments the count value held in the counter 72 when a signal indicating completion of conversion to a digital signal is output from the ADC 71. Furthermore, when the counter control circuit 74 increments the count value held in the counter 72, if the count value held in the counter 72 exceeds the maximum count value, the counter control circuit 74 sets the count value held in the counter 72 to zero. For example, if the bit width of the counter 72 is 4 bits and the count value held in the counter 72 is "15", the counter control circuit 74 sets the count value of the counter 72 to zero when a signal indicating completion of conversion to a digital signal is output from the ADC 71.
  • the counter control circuit 74 When the counter control circuit 74 receives a reset command from the control device 50, it sets the initial count value of the counter 72 to zero. Also, when a communication message sent from the control device 50 sets the count value of the counter 72, the counter control circuit 74 sets the count value of the counter 72 to a value based on that communication message.
  • the digital circuit 6 When there is a request from the control device 50 to acquire the digital signal converted by the ADC 71, the digital circuit 6 extracts the digital signal from the ADC 71. The digital circuit 6 then transmits the acquired digital signal to the control device 50. Alternatively, when there is a request from the control device 50 to acquire the digital signal converted by the ADC 71 and a count value indicating the selected power detector 70, the digital circuit 6 extracts the digital signal from the ADC 71 and transmits the acquired digital signal and the count value held in the counter 72 (the count value corresponding to the selected power detector 70) to the control device 50. Note that it is only after the ADC 71 outputs a signal indicating the completion of conversion to a digital signal that it is possible to extract the digital signal from the ADC 71.
  • the ADC 71, the counter 72, and the selector 73 may be provided one each, or multiple each.
  • the ADC 71, the counter 72, and the selector 73 may be configured to be provided two each.
  • the first ADC 71 may be connected to eight power detectors 70 provided in the RF front ends 5A to 5H
  • the second ADC 71 may be connected to eight power detectors 70 provided in the RF front ends 5I to 5P.
  • the bit width of the first counter 72 and the second counter 72 is set to 3 bits.
  • the first selector 73 may select the power detector 70 to be connected to the first ADC 71 according to the count value of the first counter 72, and the second selector 73 may select the power detector 70 to be connected to the second ADC 71 according to the count value of the second counter 72.
  • the number of power detectors 70 that can be connected to one ADC 71 does not necessarily have to be a power of 2, and may be M, which is not a power of 2.
  • the counter control circuit 74 increments the count value held in the counter 72 if the count value held in the counter 72 is other than (M-1).
  • the counter control circuit 74 sets the count value held in the counter 72 to zero if the count value held in the counter 72 is (M-1).
  • the timing at which the counter control circuit 74 controls the count value of the counter 72 is not limited to when a signal indicating the completion of conversion to a digital signal is output from the ADC 71.
  • the counter control circuit 74 may control the count value of the counter 72, for example, when there is a request from the control device 50 to acquire the digital signal converted by the ADC 71.
  • the counter control circuit 74 may control the count value of the counter 72 when transmitting a response message to the above acquisition request.
  • ⁇ Procedure for acquiring detection signal> 4 is a flowchart showing a procedure in an embodiment of the present invention in which the control device 50 acquires a detection signal of power detected by the phased array antenna module 1.
  • the control device 50 acquires a detection signal of power detected by the phased array antenna module 1.
  • a detection signal of power detected by a specific beamformer IC 10 e.g., beamformer IC 10A
  • a specific beamformer IC 10 e.g., beamformer IC 10A
  • the control device 50 first instructs the power detector 70 to connect to the ADC 71 provided in the specific beamformer IC 10 (step S11). Specifically, the control device 50 determines the power detector 70 to first connect to the ADC 71 provided in the specific beamformer IC 10. The control device 50 then transmits a communication message to the specific beamformer IC 10 instructing it to set the counter 72 to a count value corresponding to the determined power detector 70.
  • step S11 When the control device 50 issues a reset command to a specific beamformer IC 10, the count value of the counter 72 is set to zero under the control of the counter control circuit 74. Therefore, when the processing of the flowchart shown in FIG. 4 is started immediately after the control device 50 issues a reset command to the specific beamformer IC 10 described above, the processing of step S11 can be omitted.
  • a counter control circuit 74 provided in the specific beamformer IC 10 sets the count value specified in the received communication message in the counter 72. Then, a selector 73 connects a power detector 70 (for example, a power detector 70 provided in the RF front end 5A) corresponding to the count value set in the counter 72 to the ADC 71.
  • a power detector 70 for example, a power detector 70 provided in the RF front end 5A
  • the control device 50 transmits a communication message to the specific beamformer IC 10 instructing the ADC 71 to which the power detector 70 is connected to start the conversion process (step S12).
  • the counter control circuit 74 provided in the specific beamformer IC 10 outputs a trigger signal instructing the ADC 71 to start conversion. This starts the conversion process in the ADC 71. If necessary, a process of waiting until the power detector 70 connected to the ADC 71 stabilizes may be provided between steps S11 and S12.
  • step S13 the control device 50 judges whether the conversion process of the ADC 71 is completed. Specifically, the control device 50 waits a fixed time after the processing of step S12 ends, and then transmits a communication message to a specific beamformer IC 10 to instruct it to obtain a signal indicating the completion of conversion output from the ADC 71. Then, the control device 50 judges whether a response communication message in reply to this communication message contains a signal indicating the completion of conversion of the ADC 71. If the response communication message does not contain a signal indicating the completion of conversion of the ADC 71 (if the judgment result is "NO"), the control device 50 repeats the processing of step S13.
  • the control device 50 transmits an acquisition request to acquire the digital signal converted by the ADC 71 (step S14). Specifically, the control device 50 transmits a communication message to a specific beamformer IC 10 instructing it to acquire the digital signal converted by the ADC 71.
  • the counter control circuit 74 provided in the specific beamformer IC 10 When a communication message transmitted from the control device 50 is received by a specific beamformer IC 10, the counter control circuit 74 provided in the specific beamformer IC 10 generates a response communication message including the digital signal converted by the ADC 71. If a register is provided to hold the digital signal converted by the ADC 71, the response communication message may be generated including the digital signal held in the register. Alternatively, the control device 50 may generate a response communication message including the digital signal converted by the ADC 71 (or the digital signal held in the register) and the count value held in the counter 72 (the count value corresponding to the selected power detector 70). The response communication message generated by the counter control circuit 74 is transmitted to the control device 50. The control device 50 receives the response communication message transmitted from the counter control circuit 74 to obtain the digital signal converted by the ADC 71.
  • the counter control circuit 74 increments the count value of the counter 72.
  • the counter control circuit 74 sets the count value of the counter 72 to zero.
  • the selector 73 connects the power detector 70 (for example, the power detector 70 provided in the RF front end 5B) corresponding to the newly set count value of the counter 72 to the ADC 71.
  • Switching of the power detector 70 to be connected to the ADC 71 does not require instructions from the control device 50 via a communication message, but is performed by the counter control circuit 74 controlling the count value of the counter 72. This simplifies the control communication between the control device 50 and the phased array antenna module 1, and shortens the time required for control.
  • the counter control circuit 74 may control the count value of the counter 72 when the control device 50 requests to acquire the digital signal converted by the ADC 71, rather than when a signal indicating completion of conversion is output from the ADC 71.
  • the counter 72 is controlled (e.g., incremented) in parallel with the generation of the response communication message in the counter control circuit 74.
  • the control device 50 determines whether or not all of the necessary digital signals have been acquired (step S15). For example, it determines whether or not all of the digital signals indicating the detection results of the 16 power detectors 70 provided in the beamformer IC 10 have been acquired. If it is determined that all of the necessary digital signals have not been acquired (if the determination result is "NO"), the processing of steps S12 to S15 is repeated. On the other hand, if it is determined that all of the necessary digital signals have been acquired (if the determination result is "YES"), the series of processing steps shown in FIG. 4 is terminated.
  • step S11 when the processes of steps S12 to S15 are repeated, the count value of the counter 72 is controlled (e.g., incremented) by the counter control circuit 74. Therefore, when the processes of steps S12 to S15 are repeated, the process equivalent to step S11 shown in FIG. 4 (exchange of communication messages with the control device 50) is omitted. Therefore, for example, when acquiring all digital signals indicating the detection results of the 16 power detectors 70 provided in the beamformer IC 10, the process of step S11 is performed only when acquiring a digital signal indicating the detection result of the first power detector 70. When acquiring digital signals indicating the detection results of the remaining 15 power detectors 70, the process equivalent to step S11 is not performed.
  • this embodiment includes a plurality of power detectors 70 provided corresponding to a plurality of power amplifiers 64, an ADC 71 that converts the detection results of the power detectors 70 into digital signals, a counter 72, a selector 73 that selects the power detector 70 to be connected to the ADC 71 according to the count value of the counter 72, and a counter control circuit 74 that controls the count value of the counter 72.
  • This makes it possible to reduce the number of communication messages required for the upper control device 50 to instruct the power detector 70 to be connected to the ADC 71. This makes it possible to reduce control communication costs compared to conventional methods.
  • phased array antenna module described in the above embodiment is for a time division multiplexing system.
  • phased array antenna module of the present invention may be for a frequency division multiplexing system.
  • two front ends may be connected to a dual-polarized antenna element having a connection terminal for horizontal polarization and a connection terminal for vertical polarization.
  • 1...phased array antenna module 10...beamformer IC, 21...antenna element, 50...control device, 70...power detector, 71...analog-to-digital converter (ADC), 72...counter, 73...selector, 74...counter control circuit

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
PCT/JP2024/022560 2023-06-22 2024-06-21 ビームフォーマ集積回路及びフェーズドアレイアンテナモジュール Ceased WO2024262609A1 (ja)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007251341A (ja) * 2006-03-14 2007-09-27 Hitachi Kokusai Electric Inc 送信機
US20120163510A1 (en) * 2010-12-22 2012-06-28 Industry Academic Cooperation Foundation Of Hoseo University Wireless communication devices and methods
US11115136B1 (en) * 2020-07-10 2021-09-07 Lg Electronics Inc. Method for calibrating an array antenna in a wireless communication system and apparatus thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007251341A (ja) * 2006-03-14 2007-09-27 Hitachi Kokusai Electric Inc 送信機
US20120163510A1 (en) * 2010-12-22 2012-06-28 Industry Academic Cooperation Foundation Of Hoseo University Wireless communication devices and methods
US11115136B1 (en) * 2020-07-10 2021-09-07 Lg Electronics Inc. Method for calibrating an array antenna in a wireless communication system and apparatus thereof

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