WO2024255542A1 - 柔性电路板、显示模组及显示装置 - Google Patents

柔性电路板、显示模组及显示装置 Download PDF

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Publication number
WO2024255542A1
WO2024255542A1 PCT/CN2024/094322 CN2024094322W WO2024255542A1 WO 2024255542 A1 WO2024255542 A1 WO 2024255542A1 CN 2024094322 W CN2024094322 W CN 2024094322W WO 2024255542 A1 WO2024255542 A1 WO 2024255542A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
layer
coupled
flexible circuit
esd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/094322
Other languages
English (en)
French (fr)
Inventor
张秘
梁恒镇
闵航
刘练彬
牛文骁
陶益
赵辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/881,021 priority Critical patent/US20260020145A1/en
Publication of WO2024255542A1 publication Critical patent/WO2024255542A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0257—Overvoltage protection
    • H05K1/0259—Electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/005—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection avoiding undesired transient conditions
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/073—High voltage adaptations
    • H05K2201/0746—Protection against transients, e.g. layout adapted for plugging of connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display

Definitions

  • the present disclosure relates to the technical field of circuit board design, and more specifically, to a flexible circuit board, a display module, and a display device.
  • OLED Organic Light-Emitting Diode
  • the purpose of the present disclosure is to provide a flexible circuit board, a display module and a display device to solve at least one of the problems existing in the prior art.
  • a first aspect of the present disclosure provides a flexible circuit board, including an electrostatic discharge protection circuit, an electrostatic discharge detection circuit, and a switch circuit;
  • the input end of the electrostatic discharge detection circuit is coupled to the output end of the electrostatic discharge protection circuit, and the output end of the electrostatic discharge detection circuit is coupled to the control end of the switch circuit;
  • the first end of the switch circuit, the reset signal output end of the application processor, and the reset signal input end of the display driver chip are coupled to a first node, and the second end of the switch circuit is coupled to a ground end.
  • the switch circuit comprises a first switch transistor, the control of the first switch transistor
  • the control electrode is coupled to the output end of the electrostatic discharge detection circuit, the first electrode is coupled to the first node, and the second electrode is coupled to the ground end.
  • the first switch transistor is an N-type transistor.
  • the flexible circuit board also includes a first resistor and a first capacitor, the first resistor is coupled between the reset signal output terminal of the application processor and the first node, the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to the ground terminal.
  • the flexible circuit board includes a first binding area located at an end position of one side of the flexible circuit board for binding to a display panel, and at least a portion of the flexible circuit board near the first binding area includes a first ground layer, a routing layer, and a second ground layer stacked in sequence.
  • the first ground layer and the second ground layer are electrically connected through a via hole opened in the routing layer.
  • the first binding area is located at an end position of the flexible circuit board.
  • a partial area of the flexible circuit board close to the first binding area includes a first ground layer, a routing layer, and a second ground layer stacked in sequence.
  • a second aspect of the present disclosure provides a display module, comprising a display panel and the flexible circuit board provided by the first aspect of the present disclosure.
  • a third aspect of the present disclosure provides a display device, comprising the display module provided by the second aspect of the present disclosure.
  • the technical solution disclosed in the present invention can timely and effectively reset the display panel when ESD occurs, thereby effectively improving the anti-ESD capability, effectively reducing the risk of electrostatic damage to the display panel, and further improving the reliability of the product.
  • FIG. 1 is a schematic diagram showing a switch circuit in a flexible printed circuit board provided in an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram showing the wiring of a switch circuit in a flexible printed circuit board provided in an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram showing an ESD protection circuit and an ESD detection circuit in a flexible circuit board provided in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram showing signal waveforms during the reset process of the display driver chip.
  • FIG. 5 is a schematic diagram showing the area division of the flexible circuit board provided in an embodiment of the present disclosure.
  • FIG6 is a schematic cross-sectional view of a three-layer structure region in a flexible circuit board provided in an embodiment of the present disclosure.
  • on may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.
  • first the terms “first”, “second”, etc. may be used herein to describe various parts, components, elements, regions, layers and/or parts, these parts, components, elements, regions, layers and/or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and/or part from another.
  • first part, first member, first element, first region, first layer and/or first part discussed below may be referred to as the second part, second member, second element, second region, second layer and/or second part without departing from the teachings of the present disclosure.
  • the term "same-layer arrangement" used refers to two layers, parts, components, elements or parts that can be formed by the same preparation process (such as a patterning process, etc.), and the two layers, parts, components, elements or parts are generally formed of the same material.
  • two or more functional layers are arranged in the same layer, which means that these functional layers arranged in the same layer can be formed using the same material layer and the same preparation process, thereby simplifying the preparation process of the display substrate.
  • patterning process generally includes steps such as photoresist coating, exposure, development, etching, photoresist stripping, etc.
  • one-time patterning process means a process of forming patterned layers, components, members, etc. using one mask.
  • the OLED display panel can be electrically connected to the display driver chip through an FPC, so that the driver chip is set on the backlight side to achieve a narrow frame and a higher screen-to-body ratio.
  • the OLED display panel in the present invention has insufficient anti-ESD capability.
  • the OLED display panel in the related art has made some designs to improve the anti-ESD capability, for example, the first binding area (Bonding) of the FPC used to bind to the OLED display panel is located in the bending area (Bending), and MCL glue (Metal Cover Layer, bending area protective glue) is applied on the outside of the bending area to play a certain anti-ESD (Electro-Static discharge) role, the ESD (Electro-Static discharge) protection effect is still lacking, and the product may fail the ESD test.
  • MCL glue Metal Cover Layer, bending area protective glue
  • an embodiment of the present disclosure provides a flexible circuit board, including an electrostatic discharge protection circuit, an electrostatic discharge detection circuit and a switch circuit;
  • the input end of the electrostatic discharge detection circuit is coupled to the output end of the electrostatic discharge protection circuit, and the output end of the electrostatic discharge detection circuit is coupled to the control end of the switch circuit;
  • the first end of the switch circuit, the reset signal output end of the application processor, and the reset signal input end of the display driver chip are coupled to a first node, and the second end of the switch circuit is coupled to a ground end.
  • the flexible circuit board provided in the embodiment of the present disclosure can timely and effectively reset the display panel when ESD occurs, thereby effectively improving the anti-ESD capability, effectively reducing the risk of electrostatic damage to the display panel, and further improving the reliability of the display device.
  • the flexible circuit board provided in the embodiment of the present disclosure is a flexible circuit board used to connect an OLED display panel and a display driver chip (Display Driver Integrated Circuit, DDIC) in a mobile phone.
  • the display device of the mobile phone includes a display driver chip and an OLED display panel.
  • the DDIC is connected to the application processor (Application Processor, AP) of the mobile phone through the mobile industry processor interface (Mobile Industry Processor Interface, MIPI) to receive display data.
  • AP Application Processor
  • MIPI Mobile Industry Processor Interface
  • the flexible circuit board provided in the embodiment of the present disclosure can be applied to various types of display panels, and can be selected and set according to actual needs.
  • the flexible circuit board provided in the embodiment of the present disclosure can also be applied to other types of display panels such as quantum dot light emitting diodes (Quantum Dot Light Emitting Diodes, referred to as QLED) display panels and micro light emitting diodes (Micro Light Emitting Diodes, referred to as Micro LED) display panels to resist ESD.
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED Micro Light Emitting Diodes
  • the switch circuit includes a first switch transistor, A switch transistor has a control electrode coupled to the output end of the electrostatic discharge detection circuit, a first electrode coupled to the first node, and a second electrode coupled to the ground end, thereby improving the response speed of the switch circuit and ensuring the timeliness of resetting the display panel when ESD occurs.
  • the first switch transistor is an N-type transistor, which is more conducive to improving the response speed of the switch circuit and ensuring the timeliness of resetting the display panel when ESD occurs.
  • the flexible circuit board further includes a first resistor and a first capacitor, wherein the first resistor is coupled between the reset signal output terminal of the application processor and the first node, the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to the ground terminal.
  • the first resistor and the first capacitor can be used to protect a switching circuit including a switching transistor, for example, to prevent the switching transistor and other devices in the switching circuit from being broken down.
  • the switching circuit includes an N-type transistor N1, such as an NMOS tube, the gate of the N-type transistor N1 is coupled to the output terminal ESD Error flag of the electrostatic release detection circuit, such as a GPO (General-Purpose Output), the source of the N-type transistor N1 is coupled to the ground terminal GND, the drain of the N-type transistor N1, the second end of the first resistor R1, the reset signal input terminal DDIC_Reset of the display driver chip, and the first end of the first capacitor C1 are coupled to the first node A, the first end of the first resistor R1 is coupled to the reset signal output terminal AP_Reset of the application processor, and the second end of the first capacitor C1 is coupled to the ground terminal GND.
  • NPO General-Purpose Output
  • the electrostatic discharge protection circuit includes a first transient voltage suppression diode D1 and a second resistor R2.
  • the first end of the first transient voltage suppression diode D1 is coupled to the power supply terminal VCC, and the second end of the first transient voltage suppression diode D1 is grounded GND.
  • the first end of the second resistor R2 is coupled to the power supply terminal VCC and the input end of the electrostatic discharge detection circuit, and the second end of the second resistor R2 is grounded GND.
  • the first transient voltage suppression diode D1 is a bipolar transient voltage suppression diode.
  • the first transient voltage suppression diode D1 When ESD does not occur, the first transient voltage suppression diode D1 is cut off or turned off, and the static The electrostatic release protection circuit continuously outputs a high-level signal. When ESD occurs, the first transient voltage suppression diode D1 is turned on, so that the electrostatic release protection circuit outputs a low-level signal. After the ESD ends, the first transient voltage suppression diode D1 returns to the cut-off state, and the electrostatic release protection circuit resumes outputting a high-level signal. That is, the electrostatic release protection circuit outputs a high-level signal when ESD does not occur, and outputs a low-level signal when ESD occurs.
  • the electrostatic release detection circuit includes an inverter INV1, and an output end of the inverter INV1 is coupled to the gate of the N-type transistor N1 as an output end ESD Error flag of the electrostatic release detection circuit, for example, a GPO type.
  • the electrostatic discharge protection circuit When ESD does not occur, the electrostatic discharge protection circuit continuously outputs a high-level signal, the ERRORFLAG signal output by the output terminal ESD Error flag of the electrostatic discharge detection circuit, such as a GPO type, is a low-level signal, the N-type transistor N1 is turned off, the input signal RESET of the reset signal input terminal DDIC_Reset of the DDIC is a high-level signal output by the reset signal output terminal AP_Reset of the AP, the DDIC is in a normal working state, and the normal output includes driving signals such as the clock signal GCK to drive the OLED display panel to display normally, such as the interval before 4ms in FIG. 4;
  • the electrostatic discharge protection circuit resumes outputting a high-level signal, and the ERRORFLAG signal output by the output terminal ESD Error flag of the electrostatic discharge detection circuit, such as the GPO type, turns back to a low-level signal, and the N-type transistor N1 is turned off.
  • the input signal RESET of the reset signal input terminal DDIC_Reset of the DDIC turns back to a high-level signal output by the reset signal output terminal AP_Reset of the AP, and the DDIC resumes normal working state, and the normal output includes driving signals such as the clock signal GCK to drive the OLED display panel to display normally, such as the interval after 5ms in FIG.
  • the interval of 4.5ms-5ms is the reset process or reset preparation interval.
  • the flexible circuit board includes a first binding area located at an end position of one side of the flexible circuit board for binding to a display panel, and at least a portion of the flexible circuit board near the first binding area includes a first ground layer, a routing layer, and a second ground layer stacked in sequence.
  • the flexible circuit board provided by the present invention realizes timely and effective reset of the display panel when ESD occurs through the design of the switching circuit, thereby effectively improving the anti-ESD capability.
  • the flexible circuit board provided by the present invention also further improves the anti-ESD capability from the perspective of hardware stacking design by designing at least a portion of the area close to the first binding area as a three-layer structure including a first ground layer, a routing layer and a second ground layer.
  • the first ground layer and the second ground layer are electrically connected via vias provided in the routing layer, thereby further improving the ESD resistance of the three-layer structure.
  • the first binding area is located at an end position of the flexible circuit board.
  • a partial area of the flexible circuit board close to the first binding area includes a first ground layer, a routing layer, and a second ground layer which are stacked in sequence.
  • the FPC includes a first binding area for binding to the OLED display panel and a second binding area for binding to the display driver chip, the first binding area and the second binding area respectively include a plurality of binding pins, wherein the first binding area is located in the bending area (Bending), the FPC in the related art is a two-layer structure, the bottom layer is a routing layer, and the top layer is a grounding layer.
  • MCL glue is applied to the outside of the bending area, it can play a certain anti-ESD role, but there is still a risk that the ESD generated in the bending area enters the routing layer and damages the signal routing.
  • a certain width of the FPC close to the first binding area is designed as a three-layer structure including a first grounding layer, a routing layer and a second grounding layer, that is, the bottom layer and the top layer are grounding layers respectively, and the middle layer is a routing layer wrapped by the grounding layers on both sides. Therefore, when ESD occurs, static electricity can pass through the upper and lower grounding layers
  • the routing layer 602 is electrically connected to the first grounding layer 601 and the second grounding layer 603. It is understood that FIG6 is only a schematic diagram of the film layer and the via position.
  • the signal routing in the routing layer 602 is insulated from the first grounding layer 601, the second grounding layer 603, and the via 6021.
  • the display panel is, for example, an OLED display panel.
  • the OLED display panel includes a display area and a frame area surrounding the display area.
  • the frame area on one side is provided with a panel binding area.
  • the side where the panel binding area is provided is called a DP side (Data Pad, data binding side), corresponding to, for example, the lower frame side of the OLED display panel of a mobile phone.
  • the panel binding area includes a plurality of binding pins. The binding pins of the panel binding area are bound to the binding pins of the first binding area of the flexible circuit board through a chip on film (COF).
  • COF chip on film
  • OLED display panels Exemplary, regarding OLED display panels:
  • the OLED display panel includes a substrate and film layers such as a driving circuit layer, a pixel defining layer, an anode, a light-emitting device layer, a cathode and an encapsulation layer formed on the substrate.
  • film layers such as a driving circuit layer, a pixel defining layer, an anode, a light-emitting device layer, a cathode and an encapsulation layer formed on the substrate.
  • the substrate can be a flexible substrate of materials such as polyimide (PI), polyethylene naphthalate (PEN), thermoplastic polyester (PET), etc., or a rigid substrate of materials such as glass and quartz.
  • the OLED display panel may also include a barrier layer (Barrier) and a buffer layer (Buffer) located between the substrate and the driving circuit layer.
  • the barrier layer and the buffer layer can be formed on the entire surface of the substrate.
  • the barrier layer can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride
  • the buffer layer can also be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the barrier layer is beneficial to blocking water and oxygen from entering the OLED formed later from the bottom.
  • the buffer layer is beneficial to the subsequent material deposition quality.
  • the driving circuit layer may also be referred to as a thin film transistor (TFT) layer, including an active layer (Active) formed on the buffer layer by a patterning process, a gate insulating layer (GI) formed on the active layer by deposition or the like, a gate (Gate) of a thin film transistor formed on the gate insulating layer by a patterning process, and a gate electrode (Gate) formed on the gate insulating layer by a patterning process.
  • TFT thin film transistor
  • the active layer can be made of materials such as polysilicon and metal oxide
  • the gate insulating layer can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride
  • the dielectric layer can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.
  • the gate material includes metals or alloy materials such as aluminum, titanium, and cobalt.
  • the planar layer is, for example, an organic material.
  • the anode is, for example, a metal oxide such as ITO, IZO, or a metal such as Ag, Al, Mo, or an alloy thereof.
  • the anode is electrically connected to the drain through a via hole opened in the planar layer.
  • the pixel defining layer may be formed by a patterning process and surrounds the anode.
  • the material of the pixel defining layer may include organic insulating materials such as negative photoresist, polyimide, and epoxy resin.
  • the light-emitting device layer is formed on the anode exposed by the opening of the pixel definition layer.
  • the light-emitting device can be formed on the anode in the opening of the pixel definition layer by inkjet printing or evaporation, and the light-emitting device includes, for example, a light-emitting layer, and may also include an auxiliary light-emitting layer that helps the light-emitting layer emit light, and the auxiliary light-emitting layer includes, for example, one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.
  • the light-emitting layer and the auxiliary light-emitting layer are, for example, organic material layers.
  • the cathode is formed on the entire surface of the OLED display panel, covering the light-emitting device layer and the pixel defining layer.
  • the material of the cathode may include metals such as Mg, Ca, Li or Al or their alloys, or metal oxides such as IZO and ZTO, or organic materials with conductive properties such as PEDOT/PSS (poly 3,4-ethylenedioxythiophene/polystyrene sulfonate).
  • the encapsulation layer is located on the cathode.
  • the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer.
  • the first inorganic encapsulation layer and the second inorganic encapsulation layer are formed by deposition or the like.
  • the organic encapsulation layer is formed by inkjet printing.
  • the first inorganic encapsulation layer and the second inorganic encapsulation layer can be formed of inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, and the organic encapsulation layer can be formed of organic materials such as polyimide (PI) and epoxy resin.
  • PI polyimide
  • the first inorganic encapsulation layer, the organic encapsulation layer and the second inorganic encapsulation layer are formed into a composite encapsulation layer, which can form multiple protections for the functional structure of the display panel and has a better encapsulation effect.
  • the OLED display panel further includes a cover glass (CG) located on the encapsulation layer.
  • CG cover glass
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., and this embodiment does not limit this.

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Abstract

本公开实施例公开一种柔性电路板、显示模组及显示装置。在一具体实施方式中，该柔性电路板包括：包括静电释放保护电路、静电释放检测电路和开关电路；所述静电释放检测电路的输入端与所述静电释放保护电路的输出端耦接，所述静电释放检测电路的输出端与所述开关电路的控制端耦接；所述开关电路的第一端、应用处理器的复位信号输出端、显示驱动芯片的复位信号输入端耦接于第一节点，所述开关电路的第二端耦接于接地端。该实施方式可在发生ESD时及时有效地进行显示面板复位，从而有效提升抗ESD能力，有效降低静电击伤显示面板的风险，进而提高产品的可靠性。

Description

柔性电路板、显示模组及显示装置
相关公开的交叉引用
本公开主张在2023年06月13日在中国提交的中国专利公开号No.202310700882.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及电路板设计技术领域。更具体地，涉及一种柔性电路板、显示模组及显示装置。
背景技术
目前，显示设备在生活中的运用越来越多，以满足人们在娱乐、社交和商务等方面的各种需求，因此显示设备的更新和发展也越来越快。有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板由于在窄边框、高屏幕占比方面具有优势，得到很多的关注。但发明人发现，相关技术中的OLED显示面板的抗ESD能力不足。
发明内容
本公开的目的在于提供一种柔性电路板、显示模组及显示装置，以解决现有技术存在的问题中的至少一个。
为达到上述目的，本公开采用下述技术方案：
本公开第一方面提供了一种柔性电路板，包括静电释放保护电路、静电释放检测电路和开关电路；
所述静电释放检测电路的输入端与所述静电释放保护电路的输出端耦接，所述静电释放检测电路的输出端与所述开关电路的控制端耦接；
所述开关电路的第一端、应用处理器的复位信号输出端、显示驱动芯片的复位信号输入端耦接于第一节点，所述开关电路的第二端耦接于接地端。
可选地，所述开关电路包括第一开关晶体管，所述第一开关晶体管的控 制极与所述静电释放检测电路的输出端耦接、第一极耦接于所述第一节点且第二极耦接于接地端。
可选地，所述第一开关晶体管为N型晶体管。
可选地，所述柔性电路板还包括第一电阻器和第一电容器，所述第一电阻器耦接于所述应用处理器的复位信号输出端与所述第一节点之间，所述第一电容器的第一端耦接于所述第一节点，所述第一电容器的第二端耦接于所述接地端。
可选地，所述柔性电路版包括位于所述柔性电路板一侧端部位置的用于与显示面板绑定的第一绑定区，所述柔性电路版的靠近所述第一绑定区的至少部分区域包括依次层叠设置的第一接地层、走线层和第二接地层。
可选地，所述第一接地层与所述第二接地层通过开设于所述走线层的过孔电连接。
可选地，所述第一绑定区位于所述柔性电路板的端部位置。
可选地，所述柔性电路版的靠近所述第一绑定区的部分区域包括依次层叠设置的第一接地层、走线层和第二接地层。
本公开第二方面提供一种显示模组，包括显示面板和本公开第一方面提供的柔性电路板。
本公开第三方面提供一种显示装置，包括本公开第二方面提供的显示模组。
本公开的有益效果如下：
本公开的技术方案，可在发生ESD时及时有效地进行显示面板复位，从而有效提升抗ESD能力，有效降低静电击伤显示面板的风险，进而提高产品的可靠性。
附图说明
下面结合附图对本公开的具体实施方式作进一步详细的说明。
图1示出本公开实施例提供的柔性电路板中的开关电路的示意图。
图2示出本公开实施例提供的柔性电路板中的开关电路的走线示意图。
图3示出本公开实施例提供的柔性电路板中的ESD保护电路和ESD检测电路的示意图。
图4示出显示驱动芯片的复位过程的信号波形示意图。
图5示出本公开实施例提供的柔性电路板的区域划分示意图。
图6示出本公开实施例提供的柔性电路板中的三层结构区域的截面示意图。
具体实施方式
本公开中所述的“在……上”、“在……上形成”和“设置在……上”可以表示一层直接形成或设置在另一层上，也可以表示一层间接形成或设置在另一层上，即两层之间还存在其它的层。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
在本公开中，除非另有说明，所采用的术语“同层设置”指的是两个层、部件、构件、元件或部分可以通过相同制备工艺(例如构图工艺等)形成，并且，这两个层、部件、构件、元件或部分一般由相同的材料形成。例如两个或更多个功能层同层设置指的是这些同层设置的功能层可以采用相同的材料层并利用相同制备工艺形成，从而可以简化显示基板的制备工艺。
在本公开中，除非另有说明，表述“构图工艺”一般包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤。表述“一次构图工艺”意指使用一块掩模板形成图案化的层、部件、构件等的工艺。
OLED显示面板例如可通过FPC与显示驱动芯片电连接，从而将驱动芯片设置在背光侧，实现窄边框和更高的屏幕占比。但发明人发现，相关技术 中的OLED显示面板的抗ESD能力不足，虽然相关技术中的OLED显示面板做了一些提升抗ESD能力的设计，例如，FPC的用于与OLED显示面板绑定的第一绑定区(Bonding)位于弯折区(Bending)中，弯折区的外侧涂抹MCL胶(Metal Cover Layer，弯折区保护胶)，从而起到一定的抗ESD(Electro-Static discharge，静电释放)作用，但ESD(Electro-Static discharge，静电释放)保护效果还是有所欠缺，产品可能会出现无法通过ESD测试的情况。
有鉴于此，本公开实施例提供了一种柔性电路板，包括静电释放保护电路、静电释放检测电路和开关电路；
所述静电释放检测电路的输入端与所述静电释放保护电路的输出端耦接，所述静电释放检测电路的输出端与所述开关电路的控制端耦接；
所述开关电路的第一端、应用处理器的复位信号输出端、显示驱动芯片的复位信号输入端耦接于第一节点，所述开关电路的第二端耦接于接地端。
本公开实施例提供的柔性电路板，可在发生ESD时及时有效地进行显示面板复位，从而有效提升抗ESD能力，有效降低静电击伤显示面板的风险，进而提高显示装置的可靠性。
在一个具体示例中，本公开实施例提供的柔性电路板为在手机中的用于连接OLED显示面板和显示驱动芯片(Display Driver Integrated Circuit，DDIC)的柔性电路板，手机的显示装置包括显示驱动芯片和OLED显示面板，DDIC与手机的应用处理器(Application Processor，AP)通过移动产业处理器接口(Mobile Industry Processor Interface，MIPI)连接，以接收显示数据。需要说明的是，本公开实施例提供的柔性电路板可应用于多种类型的显示面板，可以根据实际需要选择设置。例如，除了OLED显示面板之外，本公开实施例提供的柔性电路板也可应用于量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板、微发光二极管(Micro Light Emitting Diodes，简称Micro LED)显示面板等其他类型的显示面板，以抗ESD能力。
在一种可能的实现方式中，所述开关电路包括第一开关晶体管，所述第 一开关晶体管的控制极与所述静电释放检测电路的输出端耦接、第一极耦接于所述第一节点且第二极耦接于接地端。由此，有利于提升开关电路的响应速度，保证在发生ESD时进行显示面板复位的及时性。
在一种可能的实现方式中，所述第一开关晶体管为N型晶体管。由此，更有利于提升开关电路的响应速度，保证在发生ESD时进行显示面板复位的及时性。
在一种可能的实现方式中，所述柔性电路板还包括第一电阻器和第一电容器，所述第一电阻器耦接于所述应用处理器的复位信号输出端与所述第一节点之间，所述第一电容器的第一端耦接于所述第一节点，所述第一电容器的第二端耦接于所述接地端。由此，可通过第一电阻器和第一电容器对例如包括开关晶体管的开关电路进行保护，避免开关电路中的开关晶体管等器件被击穿。
下面，结合上述实现方式，以显示面板为OLED显示面板为例，对本公开实施例提供的柔性电路板的静电释放保护电路结构及工作原理进行示例性说明。
例如图1和图2所示，开关电路包括例如为NMOS管的N型晶体管N1，N型晶体管N1的栅极与静电释放检测电路的例如GPO(General-Purpose Output，通用型输出)类型的输出端ESD Error flag耦接，N型晶体管N1的源极耦接于接地端GND，N型晶体管N1的漏极、第一电阻器R1的第二端、显示驱动芯片的复位信号输入端DDIC_Reset、第一电容器C1的第一端耦接于第一节点A，第一电阻器R1的第一端与应用处理器的复位信号输出端AP_Reset耦接，第一电容器C1的第二端耦接于接地端GND。
例如图3所示，静电释放保护电路包括第一瞬变电压抑制二极管D1和第二电阻器R2，第一瞬变电压抑制二极管D1的第一端与电源端VCC耦接，第一瞬变电压抑制二极管D1的第二端接地GND，第二电阻器R2的第一端与电源端VCC以及静电释放检测电路的输入端耦接，第二电阻器R2的第二端接地GND，例如，第一瞬变电压抑制二极管D1为双极性瞬变电压抑制二极管。在未发生ESD时，第一瞬变电压抑制二极管D1截止或者说关断，静 电释放保护电路持续输出高电平信号。当发生ESD时，第一瞬变电压抑制二极管D1导通，使得静电释放保护电路输出低电平信号。在ESD结束后，第一瞬变电压抑制二极管D1恢复截止状态，静电释放保护电路恢复输出高电平信号。即，静电释放保护电路在未发生ESD时输出高电平信号，当发生ESD时输出低电平信号。
继续参见图3所示，静电释放检测电路包括反相器INV1，反相器INV1的输出端作为静电释放检测电路的例如GPO类型的输出端ESD Error flag与N型晶体管N1的栅极耦接。
结合图1-图3，并参见图4所示：
在未发生ESD时，静电释放保护电路持续输出高电平信号，静电释放检测电路的例如GPO类型的输出端ESD Error flag输出的ERRORFLAG信号为低电平信号，N型晶体管N1截止，DDIC的复位信号输入端DDIC_Reset的输入信号RESET为AP的复位信号输出端AP_Reset输出的高电平信号，DDIC处于正常工作状态，正常输出包括时钟信号GCK等驱动信号以驱动OLED显示面板正常显示，例如图4中4ms之前的区间；
当发生ESD时，静电释放保护电路输出低电平信号，静电释放检测电路的例如GPO类型的输出端ESD Error flag输出的ERRORFLAG信号变为高电平信号，N型晶体管N1导通，DDIC的复位信号输入端DDIC_Reset的输入信号RESET被拉低到接地，DDIC进入复位状态，OLED显示面板进入休眠(Sleep-In)状态，例如图4中4ms-4.5ms之间的区间。例如，在DDIC的复位信号输入端DDIC_Reset的输入信号RESET被拉低到接地时DDIC将标志位F设为F＝1。
在ESD结束后，静电释放保护电路恢复输出高电平信号，静电释放检测电路的例如GPO类型的输出端ESD Error flag输出的ERRORFLAG信号变回低电平信号，N型晶体管N1截止，DDIC的复位信号输入端DDIC_Reset的输入信号RESET重新变为AP的复位信号输出端AP_Reset输出的高电平信号，DDIC恢复正常工作状态，正常输出包括时钟信号GCK等驱动信号以驱动OLED显示面板正常显示，例如图4中5ms之后的区间，其中，例 如图4中4.5ms-5ms的区间为复位过程或者说复位准备区间。例如，在DDIC的复位信号输入端DDIC_Reset的输入信号RESET重新变为AP的复位信号输出端AP_Reset输出的高电平信号时DDIC将标志位F设为F＝0，AP回读到F＝0后执行软件复位动作，DDIC执行完上电程序后恢复正常工作状态。
在一种可能的实现方式中，所述柔性电路版包括位于所述柔性电路板一侧端部位置的用于与显示面板绑定的第一绑定区，所述柔性电路版的靠近所述第一绑定区的至少部分区域包括依次层叠设置的第一接地层、走线层和第二接地层。
由此，在本公开提供的柔性电路板从电路设计的角度上，通过开关电路的设计，实现在发生ESD时及时有效地进行显示面板复位，从而有效提升抗ESD能力的基础上，本公开提供的柔性电路板还从硬件叠层设计的角度，通过将靠近第一绑定区的至少部分区域设计为包括第一接地层、走线层和第二接地层的三层结构来进一步提升抗ESD能力。
在一种可能的实现方式中，所述第一接地层与所述第二接地层通过开设于所述走线层的过孔电连接。由此，可进一步提升三层结构的抗ESD能力。
在一种可能的实现方式中，所述第一绑定区位于所述柔性电路板的端部位置。
在一种可能的实现方式中，所述柔性电路版的靠近所述第一绑定区的部分区域包括依次层叠设置的第一接地层、走线层和第二接地层。
以显示面板为OLED显示面板为例，FPC包括用于与OLED显示面板绑定的第一绑定区和用于与显示驱动芯片绑定的第二绑定区，第一绑定区和第二绑定区分别包括多个绑定引脚，其中，第一绑定区位于弯折区(Bending)中，相关技术中的FPC为两层结构，底层为走向层，顶层为接地层，虽然弯折区的外侧涂抹MCL胶，可以起到一定的抗ESD作用，但是还是存在弯折区发生的ESD进入走线层而击伤信号走线的风险，而上述实现方式，将FPC的靠近第一绑定区的一定宽度的部分区域设计为包括第一接地层、走线层和第二接地层的三层结构，即底层和顶层分别为接地层，中间层为被两侧接地层包裹的走线层，由此，发生ESD时静电可以通过上、下两层接地层 导走，可进一步提升抗ESD能力，特别是弯折区的抗ESD能力。例如图5所示，FPC的靠近第一绑定区501的区域502设计为三层结构，其余区域503依旧为包括走向层和接地层的两层结构。如图6所示，区域502中，第一接地层601和第二接地层603，通过开设于走线层602的过孔6021电连接，可理解的是，图6仅为膜层和过孔位置的示意，走线层602中的信号走线与第一接地层601、第二接地层603、过孔6021中的例如金属连接件的连接件分别绝缘。
本公开的另一个实施例提供了一种显示模组，包括显示面板和上述实施例提供的柔性电路板。其中，显示面板例如为OLED显示面板，示例性的，OLED显示面板例如包括显示区和围绕显示区的边框区，一侧的边框区设置有面板绑定区，例如设置面板绑定区的一侧称为DP侧(Data Pad，数据绑定侧)，对应于例如手机的OLED显示面板的下边框侧，面板绑定区包括多个绑定引脚，面板绑定区的绑定引脚通过覆晶薄膜(Chip On Film，COF)与柔性电路板的第一绑定区的绑定引脚绑定，柔性电路板实现OLED显示面板与显示驱动芯片的电连接。
示例性的，关于OLED显示面板：
OLED显示面板包括衬底及形成在衬底上的驱动电路层、像素界定层、阳极、发光器件层、阴极和封装层等膜层。
衬底可以为聚酰亚胺(PI)、聚萘二甲酸乙二醇酯(PEN)、热塑性聚酯(PET)等材料的柔性衬底，也可以为玻璃、石英等材料的刚性衬底，OLED显示面板还可包括位于衬底与驱动电路层之间的阻挡层(Barrier)和缓冲层(Buffer)。例如，阻挡层和缓冲层可以整面形成在衬底上。例如，阻挡层可以采用氧化硅、氮化硅、或者氮氧化硅等无机绝缘材料，缓冲层也可以采用氧化硅、氮化硅、或者氮氧化硅等无机绝缘材料。阻挡层有利于从底部阻挡水、氧进入之后形成的OLED中。缓冲层有利于后续的材料沉积质量。
驱动电路层也可称为薄膜晶体管(TFT)层，包括在缓冲层上采用构图工艺形成的有源层(Active)、在有源层上通过沉积等方式形成的栅极绝缘层(GI)、在栅绝缘层上采用构图工艺形成的薄膜晶体管的栅极(Gate)、在栅 极上通过沉积等方式形成的介电层(ILD)、在介电层上形成的源漏金属层及覆盖源漏金属层和露出的介电层的平坦层(PLN)，源漏金属层形成薄膜晶体管的源极(Source)和漏极(Drain)，例如源极通过介电层过孔与有源层电连接。其中，有源层可以采用多晶硅和金属氧化物等材料，栅极绝缘层可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，介电层可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。栅极材料包括铝、钛、钴等金属或者合金材料。平坦层例如为有机材料。
阳极(Anode)例如为ITO、IZO等金属氧化物或者Ag、Al、Mo等金属或其合金材料，阳极例如通过平坦层开设的过孔与漏极电连接。
像素界定层可利用构图工艺形成，其围绕阳极，示例性的，像素界定层的材料可以包括负性光刻胶、聚酰亚胺、环氧树脂等有机绝缘材料。
发光器件层形成在像素界定层开设的开口所暴露的阳极上。例如，可通过喷墨打印或者蒸镀等方式在像素界定层开设的开口中的阳极上形成发光器件，发光器件例如包括发光层，还可包括有助于发光层发光的辅助发光层，辅助发光层例如包括电子传输层、电子注入层、空穴传输层以及空穴注入层中的一种或多种。发光层和辅助发光层例如为有机材料层。
阴极例如在OLED显示面板上整面形成，覆盖发光器件层和像素界定层，阴极的材料可以包括Mg、Ca、Li或Al等金属或其合金，或者IZO、ZTO等金属氧化物，又或者PEDOT/PSS(聚3，4-乙烯二氧噻吩/聚苯乙烯磺酸盐)等具有导电性能有机材料。
封装层(TFE)位于阴极上，例如，封装层包括第一无机封装层、有机封装层和第二无机封装层。例如，第一无机封装层和第二无机封装层采用沉积等方式形成。有机封装层采用喷墨打印的方式形成。例如，第一无机封装层和第二无机封装层可以采用氮化硅、氧化硅、氮氧化硅等无机材料形成，有机封装层可以采用聚酰亚胺(PI)、环氧树脂等有机材料形成。由此，第一无机封装层，有机封装层以及第二无机封装层形成为复合封装层，该复合封装层可以对显示面板的功能结构形成多重保护，具有更好的封装效果。
例如，OLED显示面板还包括位于封装层上的玻璃盖板(CG)。
本公开的另一个实施例提供了一种显示装置，包括上述实施例提供的显示面板。其中，显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本实施例对此不做限定。
显然，本公开的上述实施例仅仅是为清楚地说明本公开所作的举例，而并非是对本公开的实施方式的限定，对于本领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动，这里无法对所有的实施方式予以穷举，凡是属于本公开的技术方案所引伸出的显而易见的变化或变动仍处于本公开的保护范围之列。

Claims (10)

  1. 一种柔性电路板，其特征在于，包括静电释放保护电路、静电释放检测电路和开关电路；
    所述静电释放检测电路的输入端与所述静电释放保护电路的输出端耦接，所述静电释放检测电路的输出端与所述开关电路的控制端耦接；
    所述开关电路的第一端、应用处理器的复位信号输出端、显示驱动芯片的复位信号输入端耦接于第一节点，所述开关电路的第二端耦接于接地端。
  2. 根据权利要求1所述的柔性电路板，其特征在于，所述开关电路包括第一开关晶体管，所述第一开关晶体管的控制极与所述静电释放检测电路的输出端耦接、第一极耦接于所述第一节点且第二极耦接于接地端。
  3. 根据权利要求2所述的柔性电路板，其特征在于，所述第一开关晶体管为N型晶体管。
  4. 根据权利要求1所述的柔性电路板，其特征在于，所述柔性电路板还包括第一电阻器和第一电容器，所述第一电阻器耦接于所述应用处理器的复位信号输出端与所述第一节点之间，所述第一电容器的第一端耦接于所述第一节点，所述第一电容器的第二端耦接于所述接地端。
  5. 根据权利要求1所述的柔性电路板，其特征在于，所述柔性电路版包括位于所述柔性电路板一侧端部位置的用于与显示面板绑定的第一绑定区，所述柔性电路版的靠近所述第一绑定区的至少部分区域包括依次层叠设置的第一接地层、走线层和第二接地层。
  6. 根据权利要求5所述的柔性电路板，其特征在于，所述第一接地层与所述第二接地层通过开设于所述走线层的过孔电连接。
  7. 根据权利要求5所述的柔性电路板，其特征在于，所述第一绑定区位于所述柔性电路板的端部位置。
  8. 根据权利要求7所述的柔性电路板，其特征在于，所述柔性电路版的靠近所述第一绑定区的部分区域包括依次层叠设置的第一接地层、走线层和第二接地层。
  9. 一种显示模组，其特征在于，包括显示面板和如权利要求1-8中任一项所述的柔性电路板。
  10. 一种显示装置，其特征在于，包括如权利要求9所述的显示模组。
PCT/CN2024/094322 2023-06-13 2024-05-21 柔性电路板、显示模组及显示装置 Ceased WO2024255542A1 (zh)

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CN116634658A (zh) * 2023-06-13 2023-08-22 京东方科技集团股份有限公司 柔性电路板、显示模组及显示装置
CN117095616B (zh) * 2023-09-20 2025-11-28 昆山国显光电有限公司 显示模组和显示装置

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