WO2024255519A1 - 驱动电路、驱动方法和显示装置 - Google Patents

驱动电路、驱动方法和显示装置 Download PDF

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Publication number
WO2024255519A1
WO2024255519A1 PCT/CN2024/093524 CN2024093524W WO2024255519A1 WO 2024255519 A1 WO2024255519 A1 WO 2024255519A1 CN 2024093524 W CN2024093524 W CN 2024093524W WO 2024255519 A1 WO2024255519 A1 WO 2024255519A1
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Prior art keywords
mth
transistor
electrically connected
terminal
control
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2024/093524
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English (en)
French (fr)
Inventor
于子阳
邱海军
胡明
蒋志亮
承天一
吴建鹏
王梦奇
魏齐
陈文波
燕青青
王明芳
赵攀
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/996,780 priority Critical patent/US20250391372A1/en
Publication of WO2024255519A1 publication Critical patent/WO2024255519A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method and a display device.
  • the AOD display screen is a screen that controls the partial lighting of the screen without lighting the entire mobile phone screen
  • static screens or less updated screens most of the pixel circuits on the entire screen do not need to update the pixel voltage, that is, most of the pixel circuits can be maintained at the original display brightness through low-leakage LTPO (low-temperature polycrystalline oxide) TFT (thin-film transistor), and the repeated refresh of these pixel circuits causes a waste of power consumption.
  • LTPO low-temperature polycrystalline oxide
  • TFT thin-film transistor
  • the present disclosure provides a driving circuit, comprising a driving signal generating circuit, M output driving terminals and M control circuits; the mth control circuit comprises an mth gating circuit, an mth output control circuit and an mth output circuit; M is a positive integer; m is a positive integer less than or equal to M;
  • the drive signal generating circuit is electrically connected to the control clock signal terminal, the N-1th level drive signal output terminal and the Nth level drive signal output terminal respectively, and is used for performing a shift operation on the N-1th level drive signal provided by the N-1th level drive signal output terminal under the control of the control clock signal provided by the control clock signal terminal, so as to obtain and output the Nth level drive signal through the Nth level drive signal output terminal;
  • the m-th gating circuit is electrically connected to the m-th first node, the m-th gating input terminal and the m-th gating control terminal respectively, and is used for controlling the writing of the m-th gating input signal provided by the m-th gating input terminal into the m-th first node under the control of the m-th gating control signal provided by the m-th gating control terminal;
  • the first end of the m-th output control circuit is electrically connected to the N-th level drive signal output end, and the second end of the m-th output control circuit is electrically connected to the m-th first node, and is used to perform a NAND operation on the N-th level drive signal and the potential of the second end of the m-th output control circuit to obtain the m-th first output signal;
  • the mth output circuit is used to invert the mth first output signal, and obtain an mth output driving signal through the mth output driving terminal;
  • N is a positive integer.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first inverting circuit
  • the first inversion circuit is electrically connected to the control clock signal terminal and the inverted clock signal terminal respectively, and is used to invert the control clock signal to obtain an inverted clock signal, and output the inverted clock signal through the inverted clock signal terminal;
  • the drive signal generating circuit is also electrically connected to the inverted clock signal terminal, and is also used to shift the N-1th level drive signal provided by the N-1th level drive signal output terminal under the control of the inverted clock signal, to obtain and output the Nth level drive signal through the Nth level drive signal output terminal.
  • the mth selection circuit is used to control the writing of the mth selection input signal provided by the mth selection input terminal into the mth first node when the potential of the N-1th level driving signal is the first voltage and the potential of the Nth level driving signal is the second voltage.
  • the mth gating control terminal includes an mth first control terminal, an mth second control terminal, an mth third control terminal and an mth fourth control terminal
  • the mth gating circuit includes an mth first gating transistor, an mth second gating transistor, an mth third gating transistor and an mth fourth gating transistor;
  • the gate of the mth first selection transistor is electrically connected to the mth first control terminal, and the first electrode of the mth first selection transistor is electrically connected to the mth selection input terminal;
  • the gate of the mth second selection transistor is electrically connected to the mth second control terminal, and the first electrode of the mth second selection transistor is electrically connected to the mth selection input terminal;
  • the gate of the mth third selection transistor is electrically connected to the mth third control terminal, the first electrode of the mth third selection transistor is electrically connected to the second electrode of the mth first selection transistor, and the second electrode of the mth third selection transistor is electrically connected to the mth first node;
  • the gate of the mth fourth selection transistor is electrically connected to the mth fourth control terminal, the first electrode of the mth fourth selection transistor is electrically connected to the second electrode of the mth second selection transistor, and the second electrode of the mth fourth selection transistor is electrically connected to the mth first node;
  • the mth first selection transistor is a p-type transistor
  • the mth second selection transistor is an n-type transistor
  • the mth third selection transistor is a p-type transistor
  • the mth fourth selection transistor is an n-type transistor
  • the mth first control terminal is connected to the inverted signal of the N-1th level drive signal
  • the mth second control terminal is the N-1th level drive signal output terminal
  • the mth third control terminal is the Nth level drive signal output terminal
  • the mth fourth control terminal is connected to the inverted signal of the Nth level drive signal; or, the mth first control terminal is connected to the inverted signal of the Nth level drive signal, the mth second control terminal is the Nth level drive signal output terminal, the mth third control terminal is the N-1th level drive signal output terminal, and the mth fourth control terminal is connected to the inverted signal of the N-1th level drive signal.
  • the second electrode of the mth first selection transistor is electrically connected to the second electrode of the mth second selection transistor.
  • the mth gating circuit includes an mth first gating transistor
  • the gate of the mth first selection transistor is electrically connected to the mth selection control terminal, and the mth first A first electrode of the gate transistor is electrically connected to the mth first node, and a second electrode of the mth first gate transistor is electrically connected to the mth gate input terminal.
  • the mth gating control terminal includes an mth first control terminal and an mth second control terminal;
  • the mth gating circuit includes an mth first gating transistor and an mth second gating transistor;
  • the gate of the mth first selection transistor is electrically connected to the mth first control terminal, the first electrode of the mth first selection transistor is electrically connected to the mth first node, and the second electrode of the mth first selection transistor is electrically connected to the first electrode of the mth second selection transistor;
  • the gate of the mth second selection transistor is electrically connected to the mth second control terminal, and the second electrode of the mth second selection transistor is electrically connected to the mth selection input terminal;
  • the mth first control terminal is the N-1th level drive signal output terminal
  • the mth second control terminal is the Nth level drive signal output terminal
  • the mth first selection transistor is an n-type transistor
  • the mth second selection transistor is a p-type transistor
  • the mth first control terminal is the Nth level drive signal output terminal
  • the mth second control terminal is the N-1th level drive signal output terminal
  • the mth first selection transistor is a p-type transistor
  • the mth second selection transistor is an n-type transistor
  • the mth first control terminal is connected to the inverted signal of the N-1th level driving signal
  • the mth second control terminal is the Nth level driving signal output terminal
  • the mth first selection transistor and the mth second selection transistor are both p-type transistors
  • the mth first control terminal is an output terminal of the Nth level driving signal, and the mth second control terminal is connected to the inverted signal of the N-1th level driving signal; the mth first selection transistor and the mth second selection transistor are both p-type transistors; or,
  • the mth first control terminal is the N-1th level driving signal terminal
  • the mth second control terminal is connected to the inverted signal of the Nth level driving signal
  • the mth first selection transistor and the mth second selection transistor are both n-type transistors
  • the mth first control terminal is connected to the inverted signal of the Nth level driving signal
  • the mth second control terminal is the N-1th level driving signal terminal
  • the mth first selection transistor and the mth second selection transistor are both n-type transistors.
  • the mth control circuit further includes an mth first initialization circuit
  • the mth first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the mth first node respectively, and is used to control the connection between the mth first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.
  • the mth control circuit further includes an mth reset circuit
  • the mth reset circuit is electrically connected to the first voltage terminal, the N-1th level drive signal output terminal, the N-1th level drive signal output terminal and the mth first node respectively, and is used to control the connection between the mth first node and the first voltage terminal under the control of the N-1th level drive signal and the N-1th level drive signal provided by the N-1th level drive signal output terminal. Connectivity.
  • the mth control circuit further includes an mth first voltage maintaining circuit
  • the first end of the mth first voltage maintaining circuit is electrically connected to the mth first node
  • the second end of the mth first voltage maintaining circuit is electrically connected to the DC voltage end
  • the mth voltage maintaining circuit is used to maintain the potential of the mth first node.
  • the m-th control circuit further includes an m-th second voltage maintaining circuit; the m-th first node is electrically connected to the second end of the m-th output control circuit through the m-th second voltage maintaining circuit;
  • the mth second voltage maintaining circuit comprises an mth first inverter, an mth second inverter and an mth maintaining control circuit;
  • the input end of the mth first inverter is electrically connected to the mth first node
  • the output end of the mth first inverter is electrically connected to the mth second node
  • the input end of the mth second inverter is electrically connected to the mth second node
  • the output end of the mth second inverter is electrically connected to the mth third node and the second end of the mth output control circuit
  • the mth first inverter is used to invert the potential of the mth first node, and output the inverted potential of the mth first node through the output end of the mth first inverter
  • the mth second inverter is used to invert the potential of its input end, and output the inverted potential through the output end of the mth second inverter
  • the mth maintenance control circuit is electrically connected to the mth maintenance control terminal, the mth third node and the mth first node respectively, and is used to control the connection or disconnection between the mth third node and the mth first node under the control of the mth maintenance control signal provided by the mth maintenance control terminal.
  • the mth reset circuit includes an mth first transistor and an mth second transistor;
  • the gate of the mth first transistor is electrically connected to the N-1th stage driving signal output terminal, the first electrode of the mth first transistor is electrically connected to the first voltage terminal, and the second electrode of the mth first transistor is electrically connected to the first electrode of the mth second transistor;
  • a gate electrode of the mth second transistor is electrically connected to the Nth stage driving signal output terminal, and a second electrode of the mth second transistor is electrically connected to the mth first node.
  • the mth maintenance control terminal includes an mth first maintenance control terminal and an mth second maintenance control terminal;
  • the mth sustain control circuit comprises an mth third transistor and an mth fourth transistor;
  • the gate of the mth third transistor is electrically connected to the mth first sustain control terminal, the first electrode of the mth third transistor is electrically connected to the mth first node, and the second electrode of the mth third transistor is electrically connected to the mth third node;
  • the gate of the mth fourth transistor is electrically connected to the mth second sustain control terminal, the first electrode of the mth fourth transistor is electrically connected to the mth third node, and the second electrode of the mth fourth transistor is electrically connected to the mth first node;
  • the mth third transistor is a p-type transistor, and the mth fourth transistor is an n-type transistor;
  • the mth first maintenance control terminal is the N-1th level driving signal terminal, and the mth second maintenance control terminal is Control the clock signal terminal; or,
  • the mth first sustain control terminal is an inverted clock signal terminal
  • the mth second sustain control terminal is a control clock signal terminal.
  • the mth first inverter includes an mth fifth transistor and an mth sixth transistor
  • the mth second inverter includes an mth seventh transistor and an mth eighth transistor
  • the gate of the mth fifth transistor is electrically connected to the mth first node, the first electrode of the mth fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the mth fifth transistor is electrically connected to the mth second node;
  • the gate of the mth sixth transistor is electrically connected to the mth first node, the first electrode of the mth sixth transistor is electrically connected to the mth second node, and the second electrode of the mth sixth transistor is electrically connected to the second voltage terminal;
  • the mth fifth transistor is a p-type transistor, and the mth sixth transistor is an n-type transistor;
  • a gate of the mth seventh transistor is electrically connected to the mth second node, a first electrode of the mth seventh transistor is electrically connected to the first voltage terminal, and a second electrode of the mth seventh transistor is electrically connected to the mth third node;
  • the gate of the mth eighth transistor is electrically connected to the mth second node, the first electrode of the mth eighth transistor is electrically connected to the mth third node, and the second electrode of the mth eighth transistor is electrically connected to the second voltage terminal;
  • the mth seventh transistor is a p-type transistor
  • the mth eighth transistor is an n-type transistor.
  • the mth first initialization circuit includes an mth ninth transistor
  • the gate of the mth ninth transistor is electrically connected to the initial control terminal, the first electrode of the mth ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the mth ninth transistor is electrically connected to the mth first node.
  • the mth first voltage maintaining circuit includes an mth capacitor
  • the first end of the m-th capacitor is electrically connected to the m-th first node, and the second end of the m-th capacitor is electrically connected to a DC voltage terminal.
  • the mth output control circuit includes an mth tenth transistor, an mth eleventh transistor, an mth twelfth transistor and an mth thirteenth transistor;
  • the gate of the mth tenth transistor is electrically connected to the mth first node, the first electrode of the mth tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the mth tenth transistor is electrically connected to the mth second node;
  • the gate of the mth eleventh transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the mth eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the mth eleventh transistor is electrically connected to the mth second node;
  • the gate of the m-th twelfth transistor is electrically connected to the m-th first node, and the m-th twelfth transistor A first electrode of the transistor is electrically connected to the mth second node, and a second electrode of the mth twelfth transistor is electrically connected to a first electrode of the mth thirteenth transistor;
  • the gate of the mth thirteenth transistor is electrically connected to the N-level driving signal output terminal, and the second electrode of the mth thirteenth transistor is electrically connected to the second voltage terminal;
  • the m-th tenth transistor and the m-th eleventh transistor are p-type transistors, and the m-th twelfth transistor and the m-th thirteenth transistor are n-type transistors.
  • the m-th output circuit includes an m-th fourteenth transistor and an m-th fifteenth transistor;
  • the gate of the m-th fourteenth transistor is electrically connected to the m-th second node, the first electrode of the m-th fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the m-th fourteenth transistor is electrically connected to the m-th output driving terminal;
  • the gate of the mth fifteenth transistor is electrically connected to the mth second node, the first electrode of the mth fifteenth transistor is electrically connected to the mth output driving terminal, and the second electrode of the mth fifteenth transistor is electrically connected to the second voltage terminal.
  • the driving signal generating circuit includes a first driving control circuit, a second driving control circuit, a second inverting circuit and a second initialization circuit;
  • the first drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the N-1th level drive signal output terminal and the fourth node respectively, and is used to shift and invert the N-1th drive signal provided by the N-1th level drive signal output terminal under the control of the control clock signal provided by the control clock signal terminal and the inverted clock signal provided by the inverted clock signal terminal, and obtain and output the inverted signal through the fourth node;
  • the second drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the Nth level drive signal output terminal and the fourth node respectively, and is used to invert the Nth level drive signal provided by the Nth level drive signal output terminal under the control of the control clock signal and the inverted clock signal, and obtain and output the inverted signal through the fourth node;
  • the second inverting circuit is electrically connected to the fourth node and the Nth level driving signal output terminal respectively, and is used to invert the potential of the fourth node and output the inverted signal through the Nth level driving signal output terminal;
  • the second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the Nth level drive signal output terminal respectively, and is used to control the connection between the Nth level drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.
  • the first drive control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor;
  • the gate of the sixteenth transistor is electrically connected to the inverted clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the first electrode of the seventeenth transistor;
  • the gate of the seventeenth transistor is electrically connected to the N-1th stage driving signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the fourth node;
  • the gate of the eighteenth transistor is electrically connected to the N-1th stage driving signal output terminal, the first electrode of the eighteenth transistor is electrically connected to the fourth node, and the second electrode of the eighteenth transistor is electrically connected to the first electrode of the nineteenth transistor;
  • the gate of the nineteenth transistor is electrically connected to the control clock signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the third voltage terminal;
  • the sixteenth transistor and the seventeenth transistor are p-type transistors, and the eighteenth transistor and the nineteenth transistor are n-type transistors.
  • the second drive control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a twenty-third transistor;
  • the gate of the 20th transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the 20th transistor is electrically connected to the first voltage terminal, and the second electrode of the 20th transistor is electrically connected to the first electrode of the 21st transistor;
  • a gate of the twenty-first transistor is electrically connected to the control clock signal terminal, and a second electrode of the twenty-first transistor is electrically connected to the fourth node;
  • a gate of the 22nd transistor is electrically connected to the inverted clock signal terminal, a first electrode of the 22nd transistor is electrically connected to the fourth node, and a second electrode of the 22nd transistor is electrically connected to a first electrode of the 23rd transistor;
  • a gate of the twenty-third transistor is electrically connected to the Nth stage driving signal output terminal, and a second electrode of the twenty-third transistor is electrically connected to the third voltage terminal;
  • the 20th transistor and the 21st transistor are p-type transistors, and the 22nd transistor and the 23rd transistor are n-type transistors.
  • the second inverting circuit includes a twenty-fourth transistor and a twenty-fifth transistor; the second initializing circuit includes a twenty-sixth transistor;
  • the gate of the 24th transistor is electrically connected to the fourth node, the first electrode of the 24th transistor is electrically connected to the first voltage terminal, and the second electrode of the 24th transistor is electrically connected to the first electrode of the 25th transistor and the Nth stage driving signal output terminal;
  • a gate of the twenty-fifth transistor is electrically connected to the fourth node, and a second electrode of the twenty-fifth transistor is electrically connected to the third voltage terminal;
  • the twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor;
  • a gate of the twenty-sixth transistor is electrically connected to the initial control terminal, a first electrode of the twenty-sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the Nth stage driving signal output terminal.
  • the first inverting circuit includes a twenty-seventh transistor and a twenty-eighth transistor;
  • the gate of the twenty-seventh transistor is electrically connected to the control clock signal terminal, the first electrode of the twenty-seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the twenty-seventh transistor is electrically connected to the first electrode of the twenty-eighth transistor. electrically connected to the inverted clock signal terminal;
  • a gate of the twenty-eighth transistor is electrically connected to the control clock signal terminal, and a second electrode of the twenty-eighth transistor is electrically connected to the third voltage terminal.
  • an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit, and the driving method includes:
  • the driving signal generating circuit performs a shift operation on the N-1th level driving signal under the control of the control clock signal, obtains and outputs the Nth level driving signal through the Nth level driving signal output terminal;
  • the mth gating circuit controls, under the control of the mth gating control signal, to write the mth gating input signal into the mth first node;
  • the mth output control circuit performs a NAND operation on the Nth stage driving signal and the potential of the second end of the mth output control circuit to obtain an mth first output signal;
  • the mth output circuit is used for inverting the mth first output signal, and obtaining and providing the mth output driving signal through the mth output driving terminal;
  • M is a positive integer
  • m is a positive integer less than or equal to M
  • N is a positive integer
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned driving circuit.
  • FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a circuit diagram of a related pixel circuit
  • FIG6 is a working timing diagram of the related pixel circuit shown in FIG5 ;
  • FIG7 is a circuit diagram of a related pixel circuit
  • FIG. 8 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 9 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 11 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 12 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 13 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 14 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • 15 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG16 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • 17 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG18 is a circuit diagram of at least one embodiment of a first inversion module
  • FIG19 is a circuit diagram of at least one embodiment of a second inverting module
  • FIG20 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG21 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG22 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG23 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG24 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • 25 is a waveform diagram of a control clock signal provided by the control clock signal terminal NCK and a waveform diagram of a first clock signal provided by the first clock signal terminal NCB;
  • FIG26 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG27 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG28 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG29 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG30 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG31 is a timing diagram of operation of at least one embodiment of the driving circuit shown in FIG30;
  • FIG32 is a timing diagram of the signals output by the output driver terminals of each level
  • FIG. 33 is a circuit diagram of at least one embodiment of a second voltage maintaining circuit.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the driving circuit described in the embodiment of the present disclosure includes a driving signal generating circuit, M output driving terminals and M control circuits; the mth control circuit includes an mth gating circuit, an mth output control circuit and an mth output circuit; M is a positive integer; m is a positive integer less than or equal to M;
  • the drive signal generating circuit is electrically connected to the control clock signal terminal, the N-1th level drive signal output terminal and the Nth level drive signal output terminal respectively, and is used for performing a shift operation on the N-1th level drive signal provided by the N-1th level drive signal output terminal under the control of the control clock signal provided by the control clock signal terminal, so as to obtain and output the Nth level drive signal through the Nth level drive signal output terminal;
  • the mth gating circuit is electrically connected to the mth first node, the mth gating input terminal and the mth gating control terminal respectively. for controlling, under the control of the mth gating control signal provided by the mth gating control terminal, to write the mth gating input signal provided by the mth gating input terminal into the mth first node;
  • the first end of the m-th output control circuit is electrically connected to the N-th level drive signal output end, and the second end of the m-th output control circuit is electrically connected to the m-th first node, and is used to perform a NAND operation on the N-th level drive signal and the potential of the second end of the m-th output control circuit to obtain the m-th first output signal;
  • the mth output circuit is used to invert the mth first output signal, and obtain an mth output driving signal through the mth output driving terminal;
  • N is a positive integer.
  • one driving signal generating circuit may correspond to at least one control circuit. Under the control of the control clock signal, the driving signal generating circuit performs a shift operation on the N-1th level driving signal to obtain the Nth level driving signal.
  • the mth control circuit generates the mth output driving signal based on the Nth level driving signal.
  • m is equal to 1 or m is equal to 2 for illustration, but the present invention is not limited thereto. In actual operation, m may also be an integer greater than 2.
  • the driving circuit includes a driving signal generating circuit 10, an output driving terminal NO (N) and a control circuit; the control circuit includes a gating circuit 11, an output control circuit 12 and an output circuit 13;
  • the drive signal generating circuit 10 is electrically connected to the control clock signal terminal NCK, the N-1th level drive signal output terminal NS(N-1) and the Nth level drive signal output terminal NS(N) respectively, and is used for performing a shift operation on the N-1th level drive signal provided by the N-1th level drive signal output terminal NS(N-1) under the control of the control clock signal provided by the control clock signal terminal NCK, so as to obtain and output the Nth level drive signal through the Nth level drive signal output terminal NS(N);
  • the gating circuit 11 is electrically connected to the first node N1, the gating input terminal VCT and the gating control terminal CX respectively, and is used to control the gating input signal provided by the gating input terminal VCT to be written into the first node N1 under the control of the gating control signal provided by the gating control terminal CX;
  • the first end of the output control circuit 12 is electrically connected to the N-th level drive signal output terminal NS(N), and the second end of the output control circuit 12 is electrically connected to the first node N1, for performing a non-AND operation on the N-th level drive signal and the potential of the second end of the output control circuit 12 to obtain a first output signal;
  • the output circuit 13 is electrically connected to the output control circuit 12 and the output drive terminal NO (N) respectively, and is used to invert the first output signal, obtain and provide an output drive signal through the output drive terminal NO (N);
  • N is a positive integer.
  • the embodiment of the driving circuit shown in FIG. 1 of the present disclosure may be an N-th stage driving circuit.
  • the gating circuit 11 Before the Nth stage driving signal providing stage, the gating circuit 11 writes the gating input signal provided by the gating input terminal VCT into the first node N1 under the control of the gating control signal;
  • the Nth level drive signal When the strobe input signal is a high voltage signal, in the Nth level drive signal providing stage, the Nth level drive signal
  • the output terminal NS (N) outputs a high voltage signal
  • the first output signal output by the output control circuit 12 is a low voltage signal
  • the output circuit 13 provides a high voltage signal through the output driving terminal NO (N), which can control the corresponding row pixel circuit to update the pixel voltage;
  • the Nth level drive signal output terminal NS (N) When the selection input signal is a low voltage signal, in the Nth level drive signal providing stage, the Nth level drive signal output terminal NS (N) outputs a high voltage signal, then the first output signal output by the output control circuit 12 is a high voltage signal, and the output circuit 13 provides a low voltage signal through the output drive terminal NO (N), which can control the corresponding row pixel circuit not to update the pixel voltage.
  • At least one embodiment of the present disclosure can realize the update of a partial picture of the display screen by controlling the selection input signal provided by the selection input terminal VCT, thereby reducing power consumption, or realize ultra-low power consumption of OLED (organic light emitting diode) display products such as wearable products, mobile terminals, NB (notebook computers) by partial update of the display picture.
  • OLED organic light emitting diode
  • the driving circuit includes a driving signal generating circuit 10, a first output driving terminal NO1 (N), a second output driving terminal NO2 (N), a first control circuit and a second control circuit;
  • the first control circuit includes a first gating circuit 111, a first output control circuit 121 and a first output circuit 131;
  • the second control circuit includes a second gating circuit 112, a second output control circuit 122 and a second output circuit 132;
  • the drive signal generating circuit 10 is electrically connected to the control clock signal terminal NCK, the N-1th level drive signal output terminal NS(N-1) and the Nth level drive signal output terminal NS(N) respectively, and is used for performing a shift operation on the N-1th level drive signal provided by the N-1th level drive signal output terminal NS(N-1) under the control of the control clock signal provided by the control clock signal terminal NCK, so as to obtain and output the Nth level drive signal through the Nth level drive signal output terminal NS(N);
  • the first gating circuit 111 is electrically connected to the first first node N11, the first gating input terminal VCT1 and the first gating control terminal CX1 respectively, and is used to control the first gating input signal provided by the first gating input terminal VCT1 to be written into the first first node N11 under the control of the first gating control signal provided by the first gating control terminal CX1;
  • the first end of the first output control circuit 121 is electrically connected to the N-th level drive signal output terminal NS(N), and the second end of the first output control circuit 121 is electrically connected to the first first node N11, and is used to perform a negative AND operation on the N-th level drive signal and the potential of the second end of the first output control circuit 121 to obtain a first first output signal;
  • the first output circuit 131 is electrically connected to the first output control circuit 121 and the first output driving terminal NO1 (N) respectively, and is used to invert the first first output signal to obtain and provide a first output driving signal through the first output driving terminal NO1 (N);
  • the second gating circuit 112 is electrically connected to the second first node N21, the second gating input terminal VCT2 and the second gating control terminal CX2 respectively, and is used for controlling the second gating input signal provided by the second gating input terminal VCT2 to be written into the second first node N21 under the control of the second gating control signal provided by the second gating control terminal CX2;
  • the first terminal of the second output control circuit 122 is electrically connected to the Nth stage driving signal output terminal NS(N).
  • the second end of the second output control circuit 122 is electrically connected to the second first node N21, and is used to perform a NAND operation on the Nth level driving signal and the potential of the second end of the second output control circuit 122 to obtain a second first output signal;
  • the second output circuit 132 is electrically connected to the second output control circuit 122 and the second output drive terminal NO2 (N) respectively, and is used to invert the second first output signal to obtain and provide a second output drive signal through the second output drive terminal NO2 (N);
  • N is a positive integer.
  • the embodiment of the driving circuit shown in FIG. 2 of the present disclosure may be an N-th stage driving circuit.
  • the first gating circuit 111 writes the first gating input signal provided by the first gating input terminal VCT1 into the first first node N11 under the control of the first gating control signal;
  • the second gating circuit 112 writes the second gating input signal provided by the second gating input terminal VCT2 into the second first node N21 under the control of the second gating control signal;
  • the N-th level driving signal output terminal NS(N) When the first selection input signal is a high voltage signal, in the N-th level driving signal providing stage, the N-th level driving signal output terminal NS(N) outputs a high voltage signal, then the first output signal output by the first output control circuit 121 is a low voltage signal, and the first output circuit 131 provides a high voltage signal through the first output driving terminal NO1(N), which can control the corresponding row pixel circuit to update the pixel voltage;
  • the N-th level driving signal output terminal NS(N) When the first selection input signal is a low voltage signal, in the N-th level driving signal providing stage, the N-th level driving signal output terminal NS(N) outputs a high voltage signal, then the first output signal output by the first output control circuit 121 is a high voltage signal, and the first output circuit 131 provides a low voltage signal through the first output driving terminal NO1(N), which can control the corresponding row pixel circuit not to update the pixel voltage;
  • the N-th level driving signal output terminal NS(N) When the second selection input signal is a high voltage signal, in the N-th level driving signal providing stage, the N-th level driving signal output terminal NS(N) outputs a high voltage signal, then the second first output signal output by the second output control circuit 122 is a low voltage signal, and the second output circuit 132 provides a high voltage signal through the second output driving terminal NO2(N), which can control the corresponding row pixel circuit to update the pixel voltage;
  • the N-th level drive signal output terminal NS(N) When the second selection input signal is a low voltage signal, in the N-th level drive signal providing stage, the N-th level drive signal output terminal NS(N) outputs a high voltage signal, then the second first output signal output by the second output control circuit 122 is a high voltage signal, and the second output circuit 132 provides a low voltage signal through the second output drive terminal NO2(N), which can control the corresponding row pixel circuit not to update the pixel voltage.
  • At least one embodiment of the present disclosure can realize the update of a partial picture of the display screen by controlling the first selection input signal provided by the first selection input terminal VCT1 and the second selection input signal provided by the second selection input terminal VCT2, thereby reducing power consumption, or realize ultra-low power consumption of OLED (organic light emitting diode) display products such as wearable products, mobile terminals, NBs (notebook computers) by partial update of the display picture.
  • OLED organic light emitting diode
  • the driving circuit further includes a first inverting circuit
  • the first inverting circuit is electrically connected to the control clock signal terminal and the inverted clock signal terminal respectively, and is used to Controlling the clock signal to be inverted to obtain an inverted clock signal, and outputting the inverted clock signal through the inverted clock signal terminal;
  • the drive signal generating circuit is also electrically connected to the inverted clock signal terminal, and is also used to shift the N-1th level drive signal provided by the N-1th level drive signal output terminal under the control of the inverted clock signal, to obtain and output the Nth level drive signal through the Nth level drive signal output terminal.
  • the driving circuit may further include a first inverting circuit, which inverts the control clock signal to obtain an inverted clock signal.
  • the driving signal generating circuit under the control of the control clock signal and the inverted clock signal, performs a shift operation on the N-1th level driving signal to obtain the Nth level driving signal.
  • the driving circuit further includes a first inverting circuit 31;
  • the first inversion circuit 31 is electrically connected to the control clock signal terminal NCK and the inverted clock signal terminal NCKI respectively, and is used to invert the control clock signal to obtain an inverted clock signal, and output the inverted clock signal through the inverted clock signal terminal NCKI;
  • the drive signal generating circuit 10 is also electrically connected to the inverted clock signal terminal NCKI, and is also used to shift the N-1th level drive signal provided by the N-1th level drive signal output terminal NS(N-1) under the control of the inverted clock signal, to obtain and output the Nth level drive signal through the Nth level drive signal output terminal NS(N).
  • the driving circuit further includes a first inverting circuit 31;
  • the first inversion circuit 31 is electrically connected to the control clock signal terminal NCK and the inverted clock signal terminal NCKI respectively, and is used to invert the control clock signal to obtain an inverted clock signal, and output the inverted clock signal through the inverted clock signal terminal NCKI;
  • the drive signal generating circuit 10 is also electrically connected to the inverted clock signal terminal NCKI, and is also used to shift the N-1th level drive signal provided by the N-1th level drive signal output terminal NS(N-1) under the control of the inverted clock signal, to obtain and output the Nth level drive signal through the Nth level drive signal output terminal NS(N).
  • the related pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst and an organic light emitting diode O1;
  • the gate of M1 is electrically connected to the first reset terminal NR(N), the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the gate of M3;
  • the gate of M2 is electrically connected to the first scanning terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3;
  • the gate of M4 is electrically connected to the second scanning terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3;
  • the gate of M5 is electrically connected to the light emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3;
  • the gate of M6 is electrically connected to the light emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal ELVSS;
  • the gate of M7 is electrically connected to the second scanning terminal PG(N), the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.
  • the first reset terminal NR(N) may be the N-1th stage first scan terminal NG(N), but is not limited thereto.
  • M1 and M2 are n-type transistors
  • M3, M4, M5, M6 and M7 are all p-type transistors
  • M1 and M2 are IGZO (indium gallium zinc oxide) TFTs (thin film transistors) with small leakage current
  • M3, M4, M5, M6 and M7 are all LTPS (low-temperature polycrystalline silicon) TFTs.
  • M1 and M2 are IGZO TFTs.
  • IGZO TFT can ensure that Cst can maintain the gate voltage of M3 for a longer time.
  • the second scanning terminal PG (N) is responsible for resetting the voltage of the anode of O1 and writing the data voltage on the data line into the source of the driving transistor
  • the first scanning terminal NG (N) is responsible for resetting Cst, extracting Vth (Vth is the threshold voltage of the driving transistor) and writing the data voltage into the gate of the driving transistor.
  • the first scanning signal provided by the first scanning terminal NG(N) and the second scanning signal provided by the second scanning terminal PG(N) may be in opposite phases to each other, but the present invention is not limited thereto.
  • the driving circuit described in at least one embodiment of the present disclosure may provide the first scanning signal to the first scanning terminal NG(N) via the output driving terminal NO(N), but the present invention is not limited thereto.
  • the display cycle may include a first display control stage t1 , a second display control stage t2 , and a third display control stage t3 which are set successively;
  • E(N) outputs a high voltage signal
  • NR(N) provides a high voltage signal
  • PG(N) provides a high voltage signal
  • NG(N) provides a low voltage signal
  • M5 and M6 are turned off, M1 is turned on, and the potential of the gate of M3 is pulled down to the initial voltage Vinit; the initial voltage terminal I1 is used to provide the initial voltage Vinit;
  • E(N) outputs a high voltage signal
  • NR(N) provides a low voltage signal
  • PG(N) provides a low voltage signal
  • NG(N) provides a high voltage signal
  • M5 and M6 are turned off, M1 is turned off, M2 is turned on, M4 is turned on, M2 and M3 form a diode structure
  • the data voltage Vdata provided by the data line D1 charges Cst until M3 is turned off, at which time the gate voltage of M3 is Vdata+Vth, and Vth is the threshold voltage of M3
  • M7 is turned on to reset the anode voltage of O1;
  • E(N) outputs a low voltage signal
  • NR(N) provides a low voltage signal
  • PG(N) provides a high voltage signal
  • NG(N) provides a low voltage signal
  • M5 and M6 are turned on, M3 drives O1 to emit light; O1 emits light according to the voltage setting of Vdata.
  • NG(N) can control whether the data voltage Vdata (the data voltage Vdata can be the pixel voltage) is written into the gate of M3 in the second display control stage.
  • FIG. 7 is a circuit diagram of a related pixel circuit.
  • the related pixel circuit may include a first display control transistor M1, a second display control transistor transistor M2, driving transistor M3, fourth display control transistor M4, fifth display control transistor M5, sixth display control transistor M6, seventh display control transistor M7, storage capacitor Cst and organic light emitting diode O1;
  • the gate of M1 is electrically connected to the third reset terminal RST1, the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the drain of M3;
  • the gate of M2 is electrically connected to the first scanning terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3;
  • the gate of M4 is electrically connected to the second scanning terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3;
  • the gate of M5 is electrically connected to the light emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3;
  • the gate of M6 is electrically connected to the light emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal ELVSS;
  • the gate of M7 is electrically connected to the fourth reset terminal RST2 , the source of M7 is electrically connected to the initial voltage terminal I1 , and the drain of M7 is electrically connected to the anode of O1 .
  • NG(N) can control whether the data voltage Vdata on the data line D1 is written into the gate of the driving transistor M3.
  • the first scanning signal provided by NG(N) can be used to control the opening or closing of the second transistor to control whether the data voltage on the data line is written into the gate of the driving transistor, thereby controlling whether the brightness of the pixel circuit of this row is updated; when NG(N) outputs a high voltage signal, the second transistor is turned on, and the brightness of the pixel circuit of this row can be updated; when NG(N) outputs a low voltage signal, the second transistor is always turned off, and the change of the data voltage on the data line will not be written into the gate of the driving transistor, and the luminous brightness of the organic light emitting diode will not change, that is, the display brightness of the pixel circuit of the current row in the current frame remains unchanged.
  • the pixel brightness can be refreshed by controlling the opening or closing of the N-type transistor. Therefore, when you want to achieve non-refresh of some pixels, just ensure that the N-type transistor is turned off.
  • the mth selection circuit is used to control the writing of the mth selection input signal provided by the mth selection input terminal into the mth first node when the potential of the N-1th level driving signal is the first voltage and the potential of the Nth level driving signal is the second voltage.
  • the mth gating circuit can control the writing of the mth gating input signal into the mth first node when the potential of the N-1th level driving signal is the first voltage and the potential of the Nth level driving signal is the second voltage.
  • the first voltage may be a high voltage
  • the second voltage may be a low voltage
  • the present invention is not limited thereto.
  • the first voltage may also be a low voltage
  • the second voltage may be a high voltage
  • the mth gating control terminal includes an mth first control terminal, an mth second control terminal, an mth third control terminal and an mth fourth control terminal
  • the mth gating circuit includes an mth first gating transistor, an mth second gating transistor, an mth third gating transistor and an mth fourth gating transistor;
  • the gate of the mth first gating transistor is electrically connected to the mth first control terminal, and the first electrode of the mth first gating transistor is electrically connected to the mth gating input terminal;
  • the gate of the mth second selection transistor is electrically connected to the mth second control terminal, and the first electrode of the mth second selection transistor is electrically connected to the mth selection input terminal;
  • the gate of the mth third selection transistor is electrically connected to the mth third control terminal, the first electrode of the mth third selection transistor is electrically connected to the second electrode of the mth first selection transistor, and the second electrode of the mth third selection transistor is electrically connected to the mth first node;
  • the gate of the mth fourth selection transistor is electrically connected to the mth fourth control terminal, the first electrode of the mth fourth selection transistor is electrically connected to the second electrode of the mth second selection transistor, and the second electrode of the mth fourth selection transistor is electrically connected to the mth first node;
  • the mth first selection transistor is a p-type transistor
  • the mth second selection transistor is an n-type transistor
  • the mth third selection transistor is a p-type transistor
  • the mth fourth selection transistor is an n-type transistor
  • the mth first control terminal is connected to the inverted signal of the N-1th level drive signal
  • the mth second control terminal is the N-1th level drive signal output terminal
  • the mth third control terminal is the Nth level drive signal output terminal
  • the mth fourth control terminal is connected to the inverted signal of the Nth level drive signal; or, the mth first control terminal is connected to the inverted signal of the Nth level drive signal, the mth second control terminal is the Nth level drive signal output terminal, the mth third control terminal is the N-1th level drive signal output terminal, and the mth fourth control terminal is connected to the inverted signal of the N-1th level drive signal.
  • the gating control terminal may include a first control terminal CT1, a second control terminal CT2, a third control terminal CT3, and a fourth control terminal CT4, and at least one embodiment of the gating circuit may include a first gating transistor TX1, a second gating transistor TX2, a third gating transistor TX3, and a fourth gating transistor TX4;
  • the gate of the first selection transistor TX1 is electrically connected to the first control terminal CT1, and the drain of the first selection transistor TX1 is electrically connected to the selection input terminal VCT;
  • the gate of the second selection transistor TX2 is electrically connected to the second control terminal CT2, and the drain of the second selection transistor TX2 is electrically connected to the selection input terminal VCT;
  • the gate of the third selection transistor TX3 is electrically connected to the third control terminal CT3, the drain of the third selection transistor TX3 is electrically connected to the source of the first selection transistor TX1, and the source of the third selection transistor TX3 is electrically connected to the first node N1;
  • the gate of the fourth selection transistor TX4 is electrically connected to the fourth control terminal CT4, the drain of the fourth selection transistor TX4 is electrically connected to the source of the second selection transistor TX2, and the source of the fourth selection transistor TX4 is electrically connected to the first node N1;
  • the first selection transistor TX1 is a p-type transistor
  • the second selection transistor TX2 is an n-type transistor
  • the third selection transistor TX3 is a p-type transistor
  • the fourth selection transistor TX4 is an n-type transistor
  • the first control terminal CT1 can be connected to the inverted signal of the N-1th level driving signal
  • the second control terminal CT2 It can be the N-1th level drive signal output terminal
  • the third control terminal CT3 can be the Nth level drive signal output terminal
  • the fourth control terminal CT4 can be connected to the inverted signal of the Nth level drive signal; or, the first control terminal CT1 can be connected to the inverted signal of the Nth level drive signal
  • the second control terminal CT2 can be the Nth level drive signal output terminal
  • the third control terminal CT3 can be the N-1th level drive signal output terminal
  • the fourth control terminal CT4 can be connected to the inverted signal of the N-1th level drive signal.
  • the second electrode of the mth first selection transistor is electrically connected to the second electrode of the mth second selection transistor.
  • the source of the first gating transistor TX1 is electrically connected to the source of the second gating transistor TX2 .
  • the mth gating circuit includes an mth first gating transistor
  • At least one embodiment of the gating circuit may include a first gating transistor TX1;
  • the gate of the first gate transistor TX1 is electrically connected to the gate control terminal S0, the drain of the first gate transistor TX1 is electrically connected to the first node N1, and the source of the first gate transistor TX1 is electrically connected to the gate input terminal VCT;
  • TX1 is a p-type transistor.
  • At least one embodiment of the gating circuit may include a first gating transistor TX1;
  • the gate of the first gate transistor TX1 is electrically connected to the gate control terminal S0, the source of the first gate transistor TX1 is electrically connected to the first node N1, and the drain of the first gate transistor TX1 is electrically connected to the gate input terminal VCT;
  • TX1 is an n-type transistor.
  • the mth gating control terminal includes an mth first control terminal and an mth second control terminal;
  • the mth gating circuit includes an mth first gating transistor and an mth second gating transistor;
  • the gate of the mth first selection transistor is electrically connected to the mth first control terminal, the first electrode of the mth first selection transistor is electrically connected to the mth first node, and the second electrode of the mth first selection transistor is electrically connected to the first electrode of the mth second selection transistor;
  • the mth first control terminal is the N-1th level drive signal output terminal
  • the mth second control terminal is the Nth level drive signal output terminal
  • the mth first selection transistor is an n-type transistor
  • the mth second selection transistor is a p-type transistor
  • the mth first control terminal is the Nth level drive signal output terminal
  • the mth second control terminal is the N-1th level drive signal output terminal
  • the mth first selection transistor is a p-type transistor
  • the mth second selection transistor is an n-1th level drive signal output terminal. type transistor; or,
  • the mth first control terminal is an output terminal of the Nth level driving signal, and the mth second control terminal is connected to the inverted signal of the N-1th level driving signal; the mth first selection transistor and the mth second selection transistor are both p-type transistors; or,
  • the mth first control terminal is the N-1th level driving signal terminal
  • the mth second control terminal is connected to the inverted signal of the Nth level driving signal
  • the mth first selection transistor and the mth second selection transistor are both n-type transistors
  • the gate of the first pass transistor TX1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first pass transistor TX1 is electrically connected to the first node N1, and the drain of the first pass transistor TX1 is electrically connected to the drain of the second pass transistor TX2;
  • At least one embodiment of the gating circuit may include a first gating transistor TX1 and a second gating transistor TX2 ;
  • the gate of the first selection transistor TX1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first selection transistor TX1 is electrically connected to the first node N1, and the source of the first selection transistor TX1 is electrically connected to the source of the second selection transistor T2;
  • the gate of the second selection transistor TX2 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second selection transistor TX2 is electrically connected to the selection input terminal VCT;
  • TX1 is a p-type transistor and TX2 is an n-type transistor.
  • At least one embodiment of the gating circuit may include a first gating transistor TX1 and a second gating transistor TX2 ;
  • the gate of the first gate transistor TX1 is electrically connected to the first inverted drive signal terminal NGI1, the drain of the first gate transistor TX1 is electrically connected to the first node N1, and the source of the first gate transistor TX1 is electrically connected to the drain of the second gate transistor TX2; the first inverted drive signal provided by the first inverted drive signal terminal NGI1 is inverted with the N-1th level drive signal provided by the N-1th level drive signal output terminal NS(N-1);
  • TX1 is a p-type transistor
  • TX2 is a p-type transistor
  • At least one embodiment of the gating circuit may include a first transistor TX1 and a second transistor TX2 ;
  • the gate of the first pass transistor TX1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first pass transistor TX1 is electrically connected to the first node N1, and the source of the first pass transistor TX1 is electrically connected to the drain of the second pass transistor TX2;
  • the gate of the second gate transistor TX2 is electrically connected to the first inverted drive signal terminal NGI1, and the source of the second gate transistor TX2 is electrically connected to the gate input terminal VCT; the first inverted drive signal provided by the first inverted drive signal terminal NGI1 is inverted with the N-1th level drive signal provided by the N-1th level drive signal output terminal NS(N-1);
  • TX1 is a p-type transistor
  • TX2 is a p-type transistor
  • At least one embodiment of the gating circuit may include a first gating transistor TX1 and a second gating transistor TX2 ;
  • the gate of the first selection transistor TX1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first selection transistor TX1 is electrically connected to the first node N1, and the drain of the first selection transistor TX1 is electrically connected to the source of the second selection transistor TX2;
  • the gate of the second gate transistor TX2 is electrically connected to the second inverted drive signal terminal NGI2, and the drain of the second gate transistor TX2 is electrically connected to the gate input terminal VCT; the second inverted drive signal provided by the second inverted drive signal terminal NGI2 is inverted with the N-th level drive signal provided by the N-th level drive signal output terminal NS(N);
  • TX1 is an n-type transistor
  • TX2 is an n-type transistor
  • At least one embodiment of the gating circuit may include a first gating transistor TX1 and a second gating transistor TX2 ;
  • the gate of the first gate transistor TX1 is electrically connected to the second inverted drive signal terminal NGI2, the source of the first gate transistor TX1 is electrically connected to the first node N1, and the drain of the first gate transistor TX1 is electrically connected to the source of the second gate transistor TX2; the second inverted drive signal provided by the second inverted drive signal terminal NGI2 is inverted with the N-th level drive signal provided by the N-th level drive signal output terminal NS(N);
  • the gate of the second selection transistor TX2 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second selection transistor TX2 is electrically connected to the selection input terminal VCT;
  • TX1 is an n-type transistor
  • TX2 is an n-type transistor
  • the N-1th level driving signal provided by the N-1th level driving signal output terminal NS(N-1) can be inverted by the first inversion module to obtain a first inverted driving signal provided by the first inverted driving signal terminal NGI1;
  • the first inversion module includes a first inversion control transistor T01 and a second inversion control transistor T02;
  • T01 is a p-type transistor
  • T02 is an n-type transistor
  • the Nth stage driving signal output terminal NS(N) provided by the second inverting module can be The first driving signal is inverted to obtain a second inverted driving signal provided by the second inverted driving signal terminal NGI2;
  • the second inversion module includes a third inversion control transistor T03 and a fourth inversion control transistor T04;
  • T03 is a p-type transistor
  • T04 is an n-type transistor
  • the mth control circuit further includes an mth first initialization circuit
  • the mth first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the mth first node respectively, and is used to control the connection between the mth first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.
  • the mth control circuit may further include an mth first initialization circuit, and the mth first initialization circuit controls the connection between the mth first node and the first voltage terminal under the control of an initial control signal.
  • the first voltage terminal may be a high voltage terminal, but is not limited thereto.
  • control circuit may further include a first initialization circuit 21;
  • the first initialization circuit 21 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first node N1 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.
  • NCX provides a valid voltage signal
  • the first initialization circuit 21 controls the connection between the first node N1 and the first voltage terminal V1.
  • the first control circuit may further include a first first initialization circuit 211
  • the second control circuit may further include a second first initialization circuit 212 ;
  • the first first initialization circuit 211 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the first first node N11 respectively, and is used to control the connection between the first first node N11 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX;
  • the second first initialization circuit 212 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the second first node N21 respectively, and is used to control the connection between the second first node N21 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.
  • the mth control circuit further includes an mth reset circuit
  • the mth reset circuit is electrically connected to the first voltage terminal, the N-1th level drive signal output terminal, the N-1th level drive signal output terminal and the mth first node, respectively, and is used to control the connection between the mth first node and the first voltage terminal under the control of the N-1th level drive signal and the N-1th level drive signal provided by the N-1th level drive signal output terminal.
  • the mth control circuit may further include an mth reset circuit, which, under the control of the Nth level drive signal and the N-1th level drive signal, resets the potential of the mth first node after the mth output circuit provides the mth output drive signal through the mth output drive terminal.
  • an mth reset circuit which, under the control of the Nth level drive signal and the N-1th level drive signal, resets the potential of the mth first node after the mth output circuit provides the mth output drive signal through the mth output drive terminal.
  • the mth control circuit further includes an mth first voltage maintaining circuit
  • the first end of the mth first voltage maintaining circuit is electrically connected to the mth first node
  • the second end of the mth first voltage maintaining circuit is electrically connected to the DC voltage end
  • the mth voltage maintaining circuit is used to maintain the potential of the mth first node.
  • the m-th control circuit may further include an m-th first voltage maintaining circuit, and the m-th first voltage maintaining circuit may be used to maintain the potential of the m-th first node.
  • the DC voltage terminal may be a first voltage terminal, a second voltage terminal or a third voltage terminal, but is not limited thereto.
  • the first voltage terminal may be a high voltage terminal
  • the second voltage terminal may be a first low voltage terminal
  • the third voltage terminal may be a second low voltage terminal, but the present invention is not limited thereto.
  • control circuit may further include a first voltage maintaining circuit 22 and a reset circuit 23;
  • the reset circuit 23 is electrically connected to the first voltage terminal V1, the N-1-th level drive signal output terminal NS(N-1), the N-th level drive signal output terminal NS(N) and the first node N1 respectively, and is used to control the first node N1 to be connected to the first voltage terminal V1 under the control of the N-1-th level drive signal and the N-1-th level drive signal provided by the N-1-th level drive signal output terminal NS(N-1);
  • a first end of the first voltage maintaining circuit 22 is electrically connected to the first node N1 , a second end of the first voltage maintaining circuit 22 is electrically connected to a second voltage terminal V2 , and the first voltage maintaining circuit 22 is used to maintain the potential of the first node N1 .
  • the first control circuit may further include a first first voltage maintaining circuit 221 and a first reset circuit 231 ;
  • the second control circuit may further include a second first voltage maintaining circuit 222 and a second reset circuit 232 ;
  • the first reset circuit 231 is electrically connected to the first voltage terminal V1, the N-1-th level drive signal output terminal NS(N-1), the N-th level drive signal output terminal NS(N) and the first first node N11 respectively, and is used to control the first first node N11 to be connected to the first voltage terminal V1 under the control of the N-1-th level drive signal and the N-1-th level drive signal provided by the N-1-th level drive signal output terminal NS(N-1);
  • the first end of the first first voltage maintaining circuit 221 is electrically connected to the first first node N11, the second end of the first first voltage maintaining circuit 221 is electrically connected to the second voltage terminal V2, and the first first voltage maintaining circuit 221 is used to maintain the potential of the first first node N11;
  • the second reset circuit 232 is electrically connected to the first voltage terminal V1, the N-1-th level drive signal output terminal NS(N-1), the N-th level drive signal output terminal NS(N) and the second first node N21 respectively, and is used to control the second first node N21 to be connected to the first voltage terminal V1 under the control of the N-1-th level drive signal and the N-1-th level drive signal provided by the N-1-th level drive signal output terminal NS(N-1);
  • the first end of the second first voltage maintaining circuit 222 is electrically connected to the second first node N21, the second end of the second first voltage maintaining circuit 222 is electrically connected to the second voltage terminal V2, and the second first voltage maintaining circuit 222 is used to maintain the potential of the second first node N21.
  • the m-th control circuit further includes an m-th second voltage maintaining circuit; the m-th first node is electrically connected to the second end of the m-th output control circuit through the m-th second voltage maintaining circuit;
  • the mth second voltage maintaining circuit comprises an mth first inverter, an mth second inverter and an mth maintaining control circuit;
  • the input end of the mth first inverter is electrically connected to the mth first node
  • the output end of the mth first inverter is electrically connected to the mth second node
  • the input end of the mth second inverter is electrically connected to the mth second node
  • the output end of the mth second inverter is electrically connected to the mth third node and the second end of the mth output control circuit
  • the mth first inverter is used to invert the potential of the mth first node, and output the inverted potential of the mth first node through the output end of the mth first inverter
  • the mth second inverter is used to invert the potential of its input end, and output the inverted potential through the output end of the mth second inverter
  • the mth maintenance control circuit is electrically connected to the mth maintenance control terminal, the mth third node and the mth first node respectively, and is used to control the connection or disconnection between the mth third node and the mth first node under the control of the mth maintenance control signal provided by the mth maintenance control terminal.
  • the mth control circuit may further include an mth second voltage maintaining circuit
  • the mth first node may be electrically connected to the second end of the mth output control circuit through the mth second voltage maintaining circuit
  • the mth second voltage maintaining circuit may include an mth first inverter, an mth second inverter and an mth maintenance control circuit;
  • the mth first inverter inverts the potential of the mth first node, and the mth second inverter inverts the potential of its input end;
  • the mth maintenance control circuit controls the connection or disconnection between the mth third node and the mth first node under the control of the maintenance control signal provided by the mth maintenance control end;
  • the mth sustain control circuit may control the mth third node to be disconnected from the mth first node when the mth gating circuit controls the mth gating input signal to be written into the mth first node.
  • the mth first inverter and the mth second inverter included in the mth second voltage maintaining circuit can control the connection between the mth third node and the high voltage end when the potential of the mth first node is a high voltage, so that the potential of the mth third node can be higher than the potential of the mth first node, and can control the connection between the mth third node and the low voltage end when the potential of the mth first node is a low voltage, so that the potential of the mth third node can be lower than the potential of the mth first node, so that the mth third node can better control the transistor whose gate is electrically connected to the mth third node included in the mth output control circuit.
  • control circuit may further include a second voltage maintaining circuit;
  • the maintaining control terminal includes the N-1th level driving signal output terminal NS(N-1) and the control clock signal terminal NCK; the first node N1 is electrically connected to the second terminal of the output control circuit 12 through the second voltage maintaining circuit;
  • the second voltage maintaining circuit includes a first inverter F1, a second inverter F2 and a maintaining control circuit W1;
  • the input end of the first inverter F1 is electrically connected to the first node N1, and the output end of the first inverter F1 is electrically connected to the second node N2;
  • the input end of the second inverter F2 is electrically connected to the second node N2, and the output end of the second inverter F2 is electrically connected to the third node N3 and the second end of the output control circuit 12;
  • the first inverter F1 is used to invert the potential of the first node N1, and output the inverted potential of the first node N1 through the output end of the first inverter F1;
  • the second inverter F2 is used to invert the potential at its input terminal and output the inverted potential through the output terminal of the second inverter F2;
  • the maintenance control circuit W1 is electrically connected to the N-1th level drive signal output terminal NS(N-1), the control clock signal terminal NCK, the third node N3 and the first node N1, respectively, and is used to control the connection or disconnection between the third node N3 and the first node N1 under the control of the N-1th level drive signal provided by the N-1th level drive signal output terminal NS(N-1), and to control the connection or disconnection between the third node N3 and the first node N1 under the control of the control clock signal provided by the control clock signal terminal NCK.
  • the N-1th stage driving signal output terminal may be replaced by an inverted clock signal terminal or a first clock signal terminal, but is not limited thereto.
  • FIG. 25 shows the waveform of the control clock signal provided by the control clock signal terminal NCK and the waveform of the first clock signal provided by the first clock signal terminal NCB.
  • the drive signal generating circuit includes a first drive control circuit, a second drive control circuit, a second inverting circuit, and a second initialization circuit;
  • the first drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the N-1th level drive signal output terminal and the fourth node respectively, and is used to shift and invert the N-1th drive signal provided by the N-1th level drive signal output terminal under the control of the control clock signal provided by the control clock signal terminal and the inverted clock signal provided by the inverted clock signal terminal, and obtain and output the inverted signal through the fourth node;
  • the second drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the Nth level drive signal output terminal and the fourth node respectively, and is used to invert the Nth level drive signal provided by the Nth level drive signal output terminal under the control of the control clock signal and the inverted clock signal, and obtain and output the inverted signal through the fourth node;
  • the second inverting circuit is electrically connected to the fourth node and the Nth level driving signal output terminal respectively, and is used to invert the potential of the fourth node and output the inverted signal through the Nth level driving signal output terminal;
  • the second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the Nth level drive signal output terminal respectively, and is used to control the connection between the Nth level drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.
  • control circuit when M is equal to 1, may include a first voltage maintaining circuit and/or a second voltage maintaining circuit to maintain the potential of the first node;
  • the m-th control circuit may include the m-th first voltage maintaining circuit and/or the m-th second A voltage maintaining circuit is provided to maintain the potential of the mth first node.
  • the mth reset circuit includes an mth first transistor and an mth second transistor;
  • the gate of the mth first transistor is electrically connected to the N-1th stage driving signal output terminal, the first electrode of the mth first transistor is electrically connected to the first voltage terminal, and the second electrode of the mth first transistor is electrically connected to the first electrode of the mth second transistor;
  • a gate electrode of the mth second transistor is electrically connected to the Nth stage driving signal output terminal, and a second electrode of the mth second transistor is electrically connected to the mth first node.
  • the mth maintenance control terminal includes an mth first maintenance control terminal and an mth second maintenance control terminal;
  • the mth sustain control circuit comprises an mth third transistor and an mth fourth transistor;
  • the gate of the mth third transistor is electrically connected to the mth first sustain control terminal, the first electrode of the mth third transistor is electrically connected to the mth first node, and the second electrode of the mth third transistor is electrically connected to the mth third node;
  • the gate of the mth fourth transistor is electrically connected to the mth second sustain control terminal, the first electrode of the mth fourth transistor is electrically connected to the mth third node, and the second electrode of the mth fourth transistor is electrically connected to the mth first node;
  • the mth third transistor is a p-type transistor, and the mth fourth transistor is an n-type transistor;
  • the mth first sustain control terminal is the N-1th level driving signal terminal, and the mth second sustain control terminal is the control clock signal terminal; or,
  • the mth first sustain control terminal is an inverted clock signal terminal
  • the mth second sustain control terminal is a control clock signal terminal.
  • the mth first inverter includes an mth fifth transistor and an mth sixth transistor
  • the mth second inverter includes an mth seventh transistor and an mth eighth transistor
  • the gate of the mth fifth transistor is electrically connected to the mth first node, the first electrode of the mth fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the mth fifth transistor is electrically connected to the mth second node;
  • the gate of the mth sixth transistor is electrically connected to the mth first node, the first electrode of the mth sixth transistor is electrically connected to the mth second node, and the second electrode of the mth sixth transistor is electrically connected to the second voltage terminal;
  • the mth fifth transistor is a p-type transistor, and the mth sixth transistor is an n-type transistor;
  • a gate of the mth seventh transistor is electrically connected to the mth second node, a first electrode of the mth seventh transistor is electrically connected to the first voltage terminal, and a second electrode of the mth seventh transistor is electrically connected to the mth third node;
  • the gate of the mth eighth transistor is electrically connected to the mth second node, the first electrode of the mth eighth transistor is electrically connected to the mth third node, and the second electrode of the mth eighth transistor is electrically connected to the second voltage terminal;
  • the mth seventh transistor is a p-type transistor
  • the mth eighth transistor is an n-type transistor.
  • the mth first initialization circuit includes an mth ninth transistor
  • the gate of the mth ninth transistor is electrically connected to the initial control terminal, the first electrode of the mth ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the mth ninth transistor is electrically connected to the mth first node.
  • the mth first voltage maintaining circuit includes an mth capacitor
  • the first end of the m-th capacitor is electrically connected to the m-th first node, and the second end of the m-th capacitor is electrically connected to a DC voltage terminal.
  • the mth output control circuit includes an mth tenth transistor, an mth eleventh transistor, an mth twelfth transistor and an mth thirteenth transistor;
  • the gate of the mth tenth transistor is electrically connected to the mth first node, the first electrode of the mth tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the mth tenth transistor is electrically connected to the mth second node;
  • the gate of the mth eleventh transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the mth eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the mth eleventh transistor is electrically connected to the mth second node;
  • a gate of the mth twelfth transistor is electrically connected to the mth first node, a first electrode of the mth twelfth transistor is electrically connected to the mth second node, and a second electrode of the mth twelfth transistor is electrically connected to a first electrode of the mth thirteenth transistor;
  • the gate of the mth thirteenth transistor is electrically connected to the N-level driving signal output terminal, and the second electrode of the mth thirteenth transistor is electrically connected to the second voltage terminal;
  • the m-th tenth transistor and the m-th eleventh transistor are p-type transistors, and the m-th twelfth transistor and the m-th thirteenth transistor are n-type transistors.
  • the m-th output circuit includes an m-th fourteenth transistor and an m-th fifteenth transistor;
  • the gate of the m-th fourteenth transistor is electrically connected to the m-th second node, the first electrode of the m-th fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the m-th fourteenth transistor is electrically connected to the m-th output driving terminal;
  • the gate of the mth fifteenth transistor is electrically connected to the mth second node, the first electrode of the mth fifteenth transistor is electrically connected to the mth output driving terminal, and the second electrode of the mth fifteenth transistor is electrically connected to the second voltage terminal.
  • the drive signal generating circuit includes a first drive control circuit, a second drive control circuit, a second inverting circuit, and a second initialization circuit;
  • the second drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the Nth level drive signal output terminal and the fourth node respectively, and is used to invert the Nth level drive signal provided by the Nth level drive signal output terminal under the control of the control clock signal and the inverted clock signal, and obtain and output the inverted signal through the fourth node;
  • the second inverting circuit is electrically connected to the fourth node and the Nth level driving signal output terminal respectively, and is used to invert the potential of the fourth node and output the inverted signal through the Nth level driving signal output terminal;
  • the second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the Nth level drive signal output terminal respectively, and is used to control the connection between the Nth level drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.
  • the drive signal generating circuit may include a first drive control circuit, a second drive control circuit, a second inverting circuit and a second initialization circuit; the first drive control circuit shifts and inverts the N-1th drive signal under the control of a control clock signal and an inverted clock signal, and outputs the inverted signal through a fourth node; the second drive control circuit inverts the Nth level drive signal under the control of a control clock signal and an inverted clock signal, and outputs the inverted signal through a fourth node; the second inverting circuit inverts the potential of the fourth node, and outputs the inverted signal through an Nth level drive signal output terminal; the second initialization circuit controls the connection between the Nth level drive signal output terminal and the first voltage terminal under the control of the initial control signal.
  • the driving signal generating circuit may include a first driving control circuit 41 , a second driving control circuit 42 , a second inverting circuit 44 and a second initialization circuit 40 ;
  • the first drive control circuit 41 is electrically connected to the control clock signal terminal NCK, the inverted clock signal terminal NCKI, the N-1th level drive signal output terminal NS(N-1) and the fourth node N4 respectively, and is used to shift and invert the N-1th drive signal provided by the N-1th level drive signal output terminal NS(N-1) under the control of the control clock signal provided by the control clock signal terminal NCK and the inverted clock signal provided by the inverted clock signal terminal NCKI, and obtain and output the inverted signal through the fourth node N4;
  • the second drive control circuit 42 is electrically connected to the control clock signal terminal NCK, the inverted clock signal terminal NCKI, the N-th level drive signal output terminal NS(N) and the fourth node N4, respectively, and is used to invert the N-th level drive signal provided by the N-th level drive signal output terminal NS(N) under the control of the control clock signal and the inverted clock signal, and obtain and output the inverted signal through the fourth node N4;
  • the second inverting circuit 44 is electrically connected to the fourth node N4 and the N-th level driving signal output terminal NS(N) respectively, and is used to invert the potential of the fourth node N4 and output the inverted signal through the N-th level driving signal output terminal NS(N);
  • the second initialization circuit 40 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the Nth level drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth level drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.
  • the driving signal generating circuit may include a first driving control circuit 41 , a second driving control circuit 42 , a second inverting circuit 44 and a second initialization circuit 40 ;
  • the first drive control circuit 41 is electrically connected to the control clock signal terminal NCK, the inverted clock signal terminal NCKI, the N-1th level drive signal output terminal NS(N-1) and the fourth node N4 respectively, and is used to shift and invert the N-1th drive signal provided by the N-1th level drive signal output terminal NS(N-1) under the control of the control clock signal provided by the control clock signal terminal NCK and the inverted clock signal provided by the inverted clock signal terminal NCKI, and obtain and output the inverted signal through the fourth node N4;
  • the second drive control circuit 42 is electrically connected to the control clock signal terminal NCK, the inverted clock signal terminal NCKI, the N-th level drive signal output terminal NS(N) and the fourth node N4, respectively, and is used to invert the N-th level drive signal provided by the N-th level drive signal output terminal NS(N) under the control of the control clock signal and the inverted clock signal, and obtain and output the inverted signal through the fourth node N4;
  • the second inverting circuit 44 is electrically connected to the fourth node N4 and the N-th level driving signal output terminal NS(N) respectively, and is used to invert the potential of the fourth node N4 and output the inverted signal through the N-th level driving signal output terminal NS(N);
  • the second initialization circuit 40 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the Nth level drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth level drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 28 and at least one embodiment of the driving circuit shown in FIG. 26 is that the second voltage maintaining circuit is not included.
  • the first drive control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor;
  • the gate of the sixteenth transistor is electrically connected to the inverted clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the first electrode of the seventeenth transistor;
  • the gate of the seventeenth transistor is electrically connected to the N-1th stage driving signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the fourth node;
  • the gate of the eighteenth transistor is electrically connected to the N-1th stage driving signal output terminal, the first electrode of the eighteenth transistor is electrically connected to the fourth node, and the second electrode of the eighteenth transistor is electrically connected to the first electrode of the nineteenth transistor;
  • the gate of the nineteenth transistor is electrically connected to the control clock signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the third voltage terminal;
  • the sixteenth transistor and the seventeenth transistor are p-type transistors, and the eighteenth transistor and the nineteenth transistor are n-type transistors.
  • the second drive control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor The body tube and the twenty-third transistor;
  • the gate of the 20th transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the 20th transistor is electrically connected to the first voltage terminal, and the second electrode of the 20th transistor is electrically connected to the first electrode of the 21st transistor;
  • a gate of the twenty-first transistor is electrically connected to the control clock signal terminal, and a second electrode of the twenty-first transistor is electrically connected to the fourth node;
  • a gate of the 22nd transistor is electrically connected to the inverted clock signal terminal, a first electrode of the 22nd transistor is electrically connected to the fourth node, and a second electrode of the 22nd transistor is electrically connected to a first electrode of the 23rd transistor;
  • a gate of the twenty-third transistor is electrically connected to the Nth stage driving signal output terminal, and a second electrode of the twenty-third transistor is electrically connected to the third voltage terminal;
  • the 20th transistor and the 21st transistor are p-type transistors, and the 22nd transistor and the 23rd transistor are n-type transistors.
  • the second inverting circuit includes a twenty-fourth transistor and a twenty-fifth transistor; the second initializing circuit includes a twenty-sixth transistor;
  • the gate of the 24th transistor is electrically connected to the fourth node, the first electrode of the 24th transistor is electrically connected to the first voltage terminal, and the second electrode of the 24th transistor is electrically connected to the first electrode of the 25th transistor and the Nth stage driving signal output terminal;
  • a gate of the twenty-fifth transistor is electrically connected to the fourth node, and a second electrode of the twenty-fifth transistor is electrically connected to the third voltage terminal;
  • the twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor;
  • a gate of the twenty-sixth transistor is electrically connected to the initial control terminal, a first electrode of the twenty-sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the Nth stage driving signal output terminal.
  • the first inverting circuit includes a twenty-seventh transistor and a twenty-eighth transistor;
  • the gate of the twenty-seventh transistor is electrically connected to the control clock signal terminal, the first electrode of the twenty-seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the twenty-seventh transistor is electrically connected to the first electrode of the twenty-eighth transistor and the inverted clock signal terminal;
  • a gate of the twenty-eighth transistor is electrically connected to the control clock signal terminal, and a second electrode of the twenty-eighth transistor is electrically connected to the third voltage terminal.
  • the gating control terminal includes a first control terminal, a second control terminal, a third control terminal and a fourth control terminal
  • the gating circuit includes a first gating transistor TX1, a second gating transistor TX2, a third gating transistor TX3 and a fourth gating transistor TX4;
  • the gate of the first selection transistor TX1 is electrically connected to the first control terminal.
  • the drain is electrically connected to the gate input terminal VCT;
  • the gate of the second selection transistor TX2 is electrically connected to the second control terminal, and the drain of the second selection transistor TX2 is electrically connected to the selection input terminal VCT;
  • the gate of the third selection transistor TX3 is electrically connected to the third control terminal, the drain of the third selection transistor TX3 is electrically connected to the source of the first selection transistor TX1, and the source of the third selection transistor TX3 is electrically connected to the first node N1;
  • the gate of the fourth selection transistor TX4 is electrically connected to the fourth control terminal, the drain of the fourth selection transistor TX4 is electrically connected to the source of the second selection transistor TX2, and the source of the fourth selection transistor TX4 is electrically connected to the first node N1;
  • the first selection transistor TX1 is a p-type transistor
  • the second selection transistor TX2 is an n-type transistor
  • the third selection transistor TX3 is a p-type transistor
  • the fourth selection transistor TX4 is an n-type transistor
  • the first control terminal is connected to the inverted signal NSI(N-1) of the N-1th level drive signal
  • the second control terminal is the N-1th level drive signal output terminal NS(N-1)
  • the third control terminal is the Nth level drive signal output terminal NS(N)
  • the fourth control terminal is connected to the inverted signal NSI(N) of the Nth level drive signal
  • the reset circuit includes a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the drain of the first transistor T1 is electrically connected to the high voltage terminal VGHN, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the Nth stage driving signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the first node N1;
  • T1 and T2 are p-type transistors
  • the first initialization circuit includes a ninth transistor T9;
  • the gate of the ninth transistor T9 is electrically connected to the initial control terminal NCX, the drain of the ninth transistor T9 is electrically connected to the high voltage terminal VGHN, and the source of the ninth transistor T9 is electrically connected to the first node N1;
  • T9 is a p-type transistor
  • the first voltage maintaining circuit includes a capacitor C0;
  • the first end of the capacitor C0 is electrically connected to the first node N1, and the second end of the capacitor C0 is electrically connected to the first low voltage end VGL;
  • the output control circuit includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13;
  • the gate of the tenth transistor T10 is electrically connected to the first node N1, the drain of the tenth transistor T10 is electrically connected to the high voltage terminal VGHN, and the source of the tenth transistor T10 is electrically connected to the second node N2;
  • the gate of the eleventh transistor T11 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the eleventh transistor T11 is electrically connected to the high voltage terminal VGHN, and the source of the eleventh transistor T11 is electrically connected to the second node N2;
  • the gate of the twelfth transistor T12 is electrically connected to the first node N1, the drain of the twelfth transistor T12 is electrically connected to the second node N2, and the source of the twelfth transistor T12 is electrically connected to the drain of the thirteenth transistor T13;
  • the gate of the thirteenth transistor T13 is electrically connected to the N-level driving signal output terminal NS(N), and the source of the thirteenth transistor T13 is electrically connected to the first low voltage terminal VGL;
  • the tenth transistor T10 and the eleventh transistor T11 are p-type transistors, and the twelfth transistor T12 and the thirteenth transistor T13 are n-type transistors;
  • the output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15;
  • the gate of the fourteenth transistor T14 is electrically connected to the second node N2, the drain of the fourteenth transistor T14 is electrically connected to the high voltage terminal VGHN, and the source of the fourteenth transistor T14 is electrically connected to the output driving terminal NO (N);
  • the gate of the fifteenth transistor T15 is electrically connected to the second node N2, the drain of the fifteenth transistor T15 is electrically connected to the output driving terminal NO(N), and the source of the fifteenth transistor T15 is electrically connected to the first low voltage terminal VGL;
  • T14 is a p-type transistor, and T15 is a p-type transistor;
  • the first driving control circuit includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18 and a nineteenth transistor T19;
  • the gate of the sixteenth transistor T16 is electrically connected to the inverted clock signal terminal NCKI, the drain of the sixteenth transistor T16 is electrically connected to the high voltage terminal VGHN, and the source of the sixteenth transistor T16 is electrically connected to the drain of the seventeenth transistor T17;
  • the gate of the seventeenth transistor T17 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the source of the seventeenth transistor T17 is electrically connected to the fourth node N4;
  • the gate of the eighteenth transistor T18 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the drain of the eighteenth transistor T18 is electrically connected to the fourth node N4, and the source of the eighteenth transistor T18 is electrically connected to the drain of the nineteenth transistor T19;
  • the gate of the nineteenth transistor T19 is electrically connected to the control clock signal terminal NCK, and the source of the nineteenth transistor T19 is electrically connected to the second low voltage terminal VGLN;
  • the sixteenth transistor T16 and the seventeenth transistor T17 are p-type transistors, and the eighteenth transistor T18 and the nineteenth transistor T19 are n-type transistors;
  • the second driving control circuit includes a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22 and a twenty-third transistor T23;
  • the gate of the 20th transistor T20 is electrically connected to the Nth stage driving signal output terminal NS(N), the drain of the 20th transistor T20 is electrically connected to the high voltage terminal VGHN, and the source of the 20th transistor T20 is electrically connected to the drain of the 21st transistor T21;
  • a gate of the twenty-first transistor T21 is electrically connected to the control clock signal terminal NCK, and a source of the twenty-first transistor T21 is electrically connected to the fourth node N4;
  • a gate of the 22nd transistor T22 is electrically connected to the inverted clock signal terminal NCKI, a drain of the 22nd transistor T22 is electrically connected to the fourth node N4, and a source of the 22nd transistor T22 is electrically connected to a drain of the 23rd transistor T23;
  • a gate of the twenty-third transistor T23 is electrically connected to the Nth stage driving signal output terminal NS(N), and a source of the twenty-third transistor T23 is electrically connected to the second low voltage terminal VGLN;
  • the 20th transistor T20 and the 21st transistor T21 are p-type transistors, and the 22nd transistor T22 and the 23rd transistor T23 are n-type transistors;
  • the second inverting circuit includes a twenty-fourth transistor T24 and a twenty-fifth transistor T25; the second initializing circuit includes a twenty-sixth transistor T26;
  • the gate of the 24th transistor T24 is electrically connected to the fourth node N4, the drain of the 24th transistor T24 is electrically connected to the high voltage terminal VGHN, and the source of the 24th transistor T24 is electrically connected to the drain of the 25th transistor T25 and the Nth stage driving signal output terminal NS(N);
  • a gate of the twenty-fifth transistor T25 is electrically connected to the fourth node N4, and a source of the twenty-fifth transistor T25 is electrically connected to the second low voltage terminal VGLN;
  • the twenty-fourth transistor T24 is a p-type transistor, and the twenty-fifth transistor T25 is an n-type transistor;
  • the gate of the 26th transistor T26 is electrically connected to the initial control terminal NCX, the drain of the 26th transistor T26 is electrically connected to the high voltage terminal VGHN, and the source of the 26th transistor T26 is electrically connected to the Nth stage driving signal output terminal NS(N);
  • the twenty-sixth transistor T26 is a p-type transistor
  • the first inverting circuit includes a twenty-seventh transistor T27 and a twenty-eighth transistor T28;
  • the gate of the 27th transistor T27 is electrically connected to the control clock signal terminal NCK, the drain of the 27th transistor T27 is electrically connected to the high voltage terminal VGHN, and the source of the 27th transistor T27 is electrically connected to the drain of the 28th transistor T28 and the inverted clock signal terminal NCKI;
  • a gate of the 28th transistor T28 is electrically connected to the control clock signal terminal NCK, and a source of the 28th transistor T28 is electrically connected to the second low voltage terminal VGLN;
  • the twenty-seventh transistor T27 is a p-type transistor, and the twenty-eighth transistor T28 is an n-type transistor.
  • the voltage value of the second low voltage signal provided by VGLN can be smaller than the voltage value of the first low voltage signal provided by VGL, so that when the N-level driving signal output terminal NS(N) outputs a low voltage signal and the potential of the first node N1 is a low voltage, T12 and T13 can be turned off well.
  • the first voltage terminal is a high voltage terminal VGHN
  • the second voltage terminal is a first low voltage terminal VGL
  • the third voltage terminal is a second low voltage terminal VGLN.
  • At least one embodiment of the driving circuit described in FIG. 29 of the present disclosure is in operation.
  • NS(N) When NS(N) provides a low voltage signal, T17 is turned on, T18 is turned off, the potential of N6 is a high voltage, T25 is turned on, Turn off T24, NS(N) provides a low voltage signal, and NS(N-1) provides a low voltage signal;
  • NS(N-1) provides a high voltage signal, closes T17, opens T18, the potential of N6 is low voltage, closes T25, and opens T24.
  • NS(N) and NS(N-1) both provide high voltage signals to realize the shift register from NS(N-1) to NS(N);
  • NS(N-1) provides a low voltage signal, turns on T17, turns off T18, the potential of N6 is a high voltage, turns on T25, and turns off T24.
  • NS(N) and NS(N-1) both provide low voltage signals to realize the shift register from NS(N-1) to NS(N).
  • At least one embodiment of the driving circuit shown in FIG. 29 of the present disclosure is in operation.
  • TX1 and TX2 are turned on, and when NS(N) provides a low voltage signal, TX3 and TX4 are turned on.
  • the state of the selection input signal provided by VCT within a high-low frequency switching cycle H can be obtained and written into the first node N1. Then TX1, TX2, TX3 and TX4 will not be turned on at the same time at other times to prevent the potential of N1 from being affected by the potential change of the selection input signal provided by VCT.
  • T10, T11, T12 and T13 form a NAND gate, the input signals of which are the signal provided by NS(N) and the potential of N1, respectively, and the output end of the NAND gate is electrically connected to the second node N2.
  • T24 and T25 form a second inverter circuit, the input end of the second inverter circuit is electrically connected to the fourth node N4, and the output end of the second inverter circuit is electrically connected to NS(N);
  • VCT provides a high voltage signal when TX1, TX2, TX3, and TX4 are turned on, N1 will be written with a high voltage, and the gate state of the NAND gate can ensure that NS(N) is normally passed to NO(N);
  • VCT provides a low voltage signal when TX1, TX2, TX3 and TX4 are turned on
  • N1 will be written with a low voltage, and the NAND gate is in a cut-off state, ensuring that NO(N) provides a low voltage signal, thereby achieving low level maintenance of NO(N).
  • NCX when the display starts (that is, when the display device is turned on), in the power-on stage before the first stage, NCX outputs a low voltage signal, T9 is turned on to control the potential of N1 to be a high voltage, and T26 is turned on to make NS (N) provide High voltage signal; at this time, T12 and T13 are both turned on, the potential of N2 is low voltage, T14 is turned on, T15 is turned off, and NO (N) outputs a high voltage signal, which can turn on the second display control transistor M2 included in all pixel circuits in the effective display area, clear the residual charge in the storage capacitor Cst, and improve the screen flicker when the computer is turned on;
  • TX1, TX2, TX3, and TX4 are turned on.
  • N1 When VCT provides a low voltage signal, the potential of N1 is a low voltage signal, and C0 maintains the potential of N1; T11 is turned on, T10 is turned on, the potential of N2 is a high voltage, T15 is turned on, and NO (N) outputs a low voltage signal;
  • N1 When VCT provides a high voltage signal, the potential of N1 is a high voltage signal, C0 maintains the potential of N1, T11 is turned off, T10 is turned on, the potential of N2 is a high voltage, T15 is turned on, and NO (N) outputs a low voltage signal;
  • NS(N) outputs a high voltage signal.
  • N1 When the potential of N1 is high voltage, T10 is turned off, T11 is turned off, T12 and T13 are turned on, the potential of N2 is low voltage, T14 is turned on, and NO(N) outputs a high voltage signal;
  • NS(N) After the Nth stage of driving signal supply, NS(N) outputs a low voltage signal.
  • N1 When the potential of N1 is a low voltage signal, T10 is turned on, T11 is turned on, the potential of N2 is a high voltage, and NO(N) outputs a low voltage signal;
  • N1 When the potential of N1 is a high voltage signal, T10 is turned on, T11 is turned off, the potential of N2 is a high voltage, and NO(N) outputs a low voltage signal.
  • the first gating circuit includes a first first gating transistor TX11, a first second gating transistor TX12, a first third gating transistor TX13 and a first fourth gating transistor TX14;
  • the second gating circuit includes a second first gating transistor TX21, a second second gating transistor TX22, a second third gating transistor TX23 and a second fourth gating transistor TX24;
  • the gate of the first first selection transistor TX11 is connected to the inverted signal NSI(N-1) of the N-1th stage driving signal, and the drain of the first first selection transistor TX11 is electrically connected to the first selection input terminal VCT1;
  • the gate of the first second selection transistor TX12 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the first second selection transistor TX12 is electrically connected to the first selection input terminal VCT1;
  • the gate of the first third selection transistor TX13 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first third selection transistor TX13 is electrically connected to the source of the first first selection transistor TX11, and the source of the first third selection transistor TX13 is electrically connected to the first first node N11;
  • the gate of the first fourth selection transistor TX14 is connected to the inverted signal NSI(N) of the Nth stage driving signal.
  • the drain of the first fourth selection transistor TX14 is electrically connected to the source of the first second selection transistor TX12, and the source of the first fourth selection transistor TX14 is electrically connected to the first first node N11;
  • the first first selection transistor TX11 is a p-type transistor
  • the first second selection transistor TX12 is an n-type transistor
  • the first third selection transistor TX13 is a p-type transistor
  • the first fourth selection transistor TX14 is an n-type transistor
  • the gate of the second first selection transistor TX21 is connected to the inverted signal NSI(N-1) of the N-1th stage driving signal, and the drain of the second first selection transistor TX21 is electrically connected to the second selection input terminal VCT2;
  • the gate of the second second selection transistor TX22 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second second selection transistor TX22 is electrically connected to the second selection input terminal VCT2;
  • the gate of the second third selection transistor TX23 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the second third selection transistor TX23 is electrically connected to the source of the second first selection transistor TX21, and the source of the second third selection transistor TX23 is electrically connected to the second first node N21;
  • the gate of the second fourth selection transistor TX24 is connected to the inverted signal NSI(N) of the Nth stage driving signal, the drain of the second fourth selection transistor TX24 is electrically connected to the source of the second second selection transistor TX22, and the source of the second fourth selection transistor TX24 is electrically connected to the second first node N21;
  • the second first selection transistor TX21 is a p-type transistor
  • the second second selection transistor TX22 is an n-type transistor
  • the second third selection transistor TX23 is a p-type transistor
  • the second fourth selection transistor TX24 is an n-type transistor
  • the first reset circuit includes a first first transistor T011 and a first second transistor T012;
  • the gate of the first first transistor T011 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the drain of the first first transistor T011 is electrically connected to the high voltage terminal VGHN, and the source of the first first transistor T011 is electrically connected to the drain of the first second transistor T012;
  • the gate of the first second transistor T012 is electrically connected to the Nth stage driving signal output terminal NS(N), and the source of the first second transistor T012 is electrically connected to the first first node N11;
  • T011 and T012 are p-type transistors
  • the second reset circuit includes a second first transistor T021 and a second second transistor T022;
  • the gate of the second first transistor T021 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the drain of the second first transistor T021 is electrically connected to the high voltage terminal VGHN, and the source of the second first transistor T021 is electrically connected to the drain of the second second transistor T022;
  • the gate of the second second transistor T022 is electrically connected to the Nth stage driving signal output terminal NS(N), and the source of the second second transistor T022 is electrically connected to the second first node N21;
  • T021 and T022 are p-type transistors
  • the first first initialization circuit includes a first ninth transistor T019;
  • the gate of the first ninth transistor T019 is electrically connected to the initial control terminal NCX, the drain of the first ninth transistor T019 is electrically connected to the high voltage terminal VGHN, and the source of the first ninth transistor T019 is electrically connected to the initial control terminal NCX. electrically connected to the first first node N11;
  • T019 is a p-type transistor
  • the first first voltage maintaining circuit includes a first capacitor C1; the second first voltage maintaining circuit includes a second capacitor C2;
  • the first end of the first capacitor C1 is electrically connected to the first first node N11, and the second end of the first capacitor C1 is electrically connected to the first low voltage end VGL;
  • the first end of the second capacitor C2 is electrically connected to the second first node N21, and the second end of the second capacitor C2 is electrically connected to the first low voltage end VGL;
  • the first output control circuit includes a first tenth transistor T110, a first eleventh transistor T111, a first twelfth transistor T112 and a first thirteenth transistor T113;
  • the gate of the first tenth transistor T110 is electrically connected to the first first node N11, the drain of the first tenth transistor T110 is electrically connected to the high voltage terminal VGHN, and the source of the first tenth transistor T110 is electrically connected to the first second node N12;
  • the gate of the first eleventh transistor T111 is electrically connected to the Nth stage driving signal output terminal NS(N), the drain of the first eleventh transistor T111 is electrically connected to the high voltage terminal VGHN, and the source of the first eleventh transistor T111 is electrically connected to the first second node N12;
  • the gate of the first twelfth transistor T112 is electrically connected to the first first node N11, the drain of the first twelfth transistor T112 is electrically connected to the first second node N12, and the source of the first twelfth transistor T112 is electrically connected to the drain of the first thirteenth transistor T113;
  • the gate of the first thirteenth transistor T113 is electrically connected to the N-level driving signal output terminal NS(N), and the source of the first thirteenth transistor T113 is electrically connected to the first low voltage terminal VGL;
  • the first tenth transistor T110 and the first eleventh transistor T111 are p-type transistors, and the first twelfth transistor T112 and the first thirteenth transistor T113 are n-type transistors;
  • the first output circuit includes a first fourteenth transistor T114 and a first fifteenth transistor T115;
  • the gate of the first fourteenth transistor T114 is electrically connected to the first second node N12, the drain of the first fourteenth transistor T114 is electrically connected to the high voltage terminal VGHN, and the source of the first fourteenth transistor T114 is electrically connected to the first output driving terminal NO1 (N);
  • the gate of the first fifteenth transistor T115 is electrically connected to the first second node N12, the drain of the first fifteenth transistor T115 is electrically connected to the first output driving terminal NO1 (N), and the source of the first fifteenth transistor T115 is electrically connected to the first low voltage terminal VGL;
  • T114 is a p-type transistor, and T115 is a p-type transistor;
  • the first first initialization circuit includes a first ninth transistor T019;
  • the gate of the first ninth transistor T019 is electrically connected to the initial control terminal NCX, the drain of the first ninth transistor T019 is electrically connected to the high voltage terminal VGHN, and the source of the first ninth transistor T019 is electrically connected to the first first node N11;
  • T019 is a p-type transistor
  • the second first initialization circuit includes a second ninth transistor T029;
  • the gate of the second ninth transistor T029 is electrically connected to the initial control terminal NCX, the drain of the second ninth transistor T029 is electrically connected to the high voltage terminal VGHN, and the source of the second ninth transistor T029 is electrically connected to the second first node N21;
  • T029 is a p-type transistor
  • the first first voltage maintaining circuit includes a first capacitor C1; the second first voltage maintaining circuit includes a second capacitor C2;
  • the first end of the first capacitor C1 is electrically connected to the first first node N11, and the second end of the first capacitor C1 is electrically connected to the first low voltage end VGL;
  • the first end of the second capacitor C2 is electrically connected to the second first node N21, and the second end of the second capacitor C2 is electrically connected to the first low voltage end VGL;
  • the first output control circuit includes a first tenth transistor T110, a first eleventh transistor T111, a first twelfth transistor T112 and a first thirteenth transistor T113;
  • the gate of the first tenth transistor T110 is electrically connected to the first first node N11, the drain of the first tenth transistor T110 is electrically connected to the high voltage terminal VGHN, and the source of the first tenth transistor T110 is electrically connected to the first second node N12;
  • the gate of the first eleventh transistor T111 is electrically connected to the Nth stage driving signal output terminal NS(N), the drain of the first eleventh transistor T111 is electrically connected to the high voltage terminal VGHN, and the source of the first eleventh transistor T111 is electrically connected to the first second node N12;
  • the gate of the first twelfth transistor T112 is electrically connected to the first first node N11, the drain of the first twelfth transistor T112 is electrically connected to the first second node N12, and the source of the first twelfth transistor T112 is electrically connected to the drain of the first thirteenth transistor T113;
  • the gate of the first thirteenth transistor T113 is electrically connected to the N-level driving signal output terminal NS(N), and the source of the first thirteenth transistor T113 is electrically connected to the first low voltage terminal VGL;
  • the first tenth transistor T110 and the first eleventh transistor T111 are p-type transistors, and the first twelfth transistor T112 and the first thirteenth transistor T113 are n-type transistors;
  • the first output circuit includes a first fourteenth transistor T114 and a first fifteenth transistor T115;
  • the gate of the first fourteenth transistor T114 is electrically connected to the first second node N12, the drain of the first fourteenth transistor T114 is electrically connected to the high voltage terminal VGHN, and the source of the first fourteenth transistor T114 is electrically connected to the first output driving terminal NO1 (N);
  • the gate of the first fifteenth transistor T115 is electrically connected to the first second node N12, the drain of the first fifteenth transistor T115 is electrically connected to the first output driving terminal NO1 (N), and the source of the first fifteenth transistor T115 is electrically connected to the first low voltage terminal VGL;
  • T114 is a p-type transistor, and T115 is a p-type transistor;
  • the second output control circuit includes a second tenth transistor T210, a second eleventh transistor T211, a second twelfth transistor T112 and a second thirteenth transistor T213;
  • the gate of the second tenth transistor T210 is electrically connected to the second first node N21, the drain of the second tenth transistor T210 is electrically connected to the high voltage terminal VGHN, and the source of the second tenth transistor T110 is electrically connected to the second second node N22;
  • the gate of the second eleventh transistor T211 is electrically connected to the Nth stage driving signal output terminal NS(N), the drain of the second eleventh transistor T211 is electrically connected to the high voltage terminal VGHN, and the source of the second eleventh transistor T211 is electrically connected to the second second node N22;
  • the gate of the second twelfth transistor T212 is electrically connected to the second first node N21, the drain of the second twelfth transistor T212 is electrically connected to the second second node N22, and the source of the second twelfth transistor T212 is electrically connected to the drain of the second thirteenth transistor T213;
  • the gate of the second thirteenth transistor T213 is electrically connected to the N-level driving signal output terminal NS(N), and the source of the second thirteenth transistor T213 is electrically connected to the first low voltage terminal VGL;
  • the second tenth transistor T210 and the second eleventh transistor T211 are p-type transistors, and the second twelfth transistor T212 and the second thirteenth transistor T213 are n-type transistors;
  • the second output circuit includes a second fourteenth transistor T214 and a second fifteenth transistor T215;
  • the gate of the second fourteenth transistor T214 is electrically connected to the second second node N22, the drain of the second fourteenth transistor T214 is electrically connected to the high voltage terminal VGHN, and the source of the second fourteenth transistor T214 is electrically connected to the second output driving terminal NO2 (N);
  • the gate of the second fifteenth transistor T215 is electrically connected to the second second node N22, the drain of the second fifteenth transistor T215 is electrically connected to the second output driving terminal NO2(N), and the source of the second fifteenth transistor T215 is electrically connected to the first low voltage terminal VGL;
  • T114 is a p-type transistor, and T115 is a p-type transistor;
  • the first driving control circuit includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18 and a nineteenth transistor T19;
  • the gate of the sixteenth transistor T16 is electrically connected to the inverted clock signal terminal NCKI, the drain of the sixteenth transistor T16 is electrically connected to the high voltage terminal VGHN, and the source of the sixteenth transistor T16 is electrically connected to the drain of the seventeenth transistor T17;
  • the gate of the seventeenth transistor T17 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the source of the seventeenth transistor T17 is electrically connected to the fourth node N4;
  • the gate of the eighteenth transistor T18 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the drain of the eighteenth transistor T18 is electrically connected to the fourth node N4, and the source of the eighteenth transistor T18 is electrically connected to the drain of the nineteenth transistor T19;
  • the gate of the nineteenth transistor T19 is electrically connected to the control clock signal terminal NCK, and the source of the nineteenth transistor T19 is electrically connected to the second low voltage terminal LVGL;
  • the sixteenth transistor T16 and the seventeenth transistor T17 are p-type transistors, and the eighteenth transistor T18 and the nineteenth transistor T19 are n-type transistors;
  • the second driving control circuit includes a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22 and a twenty-third transistor T23;
  • a gate of the 20th transistor T20 is electrically connected to the control clock signal terminal NCK, a drain of the 20th transistor T20 is electrically connected to the high voltage terminal VGHN, and a source of the 20th transistor T20 is electrically connected to a drain of the 21st transistor T21;
  • a gate of the twenty-first transistor T21 is electrically connected to the Nth stage driving signal output terminal NS(N), and a source of the twenty-first transistor T21 is electrically connected to the fourth node N4;
  • the gate of the 22nd transistor T22 is electrically connected to the Nth stage driving signal output terminal NS(N), the drain of the 22nd transistor T22 is electrically connected to the fourth node N4, and the source of the 22nd transistor T22 is electrically connected to the drain of the 23rd transistor T23;
  • a gate of the twenty-third transistor T23 is electrically connected to the inverted clock signal terminal NCKI, and a source of the twenty-third transistor T23 is electrically connected to the second low voltage terminal VGLN;
  • the 20th transistor T20 and the 21st transistor T21 are p-type transistors, and the 22nd transistor T22 and the 23rd transistor T23 are n-type transistors;
  • the second inverting circuit includes a twenty-fourth transistor T24 and a twenty-fifth transistor T25; the second initializing circuit includes a twenty-sixth transistor T26;
  • the gate of the 24th transistor T24 is electrically connected to the fourth node N4, the drain of the 24th transistor T24 is electrically connected to the high voltage terminal VGHN, and the source of the 24th transistor T24 is electrically connected to the drain of the 25th transistor T25 and the Nth stage driving signal output terminal NS(N);
  • a gate of the twenty-fifth transistor T25 is electrically connected to the fourth node N4, and a source of the twenty-fifth transistor T25 is electrically connected to the second low voltage terminal VGLN;
  • the twenty-fourth transistor T24 is a p-type transistor, and the twenty-fifth transistor T25 is an n-type transistor;
  • the gate of the 26th transistor T26 is electrically connected to the initial control terminal NCX, the drain of the 26th transistor T26 is electrically connected to the high voltage terminal VGHN, and the source of the 26th transistor T26 is electrically connected to the Nth stage driving signal output terminal NS(N);
  • the twenty-sixth transistor T26 is a p-type transistor
  • the first inverting circuit includes a twenty-seventh transistor T27 and a twenty-eighth transistor T28;
  • the gate of the 27th transistor T27 is electrically connected to the control clock signal terminal NCK, the drain of the 27th transistor T27 is electrically connected to the high voltage terminal VGHN, and the source of the 27th transistor T27 is electrically connected to the drain of the 28th transistor T28 and the inverted clock signal terminal NCKI;
  • a gate of the 28th transistor T28 is electrically connected to the control clock signal terminal NCK, and a source of the 28th transistor T28 is electrically connected to the second low voltage terminal VGLN;
  • the twenty-seventh transistor T27 is a p-type transistor, and the twenty-eighth transistor T28 is an n-type transistor.
  • the voltage value of the second low voltage signal provided by VGLN can be smaller than the voltage value of the first low voltage signal provided by VGL, so that when the N-level driving signal output terminal NS(N) outputs a low voltage signal and the potential of the first node N1 is a low voltage, T12 and T13 can be well turned off.
  • FIG. 31 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 30 .
  • VCT1 and VCT2 can independently write control signals to achieve separate output control of NO1 (N) and NO2 (N).
  • the first output driver terminal of the first level is labeled NO1(1)
  • the first output driver terminal of the second level is labeled NO1(2)
  • the first output driver terminal of the third level is labeled NO1(3)
  • the first output driver terminal of the fourth level is labeled NO1(4)
  • the first output driver terminal of the fifth level is labeled NO1(5)
  • the first output driver terminal of the sixth level is labeled NO1(6)
  • the first output driver terminal of the seventh level is labeled NO1(7)
  • the first output driver terminal of the eighth level is labeled NO1(8)
  • the first output driver terminal of the ninth level is labeled NO1(9)
  • the first output driver terminal of the tenth level is labeled NO1(10)
  • the first output driver terminal of the eleventh level is labeled NO1(11)
  • the first output driver terminal of the twelfth level is labeled NO1(12);
  • the first-level second output driver terminal is labeled NO2(1)
  • the second-level second output driver terminal is labeled NO2(2)
  • the third-level second output driver terminal is labeled NO2(3)
  • the fourth-level second output driver terminal is labeled NO2(4)
  • the fifth-level second output driver terminal is labeled NO2(5)
  • the sixth-level second output driver terminal is labeled NO2(6)
  • the seventh-level second output driver terminal is labeled NO2(7)
  • the eighth-level second output driver terminal is labeled NO2(8)
  • the ninth-level second output driver terminal is labeled NO2(9)
  • the tenth-level second output driver terminal is labeled NO2(10)
  • the eleventh-level second output driver terminal is labeled NO2(11)
  • the twelfth-level second output driver terminal is labeled NO2(12).
  • At least one embodiment of the second voltage maintaining circuit may include a maintaining control circuit, a first inverter, and a second inverter;
  • the sustain control circuit may include a third transistor T3 and a fourth transistor T4;
  • the gate of the third transistor T3 is electrically connected to the N-1th stage driving signal terminal NS(N-1), the drain of the third transistor T3 is electrically connected to the first node N1, and the source of the third transistor T3 is electrically connected to the third node N3;
  • the gate of the fourth transistor T4 is electrically connected to the control clock signal terminal, the drain of the fourth transistor T4 is electrically connected to the third node N3, and the source of the fourth transistor T4 is electrically connected to the first node N1;
  • the third transistor T3 is a p-type transistor, and the fourth transistor T4 is an n-type transistor;
  • the first inverter includes a fifth transistor T5 and a sixth transistor T6, and the second inverter includes a seventh transistor T7 and an eighth transistor T8;
  • the gate of the fifth transistor T5 is electrically connected to the first node N1, the drain of the fifth transistor T5 is electrically connected to the high voltage terminal VGHN, and the source of the fifth transistor T5 is electrically connected to the second node N2;
  • the gate of the sixth transistor T6 is electrically connected to the first node N1, the drain of the sixth transistor T6 is electrically connected to the second node N2, and the source of the sixth transistor T6 is electrically connected to the first low voltage terminal VGL;
  • the fifth transistor T5 is a p-type transistor
  • the sixth transistor T6 is an n-type transistor
  • the gate of the seventh transistor T7 is electrically connected to the second node N2, the drain of the seventh transistor T7 is electrically connected to the high voltage terminal VGHN, and the source of the seventh transistor T7 is electrically connected to the third node N3;
  • the gate of the eighth transistor T8 is electrically connected to the second node N2, the drain of the eighth transistor T8 is electrically connected to the third node N3, and the source of the eighth transistor T8 is electrically connected to the first low voltage terminal VGL;
  • the seventh transistor T7 is a p-type transistor
  • the eighth transistor T8 is an n-type transistor.
  • the gate of the third transistor T3 may be replaced by being electrically connected to the inverted clock signal terminal NCKI or the first clock signal terminal.
  • the absolute value of the potential of N1 will be lower, and the absolute value of the potential of N1 can be controlled to increase by the first inverter and the second inverter, so as to better control the corresponding transistors in the output circuit to be turned on or off, and maintain the control circuit to control the disconnection between N1 and N3 when each selection transistor is turned on, so as not to affect the writing of the potential of N1.
  • the driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes:
  • the driving signal generating circuit performs a shift operation on the N-1th level driving signal under the control of the control clock signal, obtains and outputs the Nth level driving signal through the Nth level driving signal output terminal;
  • the mth gating circuit controls, under the control of the mth gating control signal, to write the mth gating input signal into the mth first node;
  • the mth output control circuit performs a NAND operation on the Nth stage driving signal and the potential of the second end of the mth output control circuit to obtain an mth first output signal;
  • the mth output circuit is used to invert the mth first output signal, and obtain an mth output driving signal through the mth output driving terminal;
  • M is a positive integer
  • m is a positive integer less than or equal to M
  • N is a positive integer
  • the display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.

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Abstract

本公开提供一种驱动电路、驱动方法和显示装置。驱动电路包括驱动信号生成电路、M个输出驱动端和M个控制电路；第m控制电路包括第m选通电路、第m输出控制电路和第m输出电路；M为正整数；m为小于或等于M的正整数；驱动信号生成电路输出第N级驱动信号；第m选通电路在第m选通控制信号的控制下，控制将第m选通输入信号写入第m个第一节点；第m输出控制电路于对第N级驱动信号和第m输出控制电路的第二端的电位进行与非操作，得到第m个第一输出信号；第m输出电路对第m个第一输出信号进行反相，得到第m输出驱动信号；N为正整数。本公开能实现显示屏幕局部画面的更新。

Description

驱动电路、驱动方法和显示装置
相关申请的交叉引用
本申请主张在2023年6月16日在中国提交的中国专利申请号No.202310720909.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动方法和显示装置。
背景技术
在相关技术中，在OLED(有机发光二极管)显示器更新画面时，需要在一帧时间内，对所有行像素电路进行像素电压的初始化和写入。而在某些特殊画面下(如息屏AOD显示画面(息屏AOD显示画面为在不点亮整个手机屏幕的情况下，控制屏幕局部点亮的画面)、静态画面或较少更新的画面)，整屏绝大部分像素电路不需要更新像素电压，即绝大部分像素电路可以通过低漏电的LTPO(低温多晶氧化物)TFT(薄膜晶体管)维持在原有的显示亮度，对这些像素电路的反复刷写造成了功耗的浪费。
发明内容
在一个方面中，本公开提供一种驱动电路，包括驱动信号生成电路、M个输出驱动端和M个控制电路；第m控制电路包括第m选通电路、第m输出控制电路和第m输出电路；M为正整数；m为小于或等于M的正整数；
所述驱动信号生成电路分别与控制时钟信号端、第N-1级驱动信号输出端和第N级驱动信号输出端电连接，用于在所述控制时钟信号端提供的控制时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
第m选通电路分别与第m个第一节点、第m选通输入端和第m选通控制端电连接，用于在所述第m选通控制端提供的第m选通控制信号的控制下，控制将所述第m选通输入端提供的第m选通输入信号写入所述第m个第一节点；
所述第m输出控制电路的第一端与所述第N级驱动信号输出端电连接，所述第m输出控制电路的第二端与所述第m个第一节点电连接，用于对所述第N级驱动信号和所述第m输出控制电路的第二端的电位进行与非操作，得到第m个第一输出信号；
所述第m输出电路用于对所述第m个第一输出信号进行反相，得到并通过第m输出驱动端提供第m输出驱动信号；
N为正整数。
可选的，本公开至少一实施例所述的驱动电路还包括第一反相电路；
所述第一反相电路分别与所述控制时钟信号端和反相时钟信号端电连接，用于对所述控制时钟信号进行反相，得到反相时钟信号，并通过所述反相时钟信号端输出所述反相时钟信号；
所述驱动信号生成电路还与所述反相时钟信号端电连接，还用于在所述反相时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号。
可选的，所述第m选通电路用于在第N-1级驱动信号的电位为第一电压，并第N级驱动信号的电位为第二电压时，控制将所述第m选通输入端提供的第m选通输入信号写入所述第m个第一节点。
可选的，所述第m选通控制端包括第m个第一控制端、第m个第二控制端、第m个第三控制端和第m个第四控制端，所述第m选通电路包括第m个第一选通晶体管、第m个第二选通晶体管、第m个第三选通晶体管和第m个第四选通晶体管；
所述第m个第一选通晶体管的栅极与所述第m个第一控制端电连接，所述第m个第一选通晶体管的第一极与所述第m选通输入端电连接；
所述第m个第二选通晶体管的栅极与所述第m个第二控制端电连接，所述第m个第二选通晶体管的第一极与所述第m选通输入端电连接；
所述第m个第三选通晶体管的栅极与所述第m个第三控制端电连接，所述第m个第三选通晶体管的第一极与所述第m个第一选通晶体管的第二极电连接，所述第m个第三选通晶体管的第二极与所述第m个第一节点电连接；
所述第m个第四选通晶体管的栅极与所述第m个第四控制端电连接，所述第m个第四选通晶体管的第一极与所述第m个第二选通晶体管的第二极电连接，所述第m个第四选通晶体管的第二极与所述第m个第一节点电连接；
所述第m个第一选通晶体管为p型晶体管，所述第m个第二选通晶体管为n型晶体管，所述第m个第三选通晶体管为p型晶体管，所述第m个第四选通晶体管为n型晶体管；
所述第m个第一控制端接入第N-1级驱动信号的反相信号，所述第m个第二控制端为第N-1级驱动信号输出端，所述第m个第三控制端为第N级驱动信号输出端，所述第m个第四控制端接入第N级驱动信号的反相信号；或者，所述第m个第一控制端接入第N级驱动信号的反相信号，所述第m个第二控制端为第N级驱动信号输出端，所述第m个第三控制端为第N-1级驱动信号输出端，所述第m个第四控制端接入第N-1级驱动信号的反相信号。
可选的，所述第m个第一选通晶体管的第二极与所述第m个第二选通晶体管的第二极电连接。
可选的，所述第m选通电路包括第m个第一选通晶体管；
所述第m个第一选通晶体管的栅极与所述第m选通控制端电连接，所述第m个第一 选通晶体管的第一极与所述第m个第一节点电连接，所述第m个第一选通晶体管的第二极与所述第m选通输入端电连接。
可选的，所述第m选通控制端包括第m个第一控制端和第m个第二控制端；所述第m选通电路包括第m个第一选通晶体管和第m个第二选通晶体管；
所述第m个第一选通晶体管的栅极与第m个第一控制端电连接，所述第m个第一选通晶体管的第一极与所述第m个第一节点电连接，所述第m个第一选通晶体管的第二极与所述第m个第二选通晶体管的第一极电连接；
所述第m个第二选通晶体管的栅极与第m个第二控制端电连接，所述第m个第二选通晶体管的第二极与所述第m选通输入端电连接；
所述第m个第一控制端为第N-1级驱动信号输出端，所述第m个第二控制端为第N级驱动信号输出端，第m个第一选通晶体管为n型晶体管，第m个第二选通晶体管为p型晶体管；或者，
所述第m个第一控制端为第N级驱动信号输出端，所述第m个第二控制端为第N-1级驱动信号输出端，第m个第一选通晶体管为p型晶体管，第m个第二选通晶体管为n型晶体管；或者，
所述第m个第一控制端接入第N-1级驱动信号的反相信号，所述第m个第二控制端为第N级驱动信号输出端，所述第m个第一选通晶体管和所述第m个第二选通晶体管都为p型晶体管；或者，
所述第m个第一控制端为第N级驱动信号输出端，所述第m个第二控制端接入第N-1级驱动信号的反相信号；所述第m个第一选通晶体管和所述第m个第二选通晶体管都为p型晶体管；或者，
所述第m个第一控制端为第N-1级驱动信号端，所述第m个第二控制端接入第N级驱动信号的反相信号，所述第m个第一选通晶体管和所述第m个第二选通晶体管都为n型晶体管；或者，
所述第m个第一控制端接入第N级驱动信号的反相信号，所述第m个第二控制端为第N-1级驱动信号端，所述第m个第一选通晶体管和所述第m个第二选通晶体管都为n型晶体管。
可选的，所述第m控制电路还包括第m个第一初始化电路；
所述第m个第一初始化电路分别与初始控制端、第一电压端和第m个第一节点电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第m个第一节点与所述第一电压端之间连通。
可选的，所述第m控制电路还包括第m复位电路；
所述第m复位电路分别与第一电压端、第N-1级驱动信号输出端、第N级驱动信号输出端和第m个第一节点电连接，用于在第N级驱动信号和所述第N-1级驱动信号输出端提供的第N-1级驱动信号的控制下，控制所述第m个第一节点与所述第一电压端之间 连通。
可选的，所述第m控制电路还包括第m个第一电压维持电路；
所述第m个第一电压维持电路的第一端与所述第m个第一节点电连接，所述第m个第一电压维持电路的第二端与直流电压端电连接，所述第m电压维持电路用于维持第m个第一节点的电位。
可选的，所述第m控制电路还包括第m个第二电压维持电路；所述第m个第一节点通过所述第m个第二电压维持电路与所述第m输出控制电路的第二端电连接；
所述第m个第二电压维持电路包括第m个第一反相器、第m个第二反相器和第m维持控制电路；
所述第m个第一反相器的输入端与所述第m个第一节点电连接，所述第m个第一反相器的输出端与第m个第二节点电连接，所述第m个第二反相器的输入端与所述第m个第二节点电连接，所述第m个第二反相器的输出端与第m个第三节点和所述第m输出控制电路的第二端电连接；
所述第m个第一反相器用于对所述第m个第一节点的电位进行反相，并通过第m个第一反相器的输出端输出反相后的第m个第一节点的电位，所述第m个第二反相器用于对其输入端的电位进行反相，并通过所述第m个第二反相器的输出端输出反相后的电位；
所述第m维持控制电路分别与第m维持控制端、所述第m个第三节点和所述第m个第一节点电连接，用于在所述第m维持控制端提供的第m维持控制信号的控制下，控制所述第m个第三节点与所述第m个第一节点之间连通或断开。
可选的，所述第m复位电路包括第m个第一晶体管和第m个第二晶体管；
所述第m个第一晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第m个第一晶体管的第一极与所述第一电压端电连接，所述第m个第一晶体管的第二极与所述第m个第二晶体管的第一极电连接；
所述第m个第二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第m个第二晶体管的第二极与所述第m个第一节点电连接。
可选的，所述第m维持控制端包括第m个第一维持控制端和第m个第二维持控制端；
所述第m维持控制电路包括第m个第三晶体管和第m个第四晶体管；
所述第m个第三晶体管的栅极与所述第m个第一维持控制端电连接，所述第m个第三晶体管的第一极与所述第m个第一节点电连接，所述第m个第三晶体管的第二极与所述第m个第三节点电连接；
所述第m个第四晶体管的栅极与第m个第二维持控制端电连接，所述第m个第四晶体管的第一极与所述第m个第三节点电连接，所述第m个第四晶体管的第二极与所述第m个第一节点电连接；
所述第m个第三晶体管为p型晶体管，所述第m个第四晶体管为n型晶体管；
所述第m个第一维持控制端为第N-1级驱动信号端，所述第m个第二维持控制端为 控制时钟信号端；或者，
所述第m个第一维持控制端为反相时钟信号端，所述第m个第二维持控制端为控制时钟信号端。
可选的，所述第m个第一反相器包括第m个第五晶体管和第m个第六晶体管，所述第m个第二反相器包括第m个第七晶体管和第m个第八晶体管；
所述第m个第五晶体管的栅极与所述第m个第一节点电连接，所述第m个第五晶体管的第一极与第一电压端电连接，所述第m个第五晶体管的第二极与第m个第二节点电连接；
所述第m个第六晶体管的栅极与所述第m个第一节点电连接，所述第m个第六晶体管的第一极与所述第m个第二节点电连接，所述第m个第六晶体管的第二极与第二电压端电连接；
所述第m个第五晶体管为p型晶体管，所述第m个第六晶体管为n型晶体管；
所述第m个第七晶体管的栅极与所述第m个第二节点电连接，所述第m个第七晶体管的第一极与所述第一电压端电连接，所述第m个第七晶体管的第二极与第m个第三节点电连接；
所述第m个第八晶体管的栅极与所述第m个第二节点电连接，所述第m个第八晶体管的第一极与所述第m个第三节点电连接，所述第m个第八晶体管的第二极与第二电压端电连接；
所述第m个第七晶体管为p型晶体管，所述第m个第八晶体管为n型晶体管。
可选的，所述第m个第一初始化电路包括第m个第九晶体管；
所述第m个第九晶体管的栅极与所述初始控制端电连接，所述第m个第九晶体管的第一极与所述第一电压端电连接，所述第m个第九晶体管的第二极与所述第m个第一节点电连接。
可选的，所述第m个第一电压维持电路包括第m电容；
所述第m电容的第一端与所述第m个第一节点电连接，所述第m电容的第二端与直流电压端电连接。
可选的，所述第m输出控制电路包括第m个第十晶体管、第m个第十一晶体管、第m个第十二晶体管和第m个第十三晶体管；
所述第m个第十晶体管的栅极与所述第m个第一节点电连接，所述第m个第十晶体管的第一极与第一电压端电连接，所述第m个第十晶体管的第二极与第m个第二节点电连接；
所述第m个第十一晶体管的栅极与所述第N级驱动信号输出端电连接，所述第m个第十一晶体管的第一极与所述第一电压端电连接，所述第m个第十一晶体管的第二极所述第m个第二节点电连接；
所述第m个第十二晶体管的栅极与所述第m个第一节点电连接，所述第m个第十二 晶体管的第一极与所述第m个第二节点电连接，所述第m个第十二晶体管的第二极与所述第m个第十三晶体管的第一极电连接；
所述第m个第十三晶体管的栅极与所述N级驱动信号输出端电连接，所述第m个第十三晶体管的第二极与第二电压端电连接；
所述第m个第十晶体管和所述第m个第十一晶体管为p型晶体管，所述第m个第十二晶体管和所述第m个第十三晶体管为n型晶体管。
可选的，所述第m输出电路包括第m个第十四晶体管和第m个第十五晶体管；
所述第m个第十四晶体管的栅极与第m个第二节点电连接，所述第m个第十四晶体管的第一极与第一电压端电连接，所述第m个第十四晶体管的第二极与第m输出驱动端电连接；
所述第m个第十五晶体管的栅极与所述第m个第二节点电连接，所述第m个第十五晶体管的第一极与所述第m输出驱动端电连接，所述第m个第十五晶体管的第二极与第二电压端电连接。
可选的，所述驱动信号生成电路包括第一驱动控制电路、第二驱动控制电路、第二反相电路和第二初始化电路；
所述第一驱动控制电路分别与所述控制时钟信号端、所述反相时钟信号端、第N-1级驱动信号输出端和第四节点电连接，用于在所述控制时钟信号端提供的控制时钟信号和所述反相时钟信号端提供的反相时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1驱动信号进行移位并反相，得到并通过所述第四节点输出反相后的信号；
所述第二驱动控制电路分别与所述控制时钟信号端、所述反相时钟信号端、第N级驱动信号输出端和所述第四节点电连接，用于在所述控制时钟信号和所述反相时钟信号的控制下，对所述第N级驱动信号输出端提供的第N级驱动信号进行反相，得到并通过所述第四节点输出反相后的信号；
所述第二反相电路分别与所述第四节点和所述第N级驱动信号输出端电连接，用于对所述第四节点的电位进行反相，并通过所述第N级驱动信号输出端输出反相后的信号；
所述第二初始化电路分别与初始控制端、第一电压端和所述第N级驱动信号输出端电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第N级驱动信号输出端与所述第一电压端之间连通。
可选的，所述第一驱动控制电路包括第十六晶体管、第十七晶体管、第十八晶体管和第十九晶体管；
所述第十六晶体管的栅极与所述反相时钟信号端电连接，所述第十六晶体管的第一极与所述第一电压端电连接，所述第十六晶体管的第二极与所述第十七晶体管的第一极电连接；
所述第十七晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十七晶体管的第二极与所述第四节点电连接；
所述第十八晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十八晶体管的第一极与所述第四节点电连接，所述第十八晶体管的第二极与所述第十九晶体管的第一极电连接；
所述第十九晶体管的栅极与所述控制时钟信号端电连接，所述第十九晶体管的第二极与第三电压端电连接；
所述第十六晶体管和所述第十七晶体管为p型晶体管，所述第十八晶体管和所述第十九晶体管为n型晶体管。
可选的，所述第二驱动控制电路包括第二十晶体管、第二十一晶体管、第二十二晶体管和第二十三晶体管；
所述第二十晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十晶体管的第一极与第一电压端电连接，所述第二十晶体管的第二极与所述第二十一晶体管的第一极电连接；
所述第二十一晶体管的栅极与所述控制时钟信号端电连接，所述第二十一晶体管的第二极与所述第四节点电连接；
所述第二十二晶体管的栅极与所述反相时钟信号端电连接，所述第二十二晶体管的第一极与所述第四节点电连接，所述第二十二晶体管的第二极与所述第二十三晶体管的第一极电连接；
所述第二十三晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十三晶体管的第二极与第三电压端电连接；
所述第二十晶体管和所述第二十一晶体管为p型晶体管，所述第二十二晶体管和所述第二十三晶体管为n型晶体管。
可选的，所述第二反相电路包括第二十四晶体管和第二十五晶体管；所述第二初始化电路包括第二十六晶体管；
所述第二十四晶体管的栅极与所述第四节点电连接，所述第二十四晶体管的第一极与所述第一电压端电连接，所述第二十四晶体管的第二极与所述第二十五晶体管的第一极和所述第N级驱动信号输出端电连接；
所述第二十五晶体管的栅极与所述第四节点电连接，所述第二十五晶体管的第二极与第三电压端电连接；
所述第二十四晶体管为p型晶体管，所述第二十五晶体管为n型晶体管；
所述第二十六晶体管的栅极与所述初始控制端电连接，所述第二十六晶体管的第一极与所述第一电压端电连接，所述第二十六晶体管的第二极与所述第N级驱动信号输出端电连接。
可选的，所述第一反相电路包括第二十七晶体管和第二十八晶体管；
所述第二十七晶体管的栅极与所述控制时钟信号端电连接，所述第二十七晶体管的第一极与第一电压端电连接，所述第二十七晶体管的第二极与所述第二十八晶体管的第一极 和反相时钟信号端电连接；
所述第二十八晶体管的栅极与所述控制时钟信号端电连接，所述第二十八晶体管的第二极与第三电压端电连接。
在第二个方面中，本公开实施例提供一种驱动方法，应用于上述的驱动电路，所述驱动方法包括：
驱动信号生成电路在控制时钟信号的控制下，对第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
第m选通电路在第m选通控制信号的控制下，控制将第m选通输入信号写入第m个第一节点；
第m输出控制电路对所述第N级驱动信号和所述第m输出控制电路的第二端的电位进行与非操作，得到第m个第一输出信号；
第m输出电路用于对所述第m个第一输出信号进行反相，得到并通过第m输出驱动端提供第m输出驱动信号；
M为正整数；m为小于或等于M的正整数，N为正整数。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的驱动电路。
附图说明
图1是本公开至少一实施例所述的驱动电路的结构图；
图2是本公开至少一实施例所述的驱动电路的结构图；
图3是本公开至少一实施例所述的驱动电路的结构图；
图4是本公开至少一实施例所述的驱动电路的结构图；
图5是相关的像素电路的电路图；
图6是图5所示的相关的像素电路的工作时序图；
图7是相关的像素电路的电路图；
图8是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图9是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图10是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图11是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图12是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图13是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图14是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图15是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图16是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图17是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图18是第一反相模块的至少一实施例的电路图；
图19是第二反相模块的至少一实施例的电路图；
图20是本公开至少一实施例所述的驱动电路的结构图；
图21是本公开至少一实施例所述的驱动电路的结构图；
图22是本公开至少一实施例所述的驱动电路的结构图；
图23是本公开至少一实施例所述的驱动电路的结构图；
图24是本公开至少一实施例所述的驱动电路的结构图；
图25是控制时钟信号端NCK提供的控制时钟信号的波形图和第一时钟信号端NCB提供的第一时钟信号的波形图；
图26是本公开至少一实施例所述的驱动电路的结构图；
图27是本公开至少一实施例所述的驱动电路的结构图；
图28是本公开至少一实施例所述的驱动电路的结构图；
图29是本公开至少一实施例所述的驱动电路的电路图；
图30是本公开至少一实施例所述的驱动电路的结构图；
图31是图30所示的驱动电路的至少一实施例的工作时序图；
图32是各级输出驱动端输出的信号的时序图；
图33是第二电压维持电路的至少一实施例的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的驱动电路，包括驱动信号生成电路、M个输出驱动端和M个控制电路；第m控制电路包括第m选通电路、第m输出控制电路和第m输出电路；M为正整数；m为小于或等于M的正整数；
所述驱动信号生成电路分别与控制时钟信号端、第N-1级驱动信号输出端和第N级驱动信号输出端电连接，用于在所述控制时钟信号端提供的控制时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
第m选通电路分别与第m个第一节点、第m选通输入端和第m选通控制端电连接， 用于在所述第m选通控制端提供的第m选通控制信号的控制下，控制将所述第m选通输入端提供的第m选通输入信号写入所述第m个第一节点；
所述第m输出控制电路的第一端与所述第N级驱动信号输出端电连接，所述第m输出控制电路的第二端与所述第m个第一节点电连接，用于对所述第N级驱动信号和所述第m输出控制电路的第二端的电位进行与非操作，得到第m个第一输出信号；
所述第m输出电路用于对所述第m个第一输出信号进行反相，得到并通过第m输出驱动端提供第m输出驱动信号；
N为正整数。
在本公开实施例所述的驱动电路中，一个驱动信号生成电路可以对应至少一个控制电路，驱动信号生成电路在控制时钟信号的控制下，对第N-1级驱动信号进行移位操作，以得到第N级驱动信号，第m控制电路根据所述第N级驱动信号生成第m输出驱动信号。
在本公开至少一实施例中，以m等于1或m等于2为例进行说明，但不以此为限，在实际操作时，m也可以为大于2的整数。
如图1所示，本公开至少一实施例所述的驱动电路包括驱动信号生成电路10、输出驱动端NO(N)和控制电路；所述控制电路包括选通电路11、输出控制电路12和输出电路13；
所述驱动信号生成电路10分别与控制时钟信号端NCK、第N-1级驱动信号输出端NS(N-1)和第N级驱动信号输出端NS(N)电连接，用于在所述控制时钟信号端NCK提供的控制时钟信号的控制下，对所述第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端NS(N)输出第N级驱动信号；
所述选通电路11分别与第一节点N1、选通输入端VCT和选通控制端CX电连接，用于在所述选通控制端CX提供的选通控制信号的控制下，控制将所述选通输入端VCT提供的选通输入信号写入所述第一节点N1；
所述输出控制电路12的第一端与所述第N级驱动信号输出端NS(N)电连接，所述输出控制电路12的第二端与所述第一节点N1电连接，用于对所述第N级驱动信号和所述输出控制电路12的第二端的电位进行与非操作，得到第一输出信号；
所述输出电路13分别与所述输出控制电路12和输出驱动端NO(N)电连接，用于对所述第一输出信号进行反相，得到并通过所述输出驱动端NO(N)提供输出驱动信号；
N为正整数。
本公开图1所示的驱动电路的实施例可以为第N级驱动电路。
本公开图1所示的驱动电路的实施例在工作时，在一帧时间内，
在第N级驱动信号提供阶段之前，选通电路11在选通控制信号的控制下，将选通输入端VCT提供的选通输入信号写入第一节点N1；
当所述选通输入信号为高电压信号时，在第N级驱动信号提供阶段，第N级驱动信 号输出端NS(N)输出高电压信号，则所述输出控制电路12输出的第一输出信号为低电压信号，输出电路13通过输出驱动端NO(N)提供高电压信号，可以控制相应行像素电路更新像素电压；
当所述选通输入信号为低电压信号时，在第N级驱动信号提供阶段，第N级驱动信号输出端NS(N)输出高电压信号，则所述输出控制电路12输出的第一输出信号为高电压信号，输出电路13通过输出驱动端NO(N)提供低电压信号，可以控制相应行像素电路不更新像素电压。
本公开至少一实施例可以通过控制所述选通输入端VCT提供的选通输入信号，实现显示屏幕局部画面的更新，从而降低功耗，或通过显示画面局部更新实现穿戴产品、移动终端、NB(笔记本电脑)等OLED(有机发光二极管)显示产品的超低功耗。
如图2所示，本公开至少一实施例所述的驱动电路包括驱动信号生成电路10、第一输出驱动端NO1(N)、第二输出驱动端NO2(N)、第一控制电路和第二控制电路；所述第一控制电路包括第一选通电路111、第一输出控制电路121和第一输出电路131；所述第二控制电路包括第二选通电路112、第二输出控制电路122和第二输出电路132；
所述驱动信号生成电路10分别与控制时钟信号端NCK、第N-1级驱动信号输出端NS(N-1)和第N级驱动信号输出端NS(N)电连接，用于在所述控制时钟信号端NCK提供的控制时钟信号的控制下，对所述第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端NS(N)输出第N级驱动信号；
所述第一选通电路111分别与第一个第一节点N11、第一选通输入端VCT1和第一选通控制端CX1电连接，用于在所述第一选通控制端CX1提供的第一选通控制信号的控制下，控制将所述第一选通输入端VCT1提供的第一选通输入信号写入所述第一个第一节点N11；
所述第一输出控制电路121的第一端与所述第N级驱动信号输出端NS(N)电连接，所述第一输出控制电路121的第二端与所述第一个第一节点N11电连接，用于对所述第N级驱动信号和所述第一输出控制电路121的第二端的电位进行与非操作，得到第一个第一输出信号；
所述第一输出电路131分别与所述第一输出控制电路121和第一输出驱动端NO1(N)电连接，用于对所述第一个第一输出信号进行反相，得到并通过所述第一输出驱动端NO1(N)提供第一输出驱动信号；
所述第二选通电路112分别与第二个第一节点N21、第二选通输入端VCT2和第二选通控制端CX2电连接，用于在所述第二选通控制端CX2提供的第二选通控制信号的控制下，控制将所述第二选通输入端VCT2提供的第二选通输入信号写入所述第二个第一节点N21；
所述第二输出控制电路122的第一端与所述第N级驱动信号输出端NS(N)电连接， 所述第二输出控制电路122的第二端与所述第二个第一节点N21电连接，用于对所述第N级驱动信号和所述第二输出控制电路122的第二端的电位进行与非操作，得到第二个第一输出信号；
所述第二输出电路132分别与所述第二输出控制电路122和第二输出驱动端NO2(N)电连接，用于对所述第二个第一输出信号进行反相，得到并通过所述第二输出驱动端NO2(N)提供第二输出驱动信号；
N为正整数。
本公开图2所示的驱动电路的实施例可以为第N级驱动电路。
本公开图2所示的驱动电路的实施例在工作时，在一帧时间内，
在第N级驱动信号提供阶段之前，第一选通电路111在第一选通控制信号的控制下，将第一选通输入端VCT1提供的第一选通输入信号写入第一个第一节点N11；第二选通电路112在第二选通控制信号的控制下，将第二选通输入端VCT2提供的第二选通输入信号写入第二个第一节点N21；
当所述第一选通输入信号为高电压信号时，在第N级驱动信号提供阶段，第N级驱动信号输出端NS(N)输出高电压信号，则所述第一输出控制电路121输出的第一个第一输出信号为低电压信号，第一输出电路131通过第一输出驱动端NO1(N)提供高电压信号，可以控制相应行像素电路更新像素电压；
当所述第一选通输入信号为低电压信号时，在第N级驱动信号提供阶段，第N级驱动信号输出端NS(N)输出高电压信号，则所述第一输出控制电路121输出的第一个第一输出信号为高电压信号，第一输出电路131通过第一输出驱动端NO1(N)提供低电压信号，可以控制相应行像素电路不更新像素电压；
当所述第二选通输入信号为高电压信号时，在第N级驱动信号提供阶段，第N级驱动信号输出端NS(N)输出高电压信号，则所述第二输出控制电路122输出的第二个第一输出信号为低电压信号，第二输出电路132通过第二输出驱动端NO2(N)提供高电压信号，可以控制相应行像素电路更新像素电压；
当所述第二选通输入信号为低电压信号时，在第N级驱动信号提供阶段，第N级驱动信号输出端NS(N)输出高电压信号，则所述第二输出控制电路122输出的第二个第一输出信号为高电压信号，第二输出电路132通过第二输出驱动端NO2(N)提供低电压信号，可以控制相应行像素电路不更新像素电压。
本公开至少一实施例可以通过控制所述第一选通输入端VCT1提供的第一选通输入信号和所述第二选通输入端VCT2提供的第二选通输入信号，实现显示屏幕局部画面的更新，从而降低功耗，或通过显示画面局部更新实现穿戴产品、移动终端、NB(笔记本电脑)等OLED(有机发光二极管)显示产品的超低功耗。
在本公开至少一实施例中，所述驱动电路还包括第一反相电路；
所述第一反相电路分别与所述控制时钟信号端和反相时钟信号端电连接，用于对所述 控制时钟信号进行反相，得到反相时钟信号，并通过所述反相时钟信号端输出所述反相时钟信号；
所述驱动信号生成电路还与所述反相时钟信号端电连接，还用于在所述反相时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号。
在具体实施时，所述驱动电路还可以包括第一反相电路，所述第一反相电路对控制时钟信号进行反相，得到反相时钟信号，驱动信号生成电路在所述控制时钟信号和所述反相时钟信号的控制下，对第N-1级驱动信号进行移位操作，得到第N级驱动信号。
如图3所示，在图1所示的驱动电路的至少一实施例的基础上，所述驱动电路还包括第一反相电路31；
所述第一反相电路31分别与所述控制时钟信号端NCK和反相时钟信号端NCKI电连接，用于对所述控制时钟信号进行反相，得到反相时钟信号，并通过所述反相时钟信号端NCKI输出所述反相时钟信号；
所述驱动信号生成电路10还与所述反相时钟信号端NCKI电连接，还用于在所述反相时钟信号的控制下，对所述第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端NS(N)输出第N级驱动信号。
如图4所示，在图2所示的驱动电路的至少一实施例的基础上，所述驱动电路还包括第一反相电路31；
所述第一反相电路31分别与所述控制时钟信号端NCK和反相时钟信号端NCKI电连接，用于对所述控制时钟信号进行反相，得到反相时钟信号，并通过所述反相时钟信号端NCKI输出所述反相时钟信号；
所述驱动信号生成电路10还与所述反相时钟信号端NCKI电连接，还用于在所述反相时钟信号的控制下，对所述第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端NS(N)输出第N级驱动信号。
如图5所示，相关的像素电路可以包括第一显示控制晶体管M1、第二显示控制晶体管M2、驱动晶体管M3、第四显示控制晶体管M4、第五显示控制晶体管M5、第六显示控制晶体管M6、第七显示控制晶体管M7、存储电容Cst和有机发光二极管O1；
M1的栅极与第一复位端NR(N)电连接，M1的源极与初始电压端I1电连接，M1的漏极与M3的栅极电连接；
M2的栅极与第一扫描端NG(N)电连接，M2的源极与M3的栅极电连接，M2的漏极与M3的漏极电连接；
M4的栅极与第二扫描端PG(N)电连接，M4的源极与数据线D1电连接，M4的漏极与M3的源极电连接；
M5的栅极与发光控制端E(N)电连接，M5的源极与电源电压端ELVDD电连接，M5的漏极与M3的源极电连接；
M6的栅极与发光控制端E(N)电连接，M6的源极与M3的漏极电连接，M6的漏极与O1的阳极电连接；O1的阴极与低电平端ELVSS电连接；
M7的栅极与第二扫描端PG(N)电连接，M7的源极与初始电压端I1电连接，M7的漏极与O1的阳极电连接。
在具体实施时，所述第一复位端NR(N)可以为第N-1级第一扫描端NG(N)，但不以此为限。
在图5所示的相关的像素电路中，M1和M2为n型晶体管，M3、M4、M5、M6和M7都为p型晶体管，M1和M2为漏电流较小的IGZO(铟镓锌氧化物)TFT(薄膜晶体管)，M3、M4、M5、M6和M7都为LTPS(低温多晶硅)TFT。
在图5所示的相关的像素电路中，M1和M2为IGZO TFT，在使用低频显示时，IGZO TFT可以保证Cst能够在较长时间内维持M3的栅极的电压。
在图5所示的相关的像素电路中，第二扫描端PG(N)负责O1的阳极的电压的复位和数据线上的数据电压写入驱动晶体管的源极，第一扫描端NG(N)负责实现Cst的复位，Vth(Vth为驱动晶体管的阈值电压)提取和数据电压写入驱动晶体管的栅极。
在具体实施时，所述第一扫描端NG(N)提供的第一扫描信号与所述第二扫描端PG(N)提供的第二扫描信号可以相互反相，但不以此为限。
本公开至少一实施例所述的驱动电路可以通过输出驱动端NO(N)为第一扫描端NG(N)提供第一扫描信号，但不以此为限。
如图6所示，图5所示的相关的像素电路在工作时，显示周期可以包括先后设置的第一显示控制阶段t1、第二显示控制阶段t2和第三显示控制阶段t3；
在第一显示控制阶段t1，E(N)输出高电压信号，NR(N)提供高电压信号，PG(N)提供高电压信号，NG(N)提供低电压信号，M5和M6关断，M1打开，将M3的栅极的电位拉低为初始电压Vinit；所述初始电压端I1用于提供所述初始电压Vinit；
在第二显示控制阶段t2，E(N)输出高电压信号，NR(N)提供低电压信号，PG(N)提供低电压信号，NG(N)提供高电压信号，M5和M6关断，M1关断，M2打开，M4打开，M2与M3形成二极管结构，通过数据线D1提供的数据电压Vdata为Cst充电，直至M3关断，此时M3的栅极电压为Vdata+Vth，Vth为M3的阈值电压；M7打开，以对O1的阳极电压进行复位操作；
在第三显示控制阶段t3，E(N)输出低电压信号，NR(N)提供低电压信号，PG(N)提供高电压信号，NG(N)提供低电压信号，M5和M6打开，M3驱动O1发光；O1依据Vdata的电压设定进行发光。
由以上相关的像素电路的工作过程可知，NG(N)可以在第二显示控制阶段控制数据电压Vdata(所述数据电压Vdata可以为所述像素电压)是否写入M3的栅极。
图7是相关的像素电路的电路图。
如图7所示，相关的像素电路可以包括第一显示控制晶体管M1、第二显示控制晶体 管M2、驱动晶体管M3、第四显示控制晶体管M4、第五显示控制晶体管M5、第六显示控制晶体管M6、第七显示控制晶体管M7、存储电容Cst和有机发光二极管O1；
M1的栅极与第三复位端RST1电连接，M1的源极与初始电压端I1电连接，M1的漏极与M3的漏极电连接；
M2的栅极与第一扫描端NG(N)电连接，M2的源极与M3的栅极电连接，M2的漏极与M3的漏极电连接；
M4的栅极与第二扫描端PG(N)电连接，M4的源极与数据线D1电连接，M4的漏极与M3的源极电连接；
M5的栅极与发光控制端E(N)电连接，M5的源极与电源电压端ELVDD电连接，M5的漏极与M3的源极电连接；
M6的栅极与发光控制端E(N)电连接，M6的源极与M3的漏极电连接，M6的漏极与O1的阳极电连接；O1的阴极与低电平端ELVSS电连接；
M7的栅极与第四复位端RST2电连接，M7的源极与初始电压端I1电连接，M7的漏极与O1的阳极电连接。
图7所示的相关的像素电路在工作时，NG(N)可以控制数据线D1上的数据电压Vdata是否写入驱动晶体管M3的栅极。
在具体实施时，可以通过NG(N)提供的第一扫描信号以控制打开第二晶体管或关断第二晶体管，以控制数据线上的数据电压是否写入驱动晶体管的栅极，从而控制是否对本行像素电路的亮度进行更新；当NG(N)输出高电压信号时，第二晶体管打开，可以对本行像素电路的亮度进行更新；当NG(N)输出低电压信号时，第二晶体管始终关闭，数据线上的数据电压的变化不会写入驱动晶体管的栅极，有机发光二极管的发光亮度不会变化，即当前行像素电路在当前帧的显示亮度维持不变。综上可知，可以通过控制N型晶体管的打开或关闭，即可实现像素亮度的刷新，因此当想实现部分像素不刷新时，保证N型晶体管关闭即可。
可选的，所述第m选通电路用于在第N-1级驱动信号的电位为第一电压，并第N级驱动信号的电位为第二电压时，控制将所述第m选通输入端提供的第m选通输入信号写入所述第m个第一节点。
在具体实施时，所述第m选通电路可以在第N-1级驱动信号的电位为第一电压，并第N级驱动信号的电位为第二电压时，控制将第m选通输入信号写入所述第m个第一节点。
可选的，所述第一电压可以为高电压，所述第二电压可以为低电压，但不以此为限。在本公开至少一实施例中，所述第一电压也可以为低电压，所述第二电压可以为高电压。
可选的，所述第m选通控制端包括第m个第一控制端、第m个第二控制端、第m个第三控制端和第m个第四控制端，所述第m选通电路包括第m个第一选通晶体管、第m个第二选通晶体管、第m个第三选通晶体管和第m个第四选通晶体管；
所述第m个第一选通晶体管的栅极与所述第m个第一控制端电连接，所述第m个第一选通晶体管的第一极与所述第m选通输入端电连接；
所述第m个第二选通晶体管的栅极与所述第m个第二控制端电连接，所述第m个第二选通晶体管的第一极与所述第m选通输入端电连接；
所述第m个第三选通晶体管的栅极与所述第m个第三控制端电连接，所述第m个第三选通晶体管的第一极与所述第m个第一选通晶体管的第二极电连接，所述第m个第三选通晶体管的第二极与所述第m个第一节点电连接；
所述第m个第四选通晶体管的栅极与所述第m个第四控制端电连接，所述第m个第四选通晶体管的第一极与所述第m个第二选通晶体管的第二极电连接，所述第m个第四选通晶体管的第二极与所述第m个第一节点电连接；
所述第m个第一选通晶体管为p型晶体管，所述第m个第二选通晶体管为n型晶体管，所述第m个第三选通晶体管为p型晶体管，所述第m个第四选通晶体管为n型晶体管；
所述第m个第一控制端接入第N-1级驱动信号的反相信号，所述第m个第二控制端为第N-1级驱动信号输出端，所述第m个第三控制端为第N级驱动信号输出端，所述第m个第四控制端接入第N级驱动信号的反相信号；或者，所述第m个第一控制端接入第N级驱动信号的反相信号，所述第m个第二控制端为第N级驱动信号输出端，所述第m个第三控制端为第N-1级驱动信号输出端，所述第m个第四控制端接入第N-1级驱动信号的反相信号。
如图8所示，选通控制端可以包括第一控制端CT1、第二控制端CT2、第三控制端CT3和第四控制端CT4，选通电路的至少一实施例可以包括第一选通晶体管TX1、第二选通晶体管TX2、第三选通晶体管TX3和第四选通晶体管TX4；
所述第一选通晶体管TX1的栅极与第一控制端CT1电连接，所述第一选通晶体管TX1的漏极与选通输入端VCT电连接；
所述第二选通晶体管TX2的栅极与第二控制端CT2电连接，所述第二选通晶体管TX2的漏极与所述选通输入端VCT电连接；
所述第三选通晶体管TX3的栅极与所述第三控制端CT3电连接，所述第三选通晶体管TX3的漏极与所述第一选通晶体管TX1的源极电连接，所述第三选通晶体管TX3的源极与第一节点N1电连接；
所述第四选通晶体管TX4的栅极与所述第四控制端CT4电连接，所述第四选通晶体管TX4的漏极与所述第二选通晶体管TX2的源极电连接，所述第四选通晶体管TX4的源极与所述第一节点N1电连接；
所述第一选通晶体管TX1为p型晶体管，所述第二选通晶体管TX2为n型晶体管，所述第三选通晶体管TX3为p型晶体管，所述第四选通晶体管TX4为n型晶体管；
所述第一控制端CT1可以接入第N-1级驱动信号的反相信号，所述第二控制端CT2 可以为第N-1级驱动信号输出端，所述第三控制端CT3可以为第N级驱动信号输出端，所述第四控制端CT4可以接入第N级驱动信号的反相信号；或者，所述第一控制端CT1可以接入第N级驱动信号的反相信号，所述第二控制端CT2可以为第N级驱动信号输出端，所述第三控制端CT3可以为第N-1级驱动信号输出端，所述第四控制端CT4可以接入第N-1级驱动信号的反相信号。
在本公开至少一实施例中，所述第m个第一选通晶体管的第二极与所述第m个第二选通晶体管的第二极电连接。
如图9所示，在图8所示的选通电路的至少一实施例的基础上，所述第一选通晶体管TX1的源极与所述第二选通晶体管TX2的源极电连接。
可选的，所述第m选通电路包括第m个第一选通晶体管；
所述第m个第一选通晶体管的栅极与所述第m选通控制端电连接，所述第m个第一选通晶体管的第一极与所述第m个第一节点电连接，所述第m个第一选通晶体管的第二极与所述第m选通输入端电连接。
如图10所示，所述选通电路的至少一实施例可以包括第一选通晶体管TX1；
所述第一选通晶体管TX1的栅极与选通控制端S0电连接，所述第一选通晶体管TX1的漏极与第一节点N1电连接，所述第一选通晶体管TX1的源极与选通输入端VCT电连接；
TX1为p型晶体管。
如图11所示，所述选通电路的至少一实施例可以包括第一选通晶体管TX1；
所述第一选通晶体管TX1的栅极与选通控制端S0电连接，所述第一选通晶体管TX1的源极与第一节点N1电连接，所述第一选通晶体管TX1的漏极与选通输入端VCT电连接；
TX1为n型晶体管。
可选的，所述第m选通控制端包括第m个第一控制端和第m个第二控制端；所述第m选通电路包括第m个第一选通晶体管和第m个第二选通晶体管；
所述第m个第一选通晶体管的栅极与第m个第一控制端电连接，所述第m个第一选通晶体管的第一极与所述第m个第一节点电连接，所述第m个第一选通晶体管的第二极与所述第m个第二选通晶体管的第一极电连接；
所述第m个第二选通晶体管的栅极与第m个第二控制端电连接，所述第m个第二选通晶体管的第二极与所述第m选通输入端电连接；
所述第m个第一控制端为第N-1级驱动信号输出端，所述第m个第二控制端为第N级驱动信号输出端，第m个第一选通晶体管为n型晶体管，第m个第二选通晶体管为p型晶体管；或者，
所述第m个第一控制端为第N级驱动信号输出端，所述第m个第二控制端为第N-1级驱动信号输出端，第m个第一选通晶体管为p型晶体管，第m个第二选通晶体管为n 型晶体管；或者，
所述第m个第一控制端接入第N-1级驱动信号的反相信号，所述第m个第二控制端为第N级驱动信号输出端，所述第m个第一选通晶体管和所述第m个第二选通晶体管都为p型晶体管；或者，
所述第m个第一控制端为第N级驱动信号输出端，所述第m个第二控制端接入第N-1级驱动信号的反相信号；所述第m个第一选通晶体管和所述第m个第二选通晶体管都为p型晶体管；或者，
所述第m个第一控制端为第N-1级驱动信号端，所述第m个第二控制端接入第N级驱动信号的反相信号，所述第m个第一选通晶体管和所述第m个第二选通晶体管都为n型晶体管；或者，
所述第m个第一控制端接入第N级驱动信号的反相信号，所述第m个第二控制端为第N-1级驱动信号端，所述第m个第一选通晶体管和所述第m个第二选通晶体管都为n型晶体管。
如图12所示，所述选通电路的至少一实施例可以包括第一选通晶体管TX1和第二选通晶体管TX2；
所述第一选通晶体管TX1的栅极与第N-1级驱动信号输出端NS(N-1)电连接，所述第一选通晶体管TX1的源极与所述第一节点N1电连接，所述第一选通晶体管TX1的漏极与所述第二选通晶体管TX2的漏极电连接；
所述第二选通晶体管TX2的栅极与第N级驱动信号输出端NS(N)电连接，所述第二选通晶体管TX2的源极与所述选通输入端VCT电连接；
TX1为n型晶体管，TX2为p型晶体管。
如图13所示，所述选通电路的至少一实施例可以包括第一选通晶体管TX1和第二选通晶体管TX2；
所述第一选通晶体管TX1的栅极与第N级驱动信号输出端NS(N)电连接，所述第一选通晶体管TX1的漏极与所述第一节点N1电连接，所述第一选通晶体管TX1的源极与所述第二选通晶体管T2的源极电连接；
所述第二选通晶体管TX2的栅极与第N-1级驱动信号输出端NS(N-1)电连接，所述第二选通晶体管TX2的漏极与所述选通输入端VCT电连接；
TX1为p型晶体管，TX2为n型晶体管。
如图14所示，所述选通电路的至少一实施例可以包括第一选通晶体管TX1和第二选通晶体管TX2；
所述第一选通晶体管TX1的栅极与第一反相驱动信号端NGI1电连接，所述第一选通晶体管TX1的漏极与所述第一节点N1电连接，所述第一选通晶体管TX1的源极与所述第二选通晶体管TX2的漏极电连接；所述第一反相驱动信号端NGI1提供的第一反相驱动信号与第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号反相；
所述第二选通晶体管TX2的栅极与第N级驱动信号输出端NS(N)电连接，所述第二选通晶体管TX2的源极与所述选通输入端VCT电连接；
TX1为p型晶体管，TX2为p型晶体管。
如图15所示，所述选通电路的至少一实施例可以包括第一晶体管TX1和第二晶体管TX2；
所述第一选通晶体管TX1的栅极与第N级驱动信号输出端NS(N)电连接，所述第一选通晶体管TX1的漏极与所述第一节点N1电连接，所述第一选通晶体管TX1的源极与所述第二选通晶体管TX2的漏极电连接；
所述第二选通晶体管TX2的栅极与第一反相驱动信号端NGI1电连接，所述第二选通晶体管TX2的源极与所述选通输入端VCT电连接；所述第一反相驱动信号端NGI1提供的第一反相驱动信号与第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号反相；
TX1为p型晶体管，TX2为p型晶体管。
如图16所示，所述选通电路的至少一实施例可以包括第一选通晶体管TX1和第二选通晶体管TX2；
所述第一选通晶体管TX1的栅极与第N-1级驱动信号输出端NS(N-1)电连接，所述第一选通晶体管TX1的源极与所述第一节点N1电连接，所述第一选通晶体管TX1的漏极与所述第二选通晶体管TX2的源极电连接；
所述第二选通晶体管TX2的栅极与第二反相驱动信号端NGI2电连接，所述第二选通晶体管TX2的漏极与所述选通输入端VCT电连接；所述第二反相驱动信号端NGI2提供的第二反相驱动信号与第N级驱动信号输出端NS(N)提供的第N级驱动信号反相；
TX1为n型晶体管，TX2为n型晶体管。
如图17所示，所述选通电路的至少一实施例可以包括第一选通晶体管TX1和第二选通晶体管TX2；
所述第一选通晶体管TX1的栅极与第二反相驱动信号端NGI2电连接，所述第一选通晶体管TX1的源极与所述第一节点N1电连接，所述第一选通晶体管TX1的漏极与所述第二选通晶体管TX2的源极电连接；所述第二反相驱动信号端NGI2提供的第二反相驱动信号与第N级驱动信号输出端NS(N)提供的第N级驱动信号反相；
所述第二选通晶体管TX2的栅极与第N-1级驱动信号输出端NS(N-1)电连接，所述第二选通晶体管TX2的漏极与所述选通输入端VCT电连接；
TX1为n型晶体管，TX2为n型晶体管。
如图18所示，可以通过第一反相模块对第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号进行反相，得到第一反相驱动信号端NGI1提供的第一反相驱动信号；
所述第一反相模块包括第一反相控制晶体管T01和第二反相控制晶体管T02；
T01为p型晶体管，T02为n型晶体管。
如图19所示，可以通过第二反相模块对第N级驱动信号输出端NS(N)提供的第N 级驱动信号进行反相，得到第二反相驱动信号端NGI2提供的第二反相驱动信号；
所述第二反相模块包括第三反相控制晶体管T03和第四反相控制晶体管T04；
T03为p型晶体管，T04为n型晶体管。
在本公开至少一实施例中，所述第m控制电路还包括第m个第一初始化电路；
所述第m个第一初始化电路分别与初始控制端、第一电压端和第m个第一节点电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第m个第一节点与所述第一电压端之间连通。
在具体实施时，所述第m控制电路还可以包括第m个第一初始化电路，第m个第一初始化电路在初始控制信号的控制下，控制第m个第一节点与第一电压端之间连通。
在本公开至少一实施例中，所述第一电压端可以为高电压端，但不以此为限。
如图20所示，在图3所示的驱动电路的至少一实施例的基础上，所述控制电路还可以包括第一初始化电路21；
所述第一初始化电路21分别与初始控制端NCX、第一电压端V1和第一节点N1电连接，用于在所述初始控制端NCX提供的初始控制信号的控制下，控制所述第一节点N1与所述第一电压端V1之间连通。
图20所示的驱动电路的至少一实施例在工作时，在一帧时间开始时，NCX提供有效电压信号，所述第一初始化电路21控制第一节点N1与第一电压端V1之间连通。
如图21所示，在图4所示的驱动电路的至少一实施例的基础上，所述第一控制电路还可以包括第一个第一初始化电路211，所述第二控制电路还可以包括第二个第一初始化电路212；
所述第一个第一初始化电路211分别与初始控制端NCX、第一电压端V1和第一个第一节点N11电连接，用于在所述初始控制端NCX提供的初始控制信号的控制下，控制所述第一个第一节点N11与所述第一电压端V1之间连通；
所述第二个第一初始化电路212分别与初始控制端NCX、第一电压端V1和第二个第一节点N21电连接，用于在所述初始控制端NCX提供的初始控制信号的控制下，控制所述第二个第一节点N21与所述第一电压端V1之间连通。
在本公开至少一实施例中，所述第m控制电路还包括第m复位电路；
所述第m复位电路分别与第一电压端、第N-1级驱动信号输出端、第N级驱动信号输出端和第m个第一节点电连接，用于在第N级驱动信号和所述第N-1级驱动信号输出端提供的第N-1级驱动信号的控制下，控制所述第m个第一节点与所述第一电压端之间连通。
在具体实施时，所述第m控制电路还可以包括第m复位电路，第m复位电路在第N级驱动信号和第N-1级驱动信号的控制下，在所述第m输出电路通过第m输出驱动端提供第m输出驱动信号后，对所述第m个第一节点的电位进行复位。
在本公开至少一实施例中，所述第m控制电路还包括第m个第一电压维持电路；
所述第m个第一电压维持电路的第一端与所述第m个第一节点电连接，所述第m个第一电压维持电路的第二端与直流电压端电连接，所述第m电压维持电路用于维持第m个第一节点的电位。
在具体实施时，所述第m控制电路还可以包括第m个第一电压维持电路，所述第m个第一电压维持电路可以用于维持第m个第一节点的电位。
可选的，所述直流电压端可以为第一电压端、第二电压端或第三电压端，但不以此为限。
在本公开至少一实施例中，所述第一电压端可以为高电压端，所述第二电压端可以为第一低电压端，所述第三电压端可以为第二低电压端，但不以此为限。
如图22所示，在图20所示的驱动电路的至少一实施例的基础上，所述控制电路还可以包括第一电压维持电路22和复位电路23；
所述复位电路23分别与第一电压端V1、第N-1级驱动信号输出端NS(N-1)、第N级驱动信号输出端NS(N)和第一节点N1电连接，用于在第N级驱动信号和所述第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号的控制下，控制所述第一节点N1与所述第一电压端V1之间连通；
所述第一电压维持电路22的第一端与所述第一节点N1电连接，所述第一电压维持电路22的第二端与第二电压端V2电连接，所述第一电压维持电路22用于维持所述第一节点N1的电位。
如图23所示，在图21所示的驱动电路的至少一实施例的基础上，所述第一控制电路还可以包括第一个第一电压维持电路221和第一复位电路231；所述第二控制电路还可以包括第二个第一电压维持电路222和第二复位电路232；
所述第一复位电路231分别与第一电压端V1、第N-1级驱动信号输出端NS(N-1)、第N级驱动信号输出端NS(N)和第一个第一节点N11电连接，用于在第N级驱动信号和所述第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号的控制下，控制所述第一个第一节点N11与所述第一电压端V1之间连通；
所述第一个第一电压维持电路221的第一端与所述第一个第一节点N11电连接，所述第一个第一电压维持电路221的第二端与第二电压端V2电连接，所述第一个第一电压维持电路221用于维持所述第一个第一节点N11的电位；
所述第二复位电路232分别与第一电压端V1、第N-1级驱动信号输出端NS(N-1)、第N级驱动信号输出端NS(N)和第二个第一节点N21电连接，用于在第N级驱动信号和所述第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号的控制下，控制所述第二个第一节点N21与所述第一电压端V1之间连通；
所述第二个第一电压维持电路222的第一端与所述第二个第一节点N21电连接，所述第二个第一电压维持电路222的第二端与第二电压端V2电连接，所述第二个第一电压维持电路222用于维持所述第二个第一节点N21的电位。
可选的，所述第m控制电路还包括第m个第二电压维持电路；所述第m个第一节点通过所述第m个第二电压维持电路与所述第m输出控制电路的第二端电连接；
所述第m个第二电压维持电路包括第m个第一反相器、第m个第二反相器和第m维持控制电路；
所述第m个第一反相器的输入端与所述第m个第一节点电连接，所述第m个第一反相器的输出端与第m个第二节点电连接，所述第m个第二反相器的输入端与所述第m个第二节点电连接，所述第m个第二反相器的输出端与第m个第三节点和所述第m输出控制电路的第二端电连接；
所述第m个第一反相器用于对所述第m个第一节点的电位进行反相，并通过第m个第一反相器的输出端输出反相后的第m个第一节点的电位，所述第m个第二反相器用于对其输入端的电位进行反相，并通过所述第m个第二反相器的输出端输出反相后的电位；
所述第m维持控制电路分别与第m维持控制端、所述第m个第三节点和所述第m个第一节点电连接，用于在所述第m维持控制端提供的第m维持控制信号的控制下，控制所述第m个第三节点与所述第m个第一节点之间连通或断开。
在具体实施时，所述第m控制电路还可以包括第m个第二电压维持电路，所述第m个第一节点可以通过所述第m个第二电压维持电路与所述第m输出控制电路的第二端电连接，所述第m个第二电压维持电路可以包括第m个第一反相器、第m个第二反相器和第m维持控制电路；第m个第一反相器对所述第m个第一节点的电位进行反相，第m个第二反相器对其输入端的电位进行反相；所述第m维持控制电路在所述第m维持控制端提供的维持控制信号的控制下，控制所述第m个第三节点与所述第m个第一节点之间连通或断开；
所述第m维持控制电路可以在所述第m选通电路控制将所述第m选通输入信号写入所述第m个第一节点时，控制第m个第三节点与第m个第一节点之间断开。
本公开至少一实施例所述的驱动电路在工作时，通过增设第m个第二电压维持电路，第m个第二电压维持电路包括的第m个第一反相器和第m个第二反相器可以当第m个第一节点的电位为高电压时，控制第m个第三节点与高电压端之间连通，可以使得第m个第三节点的电位高于第m个第一节点的电位，并可以当第m个第一节点的电位为低电压时，控制第m个第三节点与低电压端之间连通，可以使得第m个第三节点的电位低于第m个第一节点的电位，使得第m个第三节点能够更好的控制第m输出控制电路包括的栅极与第m个第三节点电连接的晶体管。
如图24所示，在图22所示的驱动电路的至少一实施例的基础上，所述控制电路还可以包括第二电压维持电路；维持控制端包括第N-1级驱动信号输出端NS(N-1)和控制时钟信号端NCK；所述第一节点N1通过所述第二电压维持电路与所述输出控制电路12的第二端电连接；
所述第二电压维持电路包括第一反相器F1、第二反相器F2和维持控制电路W1；
所述第一反相器F1的输入端与所述第一节点N1电连接，所述第一反相器F1的输出端与第二节点N2电连接；
所述第二反相器F2的输入端与所述第二节点N2电连接，所述第二反相器F2的输出端与第三节点N3和所述输出控制电路12的第二端电连接；
所述第一反相器F1用于对所述第一节点N1的电位进行反相，并通过第一反相器F1的输出端输出反相后的第一节点N1的电位；
所述第二反相器F2用于对其输入端的电位进行反相，并通过所述第二反相器F2的输出端输出反相后的电位；
所述维持控制电路W1分别与第N-1级驱动信号输出端NS(N-1)、控制时钟信号端NCK、所述第三节点N3和所述第一节点N1电连接，用于在第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号的控制下，控制所述第三节点N3与所述第一节点N1之间连通或断开，在所述控制时钟信号端NCK提供的控制时钟信号的控制下，控制所述第三节点N3与所述第一节点N1之间连通或断开。
在图24所示的至少一实施例中，第N-1级驱动信号输出端可以被替换为反相时钟信号端或第一时钟信号端，但不以此为限。
图25示出了控制时钟信号端NCK提供的控制时钟信号的波形和第一时钟信号端NCB提供的第一时钟信号的波形。
在本公开至少一实施例中，所述驱动信号生成电路包括第一驱动控制电路、第二驱动控制电路、第二反相电路和第二初始化电路；
所述第一驱动控制电路分别与所述控制时钟信号端、所述反相时钟信号端、第N-1级驱动信号输出端和第四节点电连接，用于在所述控制时钟信号端提供的控制时钟信号和所述反相时钟信号端提供的反相时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1驱动信号进行移位并反相，得到并通过所述第四节点输出反相后的信号；
所述第二驱动控制电路分别与所述控制时钟信号端、所述反相时钟信号端、第N级驱动信号输出端和所述第四节点电连接，用于在所述控制时钟信号和所述反相时钟信号的控制下，对所述第N级驱动信号输出端提供的第N级驱动信号进行反相，得到并通过所述第四节点输出反相后的信号；
所述第二反相电路分别与所述第四节点和所述第N级驱动信号输出端电连接，用于对所述第四节点的电位进行反相，并通过所述第N级驱动信号输出端输出反相后的信号；
所述第二初始化电路分别与初始控制端、第一电压端和所述第N级驱动信号输出端电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第N级驱动信号输出端与所述第一电压端之间连通。
在本公开至少一实施例中，当M等于1时，所述控制电路可以包括第一电压维持电路和/或第二电压维持电路，以维持第一节点的电位；
当M大于1时，第m控制电路可以包括第m个第一电压维持电路和/或第m个第二 电压维持电路，以维持第m个第一节点的电位。
可选的，所述第m复位电路包括第m个第一晶体管和第m个第二晶体管；
所述第m个第一晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第m个第一晶体管的第一极与所述第一电压端电连接，所述第m个第一晶体管的第二极与所述第m个第二晶体管的第一极电连接；
所述第m个第二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第m个第二晶体管的第二极与所述第m个第一节点电连接。
可选的，所述第m维持控制端包括第m个第一维持控制端和第m个第二维持控制端；
所述第m维持控制电路包括第m个第三晶体管和第m个第四晶体管；
所述第m个第三晶体管的栅极与所述第m个第一维持控制端电连接，所述第m个第三晶体管的第一极与所述第m个第一节点电连接，所述第m个第三晶体管的第二极与所述第m个第三节点电连接；
所述第m个第四晶体管的栅极与第m个第二维持控制端电连接，所述第m个第四晶体管的第一极与所述第m个第三节点电连接，所述第m个第四晶体管的第二极与所述第m个第一节点电连接；
所述第m个第三晶体管为p型晶体管，所述第m个第四晶体管为n型晶体管；
所述第m个第一维持控制端为第N-1级驱动信号端，所述第m个第二维持控制端为控制时钟信号端；或者，
所述第m个第一维持控制端为反相时钟信号端，所述第m个第二维持控制端为控制时钟信号端。
可选的，所述第m个第一反相器包括第m个第五晶体管和第m个第六晶体管，所述第m个第二反相器包括第m个第七晶体管和第m个第八晶体管；
所述第m个第五晶体管的栅极与所述第m个第一节点电连接，所述第m个第五晶体管的第一极与第一电压端电连接，所述第m个第五晶体管的第二极与第m个第二节点电连接；
所述第m个第六晶体管的栅极与所述第m个第一节点电连接，所述第m个第六晶体管的第一极与所述第m个第二节点电连接，所述第m个第六晶体管的第二极与第二电压端电连接；
所述第m个第五晶体管为p型晶体管，所述第m个第六晶体管为n型晶体管；
所述第m个第七晶体管的栅极与所述第m个第二节点电连接，所述第m个第七晶体管的第一极与所述第一电压端电连接，所述第m个第七晶体管的第二极与第m个第三节点电连接；
所述第m个第八晶体管的栅极与所述第m个第二节点电连接，所述第m个第八晶体管的第一极与所述第m个第三节点电连接，所述第m个第八晶体管的第二极与第二电压端电连接；
所述第m个第七晶体管为p型晶体管，所述第m个第八晶体管为n型晶体管。
可选的，所述第m个第一初始化电路包括第m个第九晶体管；
所述第m个第九晶体管的栅极与所述初始控制端电连接，所述第m个第九晶体管的第一极与所述第一电压端电连接，所述第m个第九晶体管的第二极与所述第m个第一节点电连接。
可选的，所述第m个第一电压维持电路包括第m电容；
所述第m电容的第一端与所述第m个第一节点电连接，所述第m电容的第二端与直流电压端电连接。
可选的，所述第m输出控制电路包括第m个第十晶体管、第m个第十一晶体管、第m个第十二晶体管和第m个第十三晶体管；
所述第m个第十晶体管的栅极与所述第m个第一节点电连接，所述第m个第十晶体管的第一极与第一电压端电连接，所述第m个第十晶体管的第二极与第m个第二节点电连接；
所述第m个第十一晶体管的栅极与所述第N级驱动信号输出端电连接，所述第m个第十一晶体管的第一极与所述第一电压端电连接，所述第m个第十一晶体管的第二极所述第m个第二节点电连接；
所述第m个第十二晶体管的栅极与所述第m个第一节点电连接，所述第m个第十二晶体管的第一极与所述第m个第二节点电连接，所述第m个第十二晶体管的第二极与所述第m个第十三晶体管的第一极电连接；
所述第m个第十三晶体管的栅极与所述N级驱动信号输出端电连接，所述第m个第十三晶体管的第二极与第二电压端电连接；
所述第m个第十晶体管和所述第m个第十一晶体管为p型晶体管，所述第m个第十二晶体管和所述第m个第十三晶体管为n型晶体管。
可选的，所述第m输出电路包括第m个第十四晶体管和第m个第十五晶体管；
所述第m个第十四晶体管的栅极与第m个第二节点电连接，所述第m个第十四晶体管的第一极与第一电压端电连接，所述第m个第十四晶体管的第二极与第m输出驱动端电连接；
所述第m个第十五晶体管的栅极与所述第m个第二节点电连接，所述第m个第十五晶体管的第一极与所述第m输出驱动端电连接，所述第m个第十五晶体管的第二极与第二电压端电连接。
在本公开至少一实施例中，所述驱动信号生成电路包括第一驱动控制电路、第二驱动控制电路、第二反相电路和第二初始化电路；
所述第一驱动控制电路分别与所述控制时钟信号端、所述反相时钟信号端、第N-1级驱动信号输出端和第四节点电连接，用于在所述控制时钟信号端提供的控制时钟信号和所述反相时钟信号端提供的反相时钟信号的控制下，对所述第N-1级驱动信号输出端提供 的第N-1驱动信号进行移位并反相，得到并通过所述第四节点输出反相后的信号；
所述第二驱动控制电路分别与所述控制时钟信号端、所述反相时钟信号端、第N级驱动信号输出端和所述第四节点电连接，用于在所述控制时钟信号和所述反相时钟信号的控制下，对所述第N级驱动信号输出端提供的第N级驱动信号进行反相，得到并通过所述第四节点输出反相后的信号；
所述第二反相电路分别与所述第四节点和所述第N级驱动信号输出端电连接，用于对所述第四节点的电位进行反相，并通过所述第N级驱动信号输出端输出反相后的信号；
所述第二初始化电路分别与初始控制端、第一电压端和所述第N级驱动信号输出端电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第N级驱动信号输出端与所述第一电压端之间连通。
在具体实施时，所述驱动信号生成电路可以包括第一驱动控制电路、第二驱动控制电路、第二反相电路和第二初始化电路；所述第一驱动控制电路在控制时钟信号和反相时钟信号的控制下，对第N-1驱动信号进行移位并反相操作，通过第四节点输出反相后的信号，第二驱动控制电路在控制时钟信号和反相时钟信号的控制下，对第N级驱动信号进行反相，通过第四节点输出反相后的信号，第二反相电路对第四节点的电位进行反相，通过第N级驱动信号输出端输出反相后的信号；第二初始化电路在初始控制信号的控制下，控制第N级驱动信号输出端与第一电压端之间连通。
如图26所示，在图24所示的驱动电路的至少一实施例的基础上，所述驱动信号生成电路可以包括第一驱动控制电路41、第二驱动控制电路42、第二反相电路44和第二初始化电路40；
所述第一驱动控制电路41分别与控制时钟信号端NCK、反相时钟信号端NCKI、第N-1级驱动信号输出端NS(N-1)和第四节点N4电连接，用于在所述控制时钟信号端NCK提供的控制时钟信号和所述反相时钟信号端NCKI提供的反相时钟信号的控制下，对所述第N-1级驱动信号输出端NS(N-1)提供的第N-1驱动信号进行移位并反相，得到并通过所述第四节点N4输出反相后的信号；
所述第二驱动控制电路42分别与所述控制时钟信号端NCK、所述反相时钟信号端NCKI、第N级驱动信号输出端NS(N)和第四节点N4电连接，用于在所述控制时钟信号和所述反相时钟信号的控制下，对所述第N级驱动信号输出端NS(N)提供的第N级驱动信号进行反相，得到并通过所述第四节点N4输出反相后的信号；
所述第二反相电路44分别与所述第四节点N4和所述第N级驱动信号输出端NS(N)电连接，用于对所述第四节点N4的电位进行反相，并通过所述第N级驱动信号输出端NS(N)输出反相后的信号；
所述第二初始化电路40分别与初始控制端NCX、第一电压端V1和所述第N级驱动信号输出端NS(N)电连接，用于在所述初始控制端NCX提供的初始控制信号的控制下，控制所述第N级驱动信号输出端NS(N)与所述第一电压端V1之间连通。
如图27所示，在图23所示的驱动电路的至少一实施例的基础上，所述驱动信号生成电路可以包括第一驱动控制电路41、第二驱动控制电路42、第二反相电路44和第二初始化电路40；
所述第一驱动控制电路41分别与控制时钟信号端NCK、反相时钟信号端NCKI、第N-1级驱动信号输出端NS(N-1)和第四节点N4电连接，用于在所述控制时钟信号端NCK提供的控制时钟信号和所述反相时钟信号端NCKI提供的反相时钟信号的控制下，对所述第N-1级驱动信号输出端NS(N-1)提供的第N-1驱动信号进行移位并反相，得到并通过所述第四节点N4输出反相后的信号；
所述第二驱动控制电路42分别与所述控制时钟信号端NCK、所述反相时钟信号端NCKI、第N级驱动信号输出端NS(N)和第四节点N4电连接，用于在所述控制时钟信号和所述反相时钟信号的控制下，对所述第N级驱动信号输出端NS(N)提供的第N级驱动信号进行反相，得到并通过所述第四节点N4输出反相后的信号；
所述第二反相电路44分别与所述第四节点N4和所述第N级驱动信号输出端NS(N)电连接，用于对所述第四节点N4的电位进行反相，并通过所述第N级驱动信号输出端NS(N)输出反相后的信号；
所述第二初始化电路40分别与初始控制端NCX、第一电压端V1和所述第N级驱动信号输出端NS(N)电连接，用于在所述初始控制端NCX提供的初始控制信号的控制下，控制所述第N级驱动信号输出端NS(N)与所述第一电压端V1之间连通。
图28所示的驱动电路的至少一实施例与图26所示的驱动电路的至少一实施例的区别在于：不包含第二电压维持电路。
可选的，所述第一驱动控制电路包括第十六晶体管、第十七晶体管、第十八晶体管和第十九晶体管；
所述第十六晶体管的栅极与所述反相时钟信号端电连接，所述第十六晶体管的第一极与所述第一电压端电连接，所述第十六晶体管的第二极与所述第十七晶体管的第一极电连接；
所述第十七晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十七晶体管的第二极与所述第四节点电连接；
所述第十八晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十八晶体管的第一极与所述第四节点电连接，所述第十八晶体管的第二极与所述第十九晶体管的第一极电连接；
所述第十九晶体管的栅极与所述控制时钟信号端电连接，所述第十九晶体管的第二极与第三电压端电连接；
所述第十六晶体管和所述第十七晶体管为p型晶体管，所述第十八晶体管和所述第十九晶体管为n型晶体管。
可选的，所述第二驱动控制电路包括第二十晶体管、第二十一晶体管、第二十二晶 体管和第二十三晶体管；
所述第二十晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十晶体管的第一极与第一电压端电连接，所述第二十晶体管的第二极与所述第二十一晶体管的第一极电连接；
所述第二十一晶体管的栅极与所述控制时钟信号端电连接，所述第二十一晶体管的第二极与所述第四节点电连接；
所述第二十二晶体管的栅极与所述反相时钟信号端电连接，所述第二十二晶体管的第一极与所述第四节点电连接，所述第二十二晶体管的第二极与所述第二十三晶体管的第一极电连接；
所述第二十三晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十三晶体管的第二极与第三电压端电连接；
所述第二十晶体管和所述第二十一晶体管为p型晶体管，所述第二十二晶体管和所述第二十三晶体管为n型晶体管。
可选的，所述第二反相电路包括第二十四晶体管和第二十五晶体管；所述第二初始化电路包括第二十六晶体管；
所述第二十四晶体管的栅极与所述第四节点电连接，所述第二十四晶体管的第一极与所述第一电压端电连接，所述第二十四晶体管的第二极与所述第二十五晶体管的第一极和所述第N级驱动信号输出端电连接；
所述第二十五晶体管的栅极与所述第四节点电连接，所述第二十五晶体管的第二极与第三电压端电连接；
所述第二十四晶体管为p型晶体管，所述第二十五晶体管为n型晶体管；
所述第二十六晶体管的栅极与所述初始控制端电连接，所述第二十六晶体管的第一极与所述第一电压端电连接，所述第二十六晶体管的第二极与所述第N级驱动信号输出端电连接。
可选的，所述第一反相电路包括第二十七晶体管和第二十八晶体管；
所述第二十七晶体管的栅极与所述控制时钟信号端电连接，所述第二十七晶体管的第一极与第一电压端电连接，所述第二十七晶体管的第二极与所述第二十八晶体管的第一极和所述反相时钟信号端电连接；
所述第二十八晶体管的栅极与所述控制时钟信号端电连接，所述第二十八晶体管的第二极与第三电压端电连接。
如图29所示，在图28所示的驱动电路的至少一实施例的基础上，
所述选通控制端包括第一控制端、第二控制端、第三控制端和第四控制端，所述选通电路包括第一选通晶体管TX1、第二选通晶体管TX2、第三选通晶体管TX3和第四选通晶体管TX4；
所述第一选通晶体管TX1的栅极与所述第一控制端电连接，所述第一选通晶体管TX1 的漏极与所述选通输入端VCT电连接；
所述第二选通晶体管TX2的栅极与所述第二控制端电连接，所述第二选通晶体管TX2的漏极与所述选通输入端VCT电连接；
所述第三选通晶体管TX3的栅极与所述第三控制端电连接，所述第三选通晶体管TX3的漏极与所述第一选通晶体管TX1的源极电连接，所述第三选通晶体管TX3的源极与所述第一节点N1电连接；
所述第四选通晶体管TX4的栅极与所述第四控制端电连接，所述第四选通晶体管TX4的漏极与所述第二选通晶体管TX2的源极电连接，所述第四选通晶体管TX4的源极与所述第一节点N1电连接；
所述第一选通晶体管TX1为p型晶体管，所述第二选通晶体管TX2为n型晶体管，所述第三选通晶体管TX3为p型晶体管，所述第四选通晶体管TX4为n型晶体管；
所述第一控制端接入第N-1级驱动信号的反相信号NSI(N-1)，所述第二控制端为第N-1级驱动信号输出端NS(N-1)，所述第三控制端为第N级驱动信号输出端NS(N)，所述第四控制端接入第N级驱动信号的反相信号NSI(N)；
所述复位电路包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第一晶体管T1的漏极与高电压端VGHN电连接，所述第一晶体管T1的源极与所述第二晶体管T2的漏极电连接；
所述第二晶体管T2的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第二晶体管T2的源极与所述第一节点N1电连接；
T1和T2为p型晶体管；
所述第一初始化电路包括第九晶体管T9；
所述第九晶体管T9的栅极与所述初始控制端NCX电连接，所述第九晶体管T9的漏极与所述高电压端VGHN电连接，所述第九晶体管T9的源极与所述第一节点N1电连接；
T9为p型晶体管；
所述第一电压维持电路包括电容C0；
所述电容C0的第一端与所述第一节点N1电连接，所述电容C0的第二端与第一低电压端VGL电连接；
所述输出控制电路包括第十晶体管T10、第十一晶体管T11、第十二晶体管T12和第十三晶体管T13；
所述第十晶体管T10的栅极与所述第一节点N1电连接，所述第十晶体管T10的漏极与所述高电压端VGHN电连接，所述第十晶体管T10的源极与第二节点N2电连接；
所述第十一晶体管T11的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第十一晶体管T11的漏极与所述高电压端VGHN电连接，所述第十一晶体管T11的源极所述第二节点N2电连接；
所述第十二晶体管T12的栅极与所述第一节点N1电连接，所述第十二晶体管T12的漏极与所述第二节点N2电连接，所述第十二晶体管T12的源极与所述第十三晶体管T13的漏极电连接；
所述第十三晶体管T13的栅极与所述N级驱动信号输出端NS(N)电连接，所述第十三晶体管T13的源极与第一低电压端VGL电连接；
所述第十晶体管T10和所述第十一晶体管T11为p型晶体管，所述第十二晶体管T12和所述第十三晶体管T13为n型晶体管；
所述输出电路包括第十四晶体管T14和第十五晶体管T15；
所述第十四晶体管T14的栅极与第二节点N2电连接，所述第十四晶体管T14的漏极与高电压端VGHN电连接，所述第十四晶体管T14的源极与输出驱动端NO(N)电连接；
所述第十五晶体管T15的栅极与所述第二节点N2电连接，所述第十五晶体管T15的漏极与所述输出驱动端NO(N)电连接，所述第十五晶体管T15的源极与第一低电压端VGL电连接；
T14为p型晶体管，T15为p型晶体管；
所述第一驱动控制电路包括第十六晶体管T16、第十七晶体管T17、第十八晶体管T18和第十九晶体管T19；
所述第十六晶体管T16的栅极与所述反相时钟信号端NCKI电连接，所述第十六晶体管T16的漏极与所述高电压端VGHN电连接，所述第十六晶体管T16的源极与所述第十七晶体管T17的漏极电连接；
所述第十七晶体管T17的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第十七晶体管T17的源极与所述第四节点N4电连接；
所述第十八晶体管T18的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第十八晶体管T18的漏极与所述第四节点N4电连接，所述第十八晶体管T18的源极与所述第十九晶体管T19的漏极电连接；
所述第十九晶体管T19的栅极与所述控制时钟信号端NCK电连接，所述第十九晶体管T19的源极与第二低电压端VGLN电连接；
所述第十六晶体管T16和所述第十七晶体管T17为p型晶体管，所述第十八晶体管T18和所述第十九晶体管T19为n型晶体管；
所述第二驱动控制电路包括第二十晶体管T20、第二十一晶体管T21、第二十二晶体管T22和第二十三晶体管T23；
所述第二十晶体管T20的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第二十晶体管T20的漏极与高电压端VGHN电连接，所述第二十晶体管T20的源极与所述第二十一晶体管T21的漏极电连接；
所述第二十一晶体管T21的栅极与所述控制时钟信号端NCK电连接，所述第二十一晶体管T21的源极与所述第四节点N4电连接；
所述第二十二晶体管T22的栅极与所述反相时钟信号端NCKI电连接，所述第二十二晶体管T22的漏极与所述第四节点N4电连接，所述第二十二晶体管T22的源极与所述第二十三晶体管T23的漏极电连接；
所述第二十三晶体管T23的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第二十三晶体管T23的源极与第二低电压端VGLN电连接；
所述第二十晶体管T20和所述第二十一晶体管T21为p型晶体管，所述第二十二晶体管T22和所述第二十三晶体管T23为n型晶体管；
所述第二反相电路包括第二十四晶体管T24和第二十五晶体管T25；所述第二初始化电路包括第二十六晶体管T26；
所述第二十四晶体管T24的栅极与所述第四节点N4电连接，所述第二十四晶体管T24的漏极与所述高电压端VGHN电连接，所述第二十四晶体管T24的源极与所述第二十五晶体管T25的漏极和所述第N级驱动信号输出端NS(N)电连接；
所述第二十五晶体管T25的栅极与所述第四节点N4电连接，所述第二十五晶体管T25的源极与第二低电压端VGLN电连接；
所述第二十四晶体管T24为p型晶体管，所述第二十五晶体管T25为n型晶体管；
所述第二十六晶体管T26的栅极与所述初始控制端NCX电连接，所述第二十六晶体管T26的漏极与所述高电压端VGHN电连接，所述第二十六晶体管T26的源极与所述第N级驱动信号输出端NS(N)电连接；
所述第二十六晶体管T26为p型晶体管；
所述第一反相电路包括第二十七晶体管T27和第二十八晶体管T28；
所述第二十七晶体管T27的栅极与所述控制时钟信号端NCK电连接，所述第二十七晶体管T27的漏极与所述高电压端VGHN电连接，所述第二十七晶体管T27的源极与所述第二十八晶体管T28的漏极和反相时钟信号端NCKI电连接；
所述第二十八晶体管T28的栅极与所述控制时钟信号端NCK电连接，所述第二十八晶体管T28的源极与第二低电压端VGLN电连接；
所述第二十七晶体管T27为p型晶体管，所述第二十八晶体管T28为n型晶体管。
在图29所示的驱动电路的至少一实施例中，VGLN提供的第二低电压信号的电压值可以小于VGL提供的第一低电压信号的电压值，以使得当所述N级驱动信号输出端NS(N)输出低电压信号，并第一节点N1的电位为低电压时，T12和T13能够很好的关断。
在图29所示的驱动电路的至少一实施例中，第一电压端为高电压端VGHN，第二电压端为第一低电压端VGL，第三电压端为第二低电压端VGLN。
本公开图29所述的驱动电路的至少一实施例在工作时，
1、当GCK提供高电压信号时，T19打开，T20关闭，GCB提供低电压信号，T16打开，T23关闭，此时驱动信号生成电路处于传输状态；
当NS(N)提供低电压信号时，打开T17，关闭T18，N6的电位为高电压，打开T25， 关闭T24，NS(N)提供低电压信号，NS(N-1)提供低电压信号；
当NS(N)提供高电压信号时，关闭T17，打开T18，N6的电位为低电压，关闭T25，打开T24，NS(N)和NS(N-1)都提供高电压信号；
2、当GCK提供低电压信号时，关闭T19，打开T20，GCB提供高电压信号，关闭T16，打开T23，此时电路处于寄存状态，T21、T22、T23和T11组成锁存电路，N6的电位与NS(N)提供的信号维持之前状态不变；
3、当NS(N-1)提供的信号由低电压信号切换为高电压信号时，GCK提供低电压信号，关闭T19，打开T20，GCB提供高电压信号，关闭T16，打开T23，此时电路处于寄存状态，T21、T22、T23和T11组成锁存电路，N6的电位与NS(N)提供的信号维持之前的低电压状态不变，完成移位。在下一个时刻，GCK提供高电压信号，打开T19，关闭T20，GCB提供低电压信号，打开T16，关闭T23，此时电路处于传输状态，NS(N-1)提供高电压信号，关闭T17，打开T18，N6的电位为低电压，关闭T25，打开T24，NS(N)和NS(N-1)都提供高电压信号，实现NS(N-1)向NS(N)的移位寄存；
4、当NS(N-1)从提供高电压信号切换为提供低电压信号时，GCK提供低电压信号，关闭T19，打开T20，GCB提供高电压信号，关闭T16，打开T23，此时电路处于寄存状态，T21、T22、T23和T11组成锁存电路，N6的电位和NS(N)提供的信号维持为之前的高电压状态不变，完成移位；在下一个时刻，GCK提供高电压信号，打开T19，关闭T20，GCB提供低电压信号，打开T16，关闭T23，此时电路处于传输状态，NS(N-1)提供低电压信号，打开T17，关闭T18，N6的电位为高电压，打开T25，关闭T24，NS(N)和NS(N-1)都提供低电压信号，实现NS(N-1)向NS(N)的移位寄存。
本公开图29所示的驱动电路的至少一实施例在工作时，
当NS(N-1)提供高电压信号时，打开TX1和TX2，NS(N)提供低电压信号时，打开TX3和TX4，通过两个信号同时选通，可以获取一个高低频切换周期H内的VCT提供的选通输入信号的状态，并写入第一节点N1，然后TX1、TX2、TX3和TX4在其他时间不会同时打开，防止N1的电位被VCT提供的选通输入信号的电位变化影响。T10、T11、T12和T13组成一个与非门，该与非门的输入信号分别为NS(N)提供的信号、N1的电位，该与非门的输出端与第二节点N2电连接。T24和T25组成第二反相电路，所述第二反相电路的输入端与第四节点N4电连接，第二反相电路的输出端与NS(N)电连接；
如果VCT在TX1、TX2、TX3和TX4打开时提供高电压信号时，N1会被写入高电压，该与非门的选通状态可以保证NS(N)正常传递给NO(N)；
如果VCT在TX1、TX2、TX3和TX4打开时提供低电压信号时，N1会被写入低电压，该与非门处于截止状态，保证NO(N)提供低电压信号，从而实现NO(N)的低电平维持。
可选的，在开始显示时(也即在显示装置开机时)，在第一阶段之前的开机阶段，NCX输出低电压信号，T9打开，以控制N1的电位为高电压，T26打开，以使得NS(N)提供 高电压信号；此时，T12和T13都打开，N2的电位为低电压，T14导通，T15关断，NO(N)输出高电压信号，可以将有效显示区域中的所有像素电路包括的第二显示控制晶体管M2都打开，清空存储电容Cst中残留的电荷，改善开机屏闪不良；
之后，当NS(N-1)输出高电压信号，NS(N)输出低电压信号时，TX1、TX2、TX3和TX4打开，
当VCT提供低电压信号时，N1的电位为低电压信号，C0维持N1的电位；T11导通，T10导通，N2的电位为高电压，T15打开，NO(N)输出低电压信号；
当VCT提供高电压信号时，N1的电位为高电压信号，C0维持N1的电位，T11关断，T10导通，N2的电位为高电压，T15打开，NO(N)输出低电压信号；
之后，在第N级驱动信号提供阶段，NS(N)输出高电压信号，
当N1的电位为低电压时，T10关断，T11打开，N2的电位为高电压，T15打开，NO(N)输出低电压信号；
当N1的电位为高电压时，T10关断，T11关断，T12和T13导通，N2的电位为低电压，T14打开，NO(N)输出高电压信号；
在第N级驱动信号提供阶段之后，NS(N)输出低电压信号，
当N1的电位为低电压信号时，T10导通，T11导通，N2的电位为高电压，NO(N)输出低电压信号；
当N1的电位为高电压信号时，T10导通，T11关断，N2的电位为高电压，NO(N)输出低电压信号。
本公开图29所示的驱动电路的至少一实施例在工作时，当NS(N-1)输出高电压信号，NS(N)输出低电压信号时，TX1、TX2、TX3和TX4打开，通过以上两个信号同时选通，可以获取一个高低频切换周期内的选通输入信号状态。
如图30所示，在图27所示的驱动电路的至少一实施例的基础上，
所述第一选通电路包括第一个第一选通晶体管TX11、第一个第二选通晶体管TX12、第一个第三选通晶体管TX13和第一个第四选通晶体管TX14；
所述第二选通电路包括第二个第一选通晶体管TX21、第二个第二选通晶体管TX22、第二个第三选通晶体管TX23和第二个第四选通晶体管TX24；
所述第一个第一选通晶体管TX11的栅极接入第N-1级驱动信号的反相信号NSI(N-1)，所述第一个第一选通晶体管TX11的漏极与所述第一选通输入端VCT1电连接；
所述第一个第二选通晶体管TX12的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第一个第二选通晶体管TX12的漏极与所述第一选通输入端VCT1电连接；
所述第一个第三选通晶体管TX13的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第一个第三选通晶体管TX13的漏极与所述第一个第一选通晶体管TX11的源极电连接，所述第一个第三选通晶体管TX13的源极与所述第一个第一节点N11电连接；
所述第一个第四选通晶体管TX14的栅极接入第N级驱动信号的反相信号NSI(N)， 所述第一个第四选通晶体管TX14的漏极与所述第一个第二选通晶体管TX12的源极电连接，所述第一个第四选通晶体管TX14的源极与所述第一个第一节点N11电连接；
所述第一个第一选通晶体管TX11为p型晶体管，所述第一个第二选通晶体管TX12为n型晶体管，所述第一个第三选通晶体管TX13为p型晶体管，所述第一个第四选通晶体管TX14为n型晶体管；
所述第二个第一选通晶体管TX21的栅极接入第N-1级驱动信号的反相信号NSI(N-1)，所述第二个第一选通晶体管TX21的漏极与所述第二选通输入端VCT2电连接；
所述第二个第二选通晶体管TX22的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第二个第二选通晶体管TX22的漏极与所述第二选通输入端VCT2电连接；
所述第二个第三选通晶体管TX23的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第二个第三选通晶体管TX23的漏极与所述第二个第一选通晶体管TX21的源极电连接，所述第二个第三选通晶体管TX23的源极与所述第二个第一节点N21电连接；
所述第二个第四选通晶体管TX24的栅极接入第N级驱动信号的反相信号NSI(N)，所述第二个第四选通晶体管TX24的漏极与所述第二个第二选通晶体管TX22的源极电连接，所述第二个第四选通晶体管TX24的源极与所述第二个第一节点N21电连接；
所述第二个第一选通晶体管TX21为p型晶体管，所述第二个第二选通晶体管TX22为n型晶体管，所述第二个第三选通晶体管TX23为p型晶体管，所述第二个第四选通晶体管TX24为n型晶体管；
所述第一复位电路包括第一个第一晶体管T011和第一个第二晶体管T012；
所述第一个第一晶体管T011的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第一个第一晶体管T011的漏极与高电压端VGHN电连接，所述第一个第一晶体管T011的源极与所述第一个第二晶体管T012的漏极电连接；
所述第一个第二晶体管T012的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第一个第二晶体管T012的源极与所述第一个第一节点N11电连接；
T011和T012为p型晶体管；
所述第二复位电路包括第二个第一晶体管T021和第二个第二晶体管T022；
所述第二个第一晶体管T021的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第二个第一晶体管T021的漏极与高电压端VGHN电连接，所述第二个第一晶体管T021的源极与所述第二个第二晶体管T022的漏极电连接；
所述第二个第二晶体管T022的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第二个第二晶体管T022的源极与所述第二个第一节点N21电连接；
T021和T022为p型晶体管；
所述第一个第一初始化电路包括第一个第九晶体管T019；
所述第一个第九晶体管T019的栅极与所述初始控制端NCX电连接，所述第一个第九晶体管T019的漏极与所述高电压端VGHN电连接，所述第一个第九晶体管T019的源极 与所述第一个第一节点N11电连接；
T019为p型晶体管；
所述第一个第一电压维持电路包括第一电容C1；所述第二个第一电压维持电路包括第二电容C2；
所述第一电容C1的第一端与所述第一个第一节点N11电连接，所述第一电容C1的第二端与第一低电压端VGL电连接；
所述第二电容C2的第一端与所述第二个第一节点N21电连接，所述第二电容C2的第二端与第一低电压端VGL电连接；
所述第一输出控制电路包括第一个第十晶体管T110、第一个第十一晶体管T111、第一第十二晶体管T112和第一个第十三晶体管T113；
所述第一个第十晶体管T110的栅极与所述第一个第一节点N11电连接，所述第一个第十晶体管T110的漏极与所述高电压端VGHN电连接，所述第一个第十晶体管T110的源极与第一个第二节点N12电连接；
所述第一个第十一晶体管T111的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第一个第十一晶体管T111的漏极与所述高电压端VGHN电连接，所述第一个第十一晶体管T111的源极所述第一个第二节点N12电连接；
所述第一个第十二晶体管T112的栅极与所述第一个第一节点N11电连接，所述第一个第十二晶体管T112的漏极与所述第一个第二节点N12电连接，所述第一个第十二晶体管T112的源极与所述第一个第十三晶体管T113的漏极电连接；
所述第一个第十三晶体管T113的栅极与所述N级驱动信号输出端NS(N)电连接，所述第一个第十三晶体管T113的源极与第一低电压端VGL电连接；
所述第一个第十晶体管T110和所述第一个第十一晶体管T111为p型晶体管，所述第一个第十二晶体管T112和所述第一个第十三晶体管T113为n型晶体管；
所述第一输出电路包括第一个第十四晶体管T114和第一个第十五晶体管T115；
所述第一个第十四晶体管T114的栅极与第一个第二节点N12电连接，所述第一个第十四晶体管T114的漏极与高电压端VGHN电连接，所述第一个第十四晶体管T114的源极与第一输出驱动端NO1(N)电连接；
所述第一个第十五晶体管T115的栅极与所述第一个第二节点N12电连接，所述第一个第十五晶体管T115的漏极与所述第一输出驱动端NO1(N)电连接，所述第一个第十五晶体管T115的源极与第一低电压端VGL电连接；
T114为p型晶体管，T115为p型晶体管；
所述第一个第一初始化电路包括第一个第九晶体管T019；
所述第一个第九晶体管T019的栅极与所述初始控制端NCX电连接，所述第一个第九晶体管T019的漏极与所述高电压端VGHN电连接，所述第一个第九晶体管T019的源极与所述第一个第一节点N11电连接；
T019为p型晶体管；
所述第二个第一初始化电路包括第二个第九晶体管T029；
所述第二个第九晶体管T029的栅极与所述初始控制端NCX电连接，所述第二个第九晶体管T029的漏极与所述高电压端VGHN电连接，所述第二个第九晶体管T029的源极与所述第二个第一节点N21电连接；
T029为p型晶体管；
所述第一个第一电压维持电路包括第一电容C1；所述第二个第一电压维持电路包括第二电容C2；
所述第一电容C1的第一端与所述第一个第一节点N11电连接，所述第一电容C1的第二端与第一低电压端VGL电连接；
所述第二电容C2的第一端与所述第二个第一节点N21电连接，所述第二电容C2的第二端与第一低电压端VGL电连接；
所述第一输出控制电路包括第一个第十晶体管T110、第一个第十一晶体管T111、第一个第十二晶体管T112和第一个第十三晶体管T113；
所述第一个第十晶体管T110的栅极与所述第一个第一节点N11电连接，所述第一个第十晶体管T110的漏极与所述高电压端VGHN电连接，所述第一个第十晶体管T110的源极与第一个第二节点N12电连接；
所述第一个第十一晶体管T111的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第一个第十一晶体管T111的漏极与所述高电压端VGHN电连接，所述第一个第十一晶体管T111的源极所述第一个第二节点N12电连接；
所述第一个第十二晶体管T112的栅极与所述第一个第一节点N11电连接，所述第一个第十二晶体管T112的漏极与所述第一个第二节点N12电连接，所述第一个第十二晶体管T112的源极与所述第一个第十三晶体管T113的漏极电连接；
所述第一个第十三晶体管T113的栅极与所述N级驱动信号输出端NS(N)电连接，所述第一个第十三晶体管T113的源极与第一低电压端VGL电连接；
所述第一个第十晶体管T110和所述第一个第十一晶体管T111为p型晶体管，所述第一个第十二晶体管T112和所述第一个第十三晶体管T113为n型晶体管；
所述第一输出电路包括第一个第十四晶体管T114和第一个第十五晶体管T115；
所述第一个第十四晶体管T114的栅极与第一个第二节点N12电连接，所述第一个第十四晶体管T114的漏极与高电压端VGHN电连接，所述第一个第十四晶体管T114的源极与第一输出驱动端NO1(N)电连接；
所述第一个第十五晶体管T115的栅极与所述第一个第二节点N12电连接，所述第一个第十五晶体管T115的漏极与所述第一输出驱动端NO1(N)电连接，所述第一个第十五晶体管T115的源极与第一低电压端VGL电连接；
T114为p型晶体管，T115为p型晶体管；
所述第二输出控制电路包括第二个第十晶体管T210、第二个第十一晶体管T211、第二个第十二晶体管T112和第二个第十三晶体管T213；
所述第二个第十晶体管T210的栅极与所述第二个第一节点N21电连接，所述第二个第十晶体管T210的漏极与所述高电压端VGHN电连接，所述第二个第十晶体管T110的源极与第二个第二节点N22电连接；
所述第二个第十一晶体管T211的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第二个第十一晶体管T211的漏极与所述高电压端VGHN电连接，所述第二个第十一晶体管T211的源极所述第二个第二节点N22电连接；
所述第二个第十二晶体管T212的栅极与所述第二个第一节点N21电连接，所述第二个第十二晶体管T212的漏极与所述第二个第二节点N22电连接，所述第二个第十二晶体管T212的源极与所述第二个第十三晶体管T213的漏极电连接；
所述第二个第十三晶体管T213的栅极与所述N级驱动信号输出端NS(N)电连接，所述第二个第十三晶体管T213的源极与第一低电压端VGL电连接；
所述第二个第十晶体管T210和所述第二个第十一晶体管T211为p型晶体管，所述第二个第十二晶体管T212和所述第二个第十三晶体管T213为n型晶体管；
所述第二输出电路包括第二个第十四晶体管T214和第二个第十五晶体管T215；
所述第二个第十四晶体管T214的栅极与第二个第二节点N22电连接，所述第二个第十四晶体管T214的漏极与高电压端VGHN电连接，所述第二个第十四晶体管T214的源极与第二输出驱动端NO2(N)电连接；
所述第二个第十五晶体管T215的栅极与所述第二个第二节点N22电连接，所述第二个第十五晶体管T215的漏极与所述第二输出驱动端NO2(N)电连接，所述第二个第十五晶体管T215的源极与第一低电压端VGL电连接；
T114为p型晶体管，T115为p型晶体管；
所述第一驱动控制电路包括第十六晶体管T16、第十七晶体管T17、第十八晶体管T18和第十九晶体管T19；
所述第十六晶体管T16的栅极与所述反相时钟信号端NCKI电连接，所述第十六晶体管T16的漏极与所述高电压端VGHN电连接，所述第十六晶体管T16的源极与所述第十七晶体管T17的漏极电连接；
所述第十七晶体管T17的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第十七晶体管T17的源极与所述第四节点N4电连接；
所述第十八晶体管T18的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第十八晶体管T18的漏极与所述第四节点N4电连接，所述第十八晶体管T18的源极与所述第十九晶体管T19的漏极电连接；
所述第十九晶体管T19的栅极与所述控制时钟信号端NCK电连接，所述第十九晶体管T19的源极与第二低电压端LVGL电连接；
所述第十六晶体管T16和所述第十七晶体管T17为p型晶体管，所述第十八晶体管T18和所述第十九晶体管T19为n型晶体管；
所述第二驱动控制电路包括第二十晶体管T20、第二十一晶体管T21、第二十二晶体管T22和第二十三晶体管T23；
所述第二十晶体管T20的栅极与所述控制时钟信号端NCK电连接，所述第二十晶体管T20的漏极与高电压端VGHN电连接，所述第二十晶体管T20的源极与所述第二十一晶体管T21的漏极电连接；
所述第二十一晶体管T21的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第二十一晶体管T21的源极与所述第四节点N4电连接；
所述第二十二晶体管T22的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第二十二晶体管T22的漏极与所述第四节点N4电连接，所述第二十二晶体管T22的源极与所述第二十三晶体管T23的漏极电连接；
所述第二十三晶体管T23的栅极与所述反相时钟信号端NCKI电连接，所述第二十三晶体管T23的源极与第二低电压端VGLN电连接；
所述第二十晶体管T20和所述第二十一晶体管T21为p型晶体管，所述第二十二晶体管T22和所述第二十三晶体管T23为n型晶体管；
所述第二反相电路包括第二十四晶体管T24和第二十五晶体管T25；所述第二初始化电路包括第二十六晶体管T26；
所述第二十四晶体管T24的栅极与所述第四节点N4电连接，所述第二十四晶体管T24的漏极与所述高电压端VGHN电连接，所述第二十四晶体管T24的源极与所述第二十五晶体管T25的漏极和所述第N级驱动信号输出端NS(N)电连接；
所述第二十五晶体管T25的栅极与所述第四节点N4电连接，所述第二十五晶体管T25的源极与第二低电压端VGLN电连接；
所述第二十四晶体管T24为p型晶体管，所述第二十五晶体管T25为n型晶体管；
所述第二十六晶体管T26的栅极与所述初始控制端NCX电连接，所述第二十六晶体管T26的漏极与所述高电压端VGHN电连接，所述第二十六晶体管T26的源极与所述第N级驱动信号输出端NS(N)电连接；
所述第二十六晶体管T26为p型晶体管；
所述第一反相电路包括第二十七晶体管T27和第二十八晶体管T28；
所述第二十七晶体管T27的栅极与所述控制时钟信号端NCK电连接，所述第二十七晶体管T27的漏极与所述高电压端VGHN电连接，所述第二十七晶体管T27的源极与所述第二十八晶体管T28的漏极和反相时钟信号端NCKI电连接；
所述第二十八晶体管T28的栅极与所述控制时钟信号端NCK电连接，所述第二十八晶体管T28的源极与第二低电压端VGLN电连接；
所述第二十七晶体管T27为p型晶体管，所述第二十八晶体管T28为n型晶体管。
在图30所示的驱动电路的至少一实施例中，VGLN提供的第二低电压信号的电压值可以小于VGL提供的第一低电压信号的电压值，以使得当所述N级驱动信号输出端NS(N)输出低电压信号，并第一节点N1的电位为低电压时，T12和T13能够很好的关断。
图31是图30所示的驱动电路的至少一实施例的工作时序图。
在图30所示的驱动电路的至少一实施例中，VCT1和VCT2可以独立写入控制信号，实现NO1(N)和NO2(N)的单独输出控制。
在图32中，标号为NO1(1)的为第一级第一输出驱动端，标号为NO1(2)的为第二级第一输出驱动端，标号为NO1(3)的为第三级第一输出驱动端，标号为NO1(4)的为第四级第一输出驱动端，标号为NO1(5)的为第五级第一输出驱动端，标号为NO1(6)的为第六级第一输出驱动端，标号为NO1(7)的为第七级第一输出驱动端，标号为NO1(8)的为第八级第一输出驱动端，标号为NO1(9)的为第九级第一输出驱动端，标号为NO1(10)的为第十级第一输出驱动端，标号为NO1(11)的为第十一级第一输出驱动端，标号为NO1(12)的为第十二级第一输出驱动端；
标号为NO2(1)的为第一级第二输出驱动端，标号为NO2(2)的为第二级第二输出驱动端，标号为NO2(3)的为第三级第二输出驱动端，标号为NO2(4)的为第四级第二输出驱动端，标号为NO2(5)的为第五级第二输出驱动端，标号为NO2(6)的为第六级第二输出驱动端，标号为NO2(7)的为第七级第二输出驱动端，标号为NO2(8)的为第八级第二输出驱动端，标号为NO2(9)的为第九级第二输出驱动端，标号为NO2(10)的为第十级第二输出驱动端，标号为NO2(11)的为第十一级第二输出驱动端，标号为NO2(12)的为第十二级第二输出驱动端。
如图33所示，第二电压维持电路的至少一实施例可以包括维持控制电路、第一反相器和第二反相器；
所述维持控制电路可以包括第三晶体管T3和第四晶体管T4；
所述第三晶体管T3的栅极与第N-1级驱动信号端NS(N-1)电连接，所述第三晶体管T3的漏极与所述第一节点N1电连接，所述第三晶体管T3的源极与第三节点N3电连接；
所述第四晶体管T4的栅极与控制时钟信号端电连接，所述第四晶体管T4的漏极与所述第三节点N3电连接，所述第四晶体管T4的源极与所述第一节点N1电连接；
所述第三晶体管T3为p型晶体管，所述第四晶体管T4为n型晶体管；
所述第一反相器包括第五晶体管T5和第六晶体管T6，所述第二反相器包括第七晶体管T7和第八晶体管T8；
所述第五晶体管T5的栅极与所述第一节点N1电连接，所述第五晶体管T5的漏极与高电压端VGHN电连接，所述第五晶体管T5的源极与第二节点N2电连接；
所述第六晶体管T6的栅极与所述第一节点N1电连接，所述第六晶体管T6的漏极与所述第二节点N2电连接，所述第六晶体管T6的源极与第一低电压端VGL电连接；
所述第五晶体管T5为p型晶体管，所述第六晶体管T6为n型晶体管；
所述第七晶体管T7的栅极与所述第二节点N2电连接，所述第七晶体管T7的漏极与所述高电压端VGHN电连接，所述第七晶体管T7的源极与第三节点N3电连接；
所述第八晶体管T8的栅极与所述第二节点N2电连接，所述第八晶体管T8的漏极与所述第三节点N3电连接，所述第八晶体管T8的源极与第一低电压端VGL电连接；
所述第七晶体管T7为p型晶体管，所述第八晶体管T8为n型晶体管。
在图33所示的第二电压维持电路的至少一实施例中，所述所述第三晶体管T3的栅极可以被替换为与反相时钟信号端NCKI或第一时钟信号端电连接。
在本公开至少一实施例中，由于p型晶体管在传递低电压时有阈值电压损失，n型晶体管在传递高电压时有阈值电压损失，则N1的电位的绝对值会较低，则可以通过第一反相器和第二反相器控制N1的电位的绝对值升高，从而能够更好的控制输出电路中的相应的晶体管导通或关断，维持控制电路控制在各选通晶体管打开时，控制N1与N3之间断开，以不会影响N1的电位的写入。
本公开至少一实施例所述的驱动方法，应用于上述的驱动电路，所述驱动方法包括：
驱动信号生成电路在控制时钟信号的控制下，对第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
第m选通电路在第m选通控制信号的控制下，控制将第m选通输入信号写入第m个第一节点；
第m输出控制电路对所述第N级驱动信号和所述第m输出控制电路的第二端的电位进行与非操作，得到第m个第一输出信号；
第m输出电路用于对所述第m个第一输出信号进行反相，得到并通过第m输出驱动端提供第m输出驱动信号；
M为正整数；m为小于或等于M的正整数，N为正整数。
本公开实施例所述的显示装置包括上述的驱动电路。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (25)

  1. 一种驱动电路，包括驱动信号生成电路、M个输出驱动端和M个控制电路；第m控制电路包括第m选通电路、第m输出控制电路和第m输出电路；M为正整数；m为小于或等于M的正整数；
    所述驱动信号生成电路分别与控制时钟信号端、第N-1级驱动信号输出端和第N级驱动信号输出端电连接，用于在所述控制时钟信号端提供的控制时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
    第m选通电路分别与第m个第一节点、第m选通输入端和第m选通控制端电连接，用于在所述第m选通控制端提供的第m选通控制信号的控制下，控制将所述第m选通输入端提供的第m选通输入信号写入所述第m个第一节点；
    所述第m输出控制电路的第一端与所述第N级驱动信号输出端电连接，所述第m输出控制电路的第二端与所述第m个第一节点电连接，用于对所述第N级驱动信号和所述第m输出控制电路的第二端的电位进行与非操作，得到第m个第一输出信号；
    所述第m输出电路用于对所述第m个第一输出信号进行反相，得到并通过第m输出驱动端提供第m输出驱动信号；
    N为正整数。
  2. 如权利要求1所述的驱动电路，其中，还包括第一反相电路；
    所述第一反相电路分别与所述控制时钟信号端和反相时钟信号端电连接，用于对所述控制时钟信号进行反相，得到反相时钟信号，并通过所述反相时钟信号端输出所述反相时钟信号；
    所述驱动信号生成电路还与所述反相时钟信号端电连接，还用于在所述反相时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号。
  3. 如权利要求1所述的驱动电路，其中，所述第m选通电路用于在第N-1级驱动信号的电位为第一电压，并第N级驱动信号的电位为第二电压时，控制将所述第m选通输入端提供的第m选通输入信号写入所述第m个第一节点。
  4. 如权利要求1所述的驱动电路，其中，所述第m选通控制端包括第m个第一控制端、第m个第二控制端、第m个第三控制端和第m个第四控制端，所述第m选通电路包括第m个第一选通晶体管、第m个第二选通晶体管、第m个第三选通晶体管和第m个第四选通晶体管；
    所述第m个第一选通晶体管的栅极与所述第m个第一控制端电连接，所述第m个第一选通晶体管的第一极与所述第m选通输入端电连接；
    所述第m个第二选通晶体管的栅极与所述第m个第二控制端电连接，所述第m个第 二选通晶体管的第一极与所述第m选通输入端电连接；
    所述第m个第三选通晶体管的栅极与所述第m个第三控制端电连接，所述第m个第三选通晶体管的第一极与所述第m个第一选通晶体管的第二极电连接，所述第m个第三选通晶体管的第二极与所述第m个第一节点电连接；
    所述第m个第四选通晶体管的栅极与所述第m个第四控制端电连接，所述第m个第四选通晶体管的第一极与所述第m个第二选通晶体管的第二极电连接，所述第m个第四选通晶体管的第二极与所述第m个第一节点电连接；
    所述第m个第一选通晶体管为p型晶体管，所述第m个第二选通晶体管为n型晶体管，所述第m个第三选通晶体管为p型晶体管，所述第m个第四选通晶体管为n型晶体管；
    所述第m个第一控制端接入第N-1级驱动信号的反相信号，所述第m个第二控制端为第N-1级驱动信号输出端，所述第m个第三控制端为第N级驱动信号输出端，所述第m个第四控制端接入第N级驱动信号的反相信号；或者，所述第m个第一控制端接入第N级驱动信号的反相信号，所述第m个第二控制端为第N级驱动信号输出端，所述第m个第三控制端为第N-1级驱动信号输出端，所述第m个第四控制端接入第N-1级驱动信号的反相信号。
  5. 如权利要求4所述的驱动电路，其中，所述第m个第一选通晶体管的第二极与所述第m个第二选通晶体管的第二极电连接。
  6. 如权利要求1所述的驱动电路，其中，所述第m选通电路包括第m个第一选通晶体管；
    所述第m个第一选通晶体管的栅极与所述第m选通控制端电连接，所述第m个第一选通晶体管的第一极与所述第m个第一节点电连接，所述第m个第一选通晶体管的第二极与所述第m选通输入端电连接。
  7. 如权利要求1所述的驱动电路，其中，所述第m选通控制端包括第m个第一控制端和第m个第二控制端；所述第m选通电路包括第m个第一选通晶体管和第m个第二选通晶体管；
    所述第m个第一选通晶体管的栅极与第m个第一控制端电连接，所述第m个第一选通晶体管的第一极与所述第m个第一节点电连接，所述第m个第一选通晶体管的第二极与所述第m个第二选通晶体管的第一极电连接；
    所述第m个第二选通晶体管的栅极与第m个第二控制端电连接，所述第m个第二选通晶体管的第二极与所述第m选通输入端电连接；
    所述第m个第一控制端为第N-1级驱动信号输出端，所述第m个第二控制端为第N级驱动信号输出端，第m个第一选通晶体管为n型晶体管，第m个第二选通晶体管为p型晶体管；或者，
    所述第m个第一控制端为第N级驱动信号输出端，所述第m个第二控制端为第N-1 级驱动信号输出端，第m个第一选通晶体管为p型晶体管，第m个第二选通晶体管为n型晶体管；或者，
    所述第m个第一控制端接入第N-1级驱动信号的反相信号，所述第m个第二控制端为第N级驱动信号输出端，所述第m个第一选通晶体管和所述第m个第二选通晶体管都为p型晶体管；或者，
    所述第m个第一控制端为第N级驱动信号输出端，所述第m个第二控制端接入第N-1级驱动信号的反相信号；所述第m个第一选通晶体管和所述第m个第二选通晶体管都为p型晶体管；或者，
    所述第m个第一控制端为第N-1级驱动信号端，所述第m个第二控制端接入第N级驱动信号的反相信号，所述第m个第一选通晶体管和所述第m个第二选通晶体管都为n型晶体管；或者，
    所述第m个第一控制端接入第N级驱动信号的反相信号，所述第m个第二控制端为第N-1级驱动信号端，所述第m个第一选通晶体管和所述第m个第二选通晶体管都为n型晶体管。
  8. 如权利要求1所述的驱动电路，其中，所述第m控制电路还包括第m个第一初始化电路；
    所述第m个第一初始化电路分别与初始控制端、第一电压端和第m个第一节点电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第m个第一节点与所述第一电压端之间连通。
  9. 如权利要求1所述的驱动电路，其中，所述第m控制电路还包括第m复位电路；
    所述第m复位电路分别与第一电压端、第N-1级驱动信号输出端、第N级驱动信号输出端和第m个第一节点电连接，用于在第N级驱动信号和所述第N-1级驱动信号输出端提供的第N-1级驱动信号的控制下，控制所述第m个第一节点与所述第一电压端之间连通。
  10. 如权利要求1所述的驱动电路，其中，所述第m控制电路还包括第m个第一电压维持电路；
    所述第m个第一电压维持电路的第一端与所述第m个第一节点电连接，所述第m个第一电压维持电路的第二端与直流电压端电连接，所述第m电压维持电路用于维持第m个第一节点的电位。
  11. 如权利要求1所述的驱动电路，其中，所述第m控制电路还包括第m个第二电压维持电路；所述第m个第一节点通过所述第m个第二电压维持电路与所述第m输出控制电路的第二端电连接；
    所述第m个第二电压维持电路包括第m个第一反相器、第m个第二反相器和第m维持控制电路；
    所述第m个第一反相器的输入端与所述第m个第一节点电连接，所述第m个第一反 相器的输出端与第m个第二节点电连接，所述第m个第二反相器的输入端与所述第m个第二节点电连接，所述第m个第二反相器的输出端与第m个第三节点和所述第m输出控制电路的第二端电连接；
    所述第m个第一反相器用于对所述第m个第一节点的电位进行反相，并通过第m个第一反相器的输出端输出反相后的第m个第一节点的电位，所述第m个第二反相器用于对其输入端的电位进行反相，并通过所述第m个第二反相器的输出端输出反相后的电位；
    所述第m维持控制电路分别与第m维持控制端、所述第m个第三节点和所述第m个第一节点电连接，用于在所述第m维持控制端提供的第m维持控制信号的控制下，控制所述第m个第三节点与所述第m个第一节点之间连通或断开。
  12. 如权利要求2所述的驱动电路，其中，所述第m复位电路包括第m个第一晶体管和第m个第二晶体管；
    所述第m个第一晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第m个第一晶体管的第一极与第一电压端电连接，所述第m个第一晶体管的第二极与所述第m个第二晶体管的第一极电连接；
    所述第m个第二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第m个第二晶体管的第二极与所述第m个第一节点电连接。
  13. 如权利要求11所述的驱动电路，其中，所述第m维持控制端包括第m个第一维持控制端和第m个第二维持控制端；
    所述第m维持控制电路包括第m个第三晶体管和第m个第四晶体管；
    所述第m个第三晶体管的栅极与所述第m个第一维持控制端电连接，所述第m个第三晶体管的第一极与所述第m个第一节点电连接，所述第m个第三晶体管的第二极与所述第m个第三节点电连接；
    所述第m个第四晶体管的栅极与第m个第二维持控制端电连接，所述第m个第四晶体管的第一极与所述第m个第三节点电连接，所述第m个第四晶体管的第二极与所述第m个第一节点电连接；
    所述第m个第三晶体管为p型晶体管，所述第m个第四晶体管为n型晶体管；
    所述第m个第一维持控制端为第N-1级驱动信号端，所述第m个第二维持控制端为控制时钟信号端；或者，
    所述第m个第一维持控制端为反相时钟信号端，所述第m个第二维持控制端为控制时钟信号端。
  14. 如权利要求11所述的驱动电路，其中，所述第m个第一反相器包括第m个第五晶体管和第m个第六晶体管，所述第m个第二反相器包括第m个第七晶体管和第m个第八晶体管；
    所述第m个第五晶体管的栅极与所述第m个第一节点电连接，所述第m个第五晶体管的第一极与第一电压端电连接，所述第m个第五晶体管的第二极与第m个第二节点电 连接；
    所述第m个第六晶体管的栅极与所述第m个第一节点电连接，所述第m个第六晶体管的第一极与所述第m个第二节点电连接，所述第m个第六晶体管的第二极与第二电压端电连接；
    所述第m个第五晶体管为p型晶体管，所述第m个第六晶体管为n型晶体管；
    所述第m个第七晶体管的栅极与所述第m个第二节点电连接，所述第m个第七晶体管的第一极与所述第一电压端电连接，所述第m个第七晶体管的第二极与第m个第三节点电连接；
    所述第m个第八晶体管的栅极与所述第m个第二节点电连接，所述第m个第八晶体管的第一极与所述第m个第三节点电连接，所述第m个第八晶体管的第二极与第二电压端电连接；
    所述第m个第七晶体管为p型晶体管，所述第m个第八晶体管为n型晶体管。
  15. 如权利要求8所述的驱动电路，其中，所述第m个第一初始化电路包括第m个第九晶体管；
    所述第m个第九晶体管的栅极与所述初始控制端电连接，所述第m个第九晶体管的第一极与所述第一电压端电连接，所述第m个第九晶体管的第二极与所述第m个第一节点电连接。
  16. 如权利要求10所述的驱动电路，其中，所述第m个第一电压维持电路包括第m电容；
    所述第m电容的第一端与所述第m个第一节点电连接，所述第m电容的第二端与直流电压端电连接。
  17. 如权利要求1至16中任一权利要求所述的驱动电路，其中，所述第m输出控制电路包括第m个第十晶体管、第m个第十一晶体管、第m个第十二晶体管和第m个第十三晶体管；
    所述第m个第十晶体管的栅极与所述第m个第一节点电连接，所述第m个第十晶体管的第一极与第一电压端电连接，所述第m个第十晶体管的第二极与第m个第二节点电连接；
    所述第m个第十一晶体管的栅极与所述第N级驱动信号输出端电连接，所述第m个第十一晶体管的第一极与所述第一电压端电连接，所述第m个第十一晶体管的第二极所述第m个第二节点电连接；
    所述第m个第十二晶体管的栅极与所述第m个第一节点电连接，所述第m个第十二晶体管的第一极与所述第m个第二节点电连接，所述第m个第十二晶体管的第二极与所述第m个第十三晶体管的第一极电连接；
    所述第m个第十三晶体管的栅极与所述N级驱动信号输出端电连接，所述第m个第十三晶体管的第二极与第二电压端电连接；
    所述第m个第十晶体管和所述第m个第十一晶体管为p型晶体管，所述第m个第十二晶体管和所述第m个第十三晶体管为n型晶体管。
  18. 如权利要求1至16中任一权利要求所述的驱动电路，其中，所述第m输出电路包括第m个第十四晶体管和第m个第十五晶体管；
    所述第m个第十四晶体管的栅极与第m个第二节点电连接，所述第m个第十四晶体管的第一极与第一电压端电连接，所述第m个第十四晶体管的第二极与第m输出驱动端电连接；
    所述第m个第十五晶体管的栅极与所述第m个第二节点电连接，所述第m个第十五晶体管的第一极与所述第m输出驱动端电连接，所述第m个第十五晶体管的第二极与第二电压端电连接。
  19. 如权利要求2至16中任一权利要求所述的驱动电路，其中，所述驱动信号生成电路包括第一驱动控制电路、第二驱动控制电路、第二反相电路和第二初始化电路；
    所述第一驱动控制电路分别与所述控制时钟信号端、反相时钟信号端、第N-1级驱动信号输出端和第四节点电连接，用于在所述控制时钟信号端提供的控制时钟信号和所述反相时钟信号端提供的反相时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1驱动信号进行移位并反相，得到并通过所述第四节点输出反相后的信号；
    所述第二驱动控制电路分别与所述控制时钟信号端、所述反相时钟信号端、第N级驱动信号输出端和所述第四节点电连接，用于在所述控制时钟信号和所述反相时钟信号的控制下，对所述第N级驱动信号输出端提供的第N级驱动信号进行反相，得到并通过所述第四节点输出反相后的信号；
    所述第二反相电路分别与所述第四节点和所述第N级驱动信号输出端电连接，用于对所述第四节点的电位进行反相，并通过所述第N级驱动信号输出端输出反相后的信号；
    所述第二初始化电路分别与初始控制端、第一电压端和所述第N级驱动信号输出端电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第N级驱动信号输出端与所述第一电压端之间连通。
  20. 如权利要求19所述的驱动电路，其中，所述第一驱动控制电路包括第十六晶体管、第十七晶体管、第十八晶体管和第十九晶体管；
    所述第十六晶体管的栅极与所述反相时钟信号端电连接，所述第十六晶体管的第一极与所述第一电压端电连接，所述第十六晶体管的第二极与所述第十七晶体管的第一极电连接；
    所述第十七晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十七晶体管的第二极与所述第四节点电连接；
    所述第十八晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十八晶体管的第一极与所述第四节点电连接，所述第十八晶体管的第二极与所述第十九晶体管的第一极电连接；
    所述第十九晶体管的栅极与所述控制时钟信号端电连接，所述第十九晶体管的第二极与第三电压端电连接；
    所述第十六晶体管和所述第十七晶体管为p型晶体管，所述第十八晶体管和所述第十九晶体管为n型晶体管。
  21. 如权利要求19所述的驱动电路，其中，所述第二驱动控制电路包括第二十晶体管、第二十一晶体管、第二十二晶体管和第二十三晶体管；
    所述第二十晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十晶体管的第一极与第一电压端电连接，所述第二十晶体管的第二极与所述第二十一晶体管的第一极电连接；
    所述第二十一晶体管的栅极与所述控制时钟信号端电连接，所述第二十一晶体管的第二极与所述第四节点电连接；
    所述第二十二晶体管的栅极与所述反相时钟信号端电连接，所述第二十二晶体管的第一极与所述第四节点电连接，所述第二十二晶体管的第二极与所述第二十三晶体管的第一极电连接；
    所述第二十三晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十三晶体管的第二极与第三电压端电连接；
    所述第二十晶体管和所述第二十一晶体管为p型晶体管，所述第二十二晶体管和所述第二十三晶体管为n型晶体管。
  22. 如权利要求19所述的驱动电路，其中，所述第二反相电路包括第二十四晶体管和第二十五晶体管；所述第二初始化电路包括第二十六晶体管；
    所述第二十四晶体管的栅极与所述第四节点电连接，所述第二十四晶体管的第一极与所述第一电压端电连接，所述第二十四晶体管的第二极与所述第二十五晶体管的第一极和所述第N级驱动信号输出端电连接；
    所述第二十五晶体管的栅极与所述第四节点电连接，所述第二十五晶体管的第二极与第三电压端电连接；
    所述第二十四晶体管为p型晶体管，所述第二十五晶体管为n型晶体管；
    所述第二十六晶体管的栅极与所述初始控制端电连接，所述第二十六晶体管的第一极与所述第一电压端电连接，所述第二十六晶体管的第二极与所述第N级驱动信号输出端电连接。
  23. 如权利要求2所述的驱动电路，其中，
    所述第一反相电路包括第二十七晶体管和第二十八晶体管；
    所述第二十七晶体管的栅极与所述控制时钟信号端电连接，所述第二十七晶体管的第一极与第一电压端电连接，所述第二十七晶体管的第二极与所述第二十八晶体管的第一极和反相时钟信号端电连接；
    所述第二十八晶体管的栅极与所述控制时钟信号端电连接，所述第二十八晶体管的第 二极与第三电压端电连接。
  24. 一种驱动方法，应用于如权利要求1至23中任一权利要求所述的驱动电路，所述驱动方法包括：
    驱动信号生成电路在控制时钟信号的控制下，对第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
    第m选通电路在第m选通控制信号的控制下，控制将第m选通输入信号写入第m个第一节点；
    第m输出控制电路对所述第N级驱动信号和所述第m输出控制电路的第二端的电位进行与非操作，得到第m个第一输出信号；
    第m输出电路用于对所述第m个第一输出信号进行反相，得到并通过第m输出驱动端提供第m输出驱动信号；
    M为正整数；m为小于或等于M的正整数，N为正整数。
  25. 一种显示装置，包括如权利要求1至23中任一权利要求所述的驱动电路。
PCT/CN2024/093524 2023-06-16 2024-05-16 驱动电路、驱动方法和显示装置 Ceased WO2024255519A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104966506A (zh) * 2015-08-06 2015-10-07 京东方科技集团股份有限公司 一种移位寄存器、显示面板的驱动方法及相关装置
CN105144274A (zh) * 2013-04-23 2015-12-09 夏普株式会社 显示装置及其驱动电流检测方法
CN107784977A (zh) * 2017-12-11 2018-03-09 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN111798788A (zh) * 2020-07-13 2020-10-20 昆山国显光电有限公司 发光控制电路、发光控制驱动器和显示面板
CN113192551A (zh) * 2021-04-29 2021-07-30 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
US20230057970A1 (en) * 2020-02-14 2023-02-23 Sharp Kabushiki Kaisha Display device and method for driving same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359511B (zh) * 2007-08-03 2011-04-27 群康科技(深圳)有限公司 移位寄存器和采用该移位寄存器的液晶显示装置
JP2009188749A (ja) * 2008-02-06 2009-08-20 Sony Corp インバータ回路、シフトレジスタ回路、否定論理和回路、否定論理積回路
CN106128378B (zh) * 2016-06-28 2020-01-07 厦门天马微电子有限公司 移位寄存单元、移位寄存器及显示面板
CN109215611B (zh) * 2018-11-16 2021-08-20 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、goa单元电路及显示装置
CN110689839B (zh) * 2019-12-10 2020-04-17 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN112927644B (zh) * 2021-02-02 2022-08-23 合肥维信诺科技有限公司 栅极驱动电路和显示面板
US12272303B2 (en) * 2023-05-23 2025-04-08 Chengdu Boe Optoelectronics Technology Co., Ltd. Driving circuitry, driving method, driving module, and display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105144274A (zh) * 2013-04-23 2015-12-09 夏普株式会社 显示装置及其驱动电流检测方法
CN104966506A (zh) * 2015-08-06 2015-10-07 京东方科技集团股份有限公司 一种移位寄存器、显示面板的驱动方法及相关装置
CN107784977A (zh) * 2017-12-11 2018-03-09 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
US20230057970A1 (en) * 2020-02-14 2023-02-23 Sharp Kabushiki Kaisha Display device and method for driving same
CN111798788A (zh) * 2020-07-13 2020-10-20 昆山国显光电有限公司 发光控制电路、发光控制驱动器和显示面板
CN113192551A (zh) * 2021-04-29 2021-07-30 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置

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