WO2024255218A1 - 肖特基二极管、集成肖特基二极管的ldmosfet及其制造方法 - Google Patents

肖特基二极管、集成肖特基二极管的ldmosfet及其制造方法 Download PDF

Info

Publication number
WO2024255218A1
WO2024255218A1 PCT/CN2024/070570 CN2024070570W WO2024255218A1 WO 2024255218 A1 WO2024255218 A1 WO 2024255218A1 CN 2024070570 W CN2024070570 W CN 2024070570W WO 2024255218 A1 WO2024255218 A1 WO 2024255218A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
schottky diode
conductivity type
silicide layer
cobalt silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/070570
Other languages
English (en)
French (fr)
Inventor
宋亮
安丽琪
李永顺
陈新倩
刘新新
罗琳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab2 Co Ltd
Publication of WO2024255218A1 publication Critical patent/WO2024255218A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular to a Schottky barrier diode, an LDMOSFET (lateral double diffused metal oxide semiconductor field effect transistor) with an integrated Schottky diode, and a method for manufacturing an LDMOSFET with an integrated Schottky diode.
  • a Schottky barrier diode an LDMOSFET (lateral double diffused metal oxide semiconductor field effect transistor) with an integrated Schottky diode
  • LDMOSFET lateral double diffused metal oxide semiconductor field effect transistor
  • Fig. 1 is a circuit diagram of an exemplary LDMOSFET, in which a parasitic diode is formed between the source and drain of the LDMOS.
  • An exemplary NLDMOS can form a diode using the drain region, the drift region and the P-body region (P-Body), but the forward conduction voltage drop of the diode is generally about 0.7V, which limits the further reduction of the forward conduction voltage drop and the conduction loss.
  • a Schottky diode can be integrated inside the LDMOS to obtain lower conduction loss.
  • the exemplary Schottky diode structure uses a planar metal-semiconductor interface, and the metal-semiconductor interface (the contact surface between the metal or metal silicide and the N-type semiconductor material) is surrounded by a P-ring, and the P-ring is led out at an appropriate distance to form a Schottky diode, so it will occupy a larger plane area.
  • a Schottky diode comprises: a well region, having a first conductivity type; a body region, arranged on the upper part of the well region, having a second conductivity type; the body region is penetrated by a trench, and the bottom of the trench extends into the well region; a first cobalt silicide layer, formed on the bottom surface and inner wall of the trench, the first cobalt silicide layer and the well region form a Schottky contact;
  • the well region serves as the cathode of the Schottky diode, the first cobalt silicide layer directly in contact with the well region serves as the anode of the Schottky diode, and the first conductivity type and the second conductivity type are opposite conductivity types.
  • the above-mentioned Schottky diode utilizes the bottom surface and inner wall of the groove to form a Schottky contact with the first cobalt silicide layer and the well region with a U-shaped cross-section.
  • a larger Schottky contact area can be obtained with a smaller plane area, and because the Schottky contact is formed by cobalt silicide, it has a stronger overcurrent capability.
  • the Schottky diode further includes a first doped region located in the body region, the first doped region has a first conductivity type, and a portion of the first cobalt silicide layer is located on a surface of the first doped region.
  • a side surface of the first doped region is disposed close to the top of the trench.
  • the Schottky diode further includes: a second doped region, directly in contact with the well region, and having the first conductivity type.
  • the Schottky diode further includes: a field region insulating layer located between the body region and the second doped region.
  • the Schottky diode further includes: a substrate, and the well region is located in the substrate.
  • the Schottky diode further includes: a second cobalt silicide layer located on a surface of the second doped region, and a cathode of the Schottky diode is led out through the second cobalt silicide layer.
  • the Schottky diode further includes a metal titanium bonding layer located on an upper surface of the first cobalt silicide layer, and a titanium nitride layer located on an upper surface of the metal titanium bonding layer.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • a LDMOSFET with an integrated Schottky diode comprises: a substrate; a drift region, which is arranged in the substrate and has a first conductivity type; a body region, which is arranged in the drift region and has a second conductivity type; the body region is penetrated by a groove, and the bottom of the groove extends into the drift region; a first cobalt silicide layer, which is formed on the bottom surface and inner wall of the groove, and the first cobalt silicide layer forms a Schottky contact with the drift region; a source region, which is located in the body region, the source region has the first conductivity type, and a part of the first cobalt silicide layer is located on the surface of the source region; a drain region, which is in direct contact with the drift region and has the first conductivity type; wherein the drift region serves as the cathode of the Schottky diode, and the first cobalt silicide layer in direct contact with the drift region serves as the anode of the Scho
  • the LDMOSFET with integrated Schottky diode uses the bottom surface and inner wall of the groove to form a Schottky contact with the drift region with a U-shaped cross-section, which can obtain a larger Schottky contact area with a smaller plane area, and because the Schottky contact is formed by cobalt silicide, it has a stronger overcurrent capability.
  • the Schottky diode structure is suitable for LDMOSFETs with Low Side, High Side and full isolation structures, and therefore has wide applicability.
  • a side surface of the first doped region is disposed close to the top of the trench.
  • the LDMOSFET further includes: a field region insulating layer located between the body region and the drain region.
  • the LDMOSFET further includes: a gate, one side of which is close to the source region and the other side of which is close to the drain region, and a portion of the gate is located on the field region insulating layer.
  • the LDMOSFET further includes a second cobalt silicide layer located on the surface of the drain region, and the cathode of the Schottky diode is led out through the second cobalt silicide layer.
  • the LDMOSFET with integrated Schottky diode is a LDMOS with a fully isolated structure
  • the LDMOS with a fully isolated structure also includes: a second conductivity type well region, the drift region is located in the second conductivity type well region; a buried region, located below the second conductivity type well region and between the second conductivity type well region and the substrate, the buried region has a first conductivity type; an isolation region, located outside the second conductivity type well region, part of the substrate is located on the side of the isolation region away from the second conductivity type well region, and the bottom of the isolation region is in direct contact with the buried region.
  • the LDMOSFET further includes a metal titanium bonding layer located on an upper surface of the first cobalt silicide layer, and a titanium nitride layer located on an upper surface of the metal titanium bonding layer.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • a method for manufacturing an LDMOSFET with an integrated Schottky diode comprising: obtaining a substrate; forming a drift region in the substrate, forming a body region in the drift region, the drift region having a first conductivity type, the body region having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; forming a source region and a drain region; the source region is formed in the body region, the drain region is in direct contact with the drift region, the source region and the drain region having the first conductivity type; forming a trench penetrating the body region, the bottom of the trench extending into the drift region;
  • a metal silicide layer is formed by a self-aligned metal silicide process, wherein the metal silicide layer includes a first cobalt silicide layer formed on the bottom surface and inner wall of the trench, and a second cobalt silicide layer formed on the surface of the drain region, wherein the first cobalt silicide layer forms a Schott
  • the manufacturing method of the LDMOSFET with integrated Schottky diode uses the bottom surface and inner wall of the groove to form a Schottky contact with the drift region with a U-shaped cross-section, which can obtain a larger Schottky contact area with a smaller plane area, and because the Schottky contact is formed by the cobalt silicide layer of the self-aligned metal silicide (salicide) process, it has a stronger overcurrent capability.
  • the Schottky diode structure is suitable for LDMOSFETs with Low Side, High Side and full isolation structures, and therefore has a wide range of applicability.
  • the step before the step of forming the source region and the drain region, the step further includes: forming a field region insulating layer between the body region and the drain region.
  • the step of forming the source region and the drain region before the step of forming the source region and the drain region, it also includes: forming a gate, one side of the gate is close to the source region and the other side is close to the drain region, and a part of the gate is formed on the field region insulating layer.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the method further includes the step of forming a metal titanium bonding layer and a titanium nitride layer on the first cobalt silicide layer.
  • FIG1 is a schematic circuit diagram of an exemplary LDMOSFET
  • FIG2 is a circuit diagram of an LDMOSFET with an integrated Schottky diode
  • FIG. 3 is a schematic cross-sectional structure diagram of an LDMOSFET with an integrated Schottky diode in an embodiment of the present application;
  • FIG4 is a schematic diagram of the structure of a fully isolated LDMOSFET with an integrated Schottky diode in one embodiment of the present application;
  • FIG. 5 is a flow chart of a method for manufacturing an LDMOSFET with an integrated Schottky diode in an embodiment of the present application
  • 6a to 6c are schematic cross-sectional views of devices during the process of manufacturing LDMOS using the method shown in FIG. 5 .
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application.
  • variations from the shapes shown due to, for example, manufacturing techniques and/or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing.
  • an implanted region shown as a rectangle typically has rounded or curved features and/or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the present application.
  • the semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field.
  • P+ type represents P-type with heavy doping concentration
  • P-type represents P-type with medium doping concentration
  • P-type represents P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type represents N-type with medium doping concentration
  • N-type represents N-type with light doping concentration
  • FIG3 is a schematic diagram of the cross-sectional structure of an LDMOSFET with an integrated Schottky diode in an embodiment of the present application. Note that the structure shown in FIG3 is a bilaterally symmetrical structure, so only one of the partial structures is marked, and the other symmetrical structure is not marked.
  • the integrated Schottky diode in the embodiment shown in FIG3 includes a well region, a body region 124, and a first cobalt silicide layer 142.
  • the well region is the drift region 122 of the LDMOSFET.
  • the drift region 122 has a first conductivity type.
  • the body region 124 is arranged in the drift region 122 and has a second conductivity type.
  • the body region 124 is penetrated by the groove 131, and the bottom of the groove 131 extends into the drift region 122.
  • the first cobalt silicide layer 142 is formed on the bottom surface and inner wall of the groove 131, and the first cobalt silicide layer 142 forms a Schottky contact with the drift region 122.
  • the drift region 122 serves as the cathode of the Schottky diode
  • the first cobalt silicide layer 142 directly in contact with the drift region 122 serves as the anode of the Schottky diode.
  • the LDMOSFET is NLDMOS
  • the first conductivity type is N type
  • the second conductivity type is P type.
  • the substrate 110 is a P type substrate P-Sub
  • the drift region 122 is an N type drift region N-Drift
  • the body region 124 is a P type body region P-Body.
  • the Schottky diode uses the bottom surface and inner wall of the trench 131 to form a Schottky contact with the first cobalt silicide layer 142 and the drift region 122 with a U-shaped cross-section, and can obtain a larger Schottky contact area with a smaller plane area, so it has a stronger overcurrent capability.
  • the Schottky contact is formed by cobalt silicide, it is also conducive to obtaining a stronger overcurrent capability.
  • the LDMOSFET further includes a substrate 110, a source region 132 (a first doped region) and a drain region 134 (a second doped region).
  • the drift region 122 is located in the substrate 110.
  • the substrate 110 has a second conductivity type.
  • the source region 132 is located in the body region 124, the source region 132 has a first conductivity type, and a portion of the first cobalt silicide layer 142 is located on the surface of the source region 132.
  • one side of the source region 132 is disposed near the top of the trench 131.
  • the drain region 134 is in direct contact with the drift region 122 and has a first conductivity type.
  • the doping concentration of the drain region 134 is greater than the doping concentration of the drift region 122. That is, the source region 132 and the drain region 134 are N+ regions.
  • the structure shown in FIG3 is applicable to the Low Side, High Side and Fully Isolated NLDMOSFET in the half-bridge circuit, and therefore has wide applicability.
  • the source, bulk and substrate of the Low Side NLDMOSFET in the half-bridge circuit have the same potential; the bulk and substrate of the High Side NLDMOSFET in the half-bridge circuit have different potentials; the bulk and substrate of the Fully Isolated structure also have different potentials.
  • the LDMOSFET further includes a field insulating layer 150 and a gate 136.
  • One side of the gate 136 is close to the source region 132, and the other side is close to the drain region 134.
  • a portion of the gate 136 is located on the field insulating layer 150.
  • the field insulating layer 150 is a field oxide layer, and its material is silicon oxide, such as silicon dioxide.
  • the gate 136 is a polysilicon material, and in other embodiments, metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate 136.
  • the Schottky diode further includes a second cobalt silicide layer 144 located on the surface of the drain region 134.
  • the cathode of the Schottky diode is led out through the second cobalt silicide layer 144.
  • the second cobalt silicide layer 144 can reduce the contact resistance of the drain region 134.
  • the Schottky diode further includes a metal titanium bonding layer located on the upper surface of the first cobalt silicide layer 142 , and a titanium nitride layer located on the upper surface of the metal titanium bonding layer.
  • the conduction voltage drop of the Schottky diode can be reduced to about 0.3V, reducing the conduction voltage drop and conduction loss of the body diode between the source region 132 and the drain region 134.
  • FIG4 is a schematic diagram of the structure of a fully isolated LDMOSFET with an integrated Schottky diode in an embodiment of the present application.
  • the LDMOSFET further includes a second conductive type well region 126, a buried region 128 and an isolation region 129.
  • the drift region 122 is located in the second conductive type well region 126.
  • the buried region 128 is located below the second conductive type well region 126 and between the second conductive type well region 126 and the substrate 110.
  • the buried region 128 is a first conductive type buried layer.
  • the isolation region 129 is located outside the second conductive type well region 126, and part of the substrate 110 is located outside the isolation region 129 (i.e., on the side away from the second conductive type well region 126), and the bottom of the isolation region 129 is in direct contact with the buried region 128.
  • the isolation region 129 is a doped region of the first conductive type. The fully isolated LDMOSFET isolates the second conductive type well region 126 from the substrate 110 , so that the second conductive type well region 126 and the substrate 110 have different potentials.
  • FIG5 is a flow chart of a method for manufacturing an LDMOSFET with an integrated Schottky diode in an embodiment of the present application, comprising the following steps:
  • a drift region 122 is formed in a substrate 110, and a body region 124 is formed in the drift region 122.
  • the drift region 122 has a first conductivity type
  • the body region 124 has a second conductivity type.
  • the manufactured LDMOSFET is an NLDMOS
  • the first conductivity type is an N-type
  • the second conductivity type is a P-type.
  • the substrate 110 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc., and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors.
  • the constituent material of the substrate 110 is selected from single crystal silicon.
  • the drift region 122 may be formed by a suitable method, such as a doping process. Doping is generally achieved by ion implantation. If an N-type drift region 122 is prepared, an N-type ion doping is performed on a region of the substrate 110 where the drift region 122 is to be formed, such as by ion implantation after photolithography, to form a The N-type drift region 122.
  • the body region 124 can also be formed using a suitable method, such as a doping process.
  • a region of the drift region 122 where the body region 124 is to be formed is doped with P-type ions, such as by ion implantation after photolithography, to form a P-type body region 124 in the substrate 110.
  • the source region 132 is formed in the body region 124, and the drain region 134 is in direct contact with the drift region 122.
  • the source region 132 and the drain region 134 have a first conductivity type.
  • the step of forming a field insulating layer 150 and the step of forming a gate 136 are further included, see FIG6b.
  • the field insulating layer 150 is a field oxide layer, and its material is silicon oxide, such as silicon dioxide.
  • the field insulating layer 150 can be formed by a process known to those skilled in the art, such as a thermal oxidation process.
  • the gate 136 is made of polysilicon; in other embodiments, metal, metal nitride, metal silicide or similar compounds may be used as the gate material.
  • the gate 136 may be formed by chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), and methods such as sputtering and physical vapor deposition (PVD) may also be used.
  • CVD chemical vapor deposition
  • LTCVD low temperature chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • LTCVD rapid thermal chemical vapor deposition
  • PECVD plasma chemical vapor deposition
  • PVD physical vapor deposition
  • the thickness of the gate 136 may be a suitable thickness according to the size of the device, and no specific limitation is made here.
  • the method for forming the source region 132 and the drain region 134 includes performing source-drain ion implantation on the region where the source and drain are to be formed in the semiconductor substrate.
  • a patterned photoresist layer exposing the region where the source region 132 and the drain region 134 are to be formed can be first formed by a photolithography process, and then the source-drain ion implantation is performed using the patterned photoresist layer as a mask, and finally the patterned photoresist layer is removed by a method such as ashing.
  • an annealing process may be performed.
  • the annealing process may be performed using any annealing method known to those skilled in the art, including but not limited to rapid thermal annealing, furnace annealing, peak annealing, laser annealing, etc.
  • a rapid temperature rise annealing process may be performed to activate the dopants in the source region 132 and the drain region 134 using a high temperature of 900 to 1050° C., and simultaneously repair the lattice structure of the semiconductor substrate surface damaged in each ion implantation process.
  • a lightly doped drain (LDD) may be formed between the source region 132, the drain region 134, and the gate 136, respectively, depending on product requirements and functional considerations.
  • the bottom of the groove 131 extends into the drift region 122.
  • the groove 131 can be formed by photolithography and etching processes.
  • the bottom of the groove 131 should be as close as possible to the bottom of the drift region 122, but must be spaced from the substrate 110 below the drift region 122.
  • the larger the gold semi-interface area of the Schottky diode the stronger the ability to reduce the conduction voltage drop and conduction loss of the body diode between the source/drain.
  • the top of the trench 131 is located at the edge of the source region 132 .
  • the device structure after step S240 is completed can refer to FIG3.
  • the metal silicide layer includes a first cobalt silicide layer 142 formed on the bottom surface and inner wall of the trench 131, and a second cobalt silicide layer 144 formed on the surface of the drain region 134.
  • the first cobalt silicide layer 142 forms a Schottky contact with the well region.
  • the drift region 122 serves as the cathode of the Schottky diode, and the first cobalt silicide layer 142 in contact with the drift region 122 serves as the anode of the Schottky diode.
  • Self-aligned silicide is a simple and convenient contact metallization process. In the process of manufacturing semiconductor devices, some areas require the salicide process, while some areas require the non-salicide process. For devices that require the non-salicide process, the characteristics of the above-mentioned salicide should be used to cover the areas that require non-salicide with materials that will not react with metals. This material used to cover non-salicide devices is called a self-aligned silicide barrier film (SAB).
  • SAB self-aligned silicide barrier film
  • Step S240 can form the first cobalt silicide layer 142 by using the salicide process of the device corresponding to the line width process, such as the salicide process in the standard BCD (Bipolar-CMOS-DMOS) process of 0.18 microns.
  • the Schottky contact uses the standard salicide process to chemically react cobalt and silicon to form cobalt silicide, which is simple and easy to operate and has high process compatibility.
  • a portion of the first cobalt silicide layer 142 formed in step S240 is formed on the surface of the source region 132.
  • the manufacturing method of the LDMOSFET with integrated Schottky diode uses the bottom surface and inner wall of the groove 131 to form a Schottky contact with the drift region 122 with a U-shaped cross-section, so that a larger Schottky contact area can be obtained with a smaller plane area, and because the Schottky contact is formed by the cobalt silicide layer of the self-aligned metal silicide (salicide) process, it has a stronger overcurrent capability.
  • the Schottky diode structure is suitable for LDMOSFETs with Low Side, High Side and full isolation structures, and therefore has a wide range of applicability.
  • step S240 a step of forming a metal titanium bonding layer and a titanium nitride layer on the first cobalt silicide layer 142 to form an ohmic contact is further included.

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本申请涉及一种肖特基二极管，包括：阱区，具有第一导电类型；体区(124)，设于所述阱区的上部，具有第二导电类型；所述体区(124)被沟槽(131)贯穿，所述沟槽(131)的底部延伸至所述阱区中；第一钴硅化物层(142)，形成于所述沟槽(131)的底面和内壁，所述第一钴硅化物层(142)与所述阱区形成肖特基接触；其中，所述阱区作为所述肖特基二极管的阴极，与所述阱区直接接触的所述第一钴硅化物层(142)作为所述肖特基二极管的阳极，所述第一导电类型和第二导电类型为相反的导电类型。本申请利用沟槽的底面和内壁，使第一钴硅化物层与阱区形成U型的结构的肖特基接触，可以凭借较小的平面面积获得较大的肖特基接触面积，并且由于肖特基接触为钴硅化物所形成，因此有较强的过电流能力。

Description

肖特基二极管、集成肖特基二极管的LDMOSFET及其制造方法
本申请要求于2023年6月15日提交中国专利局，申请号为2023107156486，申请名称为“肖特基二极管、集成肖特基二极管的LDMOSFET及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造领域，特别是涉及一种肖特基二极管(Schottky Barrier Diode)，还涉及一种集成肖特基二极管的LDMOSFET(横向双扩散金属氧化物半导体场效应管)，以及一种集成肖特基二极管的LDMOSFET的制造方法。
背景技术
图1是一示例性的LDMOSFET的电路原理图，在LDMOS的源极和漏极之间形成有寄生的二极管。示例性的NLDMOS可以利用漏极区、漂移区及P型体区(P-Body)形成二极管，但该二极管的正向导通压降通常为0.7V左右，限制了正向导通压降以及导通损耗的进一步降低。
参见图2，可以通过在LDMOS内部集成一肖特基二极管来获得更低的导通损耗。示例性的肖特基二极管结构采用平面型的金属半导体界面，金半界面(金属或金属硅化物与N型半导体材料之间的接触面)周围以P-ring围绕，P-ring取适当的距离引出形成肖特基二极管，所以会占用较大的平面面积。
发明内容
基于此，有必要提供一种平面面积较小的肖特基二极管。
一种肖特基二极管，包括：阱区，具有第一导电类型；体区，设于所述阱区的上部，具有第二导电类型；所述体区被沟槽贯穿，所述沟槽的底部延伸至所述阱区中；第一钴硅化物层，形成于所述沟槽的底面和内壁，所述第一钴硅化物层与所述阱区形成肖特基接触； 其中，所述阱区作为所述肖特基二极管的阴极，与所述阱区直接接触的所述第一钴硅化物层作为所述肖特基二极管的阳极，所述第一导电类型和第二导电类型为相反的导电类型。
上述肖特基二极管，利用沟槽的底面和内壁，使第一钴硅化物层与阱区形成剖面为U型的结构的肖特基接触，可以凭借较小的平面面积获得较大的肖特基接触面积，并且由于肖特基接触为钴硅化物所形成，因此有较强的过电流能力。
在其中一个实施例中，所述肖特基二极管还包括位于所述体区中的第一掺杂区，所述第一掺杂区具有第一导电类型，一部分所述第一钴硅化物层位于所述第一掺杂区的表面。
在其中一个实施例中，所述第一掺杂区的一侧面靠近所述沟槽的顶部设置。
在其中一个实施例中，所述肖特基二极管还包括：第二掺杂区，与所述阱区直接接触，具有第一导电类型。
在其中一个实施例中，所述肖特基二极管还包括：场区绝缘层，位于所述体区与所述第二掺杂区之间。
在其中一个实施例中，所述肖特基二极管还包括：衬底，所述阱区位于所述衬底中。
在其中一个实施例中，所述肖特基二极管还包括：第二钴硅化物层，位于所述第二掺杂区的表面，所述肖特基二极管的阴极通过所述第二钴硅化物层引出。
在其中一个实施例中，所述肖特基二极管还包括位于所述第一钴硅化物层的上表面的金属钛粘结层，以及位于所述金属钛粘结层的上表面的氮化钛层。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型。
还有必要提供一种集成肖特基二极管的LDMOSFET。
一种集成肖特基二极管的LDMOSFET，包括：衬底；漂移区，设于所述衬底中，具有第一导电类型；体区，设于所述漂移区中，具有第二导电类型；所述体区被沟槽贯穿，所述沟槽的底部延伸至所述漂移区中；第一钴硅化物层，形成于所述沟槽的底面和内壁，所述第一钴硅化物层与所述漂移区形成肖特基接触；源极区，位于所述体区中，所述源极区具有第一导电类型，一部分所述第一钴硅化物层位于所述源极区的表面；漏极区，与所述漂移区直接接触，具有第一导电类型；其中，所述漂移区作为所述肖特基二极管的阴极，与所述漂移区直接接触的所述第一钴硅化物层作为所述肖特基二极管的阳极，所述第一导电类型和第二导电类型为相反的导电类型。
上述集成肖特基二极管的LDMOSFET，利用沟槽的底面和内壁，使第一钴硅化物层与漂移区形成剖面为U型的结构的肖特基接触，可以凭借较小的平面面积获得较大的肖特基接触面积，并且由于肖特基接触为钴硅化物所形成，因此有较强的过电流能力。该肖特基二极管结构适用于Low Side、High Side及全隔离结构的LDMOSFET，因此具有广泛的适用性。
在其中一个实施例中，所述第一掺杂区的一侧面靠近所述沟槽的顶部设置。
在其中一个实施例中，所述LDMOSFET还包括：场区绝缘层，位于所述体区与所述漏极区之间。
在其中一个实施例中，所述LDMOSFET还包括：栅极，一侧靠近所述源极区，另一侧靠近所述漏极区，所述栅极的一部分位于所述场区绝缘层上。
在其中一个实施例中，所述LDMOSFET还包括位于所述漏极区表面的第二钴硅化物层，所述肖特基二极管的阴极通过所述第二钴硅化物层引出。
在其中一个实施例中，所述集成肖特基二极管的LDMOSFET为全隔离结构的LDMOS，所述全隔离结构的LDMOS还包括：第二导电类型阱区，所述漂移区位于所述第二导电类型阱区中；埋藏区，位于所述第二导电类型阱区下方，且位于所述第二导电类型阱区与所述衬底之间，所述埋藏区具有第一导电类型；隔离区，位于所述第二导电类型阱区的外侧，部分所述衬底位于所述隔离区的背离所述第二导电类型阱区的一侧，所述隔离区的底部与所述埋藏区直接接触。
在其中一个实施例中，所述LDMOSFET还包括位于所述第一钴硅化物层的上表面的金属钛粘结层，以及位于所述金属钛粘结层的上表面的氮化钛层。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型。
还有必要提供一种集成肖特基二极管的LDMOSFET的制造方法。
一种集成肖特基二极管的LDMOSFET的制造方法，包括：获取衬底；所述衬底中形成有漂移区，所述漂移区中形成有体区，所述漂移区具有第一导电类型，所述体区具有第二导电类型，所述第一导电类型和第二导电类型为相反的导电类型；形成源极区和漏极区；所述源极区形成于所述体区中，所述漏极区与所述漂移区直接接触，所述源极区和漏极区具有第一导电类型；形成贯穿所述体区的沟槽，所述沟槽的底部延伸至所述漂移区中；通 过自对准金属硅化物工艺形成金属硅化物层，所述金属硅化物层包括形成于所述沟槽的底面和内壁的第一钴硅化物层，和形成于所述漏极区的表面的第二钴硅化物层，所述第一钴硅化物层与所述漂移区形成肖特基接触；其中，所述漂移区作为所述肖特基二极管的阴极，与所述漂移区直接接触的所述第一钴硅化物层作为所述肖特基二极管的阳极。
上述集成肖特基二极管的LDMOSFET的制造方法，利用沟槽的底面和内壁，使第一钴硅化物层与漂移区形成剖面为U型的结构的肖特基接触，可以凭借较小的平面面积获得较大的肖特基接触面积，并且由于肖特基接触为自对准金属硅化物(salicide)工艺的钴硅化物层所形成，因此有较强的过电流能力。该肖特基二极管结构适用于Low Side、High Side及全隔离结构的LDMOSFET，因此具有广泛的适用性。
在其中一个实施例中，所述形成源极区和漏极区的步骤之前，还包括：在所述体区与所述漏极区之间形成场区绝缘层。
在其中一个实施例中，所述形成源极区和漏极区的步骤之前，还包括：形成栅极，所述栅极的一侧靠近所述源极区、另一侧靠近所述漏极区，所述栅极的一部分形成于所述场区绝缘层上。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型。
在其中一个实施例中，所述通过自对准金属硅化物工艺形成金属硅化物层的步骤之后，还包括在所述第一钴硅化物层上形成金属钛粘结层和氮化钛层的步骤。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一示例性的LDMOSFET的电路原理图；
图2是一集成了肖特基二极管的LDMOSFET的电路原理图；
图3是本申请一实施例中集成肖特基二极管的LDMOSFET的剖面结构示意图；
图4是本申请一实施例中集成肖特基二极管的全隔离结构LDMOSFET的结构示意图；
图5是本申请一实施例中集成肖特基二极管的LDMOSFET的制造方法的流程图；
图6a至图6c是采用图5所示方法制造LDMOS的过程中器件的剖面示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。本说明书中的“连接”，如果被连接的电路、模块、单元等相互之间具有电信号或数据的传递，则应理解为“电性连接”、“通信连接”等。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向) 并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。可以理解，“至少一个”是指一个或多个，“多个”是指两个或两个以上。“元件的至少部分”是指元件的部分或全部。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本申请的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图3是本申请一实施例中集成肖特基二极管的LDMOSFET的剖面结构示意图。注意图3所示结构为左右对称结构，因此部分结构只标示出其中一个，对称的另一个则未进行标示。图3所示实施例中集成的肖特基二极管包括阱区、体区124及第一钴硅化物层142。其中阱区为LDMOSFET的漂移区122。漂移区122具有第一导电类型。体区124设于漂移区122中，具有第二导电类型。体区124被沟槽131贯穿，沟槽131的底部延伸至漂移区122中。第一钴硅化物层142形成于沟槽131的底面和内壁，第一钴硅化物层142与漂移区122形成肖特基接触。其中，漂移区122作为肖特基二极管的阴极，与漂移区122直接接触的第一钴硅化物层142作为肖特基二极管的阳极。在图3所示的实施例中， LDMOSFET为NLDMOS，第一导电类型为N型，第二导电类型为P型。相应地，衬底110为P型衬底P-Sub，漂移区122为N型漂移区N-Drift，体区124为P型体区P-Body。
上述肖特基二极管，利用沟槽131的底面和内壁，使第一钴硅化物层142与漂移区122形成剖面为U型的结构的肖特基接触，可以凭借较小的平面面积获得较大的肖特基接触面积，因此有较强的过电流能力。另一方面，由于该肖特基接触为钴硅化物所形成，同样有利于获得较强的过电流能力。
在图3所示的实施例中，该LDMOSFET还包括衬底110、源极区132(第一掺杂区)及漏极区134(第二掺杂区)。漂移区122位于衬底110中。在图3所示的实施例中，衬底110具有第二导电类型。源极区132位于体区124中，源极区132具有第一导电类型，一部分第一钴硅化物层142位于源极区132的表面。在图3所示的实施例中，源极区132的一侧面靠近沟槽131的顶部设置。漏极区134与漂移区122直接接触，具有第一导电类型。漏极区134的掺杂浓度大于漂移区122的掺杂浓度。即源极区132和漏极区134为N+区。图3所示的结构适用于半桥电路中的Low Side(低侧)、High Side(高侧)及全隔离结构(Fully Isolated)的NLDMOSFET，因此具有广泛的适用性。其中半桥电路中的Low Side NLDMOSFET的源极、体(bulk)及衬底具有相同的电位；半桥电路中的High Side NLDMOSFET的体(bulk)及衬底具有不同的电位；全隔离结构的体(bulk)及衬底也具有不同的电位。
在图3所示的实施例中，该LDMOSFET还包括场区绝缘层150和栅极136。栅极136的一侧靠近源极区132，另一侧靠近漏极区134。栅极136的一部分位于场区绝缘层150上。在本申请的一个实施例中，场区绝缘层150为场氧层，其材质为硅氧化物，例如二氧化硅。在本申请的一个实施例中，栅极136为多晶硅材料，在其他实施例中也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极136的材料。
在图3所示的实施例中，肖特基二极管还包括位于漏极区134表面的第二钴硅化物层144。肖特基二极管的阴极通过第二钴硅化物层144引出。第二钴硅化物层144能够降低漏极区134的接触电阻。
在本申请的一个实施例中，肖特基二极管还包括位于第一钴硅化物层142的上表面的金属钛粘结层，以及位于金属钛粘结层的上表面的氮化钛层。
由于U型的剖面结构使得肖特基接触面积较大，因此具有较强的降低肖特基二极管的导通压降的效果。在本申请的一个实施例中，肖特基二极管的导通压降可以减小到0.3V左右，降低了源极区132和漏极区134之间体二极管的导通压降以及导通损耗。
图4是本申请一实施例中集成肖特基二极管的全隔离结构LDMOSFET的结构示意图。在图3所示实施例的基础上，该LDMOSFET进一步包括第二导电类型阱区126、埋藏区128及隔离区129。漂移区122位于第二导电类型阱区126中。埋藏区128位于第二导电类型阱区126下方，且位于第二导电类型阱区126与衬底110之间。在图4所示的实施例中，埋藏区128为第一导电类型埋层。隔离区129位于第二导电类型阱区126的外侧，部分衬底110位于隔离区129的外侧(即背离第二导电类型阱区126的一侧)，隔离区129的底部与埋藏区128直接接触。在本申请的一个实施例中，隔离区129为第一导电类型的掺杂区。全隔离结构LDMOSFET将第二导电类型阱区126与衬底110进行隔离，使得第二导电类型阱区126与衬底110具有不同的电位。
本申请相应提供一种集成肖特基二极管的LDMOSFET的制造方法，其可以用于制造前述任一实施例所述的集成肖特基二极管的LDMOSFET。图5是本申请一实施例中集成肖特基二极管的LDMOSFET的制造方法的流程图，包括下列步骤：
S210，获取形成有漂移区和体区的衬底。
参见图6a，漂移区122形成于衬底110中，体区124形成于漂移区122中。漂移区122具有第一导电类型，体区124具有第二导电类型。在图6a所示的实施例中，制造的LDMOSFET为NLDMOS，第一导电类型为N型，第二导电类型为P型。
在本申请的一个实施例中，衬底110为半导体衬底，其材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等，还可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体。在图6a所示的实施例中，衬底110的构成材料选用单晶硅。
在本申请的一个实施例中，可以使用合适的方法形成漂移区122，例如掺杂工艺。掺杂一般是通过离子注入的方法实现。若制备N型的漂移区122，则对衬底110中预定形成漂移区122的区域进行N型离子掺杂，例如在光刻后进行离子注入，以在衬底110内形成 N型的漂移区122。同样可以使用合适的方法形成体区124，例如掺杂工艺。若制备P型的体区124，则对漂移区122中预定形成体区124的区域进行P型离子掺杂，例如在光刻后进行离子注入，以在衬底110内形成P型的体区124。
S220，形成源极区和漏极区。
源极区132形成于体区124中，漏极区134与漂移区122直接接触。源极区132和漏极区134具有第一导电类型。
在本申请的一个实施例中，在步骤S210之后、步骤S220之前，还包括形成场区绝缘层150的步骤，以及形成栅极136的步骤，参见图6b。在本申请的一个实施例中，场区绝缘层150为场氧层，其材质为硅氧化物，例如二氧化硅。场区绝缘层150可以采用本领域技术人员能够得知的工艺形成，例如热氧化工艺。
在本申请的一个实施例中，栅极136的材质为多晶硅材料；在其他实施例中也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极材质。在本申请的一个实施例中，栅极136的形成方法可以采用化学气相淀积法(CVD)，如低温化学气相淀积(LTCVD)、低压化学气相淀积(LPCVD)、快热化学气相淀积(LTCVD)、等离子体化学气相淀积(PECVD)，也可使用例如溅镀及物理气相淀积(PVD)等方法。栅极136的厚度可以根据器件的尺寸使用适合的厚度，在此不做具体限制。
在本申请的一个实施例中，形成源极区132和漏极区134的方法包括对半导体衬底中预定形成源极和漏极的区域执行源漏离子注入。具体可以利用光刻工艺首先形成暴露出预定形成源极区132和漏极区134的区域的图案化的光刻胶层，再以该图案化的光刻胶层为掩膜，进行源漏离子注入，最后利用例如灰化的方法去除图案化的光刻胶层。
随后，还可以进行退火工艺，示例性地，退火可以使用本领域技术人员熟知的任何的退火处理方法，包括但不限于快速热退火、炉管退火、峰值退火、激光退火等，例如，进行快速升温退火工艺，利用900至1050℃的高温来活化源极区132和漏极区134内的掺杂质，并同时修补在各离子注入工艺中受损的半导体衬底表面的晶格结构。此外，亦可视产品需求及功能性考量，另于源极区132漏极区134与栅极136之间分别形成轻掺杂漏极(LDD)。
S230，形成贯穿体区的沟槽。
参见图6c，沟槽131的底部延伸至漂移区122中。沟槽131可以通过光刻及刻蚀工艺形成。在本申请的一个实施例中，为了最大限度地增加后续形成的肖特基二极管的金半界面(金属或金属硅化物与N型半导体材料之间的接触面)，沟槽131的底部应尽可能地接近漂移区122的底部，但是必须与漂移区122下方的衬底110间隔设置。肖特基二极管的金半界面面积越大，减小源/漏之间的体二极管的导通压降以及导通损耗的能力就越强。
在图6c所示的实施例中，沟槽131的顶部位于源极区132的边缘。
S240，通过自对准金属硅化物(salicide)工艺形成金属硅化物层。
步骤S240完成后的器件结构可以参照图3。金属硅化物层包括形成于沟槽131的底面和内壁的第一钴硅化物层142，和形成于漏极区134表面的第二钴硅化物层144。第一钴硅化物层142与阱区形成肖特基接触。漂移区122作为肖特基二极管的阴极，与漂移区122接触的第一钴硅化物层142作为肖特基二极管的阳极。
自对准金属硅化物(salicide)是一种简单方便的接触金属化工艺。在半导体器件的制作过程中，有一些区域需要salicide过程，而有些区域需要非自对准金属硅化物(non-salicide)过程，对于需要non-salicide过程的器件，就要利用上述salicide的特性，用不会与金属反应的材料把需要non-salicide的区域覆盖起来。这种用于覆盖non-salicide器件的材料就称为自对准硅化物阻挡膜(SAB)。
步骤S240可以沿用器件对应线宽制程的salicide工序形成第一钴硅化物层142，例如0.18微米的标准BCD(Bipolar-CMOS-DMOS)工艺中的salicide工艺。肖特基接触采用标准的salicide工艺使钴与硅发生化学反应形成钴硅化物，工艺简单易行，工艺兼容性高。参照图3，步骤S240形成的一部分第一钴硅化物层142是形成在源极区132的表面。
上述集成肖特基二极管的LDMOSFET的制造方法，利用沟槽131的底面和内壁，使第一钴硅化物层132与漂移区122形成剖面为U型的结构的肖特基接触，可以凭借较小的平面面积获得较大的肖特基接触面积，并且由于肖特基接触为自对准金属硅化物(salicide)工艺的钴硅化物层所形成，因此有较强的过电流能力。该肖特基二极管结构适用于Low Side、High Side及全隔离结构的LDMOSFET，因此具有广泛的适用性。
在本申请的一个实施例中，在步骤S240之后，还包括在第一钴硅化物层142上形成金属钛粘结层和氮化钛层以形成欧姆接触的步骤。
应该理解的是，虽然本申请的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，本申请的流程图中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种肖特基二极管，包括：
    阱区，具有第一导电类型；
    体区，设于所述阱区的上部，具有第二导电类型；所述体区被沟槽贯穿，所述沟槽的底部延伸至所述阱区中；
    第一钴硅化物层，形成于所述沟槽的底面和内壁，所述第一钴硅化物层与所述阱区形成肖特基接触；
    其中，所述阱区作为所述肖特基二极管的阴极，与所述阱区直接接触的所述第一钴硅化物层作为所述肖特基二极管的阳极，所述第一导电类型和第二导电类型为相反的导电类型。
  2. 根据权利要求1所述的肖特基二极管，还包括位于所述体区中的第一掺杂区，所述第一掺杂区具有第一导电类型，一部分所述第一钴硅化物层位于所述第一掺杂区的表面。
  3. 根据权利要求2所述的肖特基二极管，其中，所述第一掺杂区的一侧面靠近所述沟槽的顶部设置。
  4. 根据权利要求1所述的肖特基二极管，还包括：
    第二掺杂区，与所述阱区直接接触，具有第一导电类型。
  5. 根据权利要求4所述的肖特基二极管，还包括：
    场区绝缘层，位于所述体区与所述第二掺杂区之间。
  6. 根据权利要求3所述的肖特基二极管，还包括：
    衬底，所述阱区位于所述衬底中。
  7. 根据权利要求3所述的肖特基二极管，还包括：
    第二钴硅化物层，位于所述第二掺杂区的表面，所述肖特基二极管的阴极通过所述第二钴硅化物层引出。
  8. 根据权利要求1所述的肖特基二极管，还包括：
    金属钛粘结层，位于所述第一钴硅化物层的上表面；
    氮化钛层，位于所述金属钛粘结层的上表面。
  9. 根据权利要求1所述的肖特基二极管，其中，所述第一导电类型为N型，所述第二导电类型为P型。
  10. 一种集成肖特基二极管的LDMOSFET，包括：
    衬底；
    漂移区，设于所述衬底中，具有第一导电类型；
    体区，设于所述漂移区中，具有第二导电类型；所述体区被沟槽贯穿，所述沟槽的底部延伸至所述漂移区中；
    第一钴硅化物层，形成于所述沟槽的底面和内壁，所述第一钴硅化物层与所述漂移区形成肖特基接触；
    源极区，位于所述体区中，所述源极区具有第一导电类型，一部分所述第一钴硅化物层位于所述源极区的表面；
    漏极区，与所述漂移区直接接触，具有第一导电类型；
    其中，所述漂移区作为所述肖特基二极管的阴极，与所述漂移区直接接触的所述第一钴硅化物层作为所述肖特基二极管的阳极，所述第一导电类型和第二导电类型为相反的导电类型。
  11. 根据权利要求10所述的集成肖特基二极管的LDMOSFET，还包括：
    场区绝缘层，位于所述体区与所述漏极区之间；
    栅极，一侧靠近所述源极区，另一侧靠近所述漏极区，所述栅极的一部分位于所述场区绝缘层上。
  12. 根据权利要求10所述的集成肖特基二极管的LDMOSFET，还包括位于所述漏极区表面的第二钴硅化物层，所述肖特基二极管的阴极通过所述第二钴硅化物层引出。
  13. 根据权利要求10所述的集成肖特基二极管的LDMOSFET，其中，所述集成肖特基二极管的LDMOSFET为全隔离结构的LDMOS，所述全隔离结构的LDMOS还包括：
    第二导电类型阱区，所述漂移区位于所述第二导电类型阱区中；
    埋藏区，位于所述第二导电类型阱区下方，且位于所述第二导电类型阱区与所述衬底之间，所述埋藏区具有第一导电类型；
    隔离区，位于所述第二导电类型阱区的外侧，部分所述衬底位于所述隔离区的背离所 述第二导电类型阱区的一侧，所述隔离区的底部与所述埋藏区直接接触。
  14. 一种集成肖特基二极管的LDMOSFET的制造方法，包括：
    获取衬底；所述衬底中形成有漂移区，所述漂移区中形成有体区，所述漂移区具有第一导电类型，所述体区具有第二导电类型，所述第一导电类型和第二导电类型为相反的导电类型；
    形成源极区和漏极区；所述源极区形成于所述体区中，所述漏极区与所述漂移区直接接触，所述源极区和漏极区具有第一导电类型；
    形成贯穿所述体区的沟槽，所述沟槽的底部延伸至所述漂移区中；
    通过自对准金属硅化物工艺形成金属硅化物层，所述金属硅化物层包括形成于所述沟槽的底面和内壁的第一钴硅化物层，和形成于所述漏极区的表面的第二钴硅化物层，所述第一钴硅化物层与所述漂移区形成肖特基接触；
    其中，所述漂移区作为所述肖特基二极管的阴极，与所述漂移区直接接触的所述第一钴硅化物层作为所述肖特基二极管的阳极。
  15. 根据权利要求14所述的集成肖特基二极管的LDMOSFET的制造方法，还包括：在所述形成源极区和漏极区之前，
    在所述体区与所述漏极区之间形成场区绝缘层；
    形成栅极，所述栅极的一侧靠近所述源极区、另一侧靠近所述漏极区，所述栅极的一部分形成于所述场区绝缘层上。
PCT/CN2024/070570 2023-06-15 2024-01-04 肖特基二极管、集成肖特基二极管的ldmosfet及其制造方法 Ceased WO2024255218A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202310715648.6 2023-06-15
CN202310715648.6A CN119153490A (zh) 2023-06-15 2023-06-15 肖特基二极管、集成肖特基二极管的ldmosfet及其制造方法

Publications (1)

Publication Number Publication Date
WO2024255218A1 true WO2024255218A1 (zh) 2024-12-19

Family

ID=93804701

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/070570 Ceased WO2024255218A1 (zh) 2023-06-15 2024-01-04 肖特基二极管、集成肖特基二极管的ldmosfet及其制造方法

Country Status (2)

Country Link
CN (1) CN119153490A (zh)
WO (1) WO2024255218A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5585294A (en) * 1994-10-14 1996-12-17 Texas Instruments Incorporated Method of fabricating lateral double diffused MOS (LDMOS) transistors
US20090294859A1 (en) * 2008-05-28 2009-12-03 Force-Mos Technology Corporation Trench MOSFET with embedded junction barrier Schottky diode
US20120175724A1 (en) * 2011-01-06 2012-07-12 Haynie Sheldon D Trenched Schottky Diode and Method of Forming a Trenched Schottky Diode
US20160260831A1 (en) * 2015-03-03 2016-09-08 Micrel, Inc. Dmos transistor with trench schottky diode
US20180358463A1 (en) * 2017-06-09 2018-12-13 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing a semiconductor device
CN109873039A (zh) * 2017-12-05 2019-06-11 无锡华润上华科技有限公司 肖特基二极管及集成肖特基二极管的ldmosfet
US10777689B1 (en) * 2019-10-18 2020-09-15 Hong Kong Applied Science and Technology Research Institute Company, Limited Silicon-carbide shielded-MOSFET embedded with a trench Schottky diode and heterojunction gate

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5585294A (en) * 1994-10-14 1996-12-17 Texas Instruments Incorporated Method of fabricating lateral double diffused MOS (LDMOS) transistors
US20090294859A1 (en) * 2008-05-28 2009-12-03 Force-Mos Technology Corporation Trench MOSFET with embedded junction barrier Schottky diode
US20120175724A1 (en) * 2011-01-06 2012-07-12 Haynie Sheldon D Trenched Schottky Diode and Method of Forming a Trenched Schottky Diode
US20160260831A1 (en) * 2015-03-03 2016-09-08 Micrel, Inc. Dmos transistor with trench schottky diode
US20180358463A1 (en) * 2017-06-09 2018-12-13 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing a semiconductor device
CN109873039A (zh) * 2017-12-05 2019-06-11 无锡华润上华科技有限公司 肖特基二极管及集成肖特基二极管的ldmosfet
US10777689B1 (en) * 2019-10-18 2020-09-15 Hong Kong Applied Science and Technology Research Institute Company, Limited Silicon-carbide shielded-MOSFET embedded with a trench Schottky diode and heterojunction gate

Also Published As

Publication number Publication date
CN119153490A (zh) 2024-12-17

Similar Documents

Publication Publication Date Title
US8853772B2 (en) High-mobility trench MOSFETs
TWI540648B (zh) 具有增加的緩衝崩潰電壓之三族氮化物ｈｅｍｔ
CN107887445A (zh) 半导体器件及其制造方法及包括该器件的电子设备
US11081580B2 (en) High-voltage semiconductor devices and methods for manufacturing the same
US8138547B2 (en) MOSFET on silicon-on-insulator REDX with asymmetric source-drain contacts
TW200818508A (en) Semiconductor device and method of manufacturing the same
CN109801961B (zh) 半导体结构及其形成方法
JP2004158813A (ja) 半導体装置及びその製造方法
CN101777586B (zh) 一种混合结型源漏场效应晶体管及其制备方法
TW201705447A (zh) Ｄｍｏｓ及ｃｍｏｓ半導體裝置之改良整合
CN102324434B (zh) 一种肖特基势垒mos晶体管及其制备方法
WO2020073459A1 (zh) 半导体器件及其制造方法及包括该器件的电子设备
WO2024255218A1 (zh) 肖特基二极管、集成肖特基二极管的ldmosfet及其制造方法
WO2025001381A1 (zh) Soi半导体结构及其制造方法
JPH0897410A (ja) 自己整合した横型ｄｍｏｓトランジスタの製造法
CN100389501C (zh) 一种肖特基势垒mos晶体管及其制作方法
CN110828566B (zh) 半导体结构及其形成方法
TWI716713B (zh) 半導體結構及其形成方法
CN108878505B (zh) 半导体装置及其制造方法
WO2024164740A1 (zh) 具有隔离结构的半导体器件及其制造方法
US10600919B1 (en) Semiconductor structure and method for forming the same
TWI852818B (zh) 半導體元件及其製造方法
JP3210146B2 (ja) 半導体装置
US20260013155A1 (en) Semiconductor device
US20250234585A1 (en) Extended drain metal oxide semiconductor (edmos) field effect transistor (fet) with dual thickness semiconductor material

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24822179

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE