WO2024254937A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024254937A1
WO2024254937A1 PCT/CN2023/108079 CN2023108079W WO2024254937A1 WO 2024254937 A1 WO2024254937 A1 WO 2024254937A1 CN 2023108079 W CN2023108079 W CN 2023108079W WO 2024254937 A1 WO2024254937 A1 WO 2024254937A1
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WO
WIPO (PCT)
Prior art keywords
layer
light
emitting
substrate
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/108079
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English (en)
French (fr)
Inventor
李小康
余海军
顾宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Filing date
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to DE112023000065.4T priority Critical patent/DE112023000065T5/de
Priority to US18/549,919 priority patent/US20250098444A1/en
Publication of WO2024254937A1 publication Critical patent/WO2024254937A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask

Definitions

  • OLED Organic Light Emitting Diode
  • the OLED device in the OLED display panel is composed of an anode, a light-emitting layer and a cathode, wherein part of the film layer in the light-emitting layer is formed by open mask evaporation, which can reduce the use of fine metal mask (FMM) and save preparation costs.
  • FMM fine metal mask
  • a pixel definition layer is disposed on one side of the substrate, and includes a first groove correspondingly disposed in the light-emitting area and a second groove disposed in the non-light-emitting area;
  • a plurality of partitions are arranged in the non-luminous area and located on a side of the pixel definition layer away from the substrate, the partitions comprising: a first portion arranged corresponding to the second groove, and a second portion arranged on a side of the first portion away from the substrate, the width of the second portion is greater than the width of the first portion, and the second portion is spaced apart from a surface of the pixel definition layer away from the substrate;
  • a light-emitting layer is arranged on a side of the pixel definition layer and the partition portion away from the substrate, the light-emitting layer includes pixels arranged corresponding to the first groove, the light-emitting layer includes a plurality of stacked sub-film layers, and at least some of the sub-film layers of the light-emitting layer are disconnected at the partition portion.
  • a sidewall of the first portion is disposed in contact with the pixel definition layer.
  • the display panel further includes a first layer located in the non-luminous area, wherein the first layer is disposed between a surface of the pixel definition layer away from the substrate and the second portion, and is disposed close to the first portion.
  • the display panel further includes a first layer located in the non-luminous area, and the first layer is at least disposed between a side wall of the first portion and a side wall of the second groove.
  • the first layer is further disposed between a bottom surface of the first portion and a bottom surface of the second groove.
  • the first layer further extends between a surface of the pixel definition layer away from the substrate and the second portion, and the light-emitting layer is spaced apart from the first layer at an end portion on the side of the partition portion.
  • the light-emitting layer includes a first light-emitting sublayer, a second light-emitting sublayer located on a side of the first light-emitting sublayer away from the substrate, and a charge generation layer located between the first light-emitting sublayer and the second light-emitting sublayer; wherein the charge generation layer is disconnected at the partition portion.
  • the display panel further includes an anode layer and a cathode layer, the anode layer is arranged on a side of the light-emitting layer close to the substrate, and the cathode layer is arranged on a side of the light-emitting layer away from the substrate; wherein the cathode layer is continuously arranged at the partition portion.
  • the display panel further includes: a driving circuit layer, disposed between the substrate and the pixel definition layer; and a planar layer, disposed between the driving circuit layer and the pixel definition layer; wherein the second groove penetrates the pixel definition layer, and the first portion is disposed in contact with the planar layer.
  • the partition portion further includes a third groove disposed on a side of the second portion away from the substrate, and at least a portion of a sub-film layer of the light-emitting layer is disposed in the third groove.
  • At least part of the sub-layers of the light-emitting layer are intermittently disposed in the third groove.
  • the third groove passes through the second portion and the first portion.
  • the second portion includes a first surface close to the first portion and a second surface far from the first portion, and an orthographic projection of the first surface on the substrate is located within an orthographic projection of the second surface on the substrate.
  • an outer contour of an orthographic projection of the first surface on the substrate is spaced apart from an outer contour of an orthographic projection of the second surface on the substrate.
  • At least one second groove is disposed between two adjacent light-emitting areas, and at least a portion of the second groove extends along an edge of an adjacent light-emitting area.
  • At least one of the pixels has a second groove arranged in a closed loop around its periphery.
  • the embodiment of the present application further provides a display device, the display device comprising a display panel, the display panel comprising a plurality of light-emitting areas arranged at intervals and a non-light-emitting area located between the light-emitting areas, the display panel comprising:
  • a pixel definition layer is disposed on one side of the substrate, and includes a first groove correspondingly disposed in the light-emitting area and a second groove disposed in the non-light-emitting area;
  • a plurality of partitions are arranged in the non-luminous area and located on a side of the pixel definition layer away from the substrate, the partitions comprising: a first portion arranged corresponding to the second groove, and a second portion arranged on a side of the first portion away from the substrate, the width of the second portion is greater than the width of the first portion, and the second portion is spaced apart from a surface of the pixel definition layer away from the substrate;
  • a light-emitting layer is arranged on a side of the pixel definition layer and the partition portion away from the substrate, the light-emitting layer includes pixels arranged corresponding to the first groove, the light-emitting layer includes a plurality of stacked sub-film layers, and at least some of the sub-film layers of the light-emitting layer are disconnected at the partition portion.
  • a sidewall of the first portion is disposed in contact with the pixel definition layer.
  • the display panel further includes a first layer located in the non-luminous area, and the first layer is at least disposed between a side wall of the first portion and a side wall of the second groove.
  • the present application sets a partition portion in the non-luminous area, wherein the first portion of the partition portion corresponds to the second groove, the second portion of the partition portion is wider than the first portion, and the second portion of the partition portion is spaced apart from the pixel definition layer, which is beneficial for disconnecting at least part of the sub-film layer of the luminous layer at the side of the second portion, thereby reducing the leakage path of the leakage current and reducing the risk of pixel stealth.
  • FIG1 is a schematic top view of a first structure of a display panel provided in an embodiment of the present application.
  • FIG2 is a schematic top view of a second structure of a display panel provided in an embodiment of the present application.
  • FIG3 is a schematic top view of a third structure of a display panel provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of a first structure along the D1-D2 section of FIG1 ;
  • FIG5 is an enlarged schematic diagram of region E of FIG4 ;
  • FIG7 is a schematic diagram of a third structure along the D1-D2 section of FIG1;
  • FIG8 is a schematic diagram of a fourth structure along the D1-D2 section of FIG1;
  • FIG9 is a schematic diagram of a fifth structure along the D1-D2 section of FIG1 ;
  • FIG10 is a sixth structural schematic diagram along the D1-D2 section of FIG1 ;
  • FIG11 is a schematic diagram of a seventh structure along the D1-D2 section of FIG1 ;
  • FIG12 is a schematic diagram of an eighth structure along the D1-D2 section of FIG1;
  • FIG13 is a schematic diagram of a ninth structural example along the D1-D2 section of FIG1 ;
  • FIG14 is an enlarged schematic diagram of region E of FIG13 ;
  • FIG15 is a schematic diagram of the tenth structure along the D1-D2 section of FIG1;
  • FIG16 is an enlarged schematic diagram of region E of FIG15 ;
  • FIG17 is a flowchart of the steps of a method for manufacturing a display panel provided in an embodiment of the present application.
  • FIG18 is a schematic top view of a step of a method for manufacturing a display panel provided in an embodiment of the present application.
  • 19A to 19F are schematic diagrams of a first process of a method for manufacturing a display panel provided in an embodiment of the present application.
  • 20A to 20F are schematic diagrams of a second process of the method for manufacturing a display panel provided in an embodiment of the present application.
  • 21A to 21D are schematic diagrams of a third process of the method for manufacturing a display panel provided in an embodiment of the present application.
  • FIG. 22 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • the present application provides a display panel and a display device. To make the purpose, technical solution and effect of the present application clearer and more specific, the present application is further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present application and are not used to limit the present application.
  • the embodiments of the present application provide a display panel and a display device.
  • the following are detailed descriptions of each. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.
  • an embodiment of the present application provides a display panel 100, including a plurality of light-emitting areas A arranged at intervals and a non-light-emitting area C located between the light-emitting areas A.
  • the display panel 100 includes:
  • the pixel definition layer 300 is disposed on the substrate 210 and includes a first groove G1 correspondingly disposed in the light emitting area A and a second groove G2 disposed in the non-light emitting area C;
  • a plurality of partitioning parts 700 are arranged in the non-luminous area C and located at a side of the pixel definition layer 300 away from the substrate 210, the partitioning part 700 includes: a first part 710 arranged corresponding to the second groove G2, and a second part 720 arranged at a side of the first part 710 away from the substrate 210, the width of the second part 720 is greater than the width of the first part 710, and the second part 720 is spaced apart from the surface of the pixel definition layer 300 away from the substrate 210;
  • the light-emitting layer 400 is arranged on a side of the pixel definition layer 300 and the partition portion 700 away from the substrate 210.
  • the light-emitting layer 400 includes pixels arranged corresponding to the first groove G1.
  • the light-emitting layer 400 includes a plurality of stacked sub-film layers, and at least part of the sub-film layers of the light-emitting layer 400 are disconnected at the partition portion 700.
  • the present application provides a partition portion in the non-luminous area, wherein the first part of the partition portion is provided in the second groove, the second part of the partition portion is wider than the first part, and at the same time, the second part of the partition portion is spaced from the pixel definition layer, which is beneficial for disconnecting at least part of the sub-film layers of the luminous layer at the side of the second part, thereby reducing the leakage path of the leakage current and reducing the risk of pixel stealing.
  • a second groove is provided in the non-luminous area, and the first part of the partition portion is provided in the second groove, thereby reducing the overall height of the partition portion, improving the leveling of the organic film layer in the encapsulation layer, and improving the encapsulation reliability of the encapsulation layer. While effectively improving the poor display caused by pixel stealing, it can also ensure better encapsulation reliability.
  • the display panel 100 includes a display area
  • the display area includes a plurality of luminous areas A arranged at intervals and a non-luminous area C located between the plurality of luminous areas A
  • the luminous area A is an area where the display panel 100 actually emits light when displaying, and is used to set a luminous unit
  • the non-luminous area C is an area where the display panel 100 remains in a black state when displaying, and is used to set necessary structures such as circuits and wiring for driving the luminous unit to emit light
  • the luminous area A generally includes a first color luminous area A1 for setting a first color luminous unit, a second color luminous area A2 for setting a second color luminous unit, and a third color luminous area A3 for setting a third color luminous unit, for example, the first color is blue, the second color is green, and the third color is red; one luminous area A corresponds to one pixel, the first color luminous area A1 corresponds to
  • the display panel 100 includes a substrate 210 and an anode layer 910 , a pixel definition layer 300 , a light emitting layer 400 , a cathode layer 920 and an encapsulation layer 800 disposed on the substrate 210 ;
  • the anode layer 910 includes a plurality of anodes arranged corresponding to the plurality of light-emitting areas A; the pixel definition layer 300 is arranged on the substrate 210, including a plurality of first grooves G1 corresponding to the plurality of light-emitting areas A and a second groove G2 arranged in the non-light-emitting area C, and a first groove G1 makes a corresponding anode exposed; the light-emitting layer 400 is arranged on the pixel definition layer 300 and the anode layer 910; the cathode layer 920 is arranged on the light-emitting layer 400; the encapsulation layer 800 is arranged on the side of the cathode layer 920 away from the substrate 210, that is, it is arranged on the side of the light-emitting layer 400 away from the substrate 210 and the side of the partition portion 700 away from the substrate 210.
  • the light emitting layer 400 includes a first light emitting sublayer 510, a second light emitting sublayer 520 located on a side of the first light emitting sublayer 510 away from the substrate 210, and a charge generation layer 610 (CGL) located between the first light emitting sublayer 510 and the second light emitting sublayer 520.
  • the light emitting layer includes a common layer 600, and the common layer 600 may include the charge generation layer 610.
  • the display panel 100 also includes a partition portion 700 arranged in the non-luminous area C, and the partition portion 700 includes: a first portion 710 arranged corresponding to the second groove G2, and a second portion 720 arranged on a side of the first portion 710 away from the substrate 210, the width of the second portion 720 is greater than the width of the first portion 710, and the second portion 720 is spaced apart from the surface of the pixel definition layer 300 away from the substrate 210.
  • the second part 720 includes a first sub-part 724 and a second sub-part 725 located outside the first sub-part 724.
  • the first sub-part 724 is connected to the first part 710; wherein the second sub-part 725 is spaced apart from the pixel definition layer 300.
  • At least one second sub-portion 725 of the partition portion 700 is spaced apart from the pixel definition layer 300.
  • the second sub-portion 725 is in a suspended state, which increases the probability of the charge generation layer 610 being disconnected at the side of the second sub-portion 725, and has a greater probability of reducing the leakage path of the leakage current, thereby reducing the risk of pixel stealing.
  • the sidewall of the first portion 710 is disposed in contact with the pixel definition layer 300.
  • the sidewall of the first portion 710 is in direct contact with the pixel definition layer 300, and the undercut structure formed between the second portion 720 and the pixel definition layer 300 is realized with a relatively simple manufacturing process, which increases the probability that at least part of the sub-film layer of the light-emitting layer 400 is disconnected on the side of the second sub-portion 725, and has a greater probability of reducing the leakage path of the leakage current, thereby reducing the risk of the pixel secretly lighting up.
  • the second portion 720 is disposed in contact with the surface of the pixel definition layer 300 away from the substrate 210.
  • a second groove is disposed in the non-luminous region, and the first portion of the partition portion is disposed in the second groove, thereby reducing the overall height of the partition portion, improving the leveling of the organic film layer in the encapsulation layer, and improving the encapsulation reliability of the encapsulation layer, effectively improving the display defects caused by the pixel stealing, and ensuring better encapsulation reliability.
  • the display panel 100 further includes a first layer 1000 located in the non-luminous area C, and the first layer 1000 is disposed between a surface of the pixel definition layer 300 away from the substrate 210 and the second portion 720 , and is disposed close to the first portion 710 .
  • the first layer 1000 can be arranged between the surface of the pixel definition layer 300 away from the substrate 210 and the second part 720 by adjusting the etching process conditions, and arranged close to the first part 710, so as to provide better support for the second part 720 and reduce the risk of the second part sinking.
  • the light emitting layer 400 is spaced apart from the first layer 1000 at an end portion on one side of the partition portion 700 .
  • the material of the first layer 1000 may include an inorganic material or a metal oxide material, such as a combination of any one or more metal oxide materials such as ITO, IZO, etc.
  • the first layer 1000 may be conductive, and the light-emitting layer 400 (such as the first light-emitting sublayer 510) is spaced apart from the first layer 1000 to avoid the generation of a new leakage path and reduce the risk of pixel stealth.
  • the display panel 100 further includes a first layer 1000 located in the non-luminous area C, and the display panel 100 further includes a first layer 1000 located between the partition portion 700 and the pixel definition layer 300, wherein the first layer 1000 is at least disposed between the side wall of the first portion 710 and the side wall of the second groove G2.
  • the first material layer 1001 can be set on the side wall of the second groove G2 and the surface of the pixel definition layer 300, and then the material film layer of the partition part 700 is formed.
  • the material film layer of the partition part 700 is patterned, and then the first material layer 1001 is patterned to remove part of the first material layer 1001 between the second part 720 and the pixel definition layer 300 to form the first layer 1000.
  • the second part 720 is suspended.
  • the probability of the common layer 600 being disconnected on the side of the second sub-part 725 is increased, and there is a greater probability of reducing the leakage path of the leakage current, thereby reducing the risk of pixel stealing.
  • the first layer 1000 is further disposed between the bottom surface of the first portion 710 and the bottom surface of the second groove G2 .
  • the first layer 1000 is arranged between the bottom surface of the first part 710 and the bottom surface of the second groove G2, so that the partition part 700 can be appropriately raised, the spacing distance between the second part 720 and the pixel definition layer 300 can be increased, and the probability of the light-emitting layer 400, for example, the common layer 600 being disconnected on the side of the second sub-part 725, is increased, and there is a greater probability of reducing the leakage path of the leakage current and reducing the risk of pixel stealing.
  • the first layer 1000 also extends between the surface of the pixel definition layer 300 away from the substrate 210 and the second portion 720 , and the light-emitting layer 400 is spaced apart from the first layer 1000 at the end on the side of the partition portion 700 .
  • the first layer can be extended outward from the second groove to below the second part by adjusting the etching process conditions, thereby facilitating better support for the second part and reducing the risk of the second part sinking.
  • the first material layer i.e., the material of the first layer 1000
  • the first material layer includes a metal oxide material or an inorganic material.
  • the metal oxide material includes any one or more combinations of ITO, IZO, etc.
  • the inorganic material such as an insulating material, includes any one or more combinations of silicon oxide compounds, silicon nitrogen compounds, silicon oxynitride, etc.
  • the first layer 1000 can be mainly used to make the second portion 720 suspended after patterning, which is only an example here without specific limitation.
  • the light-emitting layer 400 is spaced apart from the first layer 1000.
  • the material of the first layer 1000 may include a metal oxide material, such as any one or more combinations of ITO, IZO, etc.
  • the first layer 1000 may be conductive, and the light-emitting layer 400 (such as the first light-emitting sublayer 510) is spaced apart from the first layer 1000 to avoid generating a new leakage path and reduce the risk of pixel stealing.
  • the distance between the end surface of the first layer 1000 away from the substrate 210 and the substrate 210 is smaller than the distance between the surface of the pixel definition layer 300 away from the substrate 210 and the substrate 210 .
  • the first material layer 1001 When the first material layer 1001 is patterned to form the first layer 1000, a portion of the first material layer 1001 located on the side wall of the second groove G2 can be etched away by controlling the patterning time, such as the etching time, so as to reduce the risk of contact between the common layer 600 and the first layer 1000.
  • the material of the first layer 1000 may include a metal oxide material, such as any one or more combinations of ITO, IZO, etc.
  • the common layer 600 and the first layer 1000 are spaced apart to avoid the generation of a new leakage path and reduce the risk of pixel stealth.
  • a distance (a second distance L2 ) from the second surface 722 to a surface of the first portion 710 close to the substrate 210 is 0.1 ⁇ m to 4 ⁇ m.
  • the distance between the first surface 721 and the surface of the pixel definition layer 300 close to the second portion 720 is smaller than the second distance L2.
  • the distance can be adjusted according to actual conditions, such as manufacturing accuracy, process requirements, etc., which is only an example and not specifically limited.
  • the distance (third distance L3) between the farthest end point of the second sub-portion 725 away from the first sub-portion 724 and the first portion 710 is greater than or equal to 0.2 ⁇ m, so as to reduce the probability of contact between the first layer 1000 and at least part of the sub-film layer (for example, the common layer 600) of the light-emitting layer when the first layer 1000 is a metal oxide, avoid the generation of new leakage paths, and reduce the risk of pixel stealing.
  • the second portion 720 includes a first surface 721 close to the first portion 710 and a second surface 722 away from the first portion 710 , and the orthographic projection of the first surface 721 on the substrate 210 is within the orthographic projection of the second surface 722 on the substrate 210 .
  • the area of the upper surface of the second part 720 is greater than or equal to the area of the lower surface of the second part 720.
  • the second part 720 forms a non-regular trapezoidal structure, which is beneficial for at least part of the sub-film layers of the light-emitting layer (such as the common layer 600) to be disconnected on the side of the second part 720, thereby reducing and minimizing the flow path of the leakage current, which is beneficial to reducing the risk of pixel stealing, and especially improving the visual effect of the display panel at low grayscale.
  • the side of the second part 720 is represented by the first side 723, which will not be repeated below.
  • the partition part is directly set on the pixel definition layer, the part of the partition part protruding from the pixel definition layer is too high, and it will contact with the mask during the evaporation process to scratch the partition part, thereby generating particles, which can easily cause the encapsulation layer to fail.
  • thicker organic materials are required for leveling during encapsulation, which will increase the risk of module process and lead to a decrease in yield. If the height of the partition part is directly removed, a fine mask and increased related process steps are required, which will increase the cost.
  • the first part 710 of the partition part 700 is set in the second groove G2, so as to reduce the overall height of the partition part 700, reduce the thickness of the second part 720, improve the leveling of the organic film layer in the encapsulation layer 800, reduce the number of bubbles generated when the organic film layer is cured, and improve the encapsulation layer 800.
  • Better packaging reliability while effectively improving the poor display caused by pixel stealing, can also ensure better packaging reliability.
  • an outer contour of an orthographic projection of the first surface 721 on the substrate 210 is spaced apart from an outer contour of an orthographic projection of the second surface 722 on the substrate 210 .
  • the second part 720 of the partition part 700 has an inverted trapezoidal structure that is wide at the top and narrow at the bottom, which is more conducive to disconnecting at least part of the sub-film layer of the light-emitting layer 400 on the side of the second part 720, thereby reducing the leakage path of the leakage current and reducing the risk of pixel stealing.
  • an angle ⁇ between the side surface of the second portion 720 and the first surface 721 is 100° to 120°.
  • the side surface of the second portion 720 forms an undercut structure with the pixel definition layer 300, thereby increasing the probability that at least part of the sub-film layer of the light-emitting layer 400 is disconnected at the side surface of the second portion 720. If the angle between the side surface of the second portion 720 and the substrate 210 is too small, the probability that at least part of the sub-film layer of the light-emitting layer 400 is disconnected at the side surface of the second portion 720 will be reduced; if the angle between the side surface of the second portion 720 and the substrate 210 is too large, the process difficulty of forming the partition portion 700 will increase, and the cost will increase.
  • the angle ⁇ between the side surface of the second portion 720 and the first surface 721 is 100° to 120°, which can not only increase the probability that at least part of the sub-film layer of the light-emitting layer 400 is disconnected at the side surface of the second portion 720, but also facilitate the manufacturing and formation.
  • the distance (first distance L1) between the farthest point of the second surface 722 away from the first sub-portion 724 and the farthest point of the first surface 721 away from the first sub-portion 724 is 0.1 ⁇ m to 2 ⁇ m. It is easy to understand that the definition of L1 can also be applied to any embodiment in FIG. 4 to FIG. 12 .
  • the side of the second portion 720 forms an undercut structure with the pixel definition layer 300, thereby increasing the probability that at least part of the sub-film layer of the light-emitting layer 400 is disconnected at the side position of the second portion 720. If the first distance L1 is too small, the probability that at least part of the sub-film layer of the light-emitting layer 400 is disconnected at the side position of the second portion 720 will be reduced; if the first distance L1 is too large, the process difficulty of forming the partition portion 700 will increase, and the cost will increase.
  • the first distance L1 is 0.1 ⁇ m to 2 ⁇ m, which can not only increase the probability that at least part of the sub-film layer of the light-emitting layer 400 is disconnected at the side of the second portion 720, but also facilitate the manufacturing and formation.
  • the material of the partition portion 700 may be a negative photoresist. Due to the characteristics of the negative photoresist, it is convenient to form the second portion 720 into an inverted trapezoidal structure that is wider at the top and narrower at the bottom.
  • the light emitting layer 400 is disposed at intervals on the side of the second portion 720. It is easy to understand that the definition that the light emitting layer 400 is disposed at intervals on the side of the second portion 720 can also be applied to any embodiment in Figs. 4 to 12 .
  • Any film layer of the light-emitting layer 400 is disconnected at the side of the second portion 720, so as to minimize the leakage path of the leakage current and reduce the risk of pixel stealing.
  • the first light-emitting sublayer 510 includes a first light-emitting material layer 511 and a hole injection transport layer 620 (HITL) located on a side of the first light-emitting material layer 511 close to the substrate 210; wherein the first light-emitting material layer 511 is disconnected at the partition portion 700, and the hole injection transport layer 620 is disconnected at the partition portion 700.
  • HITL hole injection transport layer 620
  • the hole injection transport layer 620 and the first light emitting material layer 511 are paths for generating leakage current. The two paths are disconnected to reduce the leakage path of the leakage current and reduce the risk of pixel stealing.
  • the common layer 600 may also include the hole injection transport layer 620 .
  • first light-emitting material layer 511 and the hole injection transport layer 620 are spaced apart on the side of the second portion 720 can be applicable to a single device, which is only used as an example without specific limitation.
  • the light-emitting layer 400 includes a first light-emitting sublayer 510, a second light-emitting sublayer 520 located on a side of the first light-emitting sublayer 510 away from the substrate 210, and a charge generation layer 610 located between the first light-emitting sublayer 510 and the second light-emitting sublayer 520; wherein the charge generation layer 610 is disconnected at the partition portion 700.
  • a charge generation layer 610 is provided between the first light-emitting sublayer 510 and the second light-emitting sublayer 520, refer to FIG12 .
  • leakage current is more easily generated in the charge generation layer 610, so that adjacent pixels are stolen light, and the main leakage current path of the Tandem device is disconnected to reduce the leakage path of the leakage current and reduce the risk of pixel stolen light.
  • the common layer 600 further includes a hole injection transport layer 620 located on the side of the first light-emitting material layer 511 close to the substrate 210 ; wherein the first light-emitting material layer 511 is spaced apart on the side of the second portion 720 , and the hole injection transport layer 620 is spaced apart on the side of the second portion 720 .
  • first light-emitting material layer 511 and the hole injection transport layer 620 are spaced apart on the side of the second part 720 can be applied to a tandem device, which is only used as an example and is not specifically limited.
  • the hole injection transport layer 620 and the first light-emitting material layer 511 are both paths for generating leakage current. The two paths are disconnected to reduce the leakage path of the leakage current and reduce the risk of pixel stealing.
  • the charge generation layer 610 may be disposed at intervals on the side of the second portion 720; or, in a tandem device, the charge generation layer 610 and the first light-emitting material layer may be disposed at intervals on the side of the second portion 720; or, in a tandem device, the charge generation layer 610, the first light-emitting material layer and the hole injection transport layer 620 may all be disposed at intervals on the side of the second portion 720. This is only an example and is not specifically limited.
  • the display panel 100 further includes an anode layer 910 and a cathode layer 920 , wherein the anode layer 910 is disposed on the substrate 210 , the pixel definition layer 300 exposes a portion of the anode layer 910 , and the cathode layer 920 is disposed on a side of the light emitting layer 400 away from the substrate 210 .
  • the cathode layer 920 is continuously disposed at the partition portion 700.
  • parameters such as the height of the partition portion 700, the spacing distance between the second portion 720 and the pixel definition layer 300, and the slope of the side of the second portion 720, the cathode layer 920 is continuously disposed at the partition portion 700, thereby avoiding the cathode layer being broken and affecting the electrical performance, and reducing the risk that the cathode signal cannot be transmitted to the light-emitting area A.
  • the cathode layer 920 is arranged at intervals on the side of the second part 720.
  • the cathode layer 920 can be disconnected on the side of the second part 720; if the cathode layer 920 is to be connected on the side of the second part 720, it is necessary to control the process parameters and the thickness of the second part 720, which will increase the process cost; therefore, the requirement for the thickness of the second part 720 can be appropriately relaxed to reduce the cost, and the cathode layer 920 is disconnected on the side of the second part 720.
  • the definition of the cathode layer 920 being arranged at intervals on the side of the second part 720 can also be applied to any of the embodiments in FIG. 4 to FIG. 12 .
  • the display panel 100 further includes a cathode layer 920, and the cathode layer 920 is disposed on a side of the light emitting layer 400 away from the substrate 210.
  • the common layer 600 may further include an electron transport layer between the cathode layer 920 and the second light emitting sublayer 520.
  • the electron transport layer may be disposed at intervals on the side of the second portion 720 .
  • the electron transport layer may be continuously disposed on the side of the second portion 720. This is only an example and does not specifically limit the electron transport layer.
  • the display panel 100 includes a plurality of pixels, the pixels are arranged corresponding to the light emitting area A, the cathode layer 920 is arranged at intervals on the side of the second portion 720 , and the second groove G2 is arranged in a non-closed loop around one of the pixels.
  • the corresponding second groove G2 cannot be arranged in a closed loop around the pixel to avoid the cathode layer 920 in the light-emitting area A from becoming an isolated island and avoiding the technical problem that the cathode signal cannot be transmitted to the light-emitting area A.
  • the display panel 100 further includes a driving circuit layer 220 located on one side of the substrate 210 and a flat layer 230 located on the driving circuit layer 220 , wherein the flat layer 230 is located on a surface of the driving circuit layer 220 away from the substrate 210 , and the second groove G2 penetrates the pixel definition layer 300 to expose the flat layer 230 , so that the first portion 710 can contact the flat layer 230 .
  • the driving circuit layer 220 may include an active layer 221 , a gate layer 222 , a source-drain layer 223 , and an insulating layer between adjacent film layers that need to be insulated.
  • the structure of the driving circuit layer 220 may be a top gate design or a bottom gate design, which is only used as an example and is not specifically limited.
  • the second groove G2 penetrates the pixel definition layer 300 and forms a first depression in a portion of the planar layer 230, and the first depression is filled with the first portion 710.
  • the contact area between the first portion 710 and the planar layer 230 is further increased to improve the adhesion between the substrate 210 and the partition portion 700, reduce the risk of the partition portion 700 falling off, improve the leveling of the organic film layer in the encapsulation layer 800, and improve the encapsulation reliability of the encapsulation layer 800.
  • the partition portion 700 further includes a third groove G3 disposed on a side of the second portion 720 away from the substrate 210 , and at least a portion of a sub-film layer of the light emitting layer 400 is disposed in the third groove G3 .
  • Grooving is performed on the second portion 720 of the partition portion 700 to form a third groove G3, which can increase the probability of at least part of the sub-film layer of the light-emitting layer 400 being broken in the third groove G3, thereby reducing the risk of leakage current leakage path formation and reducing the risk of pixel stealing.
  • At least part of the sub-layers of the light emitting layer 400 are intermittently disposed in the third groove G3 .
  • At least part of the sub-layers of the light-emitting layer 400 are broken in the third groove G3, preferably the charge generation layer 610, and less preferably the first light-emitting material layer 511 and/or the hole injection transport layer 620, thereby reducing the leakage path of the leakage current and reducing the risk of pixel stealing.
  • the third groove G3 passes through the second portion 720 and the first portion 710 .
  • the third groove G3 penetrates the second portion 720 , the first portion 710 and the pixel definition layer 300 , and at least part of the sub-layer of the light emitting layer 400 is disposed in contact with the planar layer 230 through the third groove G3 .
  • the display panel 100 further includes a driving circuit layer 220 located on one side of the substrate 210 and a flat layer 230 located on the driving circuit layer 220 , wherein the flat layer 230 is located on the surface of the driving circuit layer 220 away from the substrate 210 , and the third groove G3 passes through the second portion 720 , the first portion 710 and the pixel definition layer 300 to expose the flat layer 230 , so that at least part of the sub-film layer of the light-emitting layer 400 can contact the flat layer 230 .
  • the third groove G3 penetrates the second portion 720, the first portion 710 and the pixel definition layer 300 and forms a second depression in a portion of the planar layer 230, and the second depression is filled with the common layer 600.
  • the depth of the third groove G3 is increased to increase the probability that at least part of the sub-layer of the light-emitting layer 400 is broken in the third groove G3, and there is a greater probability of reducing the leakage path of the leakage current, thereby reducing the risk of pixel stealing.
  • the display panel 100 further includes an anode layer 910 and a cathode layer 920, wherein the anode layer 910 is disposed on the substrate 210, the pixel definition layer 300 exposes a portion of the anode layer 910, and the cathode layer 920 is disposed on a side of the light emitting layer 400 away from the substrate 210; wherein the cathode layer 920 is disposed in the third groove G3.
  • the cathode layer 920 is also disposed in the third groove G3, and can fill the third groove G3, thereby preventing the groove from being too deep, reducing the difficulty of covering the packaging layer 800, and reducing the risk of packaging failure.
  • At least one second groove G2 is disposed between two adjacent light-emitting areas A, and at least a portion of the second groove G2 extends along an edge of an adjacent light-emitting area A.
  • a second groove G2 is set between the second color light-emitting area A2 and the third color light-emitting area A3, and two second grooves G2 are set between the second color light-emitting area A2 and the first color light-emitting area A1. It is easy to understand that the number between two adjacent light-emitting areas A can be three or even more, and the number between two adjacent light-emitting areas A can be adjusted according to actual conditions such as space occupancy, and is not specifically limited here.
  • the second groove G2 between the second color light-emitting area A2 and the first color light-emitting area A1 is set as a curved groove extending along the edge of the adjacent second color light-emitting area A2.
  • the second groove G2 between the second color light-emitting area A2 and the first color light-emitting area A1 can be further extended in the direction of approaching the second groove G2 between the second color light-emitting area A2 and the third color light-emitting area A3, thereby reducing the distance between the two second grooves G2, and further narrowing the connecting channel of the common layer 600 here, so that the size of the lateral leakage current here is kept below the target value.
  • the second groove G2 can be a wavy groove, a broken line groove, etc. in addition to the above-mentioned curved groove; the shape of each pixel and each color light-emitting area is only an exemplary description. In actual applications, it is adjusted according to specific circumstances.
  • the display panel 100 includes a plurality of pixels, the pixels are arranged corresponding to the light emitting area A, and the second groove G2 arranged in a closed loop is formed around at least one of the pixels.
  • the second groove G2 arranged around the pixel closed loop can increase the probability of the common layer being broken at the side of the second portion 720, thereby reducing the risk of the leakage path of the leakage current and reducing the risk of the pixel secretly lighting up.
  • the corresponding second groove G2 cannot be arranged in a closed loop around the pixel to avoid the cathode layer 920 in the light-emitting area A from becoming an isolated island and avoiding the technical problem that the cathode signal cannot be transmitted to the light-emitting area A.
  • the display panel 100 further includes a color filter layer 810 located on a side of the encapsulation layer 800 away from the substrate 210, and the color filter layer 810 includes a plurality of color resists 820.
  • the color of the color resist 820 corresponds to the color of the pixel.
  • the present application provides a partition portion in the non-luminous area, wherein the first part of the partition portion is provided in the second groove, the second part of the partition portion is wider than the first part, and at the same time, the second part of the partition portion is spaced from the pixel definition layer, which is beneficial for disconnecting at least part of the sub-film layers of the luminous layer at the side of the second part, thereby reducing the leakage path of the leakage current and reducing the risk of pixel stealing.
  • a second groove is provided in the non-luminous area, and the first part of the partition portion is provided in the second groove, thereby reducing the overall height of the partition portion, improving the leveling of the organic film layer in the encapsulation layer, and improving the encapsulation reliability of the encapsulation layer. While effectively improving the poor display caused by pixel stealing, it can also ensure better encapsulation reliability.
  • an embodiment of the present application provides a method for manufacturing a display panel 100 .
  • the display panel 100 includes a plurality of light-emitting areas A disposed at intervals and a non-light-emitting area C located between the light-emitting areas A.
  • the method for manufacturing the display panel 100 includes:
  • the partition material layer 701 is formed into a partition portion 700 which is arranged in the non-luminous area C and includes a first portion 710 and a second portion 720.
  • the first portion 710 is arranged corresponding to the second groove G2
  • the second portion 720 is arranged on a side of the first portion 710 away from the substrate 210
  • the width of the second portion 720 is greater than the width of the first portion 710
  • the second portion 720 is spaced apart from the surface of the pixel definition layer 300 away from the substrate 210.
  • the present application provides a partition portion in the non-luminous area, wherein the first part of the partition portion is provided in the second groove, the second part of the partition portion is wider than the first part, and at the same time, the second part of the partition portion is spaced from the pixel definition layer, which is beneficial for disconnecting at least part of the sub-film layers of the luminous layer at the side of the second part, thereby reducing the leakage path of the leakage current and reducing the risk of pixel stealing.
  • a second groove is provided in the non-luminous area, and the first part of the partition portion is provided in the second groove, thereby reducing the overall height of the partition portion, improving the leveling of the organic film layer in the encapsulation layer, and improving the encapsulation reliability of the encapsulation layer. While effectively improving the poor display caused by pixel stealing, it can also ensure better encapsulation reliability.
  • the manufacturing method of the display panel 100 includes:
  • the second portion 720 of the partition portion 700 formed in a subsequent step includes a first sub-portion 724 and a second sub-portion 725 located outside the first sub-portion 724, and the first sub-portion 724 is connected to the first portion 710.
  • the second sub-portion 725 and the pixel definition layer 300 can be arranged in contact, or the second sub-portion 725 and the pixel definition layer 300 can be arranged at intervals, so that when the light-emitting layer 400 is formed, the second sub-portion 725 is in a suspended state, so according to different formation processes, step S100 may include:
  • step S100 may include:
  • the material of the first material layer 1001 includes a metal oxide material or an inorganic material.
  • the metal oxide material includes any one or more combinations of ITO, IZO, etc.
  • the inorganic material such as an insulating material, includes any one or more combinations of silicon oxide compounds, silicon nitrogen compounds, silicon oxynitride, etc.
  • step S100 may include:
  • the step of providing a substrate 210 may include providing a substrate 210 ; forming a driving circuit layer 220 on the substrate 210 ; forming a planarizing layer 230 on the driving circuit layer 220 ; and forming an anode layer 910 on the planarizing layer 230 .
  • steps S110c and S120c may be performed in one step.
  • the material of the partition material layer 701 may be a negative photoresist, so as to facilitate forming the second portion 720 in an inverted trapezoidal structure that is wider at the top and narrower at the bottom.
  • the partition material layer 701 is formed into a partition portion 700 which is arranged in the non-luminous area C and includes a first portion 710 and a second portion 720.
  • the first portion 710 is arranged corresponding to the second groove G2, and the second portion 720 is arranged on a side of the first portion 710 away from the substrate 210.
  • the width of the second portion 720 is greater than the width of the first portion 710.
  • the second portion 720 is spaced apart from the surface of the pixel definition layer 300 away from the substrate 210. Please refer to Figures 19E and 20E.
  • an outer contour of the orthographic projection of the first surface 721 on the substrate 210 and an outer contour of the orthographic projection of the second surface 722 on the substrate 210 are spaced apart from each other, please refer to FIG. 4 and FIG. 5 .
  • the second portion 720 of the partition part 700 has an inverted trapezoidal structure that is wide at the top and narrow at the bottom, which is more conducive to disconnecting the film layer of the common layer 600 at the side of the second portion 720, thereby reducing the leakage path of the leakage current and reducing the risk of pixel stealing.
  • an angle between a side surface of the second portion 720 and the substrate 210 is 100° to 120°.
  • the side of the second part 720 forms an undercut structure with the pixel definition layer 300, thereby increasing the probability of the common layer 600 being disconnected at the side of the second part 720. If the angle between the side of the second part 720 and the substrate 210 is too small, the probability of the light-emitting layer 400 being disconnected at the side of the second part 720 will be reduced; if the angle between the side of the second part 720 and the substrate 210 is too large, the process difficulty of forming the partition part 700 will increase, and the cost will increase.
  • the angle between the side of the second part 720 and the substrate 210 is 100° to 120°, which can not only increase the probability of the light-emitting layer 400 being disconnected at the side of the second part 720, but also facilitate the manufacturing and formation.
  • the second portion 720 includes a first sub-portion 724 and a second sub-portion 725 located outside the first sub-portion 724 , and the first sub-portion 724 is connected to the first portion 710 .
  • step S400 may include:
  • the first material layer 1001 is removed to form the second sub-portion 725 spaced apart from the pixel definition layer 300 so that the second sub-portion 725 is in a suspended state.
  • step S400 may include:
  • the first material layer 1001 outside the second groove G2 is removed to form the second sub-portion 725 spaced apart from the pixel definition layer 300 so that the second sub-portion 725 is in a suspended state, please refer to FIG. 20F .
  • the distance between the end surface of the first layer 1000 away from the substrate 210 and the substrate 210 is smaller than the distance between the surface of the pixel definition layer 300 away from the substrate 210 and the substrate 210 .
  • the first material layer 1001 When the first material layer 1001 is patterned to form the first layer 1000, a portion of the first material layer 1001 located on the side wall of the second groove G2 can be etched away by controlling the patterning time, such as the etching time, so as to reduce the risk of contact between the common layer 600 and the first layer 1000.
  • the material of the first layer 1000 may include a metal oxide material, such as any one or more combinations of ITO, IZO, etc.
  • the common layer 600 and the first layer 1000 are spaced apart to avoid the generation of a new leakage path and reduce the risk of pixel stealth.
  • the distance (third distance L3) between the farthest end point of the second sub-portion 725 away from the first sub-portion 724 and the first portion 710 is greater than or equal to 0.2 ⁇ m, so as to reduce the probability of contact between the first layer 1000 and the common layer 600 when the first layer 1000 is a metal oxide, avoid the generation of new leakage paths, and reduce the risk of pixel stealing.
  • step S400 may include:
  • the method for manufacturing the display panel 100 further includes:
  • the cathode layer 920 is disposed continuously, as shown in FIG. 4 .
  • the cathode layer 920 is disposed at intervals on the side of the second portion 720.
  • the cathode layer 920 can be disconnected on the side of the second portion 720; if the cathode layer 920 is to be connected on the side of the second portion 720, it is necessary to control the process parameters and the thickness of the second portion 720, which will increase the process cost; therefore, the requirement for the thickness of the second portion 720 can be appropriately relaxed to reduce the cost, and the cathode layer 920 is disconnected on the side of the second portion 720.
  • the display panel 100 includes a plurality of pixels, the pixels are arranged corresponding to the light emitting area A, the cathode layer 920 is arranged at intervals on the side of the second portion 720 , and the second groove G2 is arranged in a non-closed loop around one of the pixels.
  • the corresponding second groove G2 cannot be arranged in a closed loop around the pixel to avoid the cathode layer 920 in the light-emitting area A from becoming an isolated island and avoiding the technical problem that the cathode signal cannot be transmitted to the light-emitting area A.
  • the encapsulation layer includes a first inorganic layer, a second inorganic layer, and an organic film layer located between the first inorganic layer and the second inorganic layer.
  • the present application provides a partition portion in the non-luminous area, wherein the first part of the partition portion is provided in the second groove, the second part of the partition portion is wider than the first part, and at the same time, the second part of the partition portion is spaced from the pixel definition layer, which is beneficial for disconnecting at least part of the sub-film layers of the luminous layer at the side of the second part, thereby reducing the leakage path of the leakage current and reducing the risk of pixel stealing.
  • a second groove is provided in the non-luminous area, and the first part of the partition portion is provided in the second groove, thereby reducing the overall height of the partition portion, improving the leveling of the organic film layer in the encapsulation layer, and improving the encapsulation reliability of the encapsulation layer. While effectively improving the poor display caused by pixel stealing, it can also ensure better encapsulation reliability.
  • an embodiment of the present invention further provides a display device 10 , including any of the above-mentioned display panels 100 .
  • the specific structure of the display panel 100 may be referred to any of the above embodiments and drawings of the display panel 100 , and will not be described in detail herein.
  • the display device 10 further includes a device body 20 , and the device body 20 and the display panel 100 are integrated into one body.
  • the device body 20 may include a middle frame, frame glue, etc.
  • the display device 10 may be a display terminal such as a mobile phone, a tablet, a television, etc., which is not limited here.
  • the embodiments of the present application disclose a display panel and a display device;
  • the display panel includes a light-emitting area and a non-light-emitting area,
  • the display panel includes a substrate, a pixel definition layer, a light-emitting layer and a partition portion
  • the pixel definition layer includes a first groove and a second groove arranged in the non-light-emitting area
  • the partition portion includes a first part and a second part that are connected, the first part corresponds to the second groove, the width of the second part is greater than the width of the first part, and the second part is spaced apart from the surface of the pixel definition layer away from the substrate;
  • the present application sets a partition portion in the non-light-emitting area, the first part of the partition portion is set in the second groove, the second part of the partition portion is wider than the first part, and the second part of the partition portion is spaced apart from the pixel definition layer, which is beneficial for at least part of the sub-film layer of the light

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Abstract

本申请实施例公开了一种显示面板及显示装置；显示面板包括基板、像素定义层、发光层和隔断部，像素定义层包括第一凹槽和设置于非发光区内的第二凹槽，隔断部包括连接设置的第一部分和第二部分，第一部分对应第二凹槽，第二部分的宽度大于第一部分的宽度，第二部分与像素定义层远离基板一侧的表面间隔设置。

Description

显示面板及显示装置 技术领域
本申请涉及显示领域，尤其涉及一种显示面板及显示装置。
 背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)由于其具有自发光、高对比、广视角、低功耗、可弯折等优异性能，逐渐成为显示领域的主流，OLED显示面板中的OLED器件由阳极、发光层以及阴极构成，其中发光层中的部分膜层为通过开放式掩模罩(Open Mask)蒸镀形成，这样可以减少精细金属掩模罩(Fine Metal Mask，FMM)的使用从而节省制备成本，但是这种共通的膜层不可避免地会在相邻像素间产生横向漏流，导致像素偷亮进而影响画面显示效果的问题。
因此，亟需一种显示面板及显示装置以解决上述技术问题。
 发明概述
本申请提供一种显示面板及显示装置，可以缓解目前像素偷亮影响画面显示效果的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供了一种显示面板，包括多个间隔设置的发光区以及位于各所述发光区之间的非发光区，所述显示面板包括：
基板；
像素定义层，设置于所述基板的一侧，包括对应设置于所述发光区内的第一凹槽以及设置于所述非发光区内的第二凹槽；
多个隔断部，设置于所述非发光区内且位于所述像素定义层远离所述基板的一侧，所述隔断部包括：对应所述第二凹槽设置的第一部分、和设置在所述第一部分远离所述基板一侧的第二部分，所述第二部分的宽度大于所述第一部分的宽度，所述第二部分与所述像素定义层远离所述基板一侧的表面间隔设置；
发光层，设置在所述像素定义层和所述隔断部远离所述基板的一侧，所述发光层包括对应所述第一凹槽设置的像素，所述发光层包括多个叠层设置的子膜层，所述发光层的至少部分子膜层在所述隔断部处断开设置。
在一些实施例中，所述第一部分的侧壁与所述像素定义层接触设置。
在一些实施例中，所述显示面板还包括位于所述非发光区的第一层，所述第一层设置在所述像素定义层远离所述基板一侧的表面与所述第二部分之间，且靠近所述第一部分设置。
在一些实施例中，所述发光层在所述隔断部一侧的端部与所述第一层间隔设置。
在一些实施例中，所述显示面板还包括位于所述非发光区的第一层，所述第一层至少设置于所述第一部分的侧壁与所述第二凹槽的侧壁之间。
在一些实施例中，所述第一层还设置于所述第一部分的底面与所述第二凹槽的底面之间。
在一些实施例中，所述第一层还延伸至所述像素定义层远离所述基板一侧的表面与所述第二部分之间，所述发光层在所述隔断部一侧的端部与所述第一层间隔设置。
在一些实施例中，所述发光层包括第一发光子层、位于所述第一发光子层远离所述基板一侧的第二发光子层、及位于所述第一发光子层与所述第二发光子层之间的电荷生成层；其中，所述电荷生成层在所述隔断部处断开设置。
在一些实施例中，所述显示面板还包括阳极层和阴极层，所述阳极层设置于发光层靠近所述基板一侧，所述阴极层设置于所述发光层远离所述基板一侧；其中，所述阴极层在所述隔断部处连续设置。
在一些实施例中，所述显示面板还包括：驱动电路层，设置在所述基板和所述像素定义层之间；平坦层，设置在所述驱动电路层和所述像素定义层之间；其中，所述第二凹槽贯穿所述像素定义层，所述第一部分与所述平坦层接触设置。
在一些实施例中，所述隔断部还包括设置于所述第二部分远离所述基板一侧的第三凹槽，所述第三凹槽内设置有所述发光层的至少部分子膜层。
在一些实施例中，所述发光层的至少部分子膜层在所述第三凹槽内间断设置。
在一些实施例中，所述第三凹槽贯穿所述第二部分及所述第一部分。
在一些实施例中，所述第二部分包括靠近所述第一部分的第一面以及远离所述第一部分的第二面，所述第一面在所述基板上的正投影位于所述第二面在所述基板上的正投影之内。
在一些实施例中，所述第一面在所述基板上的正投影的外轮廓与所述第二面在所述基板上的正投影的外轮廓间隔设置。
在一些实施例中，相邻两所述发光区之间设置有至少一个所述第二凹槽，至少部分所述第二凹槽沿相邻的一所述发光区边缘延伸设置。
在一些实施例中，至少一所述像素外围有呈闭环设置的所述第二凹槽。
本申请实施例还提供了一种显示装置，所述显示装置包括显示面板，所述显示面板包括多个间隔设置的发光区以及位于各所述发光区之间的非发光区，所述显示面板包括：
基板；
像素定义层，设置于所述基板的一侧，包括对应设置于所述发光区内的第一凹槽以及设置于所述非发光区内的第二凹槽；
多个隔断部，设置于所述非发光区内且位于所述像素定义层远离所述基板的一侧，所述隔断部包括：对应所述第二凹槽设置的第一部分、和设置在所述第一部分远离所述基板一侧的第二部分，所述第二部分的宽度大于所述第一部分的宽度，所述第二部分与所述像素定义层远离所述基板一侧的表面间隔设置；
发光层，设置在所述像素定义层和所述隔断部远离所述基板的一侧，所述发光层包括对应所述第一凹槽设置的像素，所述发光层包括多个叠层设置的子膜层，所述发光层的至少部分子膜层在所述隔断部处断开设置。
在一些实施例中，所述第一部分的侧壁与所述像素定义层接触设置。
在一些实施例中，所述显示面板还包括位于所述非发光区的第一层，所述第一层至少设置于所述第一部分的侧壁与所述第二凹槽的侧壁之间。
有益效果
本申请通过在非发光区设置隔断部，隔断部的第一部分对应第二凹槽设置，隔断部的第二部分比第一部分宽，同时隔断部的第二部分与像素定义层之间间隔设置，有利于发光层的至少部分子膜层在第二部分的侧面处断开，从而减少漏电流的漏电路径，减小像素偷亮的风险。
 附图说明
图1是本申请实施例提供的显示面板的第一种结构的俯视示意图；
图2是本申请实施例提供的显示面板的第二种结构的俯视示意图；
图3是本申请实施例提供的显示面板的第三种结构的俯视示意图；
图4是图1沿D1-D2截面的第一种结构示意图；
图5是图4的区域E的放大示意图；
图6是图1沿D1-D2截面的第二种结构示意图；
图7是图1沿D1-D2截面的第三种结构示意图；
图8是图1沿D1-D2截面的第四种结构示意图；
图9是图1沿D1-D2截面的第五种结构示意图；
图10是图1沿D1-D2截面的第六种结构示意图；
图11是图1沿D1-D2截面的第七种结构示意图；
图12是图1沿D1-D2截面的第八种结构示意图；
图13是图1沿D1-D2截面的第九种结构示意图；
图14是图13的区域E的放大示意图；
图15是图1沿D1-D2截面的第十种结构示意图；
图16是图15的区域E的放大示意图；
图17是本申请实施例提供的显示面板的制作方法的步骤流程图；
图18是本申请实施例提供的显示面板的制作方法的步骤中的俯视示意图；
图19A至图19F是本申请实施例提供的显示面板的制作方法的第一种流程示意图；
图20A至图20F是本申请实施例提供的显示面板的制作方法的第二种流程示意图；
图21A至图21D是本申请实施例提供的显示面板的制作方法的第三种流程示意图；
图22是本申请实施例提供的显示装置的结构示意图。
 本发明的实施方式
本申请提供一种显示面板及显示装置，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请实施例提供一种显示面板及显示装置。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图1至图16，本申请实施例提供一种显示面板100，包括多个间隔设置的发光区A以及位于各所述发光区A之间的非发光区C，所述显示面板100包括：
基板210；
像素定义层300，设置于所述基板210上，包括对应设置于所述发光区A内的第一凹槽G1以及设置于所述非发光区C内的第二凹槽G2；
多个隔断部700，设置于所述非发光区C内且位于所述像素定义层300远离所述基板210的一侧，所述隔断部700包括：对应所述第二凹槽G2设置的第一部分710、和设置在所述第一部分710远离所述基板210一侧的第二部分720，所述第二部分720的宽度大于所述第一部分710的宽度，所述第二部分720与所述像素定义层300远离所述基板210一侧的表面间隔设置；
发光层400，设置于所述像素定义层300和所述隔断部700远离所述基板210的一侧，所述发光层400包括对应所述第一凹槽G1设置的像素，所述发光层400包括多个叠层设置的子膜层，所述发光层400的至少部分子膜层在所述隔断部700处断开设置。
本申请通过在非发光区设置隔断部，隔断部的第一部分设置于第二凹槽内，隔断部的第二部分比第一部分宽，同时隔断部的第二部分与像素定义层之间间隔设置，有利于发光层的至少部分子膜层在第二部分的侧面处断开，从而减少漏电流的漏电路径，减小像素偷亮的风险；同时，在非发光区内设置第二凹槽，将隔断部的第一部分设置于第二凹槽内，从而减小隔断部的整体高度，提高封装层中有机膜层的流平性，提高封装层的封装可靠性，在有效改善因像素偷亮而造成的显示不良的同时还能保证较佳的封装可靠性。
现结合具体实施例对本申请的技术方案进行描述。
本实施例中，请参阅图1至图3，所述显示面板100包括显示区，所述显示区包括多个间隔设置的发光区A以及位于多个所述发光区A之间的非发光区C，其中，所述发光区A为显示面板100显示时实际发光的区域，用于设置发光单元，所述非发光区C为显示面板100在显示时保持黑态的区域，用于设置驱动发光单元发光的电路及走线等必要结构，所述发光区A通常包括用于设置第一颜色发光单元的第一颜色发光区A1、用于设置第二颜色发光单元的第二颜色发光区A2、以及用于设置第三颜色发光单元第三颜色发光区A3，例如，所述第一颜色为蓝色，所述第二颜色为绿色，所述第三颜色为红色；一个所述发光区A对应一个像素，第一颜色发光区A1对应蓝色像素b，第二颜色发光区A2对应绿色像素g，第三颜色发光区A3对应红色像素r，像素可以用r、g、b中任一标号表示，下文不再赘述。
请参阅图4，所述显示面板100包括基板210以及设置于所述基板210上的阳极层910、像素定义层300、发光层400、阴极层920以及封装层800；
具体地，请参阅图4，所述阳极层910包括对应多个所述发光区A设置的多个阳极；所述像素定义层300设置于所述基板210上，包括对应设置于多个所述发光区A的多个第一凹槽G1以及设置于所述非发光区C的第二凹槽G2，一所述第一凹槽G1使得对应的一所述阳极显露；所述发光层400设置于所述像素定义层300以及所述阳极层910上；所述阴极层920设置于所述发光层400上；所述封装层800设置于所述阴极层920远离基板210一侧，即设置于所述发光层400远离所述基板210一侧及所述隔断部700远离所述基板210一侧。
具体地，以叠层器式发光器件（Tandem器件）为例，所述发光层400包括第一发光子层510、位于所述第一发光子层510远离所述基板210一侧的第二发光子层520、及位于所述第一发光子层510与所述第二发光子层520之间的电荷生成层610（CGL）。所述发光层包括共通层600，所述共通层600可以包括所述电荷生成层610。
请参阅图4、图5、图6，所述显示面板100还包括设置于所述非发光区C内的隔断部700，所述隔断部700包括：对应所述第二凹槽G2设置的第一部分710、和设置在所述第一部分710远离所述基板210一侧的第二部分720，所述第二部分720的宽度大于所述第一部分710的宽度，所述第二部分720与所述像素定义层300远离所述基板210一侧的表面间隔设置。
具体的，请参阅图5、图6，所述第二部分720包括第一子部724及位于所述第一子部724外围的第二子部725，所述第一子部724与所述第一部分710连接设置；其中，所述第二子部725与所述像素定义层300间隔设置。
具体的，请参阅图4、图5、图6，至少一所述隔断部700的第二子部725与像素定义层300间隔设置，在形成发光层400例如电荷生成层610时，第二子部725处于悬空状态，增大了电荷生成层610在第二子部725的侧面断开的概率，有更大概率减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图4、图5、图6，所述第一部分710的侧壁与所述像素定义层300接触设置。所述第一部分710的侧壁与所述像素定义层300直接接触，以较简单的制作流程实现在所述第二部分720与所述像素定义层300之间形成的底切结构，增大了所述发光层400的至少部分子膜层在第二子部725的侧面断开的概率，有更大概率减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图13至图16，所述第二部分720与所述像素定义层300远离所述基板210一侧的表面接触设置。在非发光区内设置第二凹槽，将隔断部的第一部分设置于第二凹槽内，从而减小隔断部的整体高度，提高封装层中有机膜层的流平性，提高封装层的封装可靠性，在有效改善因像素偷亮而造成的显示不良的同时还能保证较佳的封装可靠性。
在一些实施例中，请参阅图6，所述显示面板100还包括位于所述非发光区C的第一层1000，所述第一层1000设置在所述像素定义层300远离所述基板210一侧的表面与所述第二部分720之间，且靠近所述第一部分710设置。
在制作过程中，可以通过刻蚀工艺条件的调整，将所述第一层1000设置在所述像素定义层300远离所述基板210一侧的表面与所述第二部分720之间，且靠近所述第一部分710设置，从而有利于对于所述第二部分720有更好的支撑效果，减小第二部分下榻的风险。
在一些实施例中，请参阅图6、图7，所述发光层400在所述隔断部700一侧的端部与所述第一层1000间隔设置。
所述第一层1000的材料可以包括无机材料或金属氧化物材料，金属氧化物材料例如ITO、IZO等任一种或多种的组合，此时，第一层1000可能具有导电性，将所述发光层400（例如第一发光子层510）与所述第一层1000间隔设置，避免产生新的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图7，所述显示面板100还包括位于所述非发光区C的第一层1000，所述显示面板100还包括位于所述隔断部700与所述像素定义层300之间的第一层1000，所述第一层1000至少设置于所述第一部分710的侧壁与第二凹槽G2的侧壁之间。
请参阅图7、图20E、图20F，在制作时，可以通过将第一材料层1001设置于所述第二凹槽G2的侧壁以及像素定义层300的表面上，再形成隔断部700的材料膜层，对隔断部700的材料膜层进行图案化，再对第一材料层1001进行图案化，以去除第二部分720与像素定义层300之间的部分第一材料层1001，形成第一层1000，同时使第二部分720悬空，在后续形成共通层600时，增大共通层600在第二子部725的侧面断开的概率，有更大概率减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图7，所述第一层1000还设置于所述第一部分710的底面与所述第二凹槽G2的底面之间。
通过如图20A至图20F的工艺，在所述第一部分710的底面与所述第二凹槽G2的底面之间设置有所述第一层1000，可以适当垫高所述隔断部700，增加所述第二部分720与所述像素定义层300之间的间隔距离，增大发光层400，例如共通层600在第二子部725的侧面断开的概率，有更大概率减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图7，所述第一层1000还延伸至所述像素定义层300远离所述基板210一侧的表面与所述第二部分720之间，所述发光层400在所述隔断部700一侧的端部与所述第一层1000间隔设置。
在制作过程中，可以通过刻蚀工艺条件的调整，将所述第一层由所述第二凹槽向外延伸至所述第二部分的下方，从而有利于对于所述第二部分有更好的支撑效果，减小第二部分下榻的风险。
在一些实施例中，所述第一材料层，即所述第一层1000的材料包括金属氧化物材料或无机材料。金属氧化物材料包括ITO、IZO等任一种或多种的组合，无机材料例如绝缘材料，包括硅氧化合物、氮硅化合物、氮氧化硅等任一种或多种的组合，第一层1000的作用主要可以用于在图案化后，使第二部分720悬空，在此只做举例，不做具体限定。
在一些实施例中，请参阅图7、图8，所述发光层400与所述第一层1000间隔设置。所述第一层1000的材料可以包括金属氧化物材料，例如ITO、IZO等任一种或多种的组合，此时，第一层1000可能具有导电性，将所述发光层400（例如第一发光子层510）与所述第一层1000间隔设置，避免产生新的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图8，所述第一层1000远离所述基板210一侧的端面与所述基板210的距离，小于所述像素定义层300远离所述基板210一侧的表面与所述基板210的距离。
在对第一材料层1001进行图案化形成第一层1000时，可以通过控制图案化时间，例如蚀刻时间等，刻蚀掉部分位于所述第二凹槽G2的侧壁上的第一材料层1001，以减少所述共通层600与所述第一层1000间接触的风险，所述第一层1000的材料可以包括金属氧化物材料，例如ITO、IZO等任一种或多种的组合，将所述共通层600与所述第一层1000间隔设置，避免产生新的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图5、图14、图16，所述第二面722至所述第一部分710靠近所述基板210一侧的表面的距离（第二距离L2）为0.1μm至4μm。
所述第一面721与所述像素定义层300靠近所述第二部分720的表面之间距离，小于所述第二距离L2即可。该距离可以根据实际情况进行调整，例如制作精度、工艺要求等，在此只做举例，不做具体限定。
在一些实施例中，请参阅图5，在俯视方向上，所述第二子部725远离所述第一子部724的最远端点与所述第一部分710之间的距离（第三距离L3）大于或等于0.2μm，以减少所述第一层1000为金属氧化物时与发光层的至少部分子膜层（例如共通层600）之间的接触的概率，避免产生新的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图5，所述第二部分720包括靠近所述第一部分710的第一面721以及远离所述第一部分710的第二面722，所述第一面721在所述基板210上的正投影位于所述第二面722在所述基板210上的正投影之内。
所述第二部分720的上表面的面积大于或等于所述第二部分720的下表面的面积，第二部分720形成非正梯形的结构，从而有利于发光层的至少部分子膜层（例如共通层600）的膜层在第二部分720的侧面断开，减少和减小漏电流的流通路径，有利于减小像素偷亮的风险，特别的改善显示面板在低灰阶的视觉效果，其中，为方便描述，所述第二部分720的侧面用第一侧面723表示，下文不再赘述。
若将隔断部直接设置在像素定义层上，隔断部凸出于像素定义层的部分过高，在蒸镀过程中会与掩模版（mask）接触划伤隔断部，从而产生微粒（particle），容易使封装层失效，另外在封装时需要更厚的有机材料才能流平，这会增大模组制程风险，导致良率下降；若直接去除隔断部的高度，需要精细的掩模板及增加相关工艺制程，会增加成本，故，请参阅图4，将隔断部700的第一部分710设置于第二凹槽G2内，从而降低隔断部700的整体高度，减少第二部分720的厚度，提高封装层800中有机膜层的流平性，减少有机膜层固化时的气泡产生数量，提高封装层800具有较佳的封装可靠性，在有效改善因像素偷亮而造成的显示不良的同时还能保证较佳的封装可靠性。
在一些实施例中，请参阅图图5，所述第一面721在所述基板210上的正投影的外轮廓与所述第二面722在所述基板210上的正投影的外轮廓间隔设置。
利用隔断部700的第二部分720呈上宽下窄的倒梯形结构，更有利于所述发光层400的至少部分子膜层在第二部分720的侧面断开，从而减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图5，所述第二部分720的侧面与所述第一面721的夹角θ为100°至120°。
所述第二部分720的侧面与所述像素定义层300形成底切结构，从而增大所述发光层400的至少部分子膜层在所述第二部分720的侧面位置断开的概率，所述第二部分720的侧面与所述基板210的夹角过小，所述发光层400的至少部分子膜层在所述第二部分720的侧面的位置断开的概率会减小；所述第二部分720的侧面与所述基板210的夹角过大，形成隔断部700的工艺难度增加，成本增加。所述第二部分720的侧面与所述第一面721的夹角θ为100°至120°，既可以提高所述发光层400的至少部分子膜层在第二部分720的侧面断开的概率，又方便制作形成。
在一些实施例中，请参阅图14，在所述显示面板100的俯视方向上，对应同一所述第二部分720的同一侧面，所述第二面722远离所述第一子部724的最远端点与所述第一面721远离所述第一子部724的最远端点之间的距离（第一距离L1）为0.1μm至2μm。易于理解，L1的限定，同样可以应用于图4至图12中的任一实施例。
所述第二部分720的侧面与所述像素定义层300形成底切结构，从而增大所述发光层400的至少部分子膜层在所述第二部分720的侧面位置断开的概率，第一距离L1过小，所述发光层400的至少部分子膜层在所述第二部分720的侧面的位置断开的概率会减小；第一距离L1过大，形成隔断部700的工艺难度增加，成本增加。第一距离L1为0.1μm至2μm，既可以提高所述发光层400的至少部分子膜层在第二部分720的侧面断开的概率，又方便制作形成。
在一些实施例中，所述隔断部700的材料可以为负性光阻，由于负性光阻的特性，方便形成第二部分720呈上宽下窄的倒梯形结构。
在一些实施例中，请参阅图4，所述发光层400在所述第二部分720的侧面间隔设置。易于理解，所述发光层400在所述第二部分720的侧面间隔设置的限定，同样可以应用于图4至图12中的任一实施例。
所述发光层400的任一膜层在第二部分720的侧面位置都是断开的，最大程度减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，所述第一发光子层510包括第一发光材料层511及位于所述第一发光材料层511靠近所述基板210一侧的空穴注入传输层620（HITL）；其中，所述第一发光材料层511在所述隔断部700处断开设置，所述空穴注入传输层620在所述隔断部700处断开设置。
所述空穴注入传输层620及所述第一发光材料层511是产生漏电流的路径，将该两条路径进行断开，以减少漏电流的漏电路径，减小像素偷亮的风险。具体的，所述共通层600还可以包括所述空穴注入传输层620。
易于理解，所述第一发光材料层511及所述空穴注入传输层620在所述第二部分720的侧面间隔设置的实施例可以适用于单(Single)器件，在此只做举例，不作具体限定。
在一些实施例中，请参阅图4，所述发光层400包括第一发光子层510、位于所述第一发光子层510远离所述基板210一侧的第二发光子层520、及位于所述第一发光子层510与所述第二发光子层520之间的电荷生成层610；其中，所述电荷生成层610在隔断部700处断开设置。
在叠层器式发光层（Tandem器件）中，在第一发光子层510与第二发光子层520之间设置有电荷生成层610，请参阅图12，相比于所述空穴注入传输层620及所述第一发光材料层511，电荷生成层610中较容易产生漏电流，以使相邻像素偷亮，将Tandem器件的漏电流主要路径断开，以减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图12，所述共通层600还包括位于所述第一发光材料层511靠近所述基板210一侧的空穴注入传输层620；其中，所述第一发光材料层511在所述第二部分720的侧面间隔设置，所述空穴注入传输层620在所述第二部分720的侧面间隔设置。
易于理解，所述第一发光材料层511及所述空穴注入传输层620在所述第二部分720的侧面间隔设置的实施例可以适用于叠层(Tandem)器件，在此只做举例，不作具体限定。所述空穴注入传输层620及所述第一发光材料层511均是产生漏电流的路径，将该两条路径进行断开，以减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，在叠层(Tandem)器件中，可以只将电荷生成层610在所述第二部分720的侧面间隔设置；或者，在叠层(Tandem)器件中，可以将电荷生成层610及所述第一发光材料层在所述第二部分720的侧面间隔设置；或者，在叠层(Tandem)器件中，可以将电荷生成层610、所述第一发光材料层及所述空穴注入传输层620均在所述第二部分720的侧面间隔设置。在此只做举例，不作具体限定。
在一些实施例中，请参阅图4，所述显示面板100还包括阳极层910和阴极层920，所述阳极层910设置于所述基板210上，所述像素定义层300暴露出部分所述阳极层910，所述阴极层920设置于所述发光层400远离所述基板210一侧。
在一些实施例中，请参阅图4，所述阴极层920在所述隔断部700处连续设置。通过调整隔断部700的高度、第二部分720与像素定义层300之间的间隔距离、及第二部分720的侧面的坡度等参数，所述阴极层920在所述隔断部700处连续设置，避免阴极层断裂设置影响电学性能，减小阴极信号无法传输至发光区A内的风险。
在一些实施例中，请参阅图15，所述阴极层920在所述第二部分720的侧面间隔设置。通过调整隔断部700的高度、第二部分720与像素定义层300之间的间隔距离、及第二部分720的侧面的坡度等参数，可以使阴极层920在第二部分720的侧面断开；若想使阴极层920在第二部分720的侧面是连接设置的，需要控制工艺参数，控制第二部分720的厚度，这样会增加工艺成本；故可以适当放宽第二部分720的厚度的要求，以减少成本，阴极层920在第二部分720的侧面呈断开设置。易于理解，所述阴极层920在所述第二部分720的侧面间隔设置的限定，同样可以应用于图4至图12中的任一实施例。
在一些实施例中，所述显示面板100还包括阴极层920，所述阴极层920设置于所述发光层400远离所述基板210一侧。所述共通层600还可以包括位于所述阴极层920与所述第二发光子层520之间的电子传输层。
在一些实施例中，所述电子传输层可以在所述第二部分720的侧面间隔设置。
在一些实施例中，所述电子传输层可以在所述第二部分720的侧面连续设置。在此只做举例，不对电子传输层作具体限定。
在一些实施例中，请参阅图1，所述显示面板100包括多个像素，所述像素对应所述发光区A设置，所述阴极层920在所述第二部分720的侧面间隔设置，对应所述第二凹槽G2围绕一所述像素呈非闭环设置。
当阴极层920在第二部分720的侧面断开时，对应第二凹槽G2不能围绕像素呈闭环设置，以避免发光区A内的阴极层920成孤岛，避免阴极信号无法传输至发光区A内的技术问题。
在一些实施例中，请参阅图4、图5、图6，所述显示面板100还包括位于所述基板210一侧的驱动电路层220和位于所述驱动电路层220上的平坦层230，所述平坦层230位于所述驱动电路层220远离基板210一侧的表面上，所述第二凹槽G2贯穿所述像素定义层300，以使平坦层230暴露，从而所述第一部分710可以与所述平坦层230接触。
所述第二凹槽G2的深度越深，所述第二凹槽G2的体积越大，填入所述第二凹槽G2的所述第一部分710的体积也越大，从而降低所述第二部分720的厚度，减小隔断部700的整体高度，提高封装层800中有机膜层的流平性，提高封装层800具有较佳的封装可靠性；同时，所述第二凹槽G2的深度越深，增大了像素定义层300与第一部分710的接触面积，提高像素定义层300与隔断部700之间的粘附力，减少隔断部700脱落的风险，提高封装层800中有机膜层的流平性，提高封装层800具有较佳的封装可靠性。
在一些实施例中，请参阅图4，所述驱动电路层220可以包括有源层221、栅极层222、源漏极层223、及位于各需要绝缘设置的相邻膜层之间的绝缘层。
具体的，请参阅图4，驱动电路层220的结构可以为顶栅设计，也可以为底栅设计，在此只做举例，不做具体限定。
在一些实施例中，所述第二凹槽G2贯穿所述像素定义层300以及使部分所述平坦层230形成第一凹陷，所述第一凹陷中填充有所述第一部分710。进一步增大第一部分710与平坦层230之间的接触面积，以提高基板210与隔断部700之间的粘附力，减少隔断部700脱落的风险，提高封装层800中有机膜层的流平性，提高封装层800具有较佳的封装可靠性。
在一些实施例中，请参阅图9，所述隔断部700还包括设置于所述第二部分720远离所述基板210一侧的第三凹槽G3，所述第三凹槽G3内设置有所述发光层400的至少部分子膜层。
在所述隔断部700的所述第二部分720上进行挖槽，以形成第三凹槽G3，可以提高所述发光层400的至少部分子膜层在第三凹槽G3内的断裂概率，从而减少漏电流的漏电路径形成的风险，减小像素偷亮的风险。
在一些实施例中，请参阅图10，所述发光层400的至少部分子膜层在所述第三凹槽G3内间断设置。
所述发光层400的至少部分子膜层在第三凹槽G3内断裂，优选的为电荷生成层610，次优选的为所述第一发光材料层511或/和空穴注入传输层620，从而减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图11，所述第三凹槽G3贯穿所述第二部分720及所述第一部分710。
所述第三凹槽G3的深度越深，所述发光层400的至少部分子膜层在第三凹槽G3内断裂的概率越大，从而有更大概率减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图11，所述第三凹槽G3贯穿所述第二部分720、所述第一部分710及所述像素定义层300，所述发光层400的至少部分子膜层通过所述第三凹槽G3与所述平坦层230接触设置。
在一些实施例中，请参阅图11，所述显示面板100还包括位于所述基板210一侧的驱动电路层220和位于所述驱动电路层220上的平坦层230，所述平坦层230位于所述驱动电路层220远离基板210一侧的表面上，所述第三凹槽G3贯穿所述第二部分720、所述第一部分710及所述像素定义层300，以使平坦层230暴露，从而所述发光层400的至少部分子膜层可以与所述平坦层230接触。
在一些实施例中，所述第三凹槽G3贯穿所述第二部分720、所述第一部分710及所述像素定义层300以及使部分所述平坦层230形成第二凹陷，所述第二凹陷中填充有所述共通层600。增大所述第三凹槽G3的深度，以使所述发光层400的至少部分子膜层在第三凹槽G3内断裂的概率增大，有更大概率减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图9、图11，所述显示面板100还包括阳极层910和阴极层920，所述阳极层910设置于所述基板210上，所述像素定义层300暴露出部分所述阳极层910，所述阴极层920设置于所述发光层400远离所述基板210一侧；其中，所述第三凹槽G3内设置有所述阴极层920。
阴极层920也设置于所述第三凹槽G3内，可以填充所述第三凹槽G3，避免凹槽过深，减小封装层800的覆盖难度，减少封装失效的风险。
在一些实施例中，请参阅图1至图3，相邻两所述发光区A之间设置有至少一个所述第二凹槽G2，至少部分所述第二凹槽G2沿相邻的一所述发光区A边缘延伸设置。
例如，请参阅图1，在第二颜色发光区A2与第三颜色发光区A3之间设置有一个第二凹槽G2，在第二颜色发光区A2与第一颜色发光区A1之间设置有两个第二凹槽G2，易于理解，相邻两所述发光区A之间的数量可以为三个甚至更多，相邻两所述发光区A之间的数量可以根据空间占位等实际情况进行调整，在此不做具体限定。
例如，所述第二颜色发光区A2为椭圆形，则将所述第二颜色发光区A2与所述第一颜色发光区A1之间的所述第二凹槽G2设置为沿相邻所述第二颜色发光区A2边缘延伸设置的曲线型凹槽，如此便可使得位于所述第二颜色发光区A2与所述第一颜色发光区A1之间的所述第二凹槽G2向靠近位于所述第二颜色发光区A2与所述第三颜色发光区A3之间的所述第二凹槽G2的方向进一步延伸，从而减小前述两个所述第二凹槽G2之间的间距，进而缩窄所述共通层600在此处的连通通道，以使得此处的横向漏流的大小保持在目标值以下。
此处仅是根据该特定的像素排布进行示例性的说明，在实际应用中，根据具体的像素排布结构，所述第二凹槽G2除了为上述的曲线型凹槽以外，还可为波浪形凹槽，折线形凹槽等；各像素、各颜色发光区的形状仅示例性的说明，在实际应用中，根据具体情况进行调整。
在一些实施例中，请参阅图2，所述显示面板100包括多个像素，所述像素对应所述发光区A设置，至少一所述像素外围有呈闭环设置的所述第二凹槽G2。
围绕像素闭环设置的所述第二凹槽G2，可以增加共通层在第二部分720的侧面断裂的概率，从而减少漏电流的漏电路径形成的风险，减小像素偷亮的风险。
当阴极层920在第二部分720的侧面断开时，对应第二凹槽G2不能围绕像素呈闭环设置，以避免发光区A内的阴极层920成孤岛，避免阴极信号无法传输至发光区A内的技术问题。
在一些实施例中，请参阅图4，所述显示面板100还包括位于所述封装层800远离所述基板210一侧的彩膜层810，所述彩膜层810包括多个色阻820。所述色阻820的颜色和像素的颜色对应。
本申请通过在非发光区设置隔断部，隔断部的第一部分设置于第二凹槽内，隔断部的第二部分比第一部分宽，同时隔断部的第二部分与像素定义层之间间隔设置，有利于发光层的至少部分子膜层在第二部分的侧面处断开，从而减少漏电流的漏电路径，减小像素偷亮的风险；同时，在非发光区内设置第二凹槽，将隔断部的第一部分设置于第二凹槽内，从而减小隔断部的整体高度，提高封装层中有机膜层的流平性，提高封装层的封装可靠性，在有效改善因像素偷亮而造成的显示不良的同时还能保证较佳的封装可靠性。
请参阅图17，本申请实施例提供了一种显示面板100的制作方法，请参阅图18，所述显示面板100包括多个间隔设置的发光区A以及位于各所述发光区A之间的非发光区C，所述显示面板100的制作方法包括：
S100、提供一基板210，在所述基板210上形成像素定义层300，包括对应形成于所述发光区A的第一凹槽G1以及形成于所述非发光区C的第二凹槽G2。
S200、在所述基板210和所述像素定义层300上形成隔断材料层701。
S300、利用图案化处理，将所述隔断材料层701形成设置于所述非发光区C且包括第一部分710和第二部分720的隔断部700，所述第一部分710对应所述第二凹槽G2设置，所述第二部分720设置在所述第一部分710远离所述基板210的一侧，所述第二部分720的宽度大于所述第一部分710的宽度，所述第二部分720与所述像素定义层300远离所述基板210一侧的表面间隔设置。
S400、在所述基板210以及所述像素定义层300上形成发光层400，所述发光层400包括多个叠层设置的子膜层，所述发光层400的至少部分子膜层在所述隔断部700处断开。
本申请通过在非发光区设置隔断部，隔断部的第一部分设置于第二凹槽内，隔断部的第二部分比第一部分宽，同时隔断部的第二部分与像素定义层之间间隔设置，有利于发光层的至少部分子膜层在第二部分的侧面处断开，从而减少漏电流的漏电路径，减小像素偷亮的风险；同时，在非发光区内设置第二凹槽，将隔断部的第一部分设置于第二凹槽内，从而减小隔断部的整体高度，提高封装层中有机膜层的流平性，提高封装层的封装可靠性，在有效改善因像素偷亮而造成的显示不良的同时还能保证较佳的封装可靠性。
现结合具体实施例对本申请的技术方案进行描述。
本实施例中，所述显示面板100的制作方法包括：
S100、提供一基板210，在所述基板210上形成像素定义层300，包括对应形成于所述发光区A的第一凹槽G1以及形成于所述非发光区C的第二凹槽G2，请参阅图19A、图19C。
在一些实施例中，在后续步骤形成的所述隔断部700的所述第二部分720包括第一子部724及位于所述第一子部724外围的第二子部725，所述第一子部724与所述第一部分710连接设置。具体的，第二子部725与像素定义层300可以接触设置，或者第二子部725与像素定义层300间隔设置，以在形成发光层400时，第二子部725处于悬空状态，故根据不同的形成工艺，步骤S100可以包括：
S110a、提供一基板210，在所述基板210上形成像素定义层300，包括对应形成于所述发光区A的第一凹槽G1，请参阅图19A。
S120a、在所述基板210和所述像素定义层300上形成第一材料层1001，请参阅图19B。
S130a、利用图案化处理，在所述像素定义层300上形成于所述非发光区C的第二凹槽G2，以及将所述第二凹槽G2上对应的所述第一材料层1001去除，请参阅图19C。
在一些实施例中，根据不同的形成工艺，步骤S100可以包括：
S110b、提供一基板210，在所述基板210上形成像素定义层300，包括对应形成于所述发光区A的第一凹槽G1，请参阅图20A。
S120b、利用图案化处理，在所述像素定义层300上形成于所述非发光区C的第二凹槽G2，请参阅图20B。
S130b、在所述基板210和所述像素定义层300上形成第一材料层1001，请参阅图20C。
在一些实施例中，所述第一材料层1001的材料包括金属氧化物材料或无机材料。金属氧化物材料包括ITO、IZO等任一种或多种的组合，无机材料例如绝缘材料，包括硅氧化合物、氮硅化合物、氮氧化硅等任一种或多种的组合。
在一些实施例中，根据不同的形成工艺，步骤S100可以包括：
S110c、提供一基板210，在所述基板210上形成像素定义层300，包括对应形成于所述发光区A的第一凹槽G1，请参阅图21A。
S120c、利用图案化处理，在所述像素定义层300上形成于所述非发光区C的第二凹槽G2，请参阅图21B。
在一些实施例中，请参阅图21A，提供一基板210的步骤可以包括提供一基板210；在所述基板210上形成驱动电路层220；在所述驱动电路层220上形成平坦层230；在所述平坦层230上形成阳极层910。
在一些实施例中，步骤S110c和S120c可以一步形成。
S200、在所述基板210和所述像素定义层300上形成隔断材料层701，请参阅图19D、图20D、图21C。
在一些实施例中，所述隔断材料层701的材料可以为负性光阻，方便形成第二部分720呈上宽下窄的倒梯形结构。
S300、利用图案化处理，将所述隔断材料层701形成设置于所述非发光区C且包括第一部分710和第二部分720的隔断部700，所述第一部分710对应所述第二凹槽G2设置，所述第二部分720设置在所述第一部分710远离所述基板210的一侧，所述第二部分720的宽度大于所述第一部分710的宽度，所述第二部分720与所述像素定义层300远离所述基板210一侧的表面间隔设置，请参阅图19E、图20E。
在一些实施例中，所述第一面721在所述基板210上的正投影的外轮廓与所述第二面722在所述基板210上的正投影的外轮廓间隔设置，请参阅图4、图5。
利用隔断部700的第二部分720呈上宽下窄的倒梯形结构，更有利于共通层600的膜层在第二部分720的侧面断开，从而减少漏电流的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图5，所述第二部分720的侧面与所述基板210的夹角为100°至120°。
所述第二部分720的侧面与所述像素定义层300形成底切结构，从而增大共通层600在所述第二部分720的侧面位置断开的概率，所述第二部分720的侧面与所述基板210的夹角过小，发光层400在所述第二部分720的侧面的位置断开的概率会减小；所述第二部分720的侧面与所述基板210的夹角过大，形成隔断部700的工艺难度增加，成本增加。所述第二部分720的侧面与所述基板210的夹角为100°至120°，既可以提高发光层400在第二部分720的侧面断开的概率，又方便制作形成。
S400、在所述基板210以及所述像素定义层300上形成发光层400，所述发光层400包括多个叠层设置的子膜层，所述发光层400的至少部分子膜层在所述隔断部700处断开，请参阅图4、图5。
在一些实施例中，请参阅图5，所述第二部分720包括第一子部724及位于所述第一子部724外围的第二子部725，所述第一子部724与所述第一部分710连接设置。
在一些实施例中，根据不同的形成工艺，步骤S400可以包括：
S410a、去除所述第一材料层1001，形成所述第二子部725与所述像素定义层300间隔设置，请参阅图19F。
在一些实施例中，请参阅图19F，去除所述第一材料层1001，形成所述第二子部725与所述像素定义层300间隔设置，以使第二子部725处于悬空状态。
S420a、在所述基板210以及所述像素定义层300上形成发光层400，所述发光层400包括多个叠层设置的子膜层，所述发光层400的至少部分子膜层在所述隔断部700处断开，请参阅图4、图5。
在一些实施例中，根据不同的形成工艺，步骤S400可以包括：
S410b、去除所述第二凹槽G2外的所述第一材料层1001，形成位于所述第二凹槽G2内的第一层1000，请参阅图20F。
在一些实施例中，去除所述第二凹槽G2外的所述第一材料层1001，形成所述第二子部725与所述像素定义层300间隔设置，以使第二子部725处于悬空状态，请参阅图20F。
在一些实施例中，请参阅图8，所述第一层1000远离所述基板210一侧的端面与所述基板210的距离，小于所述像素定义层300远离所述基板210一侧的表面与所述基板210的距离。
在对第一材料层1001进行图案化形成第一层1000时，可以通过控制图案化时间，例如蚀刻时间等，刻蚀掉部分位于所述第二凹槽G2的侧壁上的第一材料层1001，以减少所述共通层600与所述第一层1000间接触的风险，所述第一层1000的材料可以包括金属氧化物材料，例如ITO、IZO等任一种或多种的组合，将所述共通层600与所述第一层1000间隔设置，避免产生新的漏电路径，减小像素偷亮的风险。
在一些实施例中，请参阅图8，在俯视方向上，所述第二子部725远离所述第一子部724的最远端点与所述第一部分710之间的距离（第三距离L3）大于或等于0.2μm，以减少所述第一层1000为金属氧化物时与共通层600之间的接触的概率，避免产生新的漏电路径，减小像素偷亮的风险。
S420b、在所述基板210以及所述像素定义层300上形成发光层400，所述发光层400包括多个叠层设置的子膜层，所述发光层400的至少部分子膜层在所述隔断部700处断开，请参阅图7、图8。
在一些实施例中，根据不同的形成工艺，步骤S400可以包括：
S410c、在所述基板210以及所述像素定义层300上形成发光层400，所述发光层400包括多个叠层设置的子膜层，所述发光层400的至少部分子膜层在所述隔断部700处断开，请参阅图15、图16。
在一些实施例中，所述显示面板100的制作方法还包括：
S500、在所述发光层400上形成阴极层920，请参阅图4。
在一些实施例中，所述阴极层920连续设置，请参阅图4。
在一些实施例中，请参阅图15，所述阴极层920在所述第二部分720的侧面间隔设置。通过调整所述第二部分720的厚度，可以使阴极层920在第二部分720的侧面断开；若想使阴极层920在第二部分720的侧面是连接设置的，需要控制工艺参数，控制第二部分720的厚度，这样会增加工艺成本；故可以适当放宽第二部分720的厚度的要求，以减少成本，阴极层920在第二部分720的侧面呈断开设置。
在一些实施例中，请参阅图2，所述显示面板100包括多个像素，所述像素对应所述发光区A设置，所述阴极层920在所述第二部分720的侧面间隔设置，对应所述第二凹槽G2围绕一所述像素呈非闭环设置。
当阴极层920在第二部分720的侧面断开时，对应第二凹槽G2不能围绕像素呈闭环设置，以避免发光区A内的阴极层920成孤岛，避免阴极信号无法传输至发光区A内的技术问题。
S600、在所述阴极层920上形成封装层800，请参阅图4。
在一些实施例中，所述封装层包括第一无机层、第二无机层、及位于所述第一无机层与所述第二无机层之间的有机膜层。
本申请通过在非发光区设置隔断部，隔断部的第一部分设置于第二凹槽内，隔断部的第二部分比第一部分宽，同时隔断部的第二部分与像素定义层之间间隔设置，有利于发光层的至少部分子膜层在第二部分的侧面处断开，从而减少漏电流的漏电路径，减小像素偷亮的风险；同时，在非发光区内设置第二凹槽，将隔断部的第一部分设置于第二凹槽内，从而减小隔断部的整体高度，提高封装层中有机膜层的流平性，提高封装层的封装可靠性，在有效改善因像素偷亮而造成的显示不良的同时还能保证较佳的封装可靠性。
请参阅图22，本发明实施例还提供了一种显示装置10，包括如任一上述的显示面板100。
所述显示面板100的具体结构请参阅任一上述显示面板100的实施例及附图，在此不再赘述。
本实施例中，请参阅图22，所述显示装置10还包括装置主体20，所述装置主体20与所述显示面板100组合为一体。
本实施例中，所述装置主体20可以包括中框、框胶等，所述显示装置10可以为手机、平板、电视等显示终端，在此不做限定。
本申请实施例公开了一种显示面板及显示装置；显示面板包括发光区和非发光区，显示面板包括基板、像素定义层、发光层和隔断部，像素定义层包括第一凹槽和设置于非发光区内的第二凹槽，隔断部包括连接设置的第一部分和第二部分，第一部分对应第二凹槽，第二部分的宽度大于第一部分的宽度，第二部分与像素定义层远离基板一侧的表面间隔设置；本申请通过在非发光区设置隔断部，隔断部的第一部分设置于第二凹槽内，隔断部的第二部分比第一部分宽，同时隔断部的第二部分与像素定义层之间间隔设置，有利于发光层的至少部分子膜层在第二部分的侧面处断开，从而减少漏电流的漏电路径，减小像素偷亮的风险。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，其中，包括多个间隔设置的发光区以及位于各所述发光区之间的非发光区，所述显示面板包括：
    基板；
    像素定义层，设置于所述基板的一侧，包括对应设置于所述发光区内的第一凹槽以及设置于所述非发光区内的第二凹槽；
    多个隔断部，设置于所述非发光区内且位于所述像素定义层远离所述基板的一侧，所述隔断部包括：对应所述第二凹槽设置的第一部分、和设置在所述第一部分远离所述基板一侧的第二部分，所述第二部分的宽度大于所述第一部分的宽度，所述第二部分与所述像素定义层远离所述基板一侧的表面间隔设置；
    发光层，设置在所述像素定义层和所述隔断部远离所述基板的一侧，所述发光层包括对应所述第一凹槽设置的像素，所述发光层包括多个叠层设置的子膜层，所述发光层的至少部分子膜层在所述隔断部处断开设置。
  2. 根据权利要求1所述的显示面板，其中，所述第一部分的侧壁与所述像素定义层接触设置。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括位于所述非发光区的第一层，所述第一层设置在所述像素定义层远离所述基板一侧的表面与所述第二部分之间，且靠近所述第一部分设置。
  4. 根据权利要求3所述的显示面板，其中，所述发光层在所述隔断部一侧的端部与所述第一层间隔设置。
  5. 根据权利要求1所述的显示面板，其中，所述显示面板还包括位于所述非发光区的第一层，所述第一层至少设置于所述第一部分的侧壁与所述第二凹槽的侧壁之间。
  6. 根据权利要求5所述的显示面板，其中，所述第一层还设置于所述第一部分的底面与所述第二凹槽的底面之间。
  7. 根据权利要求5所述的显示面板，其中，所述第一层还延伸至所述像素定义层远离所述基板一侧的表面与所述第二部分之间，所述发光层在所述隔断部一侧的端部与所述第一层间隔设置。
  8. 根据权利要求1所述的显示面板，其中，所述发光层包括第一发光子层、位于所述第一发光子层远离所述基板一侧的第二发光子层、及位于所述第一发光子层与所述第二发光子层之间的电荷生成层；
    其中，所述电荷生成层在所述隔断部处断开设置。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板还包括阳极层和阴极层，所述阳极层设置于发光层靠近所述基板一侧，所述阴极层设置于所述发光层远离所述基板一侧；
    其中，所述阴极层在所述隔断部处连续设置。
  10. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    驱动电路层，设置在所述基板和所述像素定义层之间；
    平坦层，设置在所述驱动电路层和所述像素定义层之间；
    其中，所述第二凹槽贯穿所述像素定义层，所述第一部分与所述平坦层接触设置。
  11. 根据权利要求1所述的显示面板，其中，所述隔断部还包括设置于所述第二部分远离所述基板一侧的第三凹槽，所述第三凹槽内设置有所述发光层的至少部分子膜层。
  12. 根据权利要求11所述的显示面板，其中，所述发光层的至少部分子膜层在所述第三凹槽内间断设置。
  13. 根据权利要求12所述的显示面板，其中，所述第三凹槽贯穿所述第二部分及所述第一部分。
  14. 根据权利要求1所述的显示面板，其中，所述第二部分包括靠近所述第一部分的第一面以及远离所述第一部分的第二面，所述第一面在所述基板上的正投影位于所述第二面在所述基板上的正投影之内。
  15. 根据权利要求14所述的显示面板，其中，所述第一面在所述基板上的正投影的外轮廓与所述第二面在所述基板上的正投影的外轮廓间隔设置。
  16. 根据权利要求1所述的显示面板，其中，相邻两所述发光区之间设置有至少一个所述第二凹槽，至少部分所述第二凹槽沿相邻的一所述发光区边缘延伸设置。
  17. 根据权利要求16所述的显示面板，其中，至少一所述像素外围有呈闭环设置的所述第二凹槽。
  18. 一种显示装置，其中，所述显示装置包括显示面板，所述显示面板包括多个间隔设置的发光区以及位于各所述发光区之间的非发光区，所述显示面板包括：
    基板；
    像素定义层，设置于所述基板的一侧，包括对应设置于所述发光区内的第一凹槽以及设置于所述非发光区内的第二凹槽；
    多个隔断部，设置于所述非发光区内且位于所述像素定义层远离所述基板的一侧，所述隔断部包括：对应所述第二凹槽设置的第一部分、和设置在所述第一部分远离所述基板一侧的第二部分，所述第二部分的宽度大于所述第一部分的宽度，所述第二部分与所述像素定义层远离所述基板一侧的表面间隔设置；
    发光层，设置在所述像素定义层和所述隔断部远离所述基板的一侧，所述发光层包括对应所述第一凹槽设置的像素，所述发光层包括多个叠层设置的子膜层，所述发光层的至少部分子膜层在所述隔断部处断开设置。
  19. 根据权利要求18所述的显示装置，其中，所述第一部分的侧壁与所述像素定义层接触设置。
  20. 根据权利要求18所述的显示装置，其中，所述显示面板还包括位于所述非发光区的第一层，所述第一层至少设置于所述第一部分的侧壁与所述第二凹槽的侧壁之间。
PCT/CN2023/108079 2023-06-15 2023-07-19 显示面板及显示装置 Ceased WO2024254937A1 (zh)

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