WO2024239366A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2024239366A1
WO2024239366A1 PCT/CN2023/097609 CN2023097609W WO2024239366A1 WO 2024239366 A1 WO2024239366 A1 WO 2024239366A1 CN 2023097609 W CN2023097609 W CN 2023097609W WO 2024239366 A1 WO2024239366 A1 WO 2024239366A1
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Prior art keywords
electrode
shielding
sub
substrate
shielding electrode
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2023/097609
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English (en)
French (fr)
Inventor
严允晟
刘净
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TCL China Star Optoelectronics Technology Co Ltd
Huizhou China Star Optoelectronics Display Co Ltd
Original Assignee
TCL China Star Optoelectronics Technology Co Ltd
Huizhou China Star Optoelectronics Display Co Ltd
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Application filed by TCL China Star Optoelectronics Technology Co Ltd, Huizhou China Star Optoelectronics Display Co Ltd filed Critical TCL China Star Optoelectronics Technology Co Ltd
Priority to US18/557,946 priority Critical patent/US20260118723A1/en
Publication of WO2024239366A1 publication Critical patent/WO2024239366A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the field of display, and in particular to an array substrate and a display panel.
  • the transparent electrode layer overlaps with the data line, which can shield the electric field of the data line, and the transparent electrode layer is arranged on the whole surface and forms a large transparent storage capacitor with the pixel electrode layer, which can greatly improve the transmittance and storage capacitance.
  • the transparent electrode layer arranged on the whole surface has an electric field sealing effect, and a lateral electric field is formed between it and the pixel electrode, resulting in that the liquid crystal tilting state cannot reach the set ideal value, thereby reducing the liquid crystal efficiency.
  • the embodiments of the present application provide an array substrate and a display panel, which can solve the technical problem that a lateral electric field is formed between a transparent electrode layer disposed on the entire surface of an existing array substrate and pixel electrodes, resulting in reduced liquid crystal efficiency.
  • an array substrate comprising:
  • a first metal layer located on the substrate and including a common signal line
  • a second metal layer located on a side of the first metal layer away from the substrate and comprising a data line;
  • a pixel electrode layer located on a side of the second metal layer away from the first metal layer and comprising a plurality of pixel electrodes
  • a shielding layer located between the second metal layer and the pixel electrode layer and comprising a plurality of first shielding electrodes and second shielding electrodes arranged at intervals, wherein the first shielding electrodes and the pixel electrodes have the same potential, and the second shielding electrodes and the common signal line have the same potential;
  • the orthographic projection of the first shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the data line on the substrate and at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.
  • the array substrate comprises a plurality of pixel electrode regions and at least one driving circuit region located on one side of the pixel electrode region, and the pixel electrode is located in the pixel electrode region;
  • the pixel electrode layer further includes a connecting electrode connected to the pixel electrode and extending from the pixel electrode region to the driving circuit region, and the first shielding electrode is electrically connected to the connecting electrode in the driving circuit region.
  • the first shielding electrode includes a first sub-shielding electrode and a second sub-shielding electrode extending from one side of the first sub-shielding electrode; the first sub-shielding electrode is located in the pixel electrode area, the second sub-shielding electrode is at least located in the driving circuit area, and the second sub-shielding electrode is electrically connected to the connecting electrode in the driving circuit area.
  • the second metal layer also includes a source and a drain arranged at intervals and located in the driving circuit area; the source is electrically connected to the data line, the second sub-shielding electrode is electrically connected to the drain through a first via, the connecting electrode is overlapped with the second sub-shielding electrode in the first via through a second via, and the first via is connected to the second via.
  • the array substrate further includes:
  • An insulating layer disposed between the shielding layer and the pixel electrode layer;
  • the first via hole penetrates the color resist layer, and the second via hole penetrates the insulating layer.
  • the second shielding electrode includes a third sub-shielding electrode and a fourth sub-shielding electrode extending in a direction parallel to and connected to the data line, the third sub-shielding electrode is located on one side of the pixel electrode area, and the fourth sub-shielding electrode is located on one side of the driving circuit area; the orthographic projection of the third sub-shielding electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.
  • the first metal layer further includes a scan line, and the scan line is arranged to cross the data line;
  • the second shielding electrode further includes a fifth sub-shielding electrode parallel to the scanning line and connected to the third sub-shielding electrode, the third sub-shielding electrode, the fourth sub-shielding electrode and the fifth sub-shielding electrode are connected to form a grid, and each of the first shielding electrodes is located in a grid;
  • the orthographic projection of the fifth sub-shielding electrode on the substrate covers the orthographic projection of the scanning line on the substrate.
  • the width range of the portion where the orthographic projection of the third sub-shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate is greater than 5 micrometers.
  • the ratio of the area of the first sub-shielding electrode to the area of the pixel electrode is in the range of 30%-85%.
  • the minimum distance between the third sub-shielding electrode and the first sub-shielding electrode is in the range of 4 micrometers to 10 micrometers.
  • the array substrate further includes a third via hole, and the second shielding electrode is electrically connected to the common signal line through the third via hole.
  • the present application provides a display panel, comprising:
  • a liquid crystal layer located between the array substrate and the color filter substrate;
  • the array substrate comprises:
  • a first metal layer located on the substrate and including a common signal line
  • a second metal layer located on a side of the first metal layer away from the substrate and comprising a data line;
  • a pixel electrode layer located on a side of the second metal layer away from the first metal layer and comprising a plurality of pixel electrodes
  • a shielding layer located between the second metal layer and the pixel electrode layer and comprising a plurality of first shielding electrodes and second shielding electrodes arranged at intervals, wherein the first shielding electrodes and the pixel electrodes have the same potential, and the second shielding electrodes and the common signal line have the same potential;
  • the orthographic projection of the first shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the data line on the substrate and at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.
  • the array substrate includes a plurality of pixel electrode regions and at least one driving circuit region located on one side of the pixel electrode region, and the pixel electrode is located in the pixel electrode region;
  • the pixel electrode layer further includes a connecting electrode connected to the pixel electrode and extending from the pixel electrode region to the driving circuit region, and the first shielding electrode is electrically connected to the connecting electrode in the driving circuit region.
  • the first shielding electrode includes a first sub-shielding electrode and a second sub-shielding electrode extending from one side of the first sub-shielding electrode; the first sub-shielding electrode is located in the pixel electrode area, the second sub-shielding electrode is at least located in the driving circuit area, and the second sub-shielding electrode is electrically connected to the connecting electrode in the driving circuit area.
  • the second metal layer also includes a source and a drain that are spaced apart and located in the driving circuit area; the source is electrically connected to the data line, the second sub-shielding electrode is electrically connected to the drain through a first via, the connecting electrode is overlapped with the second sub-shielding electrode in the first via through a second via, and the first via is connected to the second via.
  • the array substrate further includes:
  • An insulating layer disposed between the shielding layer and the pixel electrode layer;
  • the first via hole penetrates the color resist layer, and the second via hole penetrates the insulating layer.
  • the second shielding electrode includes a third sub-shielding electrode and a fourth sub-shielding electrode extending in a direction parallel to and connected to the data line, the third sub-shielding electrode is located on one side of the pixel electrode area, and the fourth sub-shielding electrode is located on one side of the driving circuit area; the orthographic projection of the third sub-shielding electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.
  • the first metal layer further includes a scan line, and the scan line is arranged to cross the data line;
  • the second shielding electrode further includes a fifth sub-shielding electrode parallel to the scanning line and connected to the third sub-shielding electrode, the third sub-shielding electrode, the fourth sub-shielding electrode and the fifth sub-shielding electrode are connected to form a grid, and each of the first shielding electrodes is located in a grid;
  • the orthographic projection of the fifth sub-shielding electrode on the substrate covers the orthographic projection of the scanning line on the substrate.
  • the width range of the portion where the orthographic projection of the third sub-shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate is greater than 5 micrometers.
  • the ratio of the area of the first sub-shielding electrode to the area of the pixel electrode is in the range of 30%-85%.
  • the shielding layer provided on the entire surface is provided in two parts, namely, a first shielding electrode and a plurality of second shielding electrodes provided at intervals, the first shielding electrode and the pixel electrode have the same potential, the orthographic projection of the first shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and since there is no voltage difference between the first shielding electrode and the pixel electrode, the lateral electric field generated between the two is avoided to affect the deflection angle of the liquid crystal; at the same time, the second shielding electrode and the common signal line have the same potential, the orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the data line on the substrate, and at least partially overlaps with the orthographic projection of the pixel electrode on the substrate, which is conducive to increasing the storage capacitance between the two and can improve the transmittance. In this way, the transmittance and liquid crystal efficiency are guaranteed at the
  • FIG1 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of a planar structure of an array substrate provided in an embodiment of the present application.
  • FIG4 is a schematic diagram showing the positional relationship among the data lines, pixel electrodes and shielding layer of the array substrate in FIG3 ;
  • FIG5 is a schematic diagram showing the positional relationship between the pixel electrode region and the driving circuit region of the array substrate in FIG3 ;
  • FIG6 is a schematic diagram of a first planar structure of a shielding layer of the array substrate in FIG3 ;
  • FIG7 is a schematic diagram of a partial enlarged structure at position A in FIG6 ;
  • FIG8 is a cross-sectional view of the array substrate cut through the third via hole in FIG3 ;
  • FIG9 is a schematic diagram of a second planar structure of the shielding layer of the array substrate in FIG3 ;
  • FIG. 10 is a schematic diagram of a third planar structure of the shielding layer of the array substrate in FIG. 3 .
  • the present application provides a display panel, which includes an array substrate 100, a color filter substrate 200, and a liquid crystal layer 300.
  • the array substrate 100 and the color filter substrate 200 are arranged opposite to each other, and the liquid crystal layer 300 is located between the color filter substrate 200 and the array substrate 100.
  • the liquid crystal layer 300 includes a plurality of liquid crystal molecules 301. There is a voltage difference between the array substrate 100 and the color filter substrate 200, and the voltage difference can drive the liquid crystal molecules 301 in the liquid crystal layer 300 to rotate, thereby realizing picture display.
  • the present application provides an array substrate 100 .
  • the array substrate 100 includes a base 10 , a first metal layer 20 , a second metal layer 30 , a pixel electrode layer 40 and a shielding layer 50 .
  • the first metal layer 20 is located on the substrate 10 and includes a common signal line 21.
  • the second metal layer 30 is located on a side of the first metal layer 20 away from the substrate 10 and includes a data line 31.
  • the pixel electrode layer 40 is located on a side of the second metal layer 30 away from the first metal layer 20 and includes a plurality of pixel electrodes 41 arranged at intervals.
  • the shielding layer 50 is located between the second metal layer 30 and the pixel electrode layer 40 and includes a plurality of first shielding electrodes 51 and second shielding electrodes 52 arranged at intervals, the first shielding electrodes 51 and the pixel electrodes 41 having the same potential, and the second shielding electrodes 52 and the common signal line 21 having the same potential.
  • the orthographic projection of the first shielding electrode 51 on the substrate 10 overlaps with the orthographic projection of the pixel electrode 41 on the substrate 10, and the orthographic projection of the second shielding electrode 52 on the substrate 10 covers the orthographic projection of the data line 31 on the substrate 10 and at least partially overlaps with the orthographic projection of the pixel electrode 41 on the substrate 10.
  • the second shielding electrode 52 has the same potential as the common signal line 21, and the orthographic projection of the second shielding electrode 52 on the substrate 10 covers the orthographic projection of the data line 31 on the substrate 10, so that there is no voltage difference between the second shielding electrode 52 and the color film substrate 200, thereby ensuring that the liquid crystal above the data line 31 is in a dark state, playing the role of a black matrix, and preventing light leakage on both sides of the data line 31.
  • the orthographic projection of the second shielding electrode 52 on the substrate 10 overlaps at least partially with the orthographic projection of the pixel electrode 41 on the substrate 10, increasing the storage capacitance between the pixel electrode 41 and the shielding layer 50, which is conducive to improving the transmittance.
  • the first shielding electrode 51 and the pixel electrode 41 have the same potential, so that there is no voltage difference between the first shielding electrode 51 and the pixel electrode 41, thereby avoiding the influence of the lateral electric field generated between the two on the liquid crystal deflection angle, which is beneficial to improving the liquid crystal efficiency. In this way, the transmittance and liquid crystal efficiency are guaranteed at the same time.
  • the orthographic projection of the pixel electrode 41 on the substrate 10 covers the orthographic projection of the first shielding electrode 51 on the substrate 10 .
  • the pixel electrode 41 is transparent, and the material of the pixel electrode 41 is indium tin oxide (ITO).
  • ITO indium tin oxide
  • the material of the pixel electrode 41 is not limited to ITO, and can also be other transparent electrode materials.
  • the shielding layer 50 is also transparent to avoid blocking the backlight provided by the backlight module located on one side of the array substrate 100 .
  • the array substrate 100 includes at least one pixel electrode area 101 and at least one driving circuit area 102, and the driving circuit area 102 is located on one side of the pixel electrode area 101.
  • the pixel electrode area 101 is used to place the pixel electrode 41, and the driving circuit area 102 is used to place the driving circuit for driving the liquid crystal deflection.
  • the number of the pixel electrode areas 101 is at least two, and one driving circuit area 102 is located between two adjacent pixel electrode areas 101.
  • the pixel electrode layer 40 also includes a connecting electrode 42 extending from the pixel electrode area 101 to the driving circuit area 102 and connected to the pixel electrode 41, and the first shielding electrode 51 is electrically connected to the connecting electrode 42 in the driving circuit area 102, so that the first shielding electrode 51 and the pixel electrode 41 have the same electric potential without affecting the aperture ratio of the pixel electrode 41.
  • the first shielding electrode 51 includes a first sub-shielding electrode 511 and a second sub-shielding electrode 512 extending from one side of the first sub-shielding electrode 511; the first sub-shielding electrode 511 is located in the pixel electrode area 101, the second sub-shielding electrode 512 is at least located in the driving circuit area 102, and the second sub-shielding electrode 512 is electrically connected to the connecting electrode 42 in the driving circuit area 102. In this embodiment, the second sub-shielding electrode 512 is completely located in the driving circuit area 102.
  • the shape of the orthographic projection of the second sub-shielding electrode 512 on the substrate 10 may include one of a rectangular, rhombus, triangular regular shape or an irregular shape.
  • the shape of the second sub-shielding electrode 512 is not limited to the above structure. In this embodiment, the shape of the orthographic projection of the second sub-shielding electrode 512 on the substrate 10 is a rectangle.
  • the first shielding electrode 51 and the pixel electrode 41 have the same potential.
  • the first shielding electrode 51 is electrically connected to the pixel electrode 41 and is connected to the same signal.
  • the first shielding electrode 51 is connected to a signal routing, and the signal routing electrically connected to the pixel electrode 41 is the same signal routing.
  • the first shielding electrode 51 is connected to a signal routing, and the signal routing electrically connected to the pixel electrode 41 is a different signal routing.
  • the embodiment of the present application is described by taking the example that the first shielding electrode 51 is electrically connected to the pixel electrode 41 and receives the same signal, but it should be noted that other embodiments are also within the protection scope of the technical solution provided in the present application.
  • the second metal layer 30 also includes a source 32 and a drain 33 that are spaced apart and located in the driving circuit area 102; the source 32 is electrically connected to the data line 31, the second sub-shielding electrode 512 is electrically connected to the drain 33 through the first via 100a, the pixel electrode 41 is overlapped with the second sub-shielding electrode 512 in the first via 100a through the second via 100b, and the first via 100a is connected to the second via 100b.
  • the data signal enters the source 32, the drain 33, the second sub-shielding electrode 512, the connecting electrode 42 and the pixel electrode 41 in sequence from the data line 31.
  • the second sub-shielding electrode 512 and the pixel electrode 41 receive the same data signal, that is, no voltage difference will be generated therebetween, and thus no transverse electric field will be generated.
  • the liquid crystal molecules 301 located directly above the second sub-shielding electrode 512 are only affected by the vertical electric field formed between the pixel electrode 41 and the common electrode on the color film substrate 200, but are not affected by the transverse electric field, so that the deflection angle of the liquid crystal molecules 301 can reach the expected value, which is beneficial to improving the liquid crystal efficiency.
  • the first via hole 100a and the second via hole 100b overlap in the thickness direction of the array substrate 100 to reduce the space occupied by the first via hole 100a and the second via hole 100b in the driving circuit area 102, thereby leaving sufficient space for the arrangement of various wirings in the driving circuit, so that the area of the driving circuit area 102 is reduced and the area of the pixel electrode area 101 is increased, thereby further improving the aperture ratio.
  • the connecting electrode 42 may also be electrically connected to the drain 33 through a via, and the connecting electrode 42 is electrically connected to the second sub-shielding electrode 512 through another via; or, the connecting electrode 42 is electrically connected to the drain 33 through a via, and the second sub-shielding electrode 512 is electrically connected to the drain 33 through a via.
  • the first metal layer 20 further includes a scan line 23 and a gate 22, the scan line 23 is arranged to cross the data line 31, the extension direction of the scan line 23 is perpendicular to the extension direction of the data line 31, the area between two adjacent scan lines 23 and two adjacent data lines 31 is defined as a sub-pixel, and each sub-pixel includes a pixel electrode area 101 and a driving circuit area 102.
  • the scan line 23 extends along the X direction and is arranged at intervals along the Y direction
  • the data line 31 extends along the Y direction and is arranged at intervals along the X direction.
  • the scanning line 23 is electrically connected to the gate 22, and the source 32 and the drain 33 are respectively opposite to the gate 22.
  • the array substrate 100 further includes a gate insulating layer 81 and an active layer 60 located on one side of the first metal layer 20, the gate insulating layer 81 covers the first metal layer 20, and the active layer 60 is located on the side of the gate insulating layer 81 away from the substrate 10.
  • the array substrate 100 further includes a plurality of transistors, each transistor including a gate 22, an active layer 60, and a source 32 and a drain 33 arranged opposite to the gate 22 and the active layer 60.
  • the scanning signal enters the gate 22 from the scanning line 23 to control the opening and closing of the transistor.
  • the common signal enters the first shielding electrode 51 from the common signal line 21, so that the signals of the first shielding electrode 51 and the common electrode layer 203 on the color filter substrate 200 are the same common signal, and there is no voltage difference between the two.
  • the array substrate 100 further includes a color resist layer 70 and an insulating layer 82.
  • the color resist layer 70 is formed between the second metal layer 30 and the shielding layer 50.
  • the insulating layer 82 is disposed between the shielding layer 50 and the pixel electrode layer 40.
  • the first via hole 100a penetrates the color resist layer 70, and the second via hole 100b penetrates the insulating layer 82.
  • the color resist layer 70 includes a plurality of color resist blocks, and the plurality of color resist blocks include a blue color resist block, a red color resist block, and a green color resist block.
  • the array substrate 100 further includes a passivation layer 83, the passivation layer 83 covers the second metal layer 30, and the color resist layer 70 is located on a side of the passivation layer 83 away from the substrate 10.
  • the first via hole 100a penetrates the color resist layer 70 and the passivation layer 83.
  • the material of the passivation layer 83 includes an inorganic material, and the inorganic material may include a combination of one or more of silicon nitride, silicon oxide, and silicon oxynitride.
  • the second shielding electrode 52 includes a third sub-shielding electrode 521 and a fourth sub-shielding electrode 522 which are parallel to and connected to the data line 31, the third sub-shielding electrode 521 is located on the side of the pixel electrode area 101, and the fourth sub-shielding electrode 522 is located on the side of the driving circuit area 102; the orthographic projection of the third sub-shielding electrode 521 on the substrate 10 is at least partially overlapped with the orthographic projection of the pixel electrode 41 on the substrate 10.
  • the third sub-shielding electrode 521 overlaps with the data line 31 and the pixel electrode 41, wherein the portion of the third sub-shielding electrode 521 overlapping with the data line 31 is used to prevent the data line 31 from leaking light, and the portion of the third sub-shielding electrode 521 overlapping with the pixel electrode 41 is used to form a storage capacitor between the pixel electrode 41 to improve the transmittance.
  • the fourth sub-shielding electrode 522 overlaps a portion of the data line 31 to prevent light leakage from the data line 31 .
  • the second shielding electrode 52 also includes a fifth sub-shielding electrode 523 parallel to the scanning line 23 and connected to the third sub-shielding electrode 521, the third sub-shielding electrode 521, the fourth sub-shielding electrode 522 and the fifth sub-shielding electrode 523 are connected to form a grid, and each of the first shielding electrodes 51 is located in a grid.
  • the first sub-shielding electrode 511 and the second sub-shielding electrode 512 are both located in the same grid.
  • the orthographic projection of the fifth sub-shielding electrode 523 on the substrate 10 covers the orthographic projection of the scanning line 23 on the substrate 10, so as to shield the scanning line 23, thereby ensuring that the liquid crystal above the scanning line 23 is in a dark state, playing the role of a black matrix, and preventing light leakage on both sides of the scanning line 23.
  • the area where the second shielding electrode 52 overlaps with the pixel electrode 41 is too large, that is, the area where the first shielding electrode 51 overlaps with the pixel electrode 41 is too small, the storage capacitance between the second shielding electrode 52 and the pixel electrode 41 is large, and the transmittance is high, but the first shielding electrode 51 does not significantly improve the lateral electric field formed between it and the pixel electrode 41, and the liquid crystal efficiency is low.
  • the first shielding electrode 51 significantly improves the lateral electric field formed between it and the pixel electrode 41, and the liquid crystal efficiency is high, but the storage capacitance between the second shielding electrode 52 and the pixel electrode 41 is small, and the transmittance is low. Therefore, there needs to be a balance between the area where the second shielding electrode 52 overlaps with the pixel electrode 41 and the area where the first shielding electrode 51 overlaps with the pixel electrode 41, so as to ensure both high transmittance and liquid crystal efficiency.
  • the width d1 of the portion where the orthographic projection of the third sub-shielding electrode 521 on the substrate 10 overlaps with the orthographic projection of the pixel electrode 41 on the substrate 10 is greater than 5 micrometers. Further, the ratio of the area of the first sub-shielding electrode 511 to the area of the pixel electrode 41 is in the range of 30%-85% to ensure a higher transmittance and liquid crystal efficiency.
  • the minimum spacing d2 between the third sub-shielding electrode 521 and the first sub-shielding electrode 511 is in the range of 4 microns to 10 microns to avoid a short circuit between the third sub-shielding electrode 521 and the first sub-shielding electrode 511 disposed on the same layer.
  • the array substrate 100 also includes a third via hole 100c, the second shielding electrode 52 is electrically connected to the common signal line 21 through the third via hole 100c, and the third via hole 100c passes through the color resist layer 70, the passivation layer 83 and the gate 22 insulation layer 82.
  • the common signal line 21 includes a first common signal line and a second common signal line, the first common signal line is vertically connected to the second common signal line, and one of the first common signal line 21 and the second common signal line is parallel to the data line 31.
  • the second shielding electrode 52 is electrically connected to one of the first common signal line and the second common signal line through the third via 100c.
  • the third via 100c may be located in the driving circuit area 102.
  • the shape of the orthographic projection of the first sub-shielding electrode 511 on the substrate 10 includes one of a rectangular, rhombus, triangular regular shape or an irregular shape.
  • the shape of the first sub-shielding electrode 511 is not limited to the above-mentioned structure. Specifically, as shown in FIG6, the shape of the orthographic projection of the first sub-shielding electrode 511 on the substrate 10 is a rectangle. As shown in FIG9, the shape of the orthographic projection of the first sub-shielding electrode 511 on the substrate 10 is a rhombus.
  • the shape of the orthographic projection of the first sub-shielding electrode 511 on the substrate 10 is a hexagon, wherein the hexagon is composed of two isosceles trapezoids, and the two isosceles trapezoids are a positive isosceles trapezoid and an inverted isosceles trapezoid, respectively.
  • the color filter substrate 200 includes a color filter base 201, a patterned black matrix layer 202 formed on the color filter base 201, and a common electrode formed on the color filter base 201 and covering the black matrix layer 202, and the common electrode faces the pixel electrode layer 40.
  • a support column 400 is further disposed between the array substrate 100 and the color filter substrate 200 .
  • the support column 400 is disposed corresponding to the black matrix layer 202 to play a supporting role.
  • the shielding layer arranged on the entire surface is arranged into two parts, namely, a first shielding electrode and a plurality of second shielding electrodes arranged at intervals, the first shielding electrode and the pixel electrode have the same potential, and the positive projection of the first shielding electrode on the substrate overlaps with the positive projection of the pixel electrode on the substrate.
  • the second shielding electrode and the common signal line have the same potential
  • the positive projection of the second shielding electrode on the substrate covers the positive projection of the data line on the substrate, and at least partially overlaps with the positive projection of the pixel electrode on the substrate, which is conducive to increasing the storage capacitance between the two and can improve the transmittance. In this way, the transmittance and liquid crystal efficiency are guaranteed at the same time.

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Abstract

一种阵列基板（100）及显示面板，阵列基板（100）的屏蔽层（50）包括与像素电极（41）具有相同电位的第一屏蔽电极（51）和与公共信号线（21）具有相同电位的第二屏蔽电极（52）；第一屏蔽电极（51）在基底（10）上的正投影与像素电极（41）在基底（10）上的正投影重叠，第二屏蔽电极（52）在基底（10）上的正投影覆盖数据线（31）在基底（10）上的正投影，且与像素电极（41）在基底（10）上的正投影至少部分重叠。

Description

阵列基板及显示面板 技术领域
本申请涉及显示领域，尤其涉及一种阵列基板及显示面板。
 背景技术
现有像素结构(新增透明电极层代替DBS(data line BM less)，透明电极层与数据线交叠，可以屏蔽数据线的电场，且透明电极层整面设置且与像素电极层之间形成较大透明存储电容，可大幅提升穿透率及存储电容，但整面设置的透明电极层具有电场封闭效果，其与像素电极之间形成横向电场，导致液晶倾倒状态达不到设定的理想值，从而导致液晶效率降低。
 发明概述
本申请实施例提供一种阵列基板及显示面板，可以解决现有的阵列基板中整面设置的透明电极层与像素电极之间形成横向电场，导致液晶效率降低的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，包括：
基底；
第一金属层，位于所述基底上且包括公共信号线；
第二金属层，位于所述第一金属层的背离所述基底的一侧且包括数据线；
像素电极层，位于所述第二金属层的背离所述第一金属层的一侧且包括多个像素电极；以及
屏蔽层，位于所述第二金属层和所述像素电极层之间且包括间隔设置的多个第一屏蔽电极和第二屏蔽电极，所述第一屏蔽电极与所述像素电极具有相同电位，所述第二屏蔽电极与所述公共信号线具有相同电位；
其中，所述第一屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影重叠，所述第二屏蔽电极在所述基底上的正投影覆盖所述数据线在所述基底上的正投影，且与所述像素电极在所述基底上的正投影至少部分重叠。
根据本申请提供的阵列基板，所述阵列基板包括多个像素电极区和位于所述像素电极区一侧的至少一个驱动电路区，所述像素电极位于所述像素电极区；
所述像素电极层还包括与所述像素电极相接并从所述像素电极区延伸至所述驱动电路区的连接电极，所述第一屏蔽电极在所述驱动电路区内与所述连接电极电连接。
根据本申请提供的阵列基板，所述第一屏蔽电极包括第一子屏蔽电极以及自所述第一子屏蔽电极的一侧延伸而出的第二子屏蔽电极；所述第一子屏蔽电极位于所述像素电极区，所述第二子屏蔽电极至少位于所述驱动电路区，所述第二子屏蔽电极在所述驱动电路区内与所述连接电极电连接。
根据本申请提供的阵列基板，所述第二金属层还包括间隔设置且位于所述驱动电路区的源极及漏极；所述源极与所述数据线电连接，所述第二子屏蔽电极通过第一过孔与所述漏极电连接，所述连接电极通过第二过孔与所述第二子屏蔽电极在所述第一过孔内搭接，所述第一过孔与所述第二过孔相连通。
根据本申请提供的阵列基板，所述阵列基板还包括：
色阻层，形成在所述第二金属层和所述屏蔽层之间；以及
绝缘层，设置于所述屏蔽层和所述像素电极层之间；
其中，所述第一过孔贯穿所述色阻层，所述第二过孔贯穿所述绝缘层。
根据本申请提供的阵列基板，所述第二屏蔽电极包括延伸方向与所述数据线平行且相连接的第三子屏蔽电极和第四子屏蔽电极，所述第三子屏蔽电极位于所述像素电极区一侧，所述第四子屏蔽电极位于所述驱动电路区一侧；所述第三子屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影至少部分重叠。
根据本申请提供的阵列基板，所述第一金属层还包括扫描线，所述扫描线与所述数据线交叉设置；
所述第二屏蔽电极还包括与所述扫描线平行并与所述第三子屏蔽电极相连的第五子屏蔽电极，所述第三子屏蔽电极、第四子屏蔽电极和所述第五子屏蔽电极连接成网格状，每一所述第一屏蔽电极位于一网格中；
其中，所述第五子屏蔽电极在所述基底上的正投影覆盖所述扫描线在所述基底上的正投影。
根据本申请提供的阵列基板，所述第三子屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影重叠的部分的宽度范围大于5微米。
根据本申请提供的阵列基板，所述第一子屏蔽电极的面积与所述像素电极的面积的比值范围为30%-85%。
根据本申请提供的阵列基板，所述第三子屏蔽电极和所述第一子屏蔽电极之间的最小间距的范围为4微米-10微米。
根据本申请提供的阵列基板，所述阵列基板还包括第三过孔，所述第二屏蔽电极与所述公共信号线通过所述第三过孔电连接。
本申请提供一种显示面板，包括：
阵列基板；
彩膜基板，与所述阵列基板相对设置；以及
液晶层，位于所述阵列基板和所述彩膜基板之间；
其中，所述阵列基板包括：
基底；
第一金属层，位于所述基底上且包括公共信号线；
第二金属层，位于所述第一金属层的背离所述基底的一侧且包括数据线；
像素电极层，位于所述第二金属层的背离所述第一金属层的一侧且包括多个像素电极；以及
屏蔽层，位于所述第二金属层和所述像素电极层之间且包括间隔设置的多个第一屏蔽电极和第二屏蔽电极，所述第一屏蔽电极与所述像素电极具有相同电位，所述第二屏蔽电极与所述公共信号线具有相同电位；
其中，所述第一屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影重叠，所述第二屏蔽电极在所述基底上的正投影覆盖所述数据线在所述基底上的正投影，且与所述像素电极在所述基底上的正投影至少部分重叠。
根据本申请提供的显示面板，所述阵列基板包括多个像素电极区和位于所述像素电极区一侧的至少一个驱动电路区，所述像素电极位于所述像素电极区；
所述像素电极层还包括与所述像素电极相接并从所述像素电极区延伸至所述驱动电路区的连接电极，所述第一屏蔽电极在所述驱动电路区内与所述连接电极电连接。
根据本申请提供的显示面板，所述第一屏蔽电极包括第一子屏蔽电极以及自所述第一子屏蔽电极的一侧延伸而出的第二子屏蔽电极；所述第一子屏蔽电极位于所述像素电极区，所述第二子屏蔽电极至少位于所述驱动电路区，所述第二子屏蔽电极在所述驱动电路区内与所述连接电极电连接。
根据本申请提供的显示面板，所述第二金属层还包括间隔设置且位于所述驱动电路区的源极及漏极；所述源极与所述数据线电连接，所述第二子屏蔽电极通过第一过孔与所述漏极电连接，所述连接电极通过第二过孔与所述第二子屏蔽电极在所述第一过孔内搭接，所述第一过孔与所述第二过孔相连通。
根据本申请提供的显示面板，所述阵列基板还包括：
色阻层，形成在所述第二金属层和所述屏蔽层之间；以及
绝缘层，设置于所述屏蔽层和所述像素电极层之间；
其中，所述第一过孔贯穿所述色阻层，所述第二过孔贯穿所述绝缘层。
根据本申请提供的显示面板，所述第二屏蔽电极包括延伸方向与所述数据线平行且相连接的第三子屏蔽电极和第四子屏蔽电极，所述第三子屏蔽电极位于所述像素电极区一侧，所述第四子屏蔽电极位于所述驱动电路区一侧；所述第三子屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影至少部分重叠。
根据本申请提供的显示面板，所述第一金属层还包括扫描线，所述扫描线与所述数据线交叉设置；
所述第二屏蔽电极还包括与所述扫描线平行并与所述第三子屏蔽电极相连的第五子屏蔽电极，所述第三子屏蔽电极、第四子屏蔽电极和所述第五子屏蔽电极连接成网格状，每一所述第一屏蔽电极位于一网格中；
其中，所述第五子屏蔽电极在所述基底上的正投影覆盖所述扫描线在所述基底上的正投影。
根据本申请提供的显示面板，所述第三子屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影重叠的部分的宽度范围大于5微米。
根据本申请提供的显示面板，所述第一子屏蔽电极的面积与所述像素电极的面积的比值范围为30%-85%。
有益效果
本申请的有益效果：在本申请实施例提供的阵列基板及显示面板中，将整面设置的屏蔽层设置为两部分，分别为间隔设置的第一屏蔽电极和多个第二屏蔽电极，第一屏蔽电极与像素电极具有相同电位，第一屏蔽电极在基底上的正投影与像素电极在基底上的正投影重叠，由于第一屏蔽电极与像素电极之间没有电压差，避免两者之间产生横向电场对液晶偏转角度造成影响；与此同时，第二屏蔽电极与公共信号线具有相同电位，第二屏蔽电极在基底上的正投影覆盖数据线在基底上的正投影，且与像素电极在基底上的正投影至少部分重叠，有利于增大两者之间的存储电容，能够提高穿透率。如此，同时保证了穿透率和液晶效率。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种显示面板的截面结构示意图；
图2为本申请实施例提供的一种显示面板的膜层结构示意图；
图3为本申请实施例提供的一种阵列基板的平面结构示意图；
图4为图3中的阵列基板的数据线、像素电极和屏蔽层的位置关系示意图；
图5为图3中的阵列基板的像素电极区与驱动电路区的位置关系示意图；
图6为图3中的阵列基板的屏蔽层的第一种平面结构示意图；
图7为图6中的A位置处的局部放大结构示意图；
图8为图3中的第三过孔进行剖切的阵列基板的剖视图；
图9为图3中的阵列基板的屏蔽层的第二种平面结构示意图；
图10为图3中的阵列基板的屏蔽层的第三种平面结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体地限定。
本申请可以在不同实施中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
以下将结合具体实施例及附图对本申请提供的阵列基板及显示面板进行详细描述。
请参阅图1，本申请提供一种显示面板，所述显示面板包括阵列基板100、彩膜基板200及液晶层300，所述阵列基板100和所述彩膜基板200相对设置，所述液晶层300位于所述彩膜基板200与所述阵列基板100之间。所述液晶层300包括多个液晶分子301，所述阵列基板100和所述彩膜基板200之间存在电压差，该电压差能够驱动所述液晶层300中的液晶分子301产生转动，从而实现画面显示。
请参阅图2-图4，本申请提供一种阵列基板100，所述阵列基板100包括基底10、第一金属层20、第二金属层30、像素电极层40及屏蔽层50。
所述第一金属层20位于所述基底10上且包括公共信号线21。所述第二金属层30位于所述第一金属层20的背离所述基底10的一侧且包括数据线31。所述像素电极层40位于所述第二金属层30的背离所述第一金属层20的一侧且包括间隔设置的多个像素电极41。所述屏蔽层50位于所述第二金属层30和所述像素电极层40之间且包括间隔设置的多个第一屏蔽电极51和第二屏蔽电极52，所述第一屏蔽电极51与所述像素电极41具有相同电位，所述第二屏蔽电极52与所述公共信号线21具有相同电位。其中，所述第一屏蔽电极51在所述基底10上的正投影与所述像素电极41在所述基底10上的正投影重叠，所述第二屏蔽电极52在所述基底10上的正投影覆盖所述数据线31在所述基底10上的正投影，且与所述像素电极41在所述基底10上的正投影至少部分重叠。
可以理解的是，所述第二屏蔽电极52与所述公共信号线21具有相同电位，且所述第二屏蔽电极52在所述基底10上的正投影覆盖所述数据线31在所述基底10上的正投影，使得所述第二屏蔽电极52和所述彩膜基板200之间不存在电压差，从而确保所述数据线31上方的液晶处于暗态，起到黑矩阵的作用，避免所述数据线31两侧漏光。并且，所述第二屏蔽电极52在所述基底10上的正投影与所述像素电极41在所述基底10上的正投影至少部分重叠，增大了所述像素电极41与所述屏蔽层50之间的存储电容，有利于提高穿透率。
与此同时，所述第一屏蔽电极51与所述像素电极41具有相同电位，使得所述第一屏蔽电极51与所述像素电极41之间没有电压差，从而避免两者之间产生横向电场对液晶偏转角度造成影响，有利于提升液晶效率。如此，同时保证了穿透率和液晶效率。
在本申请实施例中，所述像素电极41在所述基底10上的正投影覆盖所述第一屏蔽电极51在所述基底10上的正投影。
所述像素电极41为透明的，所述像素电极41的材质为氧化铟锡(Indium tin oxide，ITO)。当然，所述像素电极41的材质并不局限于ITO，还可以是其他的透明电极材料。
在本申请实施例中，所述屏蔽层50也为透明的，避免对位于阵列基板100一侧的背光模组提供的背光造成遮挡。
在本申请实施例中，请参阅图5，所述阵列基板100包括至少一像素电极区101及至少一个驱动电路区102，所述驱动电路区102位于所述像素电极区101的一侧。所述像素电极区101用于放置所述像素电极41，所述驱动电路区102用于放置驱动液晶偏转的驱动电路。在本实施例中，所述像素电极区101的数量为至少两个，一个所述驱动电路区102位于两个相邻的所述像素电极区101之间。
在本申请实施例中，请结合图2和图5，所述像素电极层40还包括从所述像素电极区101延伸至所述驱动电路区102且与所述像素电极41相接的连接电极42，所述第一屏蔽电极51在所述驱动电路区102内与所述连接电极42电连接，在不影响所述像素电极41的开口率的情况下，能够使得所述第一屏蔽电极51与所述像素电极41具有相同电位。
具体的，在本申请实施例中，请结合图2和图6，所述第一屏蔽电极51包括第一子屏蔽电极511以及自所述第一子屏蔽电极511的一侧延伸而出的第二子屏蔽电极512；所述第一子屏蔽电极511位于所述像素电极区101，所述第二子屏蔽电极512至少位于所述驱动电路区102，所述第二子屏蔽电极512在所述驱动电路区102内与所述连接电极42电连接。在本实施例中，所述第二子屏蔽电极512完全位于所述驱动电路区102。
可选的，所述第二子屏蔽电极512在所述基底10上的正投影的形状可以包括矩形、菱形、三角形规则图形或不规则图形中的其中一种。所述第二子屏蔽电极512的形状也并不局限于上述的结构。在本实施例中，所述第二子屏蔽电极512在所述基底10上的正投影的形状为矩形。
需要说明的是，实现所述第一屏蔽电极51与所述像素电极41具有相同电位的方式具有多种方式。例如，在一种实施例中，所述第一屏蔽电极51与所述像素电极41电连接且接入同一信号。在另一种实施例中，所述第一屏蔽电极51与所述像素电极41之间不存在连接关系，但两者接入同一信号，具体的，所述第一屏蔽电极51接入一信号走线，该信号走线与所述像素电极41电连接的信号走线为同一信号走线。在另一种实施例中，所述第一屏蔽电极51与所述像素电极41之间不存在连接关系且接入不同的信号，但两者具有同一电位，具体的，所述第一屏蔽电极51接入一信号走线，该信号走线与所述像素电极41电连接的信号走线为不同的信号走线。
以下，本申请实施例以所述第一屏蔽电极51与所述像素电极41电连接且接入同一信号为例进行阐述说明，但需要说明的是，其它实施例也在本申请提供的技术方案的保护范围之内。
在本申请实施例中，请结合图2至图6，所述第二金属层30还包括间隔设置且位于所述驱动电路区102的源极32及漏极33；所述源极32与所述数据线31电连接，所述第二子屏蔽电极512通过第一过孔100a与所述漏极33电连接，所述像素电极41通过第二过孔100b与所述第二子屏蔽电极512在所述第一过孔100a内搭接，所述第一过孔100a与所述第二过孔100b相连通。如此，数据信号自所述数据线31依次进入所述源极32、所述漏极33、所述第二子屏蔽电极512、所述连接电极42和所述像素电极41，所述第二子屏蔽电极512和所述像素电极41接收同一数据信号，即，两者之间不会产生电压差，从而不会产生横向电场，位于所述第二子屏蔽电极512正上方的液晶分子301仅受到所述像素电极41和所述彩膜基板200上的公共电极之间形成的垂直电场，而不会受到横向电场的影响，从而能够液晶分子301偏转角度可以达到预期值，有利于提升液晶效率。
在本申请实施例中，所述第一过孔100a和所述第二过孔100b在所述阵列基板100的厚度方向上交叠，以减小所述第一过孔100a和所述第二过孔100b占据所述驱动电路区102的空间，从而为驱动电路中的多种走线的排布留出足够空间，使得所述驱动电路区102的面积减小，所述像素电极区101的面积增大，从而进一步提升了开口率。
在其他实施例中，所述连接电极42也可通过一过孔与所述漏极33电连接，所述连接电极42通过另一过孔与所述第二子屏蔽电极512电连接；或者，所述连接电极42通过一过孔与所述漏极33电连接，所述第二子屏蔽电极512通过一过孔与所述漏极33电连接。
在本申请实施例中，所述第一金属层20还包括扫描线23和栅极22，所述扫描线23与所述数据线31交叉设置，所述扫描线23的延伸方向与所述数据线31的延伸方向垂直，相邻的两条扫描线23及相邻的两条数据线31之间的区域限定为一个所述子像素，每一所述子像素包括一个所述像素电极区101和所述驱动电路区102。在本实施例中，所述扫描线23沿X方向延伸并沿Y方向间隔排列，所述数据线31沿Y方向延伸并沿X方向间隔排列。
其中，所述扫描线23与所述栅极22电连接，所述源极32及所述漏极33分别与所述栅极22位置相对。所述阵列基板100还包括位于所述第一金属层20的一侧的栅极绝缘层81和有源层60，所述栅极绝缘层81覆盖所述第一金属层20，所述有源层60位于所述栅极绝缘层81远离所述基底10的一侧。所述阵列基板100还包括多个晶体管，每个晶体管包括一个所述栅极22、一个所述有源层60及与所述栅极22及所述有源层60位置相对设置的一个所述源极32及一个所述漏极33。扫描信号自所述扫描线23进入所述栅极22，以控制晶体管的开合和关闭。公共信号自所述公共信号线21进入所述第一屏蔽电极51，以使所述第一屏蔽电极51和所述彩膜基板200上的公共电极层203的信号均为同一公共信号，两者之间不存在电压差。
在本申请实施例中，所述阵列基板100还包括色阻层70和绝缘层82。所述色阻层70形成在所述第二金属层30和所述屏蔽层50之间。所述绝缘层82设置于所述屏蔽层50和所述像素电极层40之间。其中，所述第一过孔100a贯穿所述色阻层70，所述第二过孔100b贯穿所述绝缘层82。所述色阻层70包括多个色阻块，所述多个色阻块包括蓝色色阻块、红色色阻块和绿色色阻块。
在本申请实施例中，所述阵列基板100还包括钝化层83，所述钝化层83覆盖所述第二金属层30，所述色阻层70位于所述钝化层83远离所述基底10的一侧。其中，所述第一过孔100a贯穿所述色阻层70和所述钝化层83。在本实施例中，所述钝化层83的材料包括无机材料，所述无机材料可以包括氮化硅、氧化硅和氮氧化硅的其中一种或多种的组合。
在本申请实施例中，所述第二屏蔽电极52包括与所述数据线31平行且相连接的第三子屏蔽电极521和第四子屏蔽电极522，所述第三子屏蔽电极521位于所述像素电极区101一侧，所述第四子屏蔽电极522位于所述驱动电路区102一侧；所述第三子屏蔽电极521在所述基底10上的正投影与所述像素电极41在所述基底10上的正投影至少部分重叠。也即是说，所述第三子屏蔽电极521与所述数据线31及所述像素电极41交叠，其中，所述第三子屏蔽电极521与所述数据线31交叠的部分用于防止所述数据线31漏光，与所述像素电极41交叠的部分用于与所述像素电极41之间形成存储电容，以提升穿透率。
其中，所述第四子屏蔽电极522与所述数据线31的部分交叠，以防止所述数据线31漏光。
在本申请实施例中，所述第二屏蔽电极52还包括与所述扫描线23平行并与所述第三子屏蔽电极521相连的第五子屏蔽电极523，所述第三子屏蔽电极521、第四子屏蔽电极522和所述第五子屏蔽电极523连接成网格状，每一所述第一屏蔽电极51位于一网格中，具体的，所述第一子屏蔽电极511和所述第二子屏蔽电极512均位于同一所述网格中。
在本申请实施例中，所述第五子屏蔽电极523在所述基底10上的正投影覆盖所述扫描线23在所述基底10上的正投影，以用于遮蔽所述扫描线23，从而确保所述扫描线23上方的液晶处于暗态，起到黑矩阵的作用，避免所述扫描线23两侧漏光。
可以理解的是，若所述第二屏蔽电极52与所述像素电极41交叠的面积过大，即所述第一屏蔽电极51与所述像素电极41交叠的面积过小，所述第二屏蔽电极52与所述像素电极41之间的存储电容较大，穿透率较高，但所述第一屏蔽电极51对于其与所述像素电极41之间形成的横向电场的改善作用不明显，液晶效率低。若所述第二屏蔽电极52与所述像素电极41交叠的面积过小，即所述第一屏蔽电极51与所述像素电极41交叠的面积过大，所述第一屏蔽电极51对于其与所述像素电极41之间形成的横向电场的改善作用较为明显，液晶效率高，但所述第二屏蔽电极52与所述像素电极41之间的存储电容较小，穿透率低。因此，所述第二屏蔽电极52与所述像素电极41交叠的面积、以及所述第一屏蔽电极51与所述像素电极41交叠的面积之间需要存在一平衡，以同时保证较高的穿透率和液晶效率。
有鉴于此，在本申请实施例中，请参阅图4，所述第三子屏蔽电极521在所述基底10上的正投影与所述像素电极41在所述基底10上的正投影重叠的部分的宽度d1的范围大于5微米。进一步的，所述第一子屏蔽电极511的面积与所述像素电极41的面积的比值范围为30%-85%，以保证较高的穿透率和液晶效率。
在本申请实施例中，请参阅图2和图7，所述第三子屏蔽电极521和所述第一子屏蔽电极511之间的最小间距d2的范围为4微米-10微米，以避免同层设置的所述第三子屏蔽电极521和所述第一子屏蔽电极511之间发生短路。
在本申请实施例中，请参阅图8，所述阵列基板100还包括第三过孔100c，所述第二屏蔽电极52与所述公共信号线21通过所述第三过孔100c电连接，所述第三过孔100c贯穿所述色阻层70、所述钝化层83和所述栅极22绝缘层82。
所述公共信号线21包括第一公共信号线及第二公共信号线，所述第一公共信号线与所述第二公共信号线垂直连接，所述第一公共信号线21及所述第二公共信号线中的一条平行于所述数据线31。所述第二屏蔽电极52通过所述第三过孔100c与所述第一公共信号线和所述第二公共信号线中的其中一条电连接，在本申请实施例中，所述第三过孔100c可位于所述驱动电路区102。
在本申请实施例中，所述第一子屏蔽电极511在所述基底10上的正投影的形状包括矩形、菱形、三角形规则图形或不规则图形中的其中一种。所述第一子屏蔽电极511的形状也并不局限于上述的结构。具体的，如图6所示，所述第一子屏蔽电极511在所述基底10上的正投影的形状为矩形。如图9所示，所述第一子屏蔽电极511在所述基底10上的正投影的形状为菱形。如图10所示，所述第一子屏蔽电极511在所述基底10上的正投影的形状为六边形，其中，该六边形由两个等腰梯形组成，两个等腰梯形分别为正等腰梯形和倒等腰梯形。
在本申请实施例中，请参阅图1和图2，所述彩膜基板200包括一彩膜基底201、形成在所述彩膜基底201上的图案化的黑矩阵层202及形成在所述彩膜基底201上且包覆所述黑矩阵层202的公共电极，所述公共电极面向所述像素电极层40。
所述阵列基板100和所述彩膜基板200之间还设置有支撑柱400，所述支撑柱400与所述黑矩阵层202对应设置，起到支撑作用。
有益效果：在本申请提供的阵列基板及显示面板中，将整面设置的屏蔽层设置为两部分，分别为间隔设置的第一屏蔽电极和多个第二屏蔽电极，第一屏蔽电极与像素电极具有相同电位，第一屏蔽电极在基底上的正投影与像素电极在基底上的正投影重叠，由于第一屏蔽电极与像素电极之间没有电压差，避免两者之间产生横向电场对液晶偏转角度造成影响；与此同时，第二屏蔽电极与公共信号线具有相同电位，第二屏蔽电极在基底上的正投影覆盖数据线在基底上的正投影，且与像素电极在基底上的正投影至少部分重叠，有利于增大两者之间的存储电容，能够提高穿透率。如此，同时保证了穿透率和液晶效率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种阵列基板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，包括：
    基底；
    第一金属层，位于所述基底上且包括公共信号线；
    第二金属层，位于所述第一金属层的背离所述基底的一侧且包括数据线；
    像素电极层，位于所述第二金属层的背离所述第一金属层的一侧且包括多个像素电极；以及
    屏蔽层，位于所述第二金属层和所述像素电极层之间且包括间隔设置的多个第一屏蔽电极和第二屏蔽电极，所述第一屏蔽电极与所述像素电极具有相同电位，所述第二屏蔽电极与所述公共信号线具有相同电位；
    其中，所述第一屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影重叠，所述第二屏蔽电极在所述基底上的正投影覆盖所述数据线在所述基底上的正投影，且与所述像素电极在所述基底上的正投影至少部分重叠。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括多个像素电极区和位于所述像素电极区一侧的至少一个驱动电路区，所述像素电极位于所述像素电极区；
    所述像素电极层还包括与所述像素电极相接并从所述像素电极区延伸至所述驱动电路区的连接电极，所述第一屏蔽电极在所述驱动电路区内与所述连接电极电连接。
  3. 根据权利要求2所述的阵列基板，其中，所述第一屏蔽电极包括第一子屏蔽电极以及自所述第一子屏蔽电极的一侧延伸而出的第二子屏蔽电极；所述第一子屏蔽电极位于所述像素电极区，所述第二子屏蔽电极至少位于所述驱动电路区，所述第二子屏蔽电极在所述驱动电路区内与所述连接电极电连接。
  4. 根据权利要求3所述的阵列基板，其中，所述第二金属层还包括间隔设置且位于所述驱动电路区的源极及漏极；所述源极与所述数据线电连接，所述第二子屏蔽电极通过第一过孔与所述漏极电连接，所述连接电极通过第二过孔与所述第二子屏蔽电极在所述第一过孔内搭接，所述第一过孔与所述第二过孔相连通。
  5. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括：
    色阻层，形成在所述第二金属层和所述屏蔽层之间；以及
    绝缘层，设置于所述屏蔽层和所述像素电极层之间；
    其中，所述第一过孔贯穿所述色阻层，所述第二过孔贯穿所述绝缘层。
  6. 根据权利要求3所述的阵列基板，其中，所述第二屏蔽电极包括延伸方向与所述数据线平行且相连接的第三子屏蔽电极和第四子屏蔽电极，所述第三子屏蔽电极位于所述像素电极区一侧，所述第四子屏蔽电极位于所述驱动电路区一侧；所述第三子屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影至少部分重叠。
  7. 根据权利要求6所述的阵列基板，其中，所述第一金属层还包括扫描线，所述扫描线与所述数据线交叉设置；
    所述第二屏蔽电极还包括与所述扫描线平行并与所述第三子屏蔽电极相连的第五子屏蔽电极，所述第三子屏蔽电极、第四子屏蔽电极和所述第五子屏蔽电极连接成网格状，每一所述第一屏蔽电极位于一网格中；
    其中，所述第五子屏蔽电极在所述基底上的正投影覆盖所述扫描线在所述基底上的正投影。
  8. 根据权利要求7所述的阵列基板，其中，所述第三子屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影重叠的部分的宽度范围大于5微米。
  9. 根据权利要求8所述的阵列基板，其中，所述第一子屏蔽电极的面积与所述像素电极的面积的比值范围为30%-85%。
  10. 根据权利要求6所述的阵列基板，其中，所述第三子屏蔽电极和所述第一子屏蔽电极之间的最小间距的范围为4微米-10微米。
  11. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括第三过孔，所述第二屏蔽电极与所述公共信号线通过所述第三过孔电连接。
  12. 一种显示面板，包括：
    阵列基板；
    彩膜基板，与所述阵列基板相对设置；以及
    液晶层，位于所述阵列基板和所述彩膜基板之间；
    其中，所述阵列基板包括：
    基底；
    第一金属层，位于所述基底上且包括公共信号线；
    第二金属层，位于所述第一金属层的背离所述基底的一侧且包括数据线；
    像素电极层，位于所述第二金属层的背离所述第一金属层的一侧且包括多个像素电极；以及
    屏蔽层，位于所述第二金属层和所述像素电极层之间且包括间隔设置的多个第一屏蔽电极和第二屏蔽电极，所述第一屏蔽电极与所述像素电极具有相同电位，所述第二屏蔽电极与所述公共信号线具有相同电位；
    其中，所述第一屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影重叠，所述第二屏蔽电极在所述基底上的正投影覆盖所述数据线在所述基底上的正投影，且与所述像素电极在所述基底上的正投影至少部分重叠。
  13. 根据权利要求12所述的显示面板，其中，所述阵列基板包括多个像素电极区和位于所述像素电极区一侧的至少一个驱动电路区，所述像素电极位于所述像素电极区；
    所述像素电极层还包括与所述像素电极相接并从所述像素电极区延伸至所述驱动电路区的连接电极，所述第一屏蔽电极在所述驱动电路区内与所述连接电极电连接。
  14. 根据权利要求13所述的显示面板，其中，所述第一屏蔽电极包括第一子屏蔽电极以及自所述第一子屏蔽电极的一侧延伸而出的第二子屏蔽电极；所述第一子屏蔽电极位于所述像素电极区，所述第二子屏蔽电极至少位于所述驱动电路区，所述第二子屏蔽电极在所述驱动电路区内与所述连接电极电连接。
  15. 根据权利要求14所述的显示面板，其中，所述第二金属层还包括间隔设置且位于所述驱动电路区的源极及漏极；所述源极与所述数据线电连接，所述第二子屏蔽电极通过第一过孔与所述漏极电连接，所述连接电极通过第二过孔与所述第二子屏蔽电极在所述第一过孔内搭接，所述第一过孔与所述第二过孔相连通。
  16. 根据权利要求15所述的显示面板，其中，所述阵列基板还包括：
    色阻层，形成在所述第二金属层和所述屏蔽层之间；以及
    绝缘层，设置于所述屏蔽层和所述像素电极层之间；
    其中，所述第一过孔贯穿所述色阻层，所述第二过孔贯穿所述绝缘层。
  17. 根据权利要求14所述的显示面板，其中，所述第二屏蔽电极包括延伸方向与所述数据线平行且相连接的第三子屏蔽电极和第四子屏蔽电极，所述第三子屏蔽电极位于所述像素电极区一侧，所述第四子屏蔽电极位于所述驱动电路区一侧；所述第三子屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影至少部分重叠。
  18. 根据权利要求17所述的显示面板，其中，所述第一金属层还包括扫描线，所述扫描线与所述数据线交叉设置；
    所述第二屏蔽电极还包括与所述扫描线平行并与所述第三子屏蔽电极相连的第五子屏蔽电极，所述第三子屏蔽电极、第四子屏蔽电极和所述第五子屏蔽电极连接成网格状，每一所述第一屏蔽电极位于一网格中；
    其中，所述第五子屏蔽电极在所述基底上的正投影覆盖所述扫描线在所述基底上的正投影。
  19. 根据权利要求18所述的显示面板，其中，所述第三子屏蔽电极在所述基底上的正投影与所述像素电极在所述基底上的正投影重叠的部分的宽度范围大于5微米。
  20. 根据权利要求19所述的显示面板，其中，所述第一子屏蔽电极的面积与所述像素电极的面积的比值范围为30%-85%。
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