WO2024239353A1 - 显示装置 - Google Patents

显示装置 Download PDF

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Publication number
WO2024239353A1
WO2024239353A1 PCT/CN2023/096763 CN2023096763W WO2024239353A1 WO 2024239353 A1 WO2024239353 A1 WO 2024239353A1 CN 2023096763 W CN2023096763 W CN 2023096763W WO 2024239353 A1 WO2024239353 A1 WO 2024239353A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
pixel
display device
gate driving
driving unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/096763
Other languages
English (en)
French (fr)
Inventor
李秀妍
马长文
梅新东
王超
李明月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to EP23744036.7A priority Critical patent/EP4715795A1/en
Priority to US18/263,532 priority patent/US20250098382A1/en
Priority to JP2023542621A priority patent/JP2025519293A/ja
Publication of WO2024239353A1 publication Critical patent/WO2024239353A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/32—Active-matrix LED displays characterised by the geometry or arrangement of elements within a subpixel, e.g. arrangement of the transistor within its RGB subpixel

Definitions

  • the present application relates to the field of display technology, and in particular to a display device.
  • VR Virtual Reality
  • the resolution of VR display devices is getting higher and higher, but the existing VR display devices are limited by hardware and software and cannot improve the resolution of VR display devices.
  • the present application provides a display device, which can improve the resolution and achieve a high-resolution display effect.
  • an embodiment of the present application provides a display device, comprising: a plurality of scan lines, a plurality of data lines and a plurality of sub-pixels, the plurality of scan lines comprising a first scan line and a second scan line, the first scan line and the second scan line being spaced apart along a first direction; the plurality of data lines comprising a first data line and a second data line, the first data line and the second data line being spaced apart along a second direction; the plurality of sub-pixels comprising a first sub-pixel and a second sub-pixel, the first sub-pixel comprising a first thin film transistor, the second sub-pixel comprising a second thin film transistor, the first thin film transistor being connected to the first scan line and the first data line, the second thin film transistor being connected to the second scan line and the second data line; the first thin film transistor and the second thin film transistor being alternately arranged.
  • an extension direction of the channel of the first thin film transistor and an extension direction of the channel of the adjacent second thin film transistor are mirror-symmetric in the second direction.
  • the first data lines and the second data lines are alternately arranged along the second direction, and the first scan lines and the second scan lines are alternately arranged along the first direction.
  • the plurality of sub-pixels include a plurality of sub-pixel groups, the sub-pixel groups include a first sub-pixel group and a second sub-pixel group, the first sub-pixel group and the second sub-pixel group both include a first sub-pixel column and a second sub-pixel column, the first sub-pixel column includes a plurality of the first sub-pixels spaced apart along the first direction, and the second sub-pixel column includes a plurality of the second sub-pixels spaced apart along the first direction; wherein the first sub-pixel group and the second sub-pixel group are alternately arranged along the second direction, and the first sub-pixel group and the second sub-pixel group are mirror-symmetric in the second direction.
  • the display panel includes a plurality of light shielding portions, and the light shielding portions are arranged in a one-to-one correspondence with the sub-pixel groups.
  • the display panel includes a substrate and a spacer, the orthographic projection of the shading portion on the substrate covers the orthographic projection of the spacer on the substrate, and the spacer is arranged between two adjacent first sub-pixels along the second direction; and/or the spacer is arranged between two adjacent second sub-pixels along the second direction.
  • an orthographic projection of the spacer on the substrate at least partially overlaps with an orthographic projection of the second scan line on the substrate.
  • the display device includes a substrate, the first data line is arranged on the substrate, the second data line is arranged on a side of the first data line away from the substrate, and the orthographic projection of the first data line on the substrate at least partially overlaps with the orthographic projection of the second data line on the substrate.
  • the display device has a display area and a non-display area arranged around the display area, the display area is provided with the sub-pixels, and the non-display area is provided with a first driving module, a second driving module, a multi-stage cascaded first gate driving unit and a multi-stage cascaded second gate driving unit, the first driving module is connected to the first gate driving unit, the second driving module is connected to the second gate driving unit, and the first gate driving unit and the second gate driving unit are respectively located on opposite sides of the non-display area along the second direction; wherein, the first gate driving unit is connected to at least two of the scan lines, and the second gate driving unit is connected to at least two of the scan lines.
  • the scan line includes a first sub-scan line and a second sub-scan line, the first sub-scan line and the second sub-scan line are spaced apart along the second direction, the first sub-scan line is connected to the first gate drive unit, and the second sub-scan line is connected to the second gate drive unit.
  • the first gate driving unit is connected to two adjacent first sub-scan lines
  • the second gate driving unit is connected to two adjacent second sub-scan lines.
  • the first gate driving unit is connected to the first scan line
  • the second gate driving unit is connected to the second scan line
  • the first gate driving unit is connected to two adjacent first scan lines; and/or the second gate driving unit is connected to two adjacent second scan lines.
  • the non-display area is also provided with a source driver chip
  • the source driver chip includes a plurality of first source driver chips and a plurality of second source driver chips
  • the first driver module is connected to the first source driver chip
  • the second driver module is connected to the second source driver chip
  • the source driver chip is connected to the data line.
  • the first source driver chip, the second source driver chip, the first driver module, and the second driver module are located on the same side of the non-display area along the first direction.
  • a plurality of the first source driver chips are respectively connected to a plurality of the first data lines, and a plurality of the second source driver chips are respectively connected to a plurality of the second data lines.
  • the first gate driving unit is connected to two adjacent first scan lines; and/or the second gate driving unit is connected to two adjacent second scan lines.
  • the first driving module and the second driving module are located on two opposite sides of the non-display area along the first direction.
  • the sub-pixel further includes an opening region, and a cross-sectional shape of the opening region along the horizontal direction is of a “P” type.
  • the first sub-pixel includes a first opening area
  • the second sub-pixel includes a second opening area
  • two second opening areas adjacent along the second direction are mirror-symmetrical along the first direction
  • two first opening areas adjacent along the second direction are mirror-symmetrical along the first direction
  • the display device includes a plurality of scan lines, a plurality of data lines and a plurality of sub-pixels, wherein the plurality of scan lines include a first scan line and a second scan line, wherein the first scan line and the second scan line are arranged at intervals along a first direction; the plurality of data lines include a first data line and a second data line, wherein the first data line and the second data line are arranged at intervals along a second direction; the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, wherein the first sub-pixel includes a first thin film transistor, and the second sub-pixel includes a second thin film transistor, wherein the first thin film transistor is connected to the first scan line and the first data line, and the second thin film transistor is connected to the second scan line and the second data line; and the first thin film transistor and the second thin film transistor are arranged alternately.
  • the display device provided by the present application connects the first sub-pixel to the first data line and the second sub-pixel to the second data line by setting the first data line and the second data line, that is, without increasing the load of the pixel driving circuit, the sub-pixels in the odd columns and the sub-pixels in the even columns are provided with data signals by different data lines, thereby effectively improving the resolution of the display device and achieving a high-resolution display effect.
  • FIG1 is a first schematic diagram of a display device provided in an embodiment of the present application.
  • FIG2 is a timing diagram of a backlight driving circuit in a display device provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of a first arrangement of sub-pixels in the display device provided in FIG1 ;
  • FIG4 is a schematic diagram of a second arrangement of sub-pixels in the display device provided in FIG1 ;
  • FIG5 is a schematic diagram of a light shielding portion and a spacer in a display device provided in an embodiment of the present application
  • FIG. 6 is a cross-sectional view of the arrangement of data lines in a display device provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of a first arrangement of sub-pixels in a display device provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of a second arrangement of sub-pixels in a display device provided in an embodiment of the present application.
  • FIG9 is a second schematic diagram of a display device provided in an embodiment of the present application.
  • FIG. 10 is a timing diagram of a pixel driving circuit in a display device provided in an embodiment of the present application.
  • an embodiment of the present application provides a display device 100, which includes a display panel 110.
  • the display panel 110 includes: a plurality of scan lines 10, a plurality of data lines 20, and a plurality of sub-pixels 30.
  • the plurality of scan lines 10 include a first scan line 11 and a second scan line 12, and the first scan line 11 and the second scan line 12 are arranged at intervals along a first direction Y.
  • the plurality of data lines 20 include a first data line 21 and a second data line 22, and the first data line 21 and the second data line 22 are arranged at intervals along a second direction X.
  • the plurality of sub-pixels 30 include a first sub-pixel 31 and a second sub-pixel 32, and the first sub-pixel 31 includes a first thin film transistor 311, and the second sub-pixel 32 includes a second thin film transistor 321.
  • the first thin film transistor 311 is connected to the first scan line 11 and the first data line 21, and the second thin film transistor 321 is connected to the second scan line 12 and the second data line 22.
  • the first thin film transistor 311 and the second thin film transistor 321 are arranged alternately.
  • the display device provided in the present application sets a first data line 21 and a second data line 22, so that the first thin film transistor 311 is connected to the first data line 21, and the second thin film transistor 321 is connected to the second data line 22. That is, without increasing the load of the pixel driving circuit, the sub-pixels 30 in the odd columns and the sub-pixels 30 in the even columns are provided with data signals by different data lines 20, respectively, thereby effectively improving the resolution of the display device and achieving a high-resolution display effect.
  • the first data lines 21 and the second data lines 22 are alternately arranged along the second direction X
  • the first scan lines 11 and the second scan lines 12 are alternately arranged along the first direction Y.
  • the first direction Y is the extension direction of the data lines 20
  • the second direction X is the extension direction of the scan lines 10 .
  • the pixel unit includes a first sub-pixel 31 and two second sub-pixels 32, or a second sub-pixel 32 and two first sub-pixels 31. That is, each pixel unit is driven by two data lines 20 (the first data line 21 and the second data line 22).
  • the display device 100 has a display area AA and a non-display area NA disposed around the display area AA.
  • the display area AA is provided with sub-pixels 30 and scan lines 10 and data lines 20 connected to the sub-pixels 30.
  • the non-display area NA is provided with a first driving module 40, a second driving module 50, a multi-stage cascaded first gate driving unit 61, and a multi-stage cascaded second gate driving unit 62, the first driving module 40 is connected to the first gate driving unit 61, the second driving module 50 is connected to the second gate driving unit 62, and the first gate driving unit 61 and the second gate driving unit 62 are respectively located on opposite sides of the non-display area NA along the second direction X.
  • the first gate driving unit 61 is connected to at least two scan lines 10
  • the second gate driving unit 62 is connected to at least two scan lines 10.
  • the scan line 10 includes a first sub-scan line 13 and a second sub-scan line 14, the first sub-scan line 13 and the second sub-scan line 14 are arranged at intervals along the second direction X, the first sub-scan line 13 is connected to the first gate driving unit 61, and the second sub-scan line 14 is connected to the second gate driving unit 62.
  • the first scan line 11 and the second scan line 12 both include the first sub-scan line 13 and the second sub-scan line 14.
  • the number of sub-pixels 30 connected to the first sub-scan line 13 is equal to the number of sub-pixels 30 connected to the second sub-scan line 14, so that the loads of the first gate driving unit 61 and the second gate driving unit 62 are the same, thereby avoiding uneven brightness of the display device due to load differences.
  • the length of the first sub-scan line 13 is equal to the length of the second sub-scan line 14, and the multiple sub-pixels 30 connected to the first sub-scan line 13 and the sub-pixels 30 connected to the second sub-scan line 14 are symmetrically distributed along the central axis of the display area AA, further ensuring the brightness uniformity of the display device.
  • the first gate driving unit 61 is connected to two adjacent first sub-scanning lines 13, and the second gate driving unit 62 is connected to two adjacent second sub-scanning lines 14.
  • the first gate driving unit 61 is respectively connected to the first sub-scanning line 13 of the first scan line 11 and the first sub-scanning line 13 of the adjacent second scan line 12, and correspondingly, the second gate driving unit 62 is respectively connected to the second sub-scanning line 14 of the first scan line 11 and the second sub-scanning line 14 of the adjacent second scan line 12, so that the same pixel unit is input with a scan signal by one first gate driving unit 61 or one second gate driving unit 62, which is beneficial to improve the charging time of the sub-pixel 30 and enhance the level transfer stability of the gate driving circuit.
  • the non-display area NA is also provided with a source driver chip 70
  • the source driver chip 70 includes a plurality of first source driver chips 71 and a plurality of second source driver chips 72
  • the first driver module 40 is connected to the first source driver chip 71
  • the second driver module is connected to the second source driver chip 72
  • the source driver chip 70 is connected to the data line 20.
  • a plurality of first source driver chips 71 and a plurality of second source driver chips 72 are arranged at intervals along the second direction X, the first driver module 40 and the first source driver chip 71 are correspondingly arranged along the first direction Y, and the second driver module 50 and the second source driver chip 72 are correspondingly arranged along the first direction Y.
  • the first source driver chip 71/the second source driver chip 72 are respectively connected to the plurality of data lines 20, so that three or more sub-pixels 30 in the same pixel unit are input with scan signals by the same first gate driver unit 61/the second gate driver unit 62, and are input with data signals by the same first source driver chip 71/the second source driver chip 72, so as to ensure the identity of the scan signal and the data signal, and avoid display abnormality caused by signal input differences.
  • the first source driver chip 71 , the second source driver chip 72 , the first driver module 40 and the second driver module 50 are located at the same side of the non-display area NA along the first direction Y.
  • the display device further includes a light-emitting substrate 101, which includes a plurality of light-emitting areas, wherein a plurality of light-emitting devices are arranged in the light-emitting areas, and the light-emitting devices include micro light-emitting diodes or sub-millimeter light-emitting diodes. Whether the light-emitting device in each light-emitting area is turned on or the degree of brightness is related to the grayscale of the corresponding position in the image displayed by the display device.
  • the light-emitting areas emit light in sequence, and the time when the light-emitting areas emit light is synchronized with the time when the display data is written, and the light-emitting areas start to emit light after delaying half a frame on the basis of the time when the display data is written.
  • the diffusion range of the light emitted by the light-emitting device is between 1 and 3 adjacent light-emitting areas.
  • the light-emitting areas that emit light at the same time account for 5% to 25% of all light-emitting areas.
  • the display device also includes an image processing module, which is used to process the image signal input from the host end and output image data to the backlight driving circuit, the image data includes a backlight driving signal and a synchronization signal, and the synchronization signal is used to ensure the synchronization of the backlight and the displayed image.
  • an image processing module which is used to process the image signal input from the host end and output image data to the backlight driving circuit, the image data includes a backlight driving signal and a synchronization signal, and the synchronization signal is used to ensure the synchronization of the backlight and the displayed image.
  • a frame of displayed image includes 3 sub-frames, and the image processing module simultaneously outputs the backlight driving signal and the synchronization signal to the backlight driving circuit corresponding to the 3 sub-frames.
  • the sub-frame image and backlight data newly generated by the image processing module are stored in corresponding buffers, respectively.
  • the first driving module and the second driving module realize the synchronization of the displayed image under the control of the synchronization signal output
  • the driving module can also be one, which controls the first source driver chip and the corresponding second source driver chip to synchronously output data signals under the control of the synchronization signal output by the image processing module, and controls the first gate driver unit and the corresponding second gate driver unit to synchronously output scanning signals, thereby ensuring that the backlight and the display panel are driven according to a preset timing, and at the same time, ensuring that multiple sub-frame images are displayed synchronously to avoid image abnormalities caused by image data asynchrony.
  • the extension direction of the channel of the first thin film transistor 311 and the extension direction of the channel of the adjacent second thin film transistor 321 are mirror-symmetric in the second direction X, so that the design patterns of the first thin film transistor 311 and the second thin film transistor 321 are consistent, thereby avoiding the influence of process fluctuations that cause the design patterns of adjacent sub-pixels 30 to be different and the channel lengths of the thin film transistors in the sub-pixels 30 to be inconsistent, resulting in differences in device performance and affecting the display effect.
  • the number of first sub-pixels 31 connected to the first data line 21 is the same as the number of second sub-pixels 32 connected to the second data line 22.
  • the first sub-pixels 31 are located in odd rows, and the second sub-pixels 32 are located in even rows.
  • the first sub-pixels 31 are located in even rows, and the second sub-pixels 32 are located in odd rows.
  • the plurality of sub-pixels 30 include a plurality of sub-pixel groups 33, the sub-pixel group 33 includes a first sub-pixel group 331 and a second sub-pixel group 332, the first sub-pixel group 331 and the second sub-pixel group 332 both include a first sub-pixel column and a second sub-pixel column, the first sub-pixel column includes a plurality of first sub-pixels 31 spaced apart along a first direction Y, and the second sub-pixel column includes a plurality of second sub-pixels 32 spaced apart along the first direction Y.
  • the first sub-pixel group 331 and the second sub-pixel group 332 are alternately arranged along the second direction X, and the first sub-pixel group 331 and the second sub-pixel group 332 are mirror-symmetric in the second direction X, that is, the sub-pixel group 33 includes four pixel columns, and the sub-pixel group 33 includes a first sub-pixel column, a second sub-pixel column, a second sub-pixel column, and a first sub-pixel column in the second direction X, respectively.
  • two adjacent first sub-pixels 31 are mirror-symmetrical in the second direction X
  • two adjacent second sub-pixels 32 are mirror-symmetrical in the second direction X
  • the extension directions of the channels of two adjacent first thin-film transistors 311 are mirror-symmetrical in the second direction X
  • the extension directions of the channels of two adjacent second thin-film transistors 321 are mirror-symmetrical in the second direction X, so that the design patterns of the first thin-film transistors 311 and the second thin-film transistors 321 are consistent, avoiding the influence of process fluctuations that make the design patterns of adjacent sub-pixels 30 different and thus the channel lengths of the thin-film transistors in the sub-pixels 30 inconsistent, resulting in differences in device performance and affecting the display effect.
  • the number of first sub-pixels 31 connected to the first data line 21 is the same as the number of second sub-pixels 32 connected to the second data line 22.
  • the sum of the number of first sub-pixels 31 connected to one first data line 21 and the number of second sub-pixels 32 connected to one second data line 22 is equal to the number of scan lines arranged at intervals along the first direction Y.
  • the first sub-pixels 31 are located in odd rows, and the second sub-pixels 32 are located in even rows. Alternatively, the first sub-pixels 31 are located in even rows, and the second sub-pixels 32 are located in odd rows.
  • the display device includes a plurality of light shielding portions 80, and the light shielding portions 80 are arranged in a one-to-one correspondence with the sub-pixel groups 33. That is, one light shielding portion 80 is arranged in a corresponding manner to a non-display area in one sub-pixel group 33.
  • the non-display area includes the spacer area between the scan lines 10 (the first scan line 11 and the second scan line 12), the data lines 20 (the first data line 21 and the second data line 22), the thin film transistors, and the sub-pixels 30 (the first sub-pixel 31 and the second sub-pixel 32).
  • two second sub-pixels 32 adjacent to each other along the second direction X and two first sub-pixels 31 adjacent to each other along the second direction X in the same sub-pixel group 33 form a repeating unit, that is, every four sub-pixels 30 arranged in a " ⁇ " shape in the same sub-pixel group 33 form a repeating unit.
  • the light shielding portions 80 may also be arranged one-to-one with the repeating units, that is, a plurality of light shielding portions 80 are arranged in an array.
  • the sub-pixel 30 further includes an opening area 34.
  • the first sub-pixel 31 includes a first opening area 341
  • the second sub-pixel 32 includes a second opening area 342
  • the two second opening areas 342 adjacent along the second direction X are mirror-symmetrical along the first direction Y
  • the two first opening areas 341 adjacent along the second direction X are mirror-symmetrical along the first direction Y.
  • the cross-sectional shape of the opening area 34 along the horizontal direction is a "P" type.
  • the light shielding portion 80 is rhombus-shaped corresponding to the position of two adjacent second thin film transistors 321 in the same sub-pixel group 33.
  • the display device includes a substrate 101 and a spacer 90, the orthographic projection of the light shielding portion 80 on the substrate 101 covers the orthographic projection of the spacer 90 on the substrate 101, and the spacer 90 is disposed between two adjacent second sub-pixels 32 along the second direction X.
  • the spacer 90 is disposed between two adjacent second thin film transistors 321 in the same sub-pixel group 33, and is located in the rhombus-shaped region of the light shielding portion 80.
  • the orthographic projection of the spacer 90 on the substrate 101 at least partially overlaps with the orthographic projection of the second scan line 12 on the substrate 101.
  • a spacer 90 is provided between two second sub-pixels 32 adjacent to each other along the second direction X in two adjacent sub-pixel groups 33, and the orthographic projection of the spacer 90 on the substrate 101 partially overlaps with the orthographic projection of the second scan line 12 on the substrate 101.
  • a spacer 90 may also be provided between two first sub-pixels 31 adjacent to each other along the second direction X.
  • a plurality of spacers 90 such as two, three, four, five, six, etc., may be provided between two first sub-pixels 31 adjacent to each other along the second direction X in two adjacent sub-pixel groups 33.
  • the cross-sectional areas of the plurality of spacers 90 along the first direction Y/the second direction X may be equal or unequal, that is, the sizes of the plurality of spacers 90 may be the same or different.
  • the spacer 90 is provided on the shading portion 80, and the shading portion 80 provided separately for the spacer 90 may be omitted, which simplifies the process and helps to improve the aperture ratio of the pixel.
  • the spacer 90 may also be disposed between two adjacent first sub-pixels 31 along the second direction X and between two adjacent second sub-pixels 32 along the second direction X.
  • the display device includes a substrate 101, a first data line 21 is disposed on the substrate 101, and a second data line 22 is disposed on a side of the first data line 21 away from the substrate 101, and an orthographic projection of the first data line 21 on the substrate 101 and an orthographic projection of the second data line 22 on the substrate 101 at least partially overlap.
  • the first data line 21 and the second data line 22 are disposed to overlap along the thickness direction of the substrate 101.
  • the polarity of the data signal on the first data line 21 and the polarity of the data signal on the second data line 22, which are disposed to overlap along the thickness direction of the substrate 101 are the same, and can be both positive or negative.
  • the display device further includes a light shielding portion 80, a first insulating layer 102, an active layer 103, a second insulating layer 104, a gate layer 105, a gate insulating layer 106, a first data line 21, a third insulating layer 107, a second data line 22, and a drain 23, which are sequentially arranged on the substrate 101, wherein the first sub-pixel 31 is connected to the first data line 21, the source 21 of the first sub-pixel 31 is arranged in the same layer as the first data line 21, and the drain 23 is arranged in the same layer as the second data line 22.
  • the second sub-pixel 32 is connected to the second data line 22, and correspondingly, the source 22 of the second sub-pixel 32 is arranged in the same layer as the second data line 22, and the drain 23 is arranged in the same layer as the second data line 22, so as to reduce the space occupied by the data line 20 in the display area AA and improve the aperture ratio of the pixel.
  • the first sub-pixel 31 is connected to the first scan line 11
  • the second sub-pixel 32 is connected to the second scan line 12
  • the first sub-pixel 31 is connected to the first data line 21
  • the first sub-pixel 31 is located on the first side of the first data line 21/the second data line 22
  • the second sub-pixel 32 is connected to the overlapping second data line 22
  • the second sub-pixel 32 is located on the second side opposite to the first side of the second data line 22/the first data line 21, so that the first sub-pixel 31 and the second sub-pixel 32 are alternately connected to the first data line 21 and the second data line 22 along the first direction Y.
  • the first sub-pixel 31 is connected to the first scan line 11
  • the second sub-pixel 32 is connected to the second scan line 12
  • the first sub-pixel 31 is connected to the first data line 21
  • the second sub-pixel 32 is connected to the overlapping second data line 22
  • the first sub-pixel 31 and the second sub-pixel 32 are located on the same side of the second data line 22/first data line 21, so that the first sub-pixel 31 and the second sub-pixel 32 are alternately connected to the first data line 21 and the second data line 22 along the first direction Y.
  • the present application further provides a display device 200 .
  • the difference between the display device 200 and the display device 100 is that in the display device 200 , a plurality of first source driver chips 71 are respectively connected to a plurality of first data lines 21 , and a plurality of second source driver chips 72 are respectively connected to a plurality of second data lines 22 .
  • the display device 200 includes a plurality of scan lines 10, a plurality of data lines 20, and a plurality of sub-pixels 30.
  • the plurality of scan lines 10 include a first scan line 11 and a second scan line 12, and the first scan line 11 and the second scan line 12 are arranged at intervals along a first direction Y.
  • the plurality of data lines 20 include a first data line 21 and a second data line 22, and the first data line 21 and the second data line 22 are arranged at intervals along a second direction X.
  • the plurality of sub-pixels 30 include a first sub-pixel 31 and a second sub-pixel 32, and the first sub-pixel 31 is connected to the first scan line 11 and the first data line 21, and the second sub-pixel 32 is connected to the second scan line 12 and the second data line 22.
  • the first sub-pixel 31 and the second sub-pixel 32 are arranged alternately.
  • the first data lines 21 and the second data lines 22 are alternately arranged along the second direction X
  • the first scan lines 11 and the second scan lines 12 are alternately arranged along the first direction Y.
  • the first direction Y is the extension direction of the data lines 20
  • the second direction X is the extension direction of the scan lines 10 .
  • the pixel unit includes a first sub-pixel 31 and two second sub-pixels 32, or a second sub-pixel 32 and two first sub-pixels 31. That is, each pixel unit is driven by two data lines 20 (the first data line 21 and the second data line 22).
  • the display device 200 has a display area AA and a non-display area NA disposed around the display area AA.
  • the display area AA is provided with sub-pixels 30 and scan lines 10 and data lines 20 connected to the sub-pixels 30.
  • the non-display area NA is provided with a first driving module 40, a second driving module 50, a multi-stage cascaded first gate driving unit 61, a multi-stage cascaded second gate driving unit 62 and a source driving chip 70.
  • the first driving module 40 is connected to the first gate driving unit 61
  • the second driving module 50 is connected to the second gate driving unit 62
  • the first gate driving unit 61 and the second gate driving unit 62 are respectively located on opposite sides of the non-display area NA along the second direction X.
  • the first gate driving unit 61 is connected to at least two scan lines
  • the second gate driving unit 62 is connected to at least two scan lines 10.
  • the source driver chip 70 includes a plurality of first source driver chips 71 and a plurality of second source driver chips 72 .
  • the first driver module 40 is connected to the first source driver chip 71
  • the second driver module is connected to the second source driver chip 72
  • the source driver chip 70 is connected to the data line 20 .
  • the first gate driving unit 61 is connected to two adjacent first scan lines 11, and/or the second gate driving unit 62 is connected to two adjacent second scan lines 12.
  • a plurality of cascaded first gate driving units 61 and a plurality of cascaded second gate driving units 62 are respectively connected to corresponding clock signal lines CK (CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8...), and the first gate driving unit 61 and the second gate driving unit 62 of the same level are connected to the same clock signal line, for example, the first gate driving unit 61 of the first level and the second gate driving unit 62 of the first level are both connected to CK1.
  • the first gate driving unit 61 may also be connected to a plurality of first scan lines 11, and the second gate driving unit 62 may also be connected to a plurality of second scan lines 12.
  • the first driving module 40 and the second driving module 50 are located on opposite sides of the non-display area NA along the first direction Y.
  • the first driving module 40 is arranged on a side of the first source driving chip 71 away from the display area AA
  • the second driving module 50 is arranged on a side of the second source driving chip 72 away from the display area AA.
  • a plurality of first source driving chips 71 and a plurality of second source driving chips 72 are arranged at intervals along the second direction X.
  • the clock signal lines CK (CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, ...) connected to the multi-stage cascaded first gate driving units 61 in one-to-one correspondence sequentially input high-level signals to the corresponding first gate driving units 61, and the first gate driving units 61 sequentially output high-level scanning signals (Gate1, Gate2 ... GateMK) to the sub-pixels 30 of the corresponding rows under the control of the high-level clock signals.
  • high-level scanning signals Gate1, Gate2 ... GateMK
  • the clock signal lines CK (CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, ...) connected to the multi-stage cascaded second gate driving units 62 in one-to-one correspondence sequentially input high-level signals to the corresponding second gate driving units 62, and the second gate driving units 62 sequentially output high-level scanning signals (Gate1, Gate2 ... GateMK) to the sub-pixels 30 of the corresponding rows under the control of the high-level clock signals.
  • high-level scanning signals Gate1, Gate2 ... GateMK
  • a preset time interval is set between the time when the clock signal on the previous clock line of two adjacent clock lines changes from a high level to a low level and the time when the clock signal on the next clock line changes from a low level to a high level, so as to ensure that the clock signal on the previous clock line has switched to a low level before the clock signal on the next clock line changes to a high level, thereby avoiding display abnormalities caused by mischarging.
  • the charging time of the same pixel unit includes the scanning time of two rows of sub-pixels and the input of two data voltages, which is equivalent to the charging time of each pixel unit being twice the charging time of the pixel unit in the prior art.
  • the display device 200 provided in the present application sets a first data line 21 and a second data line 22, so that the first sub-pixel 31 is connected to the first data line 21, and the second sub-pixel 32 is connected to the second data line 22, so that the sub-pixels 30 in odd columns and the sub-pixels 30 in even columns are provided with data signals by different data lines 20, that is, on the basis of reducing the load of the data line 20, the charging time of the sub-pixel 30 is increased and the charging condition is improved, and at the same time, the stability of the signal transmission of the display device can be enhanced.
  • a display device provided by an embodiment of the present application is described in detail above.
  • the description of the above embodiment is only used to help understand the core idea of the present application, and the above description should not be construed as limiting the scope of protection of the present application.

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Abstract

一种显示装置（100），显示装置（100）包括第一扫描线（11）、第二扫描线（12）、第一数据线（21）、第二数据线（22）、第一子像素（31）以及第二子像素（32），第一子像素（31）包括第一薄膜晶体管（311），第二子像素（32）包括第二薄膜晶体管（321），第一薄膜晶体管（311）与第一扫描线（11）以及第一数据线（21）连接，第二薄膜晶体管（321）与第二扫描线（12）以及第二数据线连接（22）；第一薄膜晶体管（311）与第二薄膜晶体管（321）交错设置。

Description

显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示装置。
 背景技术
VR（VirtualReality，虚拟现实）利用仿真技术与计算机图形学人机接口技术、多媒体技术、传感技术以及网络技术等实现模拟用户视觉，使用户有身临其境的体验感。随着VR显示技术的不断发展，VR显示设备的分辨率越来越高，而现有的VR显示设备受硬件和软件的限制，无法提升VR显示设备的分辨率。
 发明概述
本申请提供一种显示装置，该显示装置能够提升分辨率，实现高分辨率的显示效果。
一方面，本申请的实施例提供一种显示装置，包括：多条扫描线、多条数据线以及多个子像素，多条所述扫描线包括第一扫描线以及第二扫描线，所述第一扫描线与所述第二扫描线沿第一方向间隔设置；多条所述数据线包括第一数据线以及第二数据线，所述第一数据线与所述第二数据线沿第二方向间隔设置；多个所述子像素包括第一子像素以及第二子像素，所述第一子像素包括第一薄膜晶体管，所述第二子像素包括第二薄膜晶体管，所述第一薄膜晶体管与所述第一扫描线以及所述第一数据线连接，所述第二薄膜晶体管与所述第二扫描线以及所述第二数据线连接；所述第一薄膜晶体管与所述第二薄膜晶体管交错设置。
可选地，在本申请的一些实施例中，所述第一薄膜晶体管的沟道的延伸方向与相邻的所述第二薄膜晶体管的沟道的延伸方向在所述第二方向上呈镜像对称。
可选地，在本申请的一些实施例中，所述第一数据线与所述第二数据线沿所述第二方向交替排布，且所述第一扫描线与所述第二扫描线沿所述第一方向交替排布。
可选地，在本申请的一些实施例中，多个所述子像素包括多个子像素组，所述子像素组包括第一子像素组以及第二子像素组，所述第一子像素组以及所述第二子像素组均包括第一子像素列以及第二子像素列，所述第一子像素列包括多个沿所述第一方向间隔设置的所述第一子像素，所述第二子像素列包括多个沿所述第一方向间隔设置的所述第二子像素；其中，所述第一子像素组与所述第二子像素组沿所述第二方向交替设置，且所述第一子像素组与所述第二子像素组在所述第二方向上呈镜像对称。
可选地，在本申请的一些实施例中，所述显示面板包括多个遮光部，所述遮光部与所述子像素组一一对应设置。
可选地，在本申请的一些实施例中，所述显示面板包括基板以及隔垫物，所述遮光部在所述基板上的正投影覆盖所述隔垫物在所述基板上的正投影，所述隔垫物设于沿所述第二方向相邻的两个所述第一子像素之间；和/或，所述隔垫物设于沿所述第二方向相邻的两个所述第二子像素之间。
可选地，在本申请的一些实施例中，所述隔垫物在所述基板上的正投影与所述第二扫描线在所述基板上的正投影至少部分交叠。
可选地，在本申请的一些实施例中，所述显示装置包括基板，所述第一数据线设于所述基板上，所述第二数据线设于所述第一数据线远离所述基板的一侧，所述第一数据线在所述基板上的正投影与所述第二数据线在所述基板上的正投影至少部分交叠。
可选地，在本申请的一些实施例中，所述显示装置具有显示区以及设于所述显示区周围的非显示区，所述显示区设有所述子像素，所述非显示区设有第一驱动模块、第二驱动模块、多级级联的第一栅极驱动单元以及多级级联的第二栅极驱动单元，所述第一驱动模块与所述第一栅极驱动单元连接，所述第二驱动模块与所述第二栅极驱动单元连接，所述第一栅极驱动单元以及所述第二栅极驱动单元分别位于所述非显示区沿所述第二方向的相对两侧；其中，所述第一栅极驱动单元与至少两条所述扫描线连接，且所述第二栅极驱动单元与至少两条所述扫描线连接。
可选地，在本申请的一些实施例中，所述扫描线包括第一子扫描线以及第二子扫描线，所述第一子扫描线与所述第二子扫描线沿所述第二方向间隔设置，所述第一子扫描线与所述第一栅极驱动单元连接，所述第二子扫描线与所述第二栅极驱动单元连接。
可选地，在本申请的一些实施例中，所述第一栅极驱动单元与相邻的两条所述第一子扫描线连接，所述第二栅极驱动单元与相邻的两条所述第二子扫描线连接。
可选地，在本申请的一些实施例中，所述第一栅极驱动单元与所述第一扫描线连接，所述第二栅极驱动单元与所述第二扫描线连接。
可选地，在本申请的一些实施例中，所述第一栅极驱动单元与相邻的两条所述第一扫描线连接；和/或，所述第二栅极驱动单元与相邻的两条所述第二扫描线连接。
可选地，在本申请的一些实施例中，所述非显示区还设有源极驱动芯片，所述源极驱动芯片包括多个第一源极驱动芯片以及多个第二源极驱动芯片，所述第一驱动模块与所述第一源极驱动芯片连接，所述第二动模块与所述第二源极驱动芯片连接，所述源极驱动芯片与所述数据线连接。
可选地，在本申请的一些实施例中，所述第一源极驱动芯片、所述第二源极驱动芯片、所述第一驱动模块以及所述第二驱动模块位于所述非显示区沿所述第一方向的同一侧。
可选地，在本申请的一些实施例中，多个所述第一源极驱动芯片分别与多条所述第一数据线连接，多个所述第二源极驱动芯片分别与多条所述第二数据线连接。
可选地，在本申请的一些实施例中，所述第一栅极驱动单元与相邻的两条所述第一扫描线连接；和/或，所述第二栅极驱动单元与相邻的两条第二扫描线连接。
可选地，在本申请的一些实施例中，所述第一驱动模块以及所述第二驱动模块位于所述非显示区沿所述第一方向的相对两侧。
可选地，在本申请的一些实施例中，所述子像素还包括开口区，所述开口区沿水平方向的截面形状为类“P”型。
可选地，在本申请的一些实施例中，所述第一子像素包括第一开口区，所述第二子像素包括第二开口区，沿所述第二方向相邻的两个所述第二开口区沿所述第一方向呈镜像对称，且沿所述第二方向相邻的两个所述第一开口区沿所述第一方向呈镜像对称。
有益效果
本申请提供的显示装置包括多条扫描线、多条数据线以及多个子像素，多条所述扫描线包括第一扫描线以及第二扫描线，所述第一扫描线与所述第二扫描线沿第一方向间隔设置；多条所述数据线包括第一数据线以及第二数据线，所述第一数据线与所述第二数据线沿第二方向间隔设置；多个所述子像素包括第一子像素以及第二子像素，所述第一子像素包括第一薄膜晶体管，所述第二子像素包括第二薄膜晶体管，所述第一薄膜晶体管与所述第一扫描线以及所述第一数据线连接，所述第二薄膜晶体管与所述第二扫描线以及所述第二数据线连接；所述第一薄膜晶体管与所述第二薄膜晶体管交错设置。本申请提供的显示装置通过设置第一数据线与第二数据线，使第一子像素与第一数据线连接，第二子像素与第二数据线连接，即，在不增加像素驱动电路的负载的基础上，使得奇数列的子像素与偶数列的子像素分别由不同的数据线提供数据信号，进而有效提升显示装置的分辨率，实现高分辨率的显示效果。
 附图说明
图1是本申请的实施例提供的显示装置的第一种示意图；
图2是本申请的实施例提供的显示装置中背光驱动电路的时序图；
图3是图1提供的显示装置中的子像素的第一种排布示意图；
图4是图1提供的显示装置中的子像素的第二种排布示意图；
图5是本申请的实施例提供的显示装置中的遮光部与隔垫物的示意图；
图6是本申请的实施例提供的显示装置中的数据线的排布的剖视图；
图7是本申请的实施例提供的显示装置中的子像素的第一种排布示意图；
图8是本申请的实施例提供的显示装置中的子像素的第二种排布示意图；
图9本申请的实施例提供的显示装置的第二种示意图；
图10是本申请的实施例提供的显示装置中像素驱动电路的时序图。
 本发明的实施方式
如图1所示，本申请的实施例提供一种显示装置100，显示装置100包括显示面板110，显示面板110包括：多条扫描线10、多条数据线20以及多个子像素30，多条扫描线10包括第一扫描线11以及第二扫描线12，第一扫描线11与第二扫描线12沿第一方向Y间隔设置。多条数据线20包括第一数据线21以及第二数据线22，第一数据线21与第二数据线22沿第二方向X间隔设置。多个子像素30包括第一子像素31以及第二子像素32，第一子像素31包括第一薄膜晶体管311，第二子像素32包括第二薄膜晶体管321，第一薄膜晶体管311与第一扫描线11以及第一数据线21连接，第二薄膜晶体管321与第二扫描线12以及第二数据线22连接。第一薄膜晶体管311与第二薄膜晶体管321交错设置。
本申请提供的显示装置通过设置第一数据线21与第二数据线22，使第一薄膜晶体管311与第一数据线21连接，第二薄膜晶体管321与第二数据线22连接，即，在不增加像素驱动电路的负载的基础上，使得奇数列的子像素30与偶数列的子像素30分别由不同的数据线20提供数据信号，进而有效提升显示装置的分辨率，实现高分辨率的显示效果。
在本申请的实施例中，第一数据线21与第二数据线22沿第二方向X交替排布，且第一扫描线11与第二扫描线12沿第一方向Y交替排布。具体地，第一方向Y为数据线20的延伸方向，第二方向X为扫描线10的延伸方向。
在本申请的实施例中，像素单元包括一个第一子像素31以及两个第二子像素32，或者，一个第二子像素32以及两个第一子像素31。即，每个像素单元均由两条数据线20（第一数据线21以及第二数据线22）进行驱动。
在本申请的实施例中，显示装置100具有显示区AA以及设于显示区AA周围的非显示区NA。显示区AA设有子像素30以及与子像素30连接的扫描线10与数据线20。非显示区NA设有第一驱动模块40、第二驱动模块50、多级级联的第一栅极驱动单元61以及多级级联的第二栅极驱动单元62，第一驱动模块40与第一栅极驱动单元61连接，第二驱动模块50与第二栅极驱动单元62连接，第一栅极驱动单元61以及第二栅极驱动单元62分别位于非显示区NA沿第二方向X的相对两侧。其中，第一栅极驱动单元61与至少两条扫描线10连接，且第二栅极驱动单元62与至少两条扫描线10连接。
在本申请的实施例中，扫描线10包括第一子扫描线13以及第二子扫描线14，第一子扫描线13与第二子扫描线14沿第二方向X间隔设置，第一子扫描线13与第一栅极驱动单元61连接，第二子扫描线14与第二栅极驱动单元62连接。具体地，第一扫描线11与第二扫描线12均包括第一子扫描线13以及第二子扫描线14。第一子扫描线13上连接的子像素30的数量与第二子扫描线14上连接的子像素30的数量相等，使得第一栅极驱动单元61与第二栅极驱动单元62的负载相同，避免由于负载差异引起显示装置亮度不均。
进一步地，第一子扫描线13的长度与第二子扫描线14的长度相等，第一子扫描线13上连接的多个子像素30与第二子扫描线14上连接的子像素30沿显示区AA的中轴线对称分布，进一步确保显示装置的亮度均一性。
在本申请的实施例中，第一栅极驱动单元61与相邻的两条第一子扫描线13连接，第二栅极驱动单元62与相邻的两条第二子扫描线14连接。具体地，第一栅极驱动单元61分别与第一扫描线11的第一子扫描线13以及相邻的第二扫描线12的第一子扫描线13连接，对应的，第二栅极驱动单元62分别与第一扫描线11的第二子扫描线14以及相邻的第二扫描线12的第二子扫描线14连接，使得同一像素单元由一个第一栅极驱动单元61或者一个第二栅极驱动单元62输入扫描信号，有利于提高子像素30的充电时间并增强栅极驱动电路的级传稳定性。
在本申请的实施例中，非显示区NA还设有源极驱动芯片70，源极驱动芯片70包括多个第一源极驱动芯片71以及多个第二源极驱动芯片72，第一驱动模块40与第一源极驱动芯片71连接，第二动模块与第二源极驱动芯片72连接，源极驱动芯片70与数据线20连接。
具体地，多个第一源极驱动芯片71以及多个第二源极驱动芯片72均沿第二方向X间隔排布，第一驱动模块40与第一源极驱动芯片71沿第一方向Y对应设置，第二驱动模块50与第二源极驱动芯片72沿第一方向Y对应设置。第一源极驱动芯片71/第二源极驱动芯片72分别与多条数据线20连接，使得同一像素单元中的三个或多个子像素30由同一第一栅极驱动单元61/第二栅极驱动单元62输入扫描信号，并由同一第一源极驱动芯片71/第二源极驱动芯片72输入数据信号，确保扫描信号与数据信号的同一性，避免信号输入差异引起的显示异常。
在本申请的实施例中，第一源极驱动芯片71、第二源极驱动芯片72、第一驱动模块40以及第二驱动模块50位于非显示区NA沿第一方向Y的同一侧。
在本申请的实施例中，显示装置还包括发光基板101，发光基板101包括多个发光区，发光区内设有多个发光器件，发光器件包括微型发光二极管或者次毫米发光二极管。每个发光区中的发光器件是否开启或亮暗程度与显示装置所显示的图像中对应位置的灰阶有关。在一帧显示画面的时间周期内，发光区依次发光，发光区发光的时间与显示数据写入时间同步，且发光区在显示数据写入时间的基础上延迟半帧的时间开始发光。发光器件所发出的光线的扩散范围介于相邻的1至3个发光区内。同时发光的发光区占所有发光区域的5%至25%。
在本申请的实施例中，显示装置还包括图像处理模块，图像处理模块用于对主机端输入的图像信号进行处理并向背光驱动电路输出图像数据，图像数据包括背光驱动信号以及同步信号，同步信号用于保证背光与显示图像的同步。如图2所示，一帧显示图像包括3个子帧，图像处理模块同时向3个子帧对应的背光驱动电路输出背光驱动信号和同步信号。具体地，图像处理模块新生成的子帧图像和背光数据，分别存储在对应的缓存器中。第一驱动模块以及第二驱动模块在图像处理模块输出的同步信号的控制下实现显示图像的同步。
在本申请的实施例中，驱动模块也可以为一个，在图像处理模块输出的同步信号的控制下控制第一源极驱动芯片与对应的第二源极驱动芯片同步输出数据信号，以及控制第一栅极驱动单元与对应的第二栅极驱动单元同步输出扫描信号，确保背光与显示面板按照预设的时序驱动，同时，确保多个子帧画面同步显示，避免图像数据不同步造成的画面异常。
如图3所示，第一薄膜晶体管311的沟道的延伸方向与相邻的第二薄膜晶体管321的沟道的延伸方向在第二方向X上呈镜像对称，使得第一薄膜晶体管311与第二薄膜晶体管321的设计图形一致，避免受制程波动影响使相邻的子像素30的设计图形不同进而子像素30中的薄膜晶体管的沟道长度不一致，导致器件性能出现差异，影响显示效果。
在本申请的实施例中，第一数据线21上连接的第一子像素31的数量与第二数据线22上连接的第二子像素32的数量相同。第一子像素31位于奇数行，第二子像素32位于偶数行。或者，第一子像素31位于偶数行，第二子像素32位于奇数行。
如图4所示，多个子像素30包括多个子像素组33，子像素组33包括第一子像素组331以及第二子像素组332，第一子像素组331以及第二子像素组332均包括第一子像素列以及第二子像素列，第一子像素列包括多个沿第一方向Y间隔设置的第一子像素31，第二子像素列包括多个沿第一方向Y间隔设置的第二子像素32。其中，第一子像素组331与第二子像素组332沿第二方向X交替设置，且第一子像素组331与第二子像素组332在第二方向X上呈镜像对称，即子像素组33包括四个像素列，子像素组33在第二方向X上分别包括第一子像素列、第二子像素列、第二子像素列以及第一子像素列。
在本申请的实施例中，相邻的两个第一子像素31在第二方向X上呈镜像对称，且相邻的两个第二子像素32在第二方向X上呈镜像对称。具体地，相邻的两个第一薄膜晶体管311的沟道的延伸方向在第二方向X上呈镜像对称，相邻的两个第二薄膜晶体管321的沟道的延伸方向在第二方向X上呈镜像对称，使得第一薄膜晶体管311与第二薄膜晶体管321的设计图形一致，避免受制程波动影响使相邻的子像素30的设计图形不同进而子像素30中的薄膜晶体管的沟道长度不一致，导致器件性能出现差异，影响显示效果。
在本申请的实施例中，第一数据线21上连接的第一子像素31的数量与第二数据线22上连接的第二子像素32的数量相同。一条第一数据线21上连接的第一子像素31的数量与一条第二数据线22上连接的第二子像素32的数量之和与沿第一方向Y间隔排布的扫描线的数量相等。其中，第一子像素31位于奇数行，第二子像素32位于偶数行。或者，第一子像素31位于偶数行，第二子像素32位于奇数行。
如图5所示，显示装置包括多个遮光部80，遮光部80与子像素组33一一对应设置。即，一个遮光部80与一个子像素组33中的非显示区对应设置。非显示区域包括扫描线10（第一扫描线11、第二扫描线12）、数据线20（第一数据线21、第二数据线22）、薄膜晶体管以及子像素30（第一子像素31、第二子像素32）之间的间隔区等。
在本申请的实施例中，同一子像素组33中沿第二方向X相邻的两个第二子像素32以及沿第二方向X相邻的两个第一子像素31为一重复单元，即，同一子像素组33中每四个呈“田”字型排布的子像素30为一重复单元。具体地，遮光部80也可以和重复单元一一对应设置，即，多个遮光部80呈阵列排布。
在本申请的实施例中，子像素30还包括开口区34。具体地，第一子像素31包括第一开口区341，第二子像素32包括第二开口区342，沿第二方向X相邻的两个第二开口区342沿第一方向Y呈镜像对称，沿第二方向X相邻的两个第一开口区341沿第一方向Y呈镜像对称。具体地，开口区34沿水平方向的截面形状为类“P”型。对应的，遮光部80对应于同一子像素组33中相邻两个第二薄膜晶体管321的位置呈类菱形。
在本申请的实施例中，显示装置包括基板101以及隔垫物90，遮光部80在基板101上的正投影覆盖隔垫物90在基板101上的正投影，隔垫物90设于沿第二方向X相邻的两个第二子像素32之间。具体地，隔垫物90设于同一子像素组33中相邻两个第二薄膜晶体管321之间，并位于遮光部80的类菱形区域内。
在本申请的实施例中，隔垫物90在基板101上的正投影与第二扫描线12在基板101上的正投影至少部分交叠。图5中相邻两个子像素组33中沿第二方向X相邻的两个第二子像素32之间设有一个隔垫物90，且隔垫物90在基板101上的正投影与第二扫描线12在基板101上的正投影部分交叠。
在本申请的实施例中，隔垫物90还可以设于沿第二方向X相邻的两个第一子像素31之间。具体地，相邻两个子像素组33中沿第二方向X相邻的两个第一子像素31之间可以设置多个隔垫物90，例如两个、三个、四个、五个、六个等。多个隔垫物90沿第一方向Y/第二方向X的横截面面积可以相等也可以不相等，即，多个隔垫物90的尺寸可以相同也可以不相同。隔垫物90设于遮光部80上，可以省去单独为隔垫物90设置的遮光部80，简化工艺的同时有利于提升像素的开口率。
在本申请的实施例中，隔垫物90还可以设于沿第二方向X相邻的两个第一子像素31之间以及沿第二方向X相邻的两个第二子像素32之间。
如图6所示，显示装置包括基板101，第一数据线21设于基板101上，第二数据线22设于第一数据线21远离基板101的一侧，第一数据线21在基板101上的正投影与第二数据线22在基板101上的正投影至少部分交叠。优选地，第一数据线21与第二数据线22沿基板101厚度方向交叠设置。进一步地，沿基板101厚度方向交叠设置第一数据线21上的数据信号的极性与第二数据线22上的数据信号的极性相同，可以同为正极性或负极性。
具体地，显示装置还包括依次设于基板101上的遮光部80、第一绝缘层102、有源层103、第二绝缘层104、栅极层105、栅极绝缘层106、第一数据线21、第三绝缘层107、第二数据线22以及漏极23，其中，第一子像素31与第一数据线21连接，第一子像素31的源极21与第一数据线21同层设置，漏极23与第二数据线22同层设置。第二子像素32与第二数据线22连接，对应的，第二子像素32的源极22与第二数据线22同层设置，漏极23与第二数据线22同层设置，以减少数据线20在显示区AA的空间占比，提升像素的开口率。
如图7所示，第一子像素31与第一扫描线11连接，第二子像素32与第二扫描线12连接，第一子像素31与第一数据线21连接，且第一子像素31位于第一数据线21/第二数据线22的第一侧，第二子像素32与叠置的第二数据线22连接，且第二子像素32位于与第二数据线22/第一数据线21的第一侧相对的第二侧，使得第一子像素31与第二子像素32沿第一方向Y与第一数据线21以及第二数据线22交错连接。
如图8所示，第一子像素31与第一扫描线11连接，第二子像素32与第二扫描线12连接，第一子像素31与第一数据线21连接，第二子像素32与叠置的第二数据线22连接，且第一子像素31与第二子像素32位于第二数据线22/第一数据线21的同一侧，使得第一子像素31与第二子像素32沿第一方向Y与第一数据线21以及第二数据线22交错连接。
如图9所示，本申请还提供一种显示装置200，显示装置200与显示装置100的区别在于，显示装置200中多个第一源极驱动芯片71分别与多条第一数据线21连接，多个第二源极驱动芯片72分别与多条第二数据线22连接。
具体地，显示装置200包括多条扫描线10、多条数据线20以及多个子像素30，多条扫描线10包括第一扫描线11以及第二扫描线12，第一扫描线11与第二扫描线12沿第一方向Y间隔设置。多条数据线20包括第一数据线21以及第二数据线22，第一数据线21与第二数据线22沿第二方向X间隔设置。多个子像素30包括第一子像素31以及第二子像素32，第一子像素31与第一扫描线11以及第一数据线21连接，第二子像素32与第二扫描线12以及第二数据线22连接。第一子像素31与第二子像素32交错设置。
在本申请的实施例中，第一数据线21与第二数据线22沿第二方向X交替排布，且第一扫描线11与第二扫描线12沿第一方向Y交替排布。具体地，第一方向Y为数据线20的延伸方向，第二方向X为扫描线10的延伸方向。
在本申请的实施例中，像素单元包括一个第一子像素31以及两个第二子像素32，或者，一个第二子像素32以及两个第一子像素31。即，每个像素单元均由两条数据线20（第一数据线21以及第二数据线22）进行驱动。
在本申请的实施例中，显示装置200具有显示区AA以及设于显示区AA周围的非显示区NA。显示区AA设有子像素30以及与子像素30连接的扫描线10与数据线20。非显示区NA设有第一驱动模块40、第二驱动模块50、多级级联的第一栅极驱动单元61、多级级联的第二栅极驱动单元62以源极驱动芯片70，第一驱动模块40与第一栅极驱动单元61连接，第二驱动模块50与第二栅极驱动单元62连接，第一栅极驱动单元61以及第二栅极驱动单元62分别位于非显示区NA沿第二方向X的相对两侧。其中，第一栅极驱动单元61与至少两条扫描线10连接，且第二栅极驱动单元62与至少两条扫描线10连接。源极驱动芯片70包括多个第一源极驱动芯片71以及多个第二源极驱动芯片72，第一驱动模块40与第一源极驱动芯片71连接，第二动模块与第二源极驱动芯片72连接，源极驱动芯片70与数据线20连接。
在本申请的实施例中，第一栅极驱动单元61与相邻的两条第一扫描线11连接，和/或，第二栅极驱动单元62与相邻的两条第二扫描线12连接。多个级联的第一栅极驱动单元61与多个级联的第二栅极驱动单元62分别与对应的时钟信号线CK（CK1，CK2，CK3，CK4，CK5，CK6，CK7，CK8......）连接，同一级的第一栅极驱动单元61与第二栅极驱动单元62与同一条时钟信号线连接，例如第一级第一栅极驱动单元61以及第一级第二栅极驱动单元62均与CK1连接。具体地，第一栅极驱动单元61也可以与多条第一扫描线11连接，第二栅极驱动单元62也可以与多条第二扫描线12连接。
在本申请的实施例中，第一驱动模块40以及第二驱动模块50位于非显示区NA沿第一方向Y的相对两侧。第一驱动模块40设于第一源极驱动芯片71远离显示区AA的一侧，第二驱动模块50设于第二源极驱动芯片72远离显示区AA的一侧。具体地，多个第一源极驱动芯片71以及多个第二源极驱动芯片72均沿第二方向X间隔排布。
如图10所示，与多级级联的第一栅极驱动单元61一一对应连接的时钟信号线CK（CK1，CK2，CK3，CK4，CK5，CK6，CK7，CK8......）依次向对应的第一栅极驱动单元61输入高电平信号，第一栅极驱动单元61在高电平的时钟信号的控制下依次向对应行的子像素30输出高电平的扫描信号（Gate1，Gate2...GateMK）。对应的，与多级级联的第二栅极驱动单元62一一对应连接的时钟信号线CK（CK1，CK2，CK3，CK4，CK5，CK6，CK7，CK8......）依次向对应的第二栅极驱动单元62输入高电平信号，第二栅极驱动单元62在高电平的时钟信号的控制下依次向对应行的子像素30输出高电平的扫描信号（Gate1，Gate2...GateMK）。其中，相邻两条时钟线中前一条时钟线上的时钟信号从高电平转为低电平到下一条时钟线上的时钟信号从低电平转为高电平之间间隔预设时间，以确保下一条时钟线上的时钟信号转为高电平之前上一条时钟线上的时钟信号已切换为低电平，避免出现错充现象造成的显示异常。由于同一像素单元中的子像素分别与相邻的两条扫描线以及两条数据线连接，因而同一像素单元的充电时间包括两行子像素的扫描时间以及两次数据电压的输入，相当于每个像素单元的充电时间是现有技术中的像素单元的充电时间的两倍。
本申请提供的显示装置200通过设置第一数据线21与第二数据线22，使第一子像素31与第一数据线21连接，第二子像素32与第二数据线22连接，使得奇数列的子像素30与偶数列的子像素30分别由不同的数据线20提供数据信号，即，在减少数据线20的负载的基础上，提升子像素30的充电时间进而改善充电情况，同时可以增强显示装置信号传输的稳定性。
以上对本申请的实施例所提供的一种显示装置进行了详细介绍，以上实施例的说明只是用于帮助理解本申请的核心思想，上述说明不应被理解为对本申请的保护范围的限制。

Claims (20)

  1. 一种显示装置，其包括显示面板，所述显示面板包括：
    多条扫描线，所述扫描线包括第一扫描线以及第二扫描线，所述第一扫描线与所述第二扫描线沿第一方向间隔设置；
    多条数据线，所述数据线包括第一数据线以及第二数据线，所述第一数据线与所述第二数据线沿第二方向间隔设置；
    多个子像素，多个所述子像素包括第一子像素以及第二子像素，所述第一子像素包括第一薄膜晶体管，所述第二子像素包括第二薄膜晶体管，所述第一薄膜晶体管与所述第一扫描线以及所述第一数据线连接，所述第二薄膜晶体管与所述第二扫描线以及所述第二数据线连接；
    所述第一薄膜晶体管与所述第二薄膜晶体管交错设置。
  2. 根据权利要求1所述的显示装置，其中，所述第一薄膜晶体管的沟道的延伸方向与相邻的所述第二薄膜晶体管的沟道的延伸方向在所述第二方向上呈镜像对称。
  3. 根据权利要求2所述的显示装置，其中，所述第一数据线与所述第二数据线沿所述第二方向交替排布，且所述第一扫描线与所述第二扫描线沿所述第一方向交替排布。
  4. 根据权利要求2所述的显示装置，其中，多个所述子像素包括多个子像素组，所述子像素组包括第一子像素组以及第二子像素组，所述第一子像素组以及所述第二子像素组均包括第一子像素列以及第二子像素列，所述第一子像素列包括多个沿所述第一方向间隔设置的所述第一子像素，所述第二子像素列包括多个沿所述第一方向间隔设置的所述第二子像素；
    其中，所述第一子像素组与所述第二子像素组沿所述第二方向交替设置，且所述第一子像素组与所述第二子像素组在所述第二方向上呈镜像对称。
  5. 根据权利要求4所述的显示装置，其中，所述显示面板包括多个遮光部，所述遮光部与所述子像素组一一对应设置。
  6. 根据权利要求5所述的显示装置，其中，所述显示面板包括基板以及隔垫物，所述遮光部在所述基板上的正投影覆盖所述隔垫物在所述基板上的正投影，所述隔垫物设于沿所述第二方向相邻的两个所述第一子像素之间；
    和/或，所述隔垫物设于沿所述第二方向相邻的两个所述第二子像素之间。
  7. 根据权利要求6所述的显示装置，其中，所述隔垫物在所述基板上的正投影与所述第二扫描线在所述基板上的正投影至少部分交叠。
  8. 根据权利要求1所述的显示装置，其中，所述显示面板包括基板，所述第一数据线设于所述基板上，所述第二数据线设于所述第一数据线远离所述基板的一侧，所述第一数据线在所述基板上的正投影与所述第二数据线在所述基板上的正投影至少部分交叠。
  9. 根据权利要求4所述的显示装置，其中，所述显示装置具有显示区以及设于所述显示区周围的非显示区，所述显示区设有所述子像素，所述非显示区设有第一驱动模块、第二驱动模块、多级级联的第一栅极驱动单元以及多级级联的第二栅极驱动单元，所述第一驱动模块与所述第一栅极驱动单元连接，所述第二驱动模块与所述第二栅极驱动单元连接，所述第一栅极驱动单元以及所述第二栅极驱动单元分别位于所述非显示区沿所述第二方向的相对两侧；
    其中，所述第一栅极驱动单元与至少两条所述扫描线连接，且所述第二栅极驱动单元与至少两条所述扫描线连接。
  10. 根据权利要求9所述的显示装置，其中，所述扫描线包括第一子扫描线以及第二子扫描线，所述第一子扫描线与所述第二子扫描线沿所述第二方向间隔设置，所述第一子扫描线与所述第一栅极驱动单元连接，所述第二子扫描线与所述第二栅极驱动单元连接。
  11. 根据权利要求10所述的显示装置，其中，所述第一栅极驱动单元与相邻的两条所述第一子扫描线连接，所述第二栅极驱动单元与相邻的两条所述第二子扫描线连接。
  12. 根据权利要求9所述的显示装置，其中，所述第一栅极驱动单元与所述第一扫描线连接，所述第二栅极驱动单元与所述第二扫描线连接。
  13. 根据权利要求9所述的显示装置，其中，所述第一栅极驱动单元与相邻的两条所述第一扫描线连接；
    和/或，所述第二栅极驱动单元与相邻的两条所述第二扫描线连接。
  14. 根据权利要求9所述的显示装置，其中，所述非显示区还设有源极驱动芯片，所述源极驱动芯片包括多个第一源极驱动芯片以及多个第二源极驱动芯片，所述第一驱动模块与所述第一源极驱动芯片连接，所述第二动模块与所述第二源极驱动芯片连接，所述源极驱动芯片与所述数据线连接。
  15. 根据权利要求14所述的显示装置，其中，所述第一源极驱动芯片、所述第二源极驱动芯片、所述第一驱动模块以及所述第二驱动模块位于所述非显示区沿所述第一方向的同一侧。
  16. 根据权利要求14所述的显示装置，其中，多个所述第一源极驱动芯片分别与多条所述第一数据线连接，多个所述第二源极驱动芯片分别与多条所述第二数据线连接。
  17. 根据权利要求16所述的显示装置，其中，所述第一栅极驱动单元与相邻的两条所述第一扫描线连接；
    和/或，所述第二栅极驱动单元与相邻的两条第二扫描线连接。
  18. 根据权利要求16所述的显示装置，其中，所述第一驱动模块以及所述第二驱动模块位于所述非显示区沿所述第一方向的相对两侧。
  19. 根据权利要求1所述的显示装置，其中，所述子像素还包括开口区，所述开口区沿水平方向的截面形状为类“P”型。
  20. 根据权利要求19所述的显示装置，其中，所述第一子像素包括第一开口区，所述第二子像素包括第二开口区，沿所述第二方向相邻的两个所述第二开口区沿所述第一方向呈镜像对称，且沿所述第二方向相邻的两个所述第一开口区沿所述第一方向呈镜像对称。
PCT/CN2023/096763 2023-05-19 2023-05-29 显示装置 Ceased WO2024239353A1 (zh)

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