WO2024229666A1 - 显示面板、显示装置及裂纹检测方法 - Google Patents

显示面板、显示装置及裂纹检测方法 Download PDF

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Publication number
WO2024229666A1
WO2024229666A1 PCT/CN2023/092832 CN2023092832W WO2024229666A1 WO 2024229666 A1 WO2024229666 A1 WO 2024229666A1 CN 2023092832 W CN2023092832 W CN 2023092832W WO 2024229666 A1 WO2024229666 A1 WO 2024229666A1
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WIPO (PCT)
Prior art keywords
line
sub
detection
electrically connected
display area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/092832
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English (en)
French (fr)
Inventor
卢玉群
李泽亮
鲍建东
王伟
秦少杰
谭华
叶子进
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202380009038.2A priority Critical patent/CN119301665A/zh
Priority to US18/727,704 priority patent/US20260188151A1/en
Priority to PCT/CN2023/092832 priority patent/WO2024229666A1/zh
Publication of WO2024229666A1 publication Critical patent/WO2024229666A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/90—Assemblies of multiple devices comprising at least one organic light-emitting element
    • H10K59/95—Assemblies of multiple devices comprising at least one organic light-emitting element wherein all light-emitting elements are organic, e.g. assembled OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present invention relates to the field of display technology, and in particular to a display panel, a display device and a crack detection method.
  • a detection module or circuit is usually set up around the periphery of the display panel to detect whether there are crack defects in the periphery (edge area) of the display panel during production and transportation.
  • the following two detection methods are usually used: eddy current detection (ET detection) and resistance detection.
  • Eddy current detection is to determine whether there are cracks around the panel by detecting whether there are bright lines on the screen through the panel crack detection (PCD, Panel Crack Detection) circuit; resistance detection is to detect the resistance between the PCD circuits, and determine whether there are cracks by whether the resistance value is abnormal.
  • PCD Panel Crack Detection
  • resistance detection is to detect the resistance between the PCD circuits, and determine whether there are cracks by whether the resistance value is abnormal.
  • the above detection methods can only detect whether there are crack defects in the edge area, and cannot accurately locate the location of the defect. For example, for large-size display panels, staff need to use a microscope to slowly search for the crack location in the entire edge area of the display panel, which will consume a lot
  • Embodiments of the present disclosure provide a display panel, a display device, and a crack detection method.
  • this embodiment provides a display panel, including: a substrate, a plurality of sub-pixels and a plurality of data lines, at least one first detection line and at least one first detection control unit.
  • the substrate includes a display area and a peripheral area located outside the display area.
  • the plurality of sub-pixels and the plurality of data lines are located in the display area, the plurality of sub-pixels and the plurality of data lines are electrically connected, and at least one of the plurality of sub-pixels includes: a pixel circuit and a light-emitting element, the pixel circuit and the light-emitting element are electrically connected, and are configured to drive the light-emitting element to emit light.
  • At least one first detection line and at least one first detection control unit are located in the peripheral area, and at least one first detection control unit is electrically connected to at least one first detection line, and is configured to provide a first test signal to at least one first detection line.
  • At least one first detection line is electrically connected to a plurality of sub-pixels in a display area in any of the following ways: at least one first detection line is electrically connected to anodes of light-emitting elements of a plurality of sub-pixels in the display area; at least one first detection line is electrically connected to sources of data writing transistors of pixel circuits of a plurality of sub-pixels in the display area; at least one first detection line is electrically connected to a plurality of data lines in the display area, wherein at least one of the plurality of data lines is electrically connected to a plurality of sub-pixels arranged along a first direction, and at least one first detection line is located at least in peripheral areas on opposite sides of the display area along the first direction.
  • the at least one first detection line includes: a first main line and a plurality of first sub-lines electrically connected to the first main line, each first sub-line being electrically connected to at least one sub-pixel of the display area; and the plurality of first sub-lines being arranged sequentially along an extension direction of the first main line.
  • a gate driving circuit is further disposed in the peripheral region.
  • the first main line is located on a side of the gate driving circuit close to the display region, and a portion of each first sub-line is located on a side of the gate driving circuit away from the display region.
  • a gate driving circuit is further disposed in the peripheral region.
  • the first main line is located on a side of the gate driving circuit away from the display region, and the plurality of first sub-lines are located on a side of the first main line close to the display region.
  • the plurality of sub-pixels electrically connected to the plurality of first sub-lines of the first detection line include: A plurality of sub-pixels in the display area are closest to the first main line and are arranged along an extending direction of the first main line.
  • each first sub-line includes at least: a first line segment, a second line segment, and a first cross-line, wherein two ends of the first cross-line are electrically connected to the first line segment and the second line segment, respectively, the first line segment is located on a side of the gate drive circuit away from the display area, the second line segment is located on a side of the gate drive circuit close to the display area, and the orthographic projection of the first cross-line on the substrate at least partially overlaps with the orthographic projection of the gate drive circuit on the substrate; the first cross-line is located on a side of the first line segment and the second line segment close to the substrate.
  • the display panel in a direction perpendicular to the display panel, includes at least: a substrate and a bottom light-shielding metal layer, a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate.
  • the first crossover line is located in the bottom light-shielding metal layer, and the first line segment and the second line segment are located in the first gate metal layer.
  • the at least one first detection control unit includes: a first detection transistor, a gate of the first detection transistor is electrically connected to a first detection control line, a first electrode of the first detection transistor is electrically connected to a first test signal transmission line, and a second electrode of the first detection transistor is electrically connected to the first detection line.
  • the display panel further includes: a second detection line located in the peripheral area and at least one second detection control unit; the at least one second detection control unit is electrically connected to the second detection line and configured to provide a second test signal to the second detection line.
  • the second detection line is electrically connected to the plurality of sub-pixels in the display area.
  • the connection mode of the second detection line to the plurality of sub-pixels in the display area is different from the connection mode of the first detection line to the plurality of sub-pixels in the display area.
  • the second detection line includes: a second main line and a plurality of second sub-lines electrically connected to the second main line; each second sub-line is electrically connected to at least one sub-pixel of the display area, and the plurality of second sub-lines are sequentially arranged along an extension direction of the second main line.
  • the extension direction of the second main line intersects with an extension direction of a first main line of the first detection line.
  • the plurality of first sub-lines of the at least one first detection line are electrically connected to anodes of light-emitting elements of a plurality of sub-pixels of the display area in a one-to-one correspondence.
  • the plurality of second sub-lines of the second detection line are electrically connected to sources of data writing transistors of pixel circuits of a plurality of sub-pixels of the display area in a one-to-one correspondence.
  • the plurality of first sub-lines of the at least one first detection line are electrically connected to the plurality of data lines of the display area in a one-to-one correspondence; the plurality of data lines extend along the first direction.
  • the plurality of second sub-lines of the second detection line are electrically connected to the plurality of first power lines of the display area in a one-to-one correspondence; the plurality of first power lines extend along a second direction, and the second direction intersects the first direction.
  • the peripheral area is further provided with a first power border line.
  • the second main line is located on a side of the first power border line close to the display area, and a portion of each second sub-line is located on a side of the first power border line away from the display area.
  • the peripheral area is further provided with a first power border line.
  • the second main line is located on a side of the first power border line away from the display area, and the plurality of second sub-lines are located on a side of the second main line close to the display area.
  • the plurality of sub-pixels electrically connected to the plurality of second sub-lines of the second detection line include: a plurality of sub-pixels in the display area that are closest to the second main line and arranged along an extension direction of the second main line.
  • each second sub-line includes at least: a third line segment, a fourth line segment, and a third cross-line, wherein two ends of the third cross-line are electrically connected to the third line segment and the fourth line segment, respectively, the third line segment is located on a side of the first power border line away from the display area, the fourth line segment is located on a side of the first power border line close to the display area, and the third cross-line is located at a position where the orthographic projection of the substrate is parallel to the first power border line on the substrate.
  • the orthographic projections of the third line segment at least partially overlap; the third cross-line is located on a side of the third line segment and the fourth line segment close to the substrate.
  • the display panel in a direction perpendicular to the display panel, includes at least: a substrate and a bottom light-shielding metal layer, a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate.
  • the third crossover line is located in the bottom light-shielding metal layer, and the third line segment and the fourth line segment are located in the first gate metal layer.
  • the second detection control unit includes: a second detection transistor, a gate of the second detection transistor is electrically connected to a second detection control line, a first electrode of the second detection transistor is electrically connected to a second test signal transmission line, and a second electrode of the second detection transistor is electrically connected to the second detection line.
  • this embodiment provides a display device, including the display panel as described above.
  • the present embodiment provides a crack detection method, which is applied to the display panel as described above, including: providing a first test signal to a first detection line through a first detection control unit; determining whether there are cracks in the surrounding area and the location of the cracks based on the luminous state of multiple sub-pixels electrically connected to the first detection line.
  • the crack detection method further includes: providing a second test signal to a second detection line through a second detection control unit; and determining whether there is a crack in the peripheral area and the location of the crack based on the light emitting state of multiple sub-pixels electrically connected to the second detection line.
  • the present embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, at least one first detection line and at least one first detection control unit.
  • the substrate comprises a display area and a peripheral area located outside the display area.
  • a plurality of sub-pixels are located in the display area.
  • At least one first detection line and at least one first detection control unit are located in the peripheral area, and the at least one first detection control unit is electrically connected to the at least one first detection line and configured to provide a first test signal to the at least one first detection line.
  • the at least one first detection line is electrically connected to the plurality of sub-pixels in the display area.
  • the at least one first detection line comprises: a first main line, and a plurality of first sub-lines electrically connected to the first main line, the plurality of first sub-lines extending to the display area, and each first sub-line being electrically connected to at least one sub-pixel in the display area.
  • a portion of a line segment of at least one of the plurality of first sub-lines is located on a side of the first main line away from the display area.
  • a gate driving circuit is further disposed in the peripheral region.
  • the first main line is located on a side of the gate driving circuit close to the display region, and a portion of each first sub-line is located on a side of the gate driving circuit away from the display region.
  • the display panel further includes: a second detection line located in the peripheral area and at least one second detection control unit, the at least one second detection control unit being electrically connected to the second detection line and configured to provide a second test signal to the second detection line.
  • the second detection line is electrically connected to the plurality of sub-pixels in the display area.
  • the connection mode of the second detection line to the plurality of sub-pixels in the display area is different from the connection mode of the first detection line to the plurality of sub-pixels in the display area.
  • the second detection line includes: a second main line and a plurality of second sub-lines electrically connected to the second main line; each second sub-line is electrically connected to at least one sub-pixel of the display area, and the plurality of second sub-lines are sequentially arranged along an extension direction of the second main line.
  • the extension direction of the second main line intersects with an extension direction of a first main line of the first detection line.
  • FIG1 is a schematic plan view of a display panel according to at least one embodiment of the present disclosure.
  • FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG4 is a schematic diagram of partial wiring of a display panel according to at least one embodiment of the present disclosure.
  • FIG5 is a partial cross-sectional schematic diagram of the first sub-line shown in FIG4 ;
  • FIG6 is a partial cross-sectional schematic diagram of a display area of at least one embodiment of the present disclosure.
  • FIG. 7 is another partial wiring diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG8 is a partial cross-sectional schematic diagram of the second sub-line shown in FIG7;
  • FIG9 is a schematic diagram showing the connection between the second sub-line and the pixel circuit according to at least one embodiment of the present disclosure
  • FIG10A is a schematic diagram of a pixel circuit after a semiconductor layer is formed in FIG9 ;
  • FIG10B is a schematic diagram of the pixel circuit after the first gate metal layer is formed in FIG9 ;
  • FIG10C is a schematic diagram of the pixel circuit after the second gate metal layer is formed in FIG9 ;
  • FIG10D is a schematic diagram of the pixel circuit after the first source-drain metal layer is formed in FIG9 ;
  • 11A and 11B are schematic diagrams of display patterns for crack detection in a third frame region and a fourth frame region according to at least one embodiment of the present disclosure
  • FIG12 is a schematic diagram of a display pattern of crack detection in a second border region according to at least one embodiment of the present disclosure
  • FIG13 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure.
  • FIG14 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure.
  • FIG15 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure.
  • FIG16 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure.
  • FIG17 is a schematic plan view of another display panel according to at least one embodiment of the present disclosure.
  • FIG18 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure.
  • FIG19 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source.
  • a channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • the gate electrode may also be called a control electrode.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.
  • the "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • a extends along direction B means "the main part of A extends along direction B".
  • the present embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels and a plurality of data lines, at least one first detection line and at least one first detection control unit.
  • the substrate comprises a display area and a peripheral area located outside the display area.
  • the plurality of sub-pixels and the plurality of data lines are located in the display area, the plurality of sub-pixels and the plurality of data lines are electrically connected, and the plurality of sub-pixels and the plurality of data lines are electrically connected.
  • At least one sub-pixel in a pixel includes: a pixel circuit and a light-emitting element, the pixel circuit and the light-emitting element are electrically connected, and are configured to drive the light-emitting element to emit light.
  • At least one first detection line and at least one first detection control unit are located in a peripheral area, and at least one first detection control unit is electrically connected to at least one first detection line, and is configured to provide a first test signal to at least one first detection line.
  • At least one first detection line is electrically connected to a plurality of sub-pixels in a display area in any of the following ways: at least one first detection line is electrically connected to anodes of light-emitting elements of a plurality of sub-pixels in a display area; at least one first detection line is electrically connected to sources of data writing transistors of pixel circuits of a plurality of sub-pixels in a display area; at least one first detection line is electrically connected to a plurality of data lines in the display area, wherein at least one of the plurality of data lines is electrically connected to a plurality of sub-pixels arranged along a first direction, and at least one first detection line is at least located in the peripheral area on opposite sides of the display area along the first direction.
  • the first detection line can be electrically connected to the anodes of the light-emitting elements of multiple sub-pixels in the display area.
  • the first detection line can be lit.
  • the first detection line cannot transmit the first test signal to the anode of the corresponding light-emitting element, and the corresponding light-emitting element does not emit light. In this way, the position of the edge crack can be located according to the position of the dark line in the display area.
  • the first detection line can be electrically connected to the source of the data write transistor of the pixel circuit of multiple sub-pixels in the display area.
  • the crack detection process when the source of the data write transistor of the pixel circuit receives the first test signal transmitted by the first detection line, the light-emitting element driven by the pixel circuit does not emit light.
  • the first detection line when there is a crack at the location of the first detection line, the first detection line cannot transmit the first test signal to the corresponding pixel circuit, and the light-emitting element driven by the pixel circuit can emit light. In this way, the position of the edge crack can be located according to the position of the bright line in the display area.
  • the first detection line can be electrically connected to multiple data lines in the display area, and the multiple data lines can extend along a first direction (e.g., horizontal wiring).
  • first direction e.g., horizontal wiring.
  • the pixel circuit connected to the data line can drive the light-emitting element not to emit light.
  • the first detection line cannot transmit the first test signal to the corresponding data line, and the pixel circuit connected to the data line can drive the light-emitting element to emit light. In this way, the position of the edge crack can be located according to the position of the bright line in the display area.
  • the display panel provided in this embodiment utilizes a first detection control unit to provide a first test signal to a first detection line, and the first detection line is electrically connected to multiple sub-pixels in the display area. Based on the voltage control of the first test signal and the display results of the multiple sub-pixels in the display area, it is possible to easily determine whether there are cracks in the peripheral area and accurately locate the position of the edge cracks in the peripheral area, thereby improving work efficiency.
  • FIG. 1 is a plan view schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • the display panel of the present embodiment may include: a display area AA, and a peripheral area BB surrounding the display area AA.
  • the peripheral area BB may include: a third frame area B3 and a fourth frame area B4 located on opposite sides of the display area AA along the first direction X, and a first frame area B1 and a second frame area B2 located on opposite sides of the display area AA along the second direction Y.
  • the first frame area B1 may also be referred to as a lower frame
  • the second frame area B2 may also be referred to as an upper frame
  • the third frame area B3 may also be referred to as a left frame
  • the fourth frame area B4 may also be referred to as a right frame.
  • the first frame area B1 is connected to the third frame area B3 and the fourth frame area B4
  • the second frame area B2 is connected to the third frame area B3 and the fourth frame area B4.
  • the display area AA may be a rectangle, such as a rounded rectangle.
  • this embodiment is not limited to this.
  • the display area may be a circle, an ellipse, or other shapes.
  • the third frame area B3 and the fourth frame area B4 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged along the direction of the display area AA.
  • the circuit area may be connected to Display area AA, the circuit area may include a gate drive circuit, for example, the gate drive circuit may include multiple cascaded shift registers, and the multiple shift registers may be electrically connected to the multiple gate lines GL in the display area AA.
  • the power line area is connected to the circuit area, and may include at least a low-level power line, and the low-level power line may extend in a direction parallel to the edge of the display area and be connected to the cathode of the display area AA.
  • the crack dam area may be connected to the power line area, and may include at least a plurality of cracks set on the composite insulating layer.
  • the cutting area may be connected to the crack dam area, and may include at least a cutting groove set on the composite insulating layer, and the cutting groove may be configured so that after all the film layers of the display panel are prepared, the cutting setting can be cut along the cutting groove respectively.
  • the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX may be configured to display a dynamic image or a still image.
  • the display area AA may be referred to as an active area.
  • the display panel may be a flexible panel, and thus the display panel may be deformable, such as curling, bending, folding, or rolling up.
  • the display area AA may include at least a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL.
  • the plurality of gate lines GL may extend along a first direction X
  • the plurality of data lines DL may extend along a second direction Y.
  • the orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate substrate may intersect to form a plurality of sub-pixel regions, and a sub-pixel PX may be provided in each sub-pixel region.
  • the plurality of data lines DL are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX.
  • the plurality of data lines DL may extend to the first frame area B1.
  • the plurality of gate lines GL are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate control signals to the plurality of sub-pixels PX.
  • the gate control signal may include a scan signal and a light emitting control signal.
  • the gate control signal may include a scan signal, a light emitting control signal, and a reset control signal.
  • the first direction X may be the extending direction (row direction) of the gate line GL in the display area AA
  • the second direction Y may be the column direction.
  • the first direction X and the second direction Y may intersect, for example, the first direction X and the second direction Y may be perpendicular to each other.
  • a pixel unit of display area AA may include three sub-pixels, and the three sub-pixels are respectively a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • this embodiment is not limited to this.
  • a pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square pattern.
  • this embodiment is not limited to this.
  • a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit.
  • the pixel circuit may include multiple transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • T in the above circuit structure refers to a thin film transistor
  • C refers to a capacitor
  • the number before T represents the number of thin film transistors in the circuit
  • the number before C represents the number of capacitors in the circuit.
  • the multiple transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.
  • a plurality of transistors in a pixel circuit may be low-temperature polysilicon thin film transistors, or may be oxide thin film transistors, or may be low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of polysilicon thin film transistors uses low temperature polysilicon (LTPS), and the active layer of oxide thin film transistors uses oxide semiconductors (Oxide).
  • LTPS low temperature polysilicon
  • Oxide oxide semiconductors
  • Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Integrating low temperature polysilicon thin film transistors and oxide thin film transistors on a display panel namely LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • LTPS+Oxide LTPO for short
  • the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc.
  • the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • Fig. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit of this example is described by taking a 7T1C structure as an example.
  • the pixel circuit of this example may include seven transistors (ie, first to seventh transistors T1 to T7) and a storage capacitor Cst.
  • the light emitting element EL may include an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.
  • the display panel may include: a first scan line GL1 , a second scan line GL2 , a third scan line GL3 , a data line DL, a first power line VDD, a second power line VSS, an emission control line EML, a first initial signal line INIT1 , and a second initial signal line INIT2 .
  • the first power line VDD can be configured to provide a constant first voltage signal Vdd to the pixel circuit
  • the second power line VSS can be configured to provide a constant second voltage signal Vss to the pixel circuit
  • the first voltage signal Vdd can be greater than the second voltage signal Vss.
  • the first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit;
  • the data line DL can be configured to provide a data signal to the pixel circuit;
  • the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit;
  • the second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit, and
  • the third scan line GL3 can be configured to provide a third scan signal SCAN3 to the pixel circuit.
  • the second scan line GL2 electrically connected to the pixel circuit of the nth row can be electrically connected to the first scan line GL1 electrically connected to the pixel circuit of the n-1th row, so as to be input with the first scan signal SCAN1(n-1), that is, the second scan signal SCAN2(n) and the first scan signal SCAN1(n-1) can be the same.
  • the third scan line GL3 of the pixel circuit of the nth row can be electrically connected to the first scan line GL1 of the pixel circuit of the nth row, so as to be input with the first scan signal SCAN1(n), that is, the third scan signal SCAN3(n) and the first scan signal SCAN1(n) can be the same.
  • n is an integer greater than 0. In this way, the signal lines of the display panel can be reduced, and a narrow frame design of the display panel can be realized.
  • this embodiment is not limited to this.
  • the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit
  • the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit.
  • the first initial signal can be different from the second initial signal.
  • the first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal Vdd and the second voltage signal Vss, but are not limited thereto.
  • the first initial signal and the second initial signal can be the same, and only the first initial signal line can be set to provide the first initial signal.
  • the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.
  • the third transistor T3 can also be called a driving transistor.
  • the gate of the fourth transistor T4 is electrically connected to the first scan line GL1, The first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3.
  • the fourth transistor T4 can also be called a data writing transistor.
  • the gate of the second transistor T2 is electrically connected to the first scan line GL1, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3.
  • the second transistor T2 can also be called a threshold compensation transistor.
  • the gate of the fifth transistor T5 is electrically connected to the light emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3.
  • the gate of the sixth transistor T6 is electrically connected to the light emission control line EML
  • the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3
  • the second electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting element EL.
  • the fifth transistor T5 and the sixth transistor T6 can also be called light emission control transistors.
  • the first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3.
  • the seventh transistor T7 is electrically connected to the anode of the light emitting element EL and is configured to reset the anode of the light emitting element EL.
  • the gate of the first transistor T1 is electrically connected to the second scan line GL2, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3.
  • the gate of the seventh transistor T7 is electrically connected to the third scan line GL3, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light emitting element EL.
  • the first transistor T1 and the seventh transistor T7 can also be referred to as reset control transistors.
  • the first plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second plate of the storage capacitor Cst is electrically connected to the first power supply line VDD.
  • the first node N1 is the connection point of the storage capacitor Cst
  • the first transistor T1, the third transistor T3 and the second transistor T2 the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3,
  • the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.
  • the working process of the pixel circuit is described below. Take the pixel circuit shown in FIG2 as an example where all the multiple transistors are P-type transistors.
  • the third scanning signal provided by the third scanning line GL3 may be the same as the first scanning signal provided by the first scanning line GL1.
  • the operation process of the pixel circuit may include: a first stage, a second stage, and a third stage.
  • the first stage is called the reset stage.
  • the second scan signal SCAN2 provided by the second scan line GL2 can be a low-level signal, which turns on the first transistor T1.
  • the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1 and clear the original data voltage in the storage capacitor Cst.
  • the first scan signal SCAN1 provided by the first scan line GL1 can be a high-level signal
  • the light control signal EM provided by the light control line EML can be a high-level signal, which turns off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the light-emitting element EL does not emit light.
  • the second stage is called the data writing stage or the threshold compensation stage.
  • the first scanning signal SCAN1 provided by the first scanning line GL1 can be a low level signal
  • the second scanning signal SCAN2 provided by the second scanning line GL2 and the light control signal EM provided by the light control line EML can both be high level signals
  • the data line DL outputs the data signal DATA.
  • the third transistor T3 since the first plate of the storage capacitor Cst is at a low level, the third transistor T3 is turned on.
  • the first scanning signal SCAN1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst, and the voltage of the first plate (i.e., the first node N1) of the storage capacitor Cst is Vdata-
  • the seventh transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light emitting element EL, and the anode of the light emitting element EL is electrically connected to the anode of the light emitting element EL.
  • the first transistor T1 is turned off by the second scanning line GL2.
  • the light emitting control signal EM provided by the light emitting control signal line EML is a high level signal, which turns off the fifth transistor T5 and the sixth transistor T6.
  • the third stage is called the light-emitting stage.
  • the light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal
  • the first scanning signal SCAN1 provided by the first scanning line GL1 and the second scanning signal SCAN2 provided by the second scanning line GL2 are high-level signals.
  • the light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the first voltage signal Vdd output by the first power line VDD provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting element EL to emit light.
  • the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [Vdd-Vdata] 2 .
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vdata is the data voltage output by the data line DL
  • Vdd is the first voltage signal output by the first power line VDD.
  • the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.
  • FIG3 is a schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • at least one sub-pixel of the display area AA may include: a pixel circuit 61 and a light-emitting element 62.
  • the light-emitting element 62 may be located on a side of the pixel circuit 61 away from the substrate.
  • the pixel circuit 61 is electrically connected to the light-emitting element 62 and may be configured to drive the corresponding light-emitting element 62 to emit light.
  • the light-emitting element 62 and the connected pixel circuit 61 may overlap at least partially in the positive projection on the substrate.
  • FIG3 is illustrated by taking a plurality of pixel circuits 61 and a plurality of light-emitting elements 62 as an example, and there may be no electrical connection relationship between the pixel circuit 61 and the light-emitting element 62 illustrated in FIG3.
  • a plurality of light-emitting elements 62 arranged in sequence along the first direction X may be referred to as a row of light-emitting elements
  • a plurality of pixel circuits 61 arranged in sequence along the first direction X may be referred to as a row of pixel circuits
  • a plurality of pixel circuits 61 arranged in sequence along the second direction Y may be referred to as a column of pixel circuits
  • a plurality of light-emitting elements 62 arranged in sequence along the second direction Y may be referred to as a column of light-emitting elements.
  • the first border area B1 may include: a signal access area B11.
  • the signal access area B11 may be configured to set an integrated circuit, for example, the integrated circuit may be a display driver integrated circuit (DDI, Display Driver Integration) or a touch and display driver integrated circuit (TDDI, Touch and Display Driver Integration).
  • the integrated circuit may be a display driver integrated circuit (DDI, Display Driver Integration) or a touch and display driver integrated circuit (TDDI, Touch and Display Driver Integration).
  • the first border area B1 may be provided with first detection control units 33a and 33b, second detection control units 34a and 34b, and a first power border line 51a.
  • the first power border line 51a may extend at least along the first direction X, and be located on a side of the signal access area B11 close to the display area AA in the second direction Y.
  • the first power border line 51a may be electrically connected to a plurality of first power lines extending along the second direction Y in the display area AA, and is configured to provide a first voltage signal to the plurality of first power lines.
  • the first detection control unit 33a and the second detection control unit 34a can be located in the first frame area B1 near the third frame area B3, and the first detection control unit 33b and the second detection control unit 34b can be located in the first frame area B near the fourth frame area B4.
  • the first detection control units 33a and 33b, and the second detection control units 34a and 34b can be located on the side of the signal access area B11 near the display area AA.
  • the first detection control unit 33a can be located near the second detection control unit 34a in the first direction X.
  • the first detection control unit 33b may be located on a side of the second detection control unit 34b in the first direction X close to the edge of the display panel.
  • the first detection control unit 33a may include: a first detection transistor M1.
  • the gate of the first detection transistor M1 may be electrically connected to the first detection control line 35a
  • the first electrode of the first detection transistor M1 may be electrically connected to the first test signal transmission line 36a
  • the second electrode of the first detection transistor M1 may be electrically connected to the first detection line 31a.
  • the first detection control line 35a may extend to the signal access area B11 and be electrically connected to a first detection control pin in the signal access area B11.
  • the first test signal transmission line 36a may extend to the signal access area B11 and be electrically connected to a first test signal pin in the signal access area B11.
  • the first detection control unit 33b may include: a first detection transistor M1’.
  • the gate of the first detection transistor M1’ may be electrically connected to the first detection control line 35b
  • the first electrode of the first detection transistor M1’ may be electrically connected to the first test signal transmission line 36b
  • the second electrode of the first detection transistor M1’ may be electrically connected to the first detection line 31b.
  • the first detection control line 35b may extend to the signal access area B11 and be electrically connected to another first detection control pin in the signal access area B11.
  • the first test signal transmission line 36b may extend to the signal access area B11 and be electrically connected to another first test signal pin in the signal access area B11.
  • the first detection control pins transmitting the same first detection control signal in the signal access area B11 may be electrically connected to each other, and the first test signal pins transmitting the same first test signal may be electrically connected to each other.
  • the second detection control unit 34a may include: a second detection transistor M2.
  • the gate of the second detection transistor M2 may be electrically connected to the second detection control line 37a
  • the first electrode of the second detection transistor M2 may be electrically connected to the second test signal transmission line 38a
  • the second electrode of the second detection transistor M2 may be electrically connected to the second detection line 32.
  • the second detection control line 37a may extend to the signal access area B11 and be electrically connected to a second detection control pin in the signal access area B11.
  • the second test signal transmission line 38a may extend to the signal access area B11 and be electrically connected to a second test signal pin in the signal access area B11.
  • the second detection control unit 34b may include: a second detection transistor M2’.
  • the gate of the second detection transistor M2’ may be electrically connected to the second detection control line 37b
  • the first electrode of the second detection transistor M2’ may be electrically connected to the second test signal transmission line 38b
  • the second electrode of the second detection transistor M2’ may be electrically connected to the second detection line 32.
  • the second detection control line 37b may extend to the signal access area B11 and be electrically connected to another second detection control pin in the signal access area B11.
  • the second test signal transmission line 38a may extend to the signal access area B11 and be electrically connected to another second test signal pin in the signal access area B11.
  • the second detection control pins transmitting the same second detection control signal in the signal access area B11 may be electrically connected to each other, and the second test signal pins transmitting the same second test signal may be electrically connected to each other.
  • the third frame area B3 may be provided with a gate drive circuit 41a, a frame initial signal line 42a, and a first detection line 31a.
  • the gate drive circuit 41a may include, for example, a scan drive circuit, and the scan drive circuit may include a plurality of scan shift registers arranged along the second direction Y, and the scan drive circuit may be configured to provide scan signals to a plurality of scan lines of the display area AA (for example, providing a first scan signal to a plurality of first scan lines GL1, providing a second scan signal to a plurality of second scan lines GL2, and providing a third scan signal to a plurality of third scan lines GL3).
  • the frame initial signal line 42a may be located on one side of the gate drive circuit 41a close to the display area AA.
  • the frame initial signal line 42a may include a first frame initial signal line that transmits a first initial signal, or may include a first frame initial signal line that transmits a first initial signal and a second frame initial signal line that transmits a second initial signal.
  • the first detection line 31a may include: a first main line 311a and a plurality of first sub-lines 312a.
  • FIG3 takes six first sub-lines 312a as an example for illustration, and the present embodiment does not limit the number of first sub-lines 312a.
  • the plurality of first sub-lines 312a are electrically connected to the first main line 311a.
  • the first main line 311a may extend at least along the second direction Y.
  • the plurality of first sub-lines 312a may be arranged in sequence along the second direction Y.
  • the first main line 311a may Located on the side of the gate drive circuit 41a and the initial signal line 42a of the frame close to the display area AA.
  • the first main line 311a can be located on the side of the initial signal line 42a of the frame away from the gate drive circuit 41a.
  • a portion of each first sub-line 312a can be located on the side of the gate drive circuit 41a away from the display area AA.
  • a portion of each first sub-line 312a can be located in the power line area of the third frame area B3, and on the side of the low-level power line away from the display area AA.
  • each first sub-line 312a After each first sub-line 312a is connected to the first main line 311a, it can extend along the first direction X to the side away from the display area AA, until it passes through the gate drive circuit 41a, and then the winding extends along the first direction X to the side close to the display area AA, and finally extends to the anode of the light-emitting element 62 of a sub-pixel in the display area AA.
  • This example uses the first sub-line 312a to design the winding at the edge away from the first main line 311a, which can help to accurately locate the edge crack position of the third frame area B3, thereby improving work efficiency.
  • FIG4 is a schematic diagram of a partial wiring of a display panel of at least one embodiment of the present disclosure.
  • FIG4 illustrates a winding method of a first sub-line.
  • the first sub-line 312a may include at least: a first line segment 3121, a second line segment 3122, a first cross-line 3123, a second cross-line 3124, and a first connecting segment 3125.
  • the second cross-line 3124, the first line segment 3121, the first cross-line 3123, the second line segment 3122, and the first connecting segment 3125 may be electrically connected in sequence.
  • the second cross-line 3124 may be electrically connected to the first main line 311a, and the first connecting segment 3125 may be electrically connected to the anode of the light-emitting element 62 of a sub-pixel of the display area AA.
  • the first cross-line 3123 and the second cross-line 3124 may extend at least along the first direction X
  • the first line segment 3121 may extend at least along the second direction Y
  • the second line segment 3122 and the first connecting segment 3125 may extend at least along the first direction X.
  • a portion of the first sub-line 312 a located on a side of the gate driving circuit 41 a away from the display area AA may include a first line segment 3121 .
  • the orthographic projections of the first cross-line 3123 and the second cross-line 3124 on the substrate may overlap with the orthographic projections of the gate drive circuit 41a and the frame initial signal line 42a on the substrate, and the orthographic projections of the first line segment 3121 and the second line segment 3122 on the substrate may not overlap with the orthographic projections of the gate drive circuit 41a and the frame initial signal line 42a on the substrate.
  • the first line segment 3121 may be located on the side of the gate drive circuit 41a away from the display area AA, and the second line segment 3122 and the first connecting segment 3125 may be located on the side of the frame initial signal line 42a close to the display area AA.
  • first cross-line 3123 and the second cross-line 3124 may be in the same layer structure
  • first line segment 3121 and the second line segment 3122 may be in the same layer structure
  • first connecting segment 3125 and the second line segment 3122 may be located in different film layers.
  • the first span 3123, the first line segment 3121, and the second span 3124 of the first sub-line 312a may form a fold.
  • the first sub-line may be a serpentine line having a plurality of folds.
  • a serpentine line is a meandering curve. For example, after one end of the line extends a distance in one direction, it bends and twists and extends a distance in the opposite direction to the direction, bends and twists again and extends in the direction, and repeatedly bends and twists several times to form a serpentine line.
  • the plurality of first sub-lines 312a of the first detection line 31a may be electrically connected to the light-emitting elements 62 of the plurality of sub-pixels in a one-to-one correspondence.
  • the light-emitting elements 62 of the plurality of sub-pixels connected to the first detection line 31a may be arranged in a column, for example, the light-emitting elements 62 of the plurality of sub-pixels connected to the first detection line 31a may include a column of light-emitting elements 62 closest to the third border area B3.
  • Each first sub-line 312a of the first detection line 31a may be electrically connected to a light-emitting element 62 independently. This example, by setting each first sub-line 312a to be electrically connected to the light-emitting element 62 independently, can facilitate accurate positioning of the edge crack position of the third border area B3 according to whether the light-emitting element 62 is lit.
  • the fourth border area B4 may be provided with a gate drive circuit 41b, a border initial signal line 42b, and a first detection line 31b.
  • the gate drive circuit 41b may, for example, include a light-emitting drive circuit, the light-emitting drive circuit may include a plurality of light-emitting shift registers arranged along the second direction Y, and the light-emitting drive circuit may be configured to provide a light-emitting control signal to a plurality of light-emitting control lines of the display area AA.
  • the border initial signal line 42b may be located on a side of the gate drive circuit 41b close to the display area AA.
  • the border initial signal line 42a and the border initial signal line 42b may be electrically connected to each other.
  • the first detection line 31b may include: a first main line 311b and a plurality of first sub-lines 312b.
  • FIG3 is illustrated by taking six first sub-lines 312b as an example, and the present embodiment does not limit the number of first sub-lines 312b.
  • a plurality of first sub-lines 312b are electrically connected to the first main line 311b.
  • the first main line 311b may extend at least along the second direction Y.
  • the first main line 311b may be located on the side of the gate drive circuit 41b and the frame initial signal line 42b close to the display area AA.
  • the first main line 311b may be located on the side of the frame initial signal line 42b away from the gate drive circuit 41b.
  • each first sub-line 312b may be located on the side of the gate drive circuit 41b away from the display area AA.
  • a portion of each first sub-line 312b may be located in the power line area of the fourth frame area B4, and on the side of the low-level power line away from the display area AA.
  • This example uses the first sub-line 312b to perform a winding design at the edge away from the first main line 311b, which can help accurately locate the edge crack position of the fourth frame area B4, thereby improving work efficiency.
  • the winding design of the first sub-line 312b can refer to the description of the first sub-line 312a, so it will not be repeated here.
  • the light-emitting elements 62 of the plurality of sub-pixels connected to the first detection line 31b may be arranged in a column, for example, a column of light-emitting elements 62 closest to the fourth border region B4 may be included.
  • Each first sub-line 312b of the first detection line 31b may be independently electrically connected to a light-emitting element 62.
  • the second frame area B2 may be provided with a first power frame line 51 b and a second detection line 32.
  • the first power frame line 51 b may extend at least along the first direction X.
  • the first power frame line 51 b may be electrically connected to a plurality of first power lines extending along the second direction Y in the display area AA.
  • the second detection line 32 may include: a second main line 321 and a plurality of second sub-lines 322.
  • FIG3 takes four second sub-lines 322 as an example for illustration, and the present embodiment does not limit the number of second sub-lines 322.
  • the plurality of second sub-lines 322 are electrically connected to the second main line 321.
  • the second main line 321 may extend at least along the first direction X.
  • the plurality of second sub-lines 322 may be arranged in sequence along the first direction X.
  • the second main line 321 may be located on a side of the first power border line 51b close to the display area AA.
  • each second sub-line 322 may be located on a side of the first power border line 51b away from the display area AA. After each second sub-line 322 is connected to the second main line 321, it extends along the second direction Y to a side away from the display area AA until it passes through the first power border line 51b, and then winds along the second direction Y to extend to a side close to the display area AA, and finally extends to be electrically connected to the pixel circuit 61 of a sub-pixel in the display area AA.
  • FIG. 7 is another partial wiring schematic diagram of the display panel of at least one embodiment of the present disclosure.
  • FIG. 7 illustrates a winding method of a second sub-line 322.
  • the second sub-line 322 may include at least: a third line segment 3221, a fourth line segment 3222, a third cross-line 3223, a fourth cross-line 3224, and a second connecting segment 3225.
  • the fourth cross-line 3224, the third line segment 3221, the third cross-line 3223, the fourth line segment 3222, and the second connecting segment 3225 may be electrically connected in sequence.
  • the fourth cross-line 3224 may be electrically connected to the second main line 321, and the second connecting segment 3225 may be electrically connected to the pixel circuit 61 of the sub-pixel of the display area AA.
  • the third cross-line 3223 and the fourth cross-line 3224 may extend at least along the second direction Y
  • the third line segment 3221 may extend at least along the first direction X
  • the fourth line segment 3222 and the second connecting segment 3225 may extend along the second direction Y.
  • a portion of the second sub-line 322 located on a side of the first power border line 51 b away from the display area AA may include a third line segment 3221 .
  • the orthographic projections of the third cross-line 3223 and the fourth cross-line 3224 on the substrate may overlap with the orthographic projection of the first power border line 51b on the substrate, and the orthographic projections of the third line segment 3221 and the fourth line segment 3222 on the substrate may not overlap with the orthographic projection of the first power border line 51b on the substrate.
  • the fourth line segment 3222 and the second connecting segment 3225 may be located on the side of the first power border line 51b away from the display area AA.
  • the third cross-line 3223 and the fourth cross-line 3224 may be in the same layer structure, the third line segment 3221 and the fourth line segment 3222 may be in the same layer structure, and the second connecting segment 3225 and the fourth line segment 3222 may be located in different film layers.
  • the third span 3223, the third line segment 3221 and the fourth span 3224 of the second sub-line 322 may form a fold.
  • this embodiment is not limited to this.
  • the second sub-line may be a serpentine line with multiple folds.
  • the plurality of second sub-lines 322 of the second detection line 32 can be electrically connected to the pixel circuits 61 of the plurality of sub-pixels in one-to-one correspondence.
  • the pixel circuits 61 of the plurality of sub-pixels connected to the second detection line 32 can be arranged in a row.
  • the pixel circuits 61 connected to the second detection line 32 can include pixel circuits other than the first and last pixel circuits in a row of pixel circuits 61 closest to the second border area B2.
  • the first pixel circuit in the row of pixel circuits can be electrically connected to a light-emitting element in a column of light-emitting elements closest to the third border area B3, and the last pixel circuit in the row of pixel circuits can be electrically connected to a light-emitting element in a column of light-emitting elements closest to the fourth border area B4.
  • the sub-pixels connected to the first detection lines 31a and 31b of this example are different from the sub-pixels connected to the second detection line 32 to avoid mutual influence between the detection effects of the first detection lines 31a and 31b and the second detection line 32.
  • each second sub-line 322 of the second detection line 32 can be electrically connected to the source of a data write transistor of a pixel circuit 61 (e.g., the fourth transistor T4 in the aforementioned pixel circuit).
  • Each second sub-line 322 can be electrically connected to the data write transistor of the pixel circuit 61 independently.
  • the second frame area B2 may also be provided with a first connection line 313.
  • the first detection line 31a in the third frame area B3 may be electrically connected to the first detection line 31b in the fourth frame area B4 through the first connection line 313.
  • the two ends of the first connection line 313 may be electrically connected to the first main line 311a of the first detection line 31a and the first main line 311b of the first detection line 31b, respectively.
  • the first connection line 313 may be located on the side of the first power frame line 51b close to the display area AA, for example, it may be located on the side of the second main line 321 of the second detection line 32 close to the first power frame line 51b.
  • this embodiment is not limited to this.
  • the first detection line 31a in the third frame area B3 and the first detection line 31b in the fourth frame area B4 are electrically connected by the first connection line 313, so that the first test signal can be transmitted around the third frame area B3, the second frame area B2 and the fourth frame area B4, which is beneficial to the wiring of the peripheral area and the edge crack detection of the peripheral area.
  • the display area AA may also be provided with second connecting lines 323a and 323b.
  • One end of the second main line 321 of the second detection line 32 of the second frame area B2 may be electrically connected to the second connecting line 323a, and electrically connected to the second detection control unit 34a through the second connecting line 323a.
  • the other end of the second main line 321 may be electrically connected to the second connecting line 323b, and electrically connected to the second detection control unit 34b through the second connecting line 323b.
  • FIG6 is a schematic partial cross-sectional view of a display area of at least one embodiment of the present disclosure.
  • FIG6 is taken as an example for illustration of two sub-pixels in the display area.
  • the display area of the display panel may include at least: a substrate 10, and a circuit structure layer 12, a light emitting structure layer 13, and a packaging structure layer 14 disposed on the substrate 10.
  • the circuit structure layer 12 may include: a barrier layer 101, a bottom shading metal (BSM, Bottom Shielding Metal) layer, a buffer layer 102, a semiconductor layer, a first gate insulating layer 103, a first gate metal layer, a second gate insulating layer 104, a second gate metal layer, an interlayer insulating (ILD) layer 105, a first source and drain metal layer, a first planar (PLN) layer 106, a second source and drain metal layer, and a second Planar layer 107.
  • BSM bottom shading metal
  • BSM Bottom Shielding Metal
  • the circuit structure layer 12 in Figure 6 is illustrated by taking a transistor 21 (for example, the sixth transistor in the pixel circuit of the aforementioned embodiment) and a first capacitor 22 (for example, the storage capacitor in the pixel circuit of the aforementioned embodiment) included in each sub-pixel as an example.
  • the blocking layer 101, the buffer layer 102, the first gate insulating layer 103, the second insulating layer 104, and the interlayer insulating layer 105 can be inorganic insulating layers
  • the first planar layer 106 and the second planar layer 107 can be organic insulating layers.
  • the blocking layer 101 and the buffer layer 102 can prevent harmful substances in the substrate 10 from invading the interior of the display panel, and can also increase the adhesion of the film layer in the display panel on the substrate 10.
  • this embodiment is not limited to this.
  • a passivation layer can also be arranged between the first source and drain metal layer and the second source and drain metal layer, and the passivation layer can be located on the side of the first planar layer close to the substrate.
  • the barrier layer 101, the buffer layer 102, the first gate insulating layer 103, the second insulating layer 104, and the interlayer insulating layer 105 can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer.
  • the first flat layer 106 and the second flat layer 107 can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the bottom light-shielding metal layer, the first gate metal layer and the second gate metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), and can be a single-layer structure.
  • the first source-drain metal layer and the second source-drain metal layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the semiconductor layer may be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology. This embodiment is not limited to this.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • sexithiophene polythiophene, etc.
  • the bottom light-shielding metal layer of the display area can be configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor.
  • the bottom light-shielding metal layer can include at least: a bottom light-shielding block 20, and the orthographic projection of the bottom light-shielding block 20 on the substrate 10 can cover the orthographic projection of the channel region of the active layer 210 of the transistor 21 on the substrate 10.
  • the semiconductor layer of the display area may include at least: an active layer 210 of the transistor 21.
  • the active layer 210 of the transistor 21 may include: a first region, a second region, and a channel region between the first region and the second region.
  • the first gate metal layer may include at least: a gate 213 of the transistor 21, and a first plate 221 of the first capacitor 22.
  • the orthographic projection of the gate 213 of the transistor 21 on the substrate 10 may cover the orthographic projection of the channel region of the active layer 210 on the substrate 10.
  • the second gate metal layer may include at least: a second plate 222 of the first capacitor 22.
  • the orthographic projections of the second plate 222 and the first plate 221 of the first capacitor 22 on the substrate 10 may at least partially overlap, for example, the two may overlap.
  • the first source-drain metal layer may include at least: a source 211 and a drain 212 of the transistor 21.
  • the interlayer insulating layer 105 may be provided with a plurality of vias (for example, including a first pixel via and a second pixel via) in the display area.
  • the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region of the active layer 210; the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the second pixel via may be removed to expose at least a portion of the surface of the second region of the active layer 210.
  • the source 211 of the transistor 21 may be electrically connected to the first region of the active layer 210 through the first pixel via, and the drain 212 may be electrically connected to the second region of the active layer 210 through the second pixel via.
  • the second source-drain metal layer may include at least: a first switching electrode 23.
  • the first switching electrode 23 may be electrically connected to the drain 212 of the transistor 21 of the pixel circuit through a third pixel via provided in the first planar layer 106.
  • the first switching electrode 23 can be electrically connected to the first electrode 131 (eg, anode) of the light emitting element through the fourth pixel via hole formed in the second planar layer 107.
  • the first switching electrode 23 can be used to realize electrical connection between the pixel circuit and the light emitting element.
  • the light emitting structure layer 13 of the display area may include: a pixel definition layer 134 and a plurality of light emitting elements.
  • each light emitting element may include: a stacked first electrode 131, an organic light emitting layer 132 and the second electrode 133.
  • the first electrode 131 of the light-emitting element may be an anode, and the first electrode 131 may be disposed on the second flat layer 107, and electrically connected to the first transfer electrode 23 through the fourth pixel via hole provided in the second flat layer 107.
  • the pixel definition layer 134 is disposed on the first electrode 131 and the second flat layer 107, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and one pixel opening may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed in a pixel opening and connected to the corresponding first electrode 131.
  • the second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132.
  • the organic light-emitting layer 132 may emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.
  • An isolation column layer may be further disposed on the side of the pixel definition layer 134 away from the substrate 10, and the isolation column layer may include a plurality of isolation columns (PS) 135.
  • PS isolation columns
  • the organic light-emitting layer 132 of the light-emitting element in the display area may include a light-emitting layer (EML, Emitting Layer), and one or more film layers including a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer).
  • HIL hole injection layer
  • HTL Hole Transport Layer
  • HBL Hole Block Layer
  • EBL Electron Block Layer
  • EIL Electron Injection Layer
  • ETL Electron Transport Layer
  • the light-emitting layers of light-emitting elements of different colors may be different.
  • a red light-emitting element includes a red light-emitting layer
  • a green light-emitting element includes a green light-emitting layer
  • a blue light-emitting element includes a blue light-emitting layer.
  • the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer
  • the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer may be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated.
  • the organic light-emitting layer may be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or may be formed by an inkjet process.
  • FMM fine metal mask
  • Open Mask open mask
  • the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked.
  • the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials
  • the second encapsulation layer 142 may be made of organic materials
  • the second encapsulation layer 142 may be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element.
  • this embodiment is not limited to this.
  • the encapsulation structure layer may adopt a five-layer stacked structure of inorganic/organic/inorganic/organic/inorganic.
  • the display panel may further include: a touch structure layer 15 and a color filter layer 16 located on a side of the encapsulation structure layer 14 away from the substrate 10.
  • the color filter layer 16 may be located on a side of the touch structure layer 15 away from the encapsulation structure layer 14.
  • the color filter layer 16 may include: a plurality of filter units of different colors (for example, including a filter unit 163), a black matrix 162 located between different filter units, a color filter buffer layer (CBL) 161 located on a side of the black matrix 162 and the plurality of filter units close to the substrate 10, and a color filter protection layer (COC) 164 located on a side of the black matrix 162 and the plurality of filter units away from the substrate 10.
  • CBL color filter buffer layer
  • COC color filter protection layer
  • the plurality of filter units of the color filter layer 16 may include: a plurality of red filter units, a plurality of green filter units, and a plurality of blue filter units.
  • the filter units of different colors may correspond to light emitting elements of the light emitting structure layer 13 that emit different colors.
  • the blue filter unit may correspond to the blue light emitting element
  • the orthographic projection of the blue filter unit on the substrate may at least partially overlap with the orthographic projection of the light emitting area of the blue light emitting element on the substrate, for example, the orthographic projection of the blue filter unit on the substrate may cover the orthographic projection of the light emitting area of the blue light emitting element on the substrate.
  • the filter unit may allow a single color of light to pass through and absorb other colors of light.
  • the blue filter unit may allow blue light to pass through and absorb other colors of light.
  • FIG5 is a partial cross-sectional schematic diagram of the first sub-line shown in FIG4.
  • the first line segment 3121 and the second line segment 3122 of the first sub-line 312a may be located in the first gate metal layer, and the first cross-line 3123 may be located in the first gate metal layer.
  • the first line segment 3121 and the second line jumper 3124 may be located at the bottom light shielding metal layer, and the first connection segment 3125 may be located at the second source and drain metal layer, for example.
  • the first line segment 3121 may be electrically connected to one end of the first line jumper 3123 through the first connection via hole opened in the first gate insulation layer 103 and the buffer layer 102, and the first line jumper 3123 may extend from below the gate drive circuit 41a and the frame initial signal line 42a to cross the gate drive circuit 41a and the frame initial signal line 42a.
  • the gate drive circuit 41a may include a second capacitor, for example, and the second capacitor may include a first plate 271 located in the first gate metal layer and a second plate 272 located in the second gate metal layer.
  • the connection position of the first line segment 3121 and the first line jumper 3123 may be located on the side of the gate drive circuit 41a away from the display area.
  • the other end of the first line jumper 3123 may be electrically connected to the second line segment 3122 through the second connection via hole opened in the first gate insulation layer 103 and the buffer layer 102.
  • the connection position of the first crossover line 3123 and the second line segment 3122 may be located on the side of the gate driving circuit 41a and the frame initial signal line 42a close to the display area.
  • the second line segment 3122 may be electrically connected to the first connection segment 3125.
  • the first connection segment 3125 may be electrically connected to the second line segment 3122 located in the first gate metal layer through a third connection via hole provided in the second flat layer 107, the first flat layer 106, the interlayer insulating layer 105, and the second gate insulating layer 104.
  • the first connection segment 3125 after the first connection segment 3125 extends to the display area, it can be electrically connected to the anode 131 of a light-emitting element in the display area near the third frame area.
  • the anode 131 of the light-emitting element can be electrically connected to the first connection segment 3125 through the fourth connection via hole provided in the second flat layer 107, thereby achieving electrical connection between the anode 131 of the light-emitting element and the first sub-line 312a.
  • This example utilizes the first jumper 3123 and the second jumper 3124 arranged in the bottom shading metal layer to make the first sub-line jump in the area where the gate drive circuit and the frame initial signal line are located, which can avoid the influence of the first sub-line on the gate drive circuit and the frame initial signal line, and facilitate the wiring arrangement, which is conducive to saving space.
  • FIG8 is a partial cross-sectional schematic diagram of the second sub-line shown in FIG7.
  • the third line segment 3221 and the fourth line segment 3222 of the second sub-line 322 can be located in the first gate metal layer, and the third cross-line 3223 and the fourth cross-line 3224 can be located in the bottom light shielding metal layer.
  • the second connecting segment 3225 can be located in the second source-drain metal layer, for example.
  • the first power border line 51b can be located in the first source-drain metal layer, for example.
  • the third line segment 3221 of the second sub-line 322 can be electrically connected to one end of the third crossover 3223 through the fifth connection via provided in the first gate insulation layer 103 and the buffer layer 102, and the third crossover 3223 can extend from below the first power border line 51b to cross the first power border line 51b.
  • the connection position of the third line segment 3221 and the third crossover 3223 can be located on the side of the first power border line 51b away from the display area.
  • the other end of the third crossover 3223 can be electrically connected to the fourth line segment 3222 through the sixth connection via provided in the first gate insulation layer 103 and the buffer layer 102.
  • connection position of the third crossover 3223 and the fourth line segment 3222 can be located on the side of the first power border line 51b close to the display area AA.
  • the fourth line segment 3222 can be electrically connected to the second connection segment 3225.
  • the second connection segment 3225 can be electrically connected to the fourth line segment 3222 located in the first gate metal layer through a seventh connection via opened in the second planar layer 107, the first planar layer 106, the interlayer insulating layer 105 and the second gate insulating layer 104.
  • FIG9 is a schematic diagram of the connection between the second sub-line and the pixel circuit of at least one embodiment of the present disclosure.
  • FIG10A is a schematic diagram of the pixel circuit after the semiconductor layer is formed in FIG9.
  • FIG10B is a schematic diagram of the pixel circuit after the first gate metal layer is formed in FIG9.
  • FIG10C is a schematic diagram of the pixel circuit after the second gate metal layer is formed in FIG9.
  • FIG10D is a schematic diagram of the pixel circuit after the first source-drain metal layer is formed in FIG9.
  • the pixel circuit of this example may be the 7T1C pixel circuit shown in the aforementioned embodiment.
  • the semiconductor layer of the display area may include: active layers of multiple transistors of the pixel circuit (for example, including: active layer T10 of the first transistor of the pixel circuit of this row, active layer T20 of the second transistor, active layer T30 of the third transistor, active layer T40 of the fourth transistor, active layer T50 of the fifth transistor, active layer T60 of the sixth transistor, and active layer T70 of the seventh transistor, active layer T70' of the seventh transistor of the pixel circuit of the previous row, and active layer T10' of the first transistor of the pixel circuit of the next row).
  • the active layers of the seven transistors of the pixel circuit may be an integrated structure connected to each other.
  • the first gate metal layer of the display area may include at least: a first scan line GL1(n), a second scan line GL2(n), a third scan line GL3(n), and a light-emitting control line EML(n).
  • the second scan line GL2(n) may simultaneously serve as the gate of the first transistor T1 of the pixel circuit of this row and the gate of the seventh transistor T7' of the pixel circuit of the previous row.
  • the first scan line GL1(n) may simultaneously serve as the gate of the second transistor T2 of the pixel circuit of this row and the gate of the fourth transistor T4.
  • the third scan line GL3(n) may simultaneously serve as the gate of the seventh transistor T7 of the pixel circuit of this row and the gate of the first transistor T1' of the pixel circuit of the next row.
  • the light-emitting control line EML(n) may simultaneously serve as the gate of the fifth transistor T5 of the pixel circuit of this row and the gate of the sixth transistor T6.
  • the first plate 221 of the storage capacitor may simultaneously serve as the gate of the third transistor T3.
  • the second gate metal layer of the display region may include at least: a first initial signal line INIT1, a second plate 222 of the storage capacitor, and a protection block 24.
  • the protection block 24 may prevent other signals from interfering with the data signal.
  • the first source-drain metal layer of the display area may include at least: a data line DL, a first power line VDD, and a plurality of connection electrodes (e.g., a first connection electrode 251, a second connection electrode 252, a third connection electrode 253, and a fourth connection electrode 254).
  • the first connection electrode 251 may be electrically connected to the active layer T10 of the first transistor T1 and the first initial signal line INIT1.
  • the second connection electrode 252 may be electrically connected to the active layer T20 of the second transistor T2 and the gate of the third transistor T3.
  • the third connection electrode 253 may be electrically connected to the active layer T60 of the sixth transistor T6, and the third connection electrode 253 may be equivalent to the drain of the sixth transistor T6.
  • the fourth connection electrode 254 may be electrically connected to the first initial signal line INIT1 and the active layer T70 of the seventh transistor T7.
  • the data line DL and the first power line VDD may both extend along the second direction Y.
  • the data line DL may be electrically connected to the active layer of the fourth transistor T4.
  • the first power line VDD may be electrically connected to the protection block 24 , the second plate 222 of the storage capacitor, and the active layer T50 of the fifth transistor T5 .
  • the second source-drain metal layer of the display area may include at least: a first switching electrode 23, a second connection segment 3225 of a second sub-line of a second detection line.
  • the first switching electrode 23 may be electrically connected to the third connection electrode 253.
  • the second connection segment 3225 may be electrically connected to an active layer T40 of a data write transistor (i.e., a fourth transistor T4) of a pixel circuit.
  • the second connection segment 3225 may serve as a source of the data write transistor.
  • a second sub-line 322 may be independently connected to a data write transistor T4 of a pixel circuit, which may reduce interference with a normal display process.
  • the first detection transistor and the second detection transistor are both P-type transistors.
  • this embodiment is not limited to this.
  • the first detection transistor and the second detection transistor can both be N-type transistors; or, the first detection transistor is a P-type transistor and the second detection transistor is an N-type transistor; or, the first detection transistor is an N-type transistor and the second detection transistor is a P-type transistor.
  • the first detection transistors M1 and M1' can be controlled to be turned on by a first detection control signal, and the second detection transistors M2 and M2' can be controlled to be turned off by a second detection control signal.
  • the first detection transistors M1 and M1' provide a first test signal to the first detection lines 31a and 31b.
  • the transmission status of the first test signal on the first detection lines 31a and 31b can be determined according to the display effect of the light-emitting elements 62 connected to the first detection lines 31a and 31b in the display area, thereby locating the crack positions in the third border area B3 and the fourth border area B4 of the peripheral area.
  • 11A and 11B are schematic diagrams of display patterns for crack detection in the third border area and the fourth border area of at least one embodiment of the present disclosure.
  • the first detection lines 31a and 31b are each connected to a column of light-emitting elements 62 of sub-pixels as an example.
  • the first test signal transmitted by the first detection lines 31a and 31b can be normally provided to the anode of the connected light-emitting element 62, so that the connected light-emitting element 62 is displayed normally.
  • the first bright line L1 of the display area can indicate that there are no cracks in the third border area B3, and the second bright line L2 can indicate that there are no cracks in the fourth border area B4.
  • the first bright line L1 and the second bright line L2 can be bright lines that penetrate vertically.
  • the first sub-line of the first detection line wound at the crack position cannot transmit the first test signal to the corresponding light-emitting element in the display area, and the light-emitting element connected to the first sub-line at the crack position will not be lit, and a vertical non-penetrating bright line will appear in the display area, and the bright line at the position corresponding to the crack will be disconnected.
  • the crack at the first position W1 of the third frame area B3 can be located. If a crack occurs at the second position W2 of the fourth border area B4, the second sub-line 312b wound at the second position W2 cannot transmit the first test signal to the corresponding light-emitting element in the display area, and a second break L20 will exist on the second bright line L2 of the display area.
  • the crack at the second position W2 of the fourth border area B4 can be located based on the position of the second break L20.
  • the voltage Vg1 of the first detection control signal is set to -7V
  • the voltage Vpcd1 of the first test signal is set to 4.6V
  • the first voltage signal Vdd is set to 0V
  • the second voltage signal Vss is set to 0V
  • the data voltage Vdata is set to 0-5V
  • the voltage Vg2 of the second detection control signal is set to 7V
  • the voltage Vpcd2 of the second test signal is set to 0V.
  • This example can determine the crack conditions of the third frame area B3 and the fourth frame area B4 according to the transmission of the first test signal by the first detection lines 31a and 31b. Since the first detection transistors M1 and M1' are turned on, the voltage Vpcd1 of the first test signal can be transmitted to the first detection lines 31a and 31b, and the first main line 311a of the first detection line 31a and the first main line 311b of the first detection line 31b can transmit the first test signal to the plurality of first sub-lines 312a and 312b.
  • the first sub-line 312a has a winding design in the third frame area B3, when a crack appears on the edge of the third frame area B3, the first sub-line 312a corresponding to the edge crack position will be disconnected, and the first test signal cannot be transmitted to the corresponding light-emitting element, so that the corresponding light-emitting element will not emit light; the first sub-line 312a at the non-crack position of the third frame area B3 can normally transmit the first test signal to the corresponding light-emitting element, so that the corresponding light-emitting element can emit light normally.
  • the first sub-line 312b has a winding design in the fourth frame area B4, when a crack appears on the edge of the fourth frame area B4, the first sub-line 312b corresponding to the edge crack position will be disconnected, and the first test signal cannot be transmitted to the corresponding light-emitting element, so that the corresponding light-emitting element will not emit light; the first sub-line 312b at the non-crack position of the fourth frame area B4 can normally transmit the first test signal to the corresponding light-emitting element, so that the corresponding light-emitting element can emit light normally.
  • This example uses the first detection lines 31a and 31b to accurately locate the crack positions of the third frame area B3 and the fourth frame area B4.
  • the first detection transistors M1 and M1′ can be controlled to be disconnected by a first detection control signal, and the second detection transistors M2 and M2′ can be controlled to be turned on by a second detection control signal.
  • the second detection transistors M2 and M2′ provide a second test signal to the second detection line 32, and the transmission status of the second test signal in the second detection line 32 can be determined according to the display effect of the light-emitting elements connected to the second detection line 32 in the display area, thereby determining whether there are cracks in the second frame area and locating the crack position in the second frame area of the peripheral area.
  • FIG. 12 is a schematic diagram of a display pattern for crack detection in the second border region of at least one embodiment of the present disclosure.
  • the second detection line 32 is connected to the pixel circuits of the remaining sub-pixels in a row of sub-pixels except for the two ends.
  • the second test signal transmitted by the second detection line 32 can be normally provided to the connected pixel circuit, so that the light-emitting element connected to the pixel circuit does not show cracks.
  • a dark line running horizontally through the display area indicates that there is no crack in the second frame area B2.
  • the second sub-line 322 of the second detection line 32 wound at the crack position cannot transmit the second test signal to the pixel circuit corresponding to the display area, and the light-emitting element connected to the pixel circuit 61 connected to the second sub-line 322 at the crack position will be lit, and a dark line that does not pass through the horizontal line will appear in the display area, and the dark line at the position corresponding to the crack will be disconnected to display the bright line. As shown in FIG.
  • the second sub-line 322 wound at the third position W3 cannot transmit the second test signal to the corresponding pixel circuit 61 of the display area, and the display area will display the third bright line L3. According to the position of the third bright line L3, the crack at the third position W3 of the second frame area B2 can be located.
  • the voltage Vg1 of the first detection control signal is set to 7V
  • the voltage Vpcd1 of the first test signal is set to 0V
  • the voltage Vg2 of the second detection control signal is set to -7V
  • the voltage Vpcd2 of the second test signal is set to 7V
  • the first voltage signal Vdd is set to 4.6V
  • the second voltage signal Vss is set to -2.4.
  • the first detection transistors M1 and M1' are disconnected, and the second detection transistors M2 and M2' are turned on. This example can determine the crack condition of the second border area B2 based on the transmission of the second test signal by the second detection line 32.
  • the voltage Vpcd2 of the second test signal can be transmitted to the second detection line 32, and the second main line 321 of the second detection line 32 can transmit the second test signal to multiple second sub-lines 322. Since the second sub-line 322 has a winding design in the second frame area B2, when a crack appears at the edge of the second frame area B2, the second sub-line 322 corresponding to the edge crack position will be disconnected, and the second test signal cannot be transmitted to the corresponding pixel circuit, so that the light-emitting element connected to the corresponding pixel circuit will be lit.
  • the second sub-line 322 at the non-crack position of the second frame area B2 can normally transmit the second test signal to the corresponding pixel circuit, so that the light-emitting element connected to the pixel circuit does not emit light.
  • This example uses the second detection line 322 to determine whether there is a crack in the second frame area B2 and accurately locate the crack position of the second frame area B2.
  • the voltage Vg1 of the first detection control signal can be set to -7V
  • the voltage Vg2 of the second detection control signal can be set to -7V
  • the voltage Vg1 of the first detection control signal can be set to 7V, and the voltage Vg2 of the second detection control signal can be set to 7V, so that both the first detection transistor and the second detection transistor are disconnected to avoid affecting the normal display process.
  • the first frame region of the display panel may be provided with a second detection line, and the second detection line may be provided in a manner similar to that of the second frame region, which is not further described in this embodiment.
  • the display panel of this example sets a first detection line in the third frame area and the fourth frame area, and sets a second detection line in the second frame area.
  • FIG13 is a schematic diagram of another display panel of at least one embodiment of the present disclosure.
  • the third frame area B3 may be provided with a first detection line 31 a
  • the fourth frame area B4 may be provided with a first detection line 31 b
  • the second frame area B2 may be provided with a second detection line 32 .
  • the first detection line 31a may include: a first main line 311a and a plurality of first sub-lines 312a electrically connected to the first main line 311a.
  • the first main line 311a may be located on a side of the gate drive circuit 41a away from the display area AA, and the plurality of first sub-lines 312a may be located on a side of the first main line 311a close to the display area AA.
  • the plurality of first sub-lines 312a may be arranged sequentially along the second direction Y, and extend to the display area AA along the first direction X, and be electrically connected one-to-one with the plurality of light-emitting elements 62 in the display area AA.
  • the first sub-line 312a may use a first cross-line located in the bottom light-shielding metal layer to achieve jumping when passing through the gate drive circuit 41a and the frame initial signal line 42a. lines to avoid interference and prevent short circuits between different signals.
  • the first detection line 31b may include a first main line 311b and a plurality of first sub-lines 312b electrically connected to the first main line 311b.
  • the first main line 311b may be located on a side of the gate drive circuit 41b away from the display area AA, and the plurality of first sub-lines 312b may be located on a side of the first main line 311b close to the display area AA.
  • the plurality of first sub-lines 312b may be arranged in sequence along the second direction Y, and extend to the display area AA along the first direction X, and be electrically connected to the plurality of light-emitting elements 62 in the display area AA in a one-to-one correspondence.
  • a first crossover line located at the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.
  • the second detection line 32 may include: a second main line 321 and a plurality of second sub-lines 322 electrically connected to the second main line 321.
  • the second main line 321 may be located on a side of the first power border line 51 b away from the display area AA, and the plurality of second sub-lines 322 may be located on a side of the second main line 321 close to the display area AA.
  • the plurality of second sub-lines 322 may be arranged in sequence along the first direction X, and extend to the display area AA along the second direction Y, and be electrically connected to the plurality of pixel circuits 61 in the display area AA in a one-to-one correspondence.
  • a third cross-line located at the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.
  • the first main line 311a and the first sub-line 312a passing through the crack position cannot continue to transmit the first test signal, and the light-emitting element 62 connected to the crack position and the first sub-line 312a on the side of the crack position away from the first frame area B1 will not receive the first test signal and cannot be illuminated.
  • the display area AA will display a local bright line, and the edge of the third frame area B3 corresponding to the position without a bright line has a crack. When there is no crack in the third frame area B3, the display area AA can display the first bright line L1 as shown in Figure 11B. Similarly, it can be determined whether there is a crack in the fourth frame area B4 and the location of the crack.
  • the second main line 321 and the second sub-line 322 passing through the crack position cannot continue to transmit the second test signal, then the light-emitting elements of the pixel circuit connected to the position of the second sub-line 322 that cannot transmit the second test signal will be lit, and a bright line will be displayed in the display area AA.
  • the crack position of the second frame area B2 can be determined according to the bright line position of the display area AA.
  • FIG. 14 is a schematic diagram of another display panel of at least one embodiment of the present disclosure.
  • the third frame area B3 may be provided with a first detection line 31a, the first detection line 31a may be electrically connected to the third connection line 314a, and the third connection line 314a may be located in the display area.
  • the fourth frame area B4 may be provided with a first detection line 31b, and the first detection line 31b may be electrically connected to the third connection line 314b.
  • the third connection line 314b may be located in the display area.
  • the third connection line 314a may be located on the side of the second connection line 323a close to the third frame area B3, and the third connection line 314b may be located on the side of the second connection line 323b close to the fourth frame area B4.
  • the first detection lines 31a and 31b of this example are not directly connected, but each realizes a connection loop with the first detection control unit through the third connection line. This example can avoid occupying the wiring space of the second frame area B2.
  • FIG15 is a schematic diagram of another display panel of at least one embodiment of the present disclosure.
  • the third frame area B3 may be provided with a first detection line 31a
  • the fourth frame area B4 may be provided with a first detection line 31b
  • the second frame area B2 may be provided with a first detection line 31c.
  • the two ends of the first detection line 31c may be electrically connected to the first detection line 31a and the first detection line 31b, respectively.
  • the first detection line 31a may be electrically connected to the first detection control unit 33a
  • the first detection line 31b may be electrically connected to the first detection control unit 33b.
  • the first detection line 31a may include a first main line 311a and a plurality of first sub-lines 312a.
  • the first main line 311a may be located on a side of the gate driving circuit 41a close to the display area AA.
  • a portion of the line segments of the sub-line 312a (such as the aforementioned first line segment) may be located on a side of the gate drive circuit 41a away from the display area AA.
  • a plurality of first sub-lines 312a may be arranged in sequence along the second direction Y and extend to the display area AA, and be electrically connected to a plurality of pixel circuits 61 in the display area AA in a one-to-one correspondence.
  • a first jumper line and a second jumper line located at the bottom light shielding metal layer may be used to implement a jumper line to avoid interference and prevent short circuits between different signals.
  • the first detection line 31b may include a first main line 311b and a plurality of first sub-lines 312b electrically connected to the first main line 311b.
  • the first main line 311b may be located on a side of the gate drive circuit 41b close to the display area AA, and a portion of each first sub-line 312b may be located on a side of the gate drive circuit 41b away from the display area AA.
  • the plurality of first sub-lines 312b may be arranged in sequence along the second direction Y and extend to the display area AA, and be electrically connected to a plurality of pixel circuits 61 in the display area AA in a one-to-one correspondence.
  • a first crossover line and a second crossover line located in the bottom light shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.
  • the first detection line 31c may include a first main line 311c and a plurality of first sub-lines 312c electrically connected to the first main line 311c.
  • the first main line 311c may be located on a side of the first power border line 51b close to the display area AA.
  • the plurality of first sub-lines 312c may be arranged in sequence along the second direction Y and extend to the display area AA, and be electrically connected to the plurality of pixel circuits 61 in the display area AA in a one-to-one correspondence.
  • a jumper may be implemented by using a crossover line located at the bottom light-shielding metal layer to avoid interference and prevent short circuits between different signals.
  • the crack position can be located according to the position of the bright line in the display area during the crack detection process.
  • the first main line of the first detection line can be located on the side of the plurality of first sub-lines away from the display area.
  • FIG16 is a schematic diagram of another display panel of at least one embodiment of the present disclosure.
  • the third frame area B3 may be provided with a first detection line 31a
  • the fourth frame area B4 may be provided with a first detection line 31b
  • the second frame area B2 may be provided with a first detection line 31c.
  • the two ends of the first detection line 31c may be electrically connected to the first detection line 31a and the first detection line 31b, respectively.
  • the first detection line 31a may be electrically connected to the first detection control unit 33a
  • the first detection line 31b may be electrically connected to the first detection control unit 33b.
  • the first detection lines 31a, 31b, and 31c are electrically connected to the anodes of the light-emitting elements 62 of the multiple sub-pixels in the display area, respectively.
  • This example can locate the crack position according to the position of the dark line in the display area during the crack detection process.
  • this embodiment is not limited to this.
  • the first main line of the first detection line may be located on the side of the multiple first sub-lines away from the display area.
  • Figure 17 is a plan schematic diagram of another display panel of at least one embodiment of the present disclosure.
  • the display area AA may include: a plurality of sub-pixels PX, a plurality of data lines DL extending along a first direction X, and a plurality of first power lines VDD extending along a second direction Y.
  • the plurality of data lines DL may be arranged in sequence along the second direction Y
  • the plurality of first power lines VDD may be arranged in sequence along the first direction X.
  • Each data line DL may be electrically connected to the pixel circuits of the plurality of sub-pixels arranged along the first direction X, and may be configured to provide data signals to the plurality of pixel circuits.
  • Each first power line VDD may be electrically connected to the pixel circuits of the plurality of sub-pixels arranged along the second direction Y, and may be configured to provide a first voltage signal to the plurality of sub-pixels.
  • the data line DL and the first power line VDD may be located in different film layers to avoid mutual interference between the two.
  • the data line DL may be located in the first source-drain metal layer
  • the first power line VDD may be located in the second source-drain metal layer
  • the data line DL may be located in the first source-drain metal layer
  • the second source-drain metal layer, the first power line VDD can be located in the first source-drain metal layer.
  • FIG18 is a schematic diagram of another display panel of at least one embodiment of the present disclosure.
  • a plurality of data lines DL of the display area AA extend along the first direction X
  • a plurality of first power lines VDD extend along the second direction Y.
  • the third frame area B3 may be provided with a data supply bus (or data supply circuit) 43a and a gate drive circuit 41a.
  • the data supply bus 43a may be located on one side of the gate drive circuit 41a close to the display area AA.
  • the fourth frame area B4 may be provided with a data supply bus 43b and a gate drive circuit 41b.
  • the data supply bus 43b may be located on one side of the gate drive circuit 41b close to the display area AA.
  • the plurality of data lines DL of the display area AA may be electrically connected to the data supply buses 43a and 43b.
  • the data supply buses 43a and 43b may be electrically connected to a plurality of data pins in the signal access area B11.
  • the integrated circuit provided in the signal access area B11 may be configured to provide data signals through a plurality of data pins.
  • the third frame region B3 may be provided with a first detection line 31a.
  • the first detection line 31a may include a first main line 311a and a plurality of first sub-lines 312a.
  • the first main line 311a may be located on the side of the data supply bus 43a close to the display area AA.
  • the plurality of first sub-lines 312a may be arranged in sequence along the second direction Y and electrically connected to the first main line 311a.
  • the first sub-line 312a may extend in the first direction X to the side of the first main line 311a away from the display area AA until it extends to the side of the gate drive circuit 41a away from the display area AA, and then the first sub-line 312a is wound along the first direction X to extend to the side close to the display area AA, and finally extends to be electrically connected to a data line DL.
  • the plurality of first sub-lines 312a and the plurality of data lines DL may be electrically connected one by one.
  • the connection position of the first sub-line 312a with the data line DL may be located on the side of the first main line 311a close to the display area AA, or may be located within the display area AA.
  • the first jumper line and the second jumper line located at the bottom light shielding metal layer can be used to implement jumper to avoid interference and prevent short circuits between different signals.
  • the fourth frame area B4 may be provided with a first detection line 31b.
  • the first detection line 31b may include a first main line 311b and a plurality of first sub-lines 312b.
  • the first main line 311b may be located on the side of the data supply bus 43b close to the display area AA.
  • the plurality of first sub-lines 312b may be arranged in sequence along the second direction Y and electrically connected to the first main line 311b.
  • the first sub-line 312b may extend in the first direction X to the side of the first main line 311b away from the display area AA until it extends to the side of the gate drive circuit 41b away from the display area AA, and then the first sub-line 312b is wound along the first direction X to extend to the side close to the display area AA, and finally extends to be electrically connected to a data line DL.
  • the plurality of first sub-lines 312b and the plurality of data lines DL may be electrically connected one by one.
  • the connection position of the first sub-line 312b with the data line DL may be located on the side of the first main line 311b close to the display area AA, or may be located within the display area AA.
  • the first jumper line and the second jumper line located at the bottom light shielding metal layer can be used to implement jumper to avoid interference and prevent short circuits between different signals.
  • the second frame area B2 may be provided with a first power frame line 51 b and a second detection line 32.
  • the second detection line 32 may be electrically connected to the second detection control unit 34 a through a second connection line 323 a located in the display area AA, and electrically connected to the second detection control unit 34 b through a second connection line 323 b located in the display area AA.
  • the second detection line 32 may include: a second main line 321 and a plurality of second sub-lines 322.
  • the second main line 321 may be located on the side of the first power frame line 51 b close to the display area AA.
  • each second sub-line 322 may be located on the side of the first power frame line 51 b away from the display area AA.
  • each second sub-line 322 After each second sub-line 322 is connected to the second main line 321, it extends along the second direction Y to the side away from the display area AA, until it passes through the first power frame line 51 b, and then the winding extends along the second direction Y to the side close to the display area AA, and finally extends to be electrically connected to a first power line VDD in the display area AA.
  • the plurality of second sub-wires 322 and the plurality of first power lines VDD can be electrically connected one by one.
  • the third jumper and the fourth jumper located at the bottom light shielding metal layer can be used to implement jumper to avoid interference and prevent different signals from of short circuit.
  • the number of data lines connected to the first detection line 31a and the number of data lines connected to the first detection line 31b may be the same.
  • the multiple data lines connected to the first detection line 31a and the multiple data lines connected to the first detection line 31b may be the same.
  • this embodiment is not limited to this.
  • the multiple data lines connected to the first detection line 31a may be different from the multiple data lines connected to the first detection line 31b, so as to better distinguish the crack positions of the third frame area B3 and the fourth frame area B4. This example does not limit the number of data lines connected to the first detection line 31a and the number of first power lines connected to the second detection line 31b.
  • both the first detection transistor and the second detection transistor are P-type transistors.
  • the first test signal transmitted by the first detection lines 31a and 31b can be normally provided to the connected data lines DL, so that the sub-pixels connected to the data lines DL do not emit light, and the display area AA can display multiple dark lines.
  • the first sub-line of the first detection line wound at the crack position cannot transmit the first test signal to the corresponding data line, so that the sub-pixels connected to the data line corresponding to the crack position will be lit, and the display area AA will display the corresponding bright line. In this way, whether there are cracks in the third frame area B3 and the fourth frame area B4 and the crack positions of the third frame area B3 and the fourth frame area B4 can be determined based on the horizontal bright line position of the display area.
  • the voltage Vg1 of the first detection control signal is set to -7V
  • the voltage Vpcd1 of the first test signal is set to 7V
  • the voltage Vg2 of the second detection control signal is set to 7V
  • the voltage Vpcd2 of the second test signal is set to 0V
  • the data voltage Vdata is set to 7V.
  • the first detection transistors M1 and M1' are turned on, and the second detection transistors M2 and M2' are turned off.
  • the display area is displayed as a dark line; when there are cracks in the third frame area B3 or the fourth frame area B3, the corresponding position of the display area displays a bright line. In this way, the crack positions of the third frame area B3 and the fourth frame area B4 can be located according to the bright line positions of the display area.
  • the second test signal transmitted by the second detection line 32 can be normally provided to the connected first power line VDD, for example, so that the sub-pixel connected to the first power line VDD can be displayed normally.
  • the second test signal transmitted by the second detection line 32 cannot be provided to the connected first power line VDD, for example, so that the sub-pixel connected to the first power line VDD cannot be displayed normally.
  • the crack position of the second border area B2 can be located according to the dark line position of the display area.
  • this embodiment is not limited to this.
  • the second test signal can be used to make the sub-pixel connected to the first power line VDD not display, and when there is a crack in the second border area B2, the sub-pixel connected to the first power line VDD is displayed, thereby locating the crack position according to the bright line position of the display area.
  • the voltage Vg1 of the first detection control signal is set to 7V
  • the voltage Vpcd1 of the first test signal is set to 0V
  • the voltage Vg2 of the second detection control signal is set to -7V
  • the voltage Vpcd2 of the second test signal is set to 4.6V
  • the first terminal voltage signal Vdd and the second voltage signal Vss are both 0V.
  • the first detection transistors M1 and M1' are disconnected, and the second detection transistors M2 and M2' are turned on.
  • the display area can display a bright line
  • the corresponding position of the display area can display a dark line. In this way, the crack position of the second frame area B2 can be located according to the position of the dark line in the display area.
  • the voltage Vg1 of the first detection control signal can be set to -7V
  • the voltage Vg2 of the second detection control signal can be set to -7V
  • the display panel of this example sets a first detection line in the third frame area and the fourth frame area, and sets a second detection line in the second frame area.
  • FIG19 is a schematic diagram of another display panel of at least one embodiment of the present disclosure.
  • the third frame area B3 may be provided with a first detection line 31 a
  • the fourth frame area B4 may be provided with a first detection line 31 b
  • the second frame area B2 may be provided with a second detection line 32 .
  • the first detection line 31a may include: a first main line 311a and a plurality of first sub-lines 312a electrically connected to the first main line 311a.
  • the first main line 311a may be located on a side of the gate drive circuit 41a away from the display area AA, and the plurality of first sub-lines 312a may be located on a side of the first main line 311a close to the display area AA.
  • the plurality of first sub-lines 312a may be arranged in sequence along the second direction Y, and extend to the display area AA along the first direction X, and be electrically connected to the plurality of data lines DL in the display area AA in a one-to-one correspondence.
  • the first cross-over line located at the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.
  • the first detection line 31b may include a first main line 311b and a plurality of first sub-lines 312b electrically connected to the first main line 311b.
  • the first main line 311b may be located on a side of the gate drive circuit 41b away from the display area AA, and the plurality of first sub-lines 312b may be located on a side of the first main line 311b close to the display area AA.
  • the plurality of first sub-lines 312b may be arranged in sequence along the second direction Y, and extend to the display area AA along the first direction X, and be electrically connected to the plurality of data lines DL in the display area AA in a one-to-one correspondence.
  • the first cross-over line located at the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.
  • the second detection line 32 may include: a second main line 321 and a plurality of second sub-lines 322 electrically connected to the second main line 321.
  • the second main line 321 may be located on a side of the first power border line 51 b away from the display area AA, and the plurality of second sub-lines 322 may be located on a side of the second main line 321 close to the display area AA.
  • the plurality of second sub-lines 322 may be arranged in sequence along the first direction X, and extend to the display area AA along the second direction Y, and be electrically connected to the plurality of first power lines VDD in the display area AA in a one-to-one correspondence.
  • a third cross-line located in the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.
  • the first main line 311a and the first sub-line 312a passing through the crack position can no longer transmit the first test signal, and the data line DL connected to the crack position and the first sub-line 312a on the side of the crack position away from the first frame area B1 will not receive the first test signal, and the sub-pixel connected to the data line DL will be lit.
  • the edge of the third frame area B3 corresponding to the position of the bright line in the display area has a crack.
  • the display area can display a dark line.
  • the second main line 321 and the second sub-line 322 passing through the crack position cannot continue to transmit the second test signal, and the light-emitting element connected to the first power line connected to the position of the second sub-line 322 that cannot transmit the second test signal cannot be illuminated, and a dark line is correspondingly displayed in the display area AA.
  • the crack position of the second frame area B2 can be determined according to the dark line position of the display area AA.
  • This embodiment also provides a crack detection method, which is applied to the display panel as described above, and the crack detection method includes: providing a first test signal to a first detection line through a first detection control unit; determining whether there is a crack in the surrounding area and the location of the crack based on the luminous state of multiple sub-pixels electrically connected to the first detection line.
  • the crack detection method of this example may further include: providing a second test signal to a second detection line through a second detection control unit; determining whether there is a crack in the peripheral area and the location of the crack based on the luminous state of multiple sub-pixels electrically connected to the second detection line.
  • the description of the crack detection method of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • the present embodiment also provides a display panel, comprising: a substrate, a plurality of sub-pixels, at least one first detection line and at least one first detection control unit.
  • the substrate comprises a display area and a peripheral area located outside the display area.
  • a plurality of sub-pixels are located in the display area.
  • At least one first detection line and at least one first detection control unit are located in the peripheral area, and the at least one first detection control unit is electrically connected to the at least one first detection line and configured to provide a first test signal to the at least one first detection line.
  • the at least one first detection line is electrically connected to a plurality of sub-pixels in the display area.
  • the at least one first detection line comprises: a first main line, and a plurality of first sub-lines electrically connected to the first main line, the plurality of first sub-lines extending to the display area, and each first sub-line being electrically connected to at least one sub-pixel in the display area.
  • a portion of a line segment of at least one of the plurality of first sub-lines is located on a side of the first main line away from the display area.
  • a portion of a line segment of each of the plurality of first sub-lines may be located on a side of the first main line away from the display area.
  • the peripheral area may also be provided with a gate driving circuit.
  • the first main line may be located on a side of the gate driving circuit close to the display area, and a portion of each first sub-line may be located on a side of the gate driving circuit away from the display area.
  • the display panel may further include: a second detection line located in the peripheral area and at least one second detection control unit, the at least one second detection control unit being electrically connected to the second detection line and configured to provide a second test signal to the second detection line.
  • the second detection line is electrically connected to a plurality of sub-pixels in the display area.
  • the connection manner of the second detection line to the plurality of sub-pixels in the display area is different from the connection manner of the first detection line to the plurality of sub-pixels in the display area.
  • the first detection line may be electrically connected to the anodes of the light-emitting elements of the plurality of sub-pixels, and the second detection line may be electrically connected to the source of the data writing transistor of the pixel circuit of the plurality of sub-pixels.
  • the first detection line may be electrically connected to a plurality of data lines, and the second detection line may be electrically connected to a plurality of first power lines.
  • the second detection line may include: a second main line and a plurality of second sub-lines electrically connected to the second main line; each second sub-line is electrically connected to at least one sub-pixel of the display area, and the plurality of second sub-lines are sequentially arranged along an extension direction of the second main line.
  • the extension direction of the second main line intersects with an extension direction of the first main line of the first detection line.
  • the description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG20 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the present embodiment provides a display device, comprising: a display panel 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display panel 91.
  • the sensor 92 may be located on the non-display surface side of the display panel 91.
  • the orthographic projection of the sensor 92 on the display panel 91 may overlap with the first display area A1.
  • the display panel 91 may be a flexible OLED display panel, a QLED display panel, a Micro-LED display panel, or a Mini-LED display panel.
  • the display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function.
  • the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA, Personal Digital Assistant), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power and other departments), a monitor, and the like.
  • the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

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Abstract

一种显示面板，包括：衬底(10)、多个子像素(PX)、多条数据线(DL)、第一检测线(31a、31b)、第一检测控制单元(33a、33b)。第一检测控制单元(33a、33b)与第一检测线(31a、31b)电连接，被配置为给第一检测线(31a、31b)提供第一测试信号。第一检测线(31a、31b)通过以下任一方式与显示区域(AA)的多个子像素(PX)电连接：第一检测线(31a、31b)与显示区域(AA)的多个子像素的发光元件(62)的阳极电连接；第一检测线(31a、31b)与显示区域(AA)的多个子像素的像素电路(61)的数据写入晶体管的源极电连接；第一检测线(31a、31b)与显示区域(AA)的多条数据线(DL)电连接，数据线(DL)与沿第一方向(X)排布的多个子像素电连接。

Description

显示面板、显示装置及裂纹检测方法 技术领域
本文涉及显示技术领域，尤指一种显示面板、显示装置及裂纹检测方法。
背景技术
显示面板的外围通常会设置检测模组或电路，用于检测显示面板的外围(边缘区域)在生产运输中有无裂纹(crack)缺陷。目前通常采用以下两种检测方法：涡流检测(ET检测)和电阻检测。涡流检测是通过面板裂纹检测(PCD，Panel Crack Detection)线路检测画面是否有亮线来判断面板四周是否存在裂纹；电阻检测是对PCD线路之间的电阻进行检测，通过电阻值是否异常判断是否存在裂纹。然而，上述检测方式均只能检测出边缘区域有无裂纹缺陷，无法精确定位缺陷的位置。例如，针对大尺寸的显示面板，工作人员需要利用显微镜在显示面板的整个边缘区域慢慢寻找裂纹位置，将消耗工作人员的大量时间和精力，导致工作效率极低。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示面板、显示装置及裂纹检测方法。
一方面，本实施例提供一种显示面板，包括：衬底、多个子像素和多条数据线、至少一条第一检测线和至少一个第一检测控制单元。衬底包括显示区域和位于所述显示区域外围的周边区域。多个子像素和多条数据线位于显示区域，多个子像素和多条数据线电连接，多个子像素中的至少一个子像素包括：像素电路和发光元件，像素电路和发光元件电连接，被配置为驱动发光元件发光。至少一条第一检测线和至少一个第一检测控制单元位于周边区域，至少一个第一检测控制单元与至少一条第一检测线电连接，被配置为给至少一条第一检测线提供第一测试信号。至少一条第一检测线通过以下任一方式与显示区域的多个子像素电连接：至少一条第一检测线与显示区域的多个子像素的发光元件的阳极电连接；至少一条第一检测线与显示区域的多个子像素的像素电路的数据写入晶体管的源极电连接；至少一条第一检测线与所述显示区域的多条数据线电连接，其中，多条数据线中的至少一条数据线与沿第一方向排布的多个子像素电连接，至少一条第一检测线至少位于所述显示区域沿第一方向相对两侧的周边区域内。
在一些示例性实施方式中，所述至少一条第一检测线包括：第一主线以及与所述第一主线电连接的多条第一子线，每条第一子线与所述显示区域的至少一个子像素电连接；所述多条第一子线沿着所述第一主线的延伸方向依次排布。
在一些示例性实施方式中，所述周边区域还设置有栅极驱动电路。所述第一主线位于所述栅极驱动电路靠近所述显示区域的一侧，每条第一子线的一部分线段位于所述栅极驱动电路远离所述显示区域的一侧。
在一些示例性实施方式中，所述周边区域还设置有栅极驱动电路。所述第一主线位于所述栅极驱动电路远离所述显示区域的一侧，所述多条第一子线位于所述第一主线靠近所述显示区域的一侧。
在一些示例性实施方式中，所述第一检测线的多条第一子线电连接的多个子像素包括： 所述显示区域内最靠近所述第一主线且沿所述第一主线的延伸方向排布的多个子像素。
在一些示例性实施方式中，每条第一子线至少包括：第一线段、第二线段以及第一跨线，所述第一跨线的两端分别与所述第一线段和第二线段电连接，所述第一线段位于所述栅极驱动电路远离所述显示区域的一侧，所述第二线段位于所述栅极驱动电路靠近所述显示区域的一侧，所述第一跨线在所述衬底的正投影与所述栅极驱动电路在所述衬底的正投影至少部分交叠；所述第一跨线位于所述第一线段和第二线段靠近所述衬底的一侧。
在一些示例性实施方式中，在垂直于所述显示面板的方向上，所述显示面板至少包括：衬底以及设置在所述衬底上的底部遮光金属层、半导体层、第一栅金属层、第二栅金属层、第一源漏金属层以及第二源漏金属层。所述第一跨线位于所述底部遮光金属层，所述第一线段和所述第二线段位于所述第一栅金属层。
在一些示例性实施方式中，所述至少一个第一检测控制单元包括：第一检测晶体管，所述第一检测晶体管的栅极与第一检测控制线电连接，所述第一检测晶体管的第一极与第一测试信号传输线电连接，所述第一检测晶体管的第二极与所述第一检测线电连接。
在一些示例性实施方式中，显示面板还包括：位于所述周边区域的第二检测线和至少一个第二检测控制单元；所述至少一个第二检测控制单元与所述第二检测线电连接，被配置为给所述第二检测线提供第二测试信号。所述第二检测线与所述显示区域的多个子像素电连接。所述第二检测线与所述显示区域的多个子像素的连接方式不同于所述第一检测线与所述显示区域的多个子像素的连接方式。
在一些示例性实施方式中，所述第二检测线包括：第二主线以及与所述第二主线电连接的多条第二子线；每条第二子线与所述显示区域的至少一个子像素电连接，所述多条第二子线沿着所述第二主线的延伸方向依次排布。所述第二主线的延伸方向与所述第一检测线的第一主线的延伸方向交叉。
在一些示例性实施方式中，所述至少一条第一检测线的多条第一子线和所述显示区域的多个子像素的发光元件的阳极一一对应电连接。所述第二检测线的多条第二子线和所述显示区域的多个子像素的像素电路的数据写入晶体管的源极一一对应电连接。
在一些示例性实施方式中，所述至少一条第一检测线的多条第一子线与所述显示区域的多条数据线一一对应电连接；所述多条数据线沿所述第一方向延伸。所述第二检测线的多条第二子线和所述显示区域的多条第一电源线一一对应电连接，所述多条第一电源线沿第二方向延伸，所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，所述周边区域还设置有第一电源边框线。所述第二主线位于所述第一电源边框线靠近所述显示区域的一侧，每条第二子线的一部分位于所述第一电源边框线远离所述显示区域的一侧。
在一些示例性实施方式中，所述周边区域还设置有第一电源边框线。所述第二主线位于所述第一电源边框线远离所述显示区域的一侧，所述多条第二子线位于所述第二主线靠近所述显示区域的一侧。
在一些示例性实施方式中，所述第二检测线的多条第二子线电连接的多个子像素包括：所述显示区域内最靠近所述第二主线且沿所述第二主线的延伸方向排布的多个子像素。
在一些示例性实施方式中，每条第二子线至少包括：第三线段、第四线段以及第三跨线，所述第三跨线的两端分别与所述第三线段和第四线段电连接，所述第三线段位于所述第一电源边框线远离所述显示区域的一侧，所述第四线段位于所述第一电源边框线靠近所述显示区域的一侧，所述第三跨线在所述衬底的正投影与所述第一电源边框线在所述衬底 的正投影至少部分交叠；所述第三跨线位于所述第三线段和所述第四线段靠近所述衬底的一侧。
在一些示例性实施方式中，在垂直于所述显示面板的方向上，所述显示面板至少包括：衬底以及设置在所述衬底上的底部遮光金属层、半导体层、第一栅金属层、第二栅金属层、第一源漏金属层以及第二源漏金属层。所述第三跨线位于所述底部遮光金属层，所述第三线段和第四线段位于所述第一栅金属层。
在一些示例性实施方式中，所述第二检测控制单元包括：第二检测晶体管，所述第二检测晶体管的栅极与第二检测控制线电连接，所述第二检测晶体管的第一极与第二测试信号传输线电连接，所述第二检测晶体管的第二极与所述第二检测线电连接。
另一方面，本实施例提供一种显示装置，包括如上所述的显示面板。
另一方面，本实施例提供一种裂纹检测方法，应用于如上所述的显示面板，包括：通过第一检测控制单元向第一检测线提供第一测试信号；根据与所述第一检测线电连接的多个子像素的发光状态，确定周边区域是否存在裂纹以及裂纹所在的位置。
在一些示例性实施方式中，裂纹检测方法还包括：通过第二检测控制单元向第二检测线提供第二测试信号；根据与所述第二检测线电连接的多个子像素的发光状态，确定所述周边区域是否存在裂纹以及裂纹所在位置。
另一方面，本实施例提供一种显示面板，包括：衬底、多个子像素、至少一条第一检测线和至少一个第一检测控制单元。衬底包括显示区域和位于所述显示区域外围的周边区域。多个子像素位于所述显示区域。至少一条第一检测线和至少一个第一检测控制单元位于所述周边区域，所述至少一个第一检测控制单元与所述至少一条第一检测线电连接，被配置为给所述至少一条第一检测线提供第一测试信号。所述至少一条第一检测线与所述显示区域的多个子像素电连接。所述至少一条第一检测线包括：第一主线、以及与所述第一主线电连接的多条第一子线，所述多条第一子线延伸至所述显示区域，每条第一子线与所述显示区域的至少一个子像素电连接。所述多条第一子线中的至少一条第一子线的一部分线段位于所述第一主线远离所述显示区域的一侧。
在一些示例性实施方式中，所述周边区域还设置有栅极驱动电路。所述第一主线位于所述栅极驱动电路靠近所述显示区域的一侧，每条第一子线的一部分线段位于所述栅极驱动电路远离所述显示区域的一侧。
在一些示例性实施方式中，显示面板还包括：位于所述周边区域的第二检测线和至少一个第二检测控制单元，所述至少一个第二检测控制单元与所述第二检测线电连接，被配置为给所述第二检测线提供第二测试信号。所述第二检测线与所述显示区域的多个子像素电连接。所述第二检测线与所述显示区域的多个子像素的连接方式不同于所述第一检测线与所述显示区域的多个子像素的连接方式。
在一些示例性实施方式中，所述第二检测线包括：第二主线以及与所述第二主线电连接的多条第二子线；每条第二子线与所述显示区域的至少一个子像素电连接，所述多条第二子线沿着所述第二主线的延伸方向依次排布。所述第二主线的延伸方向与所述第一检测线的第一主线的延伸方向交叉。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开 的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示面板的平面示意图；
图2为本公开至少一实施例的像素电路的等效电路图；
图3为本公开至少一实施例的一种显示面板的示意图；
图4为本公开至少一实施例的显示面板的局部走线示意图；
图5为图4所示的第一子线的局部剖面示意图；
图6为本公开至少一实施例的显示区域的局部剖面示意图；
图7为本公开至少一实施例的显示面板的另一局部走线示意图；
图8为图7所示的第二子线的局部剖面示意图；
图9为本公开至少一实施例的第二子线与像素电路的连接示意图；
图10A为图9中形成半导体层后的像素电路的示意图；
图10B为图9中形成第一栅金属层后的像素电路的示意图；
图10C为图9中形成第二栅金属层后的像素电路的示意图；
图10D为图9中形成第一源漏金属层后的像素电路的示意图；
图11A和图11B为本公开至少一实施例的第三边框区域和第四边框区域的裂纹检测的显示图案示意图；
图12为本公开至少一实施例的第二边框区域的裂纹检测的显示图案示意图；
图13为本公开至少一实施例的另一种显示面板的示意图；
图14为本公开至少一实施例的另一种显示面板的示意图；
图15为本公开至少一实施例的另一显示面板的示意图；
图16为本公开至少一实施例的另一显示面板的示意图；
图17为本公开至少一实施例的另一显示面板的平面示意图；
图18为本公开至少一实施例的另一显示面板的示意图；
图19为本公开至少一实施例的另一显示面板的示意图；
图20为本公开至少一实施例的显示装置的示意图。
详述
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，圆形、椭圆形、三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似圆形、近似椭圆形、近似三角形、近似矩形、近似梯形、近似五边形或近似六边形等，可以存在公差导致的一些小变形，例如可以存在导角、弧边以及变形等。
本公开中的“光透过率”指的是光线透过介质的能力，是透过透明或半透明体的光通量与其入射光通量的百分率。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
在本公开中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。本公开中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
本实施例提供一种显示面板，包括：衬底、多个子像素和多条数据线、至少一条第一检测线和至少一个第一检测控制单元。衬底包括显示区域和位于所述显示区域外围的周边区域。多个子像素和多条数据线位于显示区域，多个子像素和多条数据线电连接，多个子 像素中的至少一个子像素包括：像素电路和发光元件，像素电路和发光元件电连接，被配置为驱动发光元件发光。至少一条第一检测线和至少一个第一检测控制单元位于周边区域，至少一个第一检测控制单元与至少一条第一检测线电连接，被配置为给至少一条第一检测线提供第一测试信号。至少一条第一检测线通过以下任一方式与显示区域的多个子像素电连接：至少一条第一检测线与显示区域的多个子像素的发光元件的阳极电连接；至少一条第一检测线与显示区域的多个子像素的像素电路的数据写入晶体管的源极电连接；至少一条第一检测线与所述显示区域的多条数据线电连接，其中，多条数据线中的至少一条数据线与沿第一方向排布的多个子像素电连接，至少一条第一检测线至少位于所述显示区域沿第一方向相对两侧的周边区域内。
在一些示例中，第一检测线可以与显示区域的多个子像素的发光元件的阳极电连接。在裂纹检测过程中，当发光元件的阳极接收到第一检测线传输的第一测试信号，发光元件可以被点亮，反之，当第一检测线所在位置存在裂纹，第一检测线无法将第一测试信号传输给对应的发光元件的阳极，对应的发光元件不发光。如此一来，可以根据显示区域的暗线位置来定位边缘裂纹的位置。
在一些示例中，第一检测线可以与显示区域的多个子像素的像素电路的数据写入晶体管的源极电连接。在裂纹检测过程中，当像素电路的数据写入晶体管的源极接收到第一检测线传输的第一测试信号，像素电路驱动的发光元件不发光，反之，当第一检测线所在位置存在裂纹，第一检测线无法将第一测试信号传输给对应的像素电路，所述像素电路驱动的发光元件可以发光。如此一来，可以根据显示区域的亮线位置来定位边缘裂纹的位置。
在一些示例中，第一检测线可以与显示区域内的多条数据线电连接，多条数据线可以沿第一方向延伸(例如横向布线)。在裂纹检测过程中，当数据线接收到第一检测线传输的第一测试信号，所述数据线所连接的像素电路可以驱动发光元件不发光，反之，当第一检测线所在位置存在裂纹，第一检测线无法将第一测试信号传输给对应的数据线，所述数据线所连接的像素电路可以驱动发光元件发光。如此一来，可以根据显示区域的亮线位置来定位边缘裂纹的位置。
本实施例提供的显示面板，利用第一检测控制单元给第一检测线提供第一测试信号，第一检测线与显示区域的多个子像素电连接，根据对第一测试信号的电压控制以及显示区域的多个子像素的显示结果，可以便于确定周边区域是否存在裂纹以及精确定位出周边区域存在边缘裂纹的位置，从而可以提高工作效率。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示面板的平面示意图。在一些示例中，如图1所示，本实施例的显示面板可以包括：显示区域AA、围绕显示区域AA的周边区域BB。周边区域BB可以包括：沿第一方向X位于显示区域AA相对两侧的第三边框区域B3和第四边框区域B4、沿第二方向Y位于显示区域AA相对两侧的第一边框区域B1和第二边框区域B2。其中，第一边框区域B1还可以称为下边框，第二边框区域B2还可以称为上边框，第三边框区域B3还可以称为左边框，第四边框区域B4还可以称为右边框。第一边框区域B1与第三边框区域B3和第四边框区域B4连通，第二边框区域B2与第三边框区域B3和第四边框区域B4连通。
在一些示例中，如图1所示，显示区域AA可以为矩形，例如圆角矩形。然而，本实施例对此并不限定。例如，显示区域可以为圆形、或者椭圆形等其它形状。
在一些示例中，如图1所示，第三边框区域B3和第四边框区域B4可以包括沿着显示区域AA的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区可以连接到 显示区域AA，电路区可以包括栅极驱动电路，例如，栅极驱动电路可以包括多个级联的移位寄存器，多个移位寄存器可以与显示区域AA中的多条栅线GL电连接。电源线区连接到电路区，可以至少包括低电平电源线，低电平电源线可以沿着平行于显示区域边缘的方向延伸，与显示区域AA的阴极连接。裂缝坝区可以连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区可以连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽可以被配置为在显示面板的所有膜层制备完成后，切割设置可以分别沿着切割槽进行切割。
在一些示例中，如图1所示，显示区域AA可以是平坦的区域，包括组成像素阵列的多个子像素PX，多个子像素PX可以被配置为显示动态图片或静止图像。显示区域AA可以称为有效区域。在一些示例中，显示面板可以为柔性面板，因而显示面板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在一些示例中，如图1所示，显示区域AA可以至少包括多个子像素PX、多条栅线GL以及多条数据线DL。多条栅线GL可以沿第一方向X延伸，多条数据线DL可以沿第二方向Y延伸。多条栅线GL和多条数据线DL在衬底基板上的正投影可以交叉形成多个子像素区域，每个子像素区域内可以设置一个子像素PX。多条数据线DL与多个子像素PX电连接，多条数据线DL可以被配置为向多个子像素PX提供数据信号。多条数据线DL可以延伸至第一边框区域B1。多条栅线GL与多个子像素PX电连接，多条栅线GL可以被配置为向多个子像素PX提供栅极控制信号。在一些示例中，栅极控制信号可以包括扫描信号和发光控制信号。又如，栅极控制信号可以包括扫描信号、发光控制信号和复位控制信号。
在一些示例中，如图1所示，第一方向X可以是显示区域AA中栅线GL的延伸方向(行方向)，第二方向Y可以是列方向。第一方向X和第二方向Y可以交叉，例如，第一方向X和第二方向Y可以相互垂直。
在一些示例中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例中，子像素的形状可以是矩形、菱形、五边形或六边形。当一个像素单元包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字方式排列；当一个像素单元包括四个子像素，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例中，一个子像素可以包括：像素电路以及与像素电路电连接的发光元件。像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。
在一些示例中，像素电路中的多个晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在另一些示例中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。
在一些示例中，像素电路中的多个晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温 多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，即LTPS+Oxide(简称LTPO)显示面板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diode)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
图2为本公开至少一实施例的像素电路的等效电路图。本示例的像素电路以7T1C结构为例进行说明。
在一些示例中，如图2所示，本示例的像素电路可以包括七个晶体管(即第一晶体管T1至第七晶体管T7)和一个存储电容Cst。发光元件EL可以包括阳极、阴极和设置在阳极和阴极之间的有机发光层。
在一些示例中，如图2所示，显示面板可以包括：第一扫描线GL1、第二扫描线GL2、第三扫描线GL3、数据线DL、第一电源线VDD、第二电源线VSS、发光控制线EML、第一初始信号线INIT1和第二初始信号线INIT2。
在一些示例中，第一电源线VDD可以配置为向像素电路提供恒定的第一电压信号Vdd，第二电源线VSS可以配置为向像素电路提供恒定的第二电压信号Vss，并且第一电压信号Vdd可以大于第二电压信号Vss。第一扫描线GL1可以配置为向像素电路提供第一扫描信号SCAN1；数据线DL可以配置为向像素电路提供数据信号；发光控制线EML可以配置为向像素电路提供发光控制信号EM；第二扫描线GL2可以配置为向像素电路提供第二扫描信号SCAN2，第三扫描线GL3可以配置为向像素电路提供第三扫描信号SCAN3。
在一些示例中，第n行像素电路电连接的第二扫描线GL2可以与第n-1行像素电路电连接的第一扫描线GL1电连接，以被输入第一扫描信号SCAN1(n-1)，即第二扫描信号SCAN2(n)与第一扫描信号SCAN1(n-1)可以相同。第n行像素电路的第三扫描线GL3可以与第n行像素电路的第一扫描线GL1电连接，以被输入第一扫描信号SCAN1(n)，即第三扫描信号SCAN3(n)与第一扫描信号SCAN1(n)可以相同。其中，n为大于0的整数。如此，可以减少显示面板的信号线，实现显示面板的窄边框设计。然而，本实施例对此并不限定。
在一些示例中，第一初始信号线INIT1可以配置为向像素电路提供第一初始信号，第二初始信号线INIT2可以配置为向像素电路提供第二初始信号。例如，第一初始信号可以不同于第二初始信号。其中，第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电压信号Vdd和第二电压信号Vss之间，但不限于此。在另一些示例中，第一初始信号与第二初始信号可以相同，可以仅设置第一初始信号线来提供第一初始信号。
在一些示例中，如图2所示，第三晶体管T3的栅极与第一节点N1电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第三节点N3电连接。第三晶体管T3还可以称为驱动晶体管。第四晶体管T4的栅极与第一扫描线GL1电连接， 第四晶体管T4的第一极与数据线DL电连接，第四晶体管T4的第二极与第三晶体管T3的第一极电连接。第四晶体管T4还可以称为数据写入晶体管。第二晶体管T2的栅极与第一扫描线GL1电连接，第二晶体管T2的第一极与第三晶体管T3的栅极电连接，第二晶体管T2的第二极与第三晶体管T3的第二极电连接。第二晶体管T2还可以称为阈值补偿晶体管。第五晶体管T5的栅极与发光控制线EML电连接，第五晶体管T5的第一极与第一电源线VDD电连接，第五晶体管T5的第二极与第三晶体管T3的第一极电连接。第六晶体管T6的栅极与发光控制线EML电连接，第六晶体管T6的第一极与第三晶体管T3的第二极电连接，第六晶体管T6的第二极与发光元件EL的阳极电连接。第五晶体管T5和第六晶体管T6还可以称为发光控制晶体管。第一晶体管T1与第三晶体管T3的栅极电连接，并配置为对第三晶体管T3的栅极进行复位，第七晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一晶体管T1的栅极与第二扫描线GL2电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第三晶体管T3的栅极电连接。第七晶体管T7的栅极与第三扫描线GL3电连接，第七晶体管T7的第一极与第二初始信号线INIT2电连接，第七晶体管T7的第二极与发光元件EL的阳极电连接。第一晶体管T1和第七晶体管T7还可以称为复位控制晶体管。存储电容Cst的第一极板与第三晶体管T3的栅极电连接，存储电容Cst的第二极板与第一电源线VDD电连接。
在本示例中，第一节点N1为存储电容Cst、第一晶体管T1、第三晶体管T3和第二晶体管T2的连接点，第二节点N2为第五晶体管T5、第四晶体管T4和第三晶体管T3的连接点，第三节点N3为第三晶体管T3、第二晶体管T2和第六晶体管T6的连接点，第四节点N4为第六晶体管T6、第七晶体管T7和发光元件EL的连接点。
下面对像素电路的工作过程进行说明。以图2所示的像素电路包括的多个晶体管均为P型晶体管为例进行说明。本示例中，第三扫描线GL3提供的第三扫描信号与第一扫描线GL1提供的第一扫描信号可以相同。
在一些示例中，在一帧显示时间段，像素电路的工作过程可以包括：第一阶段、第二阶段和第三阶段。
第一阶段，称为复位阶段。第二扫描线GL2提供的第二扫描信号SCAN2可以为低电平信号，使第一晶体管T1导通，第一初始信号线INIT1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中的原有数据电压。第一扫描线GL1提供的第一扫描信号SCAN1可以为高电平信号，发光控制线EML提供的发光控制信号EM可以为高电平信号，使第四晶体管T4、第二晶体管T2、第五晶体管T5、第六晶体管T6以及第七晶体管T7断开。此阶段发光元件EL不发光。
第二阶段，称为数据写入阶段或者阈值补偿阶段。第一扫描线GL1提供的第一扫描信号SCAN1可以为低电平信号，第二扫描线GL2提供的第二扫描信号SCAN2和发光控制线EML提供的发光控制信号EM可以均为高电平信号，数据线DL输出数据信号DATA。此阶段由于存储电容Cst的第一极板为低电平，因此，第三晶体管T3导通。第一扫描信号SCAN1为低电平信号，使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通，使得数据线DL输出的数据电压Vdata经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据线DL输出的数据电压Vdata与第三晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第一极板(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至发光元件EL的阳极，对发光元件EL的阳 极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第二扫描线GL2提供的第二扫描信号SCAN2可以为高电平信号，使第一晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段，称为发光阶段。发光控制线EML提供的发光控制信号EM为低电平信号，第一扫描线GL1提供的第一扫描信号SCAN1和第二扫描线GL2提供的第二扫描信号SCAN2为高电平信号。发光控制线EML提供的发光控制信号EM为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的第一电压信号Vdd通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路驱动过程中，流过第三晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K×(Vgs-Vth)2＝K×[(Vdd-Vdata+|Vth|)-Vth]2＝K×[Vdd-Vdata]2。
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为第三晶体管T3的栅极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，Vdd为第一电源线VDD输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与第三晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿第三晶体管T3的阈值电压。
图3为本公开至少一实施例的一种显示面板的示意图。在一些示例中，如图3所示，显示区域AA的至少一个子像素可以包括：像素电路61以及发光元件62。发光元件62可以位于像素电路61远离衬底的一侧。像素电路61与发光元件62电连接，可以被配置为驱动对应的发光元件62发光。发光元件62与所连接的像素电路61在衬底的正投影可以至少部分交叠。图3中以多个像素电路61和多个发光元件62为例进行示意，且图3中示意的像素电路61和发光元件62之间可以没有电连接关系。在本示例中，沿第一方向X依次排布的多个发光元件62可以称为一行发光元件，沿第一方向X依次排布的多个像素电路61可以称为一行像素电路，沿第二方向Y依次排布的多个像素电路61可以称为一列像素电路，沿第二方向Y依次排布的多个发光元件62可以称为一列发光元件。
在一些示例中，如图3所示，第一边框区域B1可以包括：信号接入区域B11。信号接入区域B11可以被配置为设置集成电路，例如，集成电路可以为显示驱动器集成电路(DDI，Display Driver Integration)或者可以为触控与显示驱动器集成电路(TDDI，Touch and Display Driver Integration)。
在一些示例中，如图3所示，第一边框区域B1可以设置有第一检测控制单元33a和33b、第二检测控制单元34a和34b、以及第一电源边框线51a。第一电源边框线51a可以至少沿第一方向X延伸，且在第二方向Y上位于信号接入区域B11靠近显示区域AA的一侧。第一电源边框线51a可以与显示区域AA内沿第二方向Y延伸的多条第一电源线电连接，被配置为给多条第一电源线提供第一电压信号。
在一些示例中，如图3所示，第一检测控制单元33a和第二检测控制单元34a可以位于第一边框区域B1内靠近第三边框区域B3的位置，第一检测控制单元33b和第二检测控制单元34b可以位于第一边框区域B内靠近第四边框区域B4的位置。第一检测控制单元33a和33b、第二检测控制单元34a和34b可以位于信号接入区域B11靠近显示区域AA的一侧。第一检测控制单元33a可以位于第二检测控制单元34a在第一方向X上靠近 显示面板边缘的一侧，第一检测控制单元33b可以位于第二检测控制单元34b在第一方向X上靠近显示面板边缘的一侧。
在一些示例中，如图3所示，第一检测控制单元33a可以包括：第一检测晶体管M1。第一检测晶体管M1的栅极可以与第一检测控制线35a电连接，第一检测晶体管M1的第一极与第一测试信号传输线36a电连接，第一检测晶体管M1的第二极与第一检测线31a电连接。第一检测控制线35a可以延伸至信号接入区域B11，并与信号接入区域B11内的一个第一检测控制引脚电连接。第一测试信号传输线36a可以延伸至信号接入区域B11，并与信号接入区域B11内的一个第一测试信号引脚电连接。
在一些示例中，如图3所示，第一检测控制单元33b可以包括：第一检测晶体管M1’。第一检测晶体管M1’的栅极可以与第一检测控制线35b电连接，第一检测晶体管M1’的第一极与第一测试信号传输线36b电连接，第一检测晶体管M1’的第二极与第一检测线31b电连接。第一检测控制线35b可以延伸至信号接入区域B11，并与信号接入区域B11内的另一个第一检测控制引脚电连接。第一测试信号传输线36b可以延伸至信号接入区域B11，并与信号接入区域B11内的另一个第一测试信号引脚电连接。信号接入区域B11内传输相同第一检测控制信号的第一检测控制引脚可以相互电连接，传输相同第一测试信号的第一测试信号引脚可以相互电连接。
在一些示例中，如图3所示，第二检测控制单元34a可以包括：第二检测晶体管M2。第二检测晶体管M2的栅极可以与第二检测控制线37a电连接，第二检测晶体管M2的第一极与第二测试信号传输线38a电连接，第二检测晶体管M2的第二极与第二检测线32电连接。第二检测控制线37a可以延伸至信号接入区域B11，并与信号接入区域B11内的一个第二检测控制引脚电连接。第二测试信号传输线38a可以延伸至信号接入区域B11，并与信号接入区域B11内的一个第二测试信号引脚电连接。
在一些示例中，如图3所示，第二检测控制单元34b可以包括：第二检测晶体管M2’。第二检测晶体管M2’的栅极可以与第二检测控制线37b电连接，第二检测晶体管M2’的第一极与第二测试信号传输线38b电连接，第二检测晶体管M2’的第二极与第二检测线32电连接。第二检测控制线37b可以延伸至信号接入区域B11，并与信号接入区域B11内的另一个第二检测控制引脚电连接。第二测试信号传输线38a可以延伸至信号接入区域B11，并与信号接入区域B11内的另一个第二测试信号引脚电连接。信号接入区域B11内传输相同第二检测控制信号的第二检测控制引脚可以相互电连接，传输相同第二测试信号的第二测试信号引脚可以相互电连接。
在一些示例中，如图3所示，第三边框区域B3可以设置有栅极驱动电路41a、边框初始信号线42a、以及第一检测线31a。栅极驱动电路41a例如可以包括扫描驱动电路，扫描驱动电路可以包括沿第二方向Y排布的多个扫描移位寄存器，扫描驱动电路可以配置为给显示区域AA的多条扫描线提供扫描信号(例如给多条第一扫描线GL1提供第一扫描信号，给多条第二扫描线GL2提供第二扫描信号，给多条第三扫描线GL3提供第三扫描信号)。边框初始信号线42a可以位于栅极驱动电路41a靠近显示区域AA的一侧。例如，边框初始信号线42a可以包括传输第一初始信号的第一边框初始信号线，或者可以包括传输第一初始信号的第一边框初始信号线和传输第二初始信号的第二边框初始信号线。
在一些示例中，如图3所示，第一检测线31a可以包括：第一主线311a和多条第一子线312a。图3中以六条第一子线312a为例进行示意，本实施例对于第一子线312a的数目并不限定。多条第一子线312a和第一主线311a电连接。第一主线311a可以至少沿第二方向Y延伸。多条第一子线312a可以沿第二方向Y依次排布。第一主线311a可以 位于栅极驱动电路41a和边框初始信号线42a靠近显示区域AA的一侧。例如，第一主线311a可以位于边框初始信号线42a远离栅极驱动电路41a的一侧。每条第一子线312a的一部分线段可以位于栅极驱动电路41a远离显示区域AA的一侧。例如，每条第一子线312a的一部分线段可以位于第三边框区域B3的电源线区，且位于低电平电源线远离显示区域AA的一侧。每条第一子线312a与第一主线311a连接后可以沿第一方向X向远离显示区域AA的一侧延伸，直至经过栅极驱动电路41a后，再绕线沿第一方向X向靠近显示区域AA的一侧延伸，最终延伸至与显示区域AA内的一个子像素的发光元件62的阳极电连接。本示例利用第一子线312a在远离第一主线311a一侧的边缘进行绕线设计，可以有利于精准定位第三边框区域B3的边缘裂纹位置，从而提高工作效率。
图4为本公开至少一实施例的显示面板的局部走线示意图。图4中示意了一条第一子线的绕线方式。在一些示例中，如图3和图4所示，第一子线312a可以至少包括：第一线段3121、第二线段3122、第一跨线3123、第二跨线3124、以及第一连接段3125。第二跨线3124、第一线段3121、第一跨线3123、第二线段3122以及第一连接段3125可以依次电连接。第二跨线3124可以与第一主线311a电连接，第一连接段3125可以与显示区域AA的一个子像素的发光元件62的阳极电连接。例如，第一跨线3123和第二跨线3124可以至少沿第一方向X延伸，第一线段3121可以至少沿第二方向Y延伸，第二线段3122和第一连接段3125可以至少沿第一方向X延伸。本示例中，第一子线312a的位于栅极驱动电路41a远离显示区域AA一侧的一部分线段可以包括第一线段3121。
在一些示例中，如图3和图4所示，第一跨线3123和第二跨线3124在衬底的正投影与栅极驱动电路41a和边框初始信号线42a在衬底的正投影可以存在交叠，第一线段3121和第二线段3122在衬底的正投影与栅极驱动电路41a和边框初始信号线42a在衬底的正投影可以没有交叠。第一线段3121可以位于栅极驱动电路41a远离显示区域AA的一侧，第二线段3122和第一连接段3125可以位于边框初始信号线42a靠近显示区域AA的一侧。例如，第一跨线3123和第二跨线3124可以为同层结构，第一线段3121和第二线段3122可以为同层结构，第一连接段3125和第二线段3122可以位于不同膜层。
在一些示例中，如图3和图4所示，第一子线312a的第一跨线3123、第一线段3121和第二跨线3124可以形成一个回折部。然而，本实施例对此并不限定。在另一些示例中，第一子线可以为蛇形走线，并具有多个回折部。其中，蛇形走线是一种弯折曲线。例如，走线一端沿一个方向延伸一段距离后，弯折迂回并向与该方向的相反方向延伸一段距离，再次弯折迂回而向该方向延伸，如此反复弯折迂回若干次，形成蛇形走线。
在一些示例中，如图3所示，第一检测线31a的多条第一子线312a与多个子像素的发光元件62可以一一对应电连接。第一检测线31a所连接的多个子像素的发光元件62可以排布为一列，例如第一检测线31a所连接的多个子像素的发光元件62可以包括最靠近第三边框区域B3的一列发光元件62。第一检测线31a的每条第一子线312a可以独立地与一个发光元件62电连接。本示例通过设置每条第一子线312a与发光元件62独立电连接，可以有利于根据发光元件62是否被点亮来精确定位第三边框区域B3的边缘裂纹位置。
在一些示例中，如图3所示，第四边框区域B4可以设置有栅极驱动电路41b、边框初始信号线42b、以及第一检测线31b。栅极驱动电路41b例如可以包括发光驱动电路，发光驱动电路可以包括沿第二方向Y排布的多个发光移位寄存器，发光驱动电路可以配置为给显示区域AA的多条发光控制线提供发光控制信号。边框初始信号线42b可以位于栅极驱动电路41b靠近显示区域AA的一侧。边框初始信号线42a和边框初始信号线42b可以相互电连接。
在一些示例中，如图3所示，第一检测线31b可以包括：第一主线311b和多条第一子线312b。图3中以六条第一子线312b为例进行示意，本实施例对于第一子线312b的数目并不限定。多条第一子线312b和第一主线311b电连接。第一主线311b可以至少沿第二方向Y延伸。第一主线311b可以位于栅极驱动电路41b和边框初始信号线42b靠近显示区域AA的一侧。例如，第一主线311b可以位于边框初始信号线42b远离栅极驱动电路41b的一侧。每条第一子线312b的一部分线段可以位于栅极驱动电路41b远离显示区域AA的一侧。例如，每条第一子线312b的一部分线段可以位于第四边框区域B4的电源线区，且位于低电平电源线远离显示区域AA的一侧。每条第一子线312b与第一主线311b连接后可以沿第一方向X向远离显示区域AA的一侧延伸，直至经过栅极驱动电路41b后，再绕线沿第一方向X向靠近显示区域AA的一侧延伸，最终延伸至与显示区域AA内的一个子像素的发光元件62的阳极电连接。本示例利用第一子线312b在远离第一主线311b一侧的边缘进行绕线设计，可以有利于精准定位第四边框区域B4的边缘裂纹位置，从而提高工作效率。关于第一子线312b的绕线设计可以参照第一子线312a的说明，故于此不再赘述。
在一些示例中，如图3所示，第一检测线31b所连接的多个子像素的发光元件62可以排布为一列，例如可以包括最靠近第四边框区域B4的一列发光元件62。第一检测线31b的每条第一子线312b可以独立地与一个发光元件62电连接。本示例通过设置每条第一子线312b与发光元件62独立电连接，可以有利于根据发光元件62是否被点亮来精确定位第四边框区域B4的边缘裂纹位置。
在一些示例中，如图3所示，第二边框区域B2可以设置有第一电源边框线51b、以及第二检测线32。第一电源边框线51b可以至少沿第一方向X延伸。第一电源边框线51b可以与显示区域AA内沿第二方向Y延伸的多条第一电源线电连接。
在一些示例中，如图3所示，第二检测线32可以包括：第二主线321和多条第二子线322。图3中以四条第二子线322为例进行示意，本实施例对于第二子线322的数目并不限定。多条第二子线322和第二主线321电连接。第二主线321可以至少沿第一方向X延伸。多条第二子线322可以沿第一方向X依次排布。第二主线321可以位于第一电源边框线51b靠近显示区域AA的一侧。每条第二子线322的一部分线段可以位于第一电源边框线51b远离显示区域AA的一侧。每条第二子线322与第二主线321连接后沿第二方向Y向远离显示区域AA的一侧延伸，直至经过第一电源边框线51b后，再绕线沿第二方向Y向靠近显示区域AA的一侧延伸，最终延伸至与显示区域AA内的一个子像素的像素电路61电连接。
图7为本公开至少一实施例的显示面板的另一局部走线示意图。图7中示意了一条第二子线322的绕线方式。在一些示例中，如图3和图7所示，第二子线322可以至少包括：第三线段3221、第四线段3222、第三跨线3223、第四跨线3224以及第二连接段3225。第四跨线3224、第三线段3221、第三跨线3223、第四线段3222以及第二连接段3225可以依次电连接。第四跨线3224可以与第二主线321电连接，第二连接段3225可以与显示区域AA的子像素的像素电路61电连接。例如，第三跨线3223和第四跨线3224可以至少沿第二方向Y延伸，第三线段3221可以至少沿第一方向X延伸，第四线段3222和第二连接段3225可以沿第二方向Y延伸。本示例中，第二子线322的位于第一电源边框线51b远离显示区域AA一侧的一部分线段可以包括第三线段3221。
在一些示例中，如图3和图7所示，第三跨线3223和第四跨线3224在衬底的正投影与第一电源边框线51b在衬底的正投影可以存在交叠，第三线段3221和第四线段3222在衬底的正投影与第一电源边框线51b在衬底的正投影可以没有交叠。第三线段3221可 以位于第一电源边框线51b远离显示区域AA的一侧，第四线段3222和第二连接段3225可以位于第一电源边框线51b靠近显示区域AA的一侧。例如，第三跨线3223和第四跨线3224可以为同层结构，第三线段3221和第四线段3222可以为同层结构，第二连接段3225和第四线段3222可以位于不同膜层。
在一些示例中，如图3和图7所示，第二子线322的第三跨线3223、第三线段3221和第四跨线3224可以形成一个回折部。然而，本实施例对此并不限定。在另一些示例中，第二子线可以为蛇形走线，具有多个回折部。
在一些示例中，如图3所示，第二检测线32的多条第二子线322与多个子像素的像素电路61可以一一对应电连接。第二检测线32所连接的多个子像素的像素电路61可以排布为一行，例如，第二检测线32所连接的像素电路61可以包括最靠近第二边框区域B2的一行像素电路61中去除第一个和最后一个像素电路以外的像素电路。该行像素电路中的第一个像素电路可以与最靠近第三边框区域B3的一列发光元件中的一个发光元件电连接，该行像素电路中的最后一个像素电路可以与最靠近第四边框区域B4的一列发光元件的一个发光元件电连接。本示例的第一检测线31a和31b所连接的子像素不同于第二检测线32所连接的子像素，以避免第一检测线31a和31b和第二检测线32的检测效果相互影响。
在一些示例中，如图3所示，第二检测线32的每条第二子线322可以与一个像素电路61的数据写入晶体管(例如前述像素电路中的第四晶体管T4)的源极电连接。每条第二子线322可以独立地与像素电路61的数据写入晶体管电连接。本示例通过设置每条第二子线322与像素电路61的数据写入晶体管独立电连接，可以有利于根据像素电路61所连接的发光元件是否被点亮来精确定位第二边框区域B2的边缘裂纹位置。
在一些示例中，如图3所示，第二边框区域B2还可以设置有第一连接线313。第三边框区域B3内的第一检测线31a可以通过第一连接线313与第四边框区域B4内的第一检测线31b电连接。第一连接线313的两端可以分别与第一检测线31a的第一主线311a和第一检测线31b的第一主线311b电连接。第一连接线313可以位于第一电源边框线51b靠近显示区域AA的一侧，例如可以位于第二检测线32的第二主线321靠近第一电源边框线51b的一侧。然而，本实施例对此并不限定。本示例中，利用第一连接线313将第三边框区域B3内的第一检测线31a和第四边框区域B4内的第一检测线31b电连接，可以实现第一测试信号在第三边框区域B3、第二边框区域B2和第四边框区域B4内的环绕传输，有利于周边区域的排线，还有利于周边区域的边缘裂纹检测。
在一些示例中，如图3所示，显示区域AA还可以设置有第二连接线323a和323b。第二边框区域B2的第二检测线32的第二主线321的一端可以与第二连接线323a电连接，并通过第二连接线323a与第二检测控制单元34a电连接。第二主线321的另一端可以与第二连接线323b电连接，并通过第二连接线323b与第二检测控制单元34b电连接。通过设置第二连接线323a和323b位于显示区域，可以避免在第三边框区域B3和第四边框区域B4排线对第二测试信号的传输产生影响。
图6为本公开至少一实施例的显示区域的局部剖面示意图。图6中以显示区域的两个子像素为例进行示意。在一些示例中，如图6所示，在垂直于显示面板的方向上，显示面板的显示区域可以至少包括：衬底10、以及设置在衬底10上的电路结构层12、发光结构层13以及封装结构层14。电路结构层12可以包括：依次设置在衬底10上的阻挡(Barrier)层101、底部遮光金属(BSM，Bottom Shielding Metal)层、缓冲(Buffer)层102、半导体层、第一栅绝缘层103、第一栅金属层、第二栅绝缘层104、第二栅金属层、层间绝缘(ILD)层105、第一源漏金属层、第一平坦(PLN)层106、第二源漏金属层以及第二 平坦层107。图6中的电路结构层12以每个子像素包括的一个晶体管21(例如前述实施例的像素电路中的第六晶体管)和一个第一电容22(例如前述实施例的像素电路中的存储电容)为例进行示意。其中，阻挡层101、缓冲层102、第一栅绝缘层103、第二绝缘层104、以及层间绝缘层105可以为无机绝缘层，第一平坦层106和第二平坦层107可以为有机绝缘层。阻挡层101和缓冲层102可以防止衬底10中的有害物质侵入显示面板的内部，还可以增加显示面板中的膜层在衬底10上的附着力。然而，本实施例对此并不限定。在另一些示例中，第一源漏金属层和第二源漏金属层之间还可以设置钝化层，钝化层可以位于第一平坦层靠近衬底的一侧。
在一些示例中，阻挡层101、缓冲层102、第一栅绝缘层103、第二绝缘层104、以及层间绝缘层105可以采用硅氧化物(SiOx，x>0)、硅氮化物(SiNy，y>0)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一平坦层106和第二平坦层107可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。底部遮光金属层、第一栅金属层和第二栅金属层可以采用金属材料，例如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，可以是单层结构。第一源漏金属层和第二源漏金属层可以采用金属材料，例如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等一种或多种材料，即本公开适用于基于氧化物(Oxide)技术、硅技术以及有机物技术制造的晶体管。本实施例对此并不限定。
在一些示例中，如图6所示，显示区域的底部遮光金属层可以被配置为至少部分覆盖像素电路的晶体管的有源层，以避免外部光线对晶体管的性能产生影响。例如，底部遮光金属层可以至少包括：底部遮光块20，底部遮光块20在衬底10的正投影可以覆盖晶体管21的有源层210的沟道区在衬底10的正投影。
在一些示例中，如图6所示，显示区域的半导体层可以至少包括：晶体管21的有源层210。晶体管21的有源层210可以包括：第一区、第二区以及位于第一区和第二区之间的沟道区。第一栅金属层可以至少包括：晶体管21的栅极213、以及第一电容22的第一极板221。晶体管21的栅极213在衬底10的正投影可以覆盖有源层210的沟道区在衬底10的正投影。第二栅金属层可以至少包括：第一电容22的第二极板222。第一电容22的第二极板222和第一极板221在衬底10的正投影可以至少部分交叠，例如，两者可以重合。第一源漏金属层可以至少包括：晶体管21的源极211和漏极212。层间绝缘层105在显示区域可以开设有多个过孔(例如，包括第一像素过孔和第二像素过孔)，第一像素过孔内的层间绝缘层103、第二栅绝缘层102和第一栅绝缘层101可以被去掉，暴露出有源层210的第一区的至少部分表面；第二像素过孔内的层间绝缘层103、第二栅绝缘层102和第一栅绝缘层101可以被去掉，暴露出有源层210的第二区的至少部分表面。晶体管21的源极211可以通过第一像素过孔与有源层210的第一区电连接，漏极212可以通过第二像素过孔与有源层210的第二区电连接。第二源漏金属层可以至少包括：第一转接电极23。第一转接电极23可以通过第一平坦层106开设的第三像素过孔与像素电路的晶体管21的漏极212电连接。第一转接电极23可以通过第二平坦层107开设的第四像素过孔与发光元件的第一电极131(例如阳极)电连接。本示例可以通过第一转接电极23实现像素电路与发光元件之间的电连接。
在一些示例中，如图6所示，显示区域的发光结构层13可以包括：像素定义层134和多个发光元件。例如，每个发光元件可以包括：叠设的第一电极131、有机发光层132 和第二电极133。发光元件的第一电极131可以为阳极，第一电极131可以设置在第二平坦层107上，并通过第二平坦层107开设的第四像素过孔，与第一转接电极23电连接。像素定义层134设置在第一电极131和第二平坦层107上，像素定义层134可以开设有多个像素开口，一个像素开口可以暴露出对应的一个第一电极131的至少部分表面。有机发光层132的至少部分可以设置在一个像素开口内，并与对应的第一电极131连接。第二电极133可以设置在有机发光层132上，并与有机发光层132连接。有机发光层132在第一电极131和第二电极133的驱动下可以出射相应颜色的光线。像素定义层134远离衬底10的一侧还可以设置隔离柱层，隔离柱层可以包括多个隔离柱(PS)135。
在一些示例中，如图6所示，显示区域的发光元件的有机发光层132可以包括发光层(EML，Emitting Layer)，以及包括空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子阻挡层(EBL，Electron Block Layer)、电子注入层(EIL，Electron Injection Layer)、电子传输层(ETL，Electron Transport Layer)中的一个或多个膜层。在第一电极131和第二电极133的电压驱动下，可以利用有机材料的发光特性根据需要的灰度发光。
在一些示例中，不同颜色的发光元件的发光层可以不同。例如，红色发光元件包括红色发光层，绿色发光元件包括绿色发光层，蓝色发光元件包括蓝色发光层。为了降低工艺难度和提升良率，位于发光层一侧的空穴注入层和空穴传输层可以采用共通层，位于发光层另一侧的电子注入层和电子传输层可以采用共通层。在一些示例中，空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以通过一次工艺(一次蒸镀工艺或一次喷墨打印工艺)制作，并通过形成的膜层表面段差或者通过表面处理等手段实现隔离。例如，相邻子像素对应的空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以是隔离的。在一些示例中，有机发光层可以通过采用精细金属掩模版(FMM，Fine Metal Mask)或者开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在一些示例中，如图6所示，封装结构层14可以包括叠设的第一封装层141、第二封装层142和第三封装层143。其中，第一封装层141和第三封装层143可以采用无机材料，第二封装层142可以采用有机材料，第二封装层142可以设置在第一封装层141和第三封装层143之间，以保证外界水汽无法进入发光元件。然而，本实施例对此并不限定。例如，封装结构层可以采用无机/有机/无机/有机/无机的五层叠设结构。
在一些示例中，如图6所示，显示面板还可以包括：位于封装结构层14远离衬底10一侧的触控结构层15以及彩色滤光层16。彩色滤光层16可以位于触控结构层15远离封装结构层14的一侧。彩色滤光层16可以包括：不同颜色的多个滤光单元(例如包括滤光单元163)、位于不同滤光单元之间的黑矩阵162、位于黑矩阵162和多个滤光单元靠近衬底10一侧的彩膜缓冲层(CBL)161、以及位于黑矩阵162和多个滤光单元远离衬底10一侧的彩膜保护层(COC)164。在一些示例中，彩色滤光层16的多个滤光单元可以包括：多个红色滤光单元、多个绿色滤光单元和多个蓝色滤光单元。不同颜色的滤光单元可以与发光结构层13的出射不同颜色的发光元件对应。例如，蓝色滤光单元可以与蓝色发光元件对应，蓝色滤光单元在衬底的正投影与蓝色发光元件的发光区域在衬底的正投影可以至少部分交叠，比如，蓝色滤光单元在衬底的正投影可以覆盖蓝色发光元件的发光区域在衬底的正投影。本示例中，滤光单元可以使单一颜色光通过并吸收其他颜色光。例如，蓝色滤光单元可以让蓝光通过并吸收其他颜色光。
图5为图4所示的第一子线的局部剖面示意图。在一些示例中，如图3至图6所示，第一子线312a的第一线段3121和第二线段3122可以位于第一栅金属层，第一跨线3123 和第二跨线3124可以位于底部遮光金属层，第一连接段3125例如可以位于第二源漏金属层。第一线段3121可以通过第一栅绝缘层103和缓冲层102开设的第一连接过孔与第一跨线3123的一端电连接，第一跨线3123可以从栅极驱动电路41a和边框初始信号线42a的下方延伸，以跨过栅极驱动电路41a和边框初始信号线42a。栅极驱动电路41a例如可以包括第二电容，第二电容可以包括位于第一栅金属层的第一极板271和位于第二栅金属层的第二极板272。第一线段3121和第一跨线3123的连接位置可以位于栅极驱动电路41a远离显示区域的一侧。第一跨线3123的另一端可以通过第一栅绝缘层103和缓冲层102开设的第二连接过孔与第二线段3122电连接。第一跨线3123和第二线段3122的连接位置可以位于栅极驱动电路41a和边框初始信号线42a靠近显示区域的一侧。第二线段3122可以与第一连接段3125电连接，例如，第一连接段3125可以通过第二平坦层107、第一平坦层106、层间绝缘层105和第二栅绝缘层104开设的第三连接过孔与位于第一栅金属层的第二线段3122电连接。
在一些示例中，如图6所示，第一连接段3125延伸至显示区域后，可以与显示区域内靠近第三边框区域的一个发光元件的阳极131电连接。发光元件的阳极131可以通过第二平坦层107开设的第四连接过孔与第一连接段3125电连接，从而实现发光元件的阳极131与第一子线312a的电连接。
本示例利用设置在底部遮光金属层的第一跨线3123和第二跨线3124来使得第一子线在栅极驱动电路和边框初始信号线所在区域进行跳线，可以避免第一子线对栅极驱动电路和边框初始信号线的影响，而且便于走线排布，有利于节省空间。
图8为图7所示的第二子线的局部剖面示意图。在一些示例中，如图3、图7和图8所示，第二子线322的第三线段3221和第四线段3222可以位于第一栅金属层，第三跨线3223和第四跨线3224可以位于底部遮光金属层。第二连接段3225例如可以位于第二源漏金属层。第一电源边框线51b例如可以位于第一源漏金属层。
在一些示例中，如图7和图8所示，第二子线322的第三线段3221可以通过第一栅绝缘层103和缓冲层102开设的第五连接过孔与第三跨线3223的一端电连接，第三跨线3223可以从第一电源边框线51b的下方延伸，以跨过第一电源边框线51b。第三线段3221和第三跨线3223的连接位置可以位于第一电源边框线51b远离显示区域的一侧。第三跨线3223的另一端可以通过第一栅绝缘层103和缓冲层102开设的第六连接过孔与第四线段3222电连接。第三跨线3223和第四线段3222的连接位置可以位于第一电源边框线51b靠近显示区域AA的一侧。第四线段3222可以与第二连接段3225电连接，例如，第二连接段3225可以通过第二平坦层107、第一平坦层106、层间绝缘层105和第二栅绝缘层104开设的第七连接过孔与位于第一栅金属层的第四线段3222电连接。
图9为本公开至少一实施例的第二子线与像素电路的连接示意图。图10A为图9中形成半导体层后的像素电路的示意图。图10B为图9中形成第一栅金属层后的像素电路的示意图。图10C为图9中形成第二栅金属层后的像素电路的示意图。图10D为图9中形成第一源漏金属层后的像素电路的示意图。本示例的像素电路可以为前述实施例所示的7T1C的像素电路。
在一些示例中，如图10A所示，显示区域的半导体层可以包括：像素电路的多个晶体管的有源层(例如包括：本行像素电路的第一晶体管的有源层T10、第二晶体管的有源层T20、第三晶体管的有源层T30、第四晶体管的有源层T40、第五晶体管的有源层T50、第六晶体管的有源层T60和第七晶体管的有源层T70，上一行像素电路的第七晶体管的有源层T70’，下一行像素电路的第一晶体管的有源层T10’)。像素电路的七个晶体管的有源层可以为相互连接的一体结构。
在一些示例中，如图10B所示，显示区域的第一栅金属层可以至少包括：第一扫描线GL1(n)、第二扫描线GL2(n)、第三扫描线GL3(n)以及发光控制线EML(n)。第二扫描线GL2(n)可以同时作为本行像素电路的第一晶体管T1的栅极以及上一行像素电路的第七晶体管T7’的栅极。第一扫描线GL1(n)可以同时作为本行像素电路的第二晶体管T2的栅极和第四晶体管T4的栅极。第三扫描线GL3(n)可以同时作为本行像素电路的第七晶体管T7的栅极和下一行像素电路的第一晶体管T1’的栅极。发光控制线EML(n)可以同时作为本行像素电路的第五晶体管T5的栅极和第六晶体管T6的栅极。存储电容的第一极板221可以同时作为第三晶体管T3的栅极。
在一些示例中，如图10C所示，显示区域的第二栅金属层可以至少包括：第一初始信号线INIT1、存储电容的第二极板222、以及保护块24。保护块24可以避免其他信号对数据信号的干扰。
在一些示例中，如图10D所示，显示区域的第一源漏金属层可以至少包括：数据线DL、第一电源线VDD、以及多个连接电极(例如第一连接电极251、第二连接电极252、第三连接电极253和第四连接电极254)。第一连接电极251可以与第一晶体管T1的有源层T10和第一初始信号线INIT1电连接。第二连接电极252可以与第二晶体管T2的有源层T20和第三晶体管T3的栅极电连接。第三连接电极253可以与第六晶体管T6的有源层T60电连接，第三连接电极253可以相当于第六晶体管T6的漏极。第四连接电极254可以第一初始信号线INIT1和第七晶体管T7的有源层T70电连接。数据线DL和第一电源线VDD可以均沿第二方向Y延伸。数据线DL可以与第四晶体管T4的有源层电连接。第一电源线VDD可以与保护块24、存储电容的第二极板222以及第五晶体管T5的有源层T50电连接。
在一些示例中，如图9所示，显示区域的第二源漏金属层可以至少包括：第一转接电极23、第二检测线的第二子线的第二连接段3225。第一转接电极23可以与第三连接电极253电连接。第二连接段3225可以与一个像素电路的数据写入晶体管(即第四晶体管T4)的有源层T40电连接。第二连接段3225可以作为数据写入晶体管的源极。一条第二子线322可以独立地与一个像素电路的数据写入晶体管T4连接，可以减少对正常显示过程的干扰。
下面对本示例的显示面板的裂纹检测方法进行举例说明。下述示例中以第一检测晶体管和第二检测晶体管均为P型晶体管为例。然而，本实施例对此并不限定。在另一些示例中，第一检测晶体管和第二检测晶体管可以均为N型晶体管；或者，第一检测晶体管为P型晶体管，第二检测晶体管为N型晶体管；或者，第一检测晶体管为N型晶体管，第二检测晶体管为P型晶体管。
在一些示例，如图3所示，通过控制第一检测控制线35a和35b传输的第一检测控制信号的电压Vg1、第二检测控制线37a和37b传输的第二检测控制信号的电压Vg2、第一测试信号传输线36a和36b传输的第一测试信号的电压Vpcd1、第二测试信号传输线38a和38b传输的第二测试信号的电压Vpcd2，并根据显示区域的显示效果可以确定周边区域是否存在裂纹并精确定位周边区域的边缘裂纹的位置。
在一些示例中，如图3所示，通过第一检测控制信号可以控制第一检测晶体管M1和M1’导通，通过第二检测控制信号可以控制第二检测晶体管M2和M2’断开，通过第一检测晶体管M1和M1’给第一检测线31a和31b提供第一测试信号，可以根据显示区域内与第一检测线31a和31b连接的发光元件62的显示效果来确定第一测试信号在第一检测线31a和31b的传输情况，从而定位周边区域的第三边框区域B3和第四边框区域B4的裂纹位置。
图11A和图11B为本公开至少一实施例的第三边框区域和第四边框区域的裂纹检测的显示图案示意图。在本示例中，以第一检测线31a和31b各自连接一列子像素的发光元件62为例。在一些示例中，在裂纹检测过程中，当第三边框区域B3和第四边框区域B4没有裂纹，第一检测线31a和31b传输的第一测试信号可以正常提供给所连接的发光元件62的阳极，使得所连接的发光元件62正常显示。在一些示例中，如图11B所示，显示区域的第一亮线L1可以指示第三边框区域B3没有裂纹，第二亮线L2可以指示第四边框区域B4没有裂纹。第一亮线L1和第二亮线L2可以为竖向贯穿的亮线。
在一些示例中，在裂纹检测过程中，当第三边框区域B3或第四边框区域B4存在裂纹，在裂纹位置绕线的第一检测线的第一子线无法将第一测试信号传输至显示区域的对应发光元件，则与裂纹位置的第一子线连接的发光元件不会被点亮，显示区域会出现竖向不贯穿的亮线，在裂纹对应位置的亮线会断开。如图11A所示，第三边框区域B3的第一位置W1发生裂纹，则在第一位置W1绕线的第一子线312a无法将第一测试信号传输至显示区域对应的发光元件62，显示区域的第一亮线L1会存在第一断口L10，根据第一断口L10的位置可以定位第三边框区域B3的第一位置W1发生裂纹。第四边框区域B4的第二位置W2发生裂纹，则在第二位置W2绕线的第二子线312b无法将第一测试信号传输至显示区域的对应发光元件，显示区域的第二亮线L2会存在第二断口L20，根据第二断口L20的位置可以定位第四边框区域B4的第二位置W2发生裂纹。
在一些示例中，设置第一检测控制信号的电压Vg1为-7V，第一测试信号的电压Vpcd1为4.6V，第一电压信号Vdd为0V，第二电压信号Vss为0V，数据电压Vdata为0～5V，第二检测控制信号的电压Vg2为7V，第二测试信号的电压Vpcd2为0V。此时，第一检测晶体管M1和M1’导通，第二检测晶体管M2和M2’断开。本示例可以根据第一检测线31a和31b对第一测试信号的传输情况来确定第三边框区域B3和第四边框区域B4的裂纹情况。由于第一检测晶体管M1和M1’导通，第一测试信号的电压Vpcd1可以被传输至第一检测线31a和31b，第一检测线31a的第一主线311a和第一检测线31b的第一主线311b可以将第一测试信号传输给多条第一子线312a和312b。由于第一子线312a在第三边框区域B3内存在绕线设计，在第三边框区域B3的边缘出现裂纹时，该边缘裂纹位置对应的第一子线312a会断开，无法将第一测试信号传输给对应的发光元件，使得对应的发光元件不会发光；在第三边框区域B3的非裂纹位置的第一子线312a可以正常传输第一测试信号给对应的发光元件，使得对应的发光元件正常发光。由于第一子线312b在第四边框区域B4内存在绕线设计，在第四边框区域B4的边缘出现裂纹时，该边缘裂纹位置对应的第一子线312b会断开，无法将第一测试信号传输给对应的发光元件，使得对应的发光元件不会发光；在第四边框区域B4的非裂纹位置的第一子线312b可以正常传输第一测试信号给对应的发光元件，使得对应的发光元件正常发光。本示例利用第一检测线31a和31b可以精确定位第三边框区域B3和第四边框区域B4的裂纹位置。
在一些示例中，如图3所示，通过第一检测控制信号可以控制第一检测晶体管M1和M1’断开，通过第二检测控制信号可以控制第二检测晶体管M2和M2’导通，通过第二检测晶体管M2和M2’给第二检测线32提供第二测试信号，可以根据显示区域内与第二检测线32连接的发光元件的显示效果来确定第二测试信号在第二检测线32的传输情况，从而确定第二边框区域是否存在裂纹并定位周边区域的第二边框区域的裂纹位置。
图12为本公开至少一实施例的第二边框区域的裂纹检测的显示图案示意图。在本示例中，以第二检测线32连接一行子像素中除两端以外的其余子像素的像素电路为例。在一些示例中，在裂纹检测过程中，当第二边框区域B2没有裂纹，第二检测线32传输的第二测试信号可以正常提供给所连接的像素电路，使得该像素电路所连接的发光元件不显 示。例如，显示区域出现贯穿横向的暗线，指示第二边框区域B2没有裂纹。
在一些示例中，在裂纹检测过程中，当第二边框区域B2存在裂纹，在裂纹位置绕线的第二检测线32的第二子线322无法将第二测试信号传输至显示区域对应的像素电路，则与裂纹位置的第二子线322连接的像素电路61所连接的发光元件会被点亮，显示区域会出现横线不贯穿的暗线，在裂纹对应位置的暗线会断开显示亮线。如图12所示，第二边框区域B2的第三位置W3发生裂纹，则在第三位置W3绕线的第二子线322无法将第二测试信号传输至显示区域的对应像素电路61，显示区域会显示第三亮线L3。根据第三亮线L3的位置，可以定位第二边框区域B2的第三位置W3发生裂纹。
在一些示例中，设置第一检测控制信号的电压Vg1为7V，第一测试信号的电压Vpcd1为0V，第二检测控制信号的电压Vg2为-7V，第二测试信号的电压Vpcd2为7V，第一电压信号Vdd为4.6V，第二电压信号Vss为-2.4。此时，第一检测晶体管M1和M1’断开，第二检测晶体管M2和M2’导通。本示例可以根据第二检测线32对第二测试信号的传输情况来确定第二边框区域B2的裂纹情况。由于第二检测晶体管M2和M2’导通，第二测试信号的电压Vpcd2可以被传输至第二检测线32，第二检测线32的第二主线321可以将第二测试信号传输给多条第二子线322。由于第二子线322在第二边框区域B2内存在绕线设计，在第二边框区域B2的边缘出现裂纹时，该边缘裂纹位置对应的第二子线322会断开，无法将第二测试信号传输给对应的像素电路，使得对应像素电路所连接的发光元件会被点亮。在第二边框区域B2的非裂纹位置的第二子线322可以正常传输第二测试信号给对应的像素电路，使得该像素电路所连接的发光元件不发光。本示例利用第二检测线322可以确定第二边框区域B2是否存在裂纹并精确定位第二边框区域B2的裂纹位置。
在一些示例中，在裂纹检测过程中，可以设置第一检测控制信号的电压Vg1为-7V，第二检测控制信号的电压Vg2为-7V，使得第一检测晶体管和第二检测晶体管均导通，根据两列子像素以及一行子像素的显示效果来判断第三边框区域、第四边框区域以及第二边框区域是否存在裂纹并定位裂纹位置。
在一些示例中，在显示区域正常显示过程中，可以设置第一检测控制信号的电压Vg1为7V，第二检测控制信号的电压Vg2为7V，使得第一检测晶体管和第二检测晶体管均断开，避免对正常显示过程产生影响。
在另一些示例中，显示面板的第一边框区域可以设置第二检测线，第二检测线的设置方式可以与第二边框区域类似，本实施例对此并不再赘述。
本示例的显示面板，通过在第三边框区域和第四边框区域设置第一检测线，在第二边框区域设置第二检测线，利用第一检测线传输第一测试信号的显示效果以及第二检测线传输第二测试信号的显示效果可以确定边框区域是否存在裂纹，并根据显示效果可以精确定位裂纹所在位置，从而提高裂纹检测效率。
图13为本公开至少一实施例的另一种显示面板的示意图。在一些示例中，如图13所示，第三边框区域B3可以设置有第一检测线31a，第四边框区域B4可以设置有第一检测线31b，第二边框区域B2可以设置有第二检测线32。
在一些示例中，如图13所示，第一检测线31a可以包括：第一主线311a以及与第一主线311a电连接的多条第一子线312a。第一主线311a可以位于栅极驱动电路41a远离显示区域AA的一侧，多条第一子线312a可以位于第一主线311a靠近显示区域AA的一侧。多条第一子线312a可以沿第二方向Y依次排布，并沿第一方向X延伸至显示区域AA，并与显示区域AA内的多个发光元件62一一对应电连接。第一子线312a在经过栅极驱动电路41a和边框初始信号线42a时可以采用位于底部遮光金属层的第一跨线实现跳 线，以避免干扰，防止不同信号之间的短路。
在一些示例中，如图13所示，第一检测线31b可以包括第一主线311b以及与第一主线311b电连接的多条第一子线312b。第一主线311b可以位于栅极驱动电路41b远离显示区域AA的一侧，多条第一子线312b可以位于第一主线311b靠近显示区域AA的一侧。多条第一子线312b可以沿第二方向Y依次排布，并沿第一方向X延伸至显示区域AA，并与显示区域AA内的多个发光元件62一一对应电连接。第一子线312b在经过栅极驱动电路41b和边框初始信号线42b时可以采用位于底部遮光金属层的第一跨线实现跳线，以避免干扰，防止不同信号之间的短路。
在一些示例中，如图13所示，第二检测线32可以包括：第二主线321以及与第二主线321电连接的多条第二子线322。第二主线321可以位于第一电源边框线51b远离显示区域AA的一侧，多条第二子线322可以位于第二主线321靠近显示区域AA的一侧。多条第二子线322可以沿第一方向X依次排布，并沿第二方向Y延伸至显示区域AA，并与显示区域AA内的多个像素电路61一一对应电连接。第二子线321在经过第一电源边框线51b时可以采用位于底部遮光金属层的第三跨线实现跳线，以避免干扰，防止不同信号之间的短路。
在一些示例中，在裂纹检测过程中，当第三边框区域B3存在裂纹，经过裂纹位置的第一主线311a及第一子线312a无法继续传输第一测试信号，则裂纹位置及裂纹位置远离第一边框区域B1一侧的第一子线312a所连接的发光元件62均不会接收到第一测试信号，无法被点亮。显示区域AA会显示局部亮线，没有亮线的位置对应的第三边框区域B3的边缘即存在裂纹。当第三边框区域B3没有裂纹，则显示区域AA可以显示如图11B所示的第一亮线L1。同理可以确定第四边框区域B4是否存在裂纹，以及裂纹的位置。
在一些示例中，在裂纹检测过程中，当第二边框区域B2存在裂纹，经过裂纹位置的第二主线321及第二子线322无法继续传输第二测试信号，则无法传输第二测试信号的第二子线322的位置所连接的像素电路的发光元件均被会点亮，在显示区域AA对应显示亮线。根据显示区域AA的亮线位置可以确定第二边框区域B2的裂纹位置。
关于本示例的显示面板的其余说明可以参照前述实施例的描述，故于此不再赘述。
图14为本公开至少一实施例的另一种显示面板的示意图。在一些示例中，如图14所示，第三边框区域B3可以设置有第一检测线31a，第一检测线31a可以与第三连接线314a电连接，第三连接线314a可以位于显示区域。第四边框区域B4可以设置有第一检测线31b，第一检测线31b可以与第三连接线314b电连接。第三连接线314b可以位于显示区域。在一些示例中，第三连接线314a可以位于第二连接线323a靠近第三边框区域B3的一侧，第三连接线314b可以位于第二连接线323b靠近第四边框区域B4的一侧。本示例的第一检测线31a和31b没有直接连接，而是各自通过第三连接线与第一检测控制单元实现连接回路。本示例可以避免占用第二边框区域B2的布线空间。
关于本示例的显示面板的其余说明可以参照前述实施例的描述，故于此不再赘述。
图15为本公开至少一实施例的另一显示面板的示意图。在一些示例中，如图15所示，第三边框区域B3可以设置有第一检测线31a，第四边框区域B4可以设置有第一检测线31b，第二边框区域B2可以设置有第一检测线31c。第一检测线31c的两端可以分别与第一检测线31a和第一检测线31b电连接。第一检测线31a可以与第一检测控制单元33a电连接，第一检测线31b可以与第一检测控制单元33b电连接。
在一些示例中，如图15所示，第一检测线31a可以包括第一主线311a和多条第一子线312a。第一主线311a可以位于栅极驱动电路41a靠近显示区域AA的一侧，每条第一 子线312a的一部分线段(例如前述的第一线段)可以位于栅极驱动电路41a远离显示区域AA的一侧。多条第一子线312a可以沿第二方向Y依次排布，并延伸至显示区域AA，与显示区域AA内的多个像素电路61一一对应电连接。第一子线312a在经过栅极驱动电路41a和边框初始信号线42a时可以采用位于底部遮光金属层的第一跨线和第二跨线实现跳线，以避免干扰，防止不同信号之间的短路。
在一些示例中，如图15所示，第一检测线31b可以包括第一主线311b以及与第一主线311b电连接的多条第一子线312b。第一主线311b可以位于栅极驱动电路41b靠近显示区域AA的一侧，每条第一子线312b的一部分线段可以位于栅极驱动电路41b远离显示区域AA的一侧。多条第一子线312b可以沿第二方向Y依次排布，并延伸至显示区域AA，与显示区域AA内的多个像素电路61一一对应电连接。第一子线312b在经过栅极驱动电路41b和边框初始信号线42b时可以采用位于底部遮光金属层的第一跨线和第二跨线实现跳线，以避免干扰，防止不同信号之间的短路。
在一些示例中，如图15所示，第一检测线31c可以包括第一主线311c以及与第一主线311c电连接的多条第一子线312c。第一主线311c可以位于第一电源边框线51b靠近显示区域AA的一侧。多条第一子线312c可以沿第二方向Y依次排布，并延伸至显示区域AA，与显示区域AA内的多个像素电路61一一对应电连接。第一子线312c在经过第一电源边框线51b时可以采用位于底部遮光金属层的跨线实现跳线，以避免干扰，防止不同信号之间的短路。
在一些示例中，在裂纹检测过程中，可以根据第一检测线31a、31b和31c所连接的两列子像素和一行子像素的显示情况，来确定第三边框区域、第四边框区域和第二边框区域是否存在裂纹以及裂纹位置。本示例可以根据裂纹检测过程中显示区域内的亮线位置来定位裂纹位置。然而，本实施例对此并不限定。在另一些示例中，第一检测线的第一主线可以位于多条第一子线远离显示区域的一侧。
关于本示例的显示面板的其余说明可以参照前述实施例的描述，故于此不再赘述。
图16为本公开至少一实施例的另一显示面板的示意图。在一些示例中，如图16所示，第三边框区域B3可以设置有第一检测线31a，第四边框区域B4可以设置有第一检测线31b，第二边框区域B2可以设置有第一检测线31c。第一检测线31c的两端可以分别与第一检测线31a和第一检测线31b电连接。第一检测线31a可以与第一检测控制单元33a电连接，第一检测线31b可以与第一检测控制单元33b电连接。第一检测线31a、31b和31c分别与显示区域的多个子像素的发光元件62的阳极电连接。本示例可以根据裂纹检测过程中显示区域内的暗线位置来定位裂纹位置。然而，本实施例对此并不限定。在另一些示例中，第一检测线的第一主线可以位于多条第一子线远离显示区域的一侧。
关于本示例的显示面板的其余说明可以参照前述实施例的描述，故于此不再赘述。
图17为本公开至少一实施例的另一显示面板的平面示意图。在一些示例中，如图17所示，显示区域AA可以包括：多个子像素PX、沿第一方向X延伸的多条数据线DL、以及沿第二方向Y延伸的多条第一电源线VDD。多条数据线DL可以沿第二方向Y依次排布，多条第一电源线VDD可以沿第一方向X依次排布。每条数据线DL可以与沿第一方向X排布的多个子像素的像素电路电连接，被配置为给所述多个像素电路提供数据信号。每条第一电源线VDD可以与沿第二方向Y排布的多个子像素的像素电路电连接，被配置为给所述多个子像素提供第一电压信号。在一些示例中，数据线DL和第一电源线VDD可以位于不同膜层，以避免两者之间的相互干扰。例如，数据线DL可以位于第一源漏金属层，第一电源线VDD可以位于第二源漏金属层；或者，数据线DL可以位于第 二源漏金属层，第一电源线VDD可以位于第一源漏金属层。
图18为本公开至少一实施例的另一显示面板的示意图。在一些示例中，如图18所示，显示区域AA的多条数据线DL沿第一方向X延伸，多条第一电源线VDD沿第二方向Y延伸。第三边框区域B3可以设置有数据供应总线(或数据供应电路)43a和栅极驱动电路41a。数据供应总线43a可以位于栅极驱动电路41a靠近显示区域AA的一侧。第四边框区域B4可以设置有数据供应总线43b和栅极驱动电路41b。数据供应总线43b可以位于栅极驱动电路41b靠近显示区域AA的一侧。显示区域AA的多条数据线DL可以与数据供应总线43a和43b电连接。数据供应总线43a和43b可以与信号接入区域B11内的多个数据引脚电连接。设置在信号接入区域B11的集成电路可以配置为通过多个数据引脚提供数据信号。
在一些示例中，如图18所示，第三边框区域B3可以设置有第一检测线31a。第一检测线31a可以包括第一主线311a和多条第一子线312a。第一主线311a可以位于数据供应总线43a靠近显示区域AA的一侧。多条第一子线312a可以沿第二方向Y依次排布，并与第一主线311a电连接。例如，第一子线312a可以在第一方向X向第一主线311a远离显示区域AA的一侧延伸，直至延伸至栅极驱动电路41a远离显示区域AA的一侧，随后第一子线312a再绕线沿第一方向X向靠近显示区域AA的一侧延伸，最终延伸至与一条数据线DL电连接。多条第一子线312a和多条数据线DL可以一一对应电连接。第一子线312a与数据线DL的连接位置可以位于第一主线311a靠近显示区域AA的一侧，或者，可以位于显示区域AA内。本实施例对此并不限定。第一子线312a在经过栅极驱动电路41a和数据供应总线43a时可以采用位于底部遮光金属层的第一跨线和第二跨线实现跳线，以避免干扰，防止不同信号之间的短路。
在一些示例中，如图18所示，第四边框区域B4可以设置有第一检测线31b。第一检测线31b可以包括第一主线311b和多条第一子线312b。第一主线311b可以位于数据供应总线43b靠近显示区域AA的一侧。多条第一子线312b可以沿第二方向Y依次排布，并与第一主线311b电连接。例如，第一子线312b可以在第一方向X向第一主线311b远离显示区域AA的一侧延伸，直至延伸至栅极驱动电路41b远离显示区域AA的一侧，随后第一子线312b再绕线沿第一方向X向靠近显示区域AA的一侧延伸，最终延伸至与一条数据线DL电连接。多条第一子线312b和多条数据线DL可以一一对应电连接。第一子线312b与数据线DL的连接位置可以位于第一主线311b靠近显示区域AA的一侧，或者，可以位于显示区域AA内。本实施例对此并不限定。第一子线312b在经过栅极驱动电路41b和数据供应总线43b时可以采用位于底部遮光金属层的第一跨线和第二跨线实现跳线，以避免干扰，防止不同信号之间的短路。
在一些示例中，如图18所示，第二边框区域B2可以设置有第一电源边框线51b和第二检测线32。第二检测线32可以通过位于显示区域AA的第二连接线323a与第二检测控制单元34a电连接，通过位于显示区域AA的第二连接线323b与第二检测控制单元34b电连接。第二检测线32可以包括：第二主线321和多条第二子线322。第二主线321可以位于第一电源边框线51b靠近显示区域AA的一侧。每条第二子线322的一部分线段(例如前述的第三线段)可以位于第一电源边框线51b远离显示区域AA的一侧。每条第二子线322与第二主线321连接后沿第二方向Y向远离显示区域AA的一侧延伸，直至经过第一电源边框线51b后，再绕线沿第二方向Y向靠近显示区域AA的一侧延伸，最终延伸至与显示区域AA内的一条第一电源线VDD电连接。多条第二子线322和多条第一电源线VDD可以一一对应电连接。第二子线322在经过第一电源边框线51b时可以采用位于底部遮光金属层的第三跨线和第四跨线实现跳线，以避免干扰，防止不同信号之间 的短路。
在一些示例中，第一检测线31a所连接的数据线的条数和第一检测线31b所连接的数据线的条数可以相同。第一检测线31a所连接的多条数据线和第一检测线31b所连接的多条数据线可以相同。然而，本实施例对此并不限定。第一检测线31a所连接的多条数据线可以不同于第一检测线31b所连接的多条数据线，以便更好地区分第三边框区域B3和第四边框区域B4的裂纹位置。本示例对于第一检测线31a所连接的数据线的数目以及第二检测线31b所连接的第一电源线的数目并不限定。
下面对本示例的显示面板的裂纹检测方法进行举例说明。下述示例中以第一检测晶体管和第二检测晶体管均为P型晶体管为例。
在一些示例中，如图18所示，在裂纹检测过程中，当第三边框区域B3和第四边框区域B4没有裂纹，第一检测线31a和31b传输的第一测试信号可以正常提供给所连接的数据线DL，使得数据线DL所连接的子像素不发光，显示区域AA可以显示多条暗线。当第三边框区域B3或第四边框区域B4存在裂纹时，在裂纹位置绕线的第一检测线的第一子线无法将第一测试信号传输至对应的数据线，使得与裂纹位置对应的数据线所连接的子像素会被点亮，显示区域AA会显示对应的亮线。如此一来，可以根据显示区域的横向亮线位置来确定第三边框区域B3和第四边框区域B4是否存在裂纹以及第三边框区域B3和第四边框区域B4的裂纹位置。
在一些示例中，设置第一检测控制信号的电压Vg1为-7V，第一测试信号的电压Vpcd1为7V，第二检测控制信号的电压Vg2为7V，第二测试信号的电压Vpcd2为0V，数据电压Vdata为7V。此时，第一检测晶体管M1和M1’导通，第二检测晶体管M2和M2’断开。当第三边框区域B3和第四边框区域B4没有裂纹，显示区域均显示为暗线；当第三边框区域B3或第四边框区域B3存在裂纹，显示区域的对应位置显示亮线。如此一来，可以根据显示区域的亮线位置来定位第三边框区域B3和第四边框区域B4的裂纹位置。
在一些示例中，如图18所示，在裂纹检测过程中，当第二边框区域B2没有裂纹，第二检测线32传输的第二测试信号可以正常提供给所连接的第一电源线VDD，例如使得第一电源线VDD所连接的子像素可以正常显示。当第二边框区域B2存在裂纹，第二检测线32传输的第二测试信号无法提供给所连接的第一电源线VDD，例如使得第一电源线VDD所连接的子像素无法正常显示。如此一来，可以根据显示区域的暗线位置来定位第二边框区域B2的裂纹位置。然而，本实施例对此并不限定。在另一些示例中，当第二边框区域B2没有裂纹，可以利用第二测试信号使得第一电源线VDD所连接的子像素不显示，当第二边框区域B2存在裂纹，使得第一电源线VDD所连接的子像素显示，从而根据显示区域的亮线位置来定位裂纹位置。
在一些示例中，设置第一检测控制信号的电压Vg1为7V，第一测试信号的电压Vpcd1为0V，第二检测控制信号的电压Vg2为-7V，第二测试信号的电压Vpcd2为4.6V，第一端电压信号Vdd和第二电压信号Vss均为0V。此时，第一检测晶体管M1和M1’断开，第二检测晶体管M2和M2’导通。当第二边框区域B2没有裂纹，显示区域可以显示亮线；当第二边框区域B2存在裂纹，显示区域的对应位置可以显示暗线。如此一来，可以根据显示区域的暗线位置来定位第二边框区域B2的裂纹位置。
在一些示例中，在裂纹检测过程中，可以设置第一检测控制信号的电压Vg1为-7V，第二检测控制信号的电压Vg2为-7V，使得第一检测晶体管和第二检测晶体管均导通，根据不同行和不同列子像素的显示效果来判断第三边框区域、第四边框区域以及第二边框区域是否存在裂纹并定位裂纹位置。
本示例的显示面板，通过在第三边框区域和第四边框区域设置第一检测线，在第二边框区域设置第二检测线，利用第一检测线传输第一测试信号给数据线的显示效果以及第二检测线传输第二测试信号给第一电源线的显示效果可以确定边框区域是否存在裂纹，并根据显示效果可以精确定位裂纹所在位置，从而提高裂纹检测效率。
图19为本公开至少一实施例的另一种显示面板的示意图。在一些示例中，如图19所示，第三边框区域B3可以设置有第一检测线31a，第四边框区域B4可以设置有第一检测线31b，第二边框区域B2可以设置有第二检测线32。
在一些示例中，如图19所示，第一检测线31a可以包括：第一主线311a以及与第一主线311a电连接的多条第一子线312a。第一主线311a可以位于栅极驱动电路41a远离显示区域AA的一侧，多条第一子线312a可以位于第一主线311a靠近显示区域AA的一侧。多条第一子线312a可以沿第二方向Y依次排布，并沿第一方向X延伸至显示区域AA，并与显示区域AA内的多条数据线DL一一对应电连接。第一子线312a在经过栅极驱动电路41a和数据供应总线43a时可以采用位于底部遮光金属层的第一跨线实现跳线，以避免干扰，防止不同信号之间的短路。
在一些示例中，如图19所示，第一检测线31b可以包括第一主线311b以及与第一主线311b电连接的多条第一子线312b。第一主线311b可以位于栅极驱动电路41b远离显示区域AA的一侧，多条第一子线312b可以位于第一主线311b靠近显示区域AA的一侧。多条第一子线312b可以沿第二方向Y依次排布，并沿第一方向X延伸至显示区域AA，并与显示区域AA内的多条数据线DL一一对应电连接。第一子线312b在经过栅极驱动电路41b和数据供应总线43b时可以采用位于底部遮光金属层的第一跨线实现跳线，以避免干扰，防止不同信号之间的短路。
在一些示例中，如图19所示，第二检测线32可以包括：第二主线321以及与第二主线321电连接的多条第二子线322。第二主线321可以位于第一电源边框线51b远离显示区域AA的一侧，多条第二子线322可以位于第二主线321靠近显示区域AA的一侧。多条第二子线322可以沿第一方向X依次排布，并沿第二方向Y延伸至显示区域AA，并与显示区域AA内的多条第一电源线VDD一一对应电连接。第二子线321在经过第一电源边框线51b时可以采用位于底部遮光金属层的第三跨线实现跳线，以避免干扰，防止不同信号之间的短路。
在一些示例中，在裂纹检测过程中，当第三边框区域B3存在裂纹，经过裂纹位置的第一主线311a及第一子线312a无法继续传输第一测试信号，则裂纹位置及裂纹位置远离第一边框区域B1一侧的第一子线312a所连接的数据线DL均不会接收到第一测试信号，数据线DL所连接的子像素会被点亮。显示区域的亮线的位置对应的第三边框区域B3的边缘即存在裂纹。当第三边框区域B3没有裂纹，则显示区域可以显示暗线。同理可以确定第四边框区域B4是否存在裂纹，以及裂纹的位置。
在一些示例中，在裂纹检测过程中，当第二边框区域B2存在裂纹，经过裂纹位置的第二主线321及第二子线322无法继续传输第二测试信号，则无法传输第二测试信号的第二子线322的位置所连接的第一电源线所连接的发光元件无法被点亮，在显示区域AA对应显示暗线。根据显示区域AA的暗线位置可以确定第二边框区域B2的裂纹位置。
关于本示例的显示面板的其余说明可以参照前述实施例的描述，故于此不再赘述。
本实施例还提供一种裂纹检测方法，应用于如上所述的显示面板，所述裂纹检测方法包括：通过第一检测控制单元向第一检测线提供第一测试信号；根据与所述第一检测线电连接的多个子像素的发光状态，确定周边区域是否存在裂纹以及裂纹所在的位置。
在一些示例性实施方式中，本示例的裂纹检测方法还可以包括：通过第二检测控制单元向第二检测线提供第二测试信号；根据与所述第二检测线电连接的多个子像素的发光状态，确定所述周边区域是否存在裂纹以及裂纹所在位置。
关于本示例的裂纹检测方法的说明可以参照前述实施例的描述，故于此不再赘述。
本实施例还提供一种显示面板，包括：衬底、多个子像素、至少一条第一检测线和至少一个第一检测控制单元。衬底包括显示区域和位于所述显示区域外围的周边区域。多个子像素位于所述显示区域。至少一条第一检测线和至少一个第一检测控制单元位于所述周边区域，所述至少一个第一检测控制单元与所述至少一条第一检测线电连接，被配置为给所述至少一条第一检测线提供第一测试信号。所述至少一条第一检测线与所述显示区域的多个子像素电连接。所述至少一条第一检测线包括：第一主线、以及与所述第一主线电连接的多条第一子线，所述多条第一子线延伸至所述显示区域，每条第一子线与所述显示区域的至少一个子像素电连接。所述多条第一子线中的至少一条第一子线的一部分线段位于所述第一主线远离所述显示区域的一侧。例如，多条第一子线中的每条第一子线的一部分线段(例如前述实施例的第一线段)可以位于第一主线远离显示区域的一侧。
在一些示例性实施方式中，所述周边区域还可以设置有栅极驱动电路。所述第一主线可以位于所述栅极驱动电路靠近所述显示区域的一侧，每条第一子线的一部分线段可以位于所述栅极驱动电路远离所述显示区域的一侧。
在一些示例性实施方式中，显示面板还可以包括：位于所述周边区域的第二检测线和至少一个第二检测控制单元，所述至少一个第二检测控制单元与所述第二检测线电连接，被配置为给所述第二检测线提供第二测试信号。所述第二检测线与所述显示区域的多个子像素电连接。所述第二检测线与所述显示区域的多个子像素的连接方式不同于所述第一检测线与所述显示区域的多个子像素的连接方式。在一些示例中，如图3所示，第一检测线可以与多个子像素的发光元件的阳极电连接，第二检测线可以与多个子像素的像素电路的数据写入晶体管的源极电连接。在另一些示例中，如图18所示，第一检测线可以与多条数据线电连接，第二检测线可以与多条第一电源线电连接。
在一些示例性实施方式中，所述第二检测线可以包括：第二主线以及与所述第二主线电连接的多条第二子线；每条第二子线与所述显示区域的至少一个子像素电连接，所述多条第二子线沿着所述第二主线的延伸方向依次排布。所述第二主线的延伸方向与所述第一检测线的第一主线的延伸方向交叉。
关于本示例的显示面板的说明可以参照前述实施例的描述，故于此不再赘述。
图20为本公开至少一实施例的显示装置的示意图。如图20所示，本实施例提供一种显示装置，包括：显示面板91以及位于远离显示面板91的发光结构层的出光侧的传感器92。传感器92可以位于显示面板91的非显示面一侧。传感器92在显示面板91上的正投影与第一显示区A1可以存在交叠。
在一些示例性实施方式中，显示面板91可以为柔性OLED显示面板、QLED显示面板、Micro-LED显示面板、或者Mini-LED显示面板。显示装置可以为具有图像(包括静态图像或动态图像，其中，动态图像可以是视频)显示功能的产品。例如，显示装置可以是：显示器、电视机、广告牌、数码相框、具有显示功能的激光打印机、电话、手机、画屏、个人数字助理(PDA，Personal Digital Assistant)、数码相机、便携式摄录机、取景器、导航仪、车辆、大面积墙壁、信息查询设备(比如电子政务、银行、医院、电力等部门的业务查询设备)、监视器等中的任一种产品。又如，显示装置还可以是微显示器，包含微显示器的VR设备或AR设备等中的任一种产品。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (25)

  1. 一种显示面板，包括：
    衬底，包括显示区域和位于所述显示区域外围的周边区域；
    多个子像素和多条数据线，位于所述显示区域，所述多个子像素和所述多条数据线电连接，所述多个子像素中的至少一个子像素包括：像素电路和发光元件，所述像素电路和所述发光元件电连接，被配置为驱动所述发光元件发光；
    至少一条第一检测线和至少一个第一检测控制单元，位于所述周边区域，所述至少一个第一检测控制单元与所述至少一条第一检测线电连接，被配置为给所述至少一条第一检测线提供第一测试信号；
    所述至少一条第一检测线通过以下任一方式与所述显示区域的多个子像素电连接：
    所述至少一条第一检测线与所述显示区域的多个子像素的发光元件的阳极电连接；
    所述至少一条第一检测线与所述显示区域的多个子像素的像素电路的数据写入晶体管的源极电连接；
    所述至少一条第一检测线与所述显示区域的多条数据线电连接，所述多条数据线中的至少一条数据线与沿第一方向排布的多个子像素电连接，所述至少一条第一检测线至少位于所述显示区域沿所述第一方向相对两侧的周边区域内。
  2. 根据权利要求1所述的显示面板，其中，所述至少一条第一检测线包括：第一主线以及与所述第一主线电连接的多条第一子线，每条第一子线与所述显示区域的至少一个子像素电连接；所述多条第一子线沿着所述第一主线的延伸方向依次排布。
  3. 根据权利要求2所述的显示面板，其中，所述周边区域还设置有栅极驱动电路；
    所述第一主线位于所述栅极驱动电路靠近所述显示区域的一侧，每条第一子线的一部分线段位于所述栅极驱动电路远离所述显示区域的一侧。
  4. 根据权利要求2所述的显示面板，其中，所述周边区域还设置有栅极驱动电路；
    所述第一主线位于所述栅极驱动电路远离所述显示区域的一侧，所述多条第一子线位于所述第一主线靠近所述显示区域的一侧。
  5. 根据权利要求2至4中任一项所述的显示面板，其中，所述第一检测线的多条第一子线电连接的多个子像素包括：所述显示区域内最靠近所述第一主线且沿所述第一主线的延伸方向排布的多个子像素。
  6. 根据权利要求3或4所述的显示面板，其中，每条第一子线至少包括：第一线段、第二线段以及第一跨线，所述第一跨线的两端分别与所述第一线段和第二线段电连接，所述第一线段位于所述栅极驱动电路远离所述显示区域的一侧，所述第二线段位于所述栅极驱动电路靠近所述显示区域的一侧，所述第一跨线在所述衬底的正投影与所述栅极驱动电路在所述衬底的正投影至少部分交叠；所述第一跨线位于所述第一线段和第二线段靠近所述衬底的一侧。
  7. 根据权利要求6所述的显示面板，其中，在垂直于所述显示面板的方向上，所述显示面板至少包括：衬底以及设置在所述衬底上的底部遮光金属层、半导体层、第一栅金属层、第二栅金属层、第一源漏金属层以及第二源漏金属层；
    所述第一跨线位于所述底部遮光金属层，所述第一线段和所述第二线段位于所述第一栅金属层。
  8. 根据权利要求2至7中任一项所述的显示面板，其中，所述至少一个第一检测控制单元包括：第一检测晶体管，所述第一检测晶体管的栅极与第一检测控制线电连接，所述第一检测晶体管的第一极与第一测试信号传输线电连接，所述第一检测晶体管的第二极与所述第一检测线电连接。
  9. 根据权利要求2至8中任一项所述的显示面板，还包括：位于所述周边区域的第二检测线和至少一个第二检测控制单元；所述至少一个第二检测控制单元与所述第二检测线电连接，被配置为给所述第二检测线提供第二测试信号；
    所述第二检测线与所述显示区域的多个子像素电连接；
    所述第二检测线与所述显示区域的多个子像素的连接方式不同于所述第一检测线与所述显示区域的多个子像素的连接方式。
  10. 根据权利要求9所述的显示面板，其中，所述第二检测线包括：第二主线以及与所述第二主线电连接的多条第二子线；每条第二子线与所述显示区域的至少一个子像素电连接，所述多条第二子线沿着所述第二主线的延伸方向依次排布；
    所述第二主线的延伸方向与所述第一检测线的第一主线的延伸方向交叉。
  11. 根据权利要求10所述的显示面板，其中，所述至少一条第一检测线的多条第一子线和所述显示区域的多个子像素的发光元件的阳极一一对应电连接；
    所述第二检测线的多条第二子线和所述显示区域的多个子像素的像素电路的数据写入晶体管的源极一一对应电连接。
  12. 根据权利要求10所述的显示面板，其中，所述至少一条第一检测线的多条第一子线与所述显示区域的多条数据线一一对应电连接；所述多条数据线沿所述第一方向延伸；
    所述第二检测线的多条第二子线和所述显示区域的多条第一电源线一一对应电连接，所述多条第一电源线沿第二方向延伸，所述第二方向与所述第一方向交叉。
  13. 根据权利要求10所述的显示面板，其中，所述周边区域还设置有第一电源边框线；
    所述第二主线位于所述第一电源边框线靠近所述显示区域的一侧，每条第二子线的一部分位于所述第一电源边框线远离所述显示区域的一侧。
  14. 根据权利要求10所述的显示面板，其中，所述周边区域还设置有第一电源边框线；
    所述第二主线位于所述第一电源边框线远离所述显示区域的一侧，所述多条第二子线位于所述第二主线靠近所述显示区域的一侧。
  15. 根据权利要求10所述的显示面板，其中，所述第二检测线的多条第二子线电连接的多个子像素包括：所述显示区域内最靠近所述第二主线且沿所述第二主线的延伸方向排布的多个子像素。
  16. 根据权利要求13或14所述的显示面板，其中，每条第二子线至少包括：第三线段、第四线段以及第三跨线，所述第三跨线的两端分别与所述第三线段和第四线段电连接，所述第三线段位于所述第一电源边框线远离所述显示区域的一侧，所述第四线段位于所述第一电源边框线靠近所述显示区域的一侧，所述第三跨线在所述衬底的正投影与所述第一电源边框线在所述衬底的正投影至少部分交叠；所述第三跨线位于所述第三线段和所述第四线段靠近所述衬底的一侧。
  17. 根据权利要求16所述的显示面板，其中，在垂直于所述显示面板的方向上，所 述显示面板至少包括：衬底以及设置在所述衬底上的底部遮光金属层、半导体层、第一栅金属层、第二栅金属层、第一源漏金属层以及第二源漏金属层；
    所述第三跨线位于所述底部遮光金属层，所述第三线段和第四线段位于所述第一栅金属层。
  18. 根据权利要求9至17中任一项所述的显示面板，其中，所述第二检测控制单元包括：第二检测晶体管，所述第二检测晶体管的栅极与第二检测控制线电连接，所述第二检测晶体管的第一极与第二测试信号传输线电连接，所述第二检测晶体管的第二极与所述第二检测线电连接。
  19. 一种显示装置，包括如权利要求1至18中任一项所述的显示面板。
  20. 一种裂纹检测方法，应用于如权利要求1至18中任一项所述的显示面板，所述裂纹检测方法包括：
    通过第一检测控制单元向第一检测线提供第一测试信号；
    根据与所述第一检测线电连接的多个子像素的发光状态，确定周边区域是否存在裂纹以及裂纹所在的位置。
  21. 根据权利要求20所述的裂纹检测方法，还包括：
    通过第二检测控制单元向第二检测线提供第二测试信号；
    根据与所述第二检测线电连接的多个子像素的发光状态，确定所述周边区域是否存在裂纹以及裂纹所在位置。
  22. 一种显示面板，包括：
    衬底，包括显示区域和位于所述显示区域外围的周边区域；
    多个子像素，位于所述显示区域；
    至少一条第一检测线和至少一个第一检测控制单元，位于所述周边区域，所述至少一个第一检测控制单元与所述至少一条第一检测线电连接，被配置为给所述至少一条第一检测线提供第一测试信号；
    所述至少一条第一检测线与所述显示区域的多个子像素电连接；
    所述至少一条第一检测线包括：第一主线、以及与所述第一主线电连接的多条第一子线，所述多条第一子线延伸至所述显示区域，每条第一子线与所述显示区域的至少一个子像素电连接；
    所述多条第一子线中的至少一条第一子线的一部分线段位于所述第一主线远离所述显示区域的一侧。
  23. 根据权利要求22所述的显示面板，其中，所述周边区域还设置有栅极驱动电路；
    所述第一主线位于所述栅极驱动电路靠近所述显示区域的一侧，每条第一子线的一部分线段位于所述栅极驱动电路远离所述显示区域的一侧。
  24. 根据权利要求22所述的显示面板，还包括：位于所述周边区域的第二检测线和至少一个第二检测控制单元，所述至少一个第二检测控制单元与所述第二检测线电连接，被配置为给所述第二检测线提供第二测试信号；
    所述第二检测线与所述显示区域的多个子像素电连接；
    所述第二检测线与所述显示区域的多个子像素的连接方式不同于所述第一检测线与所述显示区域的多个子像素的连接方式。
  25. 根据权利要求24所述的显示面板，其中，所述第二检测线包括：第二主线以及与所述第二主线电连接的多条第二子线；每条第二子线与所述显示区域的至少一个子像素电连接，所述多条第二子线沿着所述第二主线的延伸方向依次排布；
    所述第二主线的延伸方向与所述第一检测线的第一主线的延伸方向交叉。
PCT/CN2023/092832 2023-05-08 2023-05-08 显示面板、显示装置及裂纹检测方法 Ceased WO2024229666A1 (zh)

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