WO2024218845A1 - 表示装置 - Google Patents

表示装置 Download PDF

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Publication number
WO2024218845A1
WO2024218845A1 PCT/JP2023/015420 JP2023015420W WO2024218845A1 WO 2024218845 A1 WO2024218845 A1 WO 2024218845A1 JP 2023015420 W JP2023015420 W JP 2023015420W WO 2024218845 A1 WO2024218845 A1 WO 2024218845A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel circuit
stage
signal line
mode
data signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/015420
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English (en)
French (fr)
Japanese (ja)
Inventor
真 横山
展之 他谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Display Technology Corp
Original Assignee
Sharp Display Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Display Technology Corp filed Critical Sharp Display Technology Corp
Priority to PCT/JP2023/015420 priority Critical patent/WO2024218845A1/ja
Priority to JP2025514910A priority patent/JPWO2024218845A1/ja
Publication of WO2024218845A1 publication Critical patent/WO2024218845A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • This disclosure relates to a display device.
  • Patent document 1 discloses a display device equipped with a demultiplexer (DEMUX) to ensure sufficient charging time for data lines during high-speed operation.
  • DEMUX demultiplexer
  • a display device includes an Mth stage pixel circuit, an mth stage pixel circuit that is a stage after the Mth stage, an Nth stage pixel circuit that is a stage after the mth stage, an nth stage pixel circuit that is a stage after the Nth stage, a first data signal line connecting the Mth stage pixel circuit and the Nth stage pixel circuit, a second data signal line connecting the mth stage pixel circuit and the nth stage pixel circuit, a switch circuit connecting the first data signal line and the second data signal line, a data signal source connecting to the switch circuit, and a control unit that controls the switch circuit so that in a first mode, a data signal is supplied from the data signal source to the Mth stage pixel circuit, the mth stage pixel circuit, the Nth stage pixel circuit, and the nth stage pixel circuit in that order, and in a second mode, a control unit that controls the switch circuit so that a data signal is supplied from the data signal source to the Mth stage pixel circuit, the m
  • power consumption in the second mode of a display device equipped with a DEMUX is reduced.
  • FIG. 1 is a schematic diagram illustrating a configuration example of a display device according to an embodiment of the present disclosure.
  • FIG. 11 is a diagram illustrating an example of signal supply in a first mode according to an embodiment of the present disclosure.
  • FIG. 11 is a diagram illustrating an example of signal supply in a second mode according to an embodiment of the present disclosure.
  • FIG. 11 is a diagram illustrating an example of signal supply in a second mode according to an embodiment of the present disclosure.
  • 2 is a diagram showing a configuration example of a pixel circuit shown in FIG. 1;
  • FIG. 11 is a diagram illustrating an example of signal supply in a second mode according to an embodiment of the present disclosure.
  • 1A and 1B are diagrams illustrating an example of signal supply in a first mode and a second mode according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram showing a configuration example of a display device according to an embodiment of the present disclosure.
  • the display device 2 according to the present disclosure includes a display section DA in which a plurality of pixel circuits PC are provided, and a frame section NA located around the display section DA.
  • the pixel circuit PC located in the xth row and yth column is referred to as the pixel circuit PC[x, y] with [x, y] added.
  • the display device 2 includes an Mth stage pixel circuit PC[M,y], an mth stage pixel circuit PC[m,y] which is a stage subsequent to the Mth stage, an Nth stage pixel circuit PC[N,y] which is a stage subsequent to the mth stage, an nth stage pixel circuit PC[n,y] which is a stage subsequent to the Nth stage, a first data signal line DL1[y] connected to the Mth stage pixel circuit PC[M,y] and the Nth stage pixel circuit PC[N,y], a second data signal line DL2[y] connected to the mth stage pixel circuit PC[m,y] and the nth stage pixel circuit PC[n,y], and a switch circuit SWC[y] connected to the first data signal line DL1[y] and the second data signal line DL2[y].
  • the switch circuit SWC is a so-called demultiplexing circuit (DEMUX).
  • the switch circuit SWC[y] switches so that the first data signal line DL1[y] and the second data signal line DL2[y] are connected to the data signal source DS in the order of first, first, second, and second.
  • the first mode makes it easier to ensure the charging and discharging time of the first data signal line DL1 and the second data signal line DL2 by switching the switch circuit SWC. Therefore, the first mode is suitable for high-speed driving.
  • the second mode Compared to the first mode, the second mode requires less switching of the switch circuit SWC and consumes less power to drive the switch circuit SWC[y]. Therefore, the power consumption of the display device 2 in the second mode is reduced.
  • the switch circuit SWC[y] may include a first switch transistor ATr connected between the data signal source DS and the first data line DL1[y], and a second switch transistor BTr connected between the data signal source DS and the second data line DL2[y].
  • the control unit CC may be connected to the gate terminals of the first switch transistor ATr and the second switch transistor BTr via the first control line ASW and the second control line BSW.
  • FIG. 2 is a diagram showing an example of signal supply in a first mode according to an embodiment of the present disclosure.
  • a data signal can be supplied in the order of the Mth stage pixel circuit PC[M,y], the mth stage pixel circuit PC[m,y], the Nth stage pixel circuit PC[N,y], and the nth stage pixel circuit PC[n,y].
  • the Mth stage, the mth stage, the Nth stage, and the nth stage pixel circuits PC[M,y], PC[m,y], PC[N,y], and PC[n,y] can all be updated in one vertical scanning period.
  • FIG. 3 and 4 are diagrams showing an example of signal supply in the second mode according to an embodiment of the present disclosure.
  • data signals are supplied to the pixel circuits PC[M,y] and PC[N,y] of the Mth and Nth stages, and data signals are not supplied to the pixel circuits PC[m,y] and PC[n,y] of the mth and nth stages.
  • FIG. 3 shows that in the second mode, during one of two consecutive vertical scanning periods, data signals are supplied to the pixel circuits PC[M,y] and PC[N,y] of the Mth and Nth stages, and data signals are not supplied to the pixel circuits PC[m,y] and PC[n,y] of the mth and nth stages.
  • the display device 2 includes a first shift register circuit SRC1 connected to the Mth stage pixel circuit PC[M,y] and the Nth stage pixel circuit PC[N,y], and a second shift register circuit SRC2 connected to the mth stage pixel circuit PC[m,y] and the nth stage pixel circuit PC[n,y].
  • the first shift register circuit SRC1 is connected to the first clock signal line GCK1 and the third clock signal line GCK
  • the second shift register circuit SRC2 is connected to the second clock signal line GCK2 and the fourth clock signal line GCK4.
  • a clock signal is supplied to the first clock signal line GCK1 and the third clock signal line GCK3 connected to the first shift register circuit SRC1, and a clock signal is supplied to the second clock signal line GCK2 and the fourth clock signal line GCK4 connected to the second shift register circuit SRC2.
  • the shift operations of both the first shift register circuit SRC1 and the second shift register circuit SRC2 are performed.
  • a constant-level signal is supplied to the second clock signal line GCK2 and the fourth clock signal line GCK4 connected to the second shift register circuit SRC2.
  • a constant-level signal is supplied to the first clock signal line GCK1 and the third clock signal line GCK connected to the first shift register circuit SRC1.
  • the clock signals supplied in the second mode may be the same as the clock signals supplied in the first mode.
  • the vertical scanning period in the first mode and the vertical scanning period in the second mode have the same length.
  • the rewrite frequency of the data signal for the same pixel circuit in the first mode is higher than the rewrite frequency of the data signal for the same pixel circuit in the second mode. That is, it is preferable to drive at high speed in the first mode and at low speed in the second mode.
  • the first mode may be a so-called video display mode or gaming mode.
  • the rewrite frequency of the data signal for the same pixel circuit in the first mode may be 120 Hz or more.
  • the rewrite frequency of the data signal for the same pixel circuit in the second mode may be 60 Hz or less.
  • the frame rate in the first mode is 240 Hz
  • the frame rate in the second mode may be 60 Hz, 30 Hz, 1 Hz, etc.
  • the display device 2 includes a plurality of scanning signal lines GL.
  • the xth row scanning signal line GL[x] is connected to the xth row pixel circuit PC[x, y] and the unit circuit U[x] in the first shift register circuit SRC1 or the second shift register circuit SRC2.
  • FIG. 5 is a diagram showing an example of the configuration of the pixel circuit shown in FIG. 1.
  • each pixel circuit PC[x, y] is provided with a drive transistor T4 and a write transistor T3 connected to the first data signal line DL1[y] or the second data signal line DL2[y], and the gate terminal of the write transistor T3 is connected to one of the multiple scanning signal lines GL (scanning signal line GL[x] in FIG. 5).
  • Each pixel circuit PC[x,y] may include an internal compensation circuit that compensates for the threshold of the drive transistor T4.
  • internal compensation may be performed after a data signal is written.
  • the internal compensation circuit includes a compensation transistor T2, and the source or drain terminal of the drive transistor T4 is connected to the gate terminal via the compensation transistor T2.
  • Each pixel circuit PC[x,y] may further include an initialization transistor T1, T7, a light-emitting transistor T5, T6, and a storage capacitance Cst.
  • Each pixel circuit PC[x,y] may be connected to a light-emitting control line Em[x], a light-emitting element Ed, and wiring that supplies constant potentials ELVdd, ELVss, and Vini.
  • the connection with the data signal source DS switches from the first data signal line DL1[y] to the second data signal line DL2[y].
  • Changing the potential of the wiring requires charging and discharging, which takes time. With this configuration, the charging and discharging time of the second data signal line DL2[y] can be secured.
  • the connection with the data signal source DS switches from the second data signal line DL2[y] to the first data signal line DL1[y]. With this configuration, the charging and discharging time of the first data signal line DL1[y] can be secured.
  • the data signal source DS is connected to the first data signal line DL1[y]. Then, while internal compensation is being performed in the first-stage pixel circuit PC[1,y], the connection to the data signal source is switched from the first data signal line DL1[y] to the second data signal line DL2[y]. Then, after the first-stage scanning signal line GL[1] returns from ON to OFF, the connection to the data signal source is switched from the second data signal line DL2[y] to the first data signal line DL1[y].
  • the scanning signal line GL[M] connected to the Mth pixel circuit [M,y], the scanning signal line GL[m] connected to the mth pixel circuit PC[m,y], the scanning signal line GL[N] connected to the Nth pixel circuit PC[N,y], and the scanning signal line GL[n] connected to the nth pixel circuit PC[n,y] are selected in this order.
  • the scanning signal lines GL are driven in the progressive manner in the first mode.
  • the scanning signal line GL[M] connected to the pixel circuit [M,y] of the Mth stage and the scanning signal line GL[N] connected to the pixel circuit PC[N,y] of the Nth stage are selected in this order.
  • the scanning signal line GL[m] connected to the pixel circuit PC[m,y] of the mth stage and the scanning signal line GL[n] connected to the pixel circuit PC[n,y] of the nth stage are selected in this order.
  • M and N are odd numbers and m and n are even numbers (or when M and N are even numbers and m and n are odd numbers)
  • the scanning signal line GL is driven in the interlaced manner in the second mode.
  • the display device 2 includes a first driver that drives the scanning signal line GL[M] connected to the pixel circuit [M,y] of the Mth stage and the scanning signal line GL[N] connected to the pixel circuit PC[N,y] of the Nth stage, and a second driver that drives the scanning signal line GL[m] connected to the pixel circuit PC[m,y] of the mth stage and the scanning signal line GL[n] connected to the pixel circuit PC[n,y] of the nth stage, and during each vertical scanning period in the second mode, the operation of one of the first driver and the second driver is stopped.
  • the first driver and the second driver operate alternately.
  • the first driver is the first shift register circuit SRC1 described above
  • the second driver is the second shift register circuit SRC2 described above.
  • each pixel circuit PC may be connected to a light-emitting element Ed (see FIG. 5).
  • the light-emitting element Ed connected to the Mth stage pixel circuit PC[M,y] and the light-emitting element Ed connected to the Nth stage pixel circuit PC[N,y] may emit the same color
  • the light-emitting element Ed connected to the mth stage pixel circuit PC[m,y] and the light-emitting element Ed connected to the nth stage pixel circuit PC[n,y] may emit the same color.
  • Each light-emitting element Ed may have an organic light-emitting layer or a quantum dot light-emitting layer.
  • FIG. 6 is a diagram showing an example of signal supply in the second mode according to an embodiment of the present disclosure.
  • a pause period during which no data signal is supplied to any pixel circuit PC may be provided between two consecutive vertical scanning periods.
  • power consumption in the second mode can be further reduced.
  • the pause period can be achieved by providing a period during which a constant level signal is supplied to all of the first through fourth clock signal lines GCK1 through GCK4.
  • FIG. 7 is a diagram illustrating an example of signal supply in a first mode and a second mode according to an embodiment of the present disclosure.
  • the vertical scanning period in the second mode may be longer than the vertical scanning period in the first mode. This configuration can further reduce power consumption in the second mode.
  • the extension of the vertical scanning period can be achieved by reducing the clock frequency in the second mode to be lower than the clock frequency in the first mode.
  • Embodiment 3 can be combined with embodiment 2 described above.
  • the vertical scanning period of the second mode may be longer than the vertical scanning period of the first mode, and a pause period may be provided in the second mode.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
PCT/JP2023/015420 2023-04-18 2023-04-18 表示装置 Ceased WO2024218845A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2023/015420 WO2024218845A1 (ja) 2023-04-18 2023-04-18 表示装置
JP2025514910A JPWO2024218845A1 (https=) 2023-04-18 2023-04-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2023/015420 WO2024218845A1 (ja) 2023-04-18 2023-04-18 表示装置

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006003731A (ja) * 2004-06-18 2006-01-05 Mitsubishi Electric Corp 表示装置
JP2006154810A (ja) * 2004-11-26 2006-06-15 Samsung Sdi Co Ltd 順次走査及び飛び越し走査兼用の駆動回路及びこれを用いた有機電界発光装置
JP2008083320A (ja) * 2006-09-27 2008-04-10 Seiko Epson Corp 電気光学装置、その駆動方法および電子機器
JP2008197626A (ja) * 2006-12-15 2008-08-28 Nvidia Corp 節電のためにディスプレイのリフレッシュレートを調整するシステム、方法、及びコンピュータプログラム製品
JP2014219516A (ja) * 2013-05-07 2014-11-20 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 画素回路及びその駆動方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006003731A (ja) * 2004-06-18 2006-01-05 Mitsubishi Electric Corp 表示装置
JP2006154810A (ja) * 2004-11-26 2006-06-15 Samsung Sdi Co Ltd 順次走査及び飛び越し走査兼用の駆動回路及びこれを用いた有機電界発光装置
JP2008083320A (ja) * 2006-09-27 2008-04-10 Seiko Epson Corp 電気光学装置、その駆動方法および電子機器
JP2008197626A (ja) * 2006-12-15 2008-08-28 Nvidia Corp 節電のためにディスプレイのリフレッシュレートを調整するシステム、方法、及びコンピュータプログラム製品
JP2014219516A (ja) * 2013-05-07 2014-11-20 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 画素回路及びその駆動方法

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