WO2024214205A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024214205A1
WO2024214205A1 PCT/JP2023/014837 JP2023014837W WO2024214205A1 WO 2024214205 A1 WO2024214205 A1 WO 2024214205A1 JP 2023014837 W JP2023014837 W JP 2023014837W WO 2024214205 A1 WO2024214205 A1 WO 2024214205A1
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WO
WIPO (PCT)
Prior art keywords
power supply
supply line
transistor
power
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/014837
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English (en)
French (fr)
Japanese (ja)
Inventor
紘宜 武野
ウェンゼン ワン
淳 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Socionext Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Socionext Inc filed Critical Socionext Inc
Priority to CN202380096942.1A priority Critical patent/CN120917899A/zh
Priority to PCT/JP2023/014837 priority patent/WO2024214205A1/ja
Priority to JP2025513561A priority patent/JPWO2024214205A1/ja
Publication of WO2024214205A1 publication Critical patent/WO2024214205A1/ja
Priority to US19/351,386 priority patent/US20260033000A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/959—Connectability characteristics, i.e. diffusion and polysilicon geometries
    • H10D84/961—Substrate and well contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/981—Power supply lines

Definitions

  • the present invention relates to a semiconductor device.
  • a technology that provides a power switch circuit that switches between supplying and cutting off power to transistors.
  • a known technology is BS-PDN (Backside Power Delivery Network) that provides a power line on the back side of a semiconductor substrate and supplies power to transistors provided on the front side of the semiconductor substrate via TSVs (Through Silicon Vias).
  • BS-PDN Backside Power Delivery Network
  • TSVs Through Silicon Vias
  • a known technology is that directly connects vias from the back side of the semiconductor substrate to the sources and drains of transistors provided on the front side of the semiconductor substrate.
  • the present invention has been made in consideration of the above points, and aims to electrically connect the source of a transistor in a power switch circuit that is not positioned in a position that overlaps with the first power line below the substrate in a plan view to the first power line.
  • a semiconductor device in one aspect of the present invention, includes a substrate in which a first via is formed, a first power supply line formed below the substrate and supplied with a first potential, a second power supply line supplied with a second potential, a third power supply line supplied with a third potential, a power switch circuit formed above the substrate and having a first transistor electrically provided between the first power supply line and the second power supply line, and a second transistor formed above the substrate, wherein the first power supply line, the second power supply line, and the third power supply line each have a planar surface.
  • the first transistor extends in a first direction in a plan view, the first transistor has a first source and a first drain, the first transistor is arranged at a position overlapping the first power supply line in a plan view, the first source is connected to the first via connected to the first power supply line, the second transistor has a second source and a second drain, the second transistor is arranged at a position overlapping the second power supply line in a plan view, and the second source is electrically connected to the first source via a wiring formed above the substrate.
  • the disclosed technology allows the source of a transistor in a power switch circuit that does not overlap with the power line below the semiconductor substrate in a plan view to be connected to the power line below the semiconductor substrate.
  • 1 is a plan view showing an example of a layout of a semiconductor device according to a first embodiment
  • 2 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor device of FIG. 1
  • 2 is a circuit diagram showing an example of a circuit arranged in the standard cell block of FIG. 1
  • 4 is a plan view showing an example of the positional relationship between the power supply lines, virtual power supply lines, ground lines and vias arranged at positions overlapping the standard cell blocks of FIG. 3 in a plan view on the rear surface side of the semiconductor substrate, and a power switch circuit.
  • 5 is a plan view showing an example of the layout of the power switch circuit of FIG. 3 and FIG. 4.
  • 6 is a cross-sectional view showing an example of a cross section taken along line X1-X2 in FIG. 5.
  • 6 is a cross-sectional view showing another example of a cross section taken along line X1-X2 in FIG. 5.
  • 6 is a cross-sectional view showing yet another example of a cross section taken along line X1-X2 of FIG. 5.
  • 4 is a plan view showing a first modified example of the layout of the power switch circuit in FIG. 3.
  • FIG. 4 is a plan view showing a second modified example of the layout of the power switch circuit in FIG. 3 .
  • FIG. 7 is a plan view showing a third modified example of the layout of the power switch circuit in FIG. 3 .
  • FIG. 7 is a plan view showing a fourth modified example of the layout of the power switch circuit in FIG. 3 .
  • FIG. 7 is a plan view showing a fifth modified example of the layout of the power switch circuit in FIG. 3 .
  • 13 is a plan view showing an example of a layout of power supply lines arranged on the back surface side of a semiconductor substrate in a semiconductor device according to a second embodiment;
  • 15 is a plan view showing an example of the layout of the power switch circuit of FIG. 14.
  • 15 is a plan view showing a modified layout of the power switch circuit of FIG. 14.
  • the symbols indicating signals are also used to indicate signal lines or signal terminals.
  • the symbols indicating power supply potential are also used to indicate power supply lines or power supply terminals to which the power supply potential is supplied.
  • Fig. 1 shows an example of a layout of a semiconductor device according to the first embodiment.
  • the semiconductor device 100 shown in Fig. 1 may be a SoC (System on Chip), a standalone FPGA (Field-Programmable Gate Array), or the like.
  • the semiconductor device 100 has a plurality of I/O cells IOC, IOCP and an internal circuit region INTR.
  • the I/O cell IOC is an interface circuit for a signal SIG, such as an input signal, an output signal, or an input/output signal.
  • the I/O cell IOCP is an interface circuit for a power supply potential or a ground potential.
  • Each I/O cell IOC, IOCP is connected to an internal circuit area INTR.
  • the internal circuit area INTR has one or more standard cell blocks SCB in which standard cells are provided.
  • the internal circuit area INTR may be equipped with logic circuits other than standard cells, or may be equipped with memory.
  • the memory may be equipped within the standard cell block SCB.
  • the transistors equipped in the semiconductor device 100 may be finFETs (field effect transistors), nanosheet FETs, or CFETs (complementary FETs).
  • FIG. 2 shows an example of a cross-sectional structure of the semiconductor device 100 of FIG. 1.
  • the semiconductor device 100 has a substrate SUB, a wiring layer WL1 formed on the front surface FS side of the substrate SUB, and a wiring layer WL2 formed on the back surface BS side of the substrate SUB.
  • the front surface FS of the substrate SUB is an example of the upper side of the substrate SUB
  • the back surface BS of the substrate SUB is an example of the lower side of the substrate SUB.
  • a fin FIN which is a part of a transistor, is formed on the front surface of the substrate SUB.
  • the fin FIN has a source, drain, and channel.
  • a pad PAD which is an external connection terminal, is formed on the surface (back surface) of the wiring layer WL2 opposite the substrate SUB.
  • the wiring layer WL2 has multiple wiring layers BSM1 and BSM2 (two layers in FIG. 2, BSM stands for Backside Metal).
  • BSM1 and BSM2 each have wiring W1 and W2 formed therein, which respectively supply a power supply potential and a ground potential.
  • the wiring W1 and W2 are connected to each other through a via VIA1.
  • the wiring W2 and the pad PAD are connected to each other through a via VIA2.
  • the wiring W1 is connected to the source of the fin FIN via a TSV formed in the substrate SUB.
  • the TSV is an example of a first via or a second via.
  • the wiring W1 may be connected to a buried wiring BPR (Buried Power Rail) buried in the surface of the substrate SUB via the TSV.
  • BPR Buried Power Rail
  • the transistors formed on the substrate SUB are not limited to finFETs using fins, and may be, for example, planar MOSFETs, nanosheet FETs, or CFETs (Complementary FETs).
  • planar MOSFETs and nanosheet FETs the via TSV that supplies the power supply potential or ground potential is connected to the source of the transistor.
  • the via TSV that supplies the power supply potential or ground potential may be connected to the source located closest to the substrate SUB.
  • FIG. 3 shows an example of a circuit arranged in the standard cell block SCB of FIG. 1.
  • the standard cell block SCB has a power switch circuit PSW and a standard cell SC.
  • the standard cell SC is connected to a virtual power line VVDD and a ground line VSS, and operates by receiving a supply of a virtual power potential VVDD from the virtual power line VVDD.
  • the power switch circuit PSW has a control circuit CNTL and a switch transistor SWT.
  • the control circuit CNTL is a buffer circuit having inverters IV1 and IV2 connected in series between an input signal line IN and an output signal line OUT. Each inverter IV1 and IV2 operates while connected to a power supply line TVDD and a ground line VSS.
  • the inverter IV1 inverts the logic of the input signal IN and outputs it as an output signal OUT0.
  • the inverter IV2 inverts the logic of the output signal OUT0 from the inverter IV1 and outputs it as an output signal OUT.
  • the power supply line TVD is an example of a first power supply line, and the power supply potential TVD is an example of a first potential.
  • the virtual power supply line VVDD is an example of a second power supply line, and the virtual power supply potential VVDD is an example of a second potential.
  • the ground line VSS is an example of a third power supply line, and the ground potential VSS is an example of a third potential.
  • the switch transistor SWT is a PMOS transistor with a source connected to the power line TVDD and a drain connected to the virtual power line VVDD, and operates by receiving the voltage of the output signal OUT0 from the control circuit CNTL as a gate potential. While the switch transistor SWT is on, the power line TVDD and the virtual power line VVDD are electrically connected, and the power potential TVDD is supplied to the standard cell SC via the virtual power line VVDD. While the switch transistor SWT is off, the electrical connection between the power line TVDD and the virtual power line VVDD is cut off, and the virtual power line VVDD is set to a floating state. Note that, instead of the output of the inverter IV1, the input IN of the inverter IV1 or the output OUT of the inverter IV2 may be connected to the gate of the switch transistor SWT. This is similar to other embodiments.
  • the control circuit CNTL may be arranged in a region separate from the region in which the power switch circuit PSW is arranged.
  • the output signal OUT may be supplied to an input terminal IN of another power switch circuit PSW.
  • the switch transistor SWT is an example of a first transistor formed above the substrate SUB and electrically provided between the power line TVDD and the virtual power line VVDD.
  • FIG. 4 shows an example of the positional relationship between the power supply line TVDD, virtual power supply line VVDD, ground line VSS, and via VIA1 arranged at a position overlapping the standard cell block SCB of FIG. 3 in a plan view on the back surface BS side of the semiconductor substrate SUB, and the power switch circuit PSW.
  • Each wire in the wiring layer BSM1 extends in the X direction
  • each wire in the wiring layer BSM2 extends in the Y direction, which is a second direction different from the X direction.
  • the X direction is an example of a first direction.
  • the symbol ROW in FIG. 4 indicates the width of the standard cell SC in the Y direction in the wiring layer BSM1.
  • the virtual power lines VVDD of the wiring layer BSM1 are arranged in the Y direction with a spacing of two ROWs between them. Between a pair of virtual power lines VVDD adjacent in the Y direction, a ground line VSS that extends in the X direction and is interrupted at multiple points along the way, and a power line TVDD that is arranged at the position where the ground line VSS is interrupted are arranged alternately along the X direction.
  • the power switch circuits PSW indicated by the thick dashed frame are arranged, for example, in a staggered pattern (zigzag).
  • Standard cells SC are arranged in areas where the power switch circuits PSW are not arranged.
  • the power switch circuits PSW are arranged between a pair of virtual power lines VVDD adjacent in the Y direction (a spacing ROW of two lines) so as to overlap with the power line TVDD extending in the X direction in a plan view.
  • the power supply lines TVD By distributing the power supply lines TVD to positions where the ground lines VSS are interrupted, it is possible to eliminate the need for a dedicated area for the power supply lines TVD with the width of the interval ROW. Furthermore, the power supply lines TVD can be arranged only at positions where the power switch circuits PSW are arranged. This allows the arrangement density of the virtual power supply lines VVDD and the ground lines VSS in the wiring layer BSM1 to be increased compared to the case where a dedicated area for the power supply lines TVD with the width of the interval ROW is provided, and the power supply capacity to the standard cells SC can be increased.
  • the power supply line TVD, virtual power supply line VVDD, and ground line VSS are repeatedly arranged in this order in the X direction.
  • the virtual power supply lines VVDD of the wiring layers BSM1 and BSM2 are connected to each other through vias VIA1 arranged at the intersections.
  • the power supply lines TVD of the wiring layers BSM1 and BSM2 are connected to each other through vias VIA1 arranged at the intersections.
  • the ground lines VSS of the wiring layers BSM1 and BSM2 are connected to each other through vias VIA1 arranged at the intersections.
  • the virtual power supply line VVDD may be omitted from the wiring layer BSM2.
  • the power supply lines TVDD and the ground lines VSS are alternately arranged along the X direction in the wiring layer BSM2.
  • the arrangement density of the power switch circuits PSW may be set lower than that shown in FIG. 4.
  • the cut interval of the ground lines VSS extending in the X direction is set wider than that shown in FIG. 4.
  • FIG. 5 shows an example of the layout of the power switch circuit PSW of FIGS. 3 and 4.
  • the symbol Mint indicates a wiring formed in the metal wiring layer Mint that is closest to the substrate SUB among multiple metal wiring layers.
  • the symbol LI indicates a local wiring formed in a wiring layer closer to the substrate SUB than the Mint layer.
  • the wiring LI can be directly connected to the source and drain of a transistor.
  • the symbol GT indicates the gate of a transistor.
  • the symbol VIA indicates a via that connects the Mint wiring and the local wiring LI, or a via that connects the Mint wiring and the gate wiring GT.
  • TR(PMOS) indicates the transistor region (source, drain, and channel) of a PMOS transistor.
  • TR(NMOS) indicates the transistor region (source, drain, and channel) of an NMOS transistor.
  • a finFET a fin is formed in the region TR.
  • a nanosheetFET a semiconductor layer is formed as the source and drain in the region TR, and a nanosheet, which is the channel, is formed between the source and drain.
  • the power switch circuit PSW has a switch transistor SWT and a control circuit CNTL (buffer circuit) arranged side by side in the X direction in a plan view.
  • the power switch circuit PSW is designed as one cell.
  • the switch transistor SWT is arranged in a position overlapping with the virtual power line VVDD and the power line TVDD of the wiring layer BSM1 in a plan view.
  • the source of the PMOS transistor that overlaps with the power line TVD of the wiring layer BSM1 in a planar view is directly connected to the TSV connected to the power line TVD of the wiring layer BSM1.
  • the TSV directly connected to the source of the PMOS transistor that overlaps with the power line TVD of the wiring layer BSM1 in a planar view is an example of a first via.
  • the source of the PMOS transistor that does not overlap with the power line TVD of the wiring layer BSM1 in a planar view is connected to the source of the PMOS transistor connected to the TSV of the power line TVD via the local wiring LI.
  • a direct connection means that the conductor included in the TSV is in contact with the source or drain of each transistor, and also includes, for example, when the TSV has multiple layers of conductors, a part of the multiple layers of conductors being in contact with the source or drain of the transistor.
  • the drain of the PMOS transistor that overlaps with the virtual power line VVDD of the wiring layer BSM1 in a planar view is directly connected to the virtual power line VVDD of the wiring layer BSM1 via a TSV.
  • the drain of the PMOS transistor that does not overlap with the virtual power line VVDD of the wiring layer BSM1 in a planar view is connected to the drain of the PMOS transistor connected to the TSV of the virtual power line VVDD via a local wiring LI.
  • the control circuit CNTL is placed in a position overlapping the virtual power supply line VVDD and ground line VSS of the wiring layer BSM1 in a planar view.
  • the source of the NMOS transistor of the control circuit CNTL is directly connected to the ground line VSS of the wiring layer BSM1 via a TSV.
  • the control circuit CNTL is not placed in a position overlapping with the power supply line TVDD of the wiring layer BSM1 in a planar view. For this reason, the TSV (TVDD) cannot be directly connected to the source of the PMOS transistor of the control circuit CNTL (inverters IV1, IV2).
  • the source of the PMOS transistor of the control circuit CNTL is electrically connected to the source of the PMOS transistor of the switch transistor SWT via the local wiring LI and the Mint wiring. This allows the source of the PMOS transistor of the control circuit CNTL to be electrically connected to the power supply line TVDD of the wiring layer BSM1.
  • the PMOS transistors of the inverters IV1 and IV2 are an example of a second transistor formed above the substrate SUB. Note that the source of the PMOS transistor of the control circuit CNTL may be electrically connected to the source of the PMOS transistor of the switch transistor SWT via a wiring layer above the Mint wiring.
  • the source of the PMOS transistor of the control circuit CNTL can be electrically connected to the power line TVDD of the wiring layer BSM1, regardless of the layout of the power line TVDD formed in the wiring layer BSM1 on the back surface BS side of the substrate SUB.
  • the degree of freedom in the layout of the power switch circuit PSW can be increased compared to when the local wiring LI and Mint wiring are not used to connect the source of the PMOS transistor to the power line TVDD.
  • the source of the PMOS transistor of the inverter IV arranged in the standard cell SC is directly connected to the virtual power line VVDD of the wiring layer BSM1 via a TSV.
  • the source of the NMOS transistor of the inverter IV arranged in the standard cell SC is directly connected to the ground line VSS of the wiring layer BSM1 via a TSV.
  • control circuit CNTL (inverters IV1, IV2) is included in the power switch circuit PSW, but may be arranged separately from the power switch circuit PSW. In this case, the power switch circuit PSW and the control circuit CNTL may be designed as separate cells. Also, multiple power switch circuits PSW may be controlled by one control circuit CNTL.
  • each of the power supply line TVD and ground line VSS in wiring layer BSM1 is connected to a corresponding power supply line TVD and ground line VSS in wiring layer BSM2 (not shown).
  • a virtual power supply line VVDD is arranged in wiring layer BSM2, it may be connected to the virtual power supply line VVDD in wiring layer BSM1.
  • FIG. 6 shows an example of a cross section along line X1-X2 in FIG. 5.
  • the ground line VSS formed in the wiring layer BSM1 on the back surface BS side is connected to the source S (N-type impurity region) of the NMOS transistor formed on the front surface FS via a TSV formed in the substrate SUB.
  • the power supply line TVDD formed in the wiring layer BSM1 on the back surface BS side is connected to the source S (P-type impurity region) of the PMOS transistor formed on the front surface FS via a TSV formed in the substrate SUB.
  • a channel C is arranged between a source S and a drain D.
  • a gate GT is arranged on the channel C via a gate insulating film (not shown).
  • An output signal OUT0 output from an inverter IV1 of the control circuit CNTL is supplied to a gate GT of a PMOS transistor of the power switch circuit PSW via a local wiring LI, a Mint wiring, and a local wiring LI.
  • two wiring layers BSM1 and BSM2 are arranged on the back surface BS side in FIG. 6, three or more wiring layers BSM may be arranged.
  • FIG. 7 shows another example of a cross section along line X1-X2 in FIG. 5.
  • FIG. 7 has the same cross-sectional structure as FIG. 6, except that the wiring layer BSM1 is formed below the substrate SUB on the back surface BS side of the substrate SUB.
  • the wiring layer BSM1 shown in FIG. 7 is different from the buried wiring BPR (FIG. 2) that is buried on the front surface FS side of the substrate SUB.
  • the wiring layer BSM1 may be formed inside the substrate SUB below, without being exposed on the back surface BS side of the substrate SUB.
  • FIG. 8 shows yet another example of a cross section along line X1-X2 in FIG. 5.
  • FIG. 8 has the same cross-sectional structure as FIG. 5, except that the transistor formed on the substrate SUB is a nanosheet FET.
  • the nanosheet FET has a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on the surface of the nanosheet NS.
  • a nanosheet FET may be disposed in place of the finFET shown in FIG. 7.
  • FIG. 9 shows a first modified layout of the power switch circuit PSW in FIG. 3.
  • FIG. 9 has the same configuration as FIG. 5, except that the layout of the control circuit CNTL differs from that in FIG. 5, and the size of the PMOS transistor of the switch transistor SWT is larger than that in FIG. 5.
  • the switch transistor SWT and the control circuit CNTL are arranged side by side in the X direction in a plan view.
  • the two inverters IV1 and IV2 of the control circuit CNTL are arranged along the Y direction at positions overlapping the power supply line TVD and ground line VSS of the wiring layer BSM1 in a planar view.
  • the PMOS transistors of the inverters IV1 and IV2 are arranged at positions overlapping the power supply line TVD of the wiring layer BSM1 in a planar view, so that the sources of the PMOS transistors can be directly connected to the power supply line TVD of the wiring layer BSM1 via the TSV.
  • the PMOS transistors of the switch transistor SWT are also arranged at positions that overlap the virtual power line VVDD of the wiring layer BSM1 in a planar view on both sides of the control circuit CNTL in the Y direction (hereinafter, additional PMOS transistors).
  • additional PMOS transistors The sources of the additional PMOS transistors cannot be directly connected to the power line TVDD of the wiring layer BSM1 via the TSV.
  • the source of the additional PMOS transistor is electrically connected to the source of the PMOS transistor of the switch transistor SWT, which is arranged at a position overlapping the power supply line TVDD of the wiring layer BSM1 in a planar view, via the local wiring LI and the Mint wiring. This allows the source of the additional PMOS transistor to be electrically connected to the power supply line TVDD of the wiring layer BSM1.
  • the source of the PMOS transistor of the switch transistor SWT can be electrically connected to the power line TVDD of the wiring layer BSM1, regardless of the layout of the power line TVDD formed in the wiring layer BSM1 on the back surface BS side of the substrate SUB.
  • the degree of freedom in the layout of the power switch circuit PSW can be increased.
  • the control circuit CNTL (inverters IV1, IV2) may be arranged separately from the power switch circuit PSW.
  • the power switch circuit PSW and the control circuit CNTL may be designed as separate cells.
  • multiple power switch circuits PSW may be controlled by one control circuit CNTL.
  • each of the virtual power line VVDD, power line TVDD, and ground line VSS of the wiring layer BSM1 is connected to a corresponding virtual power line VVDD, power line TVDD, and ground line VSS in the wiring layer BSM2 (not shown).
  • the virtual power line VVDD does not necessarily have to be arranged in the wiring layer BSM2.
  • FIG. 10 shows a second modified layout of the power switch circuit PSW of FIG. 3.
  • the switch transistor SWT and the control circuit CNTL are arranged side by side in the Y direction in a plan view.
  • the switch transistor SWT is arranged at a position overlapping the virtual power line VVDD and the power line TVDD of the wiring layer BSM1 in a plan view.
  • the control circuit CNTL is arranged at a position overlapping the virtual power line VVDD and the ground line VSS of the wiring layer BSM1 in a plan view.
  • the control circuit CNTL (inverters IV1, IV2) is not disposed in a position that overlaps with the power supply line TVDD of the wiring layer BSM1 in a plan view. Therefore, the source of the PMOS transistor of the control circuit CNTL is electrically connected to the source of the PMOS transistor of the switch transistor SWT via the local wiring LI. This allows the source of the PMOS transistor of the control circuit CNTL to be electrically connected to the power supply line TVDD of the wiring layer BSM1.
  • the control circuit CNTL (inverters IV1, IV2) may be arranged separately from the power switch circuit PSW.
  • the power switch circuit PSW and the control circuit CNTL may be designed as separate cells.
  • multiple power switch circuits PSW may be controlled by one control circuit CNTL.
  • FIG. 11 shows a third modified layout of the power switch circuit PSW in FIG. 3.
  • a control circuit CNTL is arranged between two switch transistors SWT in the X direction.
  • the output signal OUT0 output from the first-stage inverter IV1 of the control circuit CNTL is commonly supplied to the gates of the PMOS transistors of the two switch transistors SWT via the Mint wiring.
  • the two switch transistors SWT and the control circuit CNTL are arranged using a space ROW of two. Note that one or two of the two switch transistors SWT and the control circuit CNTL may be arranged at different positions in the Y direction. For example, each switch transistor SWT and control circuit CNTL is designed as a separate cell.
  • the layout of the elements of each switch transistor SWT is similar to the layout of the elements of the switch transistor SWT in FIG. 10.
  • the layout of the elements of the control circuit CNTL is similar to the layout of the elements of the control circuit CNTL in FIG. 10, except that the sources of the NMOS transistors of inverters IV1 and IV2 are common to each other.
  • the control circuit CNTL is not disposed in a position that overlaps with the power supply line TVDD of the wiring layer BSM1 in a plan view. Therefore, the source of the PMOS transistor of the control circuit CNTL is electrically connected to the source of the PMOS transistor of the switch transistor SWT via the Mint wiring and the local wiring LI. This allows the source of the PMOS transistor of the control circuit CNTL to be electrically connected to the power supply line TVDD of the wiring layer BSM1.
  • FIG. 12 shows a fourth modified example of the layout of the power switch circuit PSW in FIG. 3.
  • the switch transistor SWT and the control circuit CNTL are arranged side by side in the Y direction in a plan view.
  • the layout of the elements of the switch transistor SWT is similar to the layout of the elements of the switch transistor SWT in FIG. 10.
  • the layout of the elements of the control circuit CNTL is similar to the layout of the elements of the control circuit CNTL in FIG. 10.
  • the ground line VSS and the virtual power line VVDD of the wiring layer BSM1 are cut to provide free space, and two power lines TVDD are arranged along the Y direction in the provided free space. That is, the ground line VSS and the power line TVDD are arranged alternately along the X direction, and the virtual power line VVDD and the power line TVDD are arranged alternately along the X direction.
  • the source of the PMOS transistor of the control circuit CNTL (inverters IV1 and IV2) to be directly connected to the power supply line TVD of the wiring layer BSM1 via the TSV.
  • the two power supply lines TVD of the wiring layer BSM1 may be arranged together as a single power supply line TVD.
  • FIG. 13 shows a fifth modified layout of the power switch circuit PSW of FIG. 3.
  • the power switch circuit PSW shown in FIG. 13 is similar to the power switch circuit PSW of FIG. 5, except that an N-type well tap NWTP and a P-type well tap PWTP are arranged between the switch transistors SWT and the control circuit CNTL aligned in the X direction.
  • the well taps NWTP and PWTP are arranged side by side in the X direction.
  • the power switch circuit PSW has the same configuration as the power switch circuit PSW in FIG. 5, except that it has well taps NWTP and PWTP.
  • the well tap NWTP is an example of a first well tap
  • the well tap PWTP is an example of a second well tap.
  • the well taps NWTP and PWTP are arranged between the switch transistor SWT and the control circuit CNTL in the X direction, but the arrangement is not limited to this.
  • the well tap PWTP may be arranged in a position overlapping with a P-type well region on the opposite side to the P-type well region PW that overlaps with the control circuit CNTL in the X direction.
  • the well tap NWTP is disposed at a position overlapping the power supply line TVDD of the wiring layer BSM1 in a plan view.
  • the well tap NWTP is formed by an NMOS transistor whose source and drain are directly connected to the power supply line TVDD of the wiring layer BSM1 via a TSV. This allows the power supply potential TVDD to be supplied to the N-type well region NW, which is the substrate region (shaded region) of the PMOS transistor.
  • the TSV directly connected to the source and drain of the well tap NWTP is an example of a second via.
  • the well tap PWTP is disposed at a position overlapping with the ground line VSS of the wiring layer BSM1 in a plan view.
  • the well tap PWTP is formed by a PMOS transistor whose source and drain are directly connected to the ground line VSS of the wiring layer BSM1 via a TSV. This allows the ground potential VSS to be supplied to the P-type well region PW, which is the substrate region (region other than the shaded region) of the NMOS transistor.
  • the NMOS transistor is an example of a third transistor of the opposite conductivity type to the PMOS transistor.
  • the TSV directly connected to the source and drain of the well tap PWTP is an example of a third via.
  • the well region NW is an N-type impurity region formed in the substrate SUB, and is electrically connected to the channel of the FinFET (PMOS).
  • the well region PW is a P-type substrate SUB or a P-type impurity region formed in the substrate SUB, and is electrically connected to the channel of the FinFET (NMOS).
  • the source of the PMOS transistor can be electrically connected to the power line TVDD of the wiring layer BSM1.
  • the degree of freedom in the layout of the power switch circuit PSW can be increased compared to a case in which the local wiring LI and Mint wiring are not used to connect the source of the PMOS transistor to the power line TVDD.
  • the power supply lines TVD By distributing the power supply lines TVD to positions where the ground lines VSS are interrupted, it is possible to eliminate the need for a dedicated area for the power supply lines TVD with the width of the interval ROW. Furthermore, the power supply lines TVD can be arranged only at positions where the power switch circuits PSW are arranged. This allows the arrangement density of the virtual power supply lines VVDD and the ground lines VSS in the wiring layer BSM1 to be increased compared to the case where a dedicated area for the power supply lines TVD with the width of the interval ROW is provided, and the power supply capacity to the standard cells SC can be increased.
  • the power supply potential TVDD can be supplied to the well region NW from the back surface BS side of the substrate SUB.
  • the ground potential VSS can be supplied to the well region PW from the back surface BS side of the substrate SUB.
  • FIG. 14 shows an example of the layout of power lines arranged on the back side of the semiconductor substrate in the semiconductor device of the second embodiment. Elements similar to those in FIG. 4 are given the same reference numerals and detailed descriptions are omitted.
  • the ground lines VSS of the wiring layer BSM1 are formed to extend uninterrupted in the X direction. Between a pair of ground lines VSS adjacent to each other in the Y direction, virtual power lines VVDD extending in the X direction and interrupted at multiple points along the way, and power lines TVDD arranged at positions where the virtual power lines VVDD are interrupted are arranged alternately along the X direction.
  • the power switch circuits PSW indicated by the thick dashed frame are arranged alternately (staggered). The rest of the configuration in FIG. 14 is the same as in FIG. 4.
  • the power supply lines TVD By distributing the power supply lines TVD to positions where the virtual power supply lines VVDD are interrupted, it is possible to eliminate the need for a dedicated area for the power supply lines TVD having the width of the interval ROW, as in FIG. 4. Also, the power supply lines TVD can be arranged only at positions where the power switch circuits PSW are arranged. This allows the arrangement density of the virtual power supply lines VVDD and the ground lines VSS in the wiring layer BSM1 to be increased compared to the case where a dedicated area for the power supply lines TVD having the width of the interval ROW is provided, and the power supply capacity to the standard cells SC can be increased.
  • FIG. 15 shows an example of the layout of the power switch circuit PSW in FIG. 14.
  • the same elements as those in FIG. 5 are given the same reference numerals, and detailed descriptions are omitted.
  • the switch transistor SWT and the control circuit CNTL are arranged side by side in the X direction in a plan view.
  • the PMOS transistor of the switch transistor SWT is arranged at a position overlapping the virtual power line VVDD and the power line TVDD of the wiring layer BSM1 in a planar view.
  • the control circuit CNTL is arranged at a position overlapping the power line TVDD and the ground line VSS of the wiring layer BSM1 in a planar view.
  • the layout of the inverter IV arranged in the standard cell SC is similar to the layout of the inverter IV arranged in the standard cell SC in Figure 5.
  • the source of the PMOS transistor arranged at a position overlapping the power supply line TVDD of the wiring layer BSM1 is directly connected to the power supply line TVDD of the wiring layer BSM1 via the TSV.
  • the source of the PMOS transistor arranged at a position overlapping the virtual power supply line VVDD of the wiring layer BSM1 in a planar view is electrically connected to the source of the PMOS transistor connected to the TSV via the local wiring LI and the Mint wiring.
  • a dummy transistor DMY (NMOS) is arranged in the area of the switch transistor SWT overlapping with the ground line VSS of the wiring layer BSM1 in a planar view.
  • the sources of the PMOS transistors of the inverters IV1 and IV2 are directly connected to the power supply line TVDD of the wiring layer BSM1 via TSV.
  • the sources of the NMOS transistors of the inverters IV1 and IV2 are directly connected to the ground line VSS of the wiring layer BSM1 via TSV.
  • the switch transistor SWT and the control circuit CNTL are arranged side by side in the X direction in a plan view, but the switch transistor SWT and the control circuit CNTL may be arranged side by side in the Y direction in a plan view, as shown in FIG. 10 or FIG. 12.
  • FIG. 16 shows a modified layout of the power switch circuit PSW in FIG. 14.
  • the same elements as in FIG. 13 are given the same reference numerals and detailed description is omitted.
  • the power switch circuit PSW shown in FIG. 16 is similar to the power switch circuit PSW in FIG. 15, except that an N-type well tap NWTP and a P-type well tap PWTP are arranged between the switch transistor SWT and the control circuit CNTL arranged in the X direction.
  • the well taps NWTP and PWTP are arranged side by side in the Y direction.
  • the well tap NWTP is disposed at a position overlapping the power supply line TVDD of the wiring layer BSM1 in a plan view.
  • the well tap NWTP is formed by an NMOS transistor whose source and drain are directly connected to the power supply line TVDD of the wiring layer BSM1 via a TSV. This allows the power supply potential TVDD to be supplied to the N-type well region NW, which is the substrate region (shaded region) of the PMOS transistor.
  • the well tap PWTP is disposed at a position overlapping the ground line VSS of the wiring layer BSM1 in a plan view.
  • the well tap PWTP is formed by a PMOS transistor whose source and drain are directly connected to the ground line VSS of the wiring layer BSM1 via a TSV. This allows the ground potential VSS to be supplied to the P-type well region PW, which is the substrate region (area other than the shaded area) of the NMOS transistor.
  • the second embodiment can achieve the same effects as the first embodiment.
  • the sources of the PMOS transistors can be electrically connected to the power supply lines TVDD of the wiring layer BSM1, and the degree of freedom in the layout of the power switch circuit PSW can be increased.
  • the arrangement density of the virtual power supply lines VVDD and the ground lines VSS in the wiring layer BSM1 can be increased, and the power supply capacity to the standard cells SC can be increased.

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  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/JP2023/014837 2023-04-12 2023-04-12 半導体装置 Ceased WO2024214205A1 (ja)

Priority Applications (4)

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CN202380096942.1A CN120917899A (zh) 2023-04-12 2023-04-12 半导体装置
PCT/JP2023/014837 WO2024214205A1 (ja) 2023-04-12 2023-04-12 半導体装置
JP2025513561A JPWO2024214205A1 (https=) 2023-04-12 2023-04-12
US19/351,386 US20260033000A1 (en) 2023-04-12 2025-10-07 Semiconductor device

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11102910A (ja) * 1997-09-29 1999-04-13 Hitachi Ltd 半導体集積回路
WO2020065916A1 (ja) * 2018-09-28 2020-04-02 株式会社ソシオネクスト 半導体装置
WO2020105713A1 (ja) * 2018-11-21 2020-05-28 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子
US20210082815A1 (en) * 2019-09-17 2021-03-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including back side power supply circuit
WO2021079511A1 (ja) * 2019-10-25 2021-04-29 株式会社ソシオネクスト 半導体装置
WO2021111604A1 (ja) * 2019-12-05 2021-06-10 株式会社ソシオネクスト 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11102910A (ja) * 1997-09-29 1999-04-13 Hitachi Ltd 半導体集積回路
WO2020065916A1 (ja) * 2018-09-28 2020-04-02 株式会社ソシオネクスト 半導体装置
WO2020105713A1 (ja) * 2018-11-21 2020-05-28 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子
US20210082815A1 (en) * 2019-09-17 2021-03-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including back side power supply circuit
WO2021079511A1 (ja) * 2019-10-25 2021-04-29 株式会社ソシオネクスト 半導体装置
WO2021111604A1 (ja) * 2019-12-05 2021-06-10 株式会社ソシオネクスト 半導体装置

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