Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
  • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
  • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Definitions

• This disclosure relates to a circuit board and a display device including the same.
• TFTs thin film transistors
• a base coat film is provided on the substrate.
• a first TFT is formed on the base coat film, and conductive parts such as wiring, electrodes, and a semiconductor layer are provided. These conductive parts are covered by an insulating film.
• a second TFT is formed on the insulating film. The semiconductor layer of the second TFT is connected to the conductive part via a contact hole formed in the insulating film.
• the purpose of this disclosure is to prevent the characteristics of a semiconductor layer made of an oxide semiconductor from changing due to the intrusion of moisture.
• the technology disclosed herein is directed to a circuit board.
• the circuit board according to the technology disclosed herein comprises a substrate, a base coat film provided on the substrate, a conductive portion provided on the base coat film, an insulating film provided so as to cover the conductive portion, and a semiconductor layer made of an oxide semiconductor provided on the insulating film.
• a contact hole penetrating the conductor portion is formed in the interlayer insulating film.
• the semiconductor layer is electrically connected to the conductive portion via the contact hole.
• the circuit board further comprises an island-shaped intermediate layer interposed between the substrate and the conductive portion in a region corresponding to the contact hole.
• the technology disclosed herein can prevent the characteristics of a semiconductor layer made of an oxide semiconductor from changing due to the intrusion of moisture.
• FIG. 1 is a plan view illustrating a schematic configuration of an organic EL display device according to the first embodiment.
• FIG. 2 is a cross-sectional view of the organic EL display device taken along line II-II in FIG.
• FIG. 3 is a plan view illustrating pixels and various wirings that configure the display area of the organic EL display device according to the first embodiment.
• FIG. 4 is a cross-sectional view of the organic EL display device taken along line IV-IV in FIG.
• FIG. 5 is a plan view illustrating a main part of the organic EL display device according to the first embodiment.
• FIG. 6 is a cross-sectional view of the organic EL display device taken along line VI-VI in FIG. FIG.
• FIG. 7 is a plan view illustrating a schematic configuration of an organic EL display device according to the second embodiment.
• 8 is a cross-sectional view illustrating a portion of the peripheral region corresponding to FIG. 6 (upper diagram) and a portion of the inner region corresponding to FIG. 6 (lower diagram) in the display region of the organic EL display device according to the second embodiment.
• FIG. 9 is a plan view illustrating a schematic configuration of an organic EL display device according to the third embodiment.
• 10 is a cross-sectional view illustrating a portion of the peripheral region corresponding to FIG. 6 (upper figure), a portion of the intermediate region corresponding to FIG. 6 (middle figure), and a portion of the inner region corresponding to FIG.
• FIG. 11 is a cross-sectional view of a portion of an organic EL display device according to a modified example, which corresponds to FIG.
• FIG. 12 is a cross-sectional view of a portion of an organic EL display device according to a modified example, which corresponds to FIG.
• FIG. 13 is a cross-sectional view of a portion of an organic EL display device according to a modified example, which corresponds to FIG.
• FIG. 14 is a cross-sectional view of a portion of an organic EL display device according to another embodiment, which corresponds to FIG.
• FIG. 15 is a cross-sectional view of a portion of the organic EL display device of the comparative example, which corresponds to FIG.
• FIG. 16 is a cross-sectional view of a portion of an organic EL display device of a comparative example, which corresponds to FIG.
• the "first direction” refers to the horizontal direction of the screen when the display device is oriented in a specified state of use.
• the “second direction” refers to the direction perpendicular to the first direction and to the vertical direction of the screen when the display device is oriented in a specified state of use.
• a row of components such as subpixels refers to a horizontal arrangement of multiple components that form a line in the first direction.
• a column of components such as subpixels refers to a vertical arrangement of multiple components that form a line in the second direction.
• a component such as a film, layer, or element
• another component such as another film, layer, or element
• it does not only mean that the other component exists directly on top of the component, but also includes cases where a component such as a film, layer, or element is interposed between the two components.
• a description that a certain component is in the same layer as another component means that the certain component is formed in the same process as the other component.
• a description that a certain component is a lower layer of another component means that the certain component is deposited in an earlier process than the other component or is formed from a film deposited in an earlier process.
• a description that a certain component is a higher layer of another component means that the certain component is deposited in a later process than the other component or is formed from a film deposited in a later process.
• the organic EL display device 1 of the first embodiment is used as a display for a mobile device such as a multi-function phone called a smartphone, a tablet terminal, etc.
• the organic EL display device 1 may also be used as a display for various other devices such as a personal computer (PC) and a television device.
• PC personal computer
• an organic EL display device 1 is combined with a camera 3 to form a display device with an in-camera that can capture an image of the front side of the screen with the camera 3.
• the organic EL display device 1 employs an active matrix driving method and is configured to perform full color display.
• the organic EL display device 1 has a display area DA, a frame area FA, and a non-display area NA.
• the display area DA is an area for displaying an image and constitutes a screen.
• the display area DA is provided in a rectangular shape, for example.
• the display area DA may be an approximately rectangular shape with at least one side in an arc shape, with at least one corner in an arc shape, with at least one side cut out, or may be any other shape.
• the display area DA is composed of a plurality of pixels PX.
• the plurality of pixels PX are arranged in a matrix.
• Each pixel PX is composed of three sub-pixels SP.
• the three sub-pixels SP are a sub-pixel SPr that emits red light, a sub-pixel SPg that emits green light, and a sub-pixel SPb that emits blue light. These three sub-pixels SPr, SPg, and SPb are arranged, for example, in a striped pattern.
• a plurality of organic EL elements 65 and a plurality of pixel circuits PC are provided in the display area DA.
• the plurality of organic EL elements 65 are provided corresponding to a plurality of sub-pixels SP.
• Each sub-pixel SP is constituted by an organic EL element 65.
• the pixel circuit PC is a circuit for each sub-pixel, and controls the light emission of the organic EL element 65 that constitutes the corresponding sub-pixel SP.
• the frame area FA is an area that constitutes the non-display portion outside the screen.
• the frame area FA is provided around the display area DA in, for example, a rectangular frame shape.
• the frame area FA may have a frame shape other than a rectangle.
• the frame area FA includes a terminal portion TP and a bent portion BP.
• the terminal part TP is a part for connecting to an external circuit such as a display control circuit (source driver).
• the terminal part TP is provided at a position near the outer edge of a part constituting one side extending in the first direction Dx of the frame area FA, so as to extend along that side.
• the terminal part TP has a plurality of terminals.
• a wiring board CB such as an FPC (Flexible Printed Circuit) is connected to the terminal part TP.
• the bent portion BP is provided between the terminal portion TP and the display area DA, and extends horizontally across the entire frame area FA in the first direction.
• the frame area FA is bent, for example, by about 180° at the bent portion BP to form a U-shape (shown by the two-dot chain line in FIG. 2).
• the terminal portion TP is positioned on the rear side of the organic EL display device 1.
• a driving circuit DC is provided in the frame area FA.
• the driving circuit DC is disposed in a portion of the frame area FA that constitutes an edge (the left and right edges in FIG. 1) adjacent to the edge on which the terminal portion TP is provided.
• the driving circuit DC is monolithically formed as part of the TFT layer 20, which will be described later.
• the driving circuit DC includes a gate driver and an emission driver.
• first frame line 40a and a second frame line 40b are provided in the frame area FA.
• the first frame line 40a and the second frame line 40b are both power supply trunk lines that are formed to surround the display area DA and extend to the terminal portion TP.
• a high-level power supply voltage (ELVDD) is supplied to the first frame line 40a via the wiring board CB.
• a low-level power supply voltage (ELVSS) is supplied to the second frame line 40b via the wiring board CB.
• the non-display area NA is an area that constitutes the non-display portion within the screen.
• the non-display area NA is provided inside the display area DA, for example in the shape of a circular island.
• the non-display area NA may be provided contiguous with the frame area FA.
• the non-display area NA may also be a shape other than circular.
• Through holes TH are formed in the non-display area NA.
• the through holes TH penetrate in the thickness direction of the circuit board 5 described below, and transmit light from the front side to the back side of the organic EL display device 1.
• the light that passes through the through hole TH is used for image capture by the camera 3.
• the camera 3 is disposed at a position corresponding to the through hole TH on the rear side of the organic EL display device 1.
• the camera 3 is an example of an electronic component that utilizes light.
• the camera 3 has an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor).
• the camera 3 is installed inside a housing (not shown) that houses the organic EL display device 1.
• the organic EL display device 1 includes a circuit board 5, a light emitting element layer 60, and a sealing film 80.
• the circuit board 5 includes a substrate layer 10 and a TFT layer (thin film transistor layer) 20.
• the substrate layer 10 is an example of a substrate that forms the base of the organic EL display device 1.
• the substrate layer 10 in this example is a substrate made of flexible resin.
• the substrate layer 10 is formed of an organic resin material such as polyimide resin, polyamide resin, or epoxy resin.
• the substrate layer 10 may have a configuration in which an organic insulating layer made of the organic resin material as described above and an inorganic insulating layer such as silicon oxide (SiO 2 ) are laminated.
• a protective film 11 having optical transparency (meaning transparency to visible light in this example) is attached to the back surface of the substrate layer 10.
• the TFT layer 20 is provided on the substrate layer 10.
• the TFT layer 20 includes a base coat film 21, various wirings 40, and a plurality of pixel circuits PC shown in Figures 3 and 4.
• the drive circuit DC, the various wirings 40, and the pixel circuits PC are provided on the base coat film 21.
• the base coat film 21 is provided on the substrate layer 10 and spreads over substantially the entire surface of the substrate layer 10.
• the base coat film 21 is formed by laminating a plurality of inorganic insulating films.
• the base coat film 21 in this example has a three-layer structure. Specifically, the base coat film 21 is formed by stacking a first inorganic insulating film 21a, a second inorganic insulating film 21b, and a third inorganic insulating film 21c in this order.
• the first inorganic insulating film 21a and the third inorganic insulating film 21c are each made of, for example, silicon oxide (SiO 2 ).
• the second inorganic insulating film 21b is made of, for example, silicon nitride (SiN). In this case, the thickness of the second inorganic insulating film 21b may be thinner than the thicknesses of the first inorganic insulating film 21a and the third inorganic insulating film 21c.
• the various wirings 40 include the first frame line 40a and the second frame line 40b described above.
• the various wirings 40 include a plurality of gate lines 40g, a plurality of light emission control lines 40e, a plurality of initialization lines 40i, a plurality of power supply lines 40p, and a plurality of source lines 40s. All of these gate lines 40g, light emission control lines 40e, initialization lines 40i, power supply lines 40p, and source lines 40s are provided in the display area DA.
• Each of the multiple gate lines 40g is a wiring that transmits a gate signal to the pixel circuit PC.
• the multiple gate lines 40g are arranged at intervals in the second direction Dy and extend parallel to each other in the first direction Dx.
• the gate lines 40g include a first gate line 40ga and a second gate line 40gb.
• the first gate line 40ga is a gate line 40g used to control the P-channel TFT 50.
• the second gate line 40gb is a gate line 40g used to control the N-channel TFT 50.
• the first gate line 40ga and the second gate line 40gb are provided for each row of sub-pixels SP. Each first gate line 40ga and each second gate line 40gb is drawn out to the frame area FA and connected to a gate driver of the drive circuit DC.
• Each of the multiple light emission control lines 40e is a wiring that transmits an emission signal to the pixel circuit PC.
• the multiple light emission control lines 40e are arranged at intervals in the second direction Dy and extend parallel to each other in the first direction Dx.
• the light emission control lines 40e are provided for each row of sub-pixels SP.
• Each light emission control line 40e is drawn out to the frame area FA and connected to an emission driver of the drive circuit DC.
• the multiple initialization lines 40i are wiring that apply an initialization voltage to the pixel circuits PC.
• the multiple initialization lines 40i are arranged at intervals in the second direction Dy and extend parallel to each other in the first direction Dx.
• An initialization line 40i is provided for each row of sub-pixels SP.
• Each initialization line 40i is drawn out to the frame area FA and connected to the drive circuit DC or the second frame line 40b.
• Each of the multiple power supply lines 40p is a wiring that applies a predetermined high-level power supply voltage (ELVDD) to the pixel circuit PC.
• the multiple power supply lines 40p are arranged at intervals in the first direction Dx and extend parallel to each other in the second direction Dy.
• a power supply line 40p is provided for each column of sub-pixels SP. Each power supply line 40p is drawn out to the frame area FA and connected to the first frame line 40a.
• Each of the multiple source lines 40s is a wiring that transmits a source signal to the pixel circuit PC.
• the multiple source lines 40s are arranged at intervals in the first direction Dx and extend parallel to each other in the second direction Dy.
• a source line 40s is provided for each column of sub-pixels SP.
• Each source line 40s is drawn out to a terminal portion TP and connected to a display control circuit (source driver) via a wiring board CB.
• the first gate line 40ga, the light emission control line 40e, and the initialization line 40i are formed in the same layer and made of the same material as the first gate electrode 24, the first capacitance electrode 25, and the relay line 40r described below.
• the second gate line 40gb is formed in the same layer and made of the same material as the second gate electrode described below.
• the power supply line 40p and the source line 40s are formed in the same layer and made of the same material as the first terminal electrode 37, the second terminal electrode 38, and the first to fourth connection lines 40ca, 40cb, 40cc, and 40cd described below.
• Each pixel circuit PC is connected to a first gate line 40ga, a second gate line 40gb, an initialization line 40i, a light emission control line 40e, and a power supply line 40p.
• Each pixel circuit PC operates based on the signals and voltages supplied by these various wirings 40, and in each frame, after resetting the charge accumulated in the pixel electrode 61, supplies a drive current corresponding to the source signal to the organic EL element 65.
• the pixel circuit PC includes a plurality of TFTs 50 and a capacitor 55.
• the plurality of TFTs 50 constituting the pixel circuit PC include a first TFT 50A and a second TFT 50B.
• the first TFT 50A and the second TFT 50B are provided in correspondence with a plurality of sub-pixels SP together with the capacitor 55, and constitute a pixel circuit PC for each sub-pixel SP.
• the pixel circuit PC includes a plurality of first TFTs 50A and a plurality of second TFTs 50B.
• the first TFT 50A is configured as a top-gate type with a top-contact structure.
• the first TFT 50A has a first semiconductor layer 22, a first gate insulating film 23, a first gate electrode 24, an interlayer insulating film 35, a first terminal electrode 37, and a second terminal electrode 38.
• the first semiconductor layer 22 is provided in an island shape on the base coat film 21, and is individually separated for each first TFT 50A.
• the first semiconductor layer 22 may be provided in a continuous manner for a plurality of first TFTs 50A.
• the first semiconductor layer 22 includes a channel region 22a and a pair of conductor regions 22b.
• the channel region 22a is provided between the pair of conductor regions 22b.
• the pair of conductor regions 22b are provided spaced apart from each other with the channel region 22a in between.
• the conductor regions 22b, which are part of the first semiconductor layer 22, are an example of a conductive portion.
• the first gate insulating film 23 covers the multiple first semiconductor layers 22 and is provided in a continuous manner for the multiple first TFTs 50A.
• the first gate insulating film 23 is provided in an island shape on each first semiconductor layer 22 and may be individually separated for each first TFT 50A.
• the first gate electrode 24 is provided on the first gate insulating film 23. The first gate electrode 24 overlaps with the channel region 22a of the first semiconductor layer 22 via the first gate insulating film 23.
• the interlayer insulating film 35 is formed by stacking a first interlayer insulating film 26 and a second interlayer insulating film 34 in this order on the first gate insulating film 23.
• the interlayer insulating film 35 is provided so as to cover the multiple first gate electrodes 24.
• a first contact hole Ha is formed in the interlayer insulating film 35.
• the first contact hole Ha penetrates to the first gate electrode 24.
• a first connection line 40ca is connected to the first gate electrode 24 via the first contact hole Ha.
• a pair of second contact holes Hb are formed in the first gate insulating film 23 and the interlayer insulating film 35 for each first TFT 50A.
• the first gate insulating film 23 and the first interlayer insulating film 26 constitute a stacked insulating film 36 that is provided to cover the first semiconductor layer 22.
• the stacked insulating film 36 is an example of an insulating film.
• Several second contact holes Hb are formed in the stacked insulating film 36. The pair of second contact holes Hb penetrate different conductor regions 22b of the corresponding first semiconductor layer 22.
• the first terminal electrode 37 and the second terminal electrode 38 are provided at positions spaced apart from each other.
• the first terminal electrode 37 and the second terminal electrode 38 are provided on the first interlayer insulating film 26 or the second interlayer insulating film 34, respectively.
• the first terminal electrode 37 and the second terminal electrode 38 are connected to the conductor region 22b of the first semiconductor layer 22 via different second contact holes Hb.
• the second TFT 50B is configured as a top-gate type with a bottom-contact structure.
• the second TFT 50B has a third terminal electrode 28, a fourth terminal electrode 29, a second semiconductor layer 31, a second gate insulating film 32, and a second gate electrode 33.
• the second semiconductor layer 31 is an example of a semiconductor layer.
• the third terminal electrode 28 and the fourth terminal electrode 29 are provided at positions spaced apart from each other on the first interlayer insulating film 26.
• a third contact hole Hc is formed in the second interlayer insulating film 34 corresponding to one of the second TFTs 50B. The third contact hole Hc penetrates to the third terminal electrode 28 of a specific second TFT 50B.
• the second connection line 40cb provided on the second interlayer insulating film 34 is connected to the third terminal electrode 28 of a given second TFT 50B through a third contact hole Hc.
• the third terminal electrode 28 is formed integrally with the second terminal electrode 38 of a given first TFT 50A, and is connected to the conductor region 22b (connection portion 22c) of the first semiconductor layer 22 through a second contact hole Hb.
• a fourth contact hole Hd is formed in the first interlayer insulating film 26, a fifth contact hole He is formed in the interlayer insulating film 35, and a relay line 40r is formed on the first gate insulating film 23, corresponding to one of the second TFTs 50B.
• the fourth contact hole Hd and the fifth contact hole He penetrate different parts of the relay line 40r.
• the fourth terminal electrode 29 of a given second TFT 50B is connected to the relay line 40r via the fourth contact hole Hd.
• the third connection line 40cc provided on the second interlayer insulating film 34 is connected to the relay line 40r via the fifth contact hole He.
• the third terminal electrode 28 and the fourth terminal electrode 29 of one second TFT 50B may be formed in a continuous manner with the third terminal electrode 28 or the fourth terminal electrode 29 of the other second TFT 50B.
• the second semiconductor layer 31 is provided in an island shape on the first interlayer insulating film 26, and is individually separated for each second TFT 50B.
• the second semiconductor layer 31 may be provided in a continuous manner for a plurality of second TFTs 50B.
• the second semiconductor layer 31 includes a channel region 31a and a pair of conductor regions 31b.
• the channel region 31a is provided between the pair of conductor regions 31b.
• the pair of conductor regions 31b are provided spaced apart from each other with the channel region 31a in between.
• One conductor region 31b in the second semiconductor layer 31 partially overlaps the third terminal electrode 28, and the other conductor region 31b partially overlaps each of the fourth terminal electrodes 29.
• the second semiconductor layer 31 is connected to the conductor region 22b of the first semiconductor layer 22 via the second contact hole Hb (contact hole CH).
• the second semiconductor layer 31 is also connected to the relay line 40r via the fourth contact hole Hd, and to the third connection line 40cc via the relay line 40r and the fifth contact hole He.
• the second gate insulating film 32 is provided in an island shape on the second semiconductor layer 31, and is individually separated for each second TFT 50B.
• the second gate insulating film 32 may cover multiple second semiconductor layers 31 and be provided in a continuous manner for multiple second TFTs 50B.
• the second gate electrode 33 is provided on the second gate insulating film 32.
• the second gate electrode 33 overlaps with the channel region 31a of the second semiconductor layer 31 via the second gate insulating film 32.
• a sixth contact hole Hf is formed in the second interlayer insulating film 34 corresponding to one of the second TFTs 50B.
• the sixth contact hole Hf penetrates the second gate electrode 33.
• the fourth connection line 40cd is connected to the second gate electrode 33 via the sixth contact hole Hf.
• the capacitor 55 includes a first capacitance electrode 25, a second capacitance electrode 30, and a first interlayer insulating film 26.
• the first capacitance electrode 25 is provided on the first gate insulating film 23.
• the second capacitance electrode 30 is provided on the first interlayer insulating film 26.
• the first capacitance electrode 25 and the second capacitance electrode 30 overlap each other with the first interlayer insulating film 26 interposed therebetween.
• the first gate insulating film 23, the first interlayer insulating film 26, the second gate insulating film 32, and the second interlayer insulating film 34 are made of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. These various inorganic insulating films may be composed of a single layer film or a laminated film.
• the various wirings and electrodes described above are made of metal materials such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu). These various wirings and electrodes may be made of a single layer film or a laminated film.
• the first semiconductor layer 22 is made of polysilicon.
• the polysilicon constituting the first semiconductor layer 22 is, for example, low temperature polysilicon (LTPS: Low Temperature Polycrystalline Silicon).
• the second semiconductor layer 31 is made of an oxide semiconductor.
• the oxide semiconductor constituting the second semiconductor layer 31 is, for example, an In-Ga-Zn-O based semiconductor.
• the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not limited.
• the In-Ga-Zn-O semiconductor may be amorphous or crystalline.
• the second semiconductor layer may contain other oxide semiconductors in addition to or instead of the In-Ga-Zn-O semiconductor.
• oxide semiconductors may include, for example, In-Sn-Zn-O based semiconductors (e.g., In 2 O 3 -SnO 2 -ZnO; InSnZnO), where the In-Sn-Zn-O based semiconductor is a ternary oxide of In (indium), Sn (tin) and Zn (zinc).
• In-Sn-Zn-O based semiconductors e.g., In 2 O 3 -SnO 2 -ZnO; InSnZnO
• the In-Sn-Zn-O based semiconductor is a ternary oxide of In (indium), Sn (tin) and Zn (zinc).
• oxide semiconductors may include In-Al-Zn-O based semiconductors, In-Al-Sn-O based semiconductors, Zn-O based semiconductors, In-Zn-O based semiconductors, Zn-Ti-O based semiconductors, Cd-Ge-O based semiconductors, Cd-Pb-O based semiconductors, CdO (cadmium oxide), Mg-Zn-O based semiconductors, and In-Ga-Sn-O based semiconductors.
• oxide semiconductors may include In-Ga-O based semiconductors, Zr-In-Zn-O based semiconductors, Hf-In-Zn-O based semiconductors, Al-Ga-Zn-O based semiconductors, InGaO 3 (ZnO) 5 , magnesium zinc oxide (Mg x Zn 1-x O), cadmium zinc oxide (Cd x Zn 1-x O), and the like.
• the planarization film 58 is provided on the second interlayer insulating film 34 so as to cover the various wirings 40, the multiple TFTs 50, and the multiple capacitors 55 in the display area DA.
• the planarization film 58 extends across the entire display area DA.
• the surface of the TFT layer 20 is planarized by the planarization film 58.
• a seventh contact hole Hg is formed in the planarization film 58 for each subpixel SP.
• the seventh contact hole Hg penetrates to the second connection line 40cb.
• the planarization film 58 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (Spin On Glass) material.
• the first to seventh contact holes Ha, Hb, Hc, Hd, He, Hf, and Hg are provided corresponding to the multiple subpixels SP (all subpixels SP) that make up the display area DA.
• the second contact hole Hb that connects the third terminal electrode 28 to the first semiconductor layer 22 is particularly related to the technology disclosed herein, and therefore will be referred to simply as the "contact hole CH" for convenience.
• the light emitting element layer 60 is provided on the TFT layer 20.
• the light emitting element layer 60 includes a plurality of organic EL elements (organic electroluminescence elements) 65 and an edge cover 66.
• the organic EL elements 65 are an example of a light emitting element.
• the organic EL elements 65 are configured as a top emission type. Light emitted by the organic EL elements 65 is extracted to the sealing film 80 side.
• the multiple organic EL elements 65 are provided corresponding to each of the multiple sub-pixels SP. Each organic EL element 65 constitutes a sub-pixel SP. The light emission of each organic EL element 65 is controlled by the operation of the corresponding pixel circuit PC. Each organic EL element 65 has a pixel electrode 61, an organic EL layer 62, and a common electrode 63.
• the pixel electrodes 61 are provided on the planarization film 58.
• the pixel electrodes 61 are arranged in a matrix corresponding to each of the multiple sub-pixels.
• Each pixel electrode 61 is connected to the second connection line 40cb via a seventh contact hole Hg.
• the pixel electrode 61 functions as an anode and injects holes into the organic EL layer 62. It is preferable to use a conductive material with a large work function for the pixel electrodes 61.
• the material of the pixel electrode 61 may be, for example, a metal such as silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), indium (In), or tin (Sn).
• the material of the pixel electrode 61 may be a metal compound or an alloy.
• the material of the pixel electrode 61 may be a conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).
• the pixel electrode 61 may be formed of a single layer film or a laminated film.
• the edge cover 66 is provided on the planarization film 58.
• the edge cover 66 is located on top of the pixel electrodes 61.
• the edge cover 66 is formed in a lattice shape to separate the multiple pixel electrodes 61. Specifically, the edge cover 66 extends between adjacent pixel electrodes 61 and around the periphery of the display area DA, covering the outer edge (peripheral end portion) of each pixel electrode 61.
• the edge cover 66 has a number of openings 67 corresponding to the sub-pixels SP. Each opening 67 partially exposes the pixel electrode 61 from the edge cover 66.
• the edge cover 66 is made of a material similar to that of the planarization film 58, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG material.
• the organic EL layer 62 is provided on each pixel electrode 61 within the opening 67 of the edge cover 66.
• the organic EL layer 62 has a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer.
• the hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer are stacked in this order on the pixel electrode 61, and are made of known compounds suitable for their respective functions.
• the organic EL layer 62 emits light when a current is applied between the pixel electrode 61 and the common electrode 63.
• the common electrode 63 is provided as a continuous common film spanning multiple subpixels SP, spreading across the entire display area DA.
• the common electrode 63 covers the edge cover 66 and each organic EL layer 62, and overlaps each pixel electrode 61 via the organic EL layer 62.
• the common electrode 63 also spreads into the frame area FA, and is connected to the second frame line 40b.
• the common electrode 63 functions as a cathode, and injects electrons into the organic EL layer 62. It is preferable to use a conductive material with a small work function for the common electrode 63.
• Examples of the material of the common electrode 63 include conductive oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO).
• the material of the common electrode 63 may be a metal such as silver (Ag), aluminum (Al), lithium (Li), magnesium (Mg), calcium (Ca), and ytterbium (Yb).
• the material of the common electrode 63 may be a metal compound or an alloy.
• the common electrode 63 may be formed of a single layer film or a laminated film.
• the sealing film 80 is provided on the light-emitting element layer 60.
• the sealing film 80 covers and seals the organic EL elements 65, and protects each organic EL element 65 (particularly the organic EL layer 62) from moisture, oxygen, and the like.
• the sealing film 80 is provided over the entire display area DA and extends to the frame area FA.
• the sealing film 80 has a first inorganic sealing layer 81, an organic sealing layer 82, and a second inorganic sealing layer 83.
• the first inorganic sealing layer 81, the organic sealing layer 82, and the second inorganic sealing layer 83 are provided in this order on the light-emitting element layer 60.
• the first inorganic sealing layer 81 and the second inorganic sealing layer 83 extend further toward the outer periphery of the frame area FA than the organic sealing layer 82, and overlap each other in the outer portion of the frame area FA.
• the organic sealing layer 82 is enclosed by the first inorganic sealing layer 81 and the second inorganic sealing layer 83.
• the first inorganic sealing layer 81 and the second inorganic sealing layer 83 are each made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.
• the organic sealing layer 82 is made of an organic resin material such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin. The organic sealing layer 82 is formed by applying a liquid material.
• the circuit board 5 of this embodiment 1 has multiple intervening layers 90 to prevent moisture that has traveled along the interface between the substrate layer 10 and the base coat film 21 from reaching the second semiconductor layer 31.
• Each of the multiple intervening layers 90 is formed in a rectangular island shape.
• the shape of each intervening layer 90 may be an island shape other than a rectangle, such as a circle.
• the intervening layers 90 are provided individually corresponding to the multiple subpixels SP. In this example, the intervening layers 90 are provided for all of the subpixels SP.
• Each intervening layer 90 is interposed between the substrate layer 10 and the first semiconductor layer 22 in a region corresponding to the contact hole CH.
• the contact hole CH is formed so that the opening area narrows toward the lower layer side, and has a tapered inner peripheral surface 36a.
• Each intervening layer 90 is provided between the inorganic insulating films that form the base coat film 21.
• the intervening layer 90 is provided between the first inorganic insulating film 21a and the second inorganic insulating film 21b.
• the first inorganic insulating film 21a is located below the intermediate layer 90.
• the second inorganic insulating film 21b and the third inorganic insulating film 21c are located above the intermediate layer 90.
• one inorganic insulating film that constitutes the base coat film 21 is provided below the intermediate layer 90, and multiple (two) inorganic insulating films are provided above the intermediate layer 90.
• the intermediate layer 90 may be provided between the second inorganic insulating film 21b and the third inorganic insulating film 21c.
• Each intermediate layer 90 is provided so as to overlap the entire lower opening of the contact hole CH in a plan view.
• the widths w1 and w2 (diameter if the intermediate layer 90 is circular) in the direction along each side of the intermediate layer 90 are larger than the lower opening diameter d1 of the contact hole CH. It is preferable that each intermediate layer 90 is provided so as to overlap the entire upper opening of the contact hole CH in a plan view. In this case, the widths w1 and w2 (diameter if the intermediate layer 90 is circular) in the direction along each side of the intermediate layer 90 are larger than the upper opening diameter d2 of the contact hole CH. Furthermore, it is even more preferable that each intermediate layer 90 is provided so as to overlap the entire connection portion 22c of the first semiconductor layer 22 to which the second terminal electrode 38 is connected via the contact hole CH in a plan view.
• the intermediate layer 90 is formed from an inorganic insulating material or a metallic material.
• inorganic insulating materials that form the intermediate layer 90 include silicon nitride (SiN).
• metallic materials that form the intermediate layer 90 include molybdenum (Mo), aluminum (Al), tungsten (W), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu). It is preferable that the material of the intermediate layer 90 is difficult for moisture to pass through.
• the TFT layer 20, the light emitting element layer 60, and the sealing film 80 are formed in this order on the substrate layer 10 using known film formation methods such as plasma CVD (Chemical Vapor Deposition), sputtering, and vacuum deposition, known coating methods such as spin coating and slit coating, and known patterning techniques such as photolithography.
• known film formation methods such as plasma CVD (Chemical Vapor Deposition), sputtering, and vacuum deposition
• known coating methods such as spin coating and slit coating
• known patterning techniques such as photolithography.
• the glass substrate 100 is peeled off from the substrate layer 10, for example by irradiating the rear surface of the substrate layer 10 with laser light from the glass substrate 100 side.
• a protective film is attached to the rear surface of the substrate layer 10.
• a polarizing plate and a cover panel are attached to the surface of the sealing film 80.
• a wiring substrate CB is connected to the terminal portion TP.
• a display control circuit (source driver) is implemented on the panel that constitutes the organic EL display device 1.
• the organic EL display device 1 can be manufactured.
• an island-shaped intermediate layer 90 is provided between the substrate layer 10 and the first semiconductor layer 22 in a region corresponding to the contact hole CH.
• the intermediate layer 90 inhibits moisture that has traveled along the interface between the substrate layer 10 and the base coat film 21 from permeating to the contact hole CH. This makes it possible to prevent moisture from reaching the second semiconductor layer 31 through the contact hole CH from the substrate layer 10 side. This makes it possible to prevent the characteristics of the second semiconductor layer 31 from changing due to the intrusion of moisture.
• the intermediate layer 90 is island-shaped, the internal stress caused by providing the intermediate layer 90 can be kept small. This makes it easy to make the intermediate layer 90 relatively thick and increase the effect of suppressing moisture penetration. Furthermore, when the intermediate layer 90 is formed from an inorganic insulating material, it is possible to suppress the occurrence of cracks in the intermediate layer 90 due to bending of the circuit board 5, etc. Furthermore, when the intermediate layer 90 is formed from a metal material, it is possible to reduce the effect of static electricity caused by the intermediate layer 90 and the reflection of light by the intermediate layer 90 on the image display.
• the base coat film 21 has a laminated structure of inorganic insulating films.
• Such a base coat film 21 has a relatively high moisture-proof function that suppresses the penetration of moisture compared to a single-layer structure.
• the intervening layer 90 is provided between the inorganic insulating films that form the base coat film 21. This makes it possible to effectively suppress the penetration of moisture that has passed through the interface between the substrate layer 10 and the base coat film 21 to the contact hole CH side.
• the intervening layer 90 is provided so as to overlap the entire lower opening of the contact hole CH in a plan view. This allows the intervening layer 90 to completely block the shortest path for moisture that has traveled along the interface between the substrate layer 10 and the base coat film 21 to penetrate into the contact hole CH. This is advantageous in preventing moisture from reaching the second semiconductor layer 31 from the substrate layer 10 side through the contact hole CH.
• the intervening layer 90 is provided so as to overlap the entire upper opening of the contact hole CH in a plan view. This makes it possible to prevent the tapered shape of the inner periphery of the contact hole CH from collapsing due to the step caused by the intervening layer 90. This is advantageous for good connection between the second terminal electrode 38 and the third terminal electrode 28 and the first semiconductor layer 22, and further between the second semiconductor layer 31 and the first semiconductor layer 22.
• the organic EL display device 1 of this embodiment 1 includes the circuit board 5 described above. This makes it possible to suppress changes in the characteristics of the second semiconductor layer 31, thereby improving the display quality of the organic EL display device 1 and increasing its reliability.
• the intervening layer 90 is provided individually corresponding to the multiple subpixels SP.
• the intervening layer 90 is provided in a fine pattern in this manner, the internal stress caused by the provision of the intervening layer 90 can be suitably suppressed. This is advantageous for adjusting the thickness of the intervening layer 90 to a range that can effectively suppress the penetration of moisture.
• the second semiconductor layer 31 constitutes the second TFT 50B provided in each subpixel SP. Therefore, by providing the intervening layer 90, it is possible to suppress changes in the characteristics of the second TFT 50B due to the intrusion of moisture.
• the intervening layer 90 is provided for all the subpixels SP. This makes it possible to uniformly suppress changes in the characteristics of the second TFT 50B due to the intrusion of moisture in all the subpixels SP.
• the organic EL display device 1 according to the second embodiment differs from the organic EL display device 1 according to the first embodiment in the range in which the intermediate layer 90 is provided.
• the organic EL display device 1 is configured similarly to the organic EL display device 1 according to the first embodiment except for the range in which the intermediate layer 90 is provided, and detailed description thereof will be omitted.
• the intervening layer 90 is provided only in some of the subpixels SP of the display area DA.
• the display area DA has a peripheral area DA1 and an inner area DA2.
• the peripheral area DA1 includes an outer peripheral area DA11 and an inner peripheral area DA12.
• the outer peripheral area DA11 is an area that runs along the outer periphery of the display area DA.
• the inner peripheral area DA12 is an area of the display area DA that runs along the periphery of the through-hole TH.
• the peripheral region DA1 is a frame-shaped region along the edge of the substrate layer 10, and a relatively large amount of moisture penetrates from the outside into the interface between the substrate layer 10 and the base coat film 21. Therefore, in each subpixel SP in the peripheral region DA1, the characteristics of the second semiconductor layer 31 are easily affected and changed by the intrusion of moisture. For this reason, as shown in the upper diagram of Figure 8, the intervening layer 90 is provided for multiple subpixels SP that make up the peripheral region DA1 (outer peripheral region DA11 and inner peripheral region DA12).
• the inner region DA2 is the region excluding the peripheral region DA1, and the amount of moisture that penetrates from the outside to the interface between the substrate layer 10 and the base coat film 21 is relatively small. Therefore, the characteristics of the second semiconductor layer 31 in each subpixel SP in the inner region DA2 are less susceptible to change due to the intrusion of moisture than the characteristics of the first semiconductor layer 22 in the subpixels SP in the peripheral region DA1. For this reason, as shown in the lower diagram of Figure 8, the intervening layer 90 is not provided for the multiple subpixels SP that make up the inner region DA2.
• an intervening layer 90 is provided for a plurality of sub-pixels SP constituting the peripheral region DA1 of the display region DA.
• the intervening layer 90 provided for each sub-pixel SP of the peripheral region DA1 functions effectively to suppress characteristic changes of the second semiconductor layer 31.
• the intervening layer 90 is not provided for the inner region DA2 of the display region DA. Therefore, the degree of characteristic changes of the second semiconductor layer 31 caused by the intrusion of moisture can be matched between the peripheral region DA1 and the inner region DA2. This is advantageous in suppressing unevenness in the image display of the organic EL display device 1.
• the size (area in a plan view) of the interposition layer 90 differs among the multiple regions into which the display area DA is divided.
• the display area DA has a peripheral area DA1, a middle area DA3, and an inner area DA2.
• the peripheral area DA1 is the same as that in the second embodiment.
• the middle area DA3 is a frame-shaped area that follows the inner periphery of the peripheral area DA1.
• the inner area DA2 is an area located inside the middle area DA3.
• the intervening layer 90 is provided for each of the multiple subpixels SP that form the peripheral region DA1, the multiple subpixels SP that form the intermediate region DA3, and the multiple subpixels SP that form the inner region DA2.
• the characteristics of the second semiconductor layer 31 shift according to the amount of moisture. The amount of moisture that reaches the second semiconductor layer 31 increases the closer it is to the edge of the substrate layer 10, and decreases the further it is from the edge of the substrate layer 10.
• the size of the intermediate layer 90 is smaller in the order of peripheral region DA1, intermediate region DA3, and inner region DA2. That is, the size of the intermediate layer 90 provided in peripheral region DA1 is larger than the size of the intermediate layer 90 provided in intermediate region DA3.
• the size of the intermediate layer 90 provided in intermediate region DA3 is larger than the size of the intermediate layer 90 provided in inner region DA2.
• the intermediate layer 90 in inner region DA2 is set to a size equivalent to the connection portion 22c of the first semiconductor layer 22.
• the size of the intermediate layer 90 is smaller in the order of the peripheral region DA1, the intermediate region DA3, and the inner region DA2. This allows the amounts of moisture reaching the second semiconductor layer 31 from the outside along the interface between the substrate layer 10 and the base coat film 21 to be adjusted to match among the peripheral region DA1, the intermediate region DA3, and the inner region DA2, and makes it possible to match the degree of change in the characteristics of the second semiconductor layer 31 caused by the intrusion of moisture. This is advantageous in suppressing unevenness in the image display of the organic EL display device 1.
• the intermediate layer 90 may be provided between the substrate layer 10 and the base coat film 21. Also, as shown in Fig. 12, the intermediate layer 90 may be provided on the base coat film 21. In this case, the connection portion 22c of the first semiconductor layer 22 is provided directly on the intermediate layer 90. In short, it is only necessary that the intermediate layer 90 is provided so as to be interposed between the substrate layer 10 and the connection portion 22c of the first semiconductor layer 22 in a region corresponding to the contact hole CH.
• the base coat film 21 may have a four-layer structure.
• the base coat film 21 has a fourth inorganic insulating film 21d in addition to the first to third inorganic insulating films 21a, 21b, and 21c.
• the fourth inorganic insulating film 21d is located in the lowest layer of the multiple inorganic insulating films that make up the base coat film 21.
• the fourth inorganic insulating film 21d is provided below the first inorganic insulating film 21a.
• the intermediate layer 90 may be provided between the fourth inorganic insulating film 21d and the first inorganic insulating film 21a. Even in this case, the inorganic insulating films that make up the base coat film 21 are provided in multiple layers (three layers) above the intermediate layer 90.
• the intermediate layer 90 is provided only in the region corresponding to the contact hole CH (second contact hole Hb) that connects the third terminal electrode 28 of the second TFT 50B to the first semiconductor layer 22, but the present invention is not limited to this.
• the intermediate layer 90 may also be provided in the region corresponding to the fourth contact hole Hd that connects the fourth terminal electrode 29 of the second TFT 50B to the relay line 40r. This can prevent moisture that has traveled along the interface between the substrate layer 10 and the base coat film 21 from permeating to the fourth contact hole Hd, thereby preventing moisture from reaching the second semiconductor layer 31 from the substrate layer 10 through the fourth contact hole Hd.
• the third terminal electrode 28 of the second TFT 50B is integrally formed with the second terminal electrode 38 of the first TFT 50A and connected to the first semiconductor layer 22, but this is not limited to the above.
• the conductive portion according to the technology disclosed herein is not limited to a semiconductor layer, and may be wiring, an electrode, or the like.
• the third terminal electrode 28 of the second TFT 50B may be connected to a metal wiring via a contact hole CH. This metal wiring may be integrally formed with the second terminal electrode 38 of the first TFT 50A and connected to the first semiconductor layer 22.
• the organic EL layer 62 is provided individually for each subpixel SP, but this is not limited to the above.
• the organic EL layer 62 may be provided as a single continuous layer in common for multiple subpixels SP.
• the organic EL display device 1 may be provided with a color filter, for example, to express color tones in each subpixel SP.
• each pixel PX is configured with sub-pixels SP of three colors, but this is not limited to this.
• the sub-pixels SP that configure each pixel PX may be four or more colors.
• the three sub-pixels SP that configure each pixel PX are arranged in a stripe pattern, but this is not limited to this.
• the arrangement of the multiple sub-pixels SP may be another arrangement, such as a pentile arrangement.
• the pixel electrode 61 functions as an anode and the common electrode 63 functions as a cathode, but this is not limited to the above.
• the organic EL display device 1 may be configured so that the pixel electrode 61 functions as a cathode and the common electrode 63 functions as an anode.
• the organic EL layer 62 has an inverted laminated structure.
• the organic EL layer 62 has a five-layer structure consisting of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, but this is not limited to the above.
• the organic EL layer 62 may have a three-layer structure consisting of a hole injection layer/transport layer, a light-emitting layer, and an electron transport layer/injection layer, or any other laminated structure may be used.
• the substrate of the organic EL display device 1 is the substrate layer 10, but this is not limited to this.
• the substrate can be made of any material, such as a plastic substrate made of polyethylene terephthalate (PET) or a glass substrate, as long as it is optically transparent.
• the camera 3 is exemplified as an electronic component that can be combined with the organic EL display device 1, but this is not limiting.
• the electronic component may be any other electronic component, such as a fingerprint sensor, face recognition sensor, or brightness sensor, as long as it is disposed on the rear side of the organic EL display device 1 and uses light that passes through the through-hole TH.
• the organic EL display device 1 does not need to have a through-hole TH and need not be combined with an electronic component that uses light, such as a camera.
• an organic EL display device 1 has been exemplified as a display device according to the present disclosure, but this is not limited thereto.
• the technology of the present disclosure is applicable to a display device equipped with a plurality of light-emitting elements.
• An example of such a display device is a quantum dot display device equipped with QLEDs (Quantum-dot Light Emitting Diodes), which are light-emitting elements that use a quantum dot-containing layer.
• QLEDs Quantum-dot Light Emitting Diodes
• the technology of the present disclosure is also applicable to liquid crystal display devices and plasma display devices.

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• 2023
  • 2023-04-10 WO PCT/JP2023/014545 patent/WO2024214141A1/ja not_active Ceased
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