WO2024178908A1 - 扫描电路和显示面板 - Google Patents

扫描电路和显示面板 Download PDF

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Publication number
WO2024178908A1
WO2024178908A1 PCT/CN2023/110193 CN2023110193W WO2024178908A1 WO 2024178908 A1 WO2024178908 A1 WO 2024178908A1 CN 2023110193 W CN2023110193 W CN 2023110193W WO 2024178908 A1 WO2024178908 A1 WO 2024178908A1
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WIPO (PCT)
Prior art keywords
transistor
control
input
signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/110193
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English (en)
French (fr)
Inventor
郭恩卿
李俊峰
盖翠丽
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Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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Publication of WO2024178908A1 publication Critical patent/WO2024178908A1/zh
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Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the present application relate to the technical field of display, for example, to a scanning circuit and a display panel.
  • the scanning circuit in the display panel is configured to provide a scanning signal to the pixel unit and control the pixel unit in the display panel to be driven row by row.
  • the clock signal provided to the scanning circuit needs to be set to an intermediate state to ensure that the scanning circuit outputs the scanning signal normally.
  • the intermediate state of the clock signal will take a certain amount of time, resulting in a relatively short pulse time of the scanning signal, which is not conducive to the display of the display panel.
  • the present application provides a scanning circuit and a display panel to increase the pulse width of a scanning signal, which is beneficial to improving the resolution and refresh rate of the display panel.
  • the embodiment of the present application provides a scanning circuit, including a first control module, a second control module and an output module;
  • the first control module is connected to the first control end of the output module, and the first control module is configured to output a first control signal to the first control end according to an input signal, a first clock signal and a first power supply;
  • the second control module is connected to the second control end of the output module, and the second control module is configured to output a second control signal to the second control end according to the input signal, the first clock signal, the first control signal, the first power supply and the second clock signal; wherein the level of the first control signal is opposite to the level of the second control signal;
  • the output module is configured to output the first power supply according to the first control signal and output the second clock signal according to the second control signal.
  • the first control module includes an input inverting unit and a clock following unit; the input inverting unit and the clock following unit have different working phases.
  • the control end of the input inverting unit is used to input the input signal
  • the input end of the input inverting unit is connected to the first power input end connected to the first power supply
  • the output end of the input inverting unit is connected to the first control end
  • the input inverting unit is used to invert the input signal when the input signal is valid.
  • the control end of the clock following unit is connected to the input signal end of the input signal.
  • the first input end of the follower unit is connected to the first power supply input end
  • the second input end of the clock follower unit is connected to the first clock signal input end
  • the output end of the clock follower unit is connected to the first control end
  • the clock follower unit is used to output the first clock signal when the first clock signal is valid.
  • the input inverting unit includes a first transistor
  • the clock following unit includes a second transistor, a third transistor and a first capacitor
  • the gate of the first transistor and the gate of the second transistor are both used to input the input signal, the first electrode of the first transistor and the first electrode of the second transistor are both connected to the first power supply input terminal, the second electrode of the first transistor and the second electrode of the third transistor are both connected to the first control terminal, the second electrode of the second transistor is connected to the gate of the third transistor and the first electrode of the first capacitor, and the first electrode of the third transistor and the second electrode of the first capacitor are both connected to the first clock signal input terminal.
  • the second control module includes an input follower unit
  • the control end of the input follower unit is connected to the first clock signal input end, the input end of the input follower unit is connected to the input signal end, the output end of the input follower unit is connected to the second control end, and the input follower unit is used to output the input signal when the first clock signal is valid.
  • the second control module further includes a node control unit
  • the third control terminal of the node control unit is connected to the first control terminal
  • the fourth control terminal of the node control unit is connected to the second clock signal input terminal
  • the input terminal of the node control unit is connected to the first power input terminal
  • the output terminal of the node control unit is connected to the second control terminal
  • the node control unit is used to control the potential of the second control terminal according to the first control signal and the second clock signal.
  • the input follower unit includes a fourth transistor, and the node control unit includes a fifth transistor and a sixth transistor;
  • the gate of the fourth transistor is connected to the first clock signal input terminal, the first electrode of the fourth transistor is connected to the input signal terminal, the second electrode of the fourth transistor and the second electrode of the sixth transistor are connected to the second control terminal; the gate of the fifth transistor is connected to the first control terminal, the first electrode of the fifth transistor is connected to the first power supply input terminal, the second electrode of the fifth transistor is connected to the first electrode of the sixth transistor, and the gate of the sixth transistor is connected to the second clock signal input terminal.
  • a gate of the first transistor is connected to an input signal terminal connected to the input signal.
  • the gate of the first transistor is connected to the second electrode of the fourth transistor.
  • the output module includes a first output unit and a second output unit;
  • the control end of the first output unit serves as the first control end, the input end of the first output unit is connected to the first power input end, and the output end of the first output unit is connected to the output end of the second output unit, serving as the output end of the scanning circuit; the control end of the second output unit serves as the second control end, and the input end of the second output unit is connected to the second clock signal input end.
  • the first output unit includes a seventh transistor and a second capacitor; the gate of the seventh transistor is connected to the first electrode of the second capacitor as the first control terminal, the first electrode of the seventh transistor and the second electrode of the second capacitor are connected to the first power input terminal, and the second electrode of the seventh transistor serves as the output terminal of the scanning circuit.
  • the second output unit includes an eighth transistor and a third capacitor; the gate of the eighth transistor is connected to the first electrode of the third capacitor as the second control terminal, the first electrode of the eighth transistor is connected to the second clock signal input terminal, and the second electrode of the eighth transistor is connected to the second electrode of the third capacitor as the output terminal of the scanning circuit.
  • the second output unit includes an eighth transistor, a ninth transistor and a third capacitor; the gate of the eighth transistor and the gate of the ninth transistor are connected to the first electrode of the third capacitor as the second control terminal, the first electrode of the eighth transistor and the first electrode of the ninth transistor are both connected to the second clock signal input terminal, the second electrode of the ninth transistor is connected to the second electrode of the third capacitor, and the second electrode of the eighth transistor serves as the output terminal of the scanning circuit.
  • the scanning circuit further includes a tenth transistor; a gate of the tenth transistor is connected to a second power input terminal connected to the second power supply, and the second control module is connected to the second control terminal through the tenth transistor.
  • An embodiment of the present application further provides a display panel, comprising a pixel driving circuit and a scanning circuit as described in any embodiment; the scanning circuit is connected to the pixel driving circuit, and the scanning circuit is configured to provide a scanning signal to the pixel driving circuit.
  • the technical solution of the embodiment of the present application sets the first control signal and the second control signal as signals with opposite levels.
  • the output module outputs the second clock signal according to the second control signal, when the second clock signal jumps from a high level to a low level, it can ensure that the output module stops outputting the first power supply according to the first control signal, avoids setting an intermediate state of the clock signal, and avoids the output module from mistakenly outputting the first power supply when the second clock signal jumps from a high level to a low level, thereby increasing the pulse width of the scanning signal output by the scanning circuit.
  • the scanning circuit is used for a display panel, it is beneficial to improve the display effect of the display panel.
  • FIG1 is a schematic diagram of a partial structure of a scanning circuit
  • FIG2 is a schematic diagram of the structure of a scanning circuit provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application.
  • FIG9 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application.
  • FIG12 is a signal timing diagram corresponding to the scanning circuit provided in FIG11;
  • FIG13 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • FIG. 14 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • Fig. 1 is a partial structural diagram of a scanning circuit.
  • the scanning circuit includes a first output transistor M1, a second output transistor M2 and a first control transistor M3, the gate of the first output transistor M1 is connected to the second electrode of the first control transistor M3, the first electrode of the first output transistor M1 is connected to the high-level power input terminal VGH, the second electrode of the first output transistor M1 is connected to the second electrode of the second output transistor M2, the lead wire at the connection point serves as the output terminal OUT of the scanning circuit, the gate of the second output transistor M2 is connected to the gate of the first control transistor M3, the first electrode of the second output transistor M2 is connected to the second clock signal input terminal CK2, the first electrode of the first control transistor M3 is connected to the first clock signal input terminal CK1, and the gate of the first control transistor M3 and the gate of the second output transistor M2 are set to input the start signal.
  • the start signal is at a low level
  • the first clock signal provided by the first clock signal input terminal CK1 is at a low level
  • the second clock signal provided by the second clock signal input terminal CK2 is at a high level
  • the first output transistor M1, the second output transistor M2 and the first control transistor M3 are turned on, and the output terminal OUT of the scanning circuit outputs a high level.
  • the first clock signal jumps before the second clock signal, that is, the first clock signal jumps from a low level to a high level first.
  • the first clock signal and the second clock signal are both at a high level, so that the first output transistor M1 is first turned off under the action of the first clock signal, and then the second clock signal jumps from a high level to a low level, so that The second output transistor M2 outputs a low level, thereby achieving the shift of the input signal.
  • the first clock signal jumps before the second clock signal, so that the state in which the first clock signal and the second clock signal are both high level is the intermediate state of the clock signal, which takes a certain time, resulting in the time of the scanning signal output by the scanning circuit being one intermediate state time less than the line time, which is not conducive to the display of the display panel.
  • the line time is the display period of the display panel divided by the number of rows of pixel units in the display panel, and the display period of the display panel is the inverse of the refresh rate of the display panel.
  • FIG2 is a schematic diagram of the structure of a scanning circuit provided by the embodiment of the present application.
  • the scanning circuit includes a first control module 110, a second control module 120 and an output module 130; the first control module 110 is connected to the first control terminal CTRL1 of the output module 130, and the first control module 110 is configured to output a first control signal to the first control terminal CTRL1 according to an input signal, a first clock signal and a first power supply; the second control module 120 is connected to the second control terminal CTRL2 of the output module 130, and the second control module 120 is configured to output a second control signal to the second control terminal CTRL2 according to an input signal, a first clock signal, a first control signal, a first power supply and a second clock signal; wherein the levels of the first control signal and the second control signal are opposite; the output module 130 is configured to output a first power supply according to the first control signal and output a second clock signal according to the second control signal.
  • the input signal terminal SIN is configured to provide an input signal
  • the first clock signal input terminal CLK1 is configured to provide a first clock signal
  • the second clock signal input terminal CLK2 is configured to provide a second clock signal
  • the first power supply input terminal VH is configured to provide a first power supply.
  • the output terminal SOUT of the scanning circuit is configured to output a scanning signal.
  • the output terminal SOUT of the scanning circuit is the output terminal of the output module 130.
  • the first power supply can be a high level
  • the first clock signal and the second clock signal can be signals of opposite levels
  • the first control signal and the second control signal can be signals of opposite levels.
  • the output signal of the output terminal of the output module 130 turned on by the low level of the control terminal as an example, when the first control terminal CTRL1 of the output module 130 is a low level, the first power supply is output, and when the second control terminal CTRL2 of the output module 130 is a low level, the second clock signal is output, and the following description is made.
  • the output module 130 can output the second clock signal according to the second control signal.
  • the level of the first control signal is opposite to that of the second control signal, that is, the first control signal is a high level, and the output module 130 stops outputting the first power supply according to the first control signal.
  • the second control signal is at a low level and the first control signal is at a high level.
  • the output module 130 has stopped outputting the high-level first power supply according to the high-level first control signal.
  • the output module 130 outputs the low-level second clock signal according to the low-level second control signal. It is no longer necessary to make the first clock signal jump before the second clock signal to control the output module 130 to stop outputting the high-level first power supply. It can ensure that the output module 130 only outputs the low-level second clock signal and avoid the appearance of the intermediate state of the clock signal. Therefore, the pulse width of the scanning signal output by the scanning circuit can be increased, which is beneficial to improving the display effect of the display panel.
  • the input signal is at a low level
  • the first clock signal is at a low level
  • the second clock signal is at a high level.
  • the second control module 120 controls the output of the second control signal according to the level of the input signal and the first clock signal to be the same as the input signal level, that is, a low level.
  • the first control signal output by the first control module 110 according to the input signal and the first clock signal is the same as the first power supply level, that is, the first control signal is at a high level, to ensure that the second control signal and the first control signal have opposite levels.
  • the output module 130 is configured to: the scan signal SOUT output according to the second control signal (low level) is the second clock signal, and the output of the first power supply is stopped according to the first control signal (high level), that is, the scan signal SOUT output by the scanning circuit in the first stage is a high level.
  • the first control signal is at a high level, when the second clock signal changes from a high level to a low level, it can also ensure that the output module 130 cannot output the level signal of the first power supply according to the first control signal (high level), thereby avoiding the occurrence of an intermediate state of the clock signal, so as to avoid the output module 130 from erroneously outputting the first power supply when the second clock signal changes from a high level to a low level, thereby increasing the pulse width of the scanning signal output by the scanning circuit.
  • the technical solution of this embodiment by setting the first control signal and the second control signal to signals of opposite levels, can ensure that the output module stops outputting the first power supply according to the first control signal when the second clock signal jumps from a high level to a low level and the output module outputs the second clock signal according to the second control signal, thereby avoiding the occurrence of an intermediate state of the clock signal, so as to avoid the output module from erroneously outputting the first power supply when the second clock signal jumps from a high level to a low level, thereby increasing the pulse width of the scanning signal output by the scanning circuit, which is beneficial to improving the display effect of the display panel.
  • Fig. 3 is a schematic diagram of the structure of another scanning circuit provided by an embodiment of the present application.
  • the first control module 110 includes an input inverting unit 111 and a clock following unit 112; the input inverting unit 111 and the clock following unit 112 have different working stages; the control end of the input inverting unit 111 is set to input an input signal, the input end of the input inverting unit 111 is connected to the first power input end VH, the output end of the input inverting unit 111 is connected to the first control end CTRL1, and the input inverting unit 111 is set to invert the input signal when the input signal is valid; the control end of the clock following unit 112 is connected to the input signal end SIN, the first input end of the clock following unit 112 is connected to the first power input end VH, the second input end of the clock following unit 112 is connected to the first clock signal input end CLK1, the output end of the clock following unit 112 is connected to the first control end CTRL1, and the clock following unit 11
  • FIG3 exemplarily shows that the control end of the input inverting unit 111 is connected to the input signal end SIN, and the control end is set to input the input signal.
  • the input signal and the first clock signal as an example, which are valid when they are at low levels.
  • the input signal is at a low level
  • the first clock signal is at a low level
  • the second clock signal is at a high level.
  • the input inverting unit 111 is set as a path according to the input signal and outputs the first control signal to the first control end CTRL1, so that the level of the first control signal is the same as the level of the first power supply, both of which are high levels, to achieve the inversion of the input signal.
  • the output module 130 stops outputting the first power supply according to the first control signal.
  • the input inverting unit 111 and the clock following unit 112 have different working phases. When the input inverting unit 111 inverts the input signal and outputs it, the clock following unit 112 stops outputting the first clock signal.
  • the input signal is at a high level
  • the first clock signal is at a high level
  • the second clock signal is at a low level.
  • the first clock signal is invalid.
  • the input inverting unit 111 is set to an open circuit according to the input signal
  • the clock following unit 112 is set to an open circuit according to the first clock signal, so that the first control terminal CTRL1 is in a floating state.
  • the potential maintaining function of the output module 130 maintains the potential of the first control terminal CTRL1 at a high level.
  • the input signal is at a high level
  • the first clock signal is at a low level
  • the second clock signal is at a high level. At this time, the first clock signal is valid.
  • the input inverting unit 111 is set to an open circuit according to the input signal, and the clock following unit 112 is set to a passage according to the first clock signal.
  • the clock following unit 112 follows and outputs the first control signal to the first control terminal CTRL1, that is, the level of the first control signal is the same as the level of the first clock signal, both of which are low levels, so that the output module 130 outputs the level signal of the first power supply according to the first control signal, that is, the scanning signal output by the scanning circuit is at a high level.
  • the input inverting unit 111 and the clock following unit 112 have different working stages. When the clock following unit 112 outputs the first clock signal, the input inverting unit 111 stops inverting and outputting the input signal.
  • Fig. 4 is a schematic diagram of the structure of another scanning circuit provided by an embodiment of the present application.
  • the input inverting unit 111 includes a first transistor T1
  • the clock following unit 112 includes a second transistor T2, a third transistor T3 and a first capacitor C1;
  • the gate of the first transistor T1 and the gate of the second transistor T2 are both set to input an input signal
  • the first electrode of the first transistor T1 and the first electrode of the second transistor T2 are both connected to the first power input terminal VH
  • the second electrode of the first transistor T1 and the second electrode of the third transistor T3 are both connected to the first control terminal CTRL1
  • the second electrode of the second transistor T2 is connected to the gate of the third transistor T3 and the first electrode of the first capacitor C1
  • the first electrode of the third transistor T3 and the second electrode of the first capacitor C1 are both connected to the first clock signal input terminal CLK1.
  • FIG4 exemplarily shows that the first transistor T1, the second transistor T2 and the third transistor T3 are P-type transistors, and the gate of the first transistor T1 and the gate of the second transistor T2 are both connected to the input signal terminal SIN, and the gate of the first transistor T1 and the gate of the second transistor T2 are both set to input the input signal.
  • the first power supply is at a high level.
  • the first transistor T1 is turned on according to the input signal, and the first power supply provided by the first power supply input terminal VH is output to the first control terminal CTRL1 to achieve the inversion of the input signal.
  • the second transistor T2 is turned on, and the second transistor T2 transmits the first power supply provided by the first power supply input terminal VH to the gate of the third transistor T3, and controls the third transistor T3 to be cut off, that is, the clock follower unit 112 stops outputting the first clock signal.
  • the input signal is at a high level, the first transistor T1 and the second transistor T2 are cut off, that is, the input inversion unit 111 stops inverting and outputting the input signal.
  • the first clock signal provided by the first clock signal input terminal CLK1 changes from a high level to a low level
  • the first capacitor C1 couples the first clock signal to the gate of the third transistor T3, so that the gate of the third transistor T3 is at a low level
  • the third transistor T3 is controlled to be turned on
  • the third transistor T3 outputs a first control signal to the first control terminal CTRL1, that is, the level of the first control signal is the same as the level of the first clock signal, both of which are low levels.
  • the output module 130 outputs a level signal of the first power supply according to the first control signal, and the scanning signal output by the scanning circuit at this stage is a high level.
  • the first transistor T1 , the second transistor T2 and the third transistor T3 may also be N-type transistors, in which case the high and low levels of the signal are inverted.
  • Fig. 5 is a schematic diagram of the structure of another scanning circuit provided by an embodiment of the present application.
  • the second control module 120 includes an input follower unit 121 and a node control unit 122; the control end of the input follower unit 121 is connected to the first clock signal input end CLK1, the input end of the input follower unit 121 is connected to the input signal end SIN, the output end of the input follower unit 121 is connected to the second control end CTRL2, and the input follower unit 121 is configured to output the input signal when the first clock signal is valid; the third control end of the node control unit 122 is connected to the first control end CTRL1, the fourth control end of the node control unit 122 is connected to the second clock signal input end CLK2, the input end of the node control unit 122 is connected to the first power input end VH, the output end of the node control unit 122 is connected to the second control end CTRL2, and the node control unit 122 is configured to control the potential of the second control end CTRL2 according
  • the input signal and the first clock signal are valid when they are low level.
  • the input signal is low level
  • the first clock signal is low level
  • the second clock signal is high level.
  • the input follower unit 121 is set as a path according to the first clock signal and outputs the second control signal to the second control terminal CTRL2, so that the level of the second control signal is the same as the level of the input signal, both of which are low level.
  • the output module 130 outputs the second clock signal according to the second control signal, that is, the scan signal is high level.
  • the first control signal is high level
  • the control node control unit 122 is open circuit.
  • the input signal is high level
  • the first clock signal is high level
  • the second clock signal is low level
  • the input follower unit 121 is set to open circuit according to the first clock signal.
  • the first control signal is maintained at a high level
  • the control node control unit 122 is continuously open circuit, so that the second control terminal CTRL2 is in a floating state.
  • the potential maintenance function of the output module 130 maintains the potential of the second control terminal CTRL2 at a low level, and the output module 130 outputs the second clock signal according to the second control signal, that is, the scan signal is low level, realizing the shift output of the input signal.
  • the input signal is at a high level
  • the first clock signal is at a low level
  • the second clock signal is at a high level
  • the input follower unit 121 is set as a path according to the first clock signal.
  • the input follower unit 121 outputs a second control signal to the second control terminal CTRL2.
  • the level of the second control signal is the same as the level of the input signal, both of which are high levels.
  • the output module 130 stops outputting the second clock signal according to the second control signal.
  • the first control signal is at a low level
  • the second clock signal is at a high level
  • the node control unit 122 is set as an open circuit according to the second clock signal.
  • the input signal is at a high level
  • the first clock signal is at a high level
  • the second clock signal is at a low level
  • the input follower unit 121 is set to be disconnected according to the first clock signal.
  • the first control module 110 is set to be disconnected according to the input signal and the first clock signal, and the potential maintaining function of the output module 130 maintains the potential of the first control terminal CTRL1 at a low level.
  • the node control unit 122 is set to be a passage according to the first control signal and the second clock signal, and the node control unit 122 outputs a second control signal to the second control terminal CTRL2.
  • the level of the second control signal is the same as the level of the first power supply, both of which are high levels, and the output module 130 stops outputting the second clock signal according to the second control signal.
  • Fig. 6 is a schematic diagram of the structure of another scanning circuit provided by an embodiment of the present application.
  • the input follower unit 121 includes a fourth transistor T4, and the node control unit 122 includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fourth transistor T4 is connected to the first clock signal input terminal CLK1, the first electrode of the fourth transistor T4 is connected to the input signal terminal SIN, the second electrode of the fourth transistor T4 and the second electrode of the sixth transistor T6 are connected to the second control terminal CTRL2;
  • the gate of the fifth transistor T5 is connected to the first control terminal CTRL1, the first electrode of the fifth transistor T5 is connected to the first power input terminal VH, the second electrode of the fifth transistor T5 is connected to the first electrode of the sixth transistor T6, and the gate of the sixth transistor T6 is connected to the second clock signal input terminal CLK2.
  • FIG6 exemplarily shows that the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all P-type transistors.
  • the first power supply is at a high level.
  • the input signal is at a low level
  • the first clock signal is at a low level
  • the second clock signal is at a high level.
  • the fourth transistor T4 is turned on
  • the sixth transistor T6 is turned off, and the fourth transistor T4 outputs a second control signal to the second control terminal CTRL2, so that the level of the second control signal is the same as the level of the input signal, both of which are low levels.
  • the output module 130 outputs a second clock signal according to the second control signal, that is, the scanning signal is at a high level.
  • the first control signal is at a high level, and the fifth transistor T5 is controlled to be turned off.
  • the input signal is at a high level
  • the first clock signal is at a high level
  • the second clock signal is at a low level
  • the fourth transistor T4 is turned off
  • the sixth transistor T6 is turned on.
  • the first control signal is maintained at a high level
  • the fifth transistor T5 is turned off, so that the second control terminal CTRL2 is in a floating state.
  • the potential maintaining function of the output module 130 maintains the potential of the second control terminal CTRL2 at a low level, and the output module 130 outputs the second clock signal according to the second control signal, that is, the scanning signal is at a low level, thereby realizing the shift output of the input signal.
  • the input signal is at a high level
  • the first clock signal is at a low level
  • the second clock signal is at a high level
  • the fourth transistor T4 is turned on
  • the sixth transistor T6 is turned off.
  • the fourth transistor T4 outputs a high level to the second control terminal CTRL2, that is, the second control signal is at a high level
  • the output module 130 stops outputting the second clock signal according to the second control signal.
  • the first control signal is at a low level
  • the fifth transistor T5 is turned on.
  • the input signal is at a high level
  • the first clock signal is at a high level
  • the second clock signal is at a low level
  • the fourth transistor T4 is turned off
  • the sixth transistor T6 is turned on.
  • the potential of the first control terminal CTRL1 is maintained at a low level, the fifth transistor T5 is turned on, and the first power supply is transmitted to the second control terminal CTRL2 as the second control signal through the fifth transistor T5 and the sixth transistor T6, that is, the level of the second control signal is the same as the level of the first power supply, both are high levels, and the output module 130 stops outputting the second clock signal according to the second control signal.
  • the gate of the first transistor T1 is connected to the input signal terminal SIN.
  • the input signal terminal SIN is configured to provide an input signal
  • the gate of the first transistor T1 may be directly connected to the input signal terminal SIN, so that the gate of the first transistor T1 is connected to the input signal.
  • Fig. 7 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application. As shown in Fig. 7, the gate of the first transistor T1 is connected to the second electrode of the fourth transistor T4.
  • the fourth transistor T4 serves as an input follower unit 121 and can output an input signal when the first clock signal is at a low level.
  • the gate of the first transistor T1 is connected to the second electrode of the fourth transistor T4, so that the first transistor T1 can obtain the input signal when the fourth transistor T4 outputs the input signal.
  • Fig. 8 is a schematic diagram of the structure of another scanning circuit provided by an embodiment of the present application.
  • the output module 130 includes a first output unit 131 and a second output unit 132; the control end of the first output unit 131 serves as the first control end CTRL1, the input end of the first output unit 131 is connected to the first power input end VH, the output end of the first output unit 131 is connected to the output end of the second output unit 132, and the lead wire at the connection serves as the output end SOUT of the scanning circuit; the control end of the second output unit 132 serves as the second control end CTRL2, and the input end of the second output unit 132 is connected to the second clock signal input end CLK2.
  • the potential of the first control terminal CTRL1 controls the state of the first output unit 131
  • the potential of the second control terminal CTRL2 controls the state of the second output unit 132.
  • the first control signal is at a low level
  • the first output unit 131 is in a pass state, and the first output unit 131 can output the first power provided by the first power input terminal VH to the output terminal SOUT, and use the first power as a scan signal of the scan circuit.
  • both the first output unit 131 and the second output unit 132 have a control terminal potential maintenance function, so that when the first control terminal CTRL1 and the second control terminal CTRL2 are in a floating state, the potentials of the first control terminal CTRL1 and the second control terminal CTRL2 can be maintained respectively.
  • Fig. 9 is a schematic diagram of the structure of another scanning circuit provided by an embodiment of the present application.
  • the first output unit 131 includes a seventh transistor T7 and a second capacitor C2; the gate of the seventh transistor T7 is connected to the first electrode of the second capacitor C2, and the lead wire at the connection is used as the first control terminal CTRL1, the first electrode of the seventh transistor T7 and the second electrode of the second capacitor C2 are connected to the first power input terminal VH, and the second electrode of the seventh transistor T7 is used as the output terminal SOUT of the scanning circuit;
  • the second output unit 132 includes an eighth transistor T8 and a third capacitor C3; the gate of the eighth transistor T8 is connected to the first electrode of the third capacitor C3, and the lead wire at the connection is used as the second control terminal CTRL2, the first electrode of the eighth transistor T8 is connected to the second clock signal input terminal CLK2, the second electrode of the eighth transistor T8 is connected to the second electrode of the third capacitor C3, and the lead wire at the connection is used as the output terminal
  • FIG9 exemplarily shows that the seventh transistor T7 and the eighth transistor T8 are P-type transistors.
  • the seventh transistor T7 is turned on, the first power supply is output to the output terminal SOUT through the seventh transistor T7, and the first power supply is used as a scanning signal of the scanning circuit.
  • the first control module 110 is set to be disconnected, the potential of the first control terminal CTRL1 is in a floating state, and the potential of the first control terminal CTRL1 can be maintained by the second capacitor C2.
  • the second control signal is at a low level
  • the potential of the second control terminal CTRL2 is at a low level
  • the eighth transistor T8 is turned on
  • the second clock signal is output to the output terminal SOUT through the eighth transistor T8, and the second clock signal is used as a scanning signal of the scanning circuit.
  • the second control module 120 is set to be disconnected
  • the potential of the second control terminal CTRL2 is in a floating state, and the potential of the second control terminal CTRL2 can be maintained by the third capacitor C3.
  • the third capacitor C3 has a coupling effect.
  • the scanning signal outputted from the output terminal SOUT of the scanning circuit jumps from a high level to a low level, and the coupling effect of the third capacitor C3 makes the gate potential of the eighth transistor T8 lower than the low level potential of the second clock signal, thereby ensuring the on-state of the eighth transistor T8 and eliminating the threshold voltage loss when the eighth transistor T8 transmits the second clock signal, ensuring that the level of the second clock signal outputted from the output terminal SOUT is relatively low, and ensuring the reliability of the scanning signal outputted by the scanning circuit.
  • Fig. 10 is a schematic diagram of the structure of another scanning circuit provided by an embodiment of the present application.
  • the first output unit 131 includes a seventh transistor T7 and a second capacitor C2; the gate of the seventh transistor T7 is connected to the first electrode of the second capacitor C2, and the lead wire at the connection is used as the first control terminal CTRL1, the first electrode of the seventh transistor T7 and the second electrode of the second capacitor C2 are connected to the first power input terminal VH, and the second electrode of the seventh transistor T7 is used as the output terminal SOUT of the scanning circuit;
  • the second output unit 132 includes an eighth transistor T8, a ninth transistor T9 and a third capacitor C3; the gate of the eighth transistor T8 and the gate of the ninth transistor T9 are connected to the first electrode of the third capacitor C3, and the lead wire at the connection is used as the second control terminal CTRL2, the first electrode of the eighth transistor T8 and the first electrode of the ninth transistor T9 are both connected to the second clock signal input terminal CLK2, the second electrode of the ninth transistor T
  • the difference of FIG. 10 is that the structure of the second output unit 132 and the connection relationship between the components are different.
  • the eighth transistor T8 and the ninth transistor T9 are turned on at the same time, the eighth transistor T8 outputs the second clock signal to the output terminal SOUT, and the ninth transistor T9 outputs the second clock signal to the second pole of the third capacitor C3.
  • the third capacitor C3 can directly couple the second clock signal to the gate of the eighth transistor T8, thereby improving the coupling speed, which is conducive to further improving the reliability of the scanning circuit outputting the scanning signal.
  • Fig. 11 is a schematic diagram of the structure of another scanning circuit provided in an embodiment of the present application.
  • the scanning circuit further includes a tenth transistor T10; the gate of the tenth transistor T10 is connected to the second power input terminal VL, and the second control module 120 is connected to the second control terminal CTRL2 through the tenth transistor T10.
  • FIG11 exemplarily shows that the tenth transistor T10 is a P-type transistor, and the second power supply provided by the second power supply input terminal VL is at a low level.
  • the second control signal is at a high level
  • the tenth transistor T10 is in an on state.
  • the second control signal is at a low level
  • the tenth transistor T10 is in a near-cutoff state.
  • the second clock signal jumps from a high level to a low level, when the potential of the second control terminal CTRL2 is less than the low level potential due to the coupling effect, the low potential can be prevented from being transmitted to the second control module 120, thereby preventing damage to the devices in the second control module 120.
  • the second control module 120 includes a fourth transistor T4 and a sixth transistor T6, the second pole potential of the fourth transistor T4 and the sixth transistor T6 can be prevented from being too low, resulting in device damage caused by a large difference between the gate potential of the fourth transistor T4 and the sixth transistor T6 and the second pole potential.
  • FIG12 is a signal timing diagram corresponding to the scanning circuit provided in FIG11.
  • the first power supply is at a high level and the second power supply is at a low level as an example for explanation.
  • sin is the timing of the input signal provided by the input signal terminal SIN
  • clk1 is the timing of the first clock signal provided by the first clock signal input terminal CLK1
  • clk2 is the timing of the second clock signal provided by the second clock signal input terminal CLK2
  • sout is the timing of the scanning signal output by the output terminal SOUT of the scanning circuit.
  • the working principle of the scanning circuit is explained below through FIG11 and FIG12.
  • the input signal is at a low level
  • the first clock signal is at a low level
  • the second clock signal is at a high level.
  • the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on, and the sixth transistor T6 is turned off.
  • the first power supply is transmitted to the first control terminal CTRL1 through the first transistor T1, and the fifth transistor T5 and the seventh transistor T7 are turned off.
  • the first power supply is transmitted to the gate of the third transistor T3 through the second transistor T2, and the third transistor T3 is turned off.
  • the input signal is output to the second control terminal CTRL2 through the fourth transistor T4 and the tenth transistor T10, and the eighth transistor T8 and the ninth transistor T9 are turned on.
  • the eighth transistor T8 outputs the second clock signal to the output terminal SOUT, and the scanning signal is at a high level in the first stage t1.
  • the ninth transistor T9 directly outputs the second clock signal to the third capacitor C3, which can improve the coupling speed, which is conducive to further improving the reliability of the scanning circuit output scanning signal.
  • the input signal is at a high level
  • the first clock signal is at a high level
  • the second clock signal is at a low level.
  • the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off, and the sixth transistor T6 is turned on.
  • the gate of the third transistor T3 is at a high level, and the third transistor T3 is turned off.
  • the first control terminal CTRL1 is in a floating state, and the maintenance effect of the second capacitor C2 makes the potential of the first control terminal CTRL1 maintain the potential of the first stage t1, which is a high level, and the fifth transistor T5 and the seventh transistor T7 continue to be turned off.
  • the second control terminal CTRL2 is in a floating state.
  • the coupling effect of the third capacitor C3 maintains the potential of the second control terminal CTRL2 less than the low level, and the eighth transistor T8 and the ninth transistor T9 are continuously turned on, which can eliminate the threshold voltage loss when the eighth transistor T8 transmits the second clock signal, ensuring that the level of the second clock signal output by the output terminal SOUT is relatively low, and ensuring the reliability of the scanning signal output by the scanning circuit.
  • the first control terminal CTRL1 The potential of the first control terminal CTRL1 is high level, and in the second stage t2, the potential of the first control terminal CTRL1 is maintained at a high level.
  • the seventh transistor T7 is always in a cut-off state, thereby avoiding the appearance of an intermediate state of the clock signal, and avoiding the seventh transistor T7 from erroneously outputting the first power when the second clock signal jumps from a high level to a low level, thereby increasing the pulse width of the scanning signal output by the scanning circuit, which is beneficial to improving the display effect of the display panel.
  • the input signal is at a high level
  • the first clock signal is at a low level
  • the second clock signal is at a high level.
  • the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off, and the fourth transistor T4 is turned on.
  • the fourth transistor T4 transmits the input signal to the second control terminal CTRL2, and controls the eighth transistor T8 and the ninth transistor T9 to be turned off.
  • the first capacitor C1 couples the first clock signal to the gate of the third transistor T3, so that the gate of the third transistor T3 is at a low level, controls the third transistor T3 to be turned on, and the third transistor T3 outputs the first control signal to the first control terminal CTRL1.
  • the level of the first control signal is the same as the level of the first clock signal, both of which are low levels.
  • the seventh transistor T7 and the fifth transistor T5 are controlled to be turned on, and the first power supply is output to the output terminal SOUT through the seventh transistor T7.
  • the scanning signal is at a high level.
  • the input signal is high level
  • the first clock signal is high level
  • the second clock signal is low level
  • the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off, and the sixth transistor T6 is turned on.
  • the first clock signal jumps from low level to high level
  • the gate of the third transistor T3 is high level
  • the third transistor T3 is turned off.
  • the first control terminal CTRL1 is in a floating state, and the maintenance effect of the second capacitor C2 makes the potential of the first control terminal CTRL1 maintain the potential of the third stage t3, which is low level, and the seventh transistor T7 and the fifth transistor T5 are controlled to be turned on.
  • the first power supply is output to the output terminal SOUT through the seventh transistor T7.
  • the scanning signal is high level.
  • the first power supply is transmitted to the second control terminal CTRL2 through the fifth transistor T5 and the sixth transistor T6 as the second control signal, that is, the level of the second control signal is the same as the level of the first power supply, both of which are high level, and the eighth transistor T8 and the ninth transistor T9 are controlled to be turned off.
  • FIG13 is a schematic diagram of the structure of a display panel provided by the embodiment of the present application.
  • the display panel includes a pixel driving circuit 10 and a scanning circuit 20 provided by any embodiment of the present application; the scanning circuit 20 is connected to the pixel driving circuit 10, and the scanning circuit 20 is configured to provide a scanning signal to the pixel driving circuit 10.
  • the display panel may be, for example, an organic light emitting diode display panel, a liquid crystal display panel, or an electronic paper display panel.
  • the display panel may include a plurality of rows of pixel driving circuits 10, a plurality of scanning circuits 20, and an input signal line 30.
  • the plurality of scanning circuits 20 are cascaded, the input signal end of the first scanning circuit 20 is connected to the input signal line 30, and the input signal provided by the input signal line 30 is shifted and output.
  • the input signal end of the next scanning circuit 20 is connected to the output end of the previous scanning circuit 20, so that Each scanning circuit 20 is connected to a row of pixel driving circuits 10, and each scanning circuit 20 is configured to provide a scanning signal for a row of pixel driving circuits 10.
  • the cascaded scanning circuits 20 output scanning signals step by step, the scanning signals can be output row by row to the pixel driving circuits 10 to control the pixel driving circuits 10 to work normally.
  • FIG14 is a schematic diagram of the structure of a display device provided in the embodiment of the present application.
  • the display device includes a display panel 1 provided in any embodiment of the present application.
  • the display device can be, for example, a mobile phone, a tablet computer, a smart wearable device, an information inquiry machine in a public place hall, etc.
  • the display device includes the display panel 1 provided in any embodiment of the present application, and its technical principles and technical effects are similar, which will not be repeated here.

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Abstract

一种扫描电路（20）和显示面板（1）。扫描电路（20）包括第一控制模块(110)、第二控制模块(120)和输出模块(130)；第一控制模块(110)与输出模块(130)的第一控制端连接，第一控制模块(110)设置为根据输入信号、第一时钟信号和第一电源输出第一控制信号至第一控制端；第二控制模块(120)与输出模块(130)的第二控制端连接，第二控制模块(120)设置为根据输入信号、第一时钟信号、第一控制信号、第一电源和第二时钟信号输出第二控制信号至第二控制端；其中，第一控制信号的电平和第二控制信号的电平相反；输出模块(130)设置为根据第一控制信号和第二控制信号输出第一电源或第二时钟信号。

Description

扫描电路和显示面板
本申请要求在2023年03月02日提交中国专利局、申请号为202310191390.4的中国专利申请的优先权，以上申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示的技术领域，例如涉及一种扫描电路和显示面板。
背景技术
显示面板中的扫描电路设置为为像素单元提供扫描信号，控制显示面板中的像素单元逐行驱动。一般，为扫描电路提供的时钟信号需要设置中间态，以保证扫描电路正常输出扫描信号。时钟信号的中间态会占用一定时间，导致扫描信号的脉冲时间比较小，不利于显示面板的显示。
发明内容
本申请提供一种扫描电路和显示面板，以增加扫描信号的脉冲宽度，有利于提高显示面板的分辨率和刷新率。
本申请实施例提供了一种扫描电路，包括第一控制模块、第二控制模块和输出模块；
所述第一控制模块与所述输出模块的第一控制端连接，所述第一控制模块设置为根据输入信号、第一时钟信号和第一电源输出第一控制信号至所述第一控制端；所述第二控制模块与所述输出模块的第二控制端连接，所述第二控制模块设置为根据所述输入信号、所述第一时钟信号、所述第一控制信号、所述第一电源和第二时钟信号输出第二控制信号至所述第二控制端；其中，所述第一控制信号的电平和所述第二控制信号的电平相反；所述输出模块设置为根据所述第一控制信号输出所述第一电源和根据所述第二控制信号输出所述第二时钟信号。
可选地，所述第一控制模块包括输入反相单元和时钟跟随单元；所述输入反相单元和所述时钟跟随单元的工作阶段不同。
所述输入反相单元的控制端用于输入所述输入信号，所述输入反相单元的输入端与接入第一电源的第一电源输入端连接，所述输入反相单元的输出端与所述第一控制端连接，所述输入反相单元用于在所述输入信号有效时反相所述输入信号。
所述时钟跟随单元的控制端与接入输入信号的输入信号端连接，所述时钟 跟随单元的第一输入端与所述第一电源输入端连接，所述时钟跟随单元的第二输入端与第一时钟信号输入端连接，所述时钟跟随单元的输出端与所述第一控制端连接，所述时钟跟随单元用于在所述第一时钟信号有效时输出所述第一时钟信号。
可选地，所述输入反相单元包括第一晶体管，所述时钟跟随单元包括第二晶体管、第三晶体管和第一电容；
所述第一晶体管的栅极和所述第二晶体管的栅极均用于输入所述输入信号，所述第一晶体管的第一极和所述第二晶体管的第一极均与所述第一电源输入端连接，所述第一晶体管的第二极和所述第三晶体管的第二极均与所述第一控制端连接，所述第二晶体管的第二极与所述第三晶体管的栅极和所述第一电容的第一极连接，所述第三晶体管的第一极和所述第一电容的第二极均与所述第一时钟信号输入端连接。
可选地，所述第二控制模块包括输入跟随单元；
所述输入跟随单元的控制端与所述第一时钟信号输入端连接，所述输入跟随单元的输入端与所述输入信号端连接，所述输入跟随单元的输出端与所述第二控制端连接，所述输入跟随单元用于在所述第一时钟信号有效时输出所述输入信号。
可选的，所述第二控制模块还包括节点控制单元；
所述节点控制单元的第三控制端与所述第一控制端连接，所述节点控制单元的第四控制端与第二时钟信号输入端连接，所述节点控制单元的输入端与所述第一电源输入端连接，所述节点控制单元的输出端与所述第二控制端连接，所述节点控制单元用于根据所述第一控制信号和所述第二时钟信号控制所述第二控制端的电位。
可选地，所述输入跟随单元包括第四晶体管，所述节点控制单元包括第五晶体管和第六晶体管；
所述第四晶体管的栅极与所述第一时钟信号输入端连接，所述第四晶体管的第一极与所述输入信号端连接，所述第四晶体管的第二极和所述第六晶体管的第二极与所述第二控制端连接；所述第五晶体管的栅极与所述第一控制端连接，所述第五晶体管的第一极与所述第一电源输入端连接，所述第五晶体管的第二极与所述第六晶体管的第一极连接，所述第六晶体管的栅极与所述第二时钟信号输入端连接。
可选地，所述第一晶体管的栅极与接入所述输入信号的输入信号端连接。
可选的，所述第一晶体管的栅极与所述第四晶体管的第二极连接。
可选地，所述输出模块包括第一输出单元和第二输出单元；
所述第一输出单元的控制端作为所述第一控制端，所述第一输出单元的输入端与第一电源输入端连接，所述第一输出单元的输出端与所述第二输出单元的输出端连接，作为所述扫描电路的输出端；所述第二输出单元的控制端作为所述第二控制端，所述第二输出单元的输入端与第二时钟信号输入端连接。
可选地，所述第一输出单元包括第七晶体管和第二电容；所述第七晶体管的栅极和所述第二电容的第一极连接，作为所述第一控制端，所述第七晶体管的第一极和所述第二电容的第二极与所述第一电源输入端连接，所述第七晶体管的第二极作为所述扫描电路的输出端。
所述第二输出单元包括第八晶体管和第三电容；所述第八晶体管的栅极与所述第三电容的第一极连接，作为所述第二控制端，所述第八晶体管的第一极与第二时钟信号输入端连接，所述第八晶体管的第二极与所述第三电容的第二极连接，作为所述扫描电路的输出端。
所述第二输出单元包括第八晶体管、第九晶体管和第三电容；所述第八晶体管的栅极和所述第九晶体管的栅极与所述第三电容的第一极连接，作为所述第二控制端，所述第八晶体管的第一极和所述第九晶体管的第一极均与所述第二时钟信号输入端连接，所述第九晶体管的第二极与所述第三电容的第二极连接，所述第八晶体管的第二极作为所述扫描电路的输出端。
可选地，扫描电路还包括第十晶体管；所述第十晶体管的栅极与接入所述第二电源的第二电源输入端连接，所述第二控制模块通过所述第十晶体管与所述第二控制端连接。
本申请实施例还提供了一种显示面板，包括像素驱动电路和任一实施例所述的扫描电路；所述扫描电路与所述像素驱动电路连接，所述扫描电路设置为为所述像素驱动电路提供扫描信号。
本申请实施例的技术方案，通过设置第一控制信号和第二控制信号为电平相反的信号，在输出模块根据第二控制信号输出第二时钟信号时，当第二时钟信号由高电平跳变为低电平时，可以保证输出模块根据第一控制信号停止输出第一电源，避免设置时钟信号的中间态以避免输出模块在第二时钟信号由高电平跳变为低电平时误输出第一电源，从而可以增加扫描电路输出的扫描信号的脉冲宽度。当扫描电路用于显示面板时，有利于提高显示面板的显示效果。
附图说明
图1为一种扫描电路的部分结构示意图；
图2为本申请实施例提供的一种扫描电路的结构示意图；
图3为本申请实施例提供的另一种扫描电路的结构示意图；
图4为本申请实施例提供的另一种扫描电路的结构示意图；
图5为本申请实施例提供的另一种扫描电路的结构示意图；
图6为本申请实施例提供的另一种扫描电路的结构示意图；
图7为本申请实施例提供的另一种扫描电路的结构示意图；
图8为本申请实施例提供的另一种扫描电路的结构示意图；
图9为本申请实施例提供的另一种扫描电路的结构示意图；
图10为本申请实施例提供的另一种扫描电路的结构示意图；
图11为本申请实施例提供的另一种扫描电路的结构示意图；
图12为图11提供的扫描电路对应的一种信号时序图；
图13为本申请实施例提供的一种显示面板的结构示意图；
图14为本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
图1为一种扫描电路的部分结构示意图。如图1所示，扫描电路包括第一输出晶体管M1、第二输出晶体管M2和第一控制晶体管M3，第一输出晶体管M1的栅极与第一控制晶体管M3的第二极连接，第一输出晶体管M1的第一极与高电平电源输入端VGH连接，第一输出晶体管M1的第二极与第二输出晶体管M2的第二极连接，连接处的引出线作为扫描电路的输出端OUT，第二输出晶体管M2的栅极与第一控制晶体管M3的栅极连接，第二输出晶体管M2的第一极与第二时钟信号输入端CK2连接，第一控制晶体管M3的第一极与第一时钟信号输入端CK1连接，第一控制晶体管M3的栅极和第二输出晶体管M2的栅极设置为输入启动信号。
以扫描电路的输出端OUT输出的扫描信号为低电平时驱动像素驱动电路工作为例进行如下说明。在第一阶段，启动信号为低电平，第一时钟信号输入端CK1提供的第一时钟信号为低电平，第二时钟信号输入端CK2提供的第二时钟信号为高电平，第一输出晶体管M1、第二输出晶体管M2和第一控制晶体管M3导通，扫描电路的输出端OUT输出高电平。在下一阶段到来之前，第一时钟信号优先于第二时钟信号跳变，即第一时钟信号先由低电平跳变为高电平，此时第一时钟信号和第二时钟信号同时为高电平，使得第一输出晶体管M1在第一时钟信号的作用下先关闭，然后第二时钟信号由高电平跳变为低电平，使得 第二输出晶体管M2输出低电平，从而实现输入信号的移位。在上述过程中，第一时钟信号优先于第二时钟信号跳变，使得第一时钟信号和第二时钟信号同时为高电平的状态即为时钟信号的中间态，需要占用一定时间，导致扫描电路输出的扫描信号的时间比行时间少一个中间态时间，不利于显示面板的显示。其中，行时间为显示面板的显示周期除以显示面板内像素单元的行数，显示面板的显示周期为显示面板的刷新率的倒数。
本申请实施例提供了一种扫描电路。图2为本申请实施例提供的一种扫描电路的结构示意图。如图2所示，该扫描电路包括第一控制模块110、第二控制模块120和输出模块130；第一控制模块110与输出模块130的第一控制端CTRL1连接，第一控制模块110设置为根据输入信号、第一时钟信号和第一电源输出第一控制信号至第一控制端CTRL1；第二控制模块120与输出模块130的第二控制端CTRL2连接，第二控制模块120设置为根据输入信号、第一时钟信号、第一控制信号、第一电源和第二时钟信号输出第二控制信号至第二控制端CTRL2；其中，第一控制信号和第二控制信号的电平相反；输出模块130设置为根据第一控制信号输出第一电源和根据第二控制信号输出第二时钟信号。
输入信号端SIN设置为提供输入信号，第一时钟信号输入端CLK1设置为提供第一时钟信号，第二时钟信号输入端CLK2设置为提供第二时钟信号，第一电源输入端VH设置为提供第一电源。扫描电路的输出端SOUT设置为输出扫描信号，在本实施例中扫描电路的输出端SOUT即为输出模块130的输出端。第一电源可以为高电平，第一时钟信号和第二时钟信号可以为电平相反的信号，以及第一控制信号和第二控制信号可以为电平相反的信号。以输出模块130由控制端的低电平导通输出端的输出信号为例，当输出模块130的第一控制端CTRL1为低电平时输出第一电源，当输出模块130的第二控制端CTRL2为低电平时输出第二时钟信号，进行如下说明。在扫描电路工作的过程中，当第二控制模块120提供的第二控制信号为低电平时，输出模块130可以根据第二控制信号输出第二时钟信号。此时第一控制信号与第二控制信号的电平相反，即第一控制信号为高电平，输出模块130根据第一控制信号停止输出第一电源。由此可以保证扫描电路输出第二时钟信号时，第二控制信号为低电平，第一控制信号为高电平。在第二时钟信号由高电平跳变为低电平之前，输出模块130已根据高电平的第一控制信号停止输出高电平的第一电源，在第二时钟信号由高电平跳变为低电平时，输出模块130根据低电平的第二控制信号输出低电平的第二时钟信号，不再需要使第一时钟信号优先于第二时钟信号跳变以控制输出模块130停止输出高电平的第一电源，既可以保证输出模块130仅输出低电平的第二时钟信号，又避免了时钟信号的中间态的出现，，从而可以增加扫描电路输出的扫描信号的脉冲宽度，有利于提高显示面板的显示效果。
示例性地，在第一阶段，输入信号为低电平，第一时钟信号为低电平，第二时钟信号为高电平。第二控制模块120根据输入信号和第一时钟信号的电平控制输出的第二控制信号与输入信号电平相同，即为低电平。此时第一控制模块110根据输入信号和第一时钟信号控制输出的第一控制信号与第一电源电平相同，即第一控制信号为高电平，以保证第二控制信号和第一控制信号的电平相反。输出模块130设置为：根据第二控制信号(低电平)输出的扫描信号SOUT为第二时钟信号，并根据第一控制信号(高电平)停止输出第一电源，也就是在该第一阶段扫描电路输出的扫描信号SOUT为高电平。由于第一控制信号为高电平，在第二时钟信号由高电平跳变为低电平时，也可以保证输出模块130根据第一控制信号(高电平)始终不能输出第一电源的电平信号，避免了时钟信号的中间态的出现，以避免输出模块130在第二时钟信号由高电平跳变为低电平时误输出第一电源，从而可以增加扫描电路输出的扫描信号的脉冲宽度。
本实施例的技术方案，通过设置第一控制信号和第二控制信号为电平相反的信号，在第二时钟信号由高电平跳变为低电平且输出模块根据第二控制信号输出第二时钟信号时，可以保证输出模块根据第一控制信号停止输出第一电源，避免了时钟信号的中间态的出现，以避免输出模块在第二时钟信号由高电平跳变为低电平时误输出第一电源，从而可以增加扫描电路输出的扫描信号的脉冲宽度，，有利于提高显示面板的显示效果。
图3为本申请实施例提供的另一种扫描电路的结构示意图。如图3所示，第一控制模块110包括输入反相单元111和时钟跟随单元112；输入反相单元111和时钟跟随单元112的工作阶段不同；输入反相单元111的控制端设置为输入输入信号，输入反相单元111的输入端与第一电源输入端VH连接，输入反相单元111的输出端与第一控制端CTRL1连接，输入反相单元111设置为在输入信号有效时反相输入信号；时钟跟随单元112的控制端与输入信号端SIN连接，时钟跟随单元112的第一输入端与第一电源输入端VH连接，时钟跟随单元112的第二输入端与第一时钟信号输入端CLK1连接，时钟跟随单元112的输出端与第一控制端CTRL1连接，时钟跟随单元112设置为在第一时钟信号有效时输出第一时钟信号。
图3中示例性地示出了输入反相单元111的控制端与输入信号端SIN连接，控制端设置为输入输入信号。以输入信号和第一时钟信号为低电平时有效为例进行说明。在第一阶段，输入信号为低电平，第一时钟信号为低电平，第二时钟信号为高电平。输入反相单元111根据输入信号设置为通路并输出第一控制信号至第一控制端CTRL1，使得第一控制信号的电平与第一电源的电平相同，均为高电平，实现输入信号的反相。输出模块130根据第一控制信号停止输出第一电源。由于第一控制信号为高电平，在第二时钟信号由高电平跳变为低电 平时，可以保证输出模块130根据第一控制信号始终不能输出第一电源的电平信号，避免了时钟信号的中间态的出现，以避免输出模块130在第二时钟信号由高电平跳变为低电平时误输出第一电源，从而可以增加扫描电路输出的扫描信号的脉冲宽度。输入反相单元111和时钟跟随单元112的工作阶段不同。当输入反相单元111对输入信号进行反相输出时，时钟跟随单元112停止输出第一时钟信号。
在第二阶段，输入信号为高电平，第一时钟信号为高电平，第二时钟信号为低电平，此时第一时钟信号无效。输入反相单元111根据输入信号设置为断路，时钟跟随单元112根据第一时钟信号设置为断路，使得第一控制端CTRL1为浮动状态。输出模块130的电位维持作用维持第一控制端CTRL1的电位为高电平。在第三阶段，输入信号为高电平，第一时钟信号为低电平，第二时钟信号为高电平，此时第一时钟信号有效。输入反相单元111根据输入信号设置为断路，时钟跟随单元112根据第一时钟信号设置为通路，时钟跟随单元112跟随输出第一控制信号至第一控制端CTRL1，即第一控制信号的电平与第一时钟信号的电平相同，均为低电平，使得输出模块130根据第一控制信号输出第一电源的电平信号，即扫描电路输出的扫描信号为高电平。同理，输入反相单元111和时钟跟随单元112的工作阶段不同。当时钟跟随单元112输出第一时钟信号时，输入反相单元111停止反相输出输入信号。
图4为本申请实施例提供的另一种扫描电路的结构示意图。如图4所示，输入反相单元111包括第一晶体管T1，时钟跟随单元112包括第二晶体管T2、第三晶体管T3和第一电容C1；第一晶体管T1的栅极和第二晶体管T2的栅极均设置为输入输入信号，第一晶体管T1的第一极和第二晶体管T2的第一极均与第一电源输入端VH连接，第一晶体管T1的第二极和第三晶体管T3的第二极均与第一控制端CTRL1连接，第二晶体管T2的第二极与第三晶体管T3的栅极和第一电容C1的第一极连接，第三晶体管T3的第一极和第一电容C1的第二极均与第一时钟信号输入端CLK1连接。
图4中示例性地示出了第一晶体管T1、第二晶体管T2和第三晶体管T3为P型晶体管，且第一晶体管T1的栅极和第二晶体管T2的栅极均与输入信号端SIN连接，第一晶体管T1的栅极和第二晶体管T2的栅极均设置为输入输入信号。第一电源为高电平，当输入信号为低电平时，第一晶体管T1根据输入信号导通，将第一电源输入端VH提供的第一电源输出至第一控制端CTRL1，实现输入信号的反相。此时第二晶体管T2导通，第二晶体管T2将第一电源输入端VH提供的第一电源传输至第三晶体管T3的栅极，控制第三晶体管T3截止，即时钟跟随单元112停止输出第一时钟信号。当输入信号为高电平时，第一晶体管T1和第二晶体管T2截止，即输入反相单元111停止反相输出输入信号。若 第一时钟信号输入端CLK1提供的第一时钟信号由高电平跳变为低电平，第一电容C1耦合第一时钟信号至第三晶体管T3的栅极，使得第三晶体管T3的栅极为低电平，控制第三晶体管T3导通，第三晶体管T3输出第一控制信号至第一控制端CTRL1，即第一控制信号的电平与第一时钟信号的电平相同，均为低电平。输出模块130根据第一控制信号输出第一电源的电平信号，在该阶段扫描电路输出的扫描信号为高电平。
在其他实施例中，第一晶体管T1、第二晶体管T2和第三晶体管T3还可以为N型晶体管，此时信号的高低电平反相。
图5为本申请实施例提供的另一种扫描电路的结构示意图。如图5所示，第二控制模块120包括输入跟随单元121和节点控制单元122；输入跟随单元121的控制端与第一时钟信号输入端CLK1连接，输入跟随单元121的输入端与输入信号端SIN连接，输入跟随单元121的输出端与第二控制端CTRL2连接，输入跟随单元121设置为在第一时钟信号有效时输出输入信号；节点控制单元122的第三控制端与第一控制端CTRL1连接，节点控制单元122的第四控制端与第二时钟信号输入端CLK2连接，节点控制单元122的输入端与第一电源输入端VH连接，节点控制单元122的输出端与第二控制端CTRL2连接，节点控制单元122设置为根据第一控制信号和第二时钟信号控制第二控制端CTRL2的电位。
以输入信号和第一时钟信号为低电平时有效为例进行说明。在第一阶段，输入信号为低电平，第一时钟信号为低电平，第二时钟信号为高电平。输入跟随单元121根据第一时钟信号设置为通路并输出第二控制信号至第二控制端CTRL2，使得第二控制信号的电平与输入信号的电平相同，均为低电平。输出模块130根据第二控制信号输出第二时钟信号，即扫描信号为高电平。第一控制信号为高电平，控制节点控制单元122为断路。在第二阶段，输入信号为高电平，第一时钟信号为高电平，第二时钟信号为低电平，输入跟随单元121根据第一时钟信号设置为断路。第一控制信号维持为高电平，继续控制节点控制单元122为断路，使得第二控制端CTRL2为浮动状态。输出模块130的电位维持作用维持第二控制端CTRL2的电位为低电平，输出模块130根据第二控制信号输出第二时钟信号，即扫描信号为低电平，实现了输入信号的移位输出。在第三阶段，输入信号为高电平，第一时钟信号为低电平，第二时钟信号为高电平，输入跟随单元121根据第一时钟信号设置为通路。输入跟随单元121输出第二控制信号至第二控制端CTRL2，第二控制信号的电平与输入信号的电平相同，均为高电平，输出模块130根据第二控制信号停止输出第二时钟信号。第一控制信号为低电平，第二时钟信号为高电平，节点控制单元122根据第二时钟信号设置为断路。在第四阶段，输入信号为高电平，第一时钟信号为高电平， 第二时钟信号为低电平，输入跟随单元121根据第一时钟信号设置为断路。第一控制模块110根据输入信号和第一时钟信号设置为断路，输出模块130的电位维持作用维持第一控制端CTRL1的电位为低电平，节点控制单元122根据第一控制信号和第二时钟信号设置为通路，节点控制单元122输出第二控制信号至第二控制端CTRL2，第二控制信号的电平与第一电源的电平相同，均为高电平，输出模块130根据第二控制信号停止输出第二时钟信号。
图6为本申请实施例提供的另一种扫描电路的结构示意图。如图6所示，输入跟随单元121包括第四晶体管T4，节点控制单元122包括第五晶体管T5和第六晶体管T6；第四晶体管T4的栅极与第一时钟信号输入端CLK1连接，第四晶体管T4的第一极与输入信号端SIN连接，第四晶体管T4的第二极和第六晶体管T6的第二极与第二控制端CTRL2连接；第五晶体管T5的栅极与第一控制端CTRL1连接，第五晶体管T5的第一极与第一电源输入端VH连接，第五晶体管T5的第二极与第六晶体管T6的第一极连接，第六晶体管T6的栅极与第二时钟信号输入端CLK2连接。
图6中示例性地示出了第四晶体管T4、第五晶体管T5和第六晶体管T6均为P型晶体管。第一电源为高电平，在第一阶段，输入信号为低电平，第一时钟信号为低电平，第二时钟信号为高电平。第四晶体管T4导通，第六晶体管T6截止，第四晶体管T4输出第二控制信号至第二控制端CTRL2，使得第二控制信号的电平与输入信号的电平相同，均为低电平。输出模块130根据第二控制信号输出第二时钟信号，即扫描信号为高电平。第一控制信号为高电平，控制第五晶体管T5截止。在第二阶段，输入信号为高电平，第一时钟信号为高电平，第二时钟信号为低电平，第四晶体管T4截止，第六晶体管T6导通。第一控制信号维持为高电平，第五晶体管T5截止，使得第二控制端CTRL2为浮动状态。输出模块130的电位维持作用维持第二控制端CTRL2的电位为低电平，输出模块130根据第二控制信号输出第二时钟信号，即扫描信号为低电平，实现了输入信号的移位输出。在第三阶段，输入信号为高电平，第一时钟信号为低电平，第二时钟信号为高电平，第四晶体管T4导通，第六晶体管T6截止。第四晶体管T4输出高电平至第二控制端CTRL2，即第二控制信号为高电平，输出模块130根据第二控制信号停止输出第二时钟信号。第一控制信号为低电平，第五晶体管T5导通。在第四阶段，输入信号为高电平，第一时钟信号为高电平，第二时钟信号为低电平，第四晶体管T4截止，第六晶体管T6导通。第一控制端CTRL1的电位维持为低电平，第五晶体管T5导通，第一电源作为第二控制信号通过第五晶体管T5和第六晶体管T6传输至第二控制端CTRL2，即第二控制信号的电平与第一电源的电平相同，均为高电平，输出模块130根据第二控制信号停止输出第二时钟信号。
可选地，第一晶体管T1的栅极与输入信号端SIN连接。
参考图6，输入信号端SIN设置为提供输入信号，第一晶体管T1的栅极可以直接与输入信号端SIN连接，使得第一晶体T1的栅极接入输入信号。
图7为本申请实施例提供的另一种扫描电路的结构示意图。如图7所示，第一晶体管T1的栅极与第四晶体管T4的第二极连接。
参考图7，第四晶体管T4作为输入跟随单元121，可以在第一时钟信号为低电平时输出输入信号，第一晶体管T1的栅极与第四晶体管T4的第二极连接，可以使第一晶体管T1在第四晶体管T4输出输入信号时获取输入信号。
图8为本申请实施例提供的另一种扫描电路的结构示意图。如图8所示，输出模块130包括第一输出单元131和第二输出单元132；第一输出单元131的控制端作为第一控制端CTRL1，第一输出单元131的输入端与第一电源输入端VH连接，第一输出单元131的输出端与第二输出单元132的输出端连接，连接处的引出线作为扫描电路的输出端SOUT；第二输出单元132的控制端作为第二控制端CTRL2，第二输出单元132的输入端与第二时钟信号输入端CLK2连接。
第一控制端CTRL1的电位控制第一输出单元131的状态，第二控制端CTRL2的电位控制第二输出单元132的状态。以第一控制信号和第二控制信号为低电平有效为例进行说明。当第一控制信号为低电平时，第一输出单元131处于通路状态，第一输出单元131可以将第一电源输入端VH提供的第一电源输出至输出端SOUT，将第一电源作为扫描电路的扫描信号。当第二控制信号为低电平时，第二输出单元132处于通路状态，第二输出单元132可以将第二时钟信号输入端CLK2提供的第二时钟信号输出至输出端SOUT，将第二时钟信号作为扫描电路的扫描信号。另外，第一输出单元131和第二输出单元132均具有控制端电位维持作用，使得第一控制端CTRL1和第二控制端CTRL2为浮动状态时可以分别维持第一控制端CTRL1和第二控制端CTRL2的电位。
图9为本申请实施例提供的另一种扫描电路的结构示意图。如图9所示，第一输出单元131包括第七晶体管T7和第二电容C2；第七晶体管T7的栅极和第二电容C2的第一极连接，连接处的引出线作为第一控制端CTRL1，第七晶体管T7的第一极和第二电容C2的第二极与第一电源输入端VH连接，第七晶体管T7的第二极作为扫描电路的输出端SOUT；第二输出单元132包括第八晶体管T8和第三电容C3；第八晶体管T8的栅极与第三电容C3的第一极连接，连接处的引出线作为第二控制端CTRL2，第八晶体管T8的第一极与第二时钟信号输入端CLK2连接，第八晶体管T8的第二极与第三电容C3的第二极连接，连接处的引出线作为扫描电路的输出端SOUT。
图9中示例性地示出了第七晶体管T7和第八晶体管T8为P型晶体管。当第一控制信号为低电平时，第一控制端CTRL1的电位为低电平，第七晶体管T7导通，第一电源通过第七晶体管T7输出至输出端SOUT，第一电源作为扫描电路的扫描信号。当第一控制模块110设置为断路时，第一控制端CTRL1的电位为浮动状态，可以通过第二电容C2维持第一控制端CTRL1的电位。当第二控制信号为低电平时，第二控制端CTRL2的电位为低电平，第八晶体管T8导通，第二时钟信号通过第八晶体管T8输出至输出端SOUT，第二时钟信号作为扫描电路的扫描信号。当第二控制模块120设置为断路时，第二控制端CTRL2的电位为浮动状态，可以通过第三电容C3维持第二控制端CTRL2的电位。另外，第三电容C3具有耦合作用。当第二时钟信号由高电平跳变为低电平时，扫描电路的输出端SOUT输出的扫描信号由高电平跳变为低电平，第三电容C3的耦合作用使得第八晶体管T8的栅极电位低于第二时钟信号的低电平电位，从而可以保证第八晶体管T8的导通状态，并可以消除第八晶体管T8传输第二时钟信号时的阈值电压损失，保证了输出端SOUT输出的第二时钟信号的电平比较低，保证了扫描电路输出的扫描信号的可靠性。
图10为本申请实施例提供的另一种扫描电路的结构示意图。如图10所示，第一输出单元131包括第七晶体管T7和第二电容C2；第七晶体管T7的栅极和第二电容C2的第一极连接，连接处的引出线作为第一控制端CTRL1，第七晶体管T7的第一极和第二电容C2的第二极与第一电源输入端VH连接，第七晶体管T7的第二极作为扫描电路的输出端SOUT；第二输出单元132包括第八晶体管T8、第九晶体管T9和第三电容C3；第八晶体管T8的栅极和第九晶体管T9的栅极与第三电容C3的第一极连接，连接处的引出线作为第二控制端CTRL2，第八晶体管T8的第一极和第九晶体管T9的第一极均与第二时钟信号输入端CLK2连接，第九晶体管T9的第二极与第三电容C3的第二极连接，第八晶体管T8的第二极作为扫描电路的输出端SOUT。
与图9相比，图10的区别在于第二输出单元132的结构以及部件之间连接关系不同。在第二控制信号为低电平时，第八晶体管T8和第九晶体管T9同时导通，第八晶体管T8输出第二时钟信号至输出端SOUT，第九晶体管T9输出第二时钟信号至第三电容C3的第二极。当第二时钟信号由高电平跳变为低电平时，第三电容C3可以直接耦合第二时钟信号至第八晶体管T8的栅极，提高了耦合速度，有利于进一步地提高扫描电路输出扫描信号的可靠性。
图11为本申请实施例提供的另一种扫描电路的结构示意图。如图11所示，扫描电路还包括第十晶体管T10；第十晶体管T10的栅极与第二电源输入端VL连接，第二控制模块120通过第十晶体管T10与第二控制端CTRL2连接。
图11示例性地示出了第十晶体管T10为P型晶体管，第二电源输入端VL提供的第二电源为低电平。当第二控制信号为高电平时，第十晶体管T10处于导通状态。第二控制信号为低电平时，第十晶体管T10处于临近截止状态。在第二时钟信号由高电平跳变为低电平，第二控制端CTRL2的电位由于耦合作用小于低电平电位时，可以避免该低电位传输至第二控制模块120，避免第二控制模块120内的器件损坏。例如，第二控制模块120包括第四晶体管T4和第六晶体管T6时，可以避免第四晶体管T4和第六晶体管T6的第二极电位太低，导致第四晶体管T4和第六晶体管T6的栅极电位与第二极电位差值太大造成的器件损坏。
图12为图11提供的扫描电路对应的一种信号时序图。参考图11和图12，以第一电源为高电平，第二电源为低电平为例进行说明。其中，sin为输入信号端SIN提供的输入信号的时序，clk1为第一时钟信号输入端CLK1提供的第一时钟信号的时序，clk2为第二时钟信号输入端CLK2提供的第二时钟信号的时序，sout为扫描电路的输出端SOUT输出的扫描信号的时序。以下通过图11和图12说明扫描电路的工作原理。
在第一阶段t1，输入信号为低电平，第一时钟信号为低电平，第二时钟信号为高电平。第一晶体管T1、第二晶体管T2和第四晶体管T4导通，第六晶体管T6截止。第一电源通过第一晶体管T1传输至第一控制端CTRL1，控制第五晶体管T5和第七晶体管T7截止。同时第一电源通过第二晶体管T2传输至第三晶体管T3的栅极，控制第三晶体管T3截止。输入信号通过第四晶体管T4和第十晶体管T10输出至第二控制端CTRL2，控制第八晶体管T8和第九晶体管T9导通，第八晶体管T8输出第二时钟信号至输出端SOUT，在该第一阶段t1扫描信号为高电平。另外，第九晶体管T9直接将第二时钟信号输出至第三电容C3，可以提高耦合速度，有利于进一步地提高扫描电路输出扫描信号的可靠性。
在第二阶段t2，输入信号为高电平，第一时钟信号为高电平，第二时钟信号为低电平。第一晶体管T1、第二晶体管T2和第四晶体管T4截止，第六晶体管T6导通。在第一时钟信号由低电平跳变为高电平时，在第一电容C1的耦合作用下，第三晶体管T3的栅极为高电平，第三晶体管T3截止，此时第一控制端CTRL1为浮动状态，第二电容C2的维持作用使得第一控制端CTRL1的电位维持为第一阶段t1的电位，为高电平，第五晶体管T5和第七晶体管T7继续截止。第二控制端CTRL2为浮动状态。当第二时钟信号由高电平跳变为低电平时，第三电容C3的耦合作用维持使得第二控制端CTRL2的电位小于低电平，第八晶体管T8和第九晶体管T9持续导通，可以消除第八晶体管T8传输第二时钟信号时的阈值电压损失，保证了输出端SOUT输出的第二时钟信号的电平比较低，保证了扫描电路输出的扫描信号的可靠性。由于第一阶段t1第一控制端CTRL1 的电位为高电平，在第二阶段t2，第一控制端CTRL1的电位维持为高电平。当第二时钟信号由高电平跳变为低电平时，可以保证第七晶体管T7一直处于截止状态，从而避免了时钟信号的中间态的出现，以避免第七晶体管T7在第二时钟信号由高电平跳变为低电平时误输出第一电源，增加了扫描电路输出的扫描信号的脉冲宽度，有利于提高显示面板的显示效果。
在第三阶段t3，输入信号为高电平，第一时钟信号为低电平，第二时钟信号为高电平。第一晶体管T1、第二晶体管T2和第六晶体管T6截止，第四晶体管T4导通，第四晶体管T4将输入信号传输至第二控制端CTRL2，控制第八晶体管T8和第九晶体管T9截止。在第一时钟信号由高电平跳变为低电平时，第一电容C1耦合第一时钟信号至第三晶体管T3的栅极，使得第三晶体管T3的栅极为低电平，控制第三晶体管T3导通，第三晶体管T3输出第一控制信号至第一控制端CTRL1，第一控制信号的电平与第一时钟信号的电平相同，均为低电平。控制第七晶体管T7和第五晶体管T5导通，第一电源通过第七晶体管T7输出至输出端SOUT，在该第三阶段t3扫描信号为高电平。
在第四阶段t4，输入信号为高电平，第一时钟信号为高电平，第二时钟信号为低电平。第一晶体管T1、第二晶体管T2和第四晶体管T4截止，第六晶体管T6导通。在第一时钟信号由低电平跳变为高电平时，在第一电容C1的耦合作用下，第三晶体管T3的栅极为高电平，第三晶体管T3截止，此时第一控制端CTRL1为浮动状态，第二电容C2的维持作用使得第一控制端CTRL1的电位维持为第三阶段t3的电位，为低电平，控制第七晶体管T7和第五晶体管T5导通，第一电源通过第七晶体管T7输出至输出端SOUT，在该第四阶段t4扫描信号为高电平。同时第一电源作为第二控制信号通过第五晶体管T5和第六晶体管T6传输至第二控制端CTRL2，即第二控制信号的电平与第一电源的电平相同，均为高电平，控制第八晶体管T8和第九晶体管T9截止。
本申请实施例还提供了一种显示面板。图13为本申请实施例提供的一种显示面板的结构示意图。如图13所示，该显示面板包括像素驱动电路10和本申请任意实施例提供的扫描电路20；扫描电路20与像素驱动电路10连接，扫描电路20设置为为像素驱动电路10提供扫描信号。
该显示面板例如可以为有机发光二极管显示面板、液晶显示面板或电子纸显示面板等。显示面板可以包括多行像素驱动电路10、多个扫描电路20和输入信号线30。多行扫描电路20进行级联，第一级扫描电路20的输入信号端与输入信号线30连接，并将输入信号线30提供的输入信号进行移位后输出。下一级扫描电路20的输入信号端与上一级扫描电路20的输出端连接，从而可以实 现输入信号的逐级输出。每个扫描电路20与一行像素驱动电路10连接，每个扫描电路20设置为为一行像素驱动电路10提供扫描信号。当级联的扫描电路20逐级输出扫描信号时，可以实现逐行输出扫描信号至像素驱动电路10，控制像素驱动电路10正常工作。
本申请实施例还提供了一种显示装置。图14为本申请实施例提供的一种显示装置的结构示意图。如图14所示，该显示装置包括本申请任意实施例提供的显示面板1。该显示装置例如可以是手机、平板电脑、智能穿戴设备、公共场所大厅的信息查询机等。该显示装置包括本申请任意实施例所提供的显示面板1，其技术原理和产生的技术效果类似，这里不再赘述。

Claims (16)

  1. 一种扫描电路，包括第一控制模块、第二控制模块和输出模块；
    所述第一控制模块与所述输出模块的第一控制端连接，所述第一控制模块设置为根据输入信号、第一时钟信号和第一电源输出第一控制信号至所述第一控制端；所述第二控制模块与所述输出模块的第二控制端连接，所述第二控制模块设置为根据所述输入信号、所述第一时钟信号、所述第一控制信号、所述第一电源和第二时钟信号输出第二控制信号至所述第二控制端；其中，所述第一控制信号的电平和所述第二控制信号的电平相反；所述输出模块设置为根据所述第一控制信号输出所述第一电源和根据所述第二控制信号输出所述第二时钟信号。
  2. 根据权利要求1所述的扫描电路，其中，所述第一控制模块包括输入反相单元和时钟跟随单元；所述输入反相单元的工作阶段和所述时钟跟随单元的工作阶段不同。
  3. 根据权利要求2所述的扫描电路，其中，所述输入反相单元的控制端设置为输入所述输入信号，所述输入反相单元的输入端与接入所述第一电源的第一电源输入端连接，所述输入反相单元的输出端与所述第一控制端连接，所述输入反相单元设置为在所述输入信号有效的情况下反相所述输入信号。
  4. 根据权利要求2所述的扫描电路，其中，所述时钟跟随单元的控制端与接入所述输入信号的输入信号端连接，所述时钟跟随单元的第一输入端与所述第一电源输入端连接，所述时钟跟随单元的第二输入端与第一时钟信号输入端连接，所述时钟跟随单元的输出端与所述第一控制端连接，所述时钟跟随单元设置为在所述第一时钟信号有效的情况下输出所述第一时钟信号。
  5. 根据权利要求2、3或4所述的扫描电路，其中，所述输入反相单元包括第一晶体管，所述时钟跟随单元包括第二晶体管、第三晶体管和第一电容；
    所述第一晶体管的栅极和所述第二晶体管的栅极均设置为输入所述输入信号，所述第一晶体管的第一极和所述第二晶体管的第一极均与所述第一电源输入端连接，所述第一晶体管的第二极和所述第三晶体管的第二极均与所述第一控制端连接，所述第二晶体管的第二极与所述第三晶体管的栅极和所述第一电容的第一极连接，所述第三晶体管的第一极和所述第一电容的第二极均与所述第一时钟信号输入端连接。
  6. 根据权利要求5所述的扫描电路，其中，所述第二控制模块包括输入跟随单元；
    所述输入跟随单元的控制端与所述第一时钟信号输入端连接，所述输入跟随单元的输入端与所述输入信号端连接，所述输入跟随单元的输出端与所述第 二控制端连接，所述输入跟随单元设置为在所述第一时钟信号有效的情况下输出所述输入信号。
  7. 根据权利要求6所述的扫描电路，其中，所述第二控制模块还包括节点控制单元；
    所述节点控制单元的第三控制端与所述第一控制端连接，所述节点控制单元的第四控制端与第二时钟信号输入端连接，所述节点控制单元的输入端与所述第一电源输入端连接，所述节点控制单元的输出端与所述第二控制端连接，所述节点控制单元设置为根据所述第一控制信号和所述第二时钟信号控制所述第二控制端的电位。
  8. 根据权利要求7所述的扫描电路，其中，所述输入跟随单元包括第四晶体管，所述节点控制单元包括第五晶体管和第六晶体管；
    所述第四晶体管的栅极与所述第一时钟信号输入端连接，所述第四晶体管的第一极与所述输入信号端连接，所述第四晶体管的第二极和所述第六晶体管的第二极与所述第二控制端连接；所述第五晶体管的栅极与所述第一控制端连接，所述第五晶体管的第一极与所述第一电源输入端连接，所述第五晶体管的第二极与所述第六晶体管的第一极连接，所述第六晶体管的栅极与所述第二时钟信号输入端连接。
  9. 根据权利要求5所述的扫描电路，其中，所述第一晶体管的栅极与接入所述输入信号的输入信号端连接。
  10. 根据权利要求8所述的扫描电路，其中，所述第一晶体管的栅极与所述第四晶体管的第二极连接。
  11. 根据权利要求1-10任一项所述的扫描电路，其中，所述输出模块包括第一输出单元和第二输出单元；
    所述第一输出单元的控制端作为所述第一控制端，所述第一输出单元的输入端与所述第一电源输入端连接，所述第一输出单元的输出端与所述第二输出单元的输出端连接，连接处的引出线作为所述扫描电路的输出端；所述第二输出单元的控制端作为所述第二控制端，所述第二输出单元的输入端与所述第二时钟信号输入端连接。
  12. 根据权利要求11所述的扫描电路，其中，所述第一输出单元包括第七晶体管和第二电容；所述第七晶体管的栅极和所述第二电容的第一极连接，连接处的引出线作为所述第一控制端，所述第七晶体管的第一极和所述第二电容的第二极与所述第一电源输入端连接，所述第七晶体管的第二极作为所述扫描电路的输出端。
  13. 根据权利要求11或12所述的扫描电路，其中，所述第二输出单元包括第八晶体管和第三电容；所述第八晶体管的栅极与所述第三电容的第一极连接，连接处的引出线作为所述第二控制端，所述第八晶体管的第一极与所述第二时钟信号输入端连接，所述第八晶体管的第二极与所述第三电容的第二极连接，连接处的引出线作为所述扫描电路的输出端。
  14. 根据权利要求11或12所述的扫描电路，其中，所述第二输出单元包括第八晶体管、第九晶体管和第三电容；所述第八晶体管的栅极和所述第九晶体管的栅极与所述第三电容的第一极连接，连接处的引出线作为所述第二控制端，所述第八晶体管的第一极和所述第九晶体管的第一极均与所述第二时钟信号输入端连接，所述第九晶体管的第二极与所述第三电容的第二极连接，所述第八晶体管的第二极作为所述扫描电路的输出端。
  15. 根据权利要求1所述的扫描电路，还包括第十晶体管；所述第十晶体管的栅极与接入所述第二电源的第二电源输入端连接，所述第二控制模块通过所述第十晶体管与所述第二控制端连接。
  16. 一种显示面板，包括像素驱动电路和权利要求1-15任一项所述的扫描电路；所述扫描电路与所述像素驱动电路连接，所述扫描电路设置为为所述像素驱动电路提供扫描信号。
PCT/CN2023/110193 2023-03-02 2023-07-31 扫描电路和显示面板 Ceased WO2024178908A1 (zh)

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