WO2024174082A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2024174082A1
WO2024174082A1 PCT/CN2023/077322 CN2023077322W WO2024174082A1 WO 2024174082 A1 WO2024174082 A1 WO 2024174082A1 CN 2023077322 W CN2023077322 W CN 2023077322W WO 2024174082 A1 WO2024174082 A1 WO 2024174082A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
shift register
transmission line
transistor
reset
Prior art date
Application number
PCT/CN2023/077322
Other languages
English (en)
French (fr)
Inventor
赵二瑾
于子阳
张跳梅
赵攀
谷泉泳
陈文波
蒋志亮
宋江
胡明
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2023/077322 priority Critical patent/WO2024174082A1/zh
Publication of WO2024174082A1 publication Critical patent/WO2024174082A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device.
  • a driving circuit is provided in the peripheral area of the display substrate to provide a driving signal for the pixel unit in the display area.
  • a plurality of pixel units are provided in the display area of the display device, and each pixel unit includes a pixel circuit.
  • Each pixel circuit is electrically connected to the driving circuit in the peripheral area, and the driving circuit provides a scanning signal and a light-emitting control signal to the pixel circuit to control the pixel circuit to provide a driving current for the light-emitting device.
  • the present disclosure provides a display substrate having a display area and a peripheral area, wherein the display area includes N pixel groups arranged along a first direction, each pixel group includes at least one row of the pixel areas, and the display substrate includes:
  • a plurality of first reset lines and a plurality of second reset lines are arranged on the base substrate, each row of pixel areas corresponds to one of the first reset lines and one of the second reset lines;
  • N+M first shift register units are arranged on the base substrate and located in the peripheral area, and the N+M first shift register units are arranged along the first direction, wherein the output end of the i-th first shift register unit is connected to the second reset line corresponding to the i-M-th row of pixel areas; the output end of the j-th first shift register is connected to the first reset line corresponding to the j-th row of pixel areas through a signal transmission line;
  • N is an integer greater than 2
  • M is a preset positive integer, M+1 ⁇ i ⁇ N+M, 1 ⁇ j ⁇ N, and i and j are both integers;
  • the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of at least one of the first shift register units on the substrate.
  • the first shift register unit includes: an output transistor, the output transistor is connected to the output end of the first shift register unit, and the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of at least one output transistor of the first shift register unit on the substrate.
  • an orthographic projection of each of the signal transmission lines on the substrate overlaps with an orthographic projection of M-1 of the first shift register units on the substrate.
  • the first shift register unit includes a storage capacitor, and an orthographic projection of the signal transmission line on the substrate has no overlap with an orthographic projection of the storage capacitor on the substrate.
  • the signal transmission line includes a plurality of transmission line segments and a connecting line segment located between two adjacent transmission line segments, and the transmission line segments extend along the first direction;
  • the signal transmission line has a head end and a tail end, the head end is connected to the output end of the first shift register unit, and the tail end is connected to the reset line; for two adjacent transmission line segments in the same signal transmission line, the distance from the transmission line segment close to the head end to the display area is greater than the distance from the transmission line segment far from the head end to the display area.
  • the connecting line segment is a straight line segment, and an obtuse angle is formed between the connecting line segment and an adjacent transmission line segment.
  • the connecting line segments in the signal transmission lines connected to the plurality of first shift register units are divided into a plurality of first line segment groups, the plurality of first line segment groups are arranged along the first direction, at least one of the first line segment groups includes M-1 connecting line segments,
  • the center line of the M-1 connecting line segments is a straight line, and the extension direction of the center line intersects with the first direction and the extension direction of the first reset line;
  • the centers of the M-1 connecting line segments are not connected on the same straight line.
  • the center connection line of the M-1 connecting line segments is a straight line, and the center connection and the connecting line segments are inclined in different directions.
  • the lengths of the connecting line segments are the same;
  • At least two connected line segments have different lengths.
  • the transmission line segments in the signal transmission line connected to the multiple first shift register units are divided into multiple second line segment groups, the multiple second line segment groups are arranged along a second direction, each of the second line segment groups includes multiple transmission line segments arranged along the first direction, and the multiple transmission line segments in the same second line segment group are located on the same straight line.
  • the distances between every two adjacent second line segment groups are equal.
  • the display substrate further comprises:
  • a plurality of scanning lines, each row of pixel areas corresponds to one of the scanning lines;
  • a plurality of second shift register units located in the peripheral area, wherein an output end of each of the second shift register units is connected to one of the scan lines;
  • a power line wherein an orthographic projection of the power line on the base substrate overlaps with an orthographic projection of the second shift register unit on the base substrate.
  • the plurality of second shift register units are located on a side of the plurality of first shift register units close to the display area.
  • the display substrate further comprises:
  • a plurality of driving signal lines are used to provide signals for the plurality of first shift register units, and an orthographic projection of at least one of the plurality of driving signal lines on the substrate overlaps with an orthographic projection of the plurality of first shift register units on the substrate.
  • the orthographic projections of the driving signal line and the signal transmission line on the substrate have no overlap.
  • At least one of the driving signal lines is disposed on the same layer as the signal transmission line.
  • the display substrate further comprises:
  • each of the remaining first shift register units is also connected to the input end of the next first shift register unit through the connecting line;
  • a plurality of first adapters each of which corresponds to one of the signal transmission lines, one end of the first adapter is connected to the connection line through a first via hole, and the other end of the first adapter is connected to the signal transmission line through a second via hole.
  • the first shift register unit includes a plurality of transistors, and the orthographic projections of the first via hole and the second via hole on the base substrate do not overlap with the orthographic projections of the transistor on the base substrate.
  • a plurality of the first transition components are arranged along the first direction.
  • connection line is disposed in the same layer as the second reset line and is electrically connected to the second reset line.
  • the signal transmission line is located on a side of the layer where the first adapter is located away from the substrate.
  • the display substrate further comprises:
  • a second adapter wherein one end of the second adapter is connected to the signal transmission line through a third via hole, and the other end of the second adapter is connected to the first reset line through a fourth via hole;
  • the first shift register unit includes a plurality of transistors, and the orthographic projections of the third via hole and the fourth via hole on the base substrate do not overlap with the orthographic projections of the transistors on the base substrate.
  • the plurality of second transition components are arranged along the first direction.
  • An embodiment of the present disclosure further provides a display device, which includes the above-mentioned display substrate.
  • the embodiment of the present disclosure further provides a method for manufacturing a display substrate, wherein the display substrate has a display area and a peripheral area, wherein the display area includes N rows of pixel areas arranged along a first direction, wherein the manufacturing method includes:
  • N+M first shift register units are formed on the substrate at positions corresponding to the peripheral area; wherein the N+M first shift register units are arranged along the first direction, and the output end of the i-th first shift register unit is connected to the second reset line corresponding to the i-M-th row of pixel areas; the output end of the j-th first shift register is connected to the first reset line corresponding to the j-th row of pixel areas through a signal transmission line; N is an integer greater than 2, M is a preset positive integer, M+1 ⁇ i ⁇ N+M, 1 ⁇ j ⁇ N, and i and j are both integers;
  • the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of at least one of the first shift register units on the substrate.
  • the manufacturing method further comprises:
  • the plurality of drive signal lines being used to provide signals to the plurality of first shift register units, wherein an orthographic projection of at least one of the plurality of drive signal lines on the substrate overlaps with an orthographic projection of the plurality of first shift register units on the substrate;
  • At least one of the driving signal lines is formed synchronously with the signal transmission line.
  • FIG. 1 is a plan view of a display substrate provided in some embodiments.
  • FIG. 2 is a circuit schematic diagram of a pixel circuit and a light-emitting device provided in some embodiments.
  • FIG. 3 is a timing diagram of the pixel circuit in FIG. 2 .
  • FIG. 4 is a timing diagram of some signals of the pixel circuits in the nth row and the pixel circuits in the (n+1)th row.
  • FIG. 5 is a plan view of a display substrate provided in some embodiments of the present disclosure.
  • FIG6 is a schematic diagram of the correspondence between the first shift register unit, the second shift register unit, and N rows of pixel areas provided in some embodiments of the present disclosure.
  • FIG. 7 is a circuit schematic diagram of a first shift register unit provided in some embodiments of the present disclosure.
  • FIG. 8A is a partial schematic diagram of a display substrate provided in some embodiments of the present disclosure.
  • FIG8B is a partial schematic diagram of the area where the first-stage shift register unit is located provided in some embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of the semiconductor layer in FIG. 8A .
  • FIG. 10 is a schematic diagram of the first gate metal layer in FIG. 8A .
  • FIG. 11 is a schematic diagram of the second gate metal layer in FIG. 8A .
  • FIG. 12 is a schematic diagram of the first source-drain metal layer in FIG. 8A .
  • FIG. 13 is a schematic diagram of the second source-drain metal layer in FIG. 8A .
  • FIG. 14 is a schematic diagram of the via distribution in FIG. 8A .
  • FIG. 15 is a plan view of a first shift register unit and signal lines provided in some other embodiments of the present disclosure.
  • FIG. 16 is a partial schematic diagram of a peripheral area provided in some other embodiments of the present disclosure.
  • film layer in the embodiments of the present disclosure is schematically illustrated and does not represent the actual thickness of the film layer.
  • the "same-layer setting" in the embodiment of the present disclosure means that two or more structures are formed by the same material layer through a composition process, so the two or more structures are in the same layer in the stacking relationship; but this does not mean that the distance between the two or more structures and the substrate 100 must be the same.
  • each transistor involved in the embodiments of the present disclosure can be independently selected from one of a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor and an organic thin film transistor.
  • the "first pole” involved in the present disclosure specifically refers to the source of the transistor, and the corresponding “second pole” specifically refers to the drain of the transistor.
  • transistors are divided into N-type transistors and P-type transistors.
  • the working level signal in the embodiments of the present disclosure refers to a signal that can control the conduction of the transistor; the non-working level signal refers to a signal that can control the turn-off of the transistor.
  • its working level signal is a high-level signal
  • the non-working level signal is a low-level signal
  • the non-working level signal is a high-level signal
  • Figure 1 is a plan view of a display substrate provided in some embodiments.
  • the display substrate includes a display area AA and a peripheral area NA located around the display area AA.
  • the display area AA includes a plurality of pixel areas arranged in an array, each pixel area is provided with a light-emitting device 20, and a pixel circuit 10 for providing a driving current to the light-emitting device 20.
  • FIG2 is a circuit schematic diagram of a pixel circuit and a light-emitting device provided in some embodiments.
  • the pixel circuit 10 includes: a first reset transistor T1', a second reset transistor T7', a driving transistor T3', a data writing transistor T4', a first light-emitting control transistor T5', a second light-emitting control transistor T6', a compensation transistor T2' and a storage capacitor Cst.
  • the two ends of the storage capacitor Cst are respectively connected to the first power line VDD and the gate of the driving transistor T3'.
  • the gate of the first reset transistor T1' is connected to the first reset line RESET1, the first electrode of the first reset transistor T1' is connected to the gate of the driving transistor T3', and the second electrode of the first reset transistor T1' is connected to the first initialization signal line Vinit1.
  • the gate of the second reset transistor T7' is connected to the gate line, the first electrode of the second reset transistor T7' is connected to the first electrode of the light-emitting device 20, and the second electrode of the second reset transistor T7' is connected to the second initialization signal line Vinit2.
  • the gate of the data writing transistor T4' is connected to the scan line GL, the first electrode of the data writing transistor T4' is connected to the first electrode of the driving transistor T3', and the second electrode of the data writing transistor T4' is connected to the data line.
  • the gate of the compensation transistor T2’ is connected to the second reset line RESET2, the first electrode of the compensation transistor T2’ is connected to the gate of the driving transistor T3’, and the second electrode of the compensation transistor T2’ is connected to the second electrode of the driving transistor T3’.
  • the gate of the first light-emitting control transistor T5’ is connected to the light-emitting control line EM, the first electrode of the first light-emitting control transistor T5’ is connected to the first power line VDD, and the second electrode of the first light-emitting control transistor T5’ is connected to the first electrode of the driving transistor T3’.
  • the gate of the second light-emitting control transistor T6’ is connected to the light-emitting control line EM, the first electrode of the second light-emitting control transistor T6’ is connected to the second electrode of the driving transistor T3’, and the second electrode of the second light-emitting control transistor T6’ is connected to the first electrode of the light-emitting device 20.
  • the second electrode of the light-emitting device 20 is connected to the second power line VSS.
  • the first electrode of the light-emitting device 20 can be an anode
  • the second electrode can be a cathode.
  • the first reset transistor T1’ in the pixel circuit 10 located in the same row is connected to the same first reset line RESET1;
  • the compensation transistor T2’ in the pixel circuit 10 located in the same row is connected to the same second reset line RESET2;
  • the first light-emitting control transistor T5’ and the second light-emitting control transistor T6’ in the pixel circuit 10 located in the same row are connected to the same light-emitting control line EM;
  • the data writing transistor T4’ in the pixel circuit 10 located in the same row is connected to the same scanning line GL, and the data writing transistor T4’ in the pixel circuit 10 located in the same column is connected to the same data line DL.
  • each transistor in the pixel circuit 10 shown in FIG2 is a P-type transistor, and at this time, a low-level signal controls each transistor to turn on.
  • FIG3 is a timing diagram of the pixel circuit in FIG2.
  • the working process of the pixel circuit 10 includes: a reset stage t1, a data writing and compensation stage t2, and a light-emitting stage t3.
  • the first reset line RESET1 provides a low-level signal, thereby controlling the first reset transistor T1' to be turned on; then the second reset line RESET2 provides an effective level signal, thereby controlling the compensation transistor T2' to be turned on.
  • the scan line GL and the second reset line RESET2 provide a low-level signal, thereby controlling the data writing transistor T4' and the compensation transistor T2' to be turned on, and the data signal on the data line DL and the threshold voltage of the driving transistor T3' are written into the storage capacitor Cst.
  • the signal on the light-emitting control line EM is a low-level signal, thereby controlling the first light-emitting control transistor T5' and the second light-emitting control transistor T6' to be turned on, and the driving transistor T3' provides a driving current for the light-emitting device.
  • the time from the rising edge of the signal on the scanning line GL to the light-emitting stage t3 is the threshold compensation time.
  • the pixel circuit 10 in FIG. 2 is only for illustrative purposes. In other examples, the pixel circuit may also adopt other structures, for example, 8T1C.
  • the peripheral area NA is provided with a first driving circuit 30, a second driving circuit 40 and a third driving circuit 50, wherein the first driving circuit 30 includes a plurality of first shift register units GOA1 connected in cascade, the second driving circuit 40 includes a plurality of second shift register units GOA2 connected in cascade, and the third driving circuit 50 includes a plurality of third shift register units GOA3 connected in cascade.
  • Each third shift register unit GOA3 is connected to a light emitting control line EM
  • each second shift register unit GOA2 is connected to a scanning line GL
  • each first shift register unit GOA1 is connected to a first reset line RESET1 and a second reset line RESET2.
  • the display area AA includes N rows of pixel areas
  • the first driving circuit 30 includes cascaded N+M first shift register units GOA1, wherein the i-th first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the i-M-th row of pixel areas; the j-th first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the j-th row of pixel areas through the signal transmission line 60;
  • N is an integer greater than 2
  • M is a preset positive integer, M+1 ⁇ i ⁇ N+M, 1 ⁇ j ⁇ N, i and j are both integers.
  • the first first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the first row of pixel areas through the signal transmission line 60, and the second first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the second row of pixel areas through the signal transmission line 60;
  • the third first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the first row of pixel areas, and is connected to the first reset line RESET1 corresponding to the third row of pixel areas through the signal transmission line 60;
  • the fourth first shift register unit GOA1 is connected to the The second reset line RESET2 corresponding to the 2nd row of pixel areas is connected, and is connected to the first reset line RESET1 corresponding to the 4th row of pixel areas through the signal transmission line 60; by analogy, the 2481st first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the 2479th row of
  • first shift register unit GOA1 connected to the first reset line RESET1 (or the second reset line RESET2) in the present disclosure means that the output end of the first shift register unit GOA1 is connected to the first reset line RESET1 (or the second reset line RESET2).
  • nth row and nth number refer to the nth row and nth number arranged along the scanning direction.
  • the first reset lines RESET1 corresponding to different pixel regions are connected to different first shift register units GOA1
  • the second reset lines RESET2 corresponding to different pixel regions are connected to different first shift register units GOA1
  • this connection structure is referred to as a "one-drive-one” structure.
  • the two first reset lines RESET1 corresponding to every two rows of pixel regions are connected to the same first shift register unit GOA1
  • the two second reset lines RESET2 corresponding to every two rows of pixel regions are connected to the same first shift register unit GOA1
  • this connection structure is referred to as a "one-drive-two" structure.
  • each pixel group includes two rows of pixel areas, and the i-th first shift register unit GOA1 is connected to each second reset line RESET2 corresponding to the i-M-th pixel group; the j-th first shift register unit GOA1 is connected to each first reset line RESET1 corresponding to the j-th pixel group through the signal transmission line 60; N is an integer greater than 2, M is a preset positive integer, M+1 ⁇ i ⁇ N+M, 1 ⁇ j ⁇ N, i and j are both integers.
  • M can be set to an integer greater than 1, such as 7 or 8, so as to increase the threshold compensation time of each row of pixel circuits 10, thereby reducing the display difference of odd and even row pixel areas.
  • the signal transmission line 60 is arranged between the first drive circuit 30 and the display area AA, and the signal transmission line 60 has a certain width, and a certain gap needs to be left between different signal transmission lines 60. Therefore, when M is set to be larger, the setting of multiple signal transmission lines 60 will increase the border width of the display product, which is not conducive to the realization of a narrow border.
  • FIG5 is a plan view of a display substrate provided in some embodiments of the present disclosure.
  • the display substrate includes: a display area AA and a peripheral area NA, the display area AA includes N pixel groups arranged along a first direction, each pixel group includes at least one row of pixel areas, and each pixel area includes a plurality of pixel areas arranged along a second direction.
  • the display substrate includes a base substrate 100, and disposed on the base substrate 100: a plurality of first reset lines RESET1, a plurality of second reset lines RESET2, and N+M first shift register units GOA1.
  • first reset line RESET1 and the second reset line RESET2 are located in the display area, and each row of pixel areas corresponds to a first reset line RESET1 and a second reset line RESET2.
  • the first shift register unit GOA1 is located in the peripheral area NA, and N+M first shift register units GOA1 are arranged along the first direction, wherein the output end of the i-th first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the i-M-th pixel group; the output end of the j-th first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the j-th pixel group through the signal transmission line 60; N is an integer greater than 2, M is a preset positive integer, M+1 ⁇ i ⁇ N+M, 2 ⁇ M, 1 ⁇ j ⁇ N, and i and j are both integers.
  • the output end of the first shift register unit GOA1 is connected to the first reset line RESET1 (or the second reset line RESET2) corresponding to a certain pixel group, which means that the output end of the first shift register unit GOA1 is connected to the first reset line RESET1 (or the second reset line RESET2) corresponding to each row of pixel areas in the pixel area.
  • Each pixel group may include a row of pixel areas to implement the "one-drive-one" structure described above.
  • each pixel group may include two rows of pixel areas to implement the "one-drive-two" structure described above.
  • each pixel area may also include other numbers.
  • each pixel group includes a row of pixel areas as an example for description.
  • the first first shift register unit GOA1_1 is connected to the first reset line RESET1 corresponding to the first row of pixel areas through the signal transmission line 60; the second first shift register unit GOA1_2 is connected to the first reset line RESET1 corresponding to the second row of pixel areas through the signal transmission line 60; and so on, the eighth first shift register unit GOA1 is connected to the first reset line RESET1 corresponding to the eighth row of pixel areas through the signal transmission line 60.
  • the 9th first shift register unit GOA1_9 is connected to the second reset line RESET2 corresponding to the 1st row of pixel areas, and is connected to the first reset line RESET1 corresponding to the 9th row of pixel areas through the signal transmission line 60;
  • the 10th first shift register unit GOA1_10 is connected to the second reset line RESET2 corresponding to the 2nd row of pixel areas, and is connected to the first reset line RESET1 corresponding to the 10th row of pixel areas through the signal transmission line 60;
  • the 2480th first shift register unit GOA1 is connected to the second reset line RESET2 corresponding to the 2472nd row of pixel areas, and is connected to the first reset line RESET1 corresponding to the 2480th row of pixel areas through the signal transmission line 60;
  • the 2481st to 2488th first shift register units GOA1 are respectively connected to the second reset lines RESET2 corresponding to the 2473rd to 2480th rows of pixel areas.
  • the orthographic projection of the signal transmission line 60 on the base substrate 100 overlaps with the orthographic projection of at least one first shift register unit GOA1 on the base substrate 100.
  • the signal transmission line 60 will not occupy the space between the first shift register unit GOA1 and the display area, thereby reducing the border width of the display substrate, which is conducive to the realization of a narrow border.
  • the signal transmission line 60 may be located on the side of the first shift register unit GOA1 away from the substrate 100, or between the first shift register unit GOA1 and the substrate 100. In the following embodiments, the signal transmission line 60 is located on the side of the first shift register unit GOA1 away from the substrate.
  • Figure 7 is a circuit schematic diagram of the first shift register unit provided in some embodiments of the present disclosure.
  • the first shift register unit GOA1 includes: an input sub-circuit ISC, an output sub-circuit OSC, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, a third processing sub-circuit PSC3, a first voltage stabilizing sub-circuit SSC1, and a second voltage stabilizing sub-circuit SSC2.
  • the output sub-circuit OSC is configured to provide the voltage of the third power line VGH or the fourth power line VGL to the output terminal OUT in response to the voltage of the fourth node N4 and the first node N1.
  • the output sub-circuit OSC includes two output transistors, namely a ninth transistor T9 and a tenth transistor T10.
  • the ninth transistor T9 is connected between the third power line VGH and the output terminal OUT.
  • the gate of the ninth transistor T9 is connected to the fourth node N4.
  • the ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. When the ninth transistor T9 is turned on, the voltage of the third power line VGH is provided to the output terminal OUT.
  • the tenth transistor T10 is connected between the output terminal OUT and the fourth power line VGL.
  • the gate of the tenth transistor T10 is connected to the first node N1.
  • the tenth transistor T10 can be turned on or off according to the voltage of the first node N1. When the tenth transistor T10 is turned on, the voltage of the fourth power line VGL is provided to the output terminal OUT.
  • the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals provided to the first input terminal IN and the first clock signal terminal CK, respectively.
  • the input sub-circuit ISC includes a first transistor T1. The gate of the first transistor T1 is connected to the first clock signal terminal CK, the first electrode of the first transistor T1 serves as the first input terminal IN, and the second electrode of the first transistor T1 is connected to the first node N1.
  • the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1.
  • the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.
  • the eighth transistor T8 is connected between the third power line VGH and the fourth node N4.
  • the gate of the eighth transistor T8 is connected to the first node N1.
  • the second capacitor C2 is connected between the third power line VGH and the fourth node N4.
  • the second capacitor C2 is configured to charge the voltage applied to the fourth node N4.
  • the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.
  • the second processing sub-circuit PSC2 is connected to the fifth node N5 and is configured to control the voltage of the fourth node N4 in response to the signal input to the third input terminal TM3.
  • the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7 and a first capacitor C1.
  • the first end of the first capacitor C1 is connected to the fifth node N5, the second end of the first capacitor C1 is connected to the third node N3, and the third node N3 is a common node between the sixth transistor T6 and the seventh transistor T7.
  • the sixth transistor T6 is connected between the third node N3 and the fifth node N5.
  • the gate of the sixth transistor T6 is connected to the fifth node N5.
  • the seventh transistor T7 is connected between the fourth node N4 and the third node N3.
  • the gate of the seventh transistor T7 is connected to the second clock signal terminal CB.
  • the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2.
  • the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a third capacitor C3.
  • the fifth transistor T5 is connected between the third power line VGH and the fourth transistor T4.
  • the gate of the fifth transistor T5 is connected to the second node N2.
  • the fourth transistor T4 is connected between the fifth transistor T5 and the second clock signal terminal CB.
  • the gate of the fourth transistor T4 is connected to the gate of the tenth transistor T10.
  • the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.
  • the second transistor T2 is connected between the second node N2 and the first clock signal terminal CK, and the gate of the second transistor T2 is connected to the first node N1.
  • the third transistor T3 is connected between the second node N2 and the fourth power line VGL, and the gate of the third transistor T3 is connected to the first clock signal terminal CK.
  • the third capacitor C3 is connected between the tenth transistor T10 and the fifth transistor T5.
  • the second plate of the third capacitor C3 is connected to the second electrode of the fifth transistor T5 and the first electrode of the fourth transistor T4.
  • a first plate of the third capacitor C3 is connected to the gate of the fourth transistor T4 and the gate of the tenth transistor T10.
  • the third processing subcircuit PSC3 is configured to control the voltage of the second node N2, wherein the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and the gate of the fourth transistor T4 is connected to the first node N1.
  • the first voltage stabilizing sub-circuit SSC1 includes an eleventh transistor T11.
  • the eleventh transistor T11 is connected between the second node N2 and the fifth node N5, and the gate of the eleventh transistor T11 is connected to the fourth power line VGL. Since the voltage provided by the fourth power line VGL is the working level voltage of the eleventh transistor T11, the eleventh transistor T11 can always remain turned on. Therefore, the second node N2 and the fifth node N5 can be maintained at the same voltage and operate substantially as the same node.
  • the second voltage stabilizing subcircuit SSC2 is connected between the first node N1 and the output subcircuit OSC.
  • the second voltage stabilizing subcircuit SSC2 is configured to limit the voltage drop width of the first node N1.
  • the second voltage stabilizing subcircuit SSC2 includes a twelfth transistor T12.
  • the twelfth transistor T12 is connected between the first node N1 and the gate of the tenth transistor T10.
  • the gate of the twelfth transistor T12 is connected to the fourth power line VGL, and the twelfth transistor T12 can always remain turned on. Therefore, the first node N1 and the gate of the tenth transistor T10 can be maintained at the same voltage.
  • each of the first to twelfth transistors T1 to T12 may be formed of a p-type transistor.
  • the operating level voltage of the first to twelfth transistors T1 to T12 may be set to a low level voltage, and the non-operating level voltage may be set to a high level voltage.
  • FIG8A is a partial schematic diagram of a display substrate provided in some embodiments of the present disclosure
  • FIG8A shows two first shift register units GOA1 and a plurality of signal transmission lines 60 and a plurality of drive signal lines in the region where the two first shift register units GOA1 are located, and the drive signal lines are used to provide drive signals for the first shift register unit GOA1, for example, the plurality of drive signal lines include: a third power line, a fourth power line, a first clock signal line, a second clock signal line, and a frame start signal line.
  • at least one drive signal line can be arranged in the same layer as the signal transmission line 60, and FIG8A to FIG14 are illustrated by taking the third power line and the signal transmission line 60 as an example.
  • FIG9 is a schematic diagram of the semiconductor layer in FIG8A
  • FIG10 is a schematic diagram of the first gate metal layer in FIG8A
  • FIG11 is a schematic diagram of the second gate metal layer in FIG8A
  • FIG12 is a schematic diagram of the first source and drain metal layer in FIG8A
  • FIG13 is a schematic diagram of the second source and drain metal layer in FIG8A
  • FIG14 is a schematic diagram of the via distribution in FIG8A.
  • the semiconductor layer Poly includes: active layers T1_a ⁇ T12a and doping region patterns of each transistor T1 ⁇ 12, and the active layer and doping region pattern of each transistor in the same first pixel circuit are integrally arranged.
  • both sides of the active layer of the transistor are provided with doping region patterns, and the doping region patterns on both sides of the active layer can be used as the first pole and the second pole of the transistor respectively.
  • the active layer T9_a of the ninth transistor T9 and the active layer T10_a of the tenth transistor T10 are arranged along the first direction.
  • the semiconductor layer Poly can be formed by patterning a semiconductor material, and the semiconductor material can be an oxide semiconductor material, such as IGZO.
  • the first gate metal layer G1 is disposed on a side of the semiconductor layer away from the substrate 100, and the first gate metal layer G1 may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.
  • the first gate metal layer may include gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloy, titanium (Ti), titanium nitride (TiN x), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnO
  • the first gate metal layer G1 includes: gates T1_g to T12_g of each transistor T1 to T12, a first plate of a first capacitor C1, a first plate of a second capacitor C2, and a first plate of a third capacitor C3.
  • the gate of the fourth transistor T3 and the first plate C31 of the third capacitor C3 can be connected as an integrated structure.
  • the gate T1_g of the first transistor T1 and the gate T3_g of the third transistor T3 can be connected as an integrated structure.
  • the gate T2_g of the second transistor T2 and the gate T8_g of the eighth transistor T8 can be connected as an integrated structure.
  • the gate T6_g of the sixth transistor T6 and the first plate C11 of the first capacitor C1 form an integrated structure.
  • the second gate metal layer G2 is disposed on a side of the first gate metal layer away from the base substrate 100, and the material of the second gate metal layer G2 can be selected from the materials of the first gate metal layer listed above.
  • the second gate metal layer G2 includes: a connecting line 70, a second plate C12 of the first capacitor C1, a second plate C22 of the second capacitor C2, and a second plate C32 of the third capacitor C3.
  • Each connecting line 70 corresponds to a first shift register unit GOA1, and the first shift register unit GOA1 is connected to the corresponding second reset line RESET2 through the corresponding connecting line 70.
  • each of the remaining first shift register units GOA1 is also connected to the input end of the next-stage first shift register unit GOA1 through a corresponding connecting line 70.
  • the input end of each first shift register unit GOA1 can be the first pole of the first transistor T1, and one end of the connecting line is connected to the first pole of the first transistor T1 through a via.
  • the connecting line 70 includes a first part 71 extending along the first direction and a second part 72 extending along the second direction, one end of the second part 72 is connected to the first pole of the first transistor T1 through a via, the other end of the second part 72 is connected to one end of the second part 72, and the other end of the first part 71 is connected to the corresponding second reset line RESET2.
  • the first part 71 and the second reset line RESET2 can be arranged in the same layer and electrically connected.
  • the "electrical connection" in the embodiment of the present disclosure can be a direct connection or an indirect connection.
  • the second gate metal layer G2 further includes a clock signal transfer line 80 of each stage of the first shift register unit GOA1.
  • the first source-drain metal layer SD1 is located on the side of the second gate metal layer G2 away from the substrate 100.
  • the first source-drain metal layer SD1 includes: a plurality of adapters, and a fourth power line VGL, a first clock signal line CKL, a second clock signal line CBL, and a frame start signal line STV.
  • the fourth power line VGL, the first clock signal line CKL, the second clock signal line CBL, and the frame start signal line STV all extend along the first direction.
  • the plurality of adapters include: a first adapter E1 to a sixteenth adapter E16.
  • each first adapter E1 corresponds to a first shift register unit GOA1. As shown in FIG8A, FIG12, and FIG14, one end of each first adapter E1 is connected to the connecting line 70 through the first via V1, and the other end is connected to the signal transmission line 60 through the second via V2. In some examples, multiple first adapters E1 are arranged along the first direction.
  • each second adapter E2 corresponds to a first shift register unit GOA1
  • one end of each second adapter E2 is connected to the signal transmission line 60 through the third via V3, and the other end is connected to the first reset line RESET1 through the fourth via V4.
  • multiple second adapters E2 can be arranged along the first direction.
  • the orthographic projections of the first via V1 , the second via V2 , the third via V3 and the fourth via V4 on the base substrate 100 do not overlap with the orthographic projections of each transistor on the base substrate 100 to prevent the transistors from being affected during the via manufacturing process.
  • the third adapter E3 is connected to the second electrode of the tenth transistor T10 through the fifth via V5, and is connected to the second electrode of the ninth transistor T9 through the sixth via V6; in addition, the third connector E3 is also connected to the second portion 72 of the connecting line 70 through the seventh via V7, and the second electrode of the ninth transistor T9, the second electrode of the tenth transistor T10, the third adapter E3 and the connecting node between the connecting line 70 can serve as the output end of the first shift register unit GOA1.
  • the fourth adapter E4 is connected to the first electrode of the tenth transistor T10 through the eighth via V8, to the gate of the twelfth transistor T12 through the ninth via V9, and to the first electrode of the third transistor T3 through the tenth via V10.
  • the gate of the twelfth transistor T12 is connected to the fourth power line VGL.
  • the fifth adapter E5 is connected to the first electrode of the ninth transistor T9 through the eleventh via hole V11, connected to the second electrode plate C22 of the second capacitor C2 through the twenty-seventh via hole V27, and connected to the first electrode of the fifth transistor T5 through the twelfth via hole V12.
  • the sixth adapter E6 is connected to the first electrode C21 of the second capacitor C2 through the thirteenth via V13, and is connected to the first electrode of the eighth transistor T8 through the fourteenth via V14.
  • the seventh connector E7 is connected to the second electrode of the fourth transistor T4 through the fifteenth via V15, is connected to the gate of the seventh transistor T7 through the sixteenth via V16, is connected to the first electrode of the sixth transistor T6 through the forty-fifth via V45, and is connected to the clock signal adapter line 80 through the forty-second via V42.
  • the eighth adapter E8 is connected to the gate of the fourth transistor T4 through the seventeenth via hole V17 , and is connected to the second electrode of the twelfth transistor T12 through the eighteenth via hole V18 .
  • the ninth adapter E9 is connected to the first electrode of the seventh transistor T7 through the nineteenth via hole V19, connected to the second electrode of the sixth transistor T6 through the twentieth via hole V20, and connected to the second electrode plate C12 of the first capacitor C1 through the twenty-first via hole V21.
  • the number of the twenty-first via hole V21 can be one or more, for example, there are two twenty-first via holes V21 to improve the connection stability.
  • the tenth adapter E10 is connected to the second electrode C32 of the third capacitor C3 through the twenty-second via V22, connected to the second electrode of the fourth transistor T4 through the twenty-third via V23, and connected to the second electrode of the fifth transistor T5 through the twenty-fourth via V24.
  • the eleventh adapter E11 is connected to the first electrode of the twelfth transistor T12 through the twenty-fifth via hole V25 , and is connected to the gate of the eighth transistor T8 through the twenty-sixth via hole V26 .
  • the twelfth adapter E12 is connected to the second electrode of the third transistor T3 through the twenty-eighth via hole V28 , is connected to the gate of the fifth transistor T5 through the twenty-ninth via hole V29 , and is connected to the first electrode of the eleventh transistor T11 through the thirtieth via hole V30 .
  • the thirteenth adapter E13 is connected to the gate of the third transistor T3 through the thirty-first via hole V31 , and is connected to the second electrode of the second transistor T2 through the thirty-second via hole V32 .
  • the fourteenth adapter E14 is connected to the gate electrode of the second transistor T2 through the thirty-third via hole V33 , and is connected to the second electrode of the first transistor T1 through the thirty-fourth via hole V34 .
  • the fifteenth adapter E15 is connected to the first electrode of the first transistor T1 through the thirty-fifth via V35.
  • each level of the first shift register unit GOA1 corresponds to a fifteenth adapter E15, and the fifteenth adapter E15 corresponding to the first shift register unit GOA1 of the first level can be connected to the frame start signal line STV; except for the first level, the fifteenth adapters E15 corresponding to the remaining first shift register units GOA1 are also connected to the connecting line 70 corresponding to the first shift register unit GOA1 of the previous level through the thirty-sixth via V36.
  • the sixteenth adapter E16 is connected to the second electrode of the eleventh transistor T11 through the thirty-seventh via hole V37 , and is connected to the gate of the sixth transistor T6 through the thirty-eighth via hole V38 .
  • the first clock signal line CKL is connected to the gate of the third transistor T3 in the odd-numbered first shift register unit GOA1 through a via V48, and is connected to the clock signal adapter line 80 in the even-numbered first shift register unit GOA1 through a via V49.
  • the second clock signal line CBL is connected to the gate of the third transistor T3 in the even-numbered first shift register unit GOA1 through a via V50, and is connected to the clock signal adapter line 80 in the odd-numbered first shift register unit GOA1 through a via V51.
  • the clock signal adapter line 80 of each first shift register unit GOA1 is used to connect the seventh adapter E7.
  • the number of vias V48 to V50 can be one or more, for example, there are two vias V48 to V50, so as to improve the connection stability.
  • the fourth power line VGL is connected to the gate of the twelfth transistor T12 through the 40th via hole V40, and is connected to the gate of the eleventh transistor T11 through the 41st via hole V41.
  • the number of the 40th via hole V40 and the 41st via hole V41 can be one or more, for example, the number of the 40th via hole V40 and the 41st via hole V41 are both two, so as to improve the connection stability.
  • the first clock signal line CKL is located on the side of the fourth power line VGL away from the display area
  • the second clock signal line CBL is located on the side of the first clock signal line CKL away from the display area
  • the frame start signal line STV is located on the side of the second clock signal line CBL away from the display area.
  • the orthographic projections of the first clock signal line CLK, the second clock signal line CBL, the frame start signal line STV, and the fourth power line VGL on the base substrate 100 do not overlap with the orthographic projections of the active layers of each transistor in the first shift register unit GOA1 on the base substrate 100 .
  • the second source-drain metal layer SD2 includes: a plurality of signal transmission lines 60 and a third power line VGH.
  • the third power line VGH extends along the first direction.
  • the orthographic projection of the third power line VGH on the substrate 100 may overlap with the orthographic projection of the third capacitor C3, the fourth transistor T4, and the eighth transistor T8 on the substrate 100.
  • the third power line VGH may be connected to the fifth adapter E5 through the thirty-ninth via V39.
  • each fifth adapter E5 may be connected to the third power line VGH through a plurality of thirty-ninth vias V39.
  • FIG8B is a partial schematic diagram of the area where the first-stage shift register unit is provided in some embodiments of the present disclosure, and FIG8B shows a partial structure in the first-stage shift register unit, as well as the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, the third power line VGH and the fourth power line VGL.
  • each first-stage shift register unit GOA corresponds to a fifteenth adapter E15, and the fifteenth adapter E15 is connected to the first electrode of the first transistor T1 through the thirty-fifth via V35.
  • the E15 corresponding to the first-stage shift register unit GOA is also connected to one end of the frame start signal adapter line 90 through the via, and the other end of the frame start signal adapter line 90 is connected to the frame start signal line STV through the via.
  • the frame start signal adapter line 90 is located in the second gate metal layer G2, and of course, it can also be located in the first gate metal layer G1.
  • the signal transmission line 60 has a head end and a tail end, and the head end of the signal transmission line 60 is connected to the first adapter E1 through the second via V2, thereby connecting to the output end of the first shift register unit GOA1 through the first adapter E1.
  • the tail end of the signal transmission line 60 is connected to the second adapter E2 through the fourth via V4, thereby connecting to the second reset line RESET2 through the second adapter E2.
  • the orthographic projection of the signal transmission line 60 on the substrate substrate 100 overlaps with the orthographic projection of at least one output transistor of at least one first shift register unit GOA1 on the substrate substrate 100. For example, in the first shift register unit GOA1 shown in FIG.
  • each signal transmission line 60 can overlap with the orthographic projection of the ninth transistor T9 and the tenth transistor T10 of at least one first shift register unit GOA1.
  • the orthographic projection of each signal transmission line 60 on the substrate 100 overlaps with the orthographic projection of the M-1 first shift register units GOA1 on the substrate 100.
  • the orthographic projection of each signal transmission line 60 on the substrate 100 overlaps with the orthographic projection of the ninth transistor T9 and the tenth transistor T10 of the M-1 first shift register units GOA1 on the substrate 100.
  • the orthographic projection of the signal transmission line 60 on the substrate substrate 100 does not overlap with the orthographic projection of the storage capacitor (such as the first capacitor C1, the second capacitor C2 and the third capacitor C3 mentioned above) on the substrate substrate 100, so as to prevent parasitic capacitance from being generated between the signal transmission line 60 and the storage capacitor, thereby preventing signal interference between the storage capacitor and the signal transmission line 60.
  • the storage capacitor such as the first capacitor C1, the second capacitor C2 and the third capacitor C3 mentioned above
  • the signal transmission line 60 is a bending structure, which includes a plurality of transmission line segments 61 and a connecting line segment 62 located between two adjacent transmission line segments 61, and the transmission line segment 61 extends along a first direction.
  • the signal transmission line 60 has a head end and a tail end, the head end is connected to the output end of the first shift register unit GOA1, and the tail end is connected to the first reset line RESET1.
  • the signal transmission line 60 is located on the side of the third power line VGH close to the display area (for FIG. 13 , the display area is located on the left side of the signal transmission line 60).
  • the distance from the transmission line segment 61 close to the head end to the display area is greater than the distance from the transmission line segment 61 far from the head end to the display area.
  • the orthographic projection of the signal transmission line 60 on the substrate substrate 100 is located between the display area and the orthographic projection of the storage capacitor on the substrate substrate 100. From the head end to the tail end of the signal transmission line 60, the signal transmission line 60 is bent multiple times in the direction close to the display area, which is conducive to reducing the width of the area occupied by multiple signal transmission lines 60.
  • the connecting line segment 62 is a straight line segment, and an obtuse angle is formed between the connecting line segment 62 and the adjacent transmission line segment 61, and the obtuse angle may be between 95° and 160°, for example, 95°, 100°, 120°, 145°, 150°, or 160°.
  • the connecting line segment 62 may also be an arc segment, so as to form a rounded structure with the adjacent transmission line segment 61.
  • the connecting line segments 62 in the signal transmission line 60 connected to the multiple first shift register units GOA1 are divided into multiple first line segment groups 62g, and the multiple first line segment groups 62g are arranged along the first direction, and at least part of the first line segment groups 62g include M-1 connecting line segments 62.
  • the center connecting line of the M-1 connecting line segments 62 is a straight line, and the extension direction of the center connecting line intersects both the first direction and the second direction.
  • the center connecting lines of the M-1 connecting line segments 62 may not be on the same straight line.
  • the center line of the M-1 connecting line segments 62 is a straight line, and the center line and the connecting line segments 62 are inclined in different directions.
  • the center line of the M-1 connecting line segments 62 is inclined in a " ⁇ " manner, and the connecting line segments 62 are inclined in a "/" manner.
  • the lengths of the connecting line segments 62 are the same, or at least two connecting line segments 62 have different lengths.
  • the connecting line segments 62 of the corresponding areas of two adjacent first shift register units are tilted in different ways.
  • the signal transmission line 60 of the output end corresponding area of the first first shift register unit GOA1_1 has the connecting line segment 62 of the signal transmission line 60 tilted in a “ ⁇ ” manner
  • the signal transmission line 60 of the output end corresponding area of the second first shift register unit GOA1_2 has the connecting line segment 62 of the signal transmission line 60 tilted in a “/” manner.
  • the orthographic projection of at least one connecting line segment 62 on the substrate 100 overlaps with the orthographic projection of the tenth transistor T10 on the substrate 100 .
  • the transmission line segments 61 in the signal transmission line 60 connected to the multiple first shift register units GOA1 are divided into multiple second line segment groups 61g, and the multiple second line segment groups 61g are arranged along the second direction.
  • Each second line segment group 61g includes multiple transmission line segments 61 arranged along the first direction, and the multiple transmission line segments 61 in the same second line segment group 61g are located on the same straight line.
  • the transmission line segments 61 in the signal transmission line 60 connected to the multiple first shift register units GOA1 are divided into multiple second line segment groups 61g, and the multiple second line segment groups 61g are arranged along the second direction.
  • Each second line segment group 61g includes multiple transmission line segments 61 arranged along the first direction, and the multiple transmission line segments 61 in the same second line segment group are located on the same straight line, so that the width of the area occupied by the multiple signal transmission lines 60 as a whole is smaller.
  • each of the transmission line segments 61 in the second line segment group 61g is connected to a different shift register unit.
  • the distance between every two adjacent second line segment groups 61g is equal.
  • the width of the transmission line segment 61 and the connecting line segment 62 may be substantially the same, and "substantially the same" in the embodiment of the present disclosure means that the difference between the two values is less than 10%, or 5%, or is completely equal.
  • the distance between two adjacent second line segment groups 61g may be less than 1.5 times the width of the transmission line segment 61.
  • the width of the transmission line segment 61 and the distance between two adjacent second line segment groups 61g are both less than or equal to 10 ⁇ m.
  • the width of the transmission line segment 61 and the distance between two adjacent second line segment groups 61g are both 3 ⁇ m, or 5 ⁇ m, or 7 ⁇ m, or 9 ⁇ m, or 10 ⁇ m.
  • the orthographic projections of the drive signal line and the signal transmission line 60 on the substrate 100 do not overlap.
  • the orthographic projections of the drive signal lines such as the fourth power line VGL, the first clock signal line CK, and the second clock signal line CB on the substrate 100 do not overlap with the orthographic projections of the active layers of the transistors in the first shift register unit GOA1 on the substrate 100.
  • the orthographic projection of at least one drive signal line on the substrate 100 overlaps with the active layer of the transistor in the first shift register unit GOA1.
  • the drive signal line that overlaps with the active layer of the transistor in the first shift register unit GOA1 is arranged in the same layer as the signal transmission line 60, and is located in the second source-drain metal layer SD2.
  • FIG15 is a plan view of the first shift register unit and signal lines provided in some other embodiments of the present disclosure.
  • the orthographic projections of the first clock signal line CKL, the second clock signal line CBL and the frame start signal line STV on the substrate 100 overlap with the orthographic projections of the active layers of the transistors in the first shift register unit GOA1 on the substrate 100.
  • the orthographic projection of the first clock signal line CKL on the substrate 100 overlaps with the orthographic projections of the active layers of the second transistor T2 and the third transistor T3 on the substrate 100.
  • the orthographic projection of the second clock signal line CBL on the substrate 100 overlaps with the orthographic projection of the active layer of the first transistor T1 on the substrate 100.
  • the orthographic projections of the driving signal line and the signal transmission line 60 on the substrate 100 also do not overlap.
  • the fourth power line VGL is located in the first source-drain metal layer.
  • the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, and the third power line VGH are all arranged in the same layer as the signal transmission line 60, and are all located in the second source-drain metal layer.
  • the orthographic projection of the frame start signal line STV on the substrate can overlap with the orthographic projection of the fourth power line VGL on the substrate.
  • the first clock signal line CKL is located on the side of the third power line VGH away from the display area
  • the second clock signal line CBL is located on the side of the first clock signal line CKL away from the display area
  • the frame start signal line STV is located on the side of the second clock signal line CBL away from the display area.
  • FIG. 15 is an example of the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, and the third power line VGH being arranged in the same layer.
  • the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, and the third power line VGH may also be arranged in different layers, for example, in two layers or multiple layers.
  • the signal transmission line 60 and any one of the drive signal lines may also be arranged in different layers.
  • the third power line is arranged in the first source-drain metal layer
  • the signal transmission line 60 is arranged in the second source-drain metal layer
  • the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV, and the third power line VGH are arranged on the side of the second source-drain metal layer away from the base substrate 100.
  • the first clock signal line CKL when the first clock signal line CKL, the second clock signal line CBL, the frame start signal line STV and the third power line VGH are arranged in the same layer, the first clock signal line CKL is connected to the thirteenth adapter E13 of the odd-numbered first shift register unit GOA1 through the forty-third via V43, and the second clock signal line is connected to the thirteenth adapter E13 of the even-numbered first shift register unit GOA1 through the forty-fourth via V44.
  • the first clock signal line CKL is directly connected to the seventh adapter E7 of the odd-numbered first shift register unit GOA1 through the via
  • the second clock signal line CBL is directly connected to the seventh adapter E7 of the even-numbered first shift register unit GOA1 through the via.
  • the frame start signal line STV when the frame start signal line STV is located in the second source-drain metal layer, the frame start signal line STV may overlap with the first electrode of the first transistor T1 in the first-stage first shift register unit GOA in a positive projection. At this time, the frame start signal STV may be directly connected to the first electrode of the first transistor T1 in the first-stage shift register unit GOA through a via without setting the frame start signal adapter line 90 in FIG. 8B .
  • the display substrate also includes a plurality of insulating layers arranged on the base substrate 100, and the plurality of insulating layers include, for example: a first gate insulating layer, a second gate insulating layer, an interlayer dielectric layer, and a passivation layer.
  • the first gate insulating layer is arranged between the semiconductor layer Poly and the first gate metal layer G1
  • the second gate insulating layer is arranged between the first gate metal layer and the second gate metal layer
  • the interlayer dielectric layer is arranged between the second gate metal layer and the first source-drain metal layer
  • the passivation layer is arranged between the first source-drain metal layer and the second source-drain metal layer.
  • the via passes through the insulating layer between the two conductive structures.
  • each transistor in the first shift register unit and each transistor in the pixel circuit can be arranged in the same layer, for example, the gate of each transistor in the first shift register unit and the gate of each transistor in the pixel circuit are arranged in the same layer, and the active layer of each transistor in the first shift register unit and the active layer of each transistor in the pixel circuit are arranged in the same layer.
  • a planarization layer can be further arranged on the side of the second source-drain metal layer SD2 away from the base substrate 100, and the light-emitting device in the display area is arranged on the side of the planarization layer away from the base substrate.
  • the materials of the first gate insulating layer, the second gate insulating layer, the interlayer dielectric layer and the passivation layer can be selected from silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc.
  • the first gate insulating layer, the second gate insulating layer, the interlayer dielectric layer and the passivation layer can be formed as a single layer or multiple layers.
  • the material of the planarization layer may include an organic material.
  • FIG16 is a partial schematic diagram of the peripheral area provided in some other embodiments of the present disclosure.
  • the display substrate further includes: a plurality of scan lines GL and a second drive circuit 40 arranged on the base substrate 100, at least a portion of the scan lines GL is located in the display area AA, the second drive circuit 40 is located in the peripheral area NA, and each row of pixel areas corresponds to a scan line GL.
  • the second drive circuit 40 includes a plurality of cascaded second shift register units GOA2, and the output end of each second shift register unit GOA2 is connected to a scan line GL for providing a scan signal for the scan line GL.
  • the second drive circuit 40 can be located on the side of the first drive circuit 30 close to the display area AA.
  • the second driving circuit 40 can be arranged on one side of the display area AA, or the second driving circuit 40 can be arranged on both opposite sides of the display area AA.
  • the structure of the second shift register unit GOA2 is similar to that of the first shift register unit GOA1, and both include multiple transistors and storage capacitors.
  • the first driving circuit 30 is located on the side of the second driving circuit 40 away from the display area AA.
  • the first driving circuit 30 can also be located on the side of the second driving circuit 40 close to the display area AA.
  • the display substrate further includes a second power line VSS, which is used to provide an electrical signal to the second electrode of the light emitting device 20 in the display area AA.
  • the orthographic projection of the second power line VSS on the base substrate 100 overlaps with the orthographic projection of the second shift register unit GOA2 on the base substrate 100, thereby reducing the border width on both sides of the display area AA.
  • the second power line VSS has a plurality of hollow portions Va to reduce the parasitic capacitance between the second power line VSS and the conductive structure in the second shift register unit GOA2.
  • the conductive structure in the second shift register unit GOA2 may include a first electrode, a second electrode, a gate electrode, and two plates of a storage capacitor of each transistor in the second shift register unit GOA2.
  • the shape of the hollow portion Va is not limited, for example, it may be rectangular, circular, triangular, elliptical or other shapes.
  • the second power line VSS can be arranged on the same layer as the signal transmission line 60, so that the second power line VSS and the signal transmission line 60 can be manufactured synchronously, simplifying the manufacturing process.
  • the first clock signal line CKL, the second clock signal line CBL, and the frame start signal line STV are also arranged on the same layer as the signal transmission line 60, further simplifying the manufacturing process.
  • the second power line VSS and the signal transmission line 60 may also be located at a different layer.
  • the second power line VSS is located at a side of the layer where the signal transmission line 60 is located away from the base substrate 100 .
  • the second power line VSS is located on a side of the layer where the signal transmission line 60 is located away from the base substrate 100, and the second power line VSS at least partially overlaps the signal transmission line 60.
  • the second power line VSS is made of the same conductive layer as the first electrode (e.g., anode) of the light-emitting device 20 in the display area AA.
  • the display substrate further includes a first signal transfer line 81 , a second signal transfer line 82 , a third signal transfer line 83 , and a fourth signal transfer line 84 disposed in the peripheral area.
  • the signal transmission line 60 can be connected to the first end of the first signal transfer line 81, the second end of the first signal transfer line 81 is connected to the first end of the second signal transfer line 82, and the second end of the second signal transfer line 82 is connected to the first reset line RESET1.
  • the connection line connected to the ninth transistor T9 and the tenth transistor T10 can be connected to the first end of the third signal transfer line 83, the second end of the third signal transfer line 83 is connected to the first end of the fourth signal transfer line 84, and the second end of the fourth signal transfer line 84 is connected to the second reset line RESET2.
  • the output end of the second shift register unit is connected to the first end of the fifth signal transfer line 85, the second end of the fifth signal transfer line 85 is connected to the first end of the sixth signal transfer line 86, and the second end of the sixth signal transfer line 86 is connected to the scan line.
  • the first reset line RESET1 and the second reset line RESET2 can be located in the first gate metal layer
  • the first signal transfer line 81, the third signal transfer line 83, and the fifth signal transfer line 85 can be located in the second gate metal layer
  • the second signal transfer line 82, the fourth signal transfer line 84 and the sixth signal transfer line 86 can be located in the first source and drain metal layer.
  • the display substrate further includes a third driving circuit 50 and a plurality of light-emitting control lines EM
  • the third driving circuit 50 is arranged in the peripheral area NA, and includes a plurality of cascaded third shift register units GOA3. At least a portion of the light-emitting control lines EM are arranged in the display area AA, and each third shift register unit GOA3 is connected to one light-emitting control line EM.
  • the present disclosure also provides a method for manufacturing the above-mentioned display substrate, wherein the display substrate has a display area and a peripheral area, wherein the display area includes N rows of pixel areas arranged along a first direction.
  • the method for manufacturing the display substrate includes:
  • N+M first shift register units at positions corresponding to the peripheral area on the substrate; wherein the N+M first shift register units are arranged along the first direction, and the output end of the i-th first shift register unit is connected to the second reset line corresponding to the i-M-th row of pixel areas; the output end of the j-th first shift register is connected to the first reset line corresponding to the j-th row of pixel areas through a signal transmission line; N is an integer greater than 2, M is a preset positive integer, M+1 ⁇ i ⁇ N+M, 1 ⁇ j ⁇ N, and i and j are both integers.
  • the orthographic projection of the signal transmission line on the substrate overlaps with the orthographic projection of at least one of the first shift register units on the substrate.
  • the first reset line and the second reset line may be located in the first gate metal layer, and both may be manufactured synchronously with a portion of the structure in the first shift register unit.
  • the first reset line and the second reset line may be manufactured synchronously with the gates of each transistor in the first shift register unit.
  • the manufacturing method further includes: forming a plurality of drive signal lines, the plurality of drive signal lines being used to provide signals for the plurality of first shift register units, the orthographic projection of at least one of the plurality of drive signal lines on the substrate overlapping with the orthographic projection of the plurality of first shift register units on the substrate, wherein at least one of the drive signal lines is formed synchronously with the signal transmission line.
  • the plurality of driving signal lines include: a first clock signal line, a second clock signal line, a frame start signal line, a third power signal line, and a fourth power signal line.
  • the third power line, the first clock signal line, the second clock signal line, and the frame start signal line are formed synchronously with the signal transmission line. In other embodiments, the third power line is formed synchronously with the signal transmission line.
  • the present disclosure also provides a display device, including the display substrate in the above embodiment.
  • the display device can be any product or component with display function, such as electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示基板及其制作方法和显示装置，显示基板具有显示区（AA）和周边区（NA），显示区（AA）包括沿第一方向排列的N个像素组，每个像素组包括至少一行像素区，显示基板包括：多条第一复位线（RESET1）和多条第二复位线（RESET2），每行像素区均对应一条第一复位线（RESET1）和一条第二复位线（RESET2）；N+M个第一移位寄存器单元（GOA1）沿第一方向排列，第i个第一移位寄存器单元（GOA1）的输出端与第i-M行像素区对应的第二复位线（RESET2）连接；第j个第一移位寄存器（GOA1）的输出端通过信号传输线（60）与第j行像素区对应的第一复位线（RESET1）连接；N为大于2的整数，M为预设正整数，M+1≤i≤N+M，1≤j≤N，i、j均为整数；信号传输线（60）在衬底基板（100）上的正投影与至少一个第一移位寄存器单元（GOA1）在衬底基板（100）上的正投影存在交叠。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种显示基板及其制作方法、显示装置。
 背景技术
显示基板的周边区中设置有驱动电路，用于为显示区的像素单元提供驱动信号。显示装置的显示区域中设置多个像素单元，每个像素单元均包括有像素电路。各个像素电路分别与周边区中的驱动电路电连接，通过驱动电路为像素电路提供扫描信号和发光控制信号，以控制像素电路为发光器件提供驱动电流。
发明内容
本公开提供一种显示基板，具有显示区和周边区，所述显示区包括沿第一方向排列的N个像素组，每个像素组包括至少一行所述像素区，所述显示基板包括：
衬底基板；
设置在所述衬底基板上的多条第一复位线和多条第二复位线，每行像素区均对应一条所述第一复位线和一条所述第二复位线；
设置在所述衬底基板上、且位于所述周边区的N+M个第一移位寄存器单元，所述N+M个第一移位寄存器单元沿所述第一方向排列，其中，第i个第一移位寄存器单元的输出端与第i-M行像素区对应的第二复位线连接；第j个第一移位寄存器的输出端通过信号传输线与第j行像素区对应的第一复位线连接；N为大于2的整数，M为预设正整数，M+1≤i≤N+M，1≤j≤N，i、j均为整数；
其中，所述信号传输线在所述衬底基板上的正投影与至少一个所述第一移位寄存器单元在所述衬底基板上的正投影存在交叠。
在一些实施例中，所述第一移位寄存器单元包括：输出晶体管，所述输出晶体管与所述第一移位寄存器单元的输出端连接，所述信号传输线在所述衬底基板上的正投影与至少一个所述第一移位寄存器单元的输出晶体管在所述衬底基板上的正投影存在交叠。
在一些实施例中，每条所述信号传输线在所述衬底基板上的正投影与M-1个所述第一移位寄存器单元在所述衬底基板上的正投影存在交叠。
在一些实施例中，所述第一移位寄存器单元包括存储电容，所述信号传输线在所述衬底基板上的正投影与所述存储电容在所述衬底基板上的正投影无交叠。
在一些实施例中，所述信号传输线包括多个传输线段以及位于相邻两个传输线段之间的连接线段，所述传输线段沿所述第一方向延伸；
所述信号传输线具有首端和尾端，所述首端与所述第一移位寄存器单元的输出端连接，所述尾端与所述复位线连接；对于同一个信号传输线中的相邻两个传输线段，靠近所述首端的传输线段到所述显示区的距离大于远离所述首端的传输线段到所述显示区的距离。
在一些实施例中，所述连接线段为直线段，所述连接线段与相邻的所述传输线段之间形成钝角。
在一些实施例中，所述多个第一移位寄存器单元所连接的信号传输线中的连接线段分为多个第一线段组，所述多个第一线段组沿所述第一方向排列，至少一个所述第一线段组中包括M-1个连接线段，
其中，所述M-1个连接线段的中心连线为直线，所述中心连线的延伸方向与所述第一方向、所述第一复位线的延伸方向均交叉；
或者，所述M-1个连接线段的中心连接不在同一直线上。
在一些实施例中，所述M-1个连接线段的中心连线为直线，且所述中心连接与所述连接线段朝不同方向倾斜。
在一些实施例中，所述M-1个连接线段中，各连接线段的长度相同；
或者，至少两个连接线段的长度不同。
在一些实施例中，所述多个第一移位寄存器单元所连接的信号传输线中的传输线段分为多个第二线段组，所述多个第二线段组沿第二方向排列，每个所述第二线段组包括沿所述第一方向排列的多个所述传输线段，同一个所述第二线段组中的多个所述传输线段位于同一直线上。
在一些实施例中，每相邻两个第二线段组之间的距离相等。
在一些实施例中，所述显示基板还包括：
多条扫描线，每行像素区均对应一条所述扫描线；
位于所述周边区的多个第二移位寄存器单元，每个所述第二移位寄存器单元的输出端连接一条所述扫描线；
电源线，电源线在所述衬底基板上的正投影与所述第二移位寄存器单元在所述衬底基板上的正投影存在交叠。
在一些实施例中，所述多个第二移位寄存器单元位于所述多个第一移位寄存器单元靠近所述显示区的一侧。
在一些实施例中，所述显示基板还包括：
多条驱动信号线，用于为所述多个第一移位寄存器单元提供信号，所述多条驱动信号线中的至少一条在所述衬底基板上的正投影与所述多个第一移位寄存器单元在所述衬底基板上的正投影存在交叠。
在一些实施例中，所述驱动信号线与所述信号传输线在所述衬底基板上的正投影无交叠。
在一些实施例中，至少一条所述驱动信号线与所述信号传输线同层设置。
在一些实施例中，所述显示基板还包括：
多条连接线，每条所述连接线对应一个所述第一移位寄存器单元，所述第一移位寄存器单元通过相应的所述连接线与所述第二复位线连接；除最后一级第一移位寄存器单元之外，其余每个所述第一移位寄存器单元还通过所述连接线与下一级第一移位寄存器单元的输入端连接；
多个第一转接件，每个所述第一转接件对应一条所述信号传输线，所述第一转接件的一端通过第一过孔与所述连接线连接，另一端通过第二过孔与所述信号传输线连接。
在一些实施例中，所述第一移位寄存器单元包括多个晶体管，所述第一过孔和所述第二过孔在所述衬底基板上的正投影均与所述晶体管在所述衬底基板上的正投影无交叠。
在一些实施例中，多个所述第一转接件沿所述第一方向排列。
在一些实施例中，所述连接线与所述第二复位线同层设置并电连接。
在一些实施例中，所述信号传输线位于所述第一转接件所在层远离所述衬底基板的一侧。
在一些实施例中，所述显示基板还包括：
第二转接件，所述第二转接件的一端通过第三过孔与所述信号传输线连接，另一端通过第四过孔与所述第一复位线连接；
其中，所述第一移位寄存器单元包括多个晶体管，所述第三过孔和所述第四过孔在所述衬底基板上的正投影均与所述晶体管在所述衬底基板上的正投影无交叠。
在一些实施例中，所述多个第二转接件沿第一方向排列。
本公开实施例还提供一种显示装置，其中，包括上述的显示基板。
本公开实施例还提供一种显示基板的制作方法，所述显示基板具有显示区和周边区，所述显示区包括沿第一方向排列的N行像素区，其中，所述制作方法包括：
在衬底基板上形成多条第一复位线和多条第二复位线，每行所述像素区均对应一条所述第一复位线和一条所述第二复位线；
在所述衬底基板上对应于所述周边区的位置形成N+M个第一移位寄存器单元；其中，所述N+M个第一移位寄存器单元沿所述第一方向排列，第i个第一移位寄存器单元的输出端与第i-M行像素区对应的第二复位线连接；第j个第一移位寄存器的输出端通过信号传输线与第j行像素区对应的第一复位线连接；N为大于2的整数，M为预设正整数，M+1≤i≤N+M，1≤j≤N，i、j均为整数；
其中，所述信号传输线在所述衬底基板上的正投影与至少一个所述第一移位寄存器单元在所述衬底基板上的正投影存在交叠。
在一些实施例中，所述制作方法还包括：
形成多条驱动信号线，所述多条驱动信号线用于为所述多个第一移位寄存器单元提供信号，所述多条驱动信号线中的至少一条在所述衬底基板上的正投影与所述多个第一移位寄存器单元在所述衬底基板上的正投影存在交叠；
其中，至少一条所述驱动信号线与所述信号传输线同步形成。
 附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为一些实施例中提供的显示基板的平面图。
图2为一些实施例中提供的像素电路和发光器件的电路原理图。
图3为图2中的像素电路的时序图。
图4为第n行像素电路和第n+1行像素电路的部分信号的时序图。
图5为本公开的一些实施例中提供的显示基板的平面图。
图6为本公开的一些实施例中提供的第一移位寄存器单元、第二移位寄存器单元与N行像素区之间的对应关系示意图。
图7为本公开的一些实施例中提供的第一移位寄存器单元的电路原理图。
图8A为本公开的一些实施例中提供的显示基板的局部示意图。
图8B为本公开的一些实施例中提供的第一级移位寄存器单元所在区域的局部示意图。
图9为图8A中半导体层的示意图。
图10为图8A中第一栅金属层的示意图。
图11为图8A中第二栅金属层的示意图。
图12为图8A中第一源漏金属层的示意图。
图13为图8A中第二源漏金属层的示意图。
图14为图8A中的过孔分布示意图。
[根据细则91更正 30.11.2023]
图15为本公开的另一些实施例中提供的第一移位寄存器单元和各信号线的平面图。
[根据细则91更正 30.11.2023]
图16为本公开的另一些实施例中提供的周边区的局部示意图。
 具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，本公开实施例使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要说明的是，本公开实施例中的膜层进行示意性说明，不代表膜层的真实厚度。
还需要说明的是，本公开实施例中的“同层设置”是指，两个结构或多个结构是由同一个材料层经过构图工艺形成的，故这两个结构或多个结构在层叠关系上是处于同一个层之中的；但这并不表示两个结构或多个结构到衬底基板100间的距离必定相同。
此外，在本公开实施例中所涉及的各个晶体管可分别独立选自多晶硅薄膜晶体管、非晶硅薄膜晶体管、氧化物薄膜晶体管以及有机薄膜晶体管中的一种。在本公开中涉及到的“第一极”具体是指晶体管的源极，相应的“第二极”具体是指晶体管的漏极。当然，本领域的技术人员应该知晓的是，该“第一极”与“第二极”可进行互换。另外，晶体管分为N型晶体管和P型晶体管，本公开实施例中的工作电平信号是指，能够控制晶体管导通的信号；非工作电平信号是指，能够控制晶体管关断的信号。对于N型晶体管而言，其工作电平信号为高电平信号，非工作电平信号为低电平信号；对于P型晶体管而言，其工作电平信号为低电平信号，非工作电平信号为高电平信号。
图1为一些实施例中提供的显示基板的平面图，如图1所示，显示基板包括显示区AA和位于该显示区AA周边的周边区NA，显示区AA包括阵列排布的多个像素区，每个像素区中设置有发光器件20、以及用于为发光器件20提供驱动电流的像素电路10。
图2为一些实施例中提供的像素电路和发光器件的电路原理图，如图2所示，像素电路10包括：第一复位晶体管T1’、第二复位晶体管T7’、驱动晶体管T3’、数据写入晶体管T4’、第一发光控制晶体管T5’、第二发光控制晶体管T6’、补偿晶体管T2’和存储电容Cst。其中，存储电容Cst的两端分别连接第一电源线VDD和驱动晶体管T3’的栅极。第一复位晶体管T1’的栅极连接第一复位线RESET1，第一复位晶体管T1’的第一极连接驱动晶体管T3’的栅极，第一复位晶体管T1’的第二极连接第一初始化信号线Vinit1。第二复位晶体管T7’的栅极连接栅线，第二复位晶体管T7’的第一极连接发光器件20的第一电极，第二复位晶体管T7’的第二极连接第二初始化信号线Vinit2。数据写入晶体管T4’的栅极连接扫描线GL，数据写入晶体管T4’的第一极连接驱动晶体管T3’的第一极，数据写入晶体管T4’的第二极连接数据线。补偿晶体管T2’的栅极连接第二复位线RESET2，补偿晶体管T2’的第一极连接驱动晶体管T3’的栅极，补偿晶体管T2’的第二极连接驱动晶体管T3’的第二极。第一发光控制晶体管T5’的栅极连接发光控制线EM，第一发光控制晶体管T5’的第一极连接第一电源线VDD，第一发光控制晶体管T5’的第二极连接驱动晶体管T3’的第一极。第二发光控制晶体管T6’的栅极连接发光控制线EM，第二发光控制晶体管T6’的第一极连接驱动晶体管T3’的第二极，第二发光控制晶体管T6’的第二极连接发光器件20的第一电极。发光器件20的第二电极连接第二电源线VSS。其中，发光器件20的第一电极可以为阳极，第二电极可以为阴极。
其中，位于同一行的像素电路10中的第一复位晶体管T1’与同一条第一复位线RESET1连接；位于同一行的像素电路10中的补偿晶体管T2’与同一条第二复位线RESET2连接；位于同一行的像素电路10中的第一发光控制晶体管T5’和第二发光控制晶体管T6’与同一条发光控制线EM连接；位于同一行的像素电路10中的数据写入晶体管T4’与同一条扫描线GL连接，位于同一列的像素电路10中的数据写入晶体管T4’与同一条数据线DL连接。
在一个示例中，图2所示的像素电路10中的各晶体管为P型晶体管，此时，低电平信号控制各晶体管开启。图3为图2中的像素电路的时序图，如图3所示，像素电路10的工作过程包括：复位阶段t1、数据写入及补偿阶段t2、发光阶段t3。其中，在复位阶段t1，第一复位线RESET1提供低电平信号，从而控制第一复位晶体管T1’导通；之后第二复位线RESET2提供有效电平信号，从而控制补偿晶体管T2’导通。在数据写入及补偿阶段t2，扫描线GL和第二复位线RESET2提供低电平信号，从而控制数据写入晶体管T4’和补偿晶体管T2’导通，数据线DL上的数据信号和驱动晶体管T3’的阈值电压被写入存储电容Cst中。在发光阶段t3，发光控制线EM上的信号为低电平信号，从而控制第一发光控制晶体管T5’和第二发光控制晶体管T6’导通，驱动晶体管T3’为发光器件提供驱动电流。
其中，扫描线GL上的信号上升沿到发光阶段t3之间的时间为阈值补偿时间。
需要说明的是，图2中的像素电路10仅为示例性说明，在其他示例中，像素电路也可以采用其他结构，例如，采用8T1C等。
如图1所示，周边区NA设置有第一驱动电路30、第二驱动电路40和第三驱动电路50，其中，第一驱动电路30包括级联的多个第一移位寄存器单元GOA1，第二驱动电路40包括级联的多个第二移位寄存器单元GOA2，第三驱动电路50包括级联的多个第三移位寄存器单元GOA3。其中，每个第三移位寄存器单元GOA3连接一条发光控制线EM，每个第二移位寄存器单元GOA2连接一条扫描线GL，每个第一移位寄存器单元GOA1连接一条第一复位线RESET1和一条第二复位线RESET2。例如，显示区AA包括N行像素区，第一驱动电路30包括级联的N+M个第一移位寄存器单元GOA1，其中，第i个第一移位寄存器单元GOA1与第i-M行像素区对应的第二复位线RESET2连接；第j个第一移位寄存器单元GOA1通过信号传输线60与第j行像素区对应的第一复位线RESET1连接；N为大于2的整数，M为预设正整数，M+1≤i≤N+M，1≤j≤N，i、j均为整数。这样，所有的第一复位线RESET1和第二复位线RESET2由同一个驱动电路来控制，从而有利于减小显示产品的边框宽度。并且，M设置得越大，越有利于增大阈值补偿时间，从而提高画质。
假设，M＝2，N＝2480，则第一移位寄存器单元GOA1的数量为2482个。第1个第一移位寄存器单元GOA1通过信号传输线60与第1行像素区对应的第一复位线RESET1连接，第2个第一移位寄存器单元GOA1通过信号传输线60与第2行像素区对应的第一复位线RESET1连接；第3个第一移位寄存器单元GOA1与第1行像素区对应的第二复位线RESET2连接，并通过信号传输线60与第3行像素区对应的第一复位线RESET1连接；第4个第一移位寄存器单元GOA1与第2行像素区对应的第二复位线RESET2连接，并通过信号传输线60与第4行像素区对应的第一复位线RESET1连接；以此类推，第2481个第一移位寄存器单元GOA1与第2479行像素区对应的第二复位线RESET2连接，并通过信号传输线60与第2480行像素区对应的第一复位线RESET1连接；第2481个第一移位寄存器单元GOA1与第2480行像素区所对应的第二复位线RESET2连接。
需要说明的是，本公开中所谓的第一移位寄存器单元GOA1与第一复位线RESET1(或第二复位线RESET2)连接，是指第一移位寄存器单元GOA1的输出端与第一复位线RESET1(或第二复位线RESET2)连接。
还需要说明的是，本公开实施例中，多行像素区是逐行被扫描，从而进行逐行显示的，“第n行”、“第n个”是指，沿扫描方向排列的第n行、第n个。
在上述实施例中，不同像素区所对应的第一复位线RESET1连接不同的第一移位寄存器单元GOA1，不同像素区所对应的第二复位线RESET2连接不同的第一移位寄存器单元GOA1，这种连接结构简称为“一驱一”结构。而在另一些实施例中，每两行像素区所对应的两条第一复位线RESET1与同一个第一移位寄存器单元GOA1连接，每两行像素区所对应的两条第二复位线RESET2与同一个第一移位寄存器单元GOA1连接，这种连接结构简称为“一驱二”结构。当采用“一驱二”结构时，假设第n行和第n+1行像素区对应的两条第一复位线RESET1连接同一个第一移位寄存器单元GOA1，第n行和第n+1行像素区对应的两条第二复位线RESET2连接同一个第一移位寄存器单元GOA1，则第n行像素电路和第n+1行像素电路的部分信号的时序图如图4所示，如图4所示，第n行像素电路10和第n+1行像素电路10的阈值补偿时间差异较大，这样可能会导致奇偶行像素区的显示出现明显差异。
为了减少相邻两行像素区的显示差异，在一些实施例中，将多行像素区划分为多个像素组，当采用“一驱二”结构时，每个像素组包括两行像素区，第i个第一移位寄存器单元GOA1与第i-M个像素组对应的各第二复位线RESET2连接；第j个第一移位寄存器单元GOA1通过信号传输线60与第j个像素组对应的各第一复位线RESET1连接；N为大于2的整数，M为预设正整数，M+1≤i≤N+M，1≤j≤N，i、j均为整数。可以将上述M设置为大于1的整数，例如为7或8，从而增加各行像素电路10的阈值补偿时间，进而减少奇偶行像素区的显示差异。
但是，无论采用“一驱一”还是“一驱二”结构，由于第一移位寄存器单元GOA1的输出端与第一复位线RESET1之间需要通过信号传输线60连接，信号传输线60设置在第一驱动电路30与显示区AA之间，而信号传输线60具有一定的宽度，并且，不同信号传输线60之间需要留有一定的间隙，因此，当M设置的较大时，多条信号传输线60的设置将增大显示产品的边框宽度，不利于窄边框的实现。
图5为本公开的一些实施例中提供的显示基板的平面图，如图5所示，显示基板包括：显示区AA和周边区NA，显示区AA包括沿第一方向排列的N个像素组，每个像素组包括至少一行像素区，每个像素区中包括沿第二方向排列的多个像素区。显示基板包括衬底基板100，以及设置在衬底基板100上的：多条第一复位线RESET1、多条第二复位线RESET2和N+M个第一移位寄存器单元GOA1。
其中，第一复位线RESET1和第二复位线RESET2的至少一部分位于显示区，每行像素区均对应一条第一复位线RESET1和一条第二复位线RESET2。第一移位寄存器单元GOA1位于周边区NA，N+M个第一移位寄存器单元GOA1沿所述第一方向排列，其中，第i个第一移位寄存器单元GOA1的输出端与第i-M个像素组对应的第二复位线RESET2连接；第j个第一移位寄存器单元GOA1的输出端通过信号传输线60与第j个像素组对应的第一复位线RESET1连接；N为大于2的整数，M为预设正整数，M+1≤i≤N+M，2≤M，1≤j≤N，i、j均为整数。其中，第一移位寄存器单元GOA1的输出端与某一像素组对应的第一复位线RESET1(或第二复位线RESET2)连接，是指，第一移位寄存器单元GOA1的输出端与像素区中各行像素区所对应的第一复位线RESET1(或第二复位线RESET2)连接。
其中，每个像素组可以包括一行像素区，以实现上文中的“一驱一”结构。或者，每个像素组可以包括两行像素区，以实现上文中的“一驱二”结构。当然，每个像素区也可以包括其他数量。在下文实施例中，以每个像素组包括一行像素区为例进行说明。
图6为本公开的一些实施例中提供的第一移位寄存器单元、第二移位寄存器单元与N行像素区之间的对应关系示意图，需要说明的是，图6中的各箭头仅表示信号流，不表示实际的信号线布置方式。图6以每个像素组包括一行像素区，M＝8，N＝2480为例进行说明，此时第一移位寄存器单元GOA1的数量为2488个。结合图5和图6所示，第1个第一移位寄存器单元GOA1_1通过信号传输线60与第1行像素区对应的第一复位线RESET1连接；第2个第一移位寄存器单元GOA1_2通过信号传输线60与第2行像素区对应的第一复位线RESET1连接；以此类推，第8个第一移位寄存器单元GOA1与通过信号传输线60与第8行像素区对应的第一复位线RESET1连接。第9个第一移位寄存器单元GOA1_9与第1行像素区对应的第二复位线RESET2连接，并通过信号传输线60与第9行像素区对应的第一复位线RESET1连接；第10个第一移位寄存器单元GOA1_10与第2行像素区对应的第二复位线RESET2连接，并通过信号传输线60与第10行像素区对应的第一复位线RESET1连接；以此类推，第2480个第一移位寄存器单元GOA1与第2472行像素区对应的第二复位线RESET2连接，并通过信号传输线60与第2480行像素区对应的第一复位线RESET1连接；第2481个至第2488个第一移位寄存器单元GOA1分别与2473行至第2480行像素区所对应的第二复位线RESET2连接。
在本公开实施例中，信号传输线60在衬底基板100上的正投影与至少一个第一移位寄存器单元GOA1在所述衬底基板100上的正投影存在交叠，这种情况下，信号传输线60不会占据第一移位寄存器单元GOA1与显示区之间的空间，从而可以减小显示基板的边框宽度，有利于窄边框的实现。
其中，信号传输线60可以位于第一移位寄存器单元GOA1远离衬底基板100的一侧，也可以位于第一移位寄存器单元GOA1与衬底基板100之间。在下文的实施例中，以信号传输线60位于第一移位寄存器单元GOA1远离衬底一侧为例进行说明。
图7为本公开的一些实施例中提供的第一移位寄存器单元的电路原理图，如图7所示，第一移位寄存器单元GOA1包括：输入子电路ISC、输出子电路OSC、第一处理子电路PSC1、第二处理子电路PSC2、第三处理子电路PSC3、第一稳压子电路SSC1、和第二稳压子电路SSC2。
在一些实施例中，输出子电路OSC被配置为响应于第四节点N4和第一节点N1的电压，向输出端OUT提供第三电源线VGH或第四电源线VGL的电压。可选地，输出子电路OSC包括两个输出晶体管，分别为第九晶体管T9和第十晶体管T10。第九晶体管T9连接在第三电源线VGH和输出端OUT之间。第九晶体管T9的栅极连接至第四节点N4。第九晶体管T9可根据第四节点N4的电压而导通或截止。当第九晶体管T9导通时，第三电源线VGH的电压被提供至输出端OUT。第十晶体管T10连接在输出端OUT和第四电源线VGL之间。第十晶体管T10的栅极连接至第一节点N1。第十晶体管T10可根据第一节点N1的电压而导通或截止。当第十晶体管T10导通时，第四电源线VGL的电压被提供至输出端OUT。
在一些实施例中，输入子电路ISC被配置为响应于分别提供至第一输入端IN和第一时钟信号端CK的信号来控制第一节点N1的电压。可选地，输入子电路ISC包括第一晶体管T1。第一晶体管T1的栅极连接至第一时钟信号端CK，第一晶体管T1的第一极作为上述第一输入端IN，第一晶体管T1的第二极连接至第一节点N1。
在一些实施例中，第一处理子电路PSC1被配置为响应于第一节点N1的电压来控制第四节点N4的电压。可选地，第一处理子电路PSC1包括第八晶体管T8和第二电容C2。第八晶体管T8连接在第三电源线VGH和第四节点N4之间。第八晶体管T8的栅极连接至第一节点N1。第二电容C2连接在第三电源线VGH和第四节点N4之间。可选地，第二电容C2被配置为对施加到第四节点N4的电压进行充电。可选地，第二电容C2被配置为稳定地维持第四节点N4的电压。
在一些实施例中，第二处理子电路PSC2连接至第五节点N5，并且被配置为响应于输入到第三输入端TM3的信号来控制第四节点N4的电压。可选地，第二处理子电路PSC2包括第六晶体管T6、第七晶体管T7和第一电容C1。第一电容C1的第一端连接至第五节点N5，第一电容C1的第二端连接至第三节点N3，第三节点N3为第六晶体管T6和第七晶体管T7之间的公共节点。第六晶体管T6连接在第三节点N3与第五节点N5之间。第六晶体管T6的栅极连接至第五节点N5。第七晶体管T7连接在第四节点N4和第三节点N3之间。第七晶体管T7的栅极连接至第二时钟信号端CB。
在一些实施例中，第三处理子电路PSC3被配置为控制第二节点N2的电压。可选地，第三处理子电路PSC3包括第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第三电容C3。第五晶体管T5连接在第三电源线VGH和第四晶体管T4之间。第五晶体管T5的栅极连接至第二节点N2。第四晶体管T4连接在第五晶体管T5和第二时钟信号端CB之间。第四晶体管T4的栅极连接至第十晶体管T10的栅极。第四晶体管T4的第二极连接至第五晶体管T5的第二极。第二晶体管T2连接在第二节点N2和第一时钟信号端CK之间，第二晶体管T2的栅极连接至第一节点N1。第三晶体管T3连接在第二节点N2和第四电源线VGL之间，第三晶体管T3的栅极连接至第一时钟信号端CK。第三电容C3连接在第十晶体管T10与第五晶体管T5之间。第三电容C3的第二极板连接至第五晶体管T5的第二极和第四晶体管T4的第一极。第三电容C3的第一极板连接至第四晶体管T4的栅极和第十晶体管T10的栅极。
可选地，在一些实施例中，第三处理子电路PSC3被配置为控制第二节点N2的电压。其中，第四晶体管T4的第二极连接至第五晶体管T5的第二极，第四晶体管T4的第一极连接至第二时钟信号端CB，第四晶体管T4的栅极连接至第一节点N1。
在一些实施例中，第一稳压子电路SSC1包括第十一晶体管T11。第十一晶体管T11连接在第二节点N2和第五节点N5之间，第十一晶体管T11的栅极连接至第四电源线VGL。由于第四电源线VGL提供的电压为第十一晶体管T11的工作电平电压，因此，第十一晶体管T11可一直保持导通。因此，第二节点N2和第五节点N5可以保持在相同的电压，并且基本上作为同一节点来操作。
在一些实施例中，第二稳压子电路SSC2连接在第一节点N1和输出子电路OSC之间。第二稳压子电路SSC2被配置为限制第一节点N1的压降宽度。可选地，第二稳压子电路SSC2包括第十二晶体管T12。第十二晶体管T12连接在第一节点N1和第十晶体管T10的栅极之间。第十二晶体管T12的栅极连接至第四电源线VGL，第十二晶体管T12可一直保持导通。因此，第一节点N1和第十晶体管T10的栅极可保持在相同的电压。
在一些实施例中，第一至第十二晶体管T1至T12中的每一个可以由p型晶体管形成。在一些实施例中，第一至第十二晶体管T1至T12的工作电平电压可设置为低电平电压，而非工作电平电压可设置为高电平电压。
图8A为本公开的一些实施例中提供的显示基板的局部示意图，图8A中示出了两个第一移位寄存器单元GOA1及其所在区域的多条信号传输线60和多条驱动信号线，驱动信号线用于为第一移位寄存器单元GOA1提供驱动信号，例如，多条驱动信号线包括：第三电源线、第四电源线、第一时钟信号线、第二时钟信号线、帧起始信号线。其中，至少一条驱动信号线可以与信号传输线60同层设置，图8A至图14是以第三电源线与信号传输线60同层设置为例进行说明的。图9为图8A中半导体层的示意图，图10为图8A中第一栅金属层的示意图，图11为图8A中第二栅金属层的示意图，图12为图8A中第一源漏金属层的示意图，图13为图8A中第二源漏金属层的示意图，图14为图8A中的过孔分布示意图。
如图8A至图14所示，半导体层Poly包括：各晶体管T1～12的有源层T1_a～T12a和掺杂区图案，同一个第一像素电路中各晶体管的有源层和掺杂区图案一体设置。对于同一个晶体管，该晶体管的有源层两侧均设有掺杂区图案，有源层两侧的掺杂区图案可分别作为晶体管的第一极和第二极。可选地，第九晶体管T9的有源层T9_a和第十晶体管T10的有源层T10_a沿第一方向排列。半导体层Poly可以采用半导体材料图案化形成，该半导体材料可以为氧化物半导体材料，例如IGZO。
第一栅金属层G1设置在半导体层远离衬底基板100的一侧，第一栅金属层G1可以包括例如金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等。例如，第一栅金属层可以包括金(Au)、金的合金、银(Ag)、银的合金、铝(Al)、铝的合金、氮化铝(AlNx)、钨(W)、氮化钨(WNx)、铜(Cu)、铜的合金、镍(Ni)、铬(Cr)、氮化铬(CrNx)、钼(Mo)、钼的合金、钛(Ti)、氮化钛(TiN x)、铂(Pt)、钽(Ta)、氮化钽(TaNx)、钕(Nd)、钪(Sc)、氧化锶钌(SRO)、氧化锌(ZnOx)、氧化锡(SnOx)、氧化铟(InOx)、氧化镓(GaOx)、氧化铟锡(ITO)、氧化铟锌(IZO)等。第一栅金属层G1可以具有单层或多层。
如图10所示，第一栅金属层G1包括：各晶体管T1～T12的栅极T1_g～T12_g、第一电容C1的第一极板、第二电容C2的第一极板和第三电容C3的第一极板。其中，第四晶体管T3的栅极与第三电容C3的第一极板C31可以连接为一体结构。第一晶体管T1的栅极T1_g与第三晶体管T3的栅极T3_g可以连接为一体结构。第二晶体管T2的栅极T2_g与第八晶体管T8的栅极T8_g可以连接为一体结构。第六晶体管T6的栅极T6_g与第一电容C1的第一极板C11形成为一体结构。
第二栅金属层G2设置在第一栅金属层远离衬底基板100的一侧，第二栅金属层G2的材料可以选自上文中所列举的第一栅金属层的材料。在一些实施例中，如图10所示，第二栅金属层G2包括：连接线70、第一电容C1的第二极板C12、第二电容C2的第二极板C22和第三电容C3的第二极板C32。其中，每条连接线70对应一个第一移位寄存器单元GOA1，第一移位寄存器单元GOA1通过相应的连接线70与相应的第二复位线RESET2连接。
可选地，除最后一级第一移位寄存器单元GOA1之外，其余每个第一移位寄存器单元GOA1还通过相应的连接线70与下一级第一移位寄存器单元GOA1的输入端连接。其中，每个第一移位寄存器单元GOA1的输入端可以为第一晶体管T1的第一极，连接线的一端通过过孔与第一晶体管T1的第一极连接。例如，连接线70包括沿第一方向延伸的第一部分71和沿第二方向延伸的第二部分72，第二部分72的一端通过过孔与第一晶体管T1的第一极连接，第二部分72的另一端与第二部分72的一端连接，第一部分71的另一端与相应的第二复位线RESET2连接。其中，第一部分71与第二复位线RESET2可以同层设置并电连接。需要说明的是，本公开实施例中的“电连接”可以是直接连接，也可以是间接连接。
在一些实施例中，第二栅金属层G2还包括每级第一移位寄存器单元GOA1的时钟信号转接线80。
如图12所示，第一源漏金属层SD1位于第二栅金属层G2远离衬底基板100的一侧，第一源漏金属层SD1包括：多个转接件、以及第四电源线VGL、第一时钟信号线CKL、第二时钟信号线CBL、帧起始信号线STV。其中，第四电源线VGL、第一时钟信号线CKL、第二时钟信号线CBL、帧起始信号线STV均沿第一方向延伸。多个转接件包括：第一转接件E1至第十六转接件E16。
其中，第一转接件E1的数量为多个，每个第一转接件E1对应一个第一移位寄存器单元GOA1。结合图8A、图12、图14所示，每个第一转接件E1的一端通过第一过孔V1与连接线70连接，另一端通过第二过孔V2与信号传输线60连接。在一些示例中，多个第一转接件E1沿第一方向排列。
第二转接件E2的数量为多个，每个第二转接件E2对应一个第一移位寄存器单元GOA1，每个第二转接件E2的一端通过第三过孔V3与信号传输线60连接，另一端通过第四过孔V4与第一复位线RESET1连接。在一些实施例中，多个第二转接件E2可以沿第一方向排列。
在一些实施例中，第一过孔V1、第二过孔V2、第三过孔V3和第四过孔V4在衬底基板100上的正投影与各晶体管在衬底基板100上的正投影均无交叠，以防止在过孔的制作过程中对晶体管造成影响。
结合图8A、图12、图14所示，第三转接件E3通过第五过孔V5与第十晶体管T10的第二极连接，并通过第六过孔V6与第九晶体管T9的第二极连接；另外，第三连接件E3还通过第七过孔V7与连接线70的第二部分72连接，第九晶体管T9的第二极、第十晶体管T10的第二极、第三转接件E3以及连接线70之间的连接节点可以作为第一移位寄存器单元GOA1的输出端。
第四转接件E4通过第八过孔V8与第十晶体管T10的第一极连接，并通过第九过孔V9与第十二晶体管T12的栅极连接，通过第十过孔V10与第三晶体管T3的第一极连接。第十二晶体管T12的栅极与第四电源线VGL连接。
第五转接件E5通过第十一过孔V11与第九晶体管T9的第一极连接，并通过第二十七过孔V27与第二电容C2的第二极板C22连接，通过第十二过孔V12与第五晶体管T5的第一极连接。
第六转接件E6通过第十三过孔V13与第二电容C2的第一极板C21连接，并通过第十四过孔V14与第八晶体管T8的第一极连接。第七连接件E7通过第十五过孔V15与第四晶体管T4的第二极连接，通过第十六过孔V16与第七晶体管T7的栅极连接，并通过第四十五过孔V45与第六晶体管T6的第一极连接，以及，通过第四十二过孔V42与时钟信号转接线80连接。
第八转接件E8通过第十七过孔V17与第四晶体管T4的栅极连接，并通过第十八过孔V18与第十二晶体管T12的第二极连接。
第九转接件E9通过第十九过孔V19与第七晶体管T7的第一极连接，并通过第二十过孔V20与第六晶体管T6第二极连接，以及通过第二十一过孔V21与第一电容C1的第二极板C12连接。其中，第二十一过孔V21的数量可以为一个或多个，例如，第二十一过孔V21为两个，以提高连接稳定性。
第十转接件E10通过第二十二过孔V22与第三电容C3的第二极板C32连接，并通过第二十三过孔V23与第四晶体管T4的第二极连接，以及通过第二十四过孔V24与第五晶体管T5的第二极连接。
第十一转接件E11通过第二十五过孔V25与第十二晶体管T12的第一极连接，并通过第二十六过孔V26与第八晶体管T8的栅极连接。
第十二转接件E12通过第二十八过孔V28与第三晶体管T3的第二极连接，并通过第二十九过孔V29与第五晶体管T5的栅极连接，以及通过第三十过孔V30与第十一晶体管T11的第一极连接。
第十三转接件E13通过第三十一过孔V31与第三晶体管T3的栅极连接，并通过第三十二过孔V32与第二晶体管T2的第二极连接。
第十四转接件E14通过第三十三过孔V33与第二晶体管T2的栅极连接，并通过第三十四过孔V34与第一晶体管T1的第二极连接。
第十五转接件E15通过第三十五过孔V35与第一晶体管T1的第一极连接，另外，每级第一移位寄存器单元GOA1均对应一个第十五转接件E15，第一级第一移位寄存器单元GOA1所对应的第十五转接件E15可以与帧起始信号线STV连接；除了第一级之外，其余第一移位寄存器单元GOA1所对应的第十五转接件E15还通过第三十六过孔V36与上一级第一移位寄存器单元GOA1所对应的连接线70连接。
第十六转接件E16通过第三十七过孔V37与第十一晶体管T11的第二极连接，并通过第三十八过孔V38与第六晶体管T6的栅极连接。
第一时钟信号线CKL通过过孔V48与奇数级第一移位寄存器单元GOA1中的第三晶体管T3的栅极连接，并通过过孔V49与偶数级第一移位寄存器单元GOA1中的时钟信号转接线80连接。第二时钟信号线CBL通过过孔V50与偶数级第一移位寄存器单元GOA1中的第三晶体管T3的栅极连接，并通过过孔V51与奇数级第一移位寄存器单元GOA1中的时钟信号转接线80连接。每级第一移位寄存器单元GOA1的时钟信号转接线80用于连接第七转接件E7。其中，过孔V48～V50的数量均可以为一个或多个，例如，过孔V48～V50均为两个，从而提高连接稳定性。
第四电源线VGL通过第四十过孔V40与第十二晶体管T12的栅极连接，以及通过第四十一过孔V41与第十一晶体管T11的栅极连接。第四十过孔V40和第四十一过孔V41的数量可以为一个或多个，例如，第四十过孔V40和第四十一过孔V41均为两个，从而提高连接稳定性。
在一些示例中，第一时钟信号线CKL位于第四电源线VGL远离显示区的一侧，第二时钟信号线CBL位于第一时钟信号线CKL远离显示区的一侧，帧起始信号线STV位于第二时钟信号线CBL远离显示区的一侧。
在一个示例中，第一时钟信号线CLK、第二时钟信号线CBL、帧起始信号线STV、第四电源线VGL在衬底基板100上的正投影与第一移位寄存器单元GOA1中各晶体管的有源层在衬底基板100上的正投影均无交叠。
在一些实施例中，第二源漏金属层SD2包括：多条信号传输线60和第三电源线VGH。其中，第三电源线VGH沿第一方向延伸。例如，第三电源线VGH在衬底基板100上的正投影可以与第三电容C3、第四晶体管T4、第八晶体管T8在衬底基板100上的正投影存在交叠。第三电源线VGH可以通过第三十九过孔V39与第五转接件E5连接。为了提高连接稳定性，每个第五转接件E5可以通过多个第三十九过孔V39与第三电源线VGH连接。
图8B为本公开的一些实施例中提供的第一级移位寄存器单元所在区域的局部示意图，图8B中示出了第一级移位寄存器单元中的部分结构，以及第一时钟信号线CKL、第二时钟信号线CBL、帧起始信号线STV、第三电源线VGH和第四电源线VGL。其中，如上文所述，每级第一移位寄存器单元GOA对应一个第十五转接件E15，第十五转接件E15通过第三十五过孔V35与第一晶体管T1的第一极连接，第一级移位寄存器单元GOA所对应的E15还通过过孔与帧起始信号转接线90的一端连接，帧起始信号转接线90的另一端通过过孔与帧起始信号线STV连接。其中，帧起始信号转接线90位于第二栅金属层G2中，当然，也可以位于第一栅金属层G1中。
结合图8A至图12所示，信号传输线60具有首端和尾端，信号传输线60的首端通过第二过孔V2与第一转接件E1连接，从而通过第一转接件E1与第一移位寄存器单元GOA1的输出端连接。信号传输线60的尾端通过第四过孔V4与第二转接件E2连接，从而通过第二转接件E2与第二复位线RESET2连接。信号传输线60在衬底基板100上的正投影与至少一个第一移位寄存器单元GOA1的至少一个输出晶体管在衬底基板100上的正投影存在交叠。例如，在图7所示的第一移位寄存器单元GOA1中，包括两个输出晶体管，即第九晶体管T9和第十晶体管T10，此时，每条信号传输线60的正投影可以与至少一个第一移位寄存器单元GOA1的第九晶体管T9和第十晶体管T10的正投影交叠。
在一些实施例中，每条信号传输线60在衬底基板100上的正投影与M-1个第一移位寄存器单元GOA1在衬底基板100上的正投影存在交叠。例如，每条信号传输线60在衬底基板100上的正投影与M-1个第一移位寄存器单元GOA1的第九晶体管T9和第十晶体管T10在衬底基板100上的正投影交叠。
如图8A所示，信号传输线60在衬底基板100上的正投影与存储电容(如上文中的第一电容C1、第二电容C2和第三电容C3)在衬底基板100上的正投影无交叠，以防止信号传输线60与存储电容之间产生寄生电容而导致存储电容与信号传输线60之间发生信号干扰。
如图13所示，信号传输线60为弯折结构，其包括多个传输线段61以及位于相邻两个传输线段61之间的连接线段62，传输线段61沿第一方向延伸。信号传输线60具有首端和尾端，首端与第一移位寄存器单元GOA1的输出端连接，尾端与第一复位线RESET1连接。其中，信号传输线60位于第三电源线VGH靠近显示区的一侧(对于图13而言，显示区位于信号传输线60的左侧)。对于同一个信号传输线60中的相邻两个传输线段61，靠近首端的传输线段61到显示区的距离大于远离首端的传输线段61到显示区的距离。信号传输线60在衬底基板100上的正投影位于显示区与存储电容在衬底基板100上的正投影之间，从信号传输线60的首端至尾端，信号传输线60向靠近显示区的方向进行多次弯折，从而有利于减少多条信号传输线60所占用的区域宽度。
其中，如图13所示，连接线段62为直线段，连接线段62与相邻的传输线段61之间形成钝角，该钝角可以在95°～160°之间，例如，95°，或100°，或120°，或145°，或150°，或160°。当然，在其他实施例中，连接线段62也可以为弧线段，从而与相邻的传输线段61之间形成圆角结构。
如图13所示，多个第一移位寄存器单元GOA1所连接的信号传输线60中的连接线段62分为多个第一线段组62g，多个第一线段组62g沿第一方向排列，至少部分第一线段组62g中包括M-1个连接线段62，在一些示例中，该M-1个连接线段62的中心连线为直线，且中心连线的延伸方向与第一方向和第二方向均交叉。当然，在另一些示例中，所述M-1个连接线段62的中心连线可以不在同一直线上。
如图13所示，M-1个连接线段62的中心连线为直线，且中心连线与连接线段62朝不同方向倾斜。例如，如图13中，M-1个连接线段62的中心连线采用“\”的倾斜方式，连接线段62采用“/”的倾斜方式。
如图13所示，在具有M-1个连接线段62的第一线段组62g中，各连接线段62的长度相同，或者，至少两个连接线段62的长度不同。
可选地，相邻两个第一移位寄存器单元对应区域的连接线段62的倾斜方式不同。例如：第1个第一移位寄存器单元GOA1_1的输出端对应区域的信号传输线60，其信号传输线60的连接线段62用“\”的倾斜方式；第2个第一移位寄存器单元GOA1_2的输出端对应区域的信号传输线60，其信号传输线60的连接线段62的连接线段62采用“/”的倾斜方式。
如图8A和图13所示，在第一线段组62g中，至少一个连接线段62在衬底基板100上的正投影与第十晶体管T10在衬底基板100上的正投影存在交叠。
如图13所示，多个第一移位寄存器单元GOA1所连接的信号传输线60中的传输线段61分为多个第二线段组61g，多个第二线段组61g沿第二方向排列，每个第二线段组61g包括沿第一方向排列的多个传输线段61，同一个第二线段组61g中的多个传输线段61位于同一直线上。
如图13所示，多个第一移位寄存器单元GOA1所连接的信号传输线60中的传输线段61分为多个第二线段组61g，多个第二线段组61g沿第二方向排列，每个第二线段组61g包括沿第一方向排列的多个传输线段61，同一个第二线段组中的多个传输线段61位于同一直线上，从而使得多条信号传输线60整体所占据的区域宽度较小。
可选地，第二线段组61g中的传输线段61各自连接不同的移位寄存器单元。
其中，每相邻两个第二线段组61g之间的距离相等。
在一个示例中，传输线段61与连接线段62的宽度可以大致相同，本公开实施例中的“大致相同”是指，两个数值的差值小于10％，或5％，或者完全相等。相邻两个第二线段组61g之间的距离可以小于传输线段61宽度的1.5倍。在一个示例中，传输线段61的宽度、相邻两个第二线段组61g之间的距离均小于或等于10μm。例如，传输线段61的宽度、相邻两个第二线段组61g之间的距离均为3μm，或5μm，或7μm，或9μm，或10μm。
在图8A至图14所示的实施例中，驱动信号线与信号传输线60在衬底基板100上的正投影无交叠。第四电源线VGL、第一时钟信号线CK、第二时钟信号线CB等驱动信号线在衬底基板100上的正投影均与第一移位寄存器单元GOA1中各晶体管的有源层在衬底基板100上的正投影无交叠。而在另一些实施例中，至少一条驱动信号线在衬底基板100上的正投影与第一移位寄存器单元GOA1中的晶体管的有源层存在交叠。与第一移位寄存器单元GOA1中晶体管的有源层存在交叠的驱动信号线与信号传输线60同层设置，均位于第二源漏金属层SD2中。
图15为本公开的另一些实施例中提供的第一移位寄存器单元和各信号线的平面图，如图15所示，第一时钟信号线CKL、第二时钟信号线CBL和帧起始信号线STV在衬底基板100上的正投影均与第一移位寄存器单元GOA1中晶体管的有源层在衬底基板100上的正投影交叠。例如，第一时钟信号线CKL在衬底基板100上的正投影与第二晶体管T2的有源层、第三晶体管T3的有源层在衬底基板100上的正投影存在交叠。第二时钟信号线CBL在衬底基板100上的正投影与第一晶体管T1的有源层在衬底基板100上的正投影存在交叠。
在图15所示的实施例中，驱动信号线与信号传输线60在衬底基板100上的正投影同样无交叠。第四电源线VGL位于第一源漏金属层中。第一时钟信号线CKL、第二时钟信号线CBL、帧起始信号线STV、第三电源线VGH均和信号传输线60同层设置，均位于第二源漏金属层中。其中，帧起始信号线STV在衬底基板上的正投影可以与第四电源线VGL在衬底基板上的正投影存在交叠。
如图15所示，第一时钟信号线CKL位于第三电源线VGH远离显示区的一侧，第二时钟信号线CBL位于第一时钟信号线CKL远离显示区的一侧，帧起始信号线STV位于第二时钟信号线CBL远离显示区的一侧。
需要说明的是，图15是以第一时钟信号线CKL、第二时钟信号线CBL、帧起始信号线STV、第三电源线VGH同层设置为例进行说明的，在其他实施例中，也可以将第一时钟信号线CKL、第二时钟信号线CBL、帧起始信号线STV、第三电源线VGH设置在不同层中，例如，设置在两层或等多层中。另外，也可以使信号传输线60与任意一条驱动信号线均设置在不同层中。例如，第三电源线设置在第一源漏金属层中，信号传输线60设置在第二源漏金属层中，第一时钟信号线CKL、第二时钟信号线CBL、帧起始信号线STV、第三电源线VGH设置在第二源漏金属层远离衬底基板100的一侧。
在一些实施例中，如图15所示，当第一时钟信号线CKL、第二时钟信号线CBL、帧起始信号线STV与第三电源线VGH同层设置时，第一时钟信号线CKL通过第四十三过孔V43与奇数级第一移位寄存器单元GOA1的第十三转接件E13连接，第二时钟信号线通过第四十四过孔V44与偶数级第一移位寄存器单元GOA1的第十三转接件E13连接。另外，在图15所示的实施例中，第二栅金属层中无需设置时钟信号连接件，此时，第一时钟信号线CKL直接通过过孔与奇数级第一移位寄存器单元GOA1的第七转接件E7连接，第二时钟信号线CBL直接过孔过孔与偶数级第一移位寄存器单元GOA1的第七转接件E7连接。
在一些实施例中，当帧起始信号线STV位于第二源漏金属层中时，帧起始信号线STV可以与第一级第一移位寄存器单元GOA中的第一晶体管T1的第一极存在正投影交叠，此时，帧起始信号STV可以直接通过过孔与第一级移位寄存器单元GOA中的第一晶体管T1的第一极连接，而无需设置图8B中的帧起始信号转接线90。
需要说明的是，显示基板还包括设置在衬底基板100上的多个绝缘层，多个绝缘层例如包括：第一栅绝缘层、第二栅绝缘层、层间介质层、钝化层。其中，第一栅绝缘层设置在半导体层Poly与第一栅金属层G1之间，第二栅绝缘层设置在第一栅金属层与第二栅金属层之间，层间介质层设置在第二栅金属层与第一源漏金属层之间，钝化层设置在第一源漏金属层与第二源漏金属层之间。其中，在本公开实施例中，两个导电结构通过过孔连接时，该过孔是贯穿两个导电结构之间的绝缘层的。
另外，在本公开实施例中，第一移位寄存器单元中各晶体管与像素电路中各晶体管的相同结构可以同层设置，例如，第一移位寄存器单元中各晶体管的栅极与像素电路中各晶体管的栅极同层设置，第一移位寄存器单元中各晶体管的有源层与像素电路中各晶体管的有源层同层设置。另外，在一些示例中，第二源漏金属层SD2远离衬底基板100的一侧还可以设置有平坦化层，显示区中的发光器件设置在平坦化层远离衬底基板的一侧。
在一些示例中，第一栅绝缘层、第二栅绝缘层、层间介质层和钝化层的材料均可以选自：氮氧化硅(SiON)、氧化硅(SiOx)、氮化硅(SiNx)、碳氧化硅(SiOxCy)、氮碳化硅(SiCxNy)、氧化铝(AlOx)、氮化铝(AlNx)、氧化钽(TaOx)、氧化铪(HfOx)、氧化锆(ZrOx)、氧化钛(TiOx)等。第一栅绝缘层、第二栅绝缘层、层间介质层和钝化层均可以形成为单层或多层。平坦化层的材料可以包括有机材料。
图16为本公开的另一些实施例中提供的周边区的局部示意图，结合图5和图16所示，显示基板还包括：设置在衬底基板100上的多条扫描线GL和第二驱动电路40，扫描线GL的至少一部分位于显示区AA，第二驱动电路40位于周边区NA，每行像素区均对应一条扫描线GL。第二驱动电路40包括级联的多个第二移位寄存器单元GOA2，每个第二移位寄存器单元GOA2的输出端连接一条扫描线GL，用于为扫描线GL提供扫描信号。其中，第二驱动电路40可以位于第一驱动电路30靠近显示区AA的一侧。
其中，可以在显示区AA的一侧设置第二驱动电路40，或者，在显示区AA的相对两侧均设置第二驱动电路40。第二移位寄存器单元GOA2的结构与第一移位寄存器单元GOA1的结构类似，均包括多个晶体管和存储电容。第一驱动电路30位于第二驱动电路40远离显示区AA的一侧。当然，在其他实施例中，第一驱动电路30也可以位于第二驱动电路40靠近显示区AA的一侧。
显示基板还包括第二电源线VSS，第二电源线VSS用于为显示区AA中的发光器件20的第二电极提供电信号。其中，第二电源线VSS在衬底基板100上的正投影与第二移位寄存器单元GOA2在衬底基板100上的正投影存在交叠，从而减小显示区AA两侧的边框宽度。
如图16所示，第二电源线VSS具有多个镂空部Va，以减小第二电源线VSS与第二移位寄存器单元GOA2中导电结构之间的寄生电容。其中，第二移位寄存器单元GOA2中的导电结构可以包括第二移位寄存器单元GOA2中各晶体管的第一极、第二极、栅极，以及存储电容的两个极板。镂空部Va的形状不作限定，例如，可以为矩形、圆形、三角形、椭圆形或其他形状。
在一些实施例中，第二电源线VSS可以与信号传输线60同层设置，从而可以使第二电源线VSS和信号传输线60同步制作，简化制备工艺。另外，第一时钟信号线CKL、第二时钟信号线CBL、帧起始信号线STV也均与信号传输线60同层设置，进一步简化制备工艺。
需要说明的是，第二电源线VSS也可以与信号传输线60位于不同层，例如，第二电源线VSS位于信号传输线60所在层远离衬底基板100的一侧。
可选地，第二电源线VSS位于信号传输线60所在层远离衬底基板100的一侧，且第二电源线VSS与信号传输线60至少部分交叠。例如：第二电源线VSS与显示区AA中的发光器件20的第一电极(例如：阳极)相同的导电层制作。
在一些实施例中，显示基板还包括设置在周边区的第一信号转接线81、第二信号转接线82、第三信号转接线83、第四信号转接线84。
信号传输线60可以与第一信号转接线81的第一端连接，第一信号转接线81的第二端与第二信号转接线82的第一端连接，第二信号转接线82的第二端与第一复位线RESET1连接。与第九晶体管T9和第十晶体管T10连接的连接线可以与第三信号转接线83的第一端连接，第三信号转接线83的第二端与第四信号转接线84的第一端连接，第四信号转接线84的第二端与第二复位线RESET2连接。第二移位寄存器单元的输出端与第五信号转接线85的第一端连接，第五信号转接线85的第二端与第六信号转接线86的第一端连接，第六信号转接线86的第二端与扫描线连接。
其中，第一复位线RESET1、第二复位线RESET2均可以位于第一栅金属层中，第一信号转接线81、第三信号转接线83、第五信号转接线85均可以位于第二栅金属层中，第二信号转接线82、第四信号转接线84和第六信号转接线86均可以位于第一源漏金属层中。
另外，在本公开实施例中，如图5所示，显示基板还包括第三驱动电路50和多条发光控制线EM，第三驱动电路50设置在周边区NA，且包括级联的多个第三移位寄存器单元GOA3。发光控制线EM的至少一部分设置在显示区AA，每个第三移位寄存器单元GOA3连接一条发光控制线EM。
本公开实施例还提供一种上述显示基板的制作方法，显示基板具有显示区和周边区，所述显示区包括沿第一方向排列的N行像素区。显示基板的制作方法包括：
S1、在衬底基板上形成多条第一复位线和多条第二复位线，每行所述像素区均对应一条所述第一复位线和一条所述第二复位线。
S2、在衬底基板上对应于所述周边区的位置形成N+M个第一移位寄存器单元；其中，所述N+M个第一移位寄存器单元沿所述第一方向排列，第i个第一移位寄存器单元的输出端与第i-M行像素区对应的第二复位线连接；第j个第一移位寄存器的输出端通过信号传输线与第j行像素区对应的第一复位线连接；N为大于2的整数，M为预设正整数，M+1≤i≤N+M，1≤j≤N，i、j均为整数。
其中，所述信号传输线在所述衬底基板上的正投影与至少一个所述第一移位寄存器单元在所述衬底基板上的正投影存在交叠。
其中，第一复位线和第二复位线可以位于第一栅金属层中，二者可以与第一移位寄存器单元中的部分结构同步制作。例如，第一复位线和第二复位线可以与第一移位寄存器单元中各晶体管的栅极同步制作。
在一些实施例中，所述制作方法还包括：形成多条驱动信号线，所述多条驱动信号线用于为所述多个第一移位寄存器单元提供信号，所述多条驱动信号线中的至少一条在所述衬底基板上的正投影与所述多个第一移位寄存器单元在所述衬底基板上的正投影存在交叠。其中，至少一条所述驱动信号线与所述信号传输线同步形成。
例如，多条驱动信号线包括：第一时钟信号线、第二时钟信号线、帧起始信号线、第三电源信号线和第四电源信号线，在一些实施例中，第三电源线、第一时钟信号线、第二时钟信号线和帧起始信号线与信号传输线同步形成。在另一些实施例中，第三电源线与信号传输线同步形成。
本公开实施例还提供一种显示装置，包括上述实施例中的显示基板。该显示装置可以为：电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (26)

  1. 一种显示基板，具有显示区和周边区，所述显示区包括沿第一方向排列的N个像素组，每个像素组包括至少一行所述像素区，所述显示基板包括：
    衬底基板；
    设置在所述衬底基板上的多条第一复位线和多条第二复位线，每行像素区均对应一条所述第一复位线和一条所述第二复位线；
    设置在所述衬底基板上、且位于所述周边区的N+M个第一移位寄存器单元，所述N+M个第一移位寄存器单元沿所述第一方向排列，其中，第i个第一移位寄存器单元的输出端与第i-M行像素区对应的第二复位线连接；第j个第一移位寄存器的输出端通过信号传输线与第j行像素区对应的第一复位线连接；N为大于2的整数，M为预设正整数，M+1≤i≤N+M，1≤j≤N，i、j均为整数；
    其中，所述信号传输线在所述衬底基板上的正投影与至少一个所述第一移位寄存器单元在所述衬底基板上的正投影存在交叠。
  2. 根据权利要求1所述的显示基板，其中，所述第一移位寄存器单元包括：输出晶体管，所述输出晶体管与所述第一移位寄存器单元的输出端连接，所述信号传输线在所述衬底基板上的正投影与至少一个所述第一移位寄存器单元的输出晶体管在所述衬底基板上的正投影存在交叠。
  3. 根据权利要求1所述的显示基板，其中，每条所述信号传输线在所述衬底基板上的正投影与M-1个所述第一移位寄存器单元在所述衬底基板上的正投影存在交叠。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述第一移位寄存器单元包括存储电容，所述信号传输线在所述衬底基板上的正投影与所述存储电容在所述衬底基板上的正投影无交叠。
  5. 根据权利要求1至3中任一项所述的显示基板，其中，所述信号传输线包括多个传输线段以及位于相邻两个传输线段之间的连接线段，所述传输线段沿所述第一方向延伸；
    所述信号传输线具有首端和尾端，所述首端与所述第一移位寄存器单元的输出端连接，所述尾端与所述复位线连接；对于同一个信号传输线中的相邻两个传输线段，靠近所述首端的传输线段到所述显示区的距离大于远离所述首端的传输线段到所述显示区的距离。
  6. 根据权利要求5所述的显示基板，其中，所述连接线段为直线段，所述连接线段与相邻的所述传输线段之间形成钝角。
  7. 根据权利要求5所述的显示基板，其中，所述多个第一移位寄存器单元所连接的信号传输线中的连接线段分为多个第一线段组，所述多个第一线段组沿所述第一方向排列，至少一个所述第一线段组中包括M-1个连接线段，
    其中，所述M-1个连接线段的中心连线为直线，所述中心连线的延伸方向与所述第一方向、所述第一复位线的延伸方向均交叉；
    或者，所述M-1个连接线段的中心连接不在同一直线上。
  8. 根据权利要求7所述的显示基板，其中，所述M-1个连接线段的中心连线为直线，且所述中心连接与所述连接线段朝不同方向倾斜。
  9. 根据权利要求7所述的显示基板，其中，所述M-1个连接线段中，各连接线段的长度相同；
    或者，至少两个连接线段的长度不同。
  10. 根据权利要求5所述的显示基板，其中，所述多个第一移位寄存器单元所连接的信号传输线中的传输线段分为多个第二线段组，所述多个第二线段组沿第二方向排列，每个所述第二线段组包括沿所述第一方向排列的多个所述传输线段，同一个所述第二线段组中的多个所述传输线段位于同一直线上。
  11. 根据权利要求10所述的显示基板，其中，每相邻两个第二线段组之间的距离相等。
  12. 根据权利要求1至11中任一项所述的显示基板，其中，所述显示基板还包括：
    多条扫描线，每行像素区均对应一条所述扫描线；
    位于所述周边区的多个第二移位寄存器单元，每个所述第二移位寄存器单元的输出端连接一条所述扫描线；
    电源线，电源线在所述衬底基板上的正投影与所述第二移位寄存器单元在所述衬底基板上的正投影存在交叠。
  13. 根据权利要求12所述的显示基板，其中，所述多个第二移位寄存器单元位于所述多个第一移位寄存器单元靠近所述显示区的一侧。
  14. 根据权利要求1至13中任一项所述的显示基板，其中，所述显示基板还包括：
    多条驱动信号线，用于为所述多个第一移位寄存器单元提供信号，所述多条驱动信号线中的至少一条在所述衬底基板上的正投影与所述多个第一移位寄存器单元在所述衬底基板上的正投影存在交叠。
  15. 根据权利要求14所述的显示基板，其中，所述驱动信号线与所述信号传输线在所述衬底基板上的正投影无交叠。
  16. 根据权利要求14所述的显示基板，其中，至少一条所述驱动信号线与所述信号传输线同层设置。
  17. 根据权利要求1至16中任一项所述的显示基板，其中，所述显示基板还包括：
    多条连接线，每条所述连接线对应一个所述第一移位寄存器单元，所述第一移位寄存器单元通过相应的所述连接线与所述第二复位线连接；除最后一级第一移位寄存器单元之外，其余每个所述第一移位寄存器单元还通过所述连接线与下一级第一移位寄存器单元的输入端连接；
    多个第一转接件，每个所述第一转接件对应一条所述信号传输线，所述第一转接件的一端通过第一过孔与所述连接线连接，另一端通过第二过孔与所述信号传输线连接。
  18. 根据权利要求17所述的显示基板，其中，所述第一移位寄存器单元包括多个晶体管，所述第一过孔和所述第二过孔在所述衬底基板上的正投影均与所述晶体管在所述衬底基板上的正投影无交叠。
  19. 根据权利要求17所述的显示基板，其中，多个所述第一转接件沿所述第一方向排列。
  20. 根据权利要求17所述的显示基板，其中，所述连接线与所述第二复位线同层设置并电连接。
  21. 根据权利要求17所述的显示基板，其中，
    所述信号传输线位于所述第一转接件所在层远离所述衬底基板的一侧。
  22. 根据权利要求1至21中任一项所述的显示基板，其中，所述显示基板还包括：
    第二转接件，所述第二转接件的一端通过第三过孔与所述信号传输线连接，另一端通过第四过孔与所述第一复位线连接；
    其中，所述第一移位寄存器单元包括多个晶体管，所述第三过孔和所述第四过孔在所述衬底基板上的正投影均与所述晶体管在所述衬底基板上的正投影无交叠。
  23. 根据权利要求22所述的显示基板，其中，所述多个第二转接件沿第一方向排列。
  24. 一种显示装置，其中，包括权利要求1至23中任一项所述的显示基板。
  25. 一种显示基板的制作方法，所述显示基板具有显示区和周边区，所述显示区包括沿第一方向排列的N行像素区，其中，所述制作方法包括：
    在衬底基板上形成多条第一复位线和多条第二复位线，每行所述像素区均对应一条所述第一复位线和一条所述第二复位线；
    在所述衬底基板上对应于所述周边区的位置形成N+M个第一移位寄存器单元；其中，所述N+M个第一移位寄存器单元沿所述第一方向排列， 第i个第一移位寄存器单元的输出端与第i-M行像素区对应的第二复位线连接；第j个第一移位寄存器的输出端通过信号传输线与第j行像素区对应的第一复位线连接；N为大于2的整数，M为预设正整数，M+1≤i≤N+M，1≤j≤N，i、j均为整数；
    其中，所述信号传输线在所述衬底基板上的正投影与至少一个所述第一移位寄存器单元在所述衬底基板上的正投影存在交叠。
  26. 根据权利要求25所述的制作方法，其中，所述制作方法还包括：
    形成多条驱动信号线，所述多条驱动信号线用于为所述多个第一移位寄存器单元提供信号，所述多条驱动信号线中的至少一条在所述衬底基板上的正投影与所述多个第一移位寄存器单元在所述衬底基板上的正投影存在交叠；
    其中，至少一条所述驱动信号线与所述信号传输线同步形成。
PCT/CN2023/077322 2023-02-21 2023-02-21 显示基板及其制作方法、显示装置 WO2024174082A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2023/077322 WO2024174082A1 (zh) 2023-02-21 2023-02-21 显示基板及其制作方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2023/077322 WO2024174082A1 (zh) 2023-02-21 2023-02-21 显示基板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
WO2024174082A1 true WO2024174082A1 (zh) 2024-08-29

Family

ID=92500114

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/077322 WO2024174082A1 (zh) 2023-02-21 2023-02-21 显示基板及其制作方法、显示装置

Country Status (1)

Country Link
WO (1) WO2024174082A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867446A (zh) * 2014-02-25 2015-08-26 三星显示有限公司 有机发光显示设备
CN108922474A (zh) * 2018-06-22 2018-11-30 武汉华星光电半导体显示技术有限公司 一种像素补偿电路及其驱动方法、amoled显示面板
CN111445824A (zh) * 2020-03-10 2020-07-24 厦门天马微电子有限公司 显示面板及显示装置
US20200394976A1 (en) * 2019-06-17 2020-12-17 Sharp Kabushiki Kaisha Scanning signal line drive circuit and display device provided with same
CN114005411A (zh) * 2021-11-05 2022-02-01 武汉天马微电子有限公司 阵列基板、显示面板及显示装置
CN114255703A (zh) * 2020-09-21 2022-03-29 京东方科技集团股份有限公司 显示基板及显示装置
WO2022160888A1 (zh) * 2021-01-29 2022-08-04 云谷（固安）科技有限公司 移位寄存器、栅极驱动电路和显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867446A (zh) * 2014-02-25 2015-08-26 三星显示有限公司 有机发光显示设备
CN108922474A (zh) * 2018-06-22 2018-11-30 武汉华星光电半导体显示技术有限公司 一种像素补偿电路及其驱动方法、amoled显示面板
US20200394976A1 (en) * 2019-06-17 2020-12-17 Sharp Kabushiki Kaisha Scanning signal line drive circuit and display device provided with same
CN111445824A (zh) * 2020-03-10 2020-07-24 厦门天马微电子有限公司 显示面板及显示装置
CN114255703A (zh) * 2020-09-21 2022-03-29 京东方科技集团股份有限公司 显示基板及显示装置
WO2022160888A1 (zh) * 2021-01-29 2022-08-04 云谷（固安）科技有限公司 移位寄存器、栅极驱动电路和显示面板
CN114005411A (zh) * 2021-11-05 2022-02-01 武汉天马微电子有限公司 阵列基板、显示面板及显示装置

Similar Documents

Publication Publication Date Title
CN111816691B (zh) 显示基板及其制作方法、显示装置
CN113823640B (zh) 显示基板和显示装置
TW571270B (en) Active matrix display panel and image display device adapting same
US20240172508A1 (en) Display substrate and display panel
EP4177897A1 (en) Display substrate and manufacturing method therefor, and display apparatus
US20220343854A1 (en) Display substrate and manufacture method thereof, and display device
US20220343856A1 (en) Display substrate and manufacturing method thereof, display device
US11594184B2 (en) Display substrate and manufacturing method thereof, display device
CN110738967B (zh) 显示设备
US20220319422A1 (en) Display substrate and display device
US20220310757A1 (en) Display substrate and display device
WO2023000322A1 (zh) 显示基板及显示装置
WO2024174082A1 (zh) 显示基板及其制作方法、显示装置
WO2022227478A1 (zh) 一种显示基板及其制作方法、显示装置
CN115398532B (zh) 显示基板及其制备方法、显示装置
CN118830015A (zh) 显示基板及其制作方法、显示装置
CN110426900B (zh) 阵列基板、显示面板及显示装置
CN111816127A (zh) Goa单元及其驱动方法、goa电路和显示面板
WO2024130634A1 (zh) 显示基板及其制备方法、显示装置
US20240268164A1 (en) Display Substrate and Display Apparatus
US12118935B2 (en) Display substrate and display apparatus
US11854489B2 (en) Display substrate and manufacturing method thereof, and display device
WO2023226010A1 (zh) 移位寄存器及其驱动方法、显示基板和显示装置
WO2024187374A1 (en) Array substrate and display apparatus
WO2024000248A9 (zh) 显示基板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23923267

Country of ref document: EP

Kind code of ref document: A1