WO2024159573A1 - 地址选择电路、地址选择方法、刷新控制电路和存储系统 - Google Patents

地址选择电路、地址选择方法、刷新控制电路和存储系统 Download PDF

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WO2024159573A1
WO2024159573A1 PCT/CN2023/078994 CN2023078994W WO2024159573A1 WO 2024159573 A1 WO2024159573 A1 WO 2024159573A1 CN 2023078994 W CN2023078994 W CN 2023078994W WO 2024159573 A1 WO2024159573 A1 WO 2024159573A1
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Prior art keywords
address
signal
state
row
shift
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English (en)
French (fr)
Inventor
刘勇
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Definitions

  • the present disclosure relates to the field of semiconductor technology and relates to, but is not limited to, an address selection circuit, an address selection method, a refresh control circuit, and a storage system.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the charge in the memory cell can decay over time, so a refresh operation needs to be performed periodically, otherwise the stored data information will be lost.
  • the charge stored in the memory cell can be maintained by recharging. This recharging of the charge in the memory cell is called a refresh operation, and the refresh operation can be repeated before the charge is significantly lost to replenish the charge and avoid errors in the stored data.
  • the word line corresponding to a single row address in the memory cell is frequently turned on, it will cause the capacitors of the adjacent addresses to have unexpected charge interactions before the refresh operation arrives, causing data errors and data loss.
  • embodiments of the present disclosure provide an address selection circuit, an address selection method, a refresh control circuit, and a storage system.
  • an address selection circuit including:
  • a plurality of address register units are configured to store row addresses; a status register unit is configured to store and output an address status signal; each bit of the address status signal is used to indicate a valid state or an invalid state of a corresponding address register unit; the valid state indicates that the row address is stored in the address register unit, and the invalid state indicates that the row address is not stored in the address register unit; a shift signal generating circuit is used to generate a shift signal according to the address status signal; a shift selection circuit is connected to the shift signal generating circuit; the shift selection circuit is used to select a plurality of address register units according to the shift signal, and use the row address stored in the selected address register unit as a row hammer address.
  • the address register unit and the status register unit are located in a page table; each page table entry of the page table includes the row address stored in the address register unit and the valid state or invalid state of the address register unit; the shift signal generating circuit is specifically used to generate a shift signal with a corresponding number of pulses based on the number of the address register units in the invalid state that are located before the first address register unit in the valid state among the multiple address register units; the shift selection circuit is specifically used to output a pointer according to the number of pulses of the shift signal to select the shift signal of the multiple page table entries. A selection is made, and the row address in the page table entry pointed to by the pointer is used as the row hammer address.
  • the shift signal generating circuit includes: a counting unit, configured to count clock pulses and generate a counting signal; a plurality of latch units, the latch units connecting the counting unit and the status register unit; the plurality of latch units are configured to latch each bit of the address state signal in sequence according to the counting signal to output a plurality of latch state signals; an arbitration unit, connecting the counting unit, the plurality of latch units and the status register unit; the arbitration unit is configured to output the shift signal according to the address state signal, the latch state signal and the counting signal, or according to the address state signal.
  • the arbitration unit is specifically configured to sequentially output a calculation result of at least one of the latch state signals and the counting signal according to the address state signal as the shift signal.
  • the arbitration unit is specifically configured to output a continuous first level as the shift signal according to the address state signal; the first level indicates that each bit of the address state signal indicates the invalid state.
  • the arbitration unit includes: a selection unit, connecting multiple latch units and the status register unit; the selection unit is configured to select and output at least one latch state signal in sequence according to the address state signal; an operation unit, connecting the selection unit and the counting unit; the operation unit is configured to operate at least one latch state signal with the counting signal in sequence to output the shift signal.
  • the address selection circuit also includes: a command decoding circuit connected to the arbitration unit; the command decoding circuit is used to generate and output an automatic refresh signal according to an external command issued by the host end; when at least one bit of the address status signal indicates the valid state, the arbitration unit is also configured to generate a first pulse of the shift signal according to the automatic refresh signal.
  • the address selection circuit further includes: a control logic connected to the counting unit; the control logic is used to disable the shift signal generating circuit when the count value represented by the counting signal is greater than a preset value.
  • the address selection circuit also includes: an address sampling circuit connected to the address register unit; the address sampling circuit is used to sample the row address and output the sampled row address to the address register unit; when the address register unit receives the row address output by the address sampling circuit, the control logic is also used to switch the corresponding bit of the row address in the address status signal from the invalid state to the valid state.
  • the address selection circuit also includes: an address operation circuit connected to the shift selection circuit; the address operation circuit is used to determine, based on the row hammer address, at least one row address adjacent to the row hammer address as a row hammer refresh address; after completing the refresh operation on the row hammer refresh address, the control logic is also used to clear the row address stored in the address register unit corresponding to the row hammer refresh address, and switch the corresponding bit of the row address in the address status signal from the valid state to the invalid state.
  • the address selection circuit is used to provide the row hammer address in the refresh control circuit
  • the refresh control circuit further includes: a refresh circuit for performing a refresh operation on at least one address line adjacent to the address line corresponding to the row hammer address.
  • an embodiment of the present disclosure provides an address selection method, comprising: storing multiple row addresses and address status signals in a page table; each bit of the address status signal is used to indicate a valid state or an invalid state of a corresponding page table entry; the valid state indicates that the row address is stored in the page table entry, and the invalid state indicates that the row address is not stored in the page table entry; outputting a shift signal based on the address status signal; selecting multiple page table entries based on the shift signal, and using the row address stored in the selected page table entry as a row hammer address.
  • outputting a shift signal according to the address status signal includes: based on the number of page table entries in the invalid state that are located before the first page table entry in the valid state among the multiple page table entries, outputting a shift signal with a corresponding number of pulses; selecting the multiple page table entries according to the shift signal, and using the row address stored in the selected page table entry as the row hammer address, includes: outputting a pointer according to the number of pulses of the shift signal to shift-select the multiple page table entries in a preset order, and using the row address in the page table entry pointed to by the pointer as the row hammer address.
  • generating a shift signal according to the address state signal includes: counting clock pulses and generating a counting signal; latching each bit of the address state signal in sequence according to the counting signal to output multiple latch state signals; outputting the shift signal according to the address state signal, the latch state signal and the counting signal, or according to the address state signal.
  • outputting the shift signal according to the address state signal includes: outputting a continuous first level as the shift signal according to the address state signal; the first level indicates that each bit of the address state signal indicates the invalid state.
  • outputting the shift signal according to the address state signal, the latch state signal and the count signal includes: according to the address state signal, outputting in sequence at least one operation result of the latch state signal and the count signal as the shift signal.
  • the operation results of at least one of the latch state signals and the counting signal are output in sequence as the shift signal, including: according to the address state signal, at least one of the latch state signals is selected and output in sequence; at least one of the latch state signals and the counting signal are operated in sequence to output the shift signal.
  • the method further includes: generating and outputting an automatic refresh signal according to an external command issued by the host end; and generating a first pulse of the shift signal according to the automatic refresh signal when at least one bit of the address status signal indicates the valid state.
  • the method further includes: disabling the shift signal generating circuit when the count value represented by the count signal is greater than a preset value.
  • the method further includes: sampling the row address; storing multiple row addresses in a page table includes: storing the sampled row address in the page table; when the sampled row address is received, switching the corresponding bit of the row address in the address status signal from the invalid state to the valid state.
  • the method further includes: determining, based on the row hammer address, at least one row address adjacent to the row hammer address as a row hammer refresh address; after completing the refresh operation on the row hammer refresh address, clearing the row address corresponding to the row hammer refresh address in the page table, and switching the corresponding bit of the row address in the address status signal from the valid state to the invalid state.
  • an embodiment of the present disclosure provides a storage system, comprising: a memory, including a peripheral circuit and a storage cell array; wherein the peripheral circuit comprises the address selection circuit described in any one of the above embodiments; and a storage controller.
  • each bit of the address state signal represents the valid state or invalid state of a corresponding address register unit
  • the shift signal generation circuit generates a shift signal according to the address state signal
  • the shift selection circuit selects multiple address register units according to the shift signal. In this way, the address selection circuit can select the first row address in a valid state as the row hammer address by polling, and refresh the row addresses adjacent to the row hammer address, thereby effectively reducing data errors caused by row hammer attack behaviors.
  • FIG1 is a schematic diagram of an address selection circuit provided in an embodiment of the present disclosure.
  • FIG2 is a schematic diagram of a shift selection circuit provided in an embodiment of the present disclosure.
  • FIG3 is a schematic diagram of a shift signal generating circuit provided by an embodiment of the present disclosure.
  • FIG4 is a working timing diagram of a shift signal generating circuit provided by an embodiment of the present disclosure.
  • FIG5 is a working timing diagram of another shift signal generating circuit provided by an embodiment of the present disclosure.
  • FIG6 is a working timing diagram of another shift signal generating circuit provided by an embodiment of the present disclosure.
  • FIG7 is a working timing diagram of another shift signal generating circuit provided by an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of an arbitration unit provided in an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of another address selection circuit provided in an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of another address selection circuit provided in an embodiment of the present disclosure.
  • FIG11 is a flowchart of a method for selecting an address provided by an embodiment of the present disclosure.
  • FIG12 is a schematic diagram of a refresh control circuit provided in an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a storage system provided in an embodiment of the present disclosure.
  • terms can be understood at least in part from their use in context.
  • the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense.
  • terms such as “one” or “the” can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context.
  • the term “based on” can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.
  • the capacitor size of the storage unit in the memory is small, so that the noise margin of the storage unit is small and it is easy to be interfered.
  • the storage unit is more susceptible to electromagnetic coupling and produces unexpected field effects.
  • the conventional refresh of the memory includes activation (Active, Act) and precharge (Precharge, Pre) operations.
  • activation activation
  • Precharge Precharge
  • a refresh window time when a word line (Word Line) in the memory is activated multiple times in succession, it may cause the capacitor of the adjacent address to flip data before the arrival of the conventional refresh signal, thereby generating erroneous storage. This phenomenon is generally called row hammer.
  • each word line corresponds to a row address
  • the row that is repeatedly accessed is called the aggressor row or the hammered row.
  • the address of the attacker row is the row hammer address
  • the row adjacent to the attacker row is called the victim row.
  • Row Hammer Refresh means refreshing the victim row after the memory has been working for a period of time to ensure that its data is correct.
  • the address of the victim row is the row hammer refresh address, and the number of accesses to the attacker row that causes data corruption is the row hammer threshold. It is worth noting that the row hammer attack behavior will cause data flipping in the victim row, including but not limited to flipping from "1" to "0", and from "0" to "1".
  • the memory automatically performs an Auto Refresh (AR) operation at a certain time interval, so the memory can automatically refresh As a row hammer refresh to refresh the victim row, the time interval between two automatic refreshes here can be adjusted according to the working conditions of the memory.
  • AR Auto Refresh
  • an embodiment of the present disclosure provides an address selection circuit 100, comprising: a plurality of address register units 101, configured to store row addresses; a status register unit 102, configured to store and output an address status signal ST_OPEN; each bit of the address status signal ST_OPEN is used to indicate a valid state or an invalid state of a corresponding address register unit 101; the valid state indicates that the row address is stored in the address register unit 101, and the invalid state indicates that the row address is not stored in the address register unit 101; a shift signal generating circuit 110, configured to generate a shift signal Shift_reg_clk according to the address status signal ST_OPEN; a shift selection circuit 120, connected to the shift signal generating circuit 110; the shift selection circuit 120 is used to select a plurality of the address register units 101 according to the shift signal Shift_reg_clk, and use the row address stored in the selected address register unit 101 as a row hammer address.
  • the address selection circuit 100 may have a page table, and the page table may be located in the peripheral circuit area of the DRAM near the storage array area.
  • the page table may store multiple row addresses, a first count value indicating the number of accesses to each row address, and the status of each page table entry, etc.
  • a data pointer may be used to point to the corresponding page table entry in the page table.
  • there are 9 page table entries in the page table that is, the page table stores 9 row addresses, the first count values corresponding to the 9 row addresses, and the status of each page table entry.
  • the storage contents in each page table entry have a corresponding relationship, and can be found by the index number of the page table and pointed to by the data pointer.
  • the address selection circuit 100 may have a plurality of address registers 101, and the address registers 101 are configured to store row addresses and output the row addresses stored therein.
  • Each row address here may physically correspond to a word line in the memory, and the row address for activation operation may be stored in the address register 101 by random sampling.
  • the random sampling method may be, for example, a method of generating a pseudo-random number by a linear feedback shift register; or a method of generating a random pulse by an oscillator. It is understandable that each address register 101 here may be configured to store a row address.
  • the state register unit 102 is configured to store the address state corresponding to the row address in the above-mentioned address register unit 101, and output the address state signal ST_OPEN.
  • the address state signal ST_OPEN can be an n-bit binary number, where each bit is "0" or "1", which is used to represent the valid (Lock, LO) state or invalid (Open, OP) state of a row address. It can be understood that n is an integer greater than 0, and n is equal to the number of address register units 101.
  • the state of the row address can be switched from LO to OP; when a new row address is input into the address register unit 101 through random sampling, the state of the row address can be switched from OP to LO, so that the dynamic update of each row address in the page table can be guaranteed.
  • the shift signal generating circuit 110 may be connected to the state register unit 102 and configured to generate a shift signal Shift_reg_clk according to the address state signal ST_OPEN, and the shift signal Shift_reg_clk may be a pulse signal.
  • the first pulse of the shift signal Shift_reg_clk is generated according to the auto-refresh signal, so the number of pulses of the shift signal may be the number of row addresses in the invalid state that are located before the first row address in the valid state among the plurality of row addresses arranged in sequence plus 1.
  • the shift signal generating circuit 110 when RA_ADDR1 is in the valid state, the shift signal generating circuit 110 outputs a shift signal with 1 pulse; when RA_ADDR2 is in the valid state and RA_ADDR1 is in the invalid state, the shift signal generating circuit 110 outputs a shift signal with 2 pulses... When RA_ADDR9 is in the valid state and RA_ADDR1 to RA_ADDR8 are all in the invalid state, the shift signal generating circuit 110 outputs a shift signal with 9 pulses. It is understandable that the shift signal generating circuit 110 does not determine the state of the row address after the first row address in the valid state.
  • the shift signal generating circuit 110 does not determine the states of RA_ADDR6 to RA_ADDR9, and outputs a shift signal having 5 pulses.
  • the shift selection circuit 120 can be connected to multiple address register units 101 and the shift signal generating circuit 110.
  • the shift selection circuit 120 is used to use the number of pulses of the shift signal Shift_reg_clk as the number of shifts to perform shift selection on multiple address register units 101 arranged in sequence, so as to use the row address selected after the shift as the row hammer address.
  • the shift selection circuit 120 can be a circular shift register (CSR), so as to use the position of bit "1" in the circular shift register as a pointer to find the first valid address in the page table.
  • the initial position of the shift selection circuit 120 can point to RA_ADDR9.
  • RA_ADDR1 When RA_ADDR1 is in a valid state, the number of pulses of the shift signal is 1, and the shift selection circuit 120 shifts once, thereby pointing to RA_ADDR1 after the shift, and using it as the row hammer address; when RA_ADDR2 is in a valid state and RA_ADDR1 is in an invalid state, the number of pulses of the shift signal is 2, and the shift selection circuit 120 shifts twice, thereby pointing to RA_ADDR2 after the shift, and using it as the row hammer address...
  • the address selection circuit 100 can select the first row address in a valid state as the row hammer address through a round robin method, and refresh the row addresses adjacent to the row hammer address, thereby effectively reducing data errors and data losses caused by row hammer attacks.
  • the memory needs to complete the refresh operation of the row address adjacent to the row hammer address within the refresh cycle time (Time for Refresh Cycle, tRFC), that is, the row hammer address selection process needs to be completed within the time interval between two automatic refreshes.
  • the address selection circuit works synchronously with the automatic refresh signal, if only the automatic refresh signal is used as the shift clock of the circular shift register, multiple shift searches cannot be performed within the time interval between two automatic refreshes. It can be understood that the address selection circuit provided in the embodiment of the present disclosure generates a shift signal through a shift signal generating circuit, and performs a shift search in a polling manner within the time interval between two automatic refreshes, thereby determining the row hammer address.
  • the address register unit 101 and the state register unit 102 are located in a page table; each page table entry of the page table includes the row address stored in the address register unit 101, and the valid state or invalid state of the address register unit 101; the shift signal generating circuit 110 is specifically used to generate a shift signal Shift_reg_clk with a corresponding number of pulses based on the number of the address register units 101 in the invalid state that are located before the first address register unit 101 in the valid state among the multiple address register units 101; the shift selection circuit 120 is specifically used to output a pointer according to the number of pulses of the shift signal Shift_reg_clk to select the multiple page table entries and point the pointer to the invalid state.
  • the row address in the page table entry is used as the row hammer address.
  • each page table entry can be understood with reference to Table 1. It is worth noting that the initial position of the pointer output by the shift selection circuit 120 can point to the last page table entry, that is, the page table entry corresponding to the index number 9, and according to the number of pulses of the shift signal Shift_reg_clk, the pointer will move downward from the initial position a corresponding number of times, and use the row address in the page table entry finally pointed to as the row hammer address.
  • the shift signal generating circuit 110 includes: a counting unit 111, configured to count clock pulses and generate a counting signal CNT_EQ; a plurality of latch units 112, wherein the latch units 112 are connected to the counting unit 111 and the state register unit; the plurality of latch units 112 are configured to latch each bit of the address state signal ST_OPEN in sequence according to the counting signal CNT_EQ to output a plurality of latch state signals ST_OPEN_LAT; an arbitration unit 113, connected to the counting unit 111, the plurality of latch units 112 and the state register unit 102; the arbitration unit 113 is configured to output the shift signal Shift_reg_clk according to the address state signal ST_OPEN, the latch state signal ST_OPEN_LAT and the counting signal CNT_EQ, or according to the address state signal ST_OPEN.
  • the arbitration unit is specifically configured to sequentially output a calculation result of at least one of the latch state signals and the counting signal according to the address state signal as the shift signal.
  • the arbitration unit is specifically configured to output a continuous first level as the shift signal according to the address state signal; the first level indicates that each bit of the address state signal indicates the invalid state.
  • the first level here can be either a high level or a low level, and the continuous first level represents skipping, so that the shift selection circuit does not perform shift selection, that is, when the next automatic refresh signal arrives, the memory does not perform row hammer refresh.
  • the counting unit 111 can count the clock pulse CLK to output the counting signal CNT_EQ, where the counting signal CNT_EQ can be a pulse signal.
  • the counting unit 111 can be a 4-bit binary counter, and the counting unit 111 can include at least one T' flip-flop.
  • the counting unit 111 can also be reset in response to the automatic refresh signal, thereby resetting the count value represented by the counting signal.
  • a plurality of latch units 112 can sequentially latch the valid state or invalid state represented by each bit of the address state signal ST_OPEN according to the count signal CNT_EQ, thereby outputting a plurality of latch state signals ST_OPEN_LAT, and the number of latch units 112 can be the same as the number of address register units. It is worth noting that each latch unit 112 can be connected to the state register unit and the count unit 111.
  • FIG. 4, FIG. 5 and FIG. 6 respectively show the timing diagrams of each signal when RA_ADDR1, RA_ADDR2, and RA_ADDR9 are the first row addresses in a valid state.
  • each latch unit 112 can generate a latch state signal ST_OPEN_LAT according to a rising edge of the count signal CNT_EQ, and the level change moment of the latch state signal ST_OPEN_LAT is aligned with a corresponding rising edge in the count signal CNT_EQ.
  • the level change time of ST_OPEN_LAT ⁇ 1> is aligned with the first rising edge of the count signal CNT_EQ
  • the level change time of ST_OPEN_LAT ⁇ 2> is aligned with the second rising edge of the count signal CNT_EQ...
  • the level change time of ST_OPEN_LAT ⁇ 8> is aligned with the eighth rising edge of the count signal CNT_EQ.
  • the latch state signal ST_OPEN_LAT remains at a low level, indicating the valid state of the corresponding row address, and specific reference may be made to ST_OPEN_LAT ⁇ 9> shown in Fig. 6.
  • the arbitration unit 113 can be connected to the counting unit 111, the plurality of latch units 112 and the state register unit 102.
  • the arbitration unit 113 outputs the operation result of at least one latch state signal ST_OPEN_LAT and the counting signal CNT_EQ according to the bit of the first valid state in the address state signal ST_OPEN as the shift signal Shift_reg_clk, where the operation can be an AND operation.
  • the address state signal ST_OPEN is "9'bxxxxxxxx0", where "0" represents the first valid state, and "x" represents that the valid state or the invalid state is not judged.
  • the arbitration unit only outputs the operation result of ST_OPEN_LAT ⁇ 1> and CNT_EQ as the shift signal Shift_reg_clk.
  • the address state signal ST_OPEN is “9'bxxxxxxx01”, where “1” represents an invalid state.
  • the arbitration unit sequentially outputs ST_OPEN_LAT ⁇ 1> and CNT_EQ, As well as the operation result of ST_OPEN_LAT ⁇ 2> and CNT_EQ, as the shift signal Shift_reg_clk.
  • the address state signal ST_OPEN is "9'b011111111", so that according to the address state signal, the arbitration unit sequentially outputs the operation results of ST_OPEN_LAT ⁇ 1> and CNT_EQ, ST_OPEN_LAT ⁇ 2> and CNT_EQ, ... and ST_OPEN_LAT ⁇ 9> and CNT_EQ, as the shift signal Shift_reg_clk.
  • the first pulse of the shift signal Shift_reg_clk is generated according to the auto-refresh signal.
  • the arbitration unit 113 can output a continuous high level as a shift signal Shift_reg_clk, where the continuous high level represents skipping (Skip), so that the shift selection circuit does not perform shift selection, that is, when the next automatic refresh signal arrives, the memory does not perform a row hammer refresh.
  • the number of shifts corresponding to the state of different row addresses can refer to Table 2, where "X" represents a valid state or an invalid state that is not judged. It is worth noting that in Table 2, index numbers 1 to 9 represent row addresses RA_ADDR1 to RA_ADDR9, respectively, and the number of shifts is the number of pulses in the shift signal Shift_reg_clk.
  • the shift signal generating circuit 110 includes a counting unit 111, a latch unit 112 and an arbitration unit 113, and generates a shift signal in a polling manner, the shift signal generating circuit 110 has the advantages of small area, high operating speed, and high reusability.
  • the arbitration unit 113 includes: a selection unit 114, connecting the plurality of latch units and the status register unit; the selection unit is configured to select and output at least one of the latch state signals ST_OPEN_LAT in sequence according to the address state signal ST_OPEN; an operation unit 115, connecting the selection unit 114 and the counting unit; the operation unit is configured to operate at least one of the latch state signals ST_OPEN_LAT and the counting signal CNT_EQ in sequence to output the shift signal Shift_reg_clk.
  • the selection unit 114 may be a data selector (Multiplexer, MUX), so as to select and output at least one latch state signal ST_OPEN_LAT in sequence according to the address state signal ST_OPEN.
  • the operation unit 115 may be an AND gate (AND), and is configured to perform an AND operation on at least one latch state signal ST_OPEN_LAT and a counting signal CNT_EQ in sequence to output a shift signal Shift_reg_clk.
  • RA_ADDR5 is taken as an example to be the first row address in a valid state.
  • the address state signal ST_OPEN is "9'bxxxx01111", so the selection unit 114 selects and outputs ST_OPEN_LAT ⁇ 1> to ST_OPEN_LAT ⁇ 5> in sequence, while ST_OPEN_LAT ⁇ 6> and the latch state signals thereafter are not output.
  • the arbitration unit 113 generates the first pulse of the shift signal Shift_reg_clk according to the automatic refresh signal; when the selection unit 114 outputs ST_OPEN_LAT ⁇ 1>, the operation unit 115 performs an AND operation on ST_OPEN_LAT ⁇ 1> and CNT_EQ to generate the second pulse of the shift signal Shift_reg_clk; when the selection unit 114 outputs ST_OPEN_LAT ⁇ 2>, the operation unit 115 performs an AND operation on ST_OPEN_LAT ⁇ 2> and CNT_EQ to generate the third pulse of the shift signal Shift_reg_clk.
  • the operation unit 115 When the selection unit 114 outputs ST_OPEN_LAT ⁇ 4>, the operation unit 115 performs an AND operation on ST_OPEN_LAT ⁇ 4> and CNT_EQ, thereby generating the fifth pulse of the shift signal Shift_reg_clk; when the selection unit 114 outputs ST_OPEN_LAT ⁇ 5>, the operation unit 115 performs an AND operation on ST_OPEN_LAT ⁇ 5> and CNT_EQ. Since ST_OPEN_LAT ⁇ 5> indicates a valid state, i.e., a low level, a pulse cannot be generated in the shift signal Shift_reg_clk. Thus, the shift signal Shift_reg_clk having five pulses can be generated through the selection unit 114 and the operation unit 115.
  • the arbitration unit may further include a plurality of operation units and a selection unit, where the number of operation units may be equal to the number of latch units.
  • the input end of each operation unit is connected to the counting unit and a latch unit, and the input end of the selection unit is connected to the output ends of the plurality of operation units. That is, each latch state signal ST_OPEN_LAT is first operated with the counting signal CNT_EQ, and then the selection unit sequentially outputs a plurality of serial comparison results as the shift signal Shift_reg_clk.
  • the address selection circuit 100 also includes: a command decoding circuit 130, connected to the arbitration unit 113; the command decoding circuit 130 is used to generate and output an automatic refresh signal AR according to an external command issued by the host end; when at least one bit of the address status signal ST_OPEN indicates the valid state, the arbitration unit 113 is also configured to generate a first pulse of the shift signal Shift_reg_clk according to the automatic refresh signal.
  • the command decoding circuit 130 can decode the external command sent by the memory controller (Memory Controller, MC) in the host side, where the external command includes but is not limited to a refresh command (Refresh, REF), a refresh management command (Refresh Management, RFM), an automatic refresh command, an activation command, etc.
  • the command decoding circuit 130 generates and outputs an automatic refresh signal according to the automatic refresh command, and when at least one row address is in a valid state, the arbitration unit 113 can generate the first pulse of the shift signal Shift_reg_clk according to the automatic refresh signal AR.
  • the address selection circuit further includes: a control logic 140 connected to the counting unit 111 ; the control logic 140 is used to disable the shift signal generating circuit 110 when the count value represented by the counting signal CNT_EQ is greater than a preset value.
  • the address selection circuit has 9 address registers.
  • the control logic 140 can disable the shift signal generating circuit 110 to reduce system power consumption.
  • the preset value can be the same as the number of address registers or different from the number of address registers, which is not limited here.
  • the address selection circuit 100 also includes: an address sampling circuit 150, connected to the address register unit 101; the address sampling circuit 150 is used to randomly sample the row address and output the sampled row address to the address register unit 101; when the address register unit 101 receives the row address output by the address sampling circuit 150, the control logic 140 is also used to switch the corresponding bit of the row address in the address status signal ST_OPEN from the invalid state to the valid state.
  • the address sampling circuit 150 can randomly capture the row address corresponding to the activation signal in response to the activation signal, and store the captured row address in the address register unit 101.
  • the control logic 140 can switch the corresponding bit of the address state signal ST_OPEN in the state register unit 102 from an invalid state to a valid state.
  • the address selection circuit 100 also includes: an address operation circuit 160, connected to the shift selection circuit 120; the address operation circuit 160 is used to determine, based on the row hammer address, at least one row address adjacent to the row hammer address as a row hammer refresh address; after completing the refresh operation on the row hammer refresh address, the control logic 140 is also used to clear the row address stored in the address storage unit 101 corresponding to the row hammer refresh address, and switch the corresponding bit of the row address in the address status signal from the valid state to the invalid state.
  • an address operation circuit 160 connected to the shift selection circuit 120
  • the address operation circuit 160 is used to determine, based on the row hammer address, at least one row address adjacent to the row hammer address as a row hammer refresh address
  • the control logic 140 is also used to clear the row address stored in the address storage unit 101 corresponding to the row hammer refresh address, and switch the corresponding bit of the row address in the address status signal from the valid state to the invalid state.
  • the address operation circuit 160 can use at least one row address adjacent to the row hammer address as a row hammer refresh address, where the row hammer refresh address is the victim row. In this way, performing a row hammer refresh operation on the word line corresponding to the victim row within tRFC can reduce data errors caused by row hammer attack behavior and improve the reliability of memory operation.
  • a row address adjacent to the row hammer address can be selected as the row hammer refresh address for refresh to reduce power consumption; or multiple row addresses adjacent to the row hammer address can be selected for refresh to improve the accuracy of refreshing the victim row.
  • control logic 140 can clear the row address stored in the address register unit 101 corresponding to the row hammer refresh address, and switch the corresponding bit of the row address in the address state signal ST_OPEN from a valid state to an invalid state. In this way, the row addresses stored in multiple address register units 101 can be dynamically updated, further improving the accuracy of generating the row hammer address.
  • the address selection circuit 100 further includes: a plurality of second counting units 103 corresponding to the plurality of address registers 101, the second counting units 103 being configured to count the number of activations of the row address stored in the address register 101 and output a second count value; a comparison circuit 104 connected to the plurality of second counting units 103, configured to compare the plurality of second count values and output the minimum count value therein; a control logic 140 is also connected to the comparison circuit 104, and the control logic 140 is also used to clear the row address stored in the address register 101 corresponding to the minimum count value, and switch the corresponding bit of the row address corresponding to the minimum count value in the address state signal from a valid state to an invalid state.
  • the row address corresponding to the minimum count value can be replaced with a new row address to ensure that the row address corresponding to the word line with a large number of activations is stored in the address register 101, thereby further improving the accuracy of generating the row hammer address.
  • an embodiment of the present disclosure provides an address selection method, including:
  • Step S10 storing a plurality of row addresses and address status signals in a page table; each bit of the address status signal is used to indicate a valid state or an invalid state of a corresponding page table entry; the valid state indicates that the row address is stored in the page table entry, and the invalid state indicates that the row address is not stored in the page table entry;
  • Step S20 outputting a shift signal according to the address state signal
  • Step S30 selecting a plurality of the page table entries according to the shift signal, and using the row address stored in the selected page table entry as a row hammer address.
  • multiple row addresses and an address state signal can be stored and output.
  • Each row address here can physically correspond to a word line in the memory, and multiple row addresses can be obtained by random sampling from the row address of the activation operation.
  • the address state signal can be an n-bit binary number, where each bit is "0" or "1", used to indicate the valid state or invalid state of a row address. It can be understood that n is an integer greater than 0, and n is equal to the number of row addresses. It is worth noting that in the address state signal, "0" can represent a valid state, "1” can represent an invalid state, or "1” can represent a valid state, and "0” can represent an invalid state, which is not limited here. The following is an example of 9 row addresses.
  • the states corresponding to the 9 row addresses and each row address can constitute a page table as shown in Table 1.
  • the state of the row address can be switched from LO to OP; when a new row address is obtained by random sampling, the state of the row address can be switched from OP to LO, so that the dynamic update of each row address can be guaranteed.
  • the shift signal can be a pulse signal.
  • the number of pulses of the shift signal can be the number of invalid row addresses in the plurality of row addresses arranged in sequence, which are located before the first valid row address plus 1.
  • a shift signal with 1 pulse is output; when RA_ADDR2 is in a valid state and RA_ADDR1 is in an invalid state, a shift signal with 2 pulses is output...
  • RA_ADDR9 is in a valid state and RA_ADDR1 to RA_ADDR8 are all in an invalid state, a shift signal with 9 pulses is output.
  • the state of the row address located after the first valid row address is not determined here.
  • RA_ADDR5 is in a valid state and RA_ADDR1 to RA_ADDR4 are all in an invalid state, the states of RA_ADDR6 to RA_ADDR9 are not determined, and a shift signal with 5 pulses is output.
  • the number of pulses of the shift signal is used as the number of shifts to shift and select a plurality of row addresses arranged in sequence, so that the row address selected after the shift is used as the row hammer address.
  • a circular shift register can be used to use the position of bit "1" in the circular shift register as a pointer to find the first valid address in the page table.
  • the initial position of the circular shift register can be Pointing to RA_ADDR9, when RA_ADDR1 is in a valid state, the number of pulses of the shift signal is 1, that is, it is shifted once, so that after the shift, it points to RA_ADDR1 and uses it as the row hammer address; when RA_ADDR2 is in a valid state and RA_ADDR1 is in an invalid state, the number of pulses of the shift signal is 2, that is, it is shifted twice, so that after the shift, it points to RA_ADDR2 and uses it as the row hammer address...
  • the number of pulses of the shift signal is 9, that is, it is shifted 9 times, so that after the shift, it points to RA_ADDR9 and uses it as the row hammer address. It is worth noting that although the initial position of the pointer can point to RA_ADDR9, it must be shifted downward in sequence, that is, when RA_ADDR9 is in a valid state and RA_ADDR1 to RA_ADDR8 are all in an invalid state, it still needs to be shifted 9 times in sequence to point to RA_ADDR9 again.
  • the first valid row address can be selected as the row hammer address through polling, and the row addresses adjacent to the row hammer address can be refreshed, thereby effectively reducing data errors and data losses caused by row hammer attacks.
  • outputting a shift signal according to the address status signal includes: based on the number of page table entries in the invalid state that are located before the first page table entry in the valid state among the multiple page table entries, outputting a shift signal with a corresponding number of pulses; selecting multiple page table entries according to the shift signal, and using the row address stored in the selected page table entry as a row hammer address, includes: outputting a pointer according to the number of pulses of the shift signal to shift-select multiple page table entries in a preset order, and using the row address in the page table entry pointed to by the pointer as the row hammer address; wherein the pointer initially points to the last page table entry.
  • generating a shift signal according to the address state signal includes: counting clock pulses and generating a counting signal; latching each bit of the address state signal in sequence according to the counting signal to output multiple latch state signals; outputting the shift signal according to the address state signal, the latch state signal and the counting signal, or according to the address state signal.
  • outputting the shift signal according to the address state signal includes: outputting a continuous first level as the shift signal according to the address state signal; the first level indicates that each bit of the address state signal indicates the invalid state.
  • outputting the shift signal according to the address state signal, the latch state signal and the count signal includes: according to the address state signal, outputting in sequence at least one operation result of the latch state signal and the count signal as the shift signal.
  • the operation results of at least one of the latch state signals and the counting signal are output in sequence as the shift signal, including: according to the address state signal, at least one of the latch state signals is selected and output in sequence; at least one of the latch state signals and the counting signal are operated in sequence to output the shift signal.
  • the method further includes: generating and outputting an automatic refresh signal according to an external command issued by the host end; and generating a first pulse of the shift signal according to the automatic refresh signal when at least one bit of the address status signal indicates the valid state.
  • the method further includes: disabling the shift signal generating circuit when the count value represented by the count signal is greater than a preset value.
  • the method further includes: sampling the row address; storing multiple row addresses in a page table includes: storing the sampled row address in the page table; when the sampled row address is received, switching the corresponding bit of the row address in the address status signal from the invalid state to the valid state.
  • the method further includes: determining, based on the row hammer address, at least one row address adjacent to the row hammer address as a row hammer refresh address; after completing the refresh operation on the row hammer refresh address, clearing the row address corresponding to the row hammer refresh address in the page table, and switching the corresponding bit of the row address in the address status signal from the valid state to the invalid state.
  • an embodiment of the present disclosure provides a refresh control circuit 200, comprising: an address selection circuit 100 as described in any of the above embodiments; a refresh circuit 201 for performing a refresh operation on at least one address line adjacent to the address line corresponding to the row hammer address.
  • the refresh control circuit 200 can be used to randomly sample multiple row addresses, and determine one of the row addresses as a row hammer address by polling, and then perform a refresh operation on at least one address line adjacent to the address line corresponding to the row hammer address to reduce data errors.
  • the refresh control circuit 200 includes an address selection circuit 100 and a refresh circuit 201.
  • the refresh circuit 201 can perform a refresh operation on at least one word line adjacent to the word line corresponding to the row hammer address according to the row hammer address output by the address selection circuit 100.
  • the refresh circuit 201 can be a row decoder (Row Decoder) circuit in a memory.
  • the address selection circuit 100 has an address operation circuit to determine the row hammer refresh address according to the row hammer address, so the refresh circuit 201 can directly refresh the word line corresponding to the row hammer refresh address.
  • an embodiment of the present disclosure provides a storage system 300, including: a memory 310, including a peripheral circuit 311 and a storage cell array 312; wherein the peripheral circuit 311 includes the address selection circuit 100 described in any of the above embodiments; and a storage controller 320.
  • the memory 310 may include but is not limited to DRAM, static random access memory (SRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.
  • the storage controller 320 can control the memory 310 to perform various operations according to the signal sent by the host. It can be understood that in the peripheral circuit 311 of the memory 310, each bit of the address state signal represents the valid state or invalid state of a corresponding row address, and the shift signal generating circuit generates a shift signal according to the address state signal, and the number of pulses of the shift signal is used to represent the number of invalid row addresses before the first valid row address among multiple row addresses. In this way, the first valid row address can be selected as the row hammer address by polling, and the row addresses adjacent to the row hammer address can be refreshed, thereby effectively reducing data errors and data loss caused by row hammer attacks in the memory 310.
  • each bit of the address state signal represents the valid state or invalid state of a corresponding address register unit
  • the shift signal generation circuit generates a shift signal according to the address state signal
  • the shift selection circuit selects multiple address register units according to the shift signal. In this way, the address selection circuit can select the first row address in a valid state as the row hammer address by polling, and refresh the row addresses adjacent to the row hammer address, thereby effectively reducing data errors caused by row hammer attack behaviors.

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Abstract

公开了一种地址选择电路、地址选择方法、刷新控制电路和存储系统，地址选择电路包括：多个地址寄存单元，配置为存储行地址；状态寄存单元，配置为存储并输出地址状态信号；地址状态信号的每一位表示对应的一个地址寄存单元的有效状态或无效状态；有效状态表示地址寄存单元中存储有行地址，无效状态表示地址寄存单元中未存储行地址；移位信号产生电路，用于根据地址状态信号，生成移位信号；移位选择电路，用于根据移位信号，对多个地址寄存单元进行选择，并将选择的地址寄存单元中存储的行地址作为行锤地址。

Description

地址选择电路、地址选择方法、刷新控制电路和存储系统
相关申请的交叉引用
本公开基于申请号为202310114718.2、申请日为2023年02月02日、发明名称为“地址选择电路、地址选择方法、刷新控制电路和存储系统”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种地址选择电路、地址选择方法、刷新控制电路和存储系统
背景技术
随着当今科学技术的不断发展，半导体存储装置的密度不断增加。高数据可靠性、高存取速度以及更小的芯片尺寸成为了半导体存储器发展的重要趋势。然而，存储器单元之间的电磁相互作用对存储器单元的影响增大，使得存储器单元数据丢失的可能性增加。
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是一种易失性存储器，其通过存储单元电容器中积累的电荷作为物理信号来存储信息。而存储单元中的电荷可随着时间的推移衰减，因此需要周期性地实行刷新操作，否则存储的数据信息将会丢失。在数据由于电荷的泄漏而丢失之前，可以通过再充电来维持在存储单元中存储的电荷。存储单元中电荷的这种再充电被称为刷新操作，并且在电荷显著丢失之前可以重复执行刷新操作，以重新补充电荷，避免存储数据发生错误。然而，当存储器单元中某一单行地址对应的字线被频繁开启时，会导致相邻地址的电容器在刷新操作到来之前发生不期望的电荷交互，造成数据错误和数据丢失。
发明内容
有鉴于此，本公开实施例提供了一种地址选择电路、地址选择方法、刷新控制电路和存储系统。
第一方面，本公开实施例提供了一种地址选择电路，包括：
多个地址寄存单元，配置为存储行地址；状态寄存单元，配置为存储并输出地址状态信号；所述地址状态信号的每一位用于表示对应的一个所述地址寄存单元的有效状态或无效状态；所述有效状态表示所述地址寄存单元中存储有所述行地址，所述无效状态表示所述地址寄存单元中未存储所述行地址；移位信号产生电路，用于根据所述地址状态信号，生成移位信号；移位选择电路，连接所述移位信号产生电路；所述移位选择电路用于根据所述移位信号，对多个所述地址寄存单元进行选择，并将选择的所述地址寄存单元中存储的所述行地址作为行锤地址。
在一些实施例中，所述地址寄存单元和所述状态寄存单元位于页表中；所述页表的每一页表项包括一个所述地址寄存单元中存储的所述行地址，以及所述地址寄存单元的有效状态或无效状态；所述移位信号产生电路具体用于基于多个所述地址寄存单元中，位于第一个处于所述有效状态的所述地址寄存单元之前的处于所述无效状态的所述地址寄存单元的个数，生成具有对应脉冲数量的移位信号；所述移位选择电路具体用于根据所述移位信号的脉冲数量输出指针，以对多个所述页表项 进行选择，并将指针指向的所述页表项中的所述行地址作为所述行锤地址。
在一些实施例中，所述移位信号产生电路包括：计数单元，配置为对时钟脉冲计数，并生成计数信号；多个锁存单元，所述锁存单元连接所述计数单元和所述状态寄存单元；多个所述锁存单元配置为根据所述计数信号，依次锁存所述地址状态信号的每一位，以输出多个锁存状态信号；仲裁单元，连接所述计数单元、多个所述锁存单元和所述状态寄存单元；所述仲裁单元配置为根据所述地址状态信号，所述锁存状态信号和所述计数信号，或根据所述地址状态信号，输出所述移位信号。
在一些实施例中，所述仲裁单元具体配置为根据所述地址状态信号，依次输出至少一个所述锁存状态信号与所述计数信号的运算结果，以作为所述移位信号。
在一些实施例中，所述仲裁单元具体配置为根据所述地址状态信号，输出持续的第一电平，以作为所述移位信号；所述第一电平表示所述地址状态信号的每一位都表示所述无效状态。
在一些实施例中，所述仲裁单元包括：选择单元，连接多个所述锁存单元和所述状态寄存单元；所述选择单元配置为根据所述地址状态信号，依次选择并输出至少一个所述锁存状态信号；运算单元，连接所述选择单元和所述计数单元；所述运算单元配置为依次将至少一个所述锁存状态信号与所述计数信号进行运算，以输出所述移位信号。
在一些实施例中，所述地址选择电路还包括：命令解码电路，连接所述仲裁单元；所述命令解码电路用于根据主机端发出的外部命令，生成并输出自动刷新信号；在所述地址状态信号的至少一位表示所述有效状态的情况下，所述仲裁单元还配置为根据所述自动刷新信号，生成所述移位信号的第一个脉冲。
在一些实施例中，所述地址选择电路还包括：控制逻辑，连接所述计数单元；所述控制逻辑用于在所述计数信号表示的计数值大于预设值的情况下，禁用所述移位信号产生电路。
在一些实施例中，所述地址选择电路还包括：地址采样电路，连接所述地址寄存单元；所述地址采样电路用于采样行地址，并将采样到的所述行地址输出至所述地址寄存单元；当所述地址寄存单元接收到所述地址采样电路输出的所述行地址时，所述控制逻辑还用于将所述行地址在所述地址状态信号中的对应位由所述无效状态切换为所述有效状态。
在一些实施例中，所述地址选择电路还包括：地址运算电路，连接所述移位选择电路；所述地址运算电路用于根据所述行锤地址，确定所述行锤地址相邻的至少一条行地址为行锤刷新地址；在对所述行锤刷新地址完成刷新操作后，所述控制逻辑还用于将所述行锤刷新地址对应的所述地址寄存单元中存储的所述行地址清空，并将所述行地址在所述地址状态信号中的对应位由所述有效状态切换为所述无效状态。
在一些实施例中，所述地址选择电路用于在刷新控制电路中提供所述行锤地址，所述刷新控制电路还包括：刷新电路，用于对与所述行锤地址对应的地址线相邻的至少一条地址线进行刷新操作。
第二方面，本公开实施例提供了一种地址选择方法，包括：在页表中存储多个行地址和地址状态信号；所述地址状态信号的每一位用于表示对应的一个页表项的有效状态或无效状态；所述有效状态表示所述页表项中存储有所述行地址，所述无效状态表示所述页表项中未存储所述行地址；根据所述地址状态信号，输出移位信号；根据所述移位信号，对多个所述页表项进行选择，并将选择的所述页表项中存储的所述行地址作为行锤地址。
在一些实施例中，所述根据所述地址状态信号，输出移位信号，包括：基于多个所述页表项中，位于第一个处于所述有效状态的所述页表项之前的处于所述无效状态的所述页表项的个数，输出具有对应脉冲数量的移位信号；所述根据所述移位信号，对多个所述页表项进行选择，并将选择的所述页表项中存储的所述行地址作为行锤地址，包括：根据所述移位信号的脉冲数量输出指针，以按照预设顺序对多个所述页表项进行移位选择，并将指针指向的所述页表项中的所述行地址作为所述行锤地址。
在一些实施例中，所述根据所述地址状态信号，生成移位信号，包括：对时钟脉冲计数，并生成计数信号；根据所述计数信号，依次锁存所述地址状态信号的每一位，以输出多个锁存状态信号；根据所述地址状态信号，所述锁存状态信号和所述计数信号，或根据所述地址状态信号，输出所述移位信号。
在一些实施例中，所述根据所述地址状态信号，输出所述移位信号，包括：根据所述地址状态信号，输出持续的第一电平，以作为所述移位信号；所述第一电平表示所述地址状态信号的每一位都表示所述无效状态。
在一些实施例中，所述根据所述地址状态信号，所述锁存状态信号和所述计数信号，输出所述移位信号，包括：根据所述地址状态信号，依次输出至少一个所述锁存状态信号与所述计数信号的运算结果，以作为所述移位信号。
在一些实施例中，所述根据所述地址状态信号，依次输出至少一个所述锁存状态信号与所述计数信号的运算结果，以作为所述移位信号，包括：根据所述地址状态信号，依次选择并输出至少一个所述锁存状态信号；依次将至少一个所述锁存状态信号与所述计数信号进行运算，以输出所述移位信号。
在一些实施例中，所述方法还包括：根据主机端发出的外部命令，生成并输出自动刷新信号；在所述地址状态信号的至少一位表示所述有效状态的情况下，根据所述自动刷新信号，生成所述移位信号的第一个脉冲。
在一些实施例中，所述方法还包括：在所述计数信号表示的计数值大于预设值的情况下，禁用所述移位信号产生电路。
在一些实施例中，所述方法还包括：采样所述行地址；所述在页表中存储多个行地址，包括：在页表中存储采样到的所述行地址；当接收到采样到的所述行地址时，将所述行地址在所述地址状态信号中的对应位由所述无效状态切换为所述有效状态。
在一些实施例中，所述方法还包括：根据所述行锤地址，确定所述行锤地址相邻的至少一条行地址为行锤刷新地址；在对所述行锤刷新地址完成刷新操作后，清空所述页表中与所述行锤刷新地址对应的所述行地址，并将所述行地址在所述地址状态信号中的对应位由所述有效状态切换为所述无效状态。
第三方面，本公开实施例提供了一种存储系统，包括：存储器，包括外围电路和存储单元阵列；其中，所述外围电路包括上述实施例中任一所述的地址选择电路；存储控制器。
在本公开实施例提供的地址选择电路中，地址状态信号的每一位表示对应的一个地址寄存单元的有效状态或无效状态，移位信号产生电路根据地址状态信号，生成移位信号，移位选择电路根据移位信号对多个地址寄存单元进行选择。如此，地址选择电路可以通过轮询的方式，选择第一个处于有效状态的行地址作为行锤地址，并对行锤地址相邻的行地址进行刷新，从而有效减少行锤攻击行为带来的数据错误。
附图说明
图1为本公开实施例提供的一种地址选择电路的示意图；
图2为本公开实施例提供的一种移位选择电路的示意图；
图3为本公开实施例提供的一种移位信号产生电路的示意图；
图4为本公开实施例提供的一种移位信号产生电路的工作时序图；
图5为本公开实施例提供的另一种移位信号产生电路的工作时序图；
图6为本公开实施例提供的又一种移位信号产生电路的工作时序图；
图7为本公开实施例提供的再一种移位信号产生电路的工作时序图；
图8为本公开实施例提供的一种仲裁单元的示意图；
图9为本公开实施例提供的另一种地址选择电路的示意图；
图10为本公开实施例提供的又一种地址选择电路的示意图；
图11为本公开实施例提供的一种地址选择方法的步骤流程图；
图12为本公开实施例提供的一种刷新控制电路的示意图；
图13为本公开实施例提供的一种存储系统的示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在一些实施例中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即这里可以不描述实际实施例的全部特征，不详细描述公知的功能和结构。
一般地，术语可以至少部分地从上下文中的使用来理解。例如，至少部分地取决于上下文，如本文中所用的术语“一个或多个”可以用于以单数意义描述任何特征、结构或特性，或者可以用于以复数意义描述特征、结构或特性的组合。类似地，诸如“一”或“所述”的术语同样可以被理解为传达单数用法或传达复数用法，这至少部分地取决于上下文。另外，属于“基于”可以被理解为不一定旨在传达排他的一组因素，并且可以替代地允许存在不一定明确地描述的附加因素，这同样至少部分地取决于上下文。
除非另有定义，本文所使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
在一些实施例中，存储器中存储单元的电容尺寸较小，使得存储单元的噪声裕度较小，容易受到干扰。此外，由于相邻存储单元之间的距离较小，存储单元更容易受到电磁耦合的影响而产生意想不到的场效应。具体地，存储器的常规刷新包括激活(Active，Act)和预充电(Precharge，Pre)操作。在一个刷新窗口时间内，当存储器中的某一根字线(Word Line)连续进行多次的激活操作时，可能会导致相邻地址的电容器在常规刷新信号到来之前发生数据翻转，进而产生错误的存储，这种现象一般称为行锤(Row Hammer)。其中，每条字线对应一个行地址，被重复进行存取访问的行被称为攻击者行(Aggressor Row)或者锤击行(Hammered Row)，攻击者行的地址即行锤地址，而与攻击者行相邻近的行则被称为受害者行(Victim Row)。行锤刷新(Row Hammer Refresh)即在存储器工作一段时间后，对受害者行进行刷新，保证其数据正确，其中，受害者行的地址即行锤刷新地址，而造成数据损坏的攻击者行的访问次数即行锤阈值。值得注意的是，行锤攻击行为会导致受害者行发生数据翻转，包括但不限于从“1”翻转到“0”，以及从“0”翻转到“1”。在一些实施例中，存储器以一定的时间间隔自动执行自动刷新(Auto Refresh，AR)操作，故存储器可以将自动刷新 作为行锤刷新，以刷新受害者行，这里两次自动刷新的时间间隔可以根据存储器的工作情况进行调整。
第一方面，如图1所示，本公开实施例提供了一种地址选择电路100，包括：多个地址寄存单元101，配置为存储行地址；状态寄存单元102，配置为存储并输出地址状态信号ST_OPEN；所述地址状态信号ST_OPEN的每一位用于表示对应的一个所述地址寄存单元101的有效状态或无效状态；所述有效状态表示所述地址寄存单元101中存储有所述行地址，所述无效状态表示所述地址寄存单元101中未存储所述行地址；移位信号产生电路110，用于根据所述地址状态信号ST_OPEN，生成移位信号Shift_reg_clk；移位选择电路120，连接所述移位信号产生电路110；所述移位选择电路120用于根据所述移位信号Shift_reg_clk，对多个所述地址寄存单元101进行选择，并将选择的所述地址寄存单元101中存储的所述行地址作为行锤地址。
应当理解的是，图中为了使得各个电路和单元均能被清晰示出，可能造成各电路和单元的尺寸比例、位置关系与实际结构不符。
在本公开实施例中，地址选择电路100中可以具有页表，页表可以位于DRAM的外围电路区域中靠近存储阵列区域的位置。页表中可以存储多个行地址、表示每个行地址的访问次数的第一计数值，以及每个页表项的状态等。且可以通过数据指针，以指向页表中对应的页表项。示例性地，页表中具有9个页表项，即页表中存储有9个行地址、9个行地址对应的第一计数值及每个页表项的状态。每一页表项中各存储内容具有对应关系，且可以通过页表的索引号找到，通过数据指针而指向。
在本公开实施例中，地址选择电路100中可以具有多个地址寄存单元101，地址寄存单元101配置为存储行地址，以及输出自身存储的行地址。这里的每个行地址在物理上可以对应于存储器中的一条字线，进行激活操作的行地址可以通过随机采样的方式被寄存到到地址寄存单元101中。随机采样方式例如可以为：通过线性反馈移位寄存器产生伪随机数；或者振荡器产生的随机脉冲的方式等方式。可以理解的是，这里的每个地址寄存单元101可以配置为存储一个行地址。
状态寄存单元102配置为存储上述地址寄存单元101中行地址对应的地址状态，并输出地址状态信号ST_OPEN。示例性地，地址状态信号ST_OPEN可以为n位的二进制数，其中每一位为“0”或者为“1”，用于表示一个行地址的有效(Lock，LO)状态或无效(Open，OP)状态，可以理解的是，n为大于0的整数，且n与地址寄存单元101的数量相等。值得注意的是，地址状态信号ST_OPEN中，既可以是“0”代表有效状态，“1”代表无效状态，也可以是“1”代表有效状态，“0”代表无效状态，这里不作限制。下面以地址选择电路100中具有9个地址寄存单元101为例进行说明，9个行地址与每个行地址对应的状态可以构成如表1所示的一个页表。在一些实施例中，当地址寄存单元101中的行地址被作为行锤地址，并将行锤地址相邻的行地址进行刷新操作之后，可以将该行地址的状态由LO切换为OP；当通过随机采样，将新的行地址输入至地址寄存单元101中时，可以将该行地址的状态由OP切换为LO，如此，可以保证页表中各个行地址的动态更新。
移位信号产生电路110可以连接状态寄存单元102，并配置为根据地址状态信号ST_OPEN，生成移位信号Shift_reg_clk，移位信号Shift_reg_clk可以为脉冲信号。在一些实施例中，移位信号Shift_reg_clk的第一个脉冲是根据自动刷新信号生成的，故移位信号的脉冲数量可以为顺序排列的多个行地址中，位于第一个处于有效状态的行地址之前的处于无效状态的行地址的数量加1。示例性地，在RA_ADDR1为有效状态的情况下，移位信号产生电路110输出具有1个脉冲的移位信号；在RA_ADDR2为有效状态，且RA_ADDR1为无效状态的情况下，移位信号产生电路110输出具有2个脉冲的移位信号……在RA_ADDR9为有效状态，且RA_ADDR1至RA_ADDR8均为无效状态的情况下，移位信号产生电路110输出具有9个脉冲的移位信号。可以理解的是，移位信号产生电路110并不判断位于第一个处于有效状态的行地址之后的行地址的状态，示例性地，若RA_ADDR5为 有效状态，且RA_ADDR1至RA_ADDR4均为无效状态的情况下，移位信号产生电路110不判断RA_ADDR6至RA_ADDR9的状态，并输出具有5个脉冲的移位信号。
表1
移位选择电路120可以连接多个地址寄存单元101和移位信号产生电路110，移位选择电路120用于将移位信号Shift_reg_clk的脉冲数量作为移位的次数，以对顺序排列的多个地址寄存单元101进行移位选择，从而将移位之后选择的行地址作为行锤地址。如图2所示，移位选择电路120可以为循环移位寄存器(Circular Shift Register，CSR)，以将bit“1”在循环移位寄存器中的位置作为指针，查找页表中的第一个有效地址。示例性地，移位选择电路120的初始位置可以指向RA_ADDR9，在RA_ADDR1为有效状态的情况下，移位信号的脉冲数量为1，移位选择电路120移位1次，从而在移位后指向RA_ADDR1，并将其作为行锤地址；在RA_ADDR2为有效状态，而RA_ADDR1为无效状态的情况下，移位信号的脉冲数量为2，移位选择电路120移位2次，从而在移位后指向RA_ADDR2，并将其作为行锤地址……在RA_ADDR9为有效状态，而RA_ADDR1至RA_ADDR8均为无效状态的情况下，移位信号的脉冲数量为9，移位选择电路120移位9次，从而在移位后指向RA_ADDR9，并将其作为行锤地址。值得注意的是，尽管移位选择电路120的初始位置可以指向RA_ADDR9，但移位选择电路120必须依次向下移位选择，即在RA_ADDR9为有效状态，而RA_ADDR1至RA_ADDR8均为无效状态的情况下，移位选择电路120仍需要依次移位9次，从而再次指向RA_ADDR9。
如此，地址选择电路100可以通过轮询(Round Robin)的方式，选择第一个处于有效状态的行地址作为行锤地址，并对行锤地址相邻的行地址进行刷新，从而有效减少行锤攻击行为带来的数据错误和数据丢失。
在一些实施例中，存储器需要在刷新周期时间(Time for Refresh Cycle，tRFC)内，完成对行锤地址相邻的行地址的刷新操作，也就是说，行锤地址的选择过程需要在两次自动刷新的时间间隔内完成。由于地址选择电路的工作同步于自动刷新信号，因此，如果仅将自动刷新信号作为循环移位寄存器的移位时钟，则无法在两次自动刷新的时间间隔内，进行多次移位查找。可以理解的是，本公开实施例提供的地址选择电路，通过移位信号产生电路生成移位信号，以轮询的方式在两次自动刷新的时间间隔内进行移位查找，从而确定行锤地址。
在一些实施例中，所述地址寄存单元101和所述状态寄存单元102位于页表中；所述页表的每一页表项包括一个所述地址寄存单元101中存储的所述行地址，以及所述地址寄存单元101的有效状态或无效状态；所述移位信号产生电路110具体用于基于多个所述地址寄存单元101中，位于第一个处于所述有效状态的所述地址寄存单元101之前的处于所述无效状态的所述地址寄存单元101的个数，生成具有对应脉冲数量的移位信号Shift_reg_clk；所述移位选择电路120具体用于根据所述移位信号Shift_reg_clk的脉冲数量输出指针，以对多个所述页表项进行选择，并将指针指向的所述 页表项中的所述行地址作为所述行锤地址。
在本公开实施例中，各个页表项可以参考表1进行理解，值得注意的是，移位选择电路120输出的指针的初始位置可以指向最后一个页表项，即索引号9对应的页表项，而根据移位信号Shift_reg_clk的脉冲数量，指针便会从初始位置依次向下移动对应的次数，并将最终指向的页表项中的行地址作为行锤地址。
在一些实施例中，如图3所示，所述移位信号产生电路110包括：计数单元111，配置为对时钟脉冲计数，并生成计数信号CNT_EQ；多个锁存单元112，所述锁存单元112连接所述计数单元111和所述状态寄存单元；多个所述锁存单元112配置为根据所述计数信号CNT_EQ，依次锁存所述地址状态信号ST_OPEN的每一位，以输出多个锁存状态信号ST_OPEN_LAT；仲裁单元113，连接所述计数单元111、多个所述锁存单元112和所述状态寄存单元102；所述仲裁单元113配置为根据所述地址状态信号ST_OPEN，所述锁存状态信号ST_OPEN_LAT和所述计数信号CNT_EQ，或根据所述地址状态信号ST_OPEN，输出所述移位信号Shift_reg_clk。
在一些实施例中，所述仲裁单元具体配置为根据所述地址状态信号，依次输出至少一个所述锁存状态信号与所述计数信号的运算结果，以作为所述移位信号。
在一些实施例中，所述仲裁单元具体配置为根据所述地址状态信号，输出持续的第一电平，以作为所述移位信号；所述第一电平表示所述地址状态信号的每一位都表示所述无效状态。这里的第一电平既可以为高电平，也可以为低电平，而持续的第一电平即代表跳过，从而使得移位选择电路不进行移位选择，即在下一次自动刷新信号到来时，存储器不进行行锤刷新。
在本公开实施例中，计数单元111可以对时钟脉冲CLK进行计数，以输出计数信号CNT_EQ，这里的计数信号CNT_EQ可以为脉冲信号。在一些实施例中，计数单元111可以为4bit的二进制计数器，计数单元111可以包括至少一个T’触发器。在一些实施例中，计数单元111还可以响应于自动刷新信号复位，从而将计数信号表示的计数值重置。
多个锁存单元112可以根据计数信号CNT_EQ，依次锁存地址状态信号ST_OPEN的每一位表示的有效状态或无效状态，从而输出多个锁存状态信号ST_OPEN_LAT，锁存单元112的数量可以与地址寄存单元的数量相同。值得注意的是，每个锁存单元112可以连接至状态寄存单元和计数单元111。图4、图5和图6分别示出了RA_ADDR1、RA_ADDR2、RA_ADDR9为第一个处于有效状态的行地址的情况下，各个信号的时序图。可以理解的是，锁存状态信号ST_OPEN_LAT由低电平转变为高电平表示无效状态，每个锁存单元112可以根据计数信号CNT_EQ的一个上升沿，生成一个锁存状态信号ST_OPEN_LAT，且锁存状态信号ST_OPEN_LAT的电平改变时刻与计数信号CNT_EQ中对应的一个上升沿对齐。示例性地，如图6所示，ST_OPEN_LAT<1>的电平改变时刻与计数信号CNT_EQ的第1个上升沿对齐，ST_OPEN_LAT<2>的电平改变时刻与计数信号CNT_EQ的第2个上升沿对齐……ST_OPEN_LAT<8>的电平改变时刻与计数信号CNT_EQ的第8个上升沿对齐。而锁存状态信号ST_OPEN_LAT保持低电平则表示对应行地址的有效状态，具体可以参考图6中示出的ST_OPEN_LAT<9>。
仲裁单元113可以连接计数单元111、多个锁存单元112和状态寄存单元102。在地址状态信号ST_OPEN的至少一位表示有效状态的情况下，仲裁单元113根据地址状态信号ST_OPEN中第一个有效状态的所在位，将至少一个锁存状态信号ST_OPEN_LAT与计数信号CNT_EQ的运算结果输出，以作为移位信号Shift_reg_clk，这里的运算可以为与运算(AND)。示例性地，如图4所示，地址状态信号ST_OPEN为“9’bxxxxxxxx0”，其中“0”代表第一个有效状态，“x”代表有效状态或无效状态不予判断，如此，根据地址状态信号，仲裁单元仅输出ST_OPEN_LAT<1>与CNT_EQ的运算结果，以作为移位信号Shift_reg_clk。如图5所示，地址状态信号ST_OPEN为“9’bxxxxxxx01”，其中“1”代表无效状态，如此，根据地址状态信号，仲裁单元依次输出ST_OPEN_LAT<1>与CNT_EQ、 以及ST_OPEN_LAT<2>与CNT_EQ的运算结果，以作为移位信号Shift_reg_clk。如图6所示，地址状态信号ST_OPEN为“9’b011111111”，如此，根据地址状态信号，仲裁单元依次输出ST_OPEN_LAT<1>与CNT_EQ、ST_OPEN_LAT<2>与CNT_EQ……以及ST_OPEN_LAT<9>与CNT_EQ的运算结果，以作为移位信号Shift_reg_clk。值得注意的是，在一些实施例中，移位信号Shift_reg_clk的第一个脉冲是根据自动刷新信号生成的。
如图7所示，在地址状态信号ST_OPEN的所有位都表示无效状态的情况下，仲裁单元113可以输出持续高电平，以作为移位信号Shift_reg_clk，这里的持续高电平即代表跳过(Skip)，从而使得移位选择电路不进行移位选择，即在下一次自动刷新信号到来时，存储器不进行行锤刷新。具体地，不同行地址的状态对应的移位次数可以参考表2，其中“X”代表有效状态或无效状态不予判断。值得注意的是，表2中用索引号1至9分别代表行地址RA_ADDR1至RA_ADDR9，移位次数即移位信号Shift_reg_clk中的脉冲数量。
由于移位信号产生电路110包括计数单元111、锁存单元112和仲裁单元113，并采用轮询的方式生成移位信号，故移位信号产生电路110具有面积小，运行速度快，可重用度高等优点。
表2
在一些实施例中，如图8所示，所述仲裁单元113包括：选择单元114，连接多个所述锁存单元和所述状态寄存单元；所述选择单元配置为根据所述地址状态信号ST_OPEN，依次选择并输出至少一个所述锁存状态信号ST_OPEN_LAT；运算单元115，连接所述选择单元114和所述计数单元；所述运算单元配置为依次将至少一个所述锁存状态信号ST_OPEN_LAT与所述计数信号CNT_EQ进行运算，以输出所述移位信号Shift_reg_clk。
在本公开实施例中，选择单元114可以为数据选择器(Multiplexer，MUX)，从而根据地址状态信号ST_OPEN，依次选择并输出至少一个锁存状态信号ST_OPEN_LAT。运算单元115可以为与门(AND)，并配置为依次将至少一个锁存状态信号ST_OPEN_LAT与计数信号CNT_EQ进行与运算，以输出移位信号Shift_reg_clk。
这里以RA_ADDR5为第一个处于有效状态的行地址为例进行说明，此时地址状态信号ST_OPEN为“9’bxxxx01111”，故选择单元114依次选择并输出ST_OPEN_LAT<1>至ST_OPEN_LAT<5>，而ST_OPEN_LAT<6>以及之后的锁存状态信号则不进行输出。如此，仲裁单元113根据自动刷新信号生成移位信号Shift_reg_clk的第1个脉冲；在选择单元114输出ST_OPEN_LAT<1>的情况下，运算单元115将ST_OPEN_LAT<1>与CNT_EQ进行与运算，从而生成移位信号Shift_reg_clk的第2个脉冲；在选择单元114输出ST_OPEN_LAT<2>的情况下，运算单元115将ST_OPEN_LAT<2>与CNT_EQ进行与运算，从而生成移位信号Shift_reg_clk的第3个脉 冲……在选择单元114输出ST_OPEN_LAT<4>的情况下，运算单元115将ST_OPEN_LAT<4>与CNT_EQ进行与运算，从而生成移位信号Shift_reg_clk的第5个脉冲；在选择单元114输出ST_OPEN_LAT<5>的情况下，运算单元115将ST_OPEN_LAT<5>与CNT_EQ进行与运算，由于ST_OPEN_LAT<5>表示有效状态，即为低电平，故无法在移位信号Shift_reg_clk中生成脉冲。由此，通过选择单元114和运算单元115，可以生成具有5个脉冲的移位信号Shift_reg_clk。
在一些实施例中，仲裁单元还可以包括多个运算单元和一个选择单元，这里运算单元的数量可以与锁存单元的数量相等。每个运算单元的输入端连接计数单元和一个锁存单元，而选择单元的输入端则连接多个运算单元输出端。也就是说，每个锁存状态信号ST_OPEN_LAT先与计数信号CNT_EQ进行运算，然后选择单元依次输出串行的多个比较结果，以作为移位信号Shift_reg_clk。
在一些实施例中，如图9所示，所述地址选择电路100还包括：命令解码电路130，连接所述仲裁单元113；所述命令解码电路130用于根据主机端发出的外部命令，生成并输出自动刷新信号AR；在所述地址状态信号ST_OPEN的至少一位表示所述有效状态的情况下，所述仲裁单元113还配置为根据所述自动刷新信号，生成所述移位信号Shift_reg_clk的第一个脉冲。
在本公开实施例中，命令解码电路130可以对主机端中存储控制器(Memory Controller，MC)发送的外部命令进行解码，这里的外部命令包括但不限于刷新命令(Refresh，REF)、刷新管理命令(Refresh Management，RFM)、自动刷新命令、激活命令等。命令解码电路130根据自动刷新命令生成并输出自动刷新信号，而在至少一个行地址为有效状态的情况下，仲裁单元113可以根据自动刷新信号AR，生成移位信号Shift_reg_clk的第一个脉冲。
在一些实施例中，如图9所示，所述地址选择电路还包括：控制逻辑140，连接所述计数单元111；所述控制逻辑140用于在所述计数信号CNT_EQ表示的计数值大于预设值的情况下，禁用所述移位信号产生电路110。
这里以地址选择电路中具有9个地址寄存单元为例进行说明，在计数单元产生的计数值大于预设值9的情况下，可以确定9个行地址的状态都经过了移位信号产生电路110的判断，此时控制逻辑140可以禁用移位信号产生电路110，以降低系统功耗。值得注意的是，预设值可以与地址寄存单元的数量相同，也可以与地址寄存单元的数量不同，这里不作限制。
在一些实施例中，如图9所示，所述地址选择电路100还包括：地址采样电路150，连接所述地址寄存单元101；所述地址采样电路150用于随机采样行地址，并将采样到的所述行地址输出至所述地址寄存单元101；当所述地址寄存单元101接收到所述地址采样电路150输出的所述行地址时，所述控制逻辑140还用于将所述行地址在所述地址状态信号ST_OPEN中的对应位由所述无效状态切换为所述有效状态。
在本公开实施例中，地址采样电路150可以响应于激活信号，对激活信号对应的行地址进行随机抓取，并将抓取到的行地址存储至地址寄存单元101中。当地址寄存单元101接收到来自于地址采样电路150采样到的新的行地址时，控制逻辑140可以将状态寄存单元102中的地址状态信号ST_OPEN的对应位，由无效状态切换为有效状态。
在一些实施例中，如图9所示，所述地址选择电路100还包括：地址运算电路160，连接所述移位选择电路120；所述地址运算电路160用于根据所述行锤地址，确定所述行锤地址相邻的至少一条行地址为行锤刷新地址；在对所述行锤刷新地址完成刷新操作后，所述控制逻辑140还用于将所述行锤刷新地址对应的所述地址寄存单元101中存储的所述行地址清空，并将所述行地址在所述地址状态信号中的对应位由所述有效状态切换为所述无效状态。
在本公开实施例中，地址运算电路160可以将行锤地址相邻的至少一条行地址作为行锤刷新地址，这里的行锤刷新地址即为受害者行。如此，在tRFC内对受害者行对应的字线执行行锤刷新操作，可以减少行锤攻击行为带来的数据错误，提高存储器工作的可靠性。在一些实施例中，根据存储器 的性能和功耗要求，可以选择与行锤地址相邻的一条行地址作为行锤刷新地址进行刷新，以降低功耗；也可以选择与行锤地址相邻的多条行地址进行刷新，以提高刷新受害行的准确性。
当对受害者行完成刷新操作之后，控制逻辑140可以将行锤刷新地址对应的地址寄存单元101中存储的行地址清空，并将该行地址在地址状态信号ST_OPEN中的对应位由有效状态切换为无效状态。如此，可以动态更新多个地址寄存单元101中存储的行地址，进一步地提高生成行锤地址的准确性。
在一些实施例中，如图10所示为地址选择电路100的局部示意图，地址选择电路100还包括：与多个地址寄存单元101一一对应的多个第二计数单元103，第二计数单元103配置为对地址寄存单元101中存储的行地址的激活次数进行计数，并输出第二计数值；比较电路104，连接多个第二计数单元103，配置为比较多个第二计数值，并输出其中的最小计数值；控制逻辑140还连接比较电路104，控制逻辑140还用于将最小计数值对应的地址寄存单元101中存储的行地址清空，并将最小计数值对应的行地址在地址状态信号中的对应位由有效状态切换为无效状态。如此，可以将最小计数值对应的行地址替换为新的行地址，以确保地址寄存单元101中存储是激活次数较多的字线对应的行地址，从而进一步地提高生成行锤地址的准确性。
第二方面，如图11所示，本公开实施例提供了一种地址选择方法，包括：
步骤S10、在页表中存储多个行地址和地址状态信号；所述地址状态信号的每一位用于表示对应的一个页表项的有效状态或无效状态；所述有效状态表示所述页表项中存储有所述行地址，所述无效状态表示所述页表项中未存储所述行地址；
步骤S20、根据所述地址状态信号，输出移位信号；
步骤S30、根据所述移位信号，对多个所述页表项进行选择，并将选择的所述页表项中存储的所述行地址作为行锤地址。
在本公开实施例中，可以存储并输出多个行地址和一个地址状态信号。这里的每个行地址在物理上可以对应于存储器中的一条字线，多个行地址可以通过从激活操作的行地址中随机采样获得。地址状态信号可以为n位的二进制数，其中每一位为“0”或者为“1”，用于表示一个行地址的有效状态或无效状态，可以理解的是，n为大于0的整数，且n与行地址的数量相等。值得注意的是，地址状态信号中，既可以是“0”代表有效状态，“1”代表无效状态，也可以是“1”代表有效状态，“0”代表无效状态，这里不作限制。下面以9个行地址为例进行说明，9个行地址与每个行地址对应的状态可以构成如表1所示的一个页表。在一些实施例中，当其中一个行地址被作为行锤地址，并将行锤地址相邻的行地址进行刷新操作之后，可以将该行地址的状态由LO切换为OP；当通过随机采样，获得新的行地址时，可以将该行地址的状态由OP切换为LO，如此，可以保证各个行地址的动态更新。
根据地址状态信号，生成移位信号，这里的移位信号可以为脉冲信号，移位信号的脉冲数量可以为顺序排列的多个行地址中，位于第一个处于有效状态的行地址之前的处于无效状态的行地址的数量加1。示例性地，在RA_ADDR1为有效状态的情况下，输出具有1个脉冲的移位信号；在RA_ADDR2为有效状态，且RA_ADDR1为无效状态的情况下，输出具有2个脉冲的移位信号……在RA_ADDR9为有效状态，且RA_ADDR1至RA_ADDR8均为无效状态的情况下，输出具有9个脉冲的移位信号。可以理解的是，这里并不判断位于第一个处于有效状态的行地址之后的行地址的状态，示例性地，若RA_ADDR5为有效状态，且RA_ADDR1至RA_ADDR4均为无效状态的情况下，不判断RA_ADDR6至RA_ADDR9的状态，并输出具有5个脉冲的移位信号。
将移位信号的脉冲数量作为移位的次数，以对顺序排列的多个行地址进行移位选择，从而将移位之后选择的行地址作为行锤地址。这里可以利用循环移位寄存器，以将bit“1”在循环移位寄存器中的位置作为指针，查找页表中的第一个有效地址。示例性地，循环移位寄存器的初始位置可以 指向RA_ADDR9，在RA_ADDR1为有效状态的情况下，移位信号的脉冲数量为1，即移位1次，从而在移位后指向RA_ADDR1，并将其作为行锤地址；在RA_ADDR2为有效状态，而RA_ADDR1为无效状态的情况下，移位信号的脉冲数量为2，即移位2次，从而在移位后指向RA_ADDR2，并将其作为行锤地址……在RA_ADDR9为有效状态，而RA_ADDR1至RA_ADDR8均为无效状态的情况下，移位信号的脉冲数量为9，即移位9次，从而在移位后指向RA_ADDR9，并将其作为行锤地址。值得注意的是，尽管指针的初始位置可以指向RA_ADDR9，但必须依次向下移位选择，即在RA_ADDR9为有效状态，而RA_ADDR1至RA_ADDR8均为无效状态的情况下，仍需要依次移位9次，从而再次指向RA_ADDR9。
如此，可以通过轮询的方式，选择第一个处于有效状态的行地址作为行锤地址，并对行锤地址相邻的行地址进行刷新，从而有效减少行锤攻击行为带来的数据错误和数据丢失。
在一些实施例中，所述根据所述地址状态信号，输出移位信号，包括：基于多个所述页表项中，位于第一个处于所述有效状态的所述页表项之前的处于所述无效状态的所述页表项的个数，输出具有对应脉冲数量的移位信号；所述根据所述移位信号，对多个所述页表项进行选择，并将选择的所述页表项中存储的所述行地址作为行锤地址，包括：根据所述移位信号的脉冲数量输出指针，以按照预设顺序对多个所述页表项进行移位选择，并将指针指向的所述页表项中的所述行地址作为所述行锤地址；其中，所述指针初始指向最后一个所述页表项。
在一些实施例中，所述根据所述地址状态信号，生成移位信号，包括：对时钟脉冲计数，并生成计数信号；根据所述计数信号，依次锁存所述地址状态信号的每一位，以输出多个锁存状态信号；根据所述地址状态信号，所述锁存状态信号和所述计数信号，或根据所述地址状态信号，输出所述移位信号。
在一些实施例中，所述根据所述地址状态信号，输出所述移位信号，包括：根据所述地址状态信号，输出持续的第一电平，以作为所述移位信号；所述第一电平表示所述地址状态信号的每一位都表示所述无效状态。
在一些实施例中，所述根据所述地址状态信号，所述锁存状态信号和所述计数信号，输出所述移位信号，包括：根据所述地址状态信号，依次输出至少一个所述锁存状态信号与所述计数信号的运算结果，以作为所述移位信号。
在一些实施例中，所述根据所述地址状态信号，依次输出至少一个所述锁存状态信号与所述计数信号的运算结果，以作为所述移位信号，包括：根据所述地址状态信号，依次选择并输出至少一个所述锁存状态信号；依次将至少一个所述锁存状态信号与所述计数信号进行运算，以输出所述移位信号。
在一些实施例中，所述方法还包括：根据主机端发出的外部命令，生成并输出自动刷新信号；在所述地址状态信号的至少一位表示所述有效状态的情况下，根据所述自动刷新信号，生成所述移位信号的第一个脉冲。
在一些实施例中，所述方法还包括：在所述计数信号表示的计数值大于预设值的情况下，禁用所述移位信号产生电路。
在一些实施例中，所述方法还包括：采样所述行地址；所述在页表中存储多个行地址，包括：在页表中存储采样到的所述行地址；当接收到采样到的所述行地址时，将所述行地址在所述地址状态信号中的对应位由所述无效状态切换为所述有效状态。
在一些实施例中，所述方法还包括：根据所述行锤地址，确定所述行锤地址相邻的至少一条行地址为行锤刷新地址；在对所述行锤刷新地址完成刷新操作后，清空所述页表中与所述行锤刷新地址对应的所述行地址，并将所述行地址在所述地址状态信号中的对应位由所述有效状态切换为所述无效状态。
第三方面，如图12所示，本公开实施例提供了一种刷新控制电路200，包括：上述实施例中任一所述的地址选择电路100；刷新电路201，用于对与所述行锤地址对应的地址线相邻的至少一条地址线进行刷新操作。
在本公开实施例中，刷新控制电路200可以用于随机采样多个行地址，并通过轮询的方式确定其中一个行地址为行锤地址，然后将行锤地址对应的地址线相邻的至少一条地址线进行刷新操作，以减少数据错误。刷新控制电路200包括地址选择电路100，以及刷新电路201，刷新电路201可以根据地址选择电路100输出的行锤地址，对行锤地址对应的字线相邻的至少一条字线进行刷新操作。示例性地，刷新电路201可以为存储器中的行解码器(Row Decoder)电路。在一些实施例中，地址选择电路100中具有地址运算电路，以根据行锤地址确定行锤刷新地址，故刷新电路201可以直接对行锤刷新地址对应的字线进行刷新。
第四方面，如图13所示，本公开实施例提供了一种存储系统300，包括：存储器310，包括外围电路311和存储单元阵列312；其中，所述外围电路311包括上述实施例中任一所述的地址选择电路100；存储控制器320。
在本公开实施例中，存储器310可以包括但不限于DRAM、静态随机存取存储器(Static Random Access Memory，SRAM)、铁电随机存取存储器(Ferroelectric Random Access Memory，FRAM)、磁性随机存取存储器(Magnetoresistive Random Access Memory，MRAM)、相变随机存取存储器(Phase Change Random Access Memory，PCRAM)、阻变随机存取存储器(Resistive Random Access Memory，RRAM)、纳米随机存取存储器(Nano Random Access Memory，NRAM)等。存储控制器320可以根据主机发出的信号，控制存储器310进行各项操作。可以理解的是，在存储器310的外围电路311中，地址状态信号的每一位表示对应的一个行地址的有效状态或无效状态，移位信号产生电路根据地址状态信号，生成移位信号，移位信号的脉冲数量用于表示多个行地址中，位于第一个处于有效状态的行地址之前的处于无效状态的行地址的个数。如此，可以通过轮询的方式，选择第一个处于有效状态的行地址作为行锤地址，并对行锤地址相邻的行地址进行刷新，从而有效减少存储器310中，由于行锤攻击行为带来的数据错误和数据丢失。
需要说明的是，本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
在本公开实施例提供的地址选择电路中，地址状态信号的每一位表示对应的一个地址寄存单元的有效状态或无效状态，移位信号产生电路根据地址状态信号，生成移位信号，移位选择电路根据移位信号对多个地址寄存单元进行选择。如此，地址选择电路可以通过轮询的方式，选择第一个处于有效状态的行地址作为行锤地址，并对行锤地址相邻的行地址进行刷新，从而有效减少行锤攻击行为带来的数据错误。

Claims (22)

  1. 一种地址选择电路(100)，包括：
    多个地址寄存单元(101)，配置为存储行地址；
    状态寄存单元(102)，配置为存储并输出地址状态信号；所述地址状态信号的每一位用于表示对应的一个所述地址寄存单元(101)的有效状态或无效状态；所述有效状态表示所述地址寄存单元(101)中存储有所述行地址，所述无效状态表示所述地址寄存单元(101)中未存储所述行地址；
    移位信号产生电路(110)，用于根据所述地址状态信号，生成移位信号；
    移位选择电路(120)，连接所述移位信号产生电路(110)；所述移位选择电路(120)用于根据所述移位信号，对多个所述地址寄存单元(101)进行选择，并将选择的所述地址寄存单元(101)中存储的所述行地址作为行锤地址。
  2. 根据权利要求1所述的地址选择电路(100)，其中，所述地址寄存单元(101)和所述状态寄存单元(102)位于页表中；所述页表的每一页表项包括一个所述地址寄存单元(101)中存储的所述行地址，以及所述地址寄存单元(101)的有效状态或无效状态；
    所述移位信号产生电路(110)具体用于基于多个所述地址寄存单元(101)中，位于第一个处于所述有效状态的所述地址寄存单元(101)之前的处于所述无效状态的所述地址寄存单元(101)的个数，生成具有对应脉冲数量的移位信号；
    所述移位选择电路(120)具体用于根据所述移位信号的脉冲数量输出指针，以对多个所述页表项进行选择，并将指针指向的所述页表项中的所述行地址作为所述行锤地址。
  3. 根据权利要求1或2所述的地址选择电路(100)，其中，所述移位信号产生电路(110)包括：
    计数单元(111)，配置为对时钟脉冲计数，并生成计数信号；
    多个锁存单元(112)，所述锁存单元(112)连接所述计数单元(111)和所述状态寄存单元(102)；多个所述锁存单元(112)配置为根据所述计数信号，依次锁存所述地址状态信号的每一位，以输出多个锁存状态信号；
    仲裁单元(113)，连接所述计数单元(111)、多个所述锁存单元(112)和所述状态寄存单元(102)；所述仲裁单元(113)配置为根据所述地址状态信号，所述锁存状态信号和所述计数信号，或根据所述地址状态信号，输出所述移位信号。
  4. 根据权利要求3所述的地址选择电路(100)，其中，所述仲裁单元(113)具体配置为根据所述地址状态信号，依次输出至少一个所述锁存状态信号与所述计数信号的运算结果，以作为所述移位信号。
  5. 根据权利要求3或4所述的地址选择电路(100)，其中，所述仲裁单元(113)具体配置为根据所述地址状态信号，输出持续的第一电平，以作为所述移位信号；所述第一电平表示所述地址状态信号的每一位都表示所述无效状态。
  6. 根据权利要求3至5中任一所述的地址选择电路(100)，其中，所述仲裁单元(113)包括：
    选择单元(114)，连接多个所述锁存单元(112)和所述状态寄存单元(102)；所述选择单元(114)配置为根据所述地址状态信号，依次选择并输出至少一个所述锁存状态信号；
    运算单元(115)，连接所述选择单元(114)和所述计数单元(111)；所述运算单元(115)配置为依次将至少一个所述锁存状态信号与所述计数信号进行运算，以输出所述移位信号。
  7. 根据权利要求3至6中任一所述的地址选择电路(100)，其中，还包括：
    命令解码电路(130)，连接所述仲裁单元(113)；所述命令解码电路(130)用于根据主机端发出的外部命令，生成并输出自动刷新信号；
    在所述地址状态信号的至少一位表示所述有效状态的情况下，所述仲裁单元(113)还配置为根 据所述自动刷新信号，生成所述移位信号的第一个脉冲。
  8. 根据权利要求3至7中任一所述的地址选择电路(100)，其中，还包括：
    控制逻辑(140)，连接所述计数单元(111)；所述控制逻辑(140)用于在所述计数信号表示的计数值大于预设值的情况下，禁用所述移位信号产生电路(110)。
  9. 根据权利要求8所述的地址选择电路(100)，其中，还包括：
    地址采样电路(150)，连接所述地址寄存单元(101)；所述地址采样电路(150)用于采样行地址，并将采样到的所述行地址输出至所述地址寄存单元(101)；
    当所述地址寄存单元(101)接收到所述地址采样电路(150)输出的所述行地址时，所述控制逻辑(140)还用于将所述行地址在所述地址状态信号中的对应位由所述无效状态切换为所述有效状态。
  10. 根据权利要求8或9所述的地址选择电路(100)，其中，还包括：
    地址运算电路(160)，连接所述移位选择电路(120)；所述地址运算电路(160)用于根据所述行锤地址，确定所述行锤地址相邻的至少一条行地址为行锤刷新地址；
    在对所述行锤刷新地址完成刷新操作后，所述控制逻辑(140)还用于将所述行锤刷新地址对应的所述地址寄存单元(101)中存储的所述行地址清空，并将所述行地址在所述地址状态信号中的对应位由所述有效状态切换为所述无效状态。
  11. 一种地址选择方法，包括：
    在页表中存储多个行地址和地址状态信号；所述地址状态信号的每一位用于表示对应的一个页表项的有效状态或无效状态；所述有效状态表示所述页表项中存储有所述行地址，所述无效状态表示所述页表项中未存储所述行地址；
    根据所述地址状态信号，输出移位信号；
    根据所述移位信号，对多个所述页表项进行选择，并将选择的所述页表项中存储的所述行地址作为行锤地址。
  12. 根据权利要求11所述的方法，其中，所述根据所述地址状态信号，输出移位信号，包括：
    基于多个所述页表项中，位于第一个处于所述有效状态的所述页表项之前的处于所述无效状态的所述页表项的个数，输出具有对应脉冲数量的移位信号；
    所述根据所述移位信号，对多个所述页表项进行选择，并将选择的所述页表项中存储的所述行地址作为行锤地址，包括：
    根据所述移位信号的脉冲数量输出指针，以按照预设顺序对多个所述页表项进行移位选择，并将指针指向的所述页表项中的所述行地址作为所述行锤地址。
  13. 根据权利要求11或12所述的方法，其中，所述根据所述地址状态信号，生成移位信号，包括：
    对时钟脉冲计数，并生成计数信号；
    根据所述计数信号，依次锁存所述地址状态信号的每一位，以输出多个锁存状态信号；
    根据所述地址状态信号，所述锁存状态信号和所述计数信号，或根据所述地址状态信号，输出所述移位信号。
  14. 根据权利要求13所述的方法，其中，所述根据所述地址状态信号，输出所述移位信号，包括：
    根据所述地址状态信号，输出持续的第一电平，以作为所述移位信号；所述第一电平表示所述地址状态信号的每一位都表示所述无效状态。
  15. 根据权利要求13或14所述的方法，其中，所述根据所述地址状态信号，所述锁存状态信号和所述计数信号，输出所述移位信号，包括：
    根据所述地址状态信号，依次输出至少一个所述锁存状态信号与所述计数信号的运算结果，以作为所述移位信号。
  16. 根据权利要求15所述的方法，其中，所述根据所述地址状态信号，依次输出至少一个所述锁存状态信号与所述计数信号的运算结果，以作为所述移位信号，包括：
    根据所述地址状态信号，依次选择并输出至少一个所述锁存状态信号；
    依次将至少一个所述锁存状态信号与所述计数信号进行运算，以输出所述移位信号。
  17. 根据权利要求13至16中任一所述的方法，其中，还包括：
    根据主机端发出的外部命令，生成并输出自动刷新信号；
    在所述地址状态信号的至少一位表示所述有效状态的情况下，根据所述自动刷新信号，生成所述移位信号的第一个脉冲。
  18. 根据权利要求13至17中任一所述的方法，其中，还包括：
    在所述计数信号表示的计数值大于预设值的情况下，禁用所述移位信号产生电路(110)。
  19. 根据权利要求18所述的方法，其中，还包括：
    采样所述行地址；
    所述在页表中存储多个行地址，包括：在页表中存储采样到的所述行地址；
    当接收到采样到的所述行地址时，将所述行地址在所述地址状态信号中的对应位由所述无效状态切换为所述有效状态。
  20. 根据权利要求18或19所述的方法，其中，还包括：
    根据所述行锤地址，确定所述行锤地址相邻的至少一条行地址为行锤刷新地址；
    在对所述行锤刷新地址完成刷新操作后，清空所述页表中与所述行锤刷新地址对应的所述行地址，并将所述行地址在所述地址状态信号中的对应位由所述有效状态切换为所述无效状态。
  21. 根据权利要求1至10中任一所述的地址选择电路(100)，其中，所述地址选择电路(100)用于在刷新控制电路(200)中提供所述行锤地址，所述刷新控制电路(200)还包括：
    刷新电路(201)，用于对与所述行锤地址对应的地址线相邻的至少一条地址线进行刷新操作。
  22. 一种存储系统(300)，包括：
    存储器(310)，包括外围电路(311)和存储单元阵列(312)；其中，所述外围电路(311)包括如权利要求1至10中任一所述的地址选择电路(100)；
    存储控制器(320)。
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