WO2024143384A1 - ＳｉＣ半導体装置 - Google Patents

ＳｉＣ半導体装置 Download PDF

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Publication number
WO2024143384A1
WO2024143384A1 PCT/JP2023/046705 JP2023046705W WO2024143384A1 WO 2024143384 A1 WO2024143384 A1 WO 2024143384A1 JP 2023046705 W JP2023046705 W JP 2023046705W WO 2024143384 A1 WO2024143384 A1 WO 2024143384A1
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Prior art keywords
region
trench
semiconductor layer
semiconductor device
sic
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PCT/JP2023/046705
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024567875A priority Critical patent/JPWO2024143384A1/ja
Priority to DE112023004917.3T priority patent/DE112023004917T5/de
Priority to CN202380089504.2A priority patent/CN120435925A/zh
Publication of WO2024143384A1 publication Critical patent/WO2024143384A1/ja
Priority to US19/252,687 priority patent/US20250324682A1/en
Anticipated expiration legal-status Critical
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    • H10D62/109—Reduced surface field [RESURF] PN junction structures
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    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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Definitions

  • the present disclosure provides a novel SiC semiconductor device.
  • FIG. 1 is a plan view showing a SiC semiconductor device according to a specific embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a plan view showing an example of a chip layout.
  • FIG. 4 is a perspective view showing an example of a chip layout.
  • FIG. 5 is a plan view showing an active region and a trench structure according to the first embodiment.
  • FIG. 6 is a cross-sectional perspective view showing an active region and a trench structure according to the first embodiment.
  • FIG. 7 is an enlarged cross-sectional view showing a trench structure according to the first embodiment.
  • FIG. 8 is a graph showing an example of a p-type concentration gradient of an impurity region.
  • FIG. 8 is a graph showing an example of a p-type concentration gradient of an impurity region.
  • FIG. 9 is a graph showing a comparative example of the p-type concentration gradient of the impurity region.
  • FIG. 10 is a graph showing an example of the n-type concentration gradient in the column region.
  • FIG. 11 is a perspective view showing the configuration of the outer circumferential area.
  • FIG. 12 is a cross-sectional view showing a main part of the outer circumferential region.
  • FIG. 13 is a cross-sectional view showing a main part of the outer circumferential region.
  • FIG. 14 is a schematic diagram showing a wafer used in the manufacture of a SiC semiconductor device.
  • FIG. 15 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device.
  • FIG. 15 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device.
  • FIG. 16A is a cross-sectional perspective view showing an example of a manufacturing method for a SiC semiconductor device.
  • FIG. 16B is a cross-sectional perspective view showing a step subsequent to that of FIG. 16A.
  • FIG. 16C is a cross-sectional perspective view showing a step subsequent to FIG. 16B.
  • FIG. 16D is a cross-sectional perspective view showing a step subsequent to FIG. 16C.
  • FIG. 16E is a cross-sectional perspective view showing a step subsequent to FIG. 16D.
  • FIG. 16F is a cross-sectional perspective view showing a step subsequent to FIG. 16E.
  • FIG. 16G is a cross-sectional perspective view showing a step subsequent to FIG. 16F.
  • FIG. 17A is a schematic diagram for explaining the crystal orientation measurement process.
  • FIG. 17B is a schematic diagram for explaining the crystal orientation measurement process.
  • FIG. 18A is a schematic diagram for explaining the ion implantation step.
  • FIG. 18B is a schematic diagram for explaining the ion implantation step.
  • FIG. 19 is a cross-sectional perspective view showing a trench structure according to the second embodiment.
  • FIG. 20 is a cross-sectional perspective view showing a trench structure according to the third embodiment.
  • FIG. 21 is a cross-sectional perspective view showing a trench structure according to the fourth embodiment.
  • FIG. 22 is a cross-sectional perspective view showing a SiC semiconductor device according to a first modification.
  • FIG. 23 is a cross-sectional perspective view showing a SiC semiconductor device according to a second modification.
  • FIG. 24 is a cross-sectional perspective view showing a SiC semiconductor device according to a third modification.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4).
  • the first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.
  • the second side 5B is connected to the first side 5A
  • the third side 5C is connected to the second side 5B
  • the fourth side 5D is connected to the first side 5A and the third side 5C.
  • the first side 5A and the third side 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, perpendicular to) the first direction X.
  • the second side 5B and the fourth side 5D extend in the second direction Y and face the first direction X.
  • the first axis channel C1 is a region in which the atomic rows extend in the stacking direction and the horizontal atomic rows (atomic distance/atomic density) are sparse in plan view.
  • the first axis channel C1 is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.
  • a low-index crystal axis is a crystal axis in which the absolute values of "a1", “a2", “a3” and “c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c) (the same applies hereinafter in this specification).
  • the base layer 6 may have a peak n-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction.
  • the n-type impurity concentration of the base layer 6 is preferably adjusted by a single type of pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted by a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted by nitrogen.
  • the chip 2 includes a semiconductor layer 7 made of single crystal SiC that is stacked on the base layer 6.
  • the semiconductor layer 7 may also be called a "SiC layer,” “semiconductor region,” etc.
  • the semiconductor layer 7 extends in a layered manner in the horizontal direction and forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the base layer 6.
  • the n-type impurity concentration of the semiconductor layer 7 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the semiconductor layer 7 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the semiconductor layer 7 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the semiconductor layer 7 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1.
  • the second thickness T2 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the second thickness T2 may have a value that belongs to any one of the following ranges: 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, and 8 ⁇ m or more and 10 ⁇ m or less.
  • the second thickness T2 is preferably 2 ⁇ m or more and 8 ⁇ m or less.
  • the SiC semiconductor device 1 includes an active region 8 set in the chip 2.
  • the active region 8 is set in the inner part of the chip 2 at a distance from the periphery of the chip 2 (first to fourth side faces 5A to 5D) in a plan view.
  • the active region 8 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar area of the active region 8 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the SiC semiconductor device 1 includes a peripheral region 9 that is set outside the active region 8 in the chip 2.
  • the peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a planar view.
  • the peripheral region 9 extends in a band shape along the active region 8 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 8.
  • the SiC semiconductor device 1 includes an active surface 10 formed on the first main surface 3, an outer surface 11, and first to fourth connecting surfaces 12A to 12D.
  • the active surface 10, the outer surface 11, and the first to fourth connecting surfaces 12A to 12D define an active plateau 13 on the first main surface 3.
  • the active surface 10 may be referred to as the "first surface portion,” the outer peripheral surface 11 as the “second surface portion,” the first to fourth connection surfaces 12A to 12D as the “connection surface portions,” and the active plateau 13 as the “mesa portion.”
  • the active surface 10, the outer peripheral surface 11, and the first to fourth connection surfaces 12A to 12D may be considered to be components of the chip 2 (first main surface 3).
  • the active surface 10 is formed in the active region 8. That is, the active surface 10 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.
  • the active surface 10 has a flat surface extending in the first direction X and the second direction Y.
  • the active surface 10 is formed by a c-plane (Si-plane).
  • the active surface 10 is formed in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the outer peripheral surface 11 is formed in the outer peripheral region 9. That is, the outer peripheral surface 11 is formed outside the active surface 10.
  • the outer peripheral surface 11 is recessed in the thickness direction of the chip 2 (towards the second main surface 4) relative to the active surface 10. Specifically, in this embodiment, the outer peripheral surface 11 is recessed to a depth less than the thickness of the semiconductor layer 7 so as to expose the semiconductor layer 7. That is, the outer peripheral surface 11 faces the base layer 6 across a portion of the semiconductor layer 7, exposing the semiconductor layer 7.
  • the outer peripheral surface 11 extends in a band shape along the active surface 10 in a plan view, and is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 10.
  • the outer peripheral surface 11 has a flat surface extending in the first direction X and the second direction Y, and is formed approximately parallel to the active surface 10.
  • the outer peripheral surface 11 is formed by a c-plane (Si-plane).
  • the outer peripheral surface 11 is connected to the first to fourth side surfaces 5A to 5D.
  • the outer peripheral surface 11 has an outer peripheral depth DO.
  • the outer peripheral depth DO may be 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the outer peripheral depth DO may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the outer peripheral depth DO is preferably 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the first to fourth connection surfaces 12A to 12D extend in the vertical direction Z and connect the active surface 10 and the outer peripheral surface 11.
  • the first connection surface 12A is located on the first side surface 5A side
  • the second connection surface 12B is located on the second side surface 5B side
  • the third connection surface 12C is located on the third side surface 5C side
  • the fourth connection surface 12D is located on the fourth side surface 5D side.
  • the first connection surface 12A and the third connection surface 12C extend in the first direction X and face the second direction Y.
  • the second connection surface 12B and the fourth connection surface 12D extend in the second direction Y and face the first direction X.
  • the first to fourth connection surfaces 12A to 12D may extend approximately vertically between the active surface 10 and the outer peripheral surface 11 so as to define a quadrangular prism-shaped active plateau 13.
  • the first to fourth connection surfaces 12A to 12D may be inclined obliquely downward from the active surface 10 toward the outer peripheral surface 11 so as to define a quadrangular pyramid-shaped active plateau 13.
  • the active plateau 13 is defined in a protruding shape on the semiconductor layer 7 at the first main surface 3.
  • the active plateau 13 is formed only on the semiconductor layer 7, and is not formed on the base layer 6.
  • the SiC semiconductor device 1 includes a p-type impurity region 15 formed in at least a portion of the semiconductor layer 7 located in the active region 8.
  • the impurity region 15 has an n-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7, and inverts the conductivity type of the semiconductor layer 7 from n-type to p-type.
  • impurity region 15 contains a trivalent element in addition to the pentavalent element that constitutes the conductivity type of semiconductor layer 7.
  • Impurity region 15 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of impurity region 15 is preferably adjusted by at least one kind of trivalent element.
  • the p-type impurity concentration of the impurity region 15 is adjusted by a trivalent element that is heavier than carbon.
  • the impurity region 15 contains a trivalent element other than boron (at least one of aluminum, gallium, and indium).
  • the p-type impurity concentration of the impurity region 15 is adjusted by aluminum.
  • the upper end of the impurity region 15 may be exposed from the first main surface 3.
  • the upper end of the impurity region 15 may be formed at a distance from the upper end of the semiconductor layer 7 (i.e., the semiconductor layer 7) toward the lower end, and may face the first main surface 3 with a part (upper end) of the semiconductor layer 7 in between.
  • Such a structure is identified by analyzing the p-type impurity concentration (concentration gradient) of the impurity region 15.
  • the lower end of the impurity region 15 is formed at a distance from the lower end of the semiconductor layer 7 (i.e., the base layer 6) toward the upper end, and faces the base layer 6 across a part (lower end) of the semiconductor layer 7.
  • the distance between the lower end of the semiconductor layer 7 and the lower end of the impurity region 15 may be more than 0 ⁇ m and not more than 5 ⁇ m.
  • the impurity region 15 has a thickness less than the second thickness T2 of the semiconductor layer 7.
  • the thickness of the impurity region 15 may be 1 ⁇ m or more and less than 10 ⁇ m.
  • the thickness of the impurity region 15 may have a value belonging to any one of the following ranges: 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, and 8 ⁇ m or more and less than 10 ⁇ m.
  • the thickness of the impurity region 15 is preferably 2 ⁇ m or more and 8 ⁇ m or less.
  • the lower end of the impurity region 15 may cross the boundary between the base layer 6 and the semiconductor layer 7 and be located within the base layer 6.
  • the impurity region 15 has an off-direction Do and an off-angle ⁇ o that are approximately the same as the off-direction Do and off-angle ⁇ o of the second axis channel C2.
  • the impurity region 15 is inclined from the vertical axis toward the off-direction Do by the off-angle ⁇ o.
  • the impurity region 15 consists of a single impurity region having a thickness (depth) that crosses the middle part of the semiconductor layer 7 along the second axis channel C2.
  • Figure 9 is a graph showing the case where the impurity region 15 is formed by the random injection method.
  • Figure 9 shows the concentration gradient of the impurity region 15 when a predetermined trivalent element (here, aluminum) is introduced into the semiconductor layer 7 in a random direction with an injection energy of 500 KeV or more and 800 KeV or less.
  • a predetermined trivalent element here, aluminum
  • the body region 20 does not necessarily have to be formed.
  • a part (surface portion) of the impurity region 15 can function as part of the body region 20
  • a part (surface portion) of the impurity region 15 may be formed as the body region 20, and the body region 20 may be omitted.
  • the surface portion of the impurity region 15 may also serve as the body region 20, and the body region 20 may be formed using the surface portion of the impurity region 15. This configuration is applicable both to the case where the impurity region 15 is formed at a distance from the first main surface 3 to the lower end side of the semiconductor layer 7, and to the case where the impurity region 15 is exposed from the first main surface 3.
  • the multiple trench structures 25 are spaced apart from each other in the active region 8, extending inward from the periphery (first to fourth connection surfaces 12A to 12D) of the active surface 10.
  • the multiple trench structures 25 are arranged at intervals in the first direction X, and are each formed in a strip shape extending in the second direction Y.
  • the trench depth DT is preferably greater than the trench width WT.
  • each of the multiple trench structures 25 has an aspect ratio DT/WT that extends in a vertically elongated columnar shape.
  • the aspect ratio DT/WT is the ratio of the trench width WT to the trench depth DT.
  • the trench depth DT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the multiple trench structures 25 are arranged at intervals of the trench pitch PT in the first direction X.
  • the trench pitch PT is preferably less than the second thickness T2 of the semiconductor layer 7.
  • the trench pitch PT is preferably less than the thickness of the impurity region 15.
  • the trench pitch PT is preferably less than the trench depth DT.
  • the trench pitch PT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the SiC semiconductor device 1 includes a plurality of n-type inversion columns 30 formed at intervals in the horizontal direction in the semiconductor layer 7.
  • the inversion columns 30 may be referred to as a "first column region,” an “inversion column region,” a “drift region,” an “inversion drift region,” or the like.
  • the inversion columns 30 have an n-type impurity concentration higher than the p-type impurity concentration of the impurity region 15, and invert the conductivity type of the impurity region 15 from p-type to n-type.
  • the multiple inversion columns 30 overlap the multiple trench structures 25 in the stacking direction. Specifically, the multiple inversion columns 30 overlap the multiple trench structures 25 in a one-to-one correspondence in the stacking direction.
  • the multiple inversion columns 30 are formed in the active region 8 at intervals inward from the periphery of the active surface 10 (first to fourth connection surfaces 12A to 12D).
  • both ends of the multiple inversion columns 30 may be located on the inner side of the active region 8 relative to both ends of the multiple trench structures 25. With respect to the second direction Y, both ends of the multiple inversion columns 30 may be located on the peripheral side of the active region 8 relative to both ends of the multiple trench structures 25.
  • both ends of the multiple inversion columns 30 may be located on the inner side of the active region 8 relative to the peripheral portion (both ends) of the impurity region 15.
  • both ends of the multiple inversion columns 30 may be located on the peripheral side of the active region 8 relative to the peripheral portion (both ends) of the impurity region 15.
  • the multiple inversion columns 30 have upper ends located on the bottom wall side of the trench structure 25 and lower ends located on the lower end side of the semiconductor layer 7.
  • the upper ends of the multiple inversion columns 30 are located in a region on the bottom wall side of the trench structure 25 relative to the intermediate part of the thickness range of the lower region 7a
  • the lower ends of the multiple inversion columns 30 are located in a region on the lower end side of the semiconductor layer 7 relative to the intermediate part of the thickness range of the lower region 7a.
  • the upper ends of the multiple inversion columns 30 are formed at intervals on the lower end side of the semiconductor layer 7 relative to the depth position of the outer circumferential surface 11.
  • the upper ends of the multiple inversion columns 30 are formed at intervals on the lower end side of the semiconductor layer 7 from the bottom walls of the multiple trench structures 25, and face the multiple trench structures 25 with a part of the impurity region 15 in between.
  • the upper ends of the multiple inversion columns 30 are electrically connected to the relatively high concentration impurity region 15.
  • the upper ends of the multiple inversion columns 30 may also be connected to the bottom walls of the multiple trench structures 25.
  • the lower ends of the multiple inversion columns 30 are drawn across the bottom of the impurity region 15 to the lower layer of the semiconductor layer 7. That is, the multiple inversion columns 30 include a portion located in the region between the bottom of the impurity region 15 and the bottom walls of the multiple trench structures 25, and a portion located in the region between the lower end of the semiconductor layer 7 and the bottom of the impurity region 15.
  • the lower ends of the multiple inversion columns 30 are electrically connected to the lower layer of the semiconductor layer 7. That is, the multiple inversion columns 30 are electrically connected to the base layer 6 via a portion of the semiconductor layer 7.
  • the multiple inversion columns 30 each have a column thickness TC (region depth).
  • the column thickness TC is preferably less than the second thickness T2 of the semiconductor layer 7.
  • the column thickness TC is preferably less than the thickness of the impurity region 15. It is particularly preferable that the column thickness TC is equal to or greater than the trench depth DT. It is preferable that the column thickness TC is greater than the trench width WT. It is particularly preferable that the column thickness TC is greater than the trench depth DT. Of course, the column thickness TC may be less than the trench depth DT.
  • each of the non-inversion columns 35 is made up of a p-type channeling region extending along the second axial channel C2.
  • the non-inversion columns 35 are arranged at intervals in the first direction X (m-axis direction) in the semiconductor layer 7 (lower region 7a), and are each partitioned into strips extending in the second direction Y (a-axis direction).
  • the non-inversion columns 35 overlap the regions between the trench structures 25 in the stacking direction.
  • both ends of each intermediate region 36 may be located on the inner side of the active region 8 relative to both ends of the corresponding trench structure 25.
  • both ends of the multiple inversion columns 30 may be located on the peripheral side of the active region 8 relative to both ends of the multiple trench structures 25.
  • the multiple field regions 40 are arranged at intervals from the periphery of the active surface 10 (first to fourth connection surfaces 12A to 12D) and the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). Specifically, the multiple field regions 40 are arranged at intervals from the well region 39 to the periphery side of the outer circumferential surface 11.
  • the field regions 40 preferably have a width different from the column width WC of the inversion column 30.
  • the electric field relaxation effect of the field regions 40 is preferably adjusted separately from the inversion columns 30. It is particularly preferable that the width of the field regions 40 is greater than the column width WC.
  • the width of the field regions 40 may be smaller than the column width WC.
  • the width of the inversion column 30 may be approximately equal to the column width WC.
  • the multiple field regions 40 are preferably formed at a pitch different from the column pitch PC of the inversion column 30. It is particularly preferable that the pitch of the multiple field regions 40 is larger than the column pitch PC. The pitch of the multiple field regions 40 may be smaller than the column pitch PC. The pitch of the multiple field regions 40 may be approximately equal to the column pitch PC.
  • the first insulating film 42 selectively covers the first main surface 3 in the active region 8 and the peripheral region 9. Specifically, the first insulating film 42 selectively covers the active surface 10, the peripheral surface 11, and the first to fourth connection surfaces 12A to 12D. The first insulating film 42 is connected to the insulating film 27 in the active surface 10, exposing the buried electrode 28.
  • the second insulating film 43 covers the multiple trench structures 25 (buried electrodes 28) in the active region 8.
  • the second insulating film 43 covers the well region 39 and the multiple field regions 40 on the periphery of the outer peripheral region 9, sandwiching the first insulating film 42 between them.
  • the second insulating film 43 is continuous with the first to fourth side surfaces 5A to 5D.
  • the second insulating film 43 may be formed at a distance inward from the periphery of the outer peripheral surface 11, exposing the peripheral portion of the first main surface 3 together with the first insulating film 42.
  • the SiC semiconductor device 1 includes a plurality of contact openings 44 formed in the interlayer insulating film 41.
  • the plurality of contact openings 44 includes a plurality of contact openings 44 (not shown) that expose a plurality of trench structures 25 (buried electrodes 28), and a plurality of contact openings 44 that expose a plurality of source regions 37.
  • the plurality of contact openings 44 for the source regions 37 are formed in the regions between the plurality of adjacent trench structures 25, and expose the plurality of source regions 37 and the plurality of contact regions 38.
  • the SiC semiconductor device 1 includes a sidewall structure 45 arranged in the interlayer insulating film 41 so as to cover at least one of the first to fourth connection surfaces 12A to 12D.
  • the sidewall structure 45 is arranged on the first insulating film 42 and is covered by the second insulating film 43.
  • the sidewall structure 45 reduces the step formed between the active surface 10 and the outer peripheral surface 11.
  • the sidewall structure 45 may have a portion that extends in a film shape along the outer peripheral surface 11, and a portion that extends in a film shape along the first to fourth connection surfaces 12A to 12D.
  • the sidewall structure 45 is formed at a distance from the innermost field region 40 toward the active surface 10, and faces the well region 39 in the horizontal direction and stacking direction, sandwiching the first insulating film 42 between them.
  • the sidewall structure 45 may face the body region 20, sandwiching the first insulating film 42 between them.
  • the SiC semiconductor device 1 includes a gate pad 50 disposed on the interlayer insulating film 41.
  • the gate pad 50 is an electrode to which a gate potential is applied from the outside.
  • the gate pad 50 may be referred to as a "gate pad electrode", a "first pad electrode”, etc.
  • the gate pad 50 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 41 side.
  • the gate pad 50 is disposed on a portion of the interlayer insulating film 41 that covers the active region 8. Specifically, the gate pad 50 is disposed on the active surface 10 at a distance from the outer peripheral surface 11 in a plan view. The gate pad 50 is disposed in a region close to the center of one side of the active surface 10 (the second connection surface 12B in this embodiment) in a plan view.
  • the gate pad 50 may be disposed in a region along any of the central portions of the first to fourth connection surfaces 12A to 12D.
  • the gate pad 50 may be disposed at any corner of the active surface 10 in a planar view.
  • the gate pad 50 may also be disposed at the central portion of the active surface 10 in a planar view.
  • the gate pad 50 is formed in a quadrangular shape in a planar view.
  • the SiC semiconductor device 1 includes at least one gate wiring 51 (multiple in this embodiment) that is drawn from the gate pad 50 onto the interlayer insulating film 41.
  • the gate wiring 51 may also be referred to as a "wiring”, a “wiring electrode”, etc.
  • the multiple gate wirings 51 are arranged on the active surface 10 at intervals from the outer peripheral surface 11 in a plan view.
  • the multiple gate wirings 51 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the interlayer insulating film 41 side.
  • the multiple gate wirings 51 include a first gate wiring 51A and a second gate wiring 51B.
  • the first gate wiring 51A is pulled out from the gate pad 50 toward the first connection surface 12A and extends in a line along the periphery of the active surface 10 so as to intersect (specifically, perpendicular to) a portion (specifically, one end) of the multiple trench structures 25.
  • the first gate wiring 51A penetrates the interlayer insulating film 41 via the multiple contact openings 44 and is electrically connected to one end of the multiple trench structures 25.
  • the second gate wiring 51B is pulled out from the gate pad 50 toward the third connection surface 12C and extends in a line along the periphery of the active surface 10 so as to intersect (specifically, perpendicular to) a portion (specifically, the other end) of the multiple trench structures 25.
  • the second gate wiring 51B penetrates the interlayer insulating film 41 via the multiple contact openings 44 and is electrically connected to the other end of the multiple trench structures 25.
  • the SiC semiconductor device 1 includes a source pad 52 disposed on the interlayer insulating film 41 at a distance from the gate pad 50 and the gate wiring 51.
  • the source pad 52 is an electrode to which a source potential is applied from the outside.
  • the source pad 52 may be referred to as a "source pad electrode", a "second pad electrode”, etc.
  • the source pad 52 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 41 side.
  • the source pad 52 is disposed on the active surface 10 at a distance from the outer peripheral surface 11 in a plan view.
  • the source pad 52 is formed in a polygonal shape having a recess along the gate pad 50 in a plan view.
  • the source pad 52 may also be formed in a square shape in a plan view.
  • the source pad 52 penetrates the interlayer insulating film 41 through a plurality of contact openings 44, and is electrically connected to the body region 20, the plurality of source regions 37, and the plurality of contact regions 38. In other words, the source pad 52 is electrically connected to the plurality of non-inversion columns 35 (impurity regions 15) through the body region 20.
  • the SiC semiconductor device 1 includes a drain pad 53 covering the second main surface 4.
  • the drain pad 53 is an electrode to which a drain potential is applied from the outside.
  • the drain pad 53 may be referred to as a "drain pad electrode”, a “third pad electrode”, etc.
  • the drain pad 53 forms an ohmic contact with the base layer 6 exposed from the second main surface 4.
  • the drain pad 53 is electrically connected to the multiple inversion columns 30 (intermediate region 36) via the base layer 6.
  • the drain pad 53 may cover the entire second main surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D).
  • the drain pad 53 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.
  • the breakdown voltage that can be applied between the source pad 52 and the drain pad 53 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to any one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIG. 14 is a schematic diagram showing a wafer 60 used in the manufacture of a SiC semiconductor device 1.
  • the wafer 60 is a substrate for the base layer 6 and contains a SiC single crystal.
  • the wafer 60 is formed in a flat disk shape. Of course, the wafer 60 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 60 has a first wafer main surface 61 on one side, a second wafer main surface 62 on the other side, and a wafer side surface 63 connecting the first wafer main surface 61 and the second wafer main surface 62.
  • the first wafer main surface 61 corresponds to the upper end of the base layer 6, and the second wafer main surface 62 corresponds to the lower end of the base layer 6.
  • the first wafer main surface 61 and the second wafer main surface 62 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 61 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 62 is formed by the carbon surface of the SiC single crystal.
  • the wafer 60 (the first wafer main surface 61 and the second wafer main surface 62) has the off-direction Do and off-angle ⁇ o described above.
  • the wafer 60 has a mark 64 on the wafer side surface 63 that indicates the crystal orientation of the SiC single crystal.
  • the mark 64 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 61 in a plan view.
  • the mark 64 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction.
  • the mark 64 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.
  • FIG. 14 an orientation flat extending in the m-axis direction (first direction X) in a plan view is shown.
  • a plurality of device regions 65 and a plurality of cutting lines 66 are set on the wafer 60 by alignment marks or the like.
  • Each device region 65 is an area corresponding to a SiC semiconductor device 1.
  • Each of the plurality of device regions 65 is set to have a rectangular shape in a plan view.
  • the multiple device regions 65 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 65 are each set at intervals inward from the periphery of the first wafer main surface 61 in a plan view.
  • the multiple cutting lines 66 are set in a lattice extending along the first direction X and the second direction Y to partition the multiple device regions 65.
  • FIG. 15 is a flow chart showing an example of a method for manufacturing a SiC semiconductor device 1.
  • FIGS. 16A to 16O are cross-sectional perspective views showing an example of a method for manufacturing a SiC semiconductor device 1.
  • FIGS. 17A to 17B are schematic diagrams for explaining the crystal orientation measurement process.
  • FIGS. 18A to 18B are schematic diagrams for explaining the ion implantation process.
  • FIGS. 16A to 16O show cross-sectional perspective views of a portion of an active region 8 of one device region 65.
  • the aforementioned wafer 60 preparation process is carried out (step S1 in FIG. 15).
  • the semiconductor layer 7 formation process is carried out (step S2 in FIG. 15).
  • the semiconductor layer 7 is formed starting from the first wafer main surface 61 (wafer 60) by epitaxial growth.
  • the wafer 60 is cut from an ingot (SiC ingot), which is a crystalline mass, but there is a risk that an error will occur in the off-angle ⁇ o due to process error. If an error occurs in the off-angle ⁇ o of the wafer 60, a process error will also occur in the off-angle ⁇ o of the semiconductor layer 7, which will become an obstacle during the channeling injection process. Therefore, it is preferable that data (information) on the off-angle ⁇ o is obtained prior to the channeling injection process, and the channeling injection process is carried out based on the data (information) on the off-angle ⁇ o.
  • the X-ray diffraction device 67 includes an irradiation unit 68 and a detection unit 69, and performs the rocking curve measurement method.
  • the irradiation unit 68 irradiates the upper end of the semiconductor layer 7 (the first wafer main surface 61 of the wafer 60) with incident X-rays L1 having a predetermined incident angle ⁇ .
  • the incident angle ⁇ is defined as the angle between the incident X-rays L1 and the upper end of the semiconductor layer 7 (the first wafer main surface 61 of the wafer 60).
  • the detector 69 is positioned at an angular position of diffraction angle 2 ⁇ ( ⁇ is the Bragg angle) relative to the irradiation position of the incident X-rays L1 on the wafer 60, and detects the diffracted X-rays L2.
  • the diffraction angle 2 ⁇ is the angle between the incident direction of the incident X-rays L1 and the diffraction direction of the diffracted X-rays L2.
  • the diffraction angle 2 ⁇ is fixed and the incident angle ⁇ is varied within a small angular range to measure a rocking curve that represents the intensity of the diffracted X-ray L2 (the intensity profile of the diffracted X-ray L2).
  • the rocking curve has the intensity of the diffracted X-ray L2 on the vertical axis and the incident angle ⁇ on the horizontal axis.
  • the incident angle ⁇ is determined as the angle position at which the intensity of the diffracted X-ray L2 reaches its peak value.
  • the rocking curve measurement method is performed only at one location (e.g., the center) of the upper end of the semiconductor layer 7 (first wafer main surface 61 of the wafer 60). If in-plane variation in the off-angle ⁇ o is expected, the rocking curve measurement method may be performed at multiple locations (e.g., the center and peripheral portions) of the upper end of the semiconductor layer 7 (first wafer main surface 61 of the wafer 60).
  • FIG. 17B shows the measurement points when the rocking curve measurement method is performed on multiple points (five points in this case) on the upper end of the semiconductor layer 7.
  • the off angle ⁇ o of the semiconductor layer 7 is set to about 4° in this case.
  • FIG. 17B shows the first to fifth measurement points Po1 to Po5.
  • the first measurement point Po1 is set in the center of the semiconductor layer 7.
  • the second measurement point Po2 is set on the periphery of the semiconductor layer 7 at a distance from the first measurement point Po1 to one side in the second direction Y (the opposite side to the mark 64).
  • the third measurement point Po3 is set on the periphery of the semiconductor layer 7 at a distance from the first measurement point Po1 to one side in the first direction X (to the right of the mark 64).
  • the fourth measurement point Po4 is set on the periphery of the semiconductor layer 7 at a distance from the first measurement point Po1 to the other side in the second direction Y (the side toward the mark 64).
  • the fifth measurement point Po5 is set on the periphery of the semiconductor layer 7 at a distance from the first measurement point Po1 to the other side in the first direction X (to the left of the mark 64).
  • the average value of the off-angle ⁇ o of the first to fifth measurement points Po1 to Po5 was 4.036°, and the standard deviation of these off-angles ⁇ o was 0.009° ( ⁇ 0.01°). From this, it can be understood that the in-plane variation of the off-angle ⁇ o occurring at the upper end of the semiconductor layer 7 (first wafer main surface 61 of wafer 60) is extremely small, and does not interfere with the channeling implantation process.
  • the measurement point may be any one or more (all) of the first to fifth measurement points Po1 to Po5.
  • the measurement point may be only the first measurement point Po1. Reducing the number of measurement points (number of measurements) reduces the manufacturing man-hours (manufacturing costs).
  • the off-angle ⁇ o may be measured at multiple locations on the upper end (first wafer main surface 61) of the semiconductor layer 7, and an implantation angle may be set in the channeling implantation process according to the in-plane variation of the off-angle ⁇ o.
  • the manufacturing man-hours manufacturing costs
  • the in-plane error of the impurity regions 15 and multiple inversion columns 30 formed in the semiconductor layer 7 is appropriately suppressed.
  • the off-angle ⁇ o of the semiconductor layer 7 is approximately equal to the off-angle ⁇ o of the wafer 60. Therefore, the crystal orientation measurement process may be performed on the wafer 60 prior to the semiconductor layer 7 formation process. However, from the standpoint of ensuring accuracy, it is preferable that the crystal orientation measurement process be performed on the semiconductor layer 7.
  • the process of forming impurity region 15 includes a channeling injection process of a trivalent element (p-type impurity) into semiconductor layer 7.
  • the trivalent element is introduced into the entire semiconductor layer 7 via a mask (not shown) having a predetermined layout.
  • a trivalent element is introduced into the semiconductor layer 7 with a predetermined injection energy in a direction intersecting the second axial channel C2 (off angle ⁇ o) (see also FIG. 9).
  • a trivalent element is injected along the vertical direction Z perpendicular to the upper end (first wafer main surface 61) of the semiconductor layer 7.
  • the trivalent element is introduced along a direction in which the atomic rows are relatively dense in a plan view, so the trivalent element collides with the atomic rows at a relatively shallow depth position. Therefore, the atomic rows prevent the introduction of the trivalent element into a relatively deep depth position of the semiconductor layer 7. As a result, an impurity region 15 that does not have a first slow portion 18 is formed.
  • the injection angle of the trivalent element into the semiconductor layer 7 is controlled, and the trivalent element is introduced into the semiconductor layer 7 along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined injection energy (also refer to FIG. 8).
  • a predetermined injection energy also refer to FIG. 8.
  • the wafer 60 may be supported horizontally and the trivalent element may be introduced into the semiconductor layer 7 along the second axial channel C2.
  • the wafer 60 may be supported tilted by an off angle ⁇ o from the horizontal and the trivalent element may be introduced into the semiconductor layer 7 along the second axial channel C2.
  • the implantation energy of the trivalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection temperature of the trivalent element may be adjusted in the range of 0°C to 1500°C.
  • the injection temperature may have a value that belongs to any one of the following ranges: 0°C to 25°C, 25°C to 50°C, 50°C to 100°C, 100°C to 250°C, 250°C to 500°C, 500°C to 750°C, 750°C to 1000°C, 1000°C to 1250°C, and 1250°C to 1500°C.
  • the injection angle of the trivalent element is preferably set within a range of ⁇ 2° with respect to the axis along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the injection angle of the trivalent element is set within a range of ⁇ 1° with respect to the axis along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).
  • the trivalent element is introduced along the second axial channel C2, in which the atomic rows are relatively sparse in plan view.
  • the trivalent element travels through the second axial channel C2 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the semiconductor layer 7.
  • the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.
  • the trivalent element belongs to the heavy elements heavier than carbon is introduced into the semiconductor layer 7.
  • the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this form, the trivalent element is aluminum.
  • the trivalent element may be electrically activated by an annealing method, and at the same time, lattice defects and the like that have occurred in the semiconductor layer 7 may be repaired.
  • the annealing temperature for the semiconductor layer 7 may be 500°C or higher and 2000°C or lower.
  • the body region 20 formation process includes a random injection process of a trivalent element (p-type impurity) into the surface portion of the semiconductor layer 7.
  • the trivalent element is introduced into the entire semiconductor layer 7.
  • the trivalent element is injected along the vertical direction Z perpendicular to the upper end (first wafer main surface 61) of the semiconductor layer 7.
  • the body region 20 is formed throughout the entire surface portion of the semiconductor layer 7.
  • a process for forming a plurality of source regions 37 is carried out (step S6 in FIG. 15).
  • the plurality of source regions 37 are formed by introducing a pentavalent element into the surface layer of the semiconductor layer 7 by a random injection method through a mask (not shown) having a predetermined layout.
  • the multiple first openings 71a are formed at intervals in the first direction X, and are each partitioned into a band extending in the second direction Y. In other words, the multiple first openings 71a have an extension direction that extends along the off direction Do in a plan view.
  • the first mask 71 also has first openings 71a (not shown) that expose the area where the outer peripheral surface 11 is to be formed.
  • the first openings 71a for the outer peripheral surface 11 are formed in a grid pattern along the multiple planned cutting lines 66.
  • a process for forming a second mask 72 having a predetermined pattern is carried out (step S10 in FIG. 15).
  • the second mask 72 is preferably an organic mask (resist mask).
  • the second mask 72 is disposed on the upper end of the semiconductor layer 7, and has a plurality of second openings 72a that expose the plurality of trenches 26 in a one-to-one correspondence.
  • the second openings 72a are formed at intervals in the first direction X, and are each partitioned into bands extending in the second direction Y. In other words, the second openings 72a have an extension direction that extends along the off-direction Do in a planar view.
  • the wafer 60 may be supported horizontally and the pentavalent element may be introduced into the semiconductor layer 7 along the second axial channel C2.
  • the wafer 60 may be supported tilted by an off angle ⁇ o from the horizontal and the pentavalent element may be introduced into the semiconductor layer 7 along the second axial channel C2.
  • the implantation energy of the pentavalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection energy for the inversion column 30 may be approximately equal to the injection energy for the impurity region 15, or may be different from the injection energy for the impurity region 15.
  • the injection energy for the inversion column 30 may be equal to or greater than the injection energy for the impurity region 15.
  • the injection energy for the inversion column 30 may be less than the injection energy for the impurity region 15.
  • the injection temperature of the pentavalent element may be adjusted in the range of 0°C to 1500°C.
  • the injection temperature may have a value that belongs to any one of the following ranges: 0°C to 25°C, 25°C to 50°C, 50°C to 100°C, 100°C to 250°C, 250°C to 500°C, 500°C to 750°C, 750°C to 1000°C, 1000°C to 1250°C, and 1250°C to 1500°C.
  • the injection angle of the pentavalent element is preferably set within a range of ⁇ 2° with respect to the axis along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the injection angle of the pentavalent element is set within a range of ⁇ 1° with respect to the axis along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).
  • the second openings 72a have an extension direction that extends along the off-direction Do, and the injection angle of the pentavalent element is inclined to the off-direction Do. Therefore, the pentavalent element is introduced into the semiconductor layer 7 through the second openings 72a almost perpendicular to the bottom wall of the trench 26 in a cross-sectional view perpendicular to the extension direction.
  • the multiple trench structures 25 each include a trench 26, an insulating film 27, a buried electrode 28, and a buried insulator 80.
  • the trench 26 has a form similar to that of the first embodiment.
  • the insulating film 27 is formed at a distance from the first main surface 3 (active surface 10) to the bottom wall side of the trench 26, exposing the surface portion of the first main surface 3 (active surface 10) at the opening end of the trench 26. It is preferable that the upper end of the insulating film 27 is located on the first main surface 3 side relative to the middle part of the depth range of the trench 26.
  • the multiple source regions 37 on one side may face the regions between the multiple source regions 37 on the other side in a one-to-one correspondence.
  • the multiple source regions 37 may be arranged in a staggered pattern in a planar view.
  • the multiple source regions 37 have portions exposed from the sidewall of the trench 26 at the opening end of the trench 26, and face the buried electrode 28 and the buried insulator 80 with the insulating film 27 between them.
  • the aforementioned interlayer insulating film 41 has a layered structure including a first insulating film 42 and a second insulating film 43.
  • the first insulating film 42 selectively covers the active surface 10, the outer peripheral surface 11, and the first to fourth connecting surfaces 12A to 12D.
  • the aforementioned gate pad 50, the aforementioned multiple gate wirings 51, and the aforementioned drain pad 53 have the same configuration as in the first embodiment.
  • the aforementioned source pad 52 penetrates into the single contact opening 44 from above the interlayer insulating film 41, and collectively covers the inner parts (buried insulator 80) of the multiple trench structures 25, the multiple source regions 37, and the multiple contact regions 38 within the single contact opening 44.
  • the source pad 52 is electrically insulated from the multiple trench structures 25 (buried electrodes 28) by the buried insulator 80, and is electrically connected to the multiple source regions 37 and multiple contact regions 38 at the first major surface 3 (active surface 10). In this embodiment, the source pad 52 is also electrically connected to exposed portions of the multiple intermediate regions 36 at the first major surface 3.
  • FIG. 20 is a cross-sectional perspective view showing a trench structure 25 according to the third embodiment.
  • the trench structures 25 according to the third embodiment each have a configuration that is a modification of the trench structures 25 according to the second embodiment.
  • the upper insulating film 81 is formed as an insulating film 27 for controlling the channel Ch, and covers the wall surface on the opening side of the trench 26 relative to the bottom of the body region 20.
  • the upper insulating film 81 has a portion that crosses the bottom of the body region 20 and covers the impurity region 15 (non-inversion column 35). In this case, it is preferable that the coverage area of the upper insulating film 81 relative to the body region 20 is larger than the coverage area of the upper insulating film 81 relative to the impurity region 15 (non-inversion column 35).
  • the upper insulating film 81 may include a silicon oxide film. It is preferable that the upper insulating film 81 includes a silicon oxide film made of an oxide of the chip 2.
  • the upper insulating film 81 may have a thickness of 1 nm or more and 100 nm or less. The thickness of the upper insulating film 81 may have a value that belongs to any one of the following ranges: 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the lower insulating film 82 covers the wall surface on the bottom wall side of the trench 26 relative to the bottom of the body region 20.
  • the lower insulating film 82 covers the impurity region 15 (non-inversion column 35).
  • the coverage area of the lower insulating film 82 relative to the impurity region 15 (non-inversion column 35) is larger than the coverage area of the upper insulating film 81 relative to the body region 20.
  • the lower insulating film 82 may include a silicon oxide film.
  • the lower insulating film 82 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.
  • the lower insulating film 82 has a thickness greater than that of the upper insulating film 81.
  • the thickness of the lower insulating film 82 is preferably 10 to 50 times the thickness of the upper insulating film 81.
  • the lower insulating film 82 may have a thickness of 100 nm or more and 500 nm or less.
  • the thickness of the lower insulating film 82 may have a value that belongs to any one of the following ranges: 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or less, and 450 nm or more and 500 nm or less.
  • the facing area of the upper electrode 83 with respect to the body region 20 is larger than the facing area of the upper electrode 83 with respect to the impurity region 15 (non-inverted column 35).
  • the upper electrode 83 is embedded in the trench 26 at a distance from the first main surface 3 (active surface 10) toward the bottom wall of the trench 26, and defines an opening recess that is recessed toward the bottom wall of the trench 26 at the opening end of the trench 26.
  • the upper electrode 83 exposes the surface portion of the first main surface 3 (active surface 10) and the upper end of the upper insulating film 81 at the opening end of the trench 26.
  • a gate potential is applied to the upper electrode 83 as a control potential.
  • the upper electrode 83 controls the inversion and non-inversion of the channel Ch (current path) in the body region 20 in response to the gate potential.
  • the upper electrode 83 may include p-type or n-type conductive polysilicon.
  • the facing area of the lower electrode 84 with respect to the impurity region 15 is larger than the facing area of the upper electrode 83 with respect to the body region 20.
  • the lower electrode 84 extends in a wall shape along the depth direction of the trench 26.
  • the lower electrode 84 has an upper end that protrudes from the lower insulating film 82 toward the upper electrode 83, and is engaged with the lower end of the upper electrode 83.
  • the upper end of the lower electrode 84 faces the upper insulating film 81 (body region 20) horizontally, sandwiching the lower end of the upper electrode 83 therebetween.
  • the intermediate insulating film 85 is interposed between the upper electrode 83 and the lower electrode 84, and electrically insulates the upper electrode 83 and the lower electrode 84 within the trench 26.
  • the intermediate insulating film 85 is continuous with the upper insulating film 81 and the lower insulating film 82.
  • the intermediate insulating film 85 has a thickness smaller than that of the lower insulating film 82. It is preferable that the thickness of the intermediate insulating film 85 is greater than that of the upper insulating film 81.
  • the intermediate insulating film 85 may include a silicon oxide film. It is preferable that the intermediate insulating film 85 includes a silicon oxide film made of an oxide of the lower electrode 84.
  • the buried insulator 80 is buried in the trench 26 (open recess) so as to expose the first principal surface 3 (active surface 10), and covers the upper insulating film 81 and the upper electrode 83 within the recess.
  • the buried insulator 80 is buried in the trench 26 at a distance from the first principal surface 3 (active surface 10) toward the upper electrode 83, and exposes the surface portion of the first principal surface 3 (active surface 10) at the open end of the trench 26.
  • each intermediate region 36 along the sidewall of the trench 26 is formed at a distance from the bottom of the body region 20 toward the bottom wall of the trench structure 25, and faces the body region 20 with a part of the impurity region 15 in between.
  • each intermediate region 36 may be connected to the body region 20.
  • each intermediate region 36 may face the upper electrode 83 with the upper insulating film 81 in between.
  • the aforementioned gate wirings 51 penetrate the interlayer insulating film 41 via the contact openings 44 and are electrically connected to the upper electrodes 83.
  • the gate wirings 51 penetrate the interlayer insulating film 41 via the contact openings 44 and are electrically connected to the upper electrodes 83 and the lower electrodes 84.
  • FIG. 21 is a cross-sectional perspective view showing a trench structure 25 according to the fourth embodiment.
  • the multiple trench structures 25 according to the first embodiment are arranged at intervals in the first direction X (m-axis direction) and each are formed in a band shape extending in the second direction Y (a-axis direction).
  • the multiple trench structures 25 may each be formed in a band shape extending in the first direction X (m-axis direction) and arranged at intervals in the second direction Y (a-axis direction).
  • the impurity region 15 in the first modified example has a bottom located within the base layer 6 across the boundary between the base layer 6 and the semiconductor layer 7.
  • the bottom of the impurity region 15 is located in the surface layer of the base layer 6. Since the second axial channel C2 is approximately coincident with the first axial channel C1, the bottom of the impurity region 15 is formed along the first axial channel C1 within the base layer 6.
  • the aforementioned inversion column 30 crosses the bottom of the impurity region 15 in the base layer 6 and has a lower end electrically connected to the base layer 6.
  • the lower end of the inversion column 30 is located in the surface layer of the base layer 6. Since the second axial channel C2 is approximately coincident with the first axial channel C1, the lower end of the inversion column 30 is formed along the first axial channel C1 in the base layer 6.
  • FIG. 23 is a cross-sectional perspective view showing a SiC semiconductor device 1 according to a second modified example.
  • the impurity region 15 was formed in the semiconductor layer 7.
  • a p-type semiconductor layer 7 (a p-type epitaxial layer) is formed, and the p-type impurity region 15 is omitted.
  • the p-type semiconductor layer 7 is distinguished from the impurity region 15 in that it does not have the first gradually increasing portion 16, the first peak portion 17, the first gradual portion 18, or the first gradually decreasing portion 19.
  • the p-type impurity concentration of the semiconductor layer 7 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the semiconductor layer 7 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the p-type impurity concentration of the semiconductor layer 7 may be approximately constant in the thickness direction.
  • the p-type impurity concentration of the semiconductor layer 7 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the p-type impurity concentration of the semiconductor layer 7 may be adjusted by at least one trivalent element.
  • the trivalent element of the semiconductor layer 7 may be at least one of boron, aluminum, gallium, and indium.
  • the trivalent element of the semiconductor layer 7 is typically boron or aluminum.
  • a configuration including a p-type impurity region 15 may be adopted.
  • the p-type impurity concentration of the p-type semiconductor layer 7 is corrected (adjusted) by the p-type impurity region 15.
  • the buffer layer 86 has a third axis channel C3 along the stacking direction.
  • the third axis channel C3 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the buffer layer 86, and is surrounded by atomic rows along a crystal axis that extends in the stacking direction (crystal growth direction).
  • the third axis channel C3 is a region in which the atomic rows extend in the stacking direction and the atomic rows (atomic distance/atomic density) in the horizontal direction are sparse in a planar view. It is preferable that the third axis channel C3 is a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.
  • the n-type impurity concentration of the buffer layer 86 is preferably adjusted with at least nitrogen.
  • the buffer layer 86 preferably contains nitrogen and a pentavalent element other than nitrogen.
  • the buffer layer 86 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.
  • the semiconductor layer 7 is stacked on the buffer layer 86.
  • the semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the buffer layer 86. Therefore, the semiconductor layer 7 has an off-direction Do and an off-angle ⁇ o that are approximately the same as the off-direction Do and off-angle ⁇ o of the buffer layer 86.
  • the second axis channel C2 is approximately the same as the third axis channel C3.
  • the second thickness T2 of the semiconductor layer 7 is preferably greater than the third thickness T3.
  • the second thickness T2 may be less than the third thickness T3.
  • the second thickness T2 may be approximately equal to the third thickness T3.
  • the impurity region 15 may have a bottom located in the semiconductor layer 7, and the inversion column 30 may have a lower end located in the base layer 6, the semiconductor layer 7, or the buffer layer 86.
  • the impurity region 15 may have a bottom located in the buffer layer 86, and the inversion column 30 may have a lower end located in the base layer 6 or the buffer layer 86.
  • the above-mentioned embodiment can be implemented in other forms.
  • the above-mentioned embodiment employs the base layer 6, semiconductor layer 7, and buffer layer 86, each of which contains a SiC single crystal.
  • the base layer 6, semiconductor layer 7, and buffer layer 86 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • a wide band gap semiconductor is a semiconductor having a band gap larger than that of silicon.
  • Examples of single crystals of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga 2 O 3 ).
  • the base layer 6, the semiconductor layer 7, and the buffer layer 86 may be made of the same type of single crystal, or may be made of different types of single crystal.
  • the low-index crystal axis of a cubic crystal is a crystal axis in which the absolute values of "h", "k” and “l” in the Miller indices (h, k, l) are all 2 or less (preferably 1 or less).
  • the base layer 6, the semiconductor layer 7 and the buffer layer 86 may contain single crystal silicon.
  • an n-type base layer 6 is shown.
  • a p-type base layer 6 may be adopted.
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure.
  • the "source” of the MISFET structure is replaced with the "emitter” of the IGBT structure, and the "drain” of the MISFET structure is replaced with the "collector” of the IGBT structure.
  • the p-type base layer 6 may be a p-type region containing a trivalent element introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.
  • A6 The semiconductor device (1) described in A5, in which the concentration gradient includes a peak value (P2) on the upper end side and a gradual portion (33) in which the impurity concentration gradually decreases at a gradual rate of decrease in the region on the lower end side of the peak value (P2).

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Recrystallisation Techniques (AREA)
PCT/JP2023/046705 2022-12-28 2023-12-26 ＳｉＣ半導体装置 Ceased WO2024143384A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020047623A (ja) * 2018-09-14 2020-03-26 株式会社東芝 半導体装置
JP2020191327A (ja) * 2019-05-20 2020-11-26 株式会社豊田中央研究所 半導体装置とその製造方法
JP2021089916A (ja) * 2019-12-02 2021-06-10 富士電機株式会社 炭化珪素半導体装置の製造方法、炭化珪素基板の製造方法および炭化珪素基板
JP2022093100A (ja) * 2020-12-11 2022-06-23 株式会社デンソー 炭化珪素半導体装置およびその製造方法
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020047623A (ja) * 2018-09-14 2020-03-26 株式会社東芝 半導体装置
JP2020191327A (ja) * 2019-05-20 2020-11-26 株式会社豊田中央研究所 半導体装置とその製造方法
JP2021089916A (ja) * 2019-12-02 2021-06-10 富士電機株式会社 炭化珪素半導体装置の製造方法、炭化珪素基板の製造方法および炭化珪素基板
JP2022093100A (ja) * 2020-12-11 2022-06-23 株式会社デンソー 炭化珪素半導体装置およびその製造方法
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

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