WO2024143382A1 - ＳｉＣ半導体装置 - Google Patents

ＳｉＣ半導体装置 Download PDF

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Publication number
WO2024143382A1
WO2024143382A1 PCT/JP2023/046703 JP2023046703W WO2024143382A1 WO 2024143382 A1 WO2024143382 A1 WO 2024143382A1 JP 2023046703 W JP2023046703 W JP 2023046703W WO 2024143382 A1 WO2024143382 A1 WO 2024143382A1
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inversion
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French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024567873A priority Critical patent/JPWO2024143382A1/ja
Priority to CN202380088390.XA priority patent/CN120419307A/zh
Priority to DE112023004893.2T priority patent/DE112023004893T5/de
Publication of WO2024143382A1 publication Critical patent/WO2024143382A1/ja
Priority to US19/243,722 priority patent/US20250318213A1/en
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Definitions

  • FIG. 35 is a sectional perspective view showing a gate structure according to the fifth embodiment.
  • FIG. 36 is a plan view showing a SiC semiconductor device according to the third embodiment.
  • 37A is a cross-sectional view taken along line XXXVIIA-XXXVIIA shown in FIG. 36.
  • FIG. 37B is a cross-sectional view taken along line XXXVIIB-XXXVIIB shown in FIG. 36.
  • FIG. 38A is a plan view showing an example of a chip layout.
  • FIG. 38B is a plan view showing an example of a chip layout.
  • FIG. 39 is a perspective view showing an example of a chip layout.
  • FIG. 40 is a perspective view showing the configuration of the outer circumferential area.
  • FIG. 40 is a perspective view showing the configuration of the outer circumferential area.
  • FIG. 41 is a cross-sectional perspective view showing a diode structure according to the first embodiment.
  • FIG. 42 is a cross-sectional perspective view showing a diode structure according to the second embodiment.
  • FIG. 43 is a cross-sectional perspective view showing a diode structure according to the third embodiment.
  • FIG. 44 is a cross-sectional perspective view showing a diode structure according to the fourth embodiment.
  • FIG. 45 is a cross-sectional perspective view showing a diode structure according to the fifth embodiment.
  • FIG. 46 is a cross-sectional perspective view showing a reversing column according to a first modified example.
  • FIG. 47 is a cross-sectional perspective view showing a reversing column according to the second modified example.
  • FIG. 48 is a cross-sectional perspective view showing a reversing column according to the third modified example.
  • FIG. 49 is a cross-sectional perspective view showing a reversing column according to the fourth modified example.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the “first conductivity type” and “p-type” as the “second conductivity type”.
  • p-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • SiC semiconductor device 1A includes chip 2 including SiC single crystal.
  • Chip 2 may be referred to as a "SiC chip” or a “semiconductor chip".
  • chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape.
  • the hexagonal SiC single crystal has multiple polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc.
  • chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of other polytypes.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the second side 5B is connected to the first side 5A
  • the third side 5C is connected to the second side 5B
  • the fourth side 5D is connected to the first side 5A and the third side 5C.
  • the first side 5A and the third side 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X.
  • the second side 5B and the fourth side 5D extend in the second direction Y and face the first direction X.
  • the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal
  • the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal.
  • the first side 5A and the third side 5C are each formed by the m-plane ((1-100) plane) of the SiC single crystal.
  • the second side 5B and the fourth side 5D are each formed by the a-plane ((11-20) plane) of the SiC single crystal.
  • the a-plane is a crystal plane perpendicular to the a-axis direction
  • the m-plane is a crystal plane perpendicular to the m-axis direction.
  • the first direction X may be the m-axis direction of the SiC single crystal
  • the second direction Y may be the a-axis direction of the SiC single crystal.
  • the first to fourth side surfaces 5A to 5D may each be a ground surface.
  • the first to fourth side surfaces 5A to 5D may each be a cleavage surface.
  • the XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z.
  • the axis extending along the vertical direction Z may be referred to as the "vertical axis.”
  • the first direction X and the second direction Y may be referred to as the "horizontal direction.”
  • the horizontal direction is also the direction extending along the first main surface 3.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle ⁇ off inclined at a predetermined angle in a predetermined off direction Doff with respect to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined by the off angle ⁇ off from the vertical axis toward the off direction Doff.
  • the c-plane of the SiC single crystal is inclined by the off angle ⁇ off with respect to the horizontal plane.
  • the off-direction Doff is preferably the a-axis direction of the SiC single crystal (i.e., the first direction X).
  • the off-angle ⁇ off may be greater than 0° and less than or equal to 10°.
  • the off-angle ⁇ off may have a value that falls within any one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle ⁇ off is preferably 5° or less. It is particularly preferable that the off angle ⁇ off is 2° or more and 4.5° or less.
  • the off angle ⁇ off is typically set in the range of 4° ⁇ 0.1°. Of course, this specification does not exclude a configuration in which the off angle ⁇ off is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the chip 2 includes an n-type base layer 6 made of SiC single crystal.
  • the base layer 6 may also be referred to as a "base SiC layer", a “base region”, etc.
  • the base layer 6 extends in a layered manner in the horizontal direction and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate).
  • the base layer 6 has the off direction Doff and off angle ⁇ off described above.
  • the base layer 6 has a base axis channel CHB along the stacking direction.
  • the base axis channel CHB is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the base layer 6, and is surrounded by atomic rows that form a crystal axis that extends in the stacking direction (crystal growth direction).
  • the base axis channel CHB is a region in which the atomic rows extend in the stacking direction and the horizontal atomic rows (atomic distance/atomic density) are sparse in plan view.
  • the base axis channel CHB is preferably a region surrounded by atomic rows along low-index crystal axes among the crystal axes.
  • the low-index crystal axes are crystal axes in which the absolute values of "a1", “a2", “a3” and “c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c) (the same applies hereinafter in this specification).
  • the base axis channel CHB is composed of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal.
  • the base axis channel CHB extends along the c-axis and has the off-direction Doff and off-angle ⁇ off described above.
  • the base axis channel CHB is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the base layer 6 may have a peak n-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction.
  • the n-type impurity concentration of the base layer 6 is preferably adjusted by a single type of pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted by a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted by nitrogen.
  • the base layer 6 has a base thickness TB.
  • the base thickness TB may be 5 ⁇ m or more and 300 ⁇ m or less.
  • the base thickness TB may have a value belonging to any one of the following ranges: 5 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 250 ⁇ m or less, and 250 ⁇ m or more and 300 ⁇ m or less.
  • the base thickness TB is preferably 50 ⁇ m or more and 250 ⁇ m or less.
  • the chip 2 includes a laminated portion 7 laminated on a base layer 6.
  • the laminated portion 7 may be referred to as a "semiconductor layer", a “SiC layer”, a “SiC laminated portion”, a “semiconductor laminated portion”, etc.
  • the laminated portion 7 has a laminated structure in which multiple (two or more) semiconductor layers made of SiC single crystal are laminated.
  • the multiple semiconductor layers are provided as layers for forming a superjunction structure SJ.
  • the number of layers of multiple semiconductor layers (superjunction structure SJ) is arbitrary and is adjusted appropriately depending on the electrical characteristics to be achieved. Examples of electrical characteristics include a breakdown voltage value (breakdown voltage) and a resistance value.
  • the number of layers of the multiple semiconductor layers is typically 2 to 5 (2, 3, 4, or 5).
  • the stacked portion 7 has a two-layer structure including an n-type first layer 8 made of SiC single crystal and an n-type second layer 9 made of SiC single crystal.
  • the first layer 8 may be referred to as the "first SiC layer”, the “first semiconductor layer”, etc.
  • the second layer 9 may be referred to as the "second SiC layer”, the "second semiconductor layer”, etc.
  • the first layer 8 is laminated on the base layer 6.
  • the first layer 8 extends horizontally in a layered manner, forming the middle part of the chip 2 and part of the first to fourth side faces 5A to 5D.
  • the first layer 8 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the base layer 6.
  • the first layer 8 has a lower end and an upper end.
  • the lower end of the first layer 8 is the starting point of crystal growth, and the upper end of the first layer 8 is the end point of crystal growth. Since the first layer 8 is grown continuously from the base layer 6, the lower end of the first layer 8 coincides with the upper end of the base layer 6.
  • the boundary between the base layer 6 and the first layer 8 is not necessarily visible, and can be indirectly evaluated and/or determined from other configurations or elements.
  • the first layer 8 has an off-direction Doff and an off-angle ⁇ off that are approximately the same as the off-direction Doff and off-angle ⁇ off of the base layer 6.
  • the first layer 8 has a first axis channel CH1 along the stacking direction.
  • the first axis channel CH1 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the first layer 8, and is surrounded by atomic rows along a crystal axis that extends in the stacking direction (crystal growth direction).
  • the first axis channel CH1 is a region in which the atomic rows extend in the stacking direction and the atomic rows (atomic distance/atomic density) in the horizontal direction are sparse in a planar view. It is preferable that the first axis channel CH1 is a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.
  • the first axis channel CH1 consists of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the first axis channel CH1 extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the first axis channel CH1 is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the n-type impurity concentration of the first layer 8 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the first layer 8 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the first layer 8 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the first layer 8 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the n-type impurity concentration of the first layer 8 is adjusted by nitrogen.
  • the first layer 8 may have an n-type impurity concentration adjusted by at least one pentavalent element.
  • the n-type impurity concentration of the first layer 8 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • the second layer 9 has a second axial channel CH2 that runs along the stacking direction.
  • the second axial channel CH2 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the second layer 9, and is surrounded by atomic rows that run along the crystal axis that extends in the stacking direction (crystal growth direction).
  • the second axis channel CH2 consists of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the second axis channel CH2 extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the second axis channel CH2 is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the second thickness T2 is preferably 1 ⁇ m or more.
  • the second thickness T2 is preferably 5 ⁇ m or less.
  • the second thickness T2 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the SiC semiconductor device 1A includes an active region 10 set in the chip 2.
  • the active region 10 is set in the inner part of the chip 2 at a distance from the periphery of the chip 2 (first to fourth side faces 5A to 5D) in a plan view.
  • the active region 10 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar area of the active region 10 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the SiC semiconductor device 1A includes a peripheral region 11 that is set outside the active region 10 in the chip 2.
  • the peripheral region 11 is provided in a region between the periphery of the chip 2 and the active region 10 in a planar view.
  • the peripheral region 11 extends in a band shape along the active region 10 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 10.
  • the first impurity region 12 is a p-type channeling region that extends along the first axial channel CH1 in the first layer 8 in a cross-sectional view.
  • the first impurity region 12 is an impurity region that is introduced parallel or nearly parallel to a region (first axial channel CH1) surrounded by atomic rows along the low-index crystal axis in the first layer 8, and extends at an angle with respect to the first main surface 3.
  • the first impurity region 12 has an off direction Doff and an off angle ⁇ off that are approximately equal to the off direction Doff and the off angle ⁇ off of the first axial channel CH1.
  • the first impurity region 12 is inclined from the vertical axis toward the off direction Doff by the off angle ⁇ off.
  • the first impurity region 12 has a lower end located on the lower end side of the first layer 8, and an upper end located on the upper end side of the first layer 8.
  • the lower end of the first impurity region 12 is located in a region on the lower end side of the first layer 8 with respect to the intermediate part of the thickness range of the first layer 8
  • the upper end of the first impurity region 12 is located in a region on the upper end side of the first layer 8 with respect to the intermediate part of the thickness range of the first layer 8.
  • the first impurity region 12 is made up of a single impurity region having a thickness (depth) that crosses the intermediate part of the first layer 8 along the first axial channel CH1.
  • the lower end of the first impurity region 12 may be formed at a distance from the lower end of the first layer 8 (i.e., the base layer 6) toward the upper end, and may face the base layer 6 across a part (lower end) of the first layer 8.
  • the lower end of the first impurity region 12 may be approximately coincident with the lower end of the first layer 8 and connected to the base layer 6.
  • the lower end of the first impurity region 12 may have an extension that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6. Since the first axis channel CH1 is approximately coincident with the base axis channel CHB, the extension of the first impurity region 12 is formed along the base axis channel CHB within the first layer 8.
  • the upper end of the first impurity region 12 may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face the upper end of the first layer 8 across a part (upper end) of the first layer 8.
  • the upper end of the first impurity region 12 may be approximately coincident with the upper end of the first layer 8 and connected to the second layer 9.
  • the distance between the upper end of the first layer 8 and the upper end of the first impurity region 12 may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the upper ends of the first layer 8 and the upper end may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the first impurity region 12 may be formed in almost the entire area of the first layer 8.
  • the first impurity region 12 may invert the conductivity type of almost the entire area of the first layer 8 from n-type to p-type.
  • the first layer 8 may be considered to be a p-type first layer 8.
  • the thickness of the first impurity region 12 may be less than the first thickness T1 of the first layer 8. The thickness of the first impurity region 12 may be greater than the first thickness T1. The thickness of the first impurity region 12 may be approximately equal to the first thickness T1. The thickness of the first impurity region 12 may be less than the second thickness T2 of the second layer 9. The thickness of the first impurity region 12 may be greater than the second thickness T2. The thickness of the first impurity region 12 may be approximately equal to the second thickness T2.
  • the thickness of the first impurity region 12 is preferably 1 ⁇ m or more.
  • the thickness of the first impurity region 12 is preferably 5 ⁇ m or less.
  • the thickness of the first impurity region 12 may have a value belonging to any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the SiC semiconductor device 1A includes a p-type second impurity region 13 formed in at least a portion of the second layer 9 located in the active region 10.
  • the second impurity region 13 is extended from the active region 10 to the peripheral region 11.
  • the second impurity region 13 is extended from a portion of the second layer 9 located in the active region 10 to a portion of the second layer 9 located in the peripheral region 11.
  • the second impurity region 13 extends from the outer periphery region 11 toward the first to fourth side faces 5A to 5D and is exposed from the first to fourth side faces 5A to 5D.
  • the second impurity region 13 may be formed in the second layer 9 at a distance inward from the first to fourth side faces 5A to 5D.
  • the peripheral portion of the second impurity region 13 may be located in the active region 10 or in the outer periphery region 11.
  • the p-type impurity concentration (peak value) of the second impurity region 13 may be equal to or greater than the p-type impurity concentration (peak value) of the first impurity region 12.
  • the n-type impurity concentration (peak value) of the second impurity region 13 may be less than the n-type impurity concentration (peak value) of the first impurity region 12.
  • the n-type impurity concentration (peak value) of the second impurity region 13 may be approximately equal to the n-type impurity concentration (peak value) of the first impurity region 12.
  • the gradual decrease portion 22 has a thickness of 1 ⁇ m or more and 1.3 ⁇ m or less, and has a concentration decrease rate of 50% or less within this thickness range.
  • the p-type impurity concentration of the gradual decrease portion 22 is within a concentration range of 3 ⁇ 10 16 cm -3 or more and 6 ⁇ 10 16 cm -3 or less.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual decrease portion 22 to 1 ⁇ 10 15 cm -3 .
  • the second impurity region 13 (960 KeV) has a thickness of 3.1 ⁇ m or more and 3.3 ⁇ m or less, and has an upper end spaced from the upper end (first main surface 3) of the second layer 9 toward the lower end (first layer 8 side), and a lower end located within the first layer 8.
  • the gradual decrease portion 22 has a thickness of 1.3 ⁇ m or more and 1.7 ⁇ m or less, and has a concentration decrease rate of 50% or less within this thickness range.
  • the p-type impurity concentration of the gradual decrease portion 22 is within a concentration range of 2.2 ⁇ 10 16 cm -3 or more and 4.5 ⁇ 10 16 cm -3 or less.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual decrease portion 22 to 1 ⁇ 10 15 cm -3 .
  • the gradual portion 22 has a thickness of 1.5 ⁇ m or more and 1.8 ⁇ m or less, and has a concentration decrease rate of 50% or less in this thickness range.
  • the gradual portion 22 crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. That is, the extension of the second impurity region 13 includes a part of the gradual portion 22.
  • the p-type impurity concentration of the gradual portion 22 is within a concentration range of 2 ⁇ 10 16 cm ⁇ 3 or more and 4 ⁇ 10 16 cm ⁇ 3 or less.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual portion 22 to 1 ⁇ 10 15 cm ⁇ 3 .
  • the p-type impurity concentration of the second impurity region 13 has a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 at any implantation energy.
  • the thickness (depth) of the second impurity region 13 increases with increasing implantation energy.
  • the depth position of the upper end of the second impurity region 13 relative to the upper end of the second layer 9 increases with increasing implantation energy.
  • a second impurity region 13 having a relatively large thickness for example, a thickness of 1 ⁇ m or more and 5 ⁇ m or less
  • a second thickness T2 for example, a second thickness T2 of 1 ⁇ m or more
  • SiC single crystals have physical properties that make it difficult for impurities to diffuse. Therefore, the above problem is generally solved by a multi-epitaxial growth method or a multi-stage random injection method.
  • the second impurity region 13 having the slow portion 22 with a thickness of 0.5 ⁇ m to 2 ⁇ m is formed in the second layer 9 having a relatively large thickness (for example, a thickness of 1 ⁇ m to 5 ⁇ m). Therefore, the second impurity region 13 is formed with fewer steps than when the random injection method is adopted.
  • each second impurity region 13 is composed of an integrated region of multiple impurity regions (second impurity regions 13) formed in the second layer 9 along the second axial channel CH2 so as to cross the middle part of the second layer 9.
  • the p-type impurity concentration (concentration gradient) of each second impurity region 13 is the sum of the p-type impurity concentrations (concentration gradients) of the multiple impurity regions (second impurity regions 13).
  • the p-type impurity concentration of each second impurity region 13 has a concentration gradient (sum of concentration gradients) obtained by superimposing at least two of the five graphs shown in Figures 6A to 6E.
  • the amount of trivalent elements passing through the upper end of the second layer 9 increases, and the range of the free space on the upper end side (i.e., the distance between the first main surface 3 and the second impurity region 13) expands, making it more difficult to design the second impurity region 13.
  • the size of the ion accelerator may reach several tens of meters, which is considered to be unrealistic from the standpoint of cost-effectiveness (installation space and capital investment). Therefore, when forming a relatively thick second impurity region 13 by channeling implantation, it is preferable to limit the implantation energy to 2000 KeV or less and increase the number of layers in the stacked portion 7.
  • the SiC semiconductor device 1A includes a plurality of first inversion columns 14 of n-type formed in at least a portion of the first layer 8 located in the active region 10.
  • the first inversion columns 14 may be referred to as "first inversion regions" or the like.
  • the plurality of first inversion columns 14 are formed at intervals in the horizontal direction in the first layer 8, and invert the conductivity type of the first impurity region 12 from p-type to n-type.
  • the first inversion columns 14 include a pentavalent element in the first layer 8 and a trivalent element in the first impurity region 12.
  • the first inversion columns 14 are arranged at intervals in the first arrangement direction Da1 in the first layer 8, and are each formed in a strip shape extending in the first extension direction De1.
  • the first extension direction De1 is a direction that intersects or is perpendicular to the first arrangement direction Da1. In other words, the first inversion columns 14 are formed in a stripe shape extending in the first extension direction De1.
  • the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y).
  • first arrangement direction Da1 may be the m-axis direction
  • first extension direction De1 may be the a-axis direction
  • first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction
  • first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple first inversion columns 14 are extended from the active region 10 to the outer circumferential region 11 (see FIG. 3A). That is, the multiple first inversion columns 14 are extended from a portion of the first layer 8 located within the active region 10 to a portion of the first layer 8 located within the outer circumferential region 11.
  • the multiple first inversion columns 14 are also arranged at intervals in the first array direction Da1 in the outer circumferential region 11, and are each formed in a band shape extending in the first extension direction De1.
  • first inversion columns 14 each extend from the outer peripheral region 11 toward either or both of the first side 5A and the third side 5C (both in this embodiment), and each have a portion exposed from either or both of the first side 5A and the third side 5C (both in this embodiment).
  • the first inversion columns 14 are made of n-type channeling regions that extend along the first axial channel CH1 in the first layer 8 in a cross-sectional view.
  • the first inversion columns 14 are made of impurity regions that are introduced parallel or nearly parallel to the region (first axial channel CH1) surrounded by the atomic rows along the low-index crystal axis in the first layer 8, and extend at an angle with respect to the first main surface 3.
  • the first reversing columns 14 have an off direction Doff and an off angle ⁇ off that are approximately equal to the off direction Doff and the off angle ⁇ off of the first axis channel CH1. In other words, the first reversing columns 14 are inclined from the vertical axis toward the off direction Doff by the off angle ⁇ off.
  • the first inversion columns 14 each have a lower end located at the lower end side of the first layer 8 and an upper end located at the upper end side of the first layer 8.
  • the lower ends of the first inversion columns 14 are located in a region on the lower end side of the first layer 8 relative to the intermediate part of the thickness range of the first layer 8
  • the upper ends of the first inversion columns 14 are located in a region on the upper end side of the first layer 8 relative to the intermediate part of the thickness range of the first layer 8.
  • the first inversion columns 14 are made of a single impurity region having a thickness (depth) that crosses the intermediate part of the first layer 8 along the first axial channel CH1.
  • the lower ends of the multiple first inversion columns 14 preferably have an extension that crosses the lower end of the first impurity region 12.
  • the extensions of the multiple first inversion columns 14 preferably cross the lower end of the first impurity region 12 within the base layer 6 and are connected to the base layer 6.
  • the extensions of the first inversion columns 14 cross the lower end of the first impurity region 12 within the first layer 8 and are connected to at least the first layer 8.
  • the extensions of the first inversion columns 14 may cross the boundary between the base layer 6 and the first layer 8 and be located in the surface layer of the base layer 6.
  • the extension of the first inverted column 14 is formed along the base axis channel CHB in the base layer 6.
  • the extensions of the multiple first inverted columns 14 may be formed at intervals from the lower end of the first layer 8 to the upper end of the first layer 8.
  • the thickness of the extension of the first inversion column 14 based on the lower end of the first impurity region 12 may be more than 0 ⁇ m and not more than 2 ⁇ m.
  • the thickness of the extension of the first inversion column 14 may have a value that belongs to any one of the following ranges: more than 0 ⁇ m and not more than 0.5 ⁇ m, 0.5 ⁇ m or more to 1 ⁇ m or less, 1 ⁇ m or more to 1.5 ⁇ m or less, and 1.5 ⁇ m or more to 2 ⁇ m or less.
  • the upper end of the first inversion column 14 may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face the upper end of the first layer 8 across a portion (upper end) of the first layer 8.
  • the upper end of the first inversion column 14 may be approximately coincident with the upper end of the first layer 8 and connected to the second layer 9.
  • the distance between the upper end of the first layer 8 and the upper end of the first inversion column 14 may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the upper end of the first layer 8 and the upper end of the first inversion column 14 may have a value that belongs to any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the first inversion columns 14 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the n-type impurity concentration of the first inversion columns 14 is preferably adjusted by at least one pentavalent element.
  • the n-type impurity concentration of the first inversion columns 14 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • the first inversion column 14 preferably contains a pentavalent element other than nitrogen and phosphorus.
  • the n-type impurity concentration of the first inversion column 14 is preferably adjusted with at least one of arsenic, antimony, and bismuth. In view of availability, the n-type impurity concentration of the first inversion column 14 is preferably adjusted with arsenic or antimony.
  • the first inversion columns 14 each have a first width W1.
  • the first width W1 is the width along the first arrangement direction Da1 of the first inversion columns 14. It is preferable that the first width W1 is less than the first thickness T1 of the first layer 8. Of course, the first width W1 may be equal to or greater than the first thickness T1. It is preferable that the first width W1 is less than the second thickness T2 of the second layer 9. Of course, the first width W1 may be equal to or greater than the second thickness T2.
  • the first width W1 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 may have a value belonging to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the first inversion columns 14 each have a first region thickness TR1 (first region depth).
  • the first region thickness TR1 may be less than the first thickness T1 of the first layer 8.
  • the first region thickness TR1 may be greater than the first thickness T1.
  • the first region thickness TR1 may be approximately equal to the first thickness T1.
  • the first region thickness TR1 may be less than the second thickness T2 of the second layer 9.
  • the first region thickness TR1 may be greater than the second thickness T2.
  • the first region thickness TR1 may be approximately equal to the second thickness T2.
  • the first region thickness TR1 is preferably 1 ⁇ m or more.
  • the first region thickness TR1 is preferably 5 ⁇ m or less.
  • the first region thickness TR1 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 is less than the first thickness T1 of the first layer 8, and that the first region thickness TR1 is greater than the first width W1.
  • each of the first inverted columns 14 has a first aspect ratio TR1/W1 that extends in a vertically elongated columnar shape along the first axial channel CH1.
  • the first aspect ratio TR1/W1 is the ratio of the first region thickness TR1 to the first width W1.
  • the first region thickness TR1 is greater than the first thickness T1.
  • the first aspect ratio TR1/W1 may be greater than 1 and less than or equal to 100.
  • the first pitch P1 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first pitch P1 may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first pitch P1 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the multiple first inversion columns 14 differ from the second impurity region 13 (first impurity region 12) in that they are composed of a pentavalent element, but like the second impurity region 13 (first impurity region 12), the multiple first inversion columns 14 have a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 from the upper end to the lower end (see also Figures 6A to 6E).
  • the concentration gradient of the first inversion column 14 can be explained by replacing “second impurity region 13" with “first inversion column 14" and "p-type (trivalent element)” with “n-type (pentavalent element)” in the explanation of the concentration gradient of the second impurity region 13 (first impurity region 12) described above (also see Figures 6A to 6E).
  • the multiple first non-inversion columns 15 are made of p-type channeling regions that extend along the first axial channel CH1 in the first layer 8 in a cross-sectional view, and are partitioned at intervals in the horizontal direction in the first layer 8. Specifically, the multiple first non-inversion columns 15 are arranged at intervals in the first array direction Da1 in the first layer 8, and are each partitioned into bands extending in the first extension direction De1.
  • the first non-inverting columns 15 form a first pn junction having charge balance together with the first inverting columns 14.
  • the first non-inverting columns 15 and the first inverting columns 14 form a first superjunction structure SJ1.
  • the SiC semiconductor device 1A includes a plurality of n-type second inversion columns 16 formed in at least a portion of the second layer 9 located in the active region 10.
  • the second inversion columns 16 may be referred to as "second inversion regions" or the like.
  • the plurality of second inversion columns 16 are formed at intervals in the horizontal direction in the second layer 9, and invert the conductivity type of the second impurity region 13 from p-type to n-type.
  • the second inversion columns 16 include a pentavalent element in the second layer 9 and a trivalent element in the second impurity region 13.
  • the second extension direction De2 is a direction that intersects or is perpendicular to the second arrangement direction Da2.
  • the second inversion columns 16 are formed in a stripe shape extending in the second extension direction De2.
  • the second arrangement direction Da2 is the m-axis direction (second direction Y)
  • the second extension direction De2 is the a-axis direction (first direction X).
  • the second arrangement direction Da2 may be the a-axis direction and the second extension direction De2 may be the m-axis direction.
  • the first arrangement direction Da1 is a direction other than the a-axis direction and the m-axis direction and the first extension direction De1 is a direction other than the a-axis direction and the m-axis direction
  • the second arrangement direction Da2 may be one of the a-axis direction and the m-axis direction and the second extension direction De2 may be the other of the a-axis direction and the m-axis direction.
  • the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction
  • the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.
  • the second inverted columns 16 are also arranged at intervals in the second arrangement direction Da2 in the outer peripheral region 11, and are each formed in a band shape extending in the second extension direction De2. In other words, the second inverted columns 16 intersect with the first inverted columns 14 and the first non-inverted columns 15 in the outer peripheral region 11.
  • the second inversion columns 16 are made of n-type channeling regions that extend along the second axial channel CH2 in the second layer 9 in a cross-sectional view.
  • the second inversion columns 16 are made of impurity regions that are introduced parallel or nearly parallel to the region (second axial channel CH2) surrounded by the atomic rows along the low-index crystal axis in the second layer 9, and extend at an angle with respect to the first main surface 3.
  • the second reversing columns 16 have an off direction Doff and an off angle ⁇ off that are approximately equal to the off direction Doff and the off angle ⁇ off of the second axis channel CH2. In other words, the second reversing columns 16 are inclined by the off angle ⁇ off from the vertical axis toward the off direction Doff.
  • the second inversion columns 16 each have a lower end located at the lower end side of the second layer 9 and an upper end located at the upper end side of the second layer 9.
  • the lower ends of the second inversion columns 16 are located in a region on the lower end side of the second layer 9 with respect to the intermediate part of the thickness range of the second layer 9
  • the upper ends of the second inversion columns 16 are located in a region on the upper end side of the second layer 9 with respect to the intermediate part of the thickness range of the second layer 9.
  • the second inversion columns 16 are made of a single impurity region having a thickness (depth) that crosses the intermediate part of the second layer 9 along the second axial channel CH2.
  • the lower ends of the second inversion columns 16 preferably have an extension that crosses the lower end of the second impurity region 13.
  • the extensions of the second inversion columns 16 preferably cross the lower end of the second impurity region 13 within the first layer 8 and are connected to the first layer 8.
  • the extensions of the second inversion columns 16 are connected to the first inversion columns 14 within the first layer 8.
  • the second inversion columns 16, together with the first inversion columns 14, form one three-dimensional lattice-shaped inversion column that extends continuously in the thickness direction. Since the second axial channel CH2 is approximately coincident with the first axial channel CH1, the extensions of the second inversion columns 16 are formed along the first axial channel CH1 within the first layer 8.
  • the extensions of the second inversion columns 16 cross the boundary between the first layer 8 and the second layer 9 and are connected to the first inversion columns 14 within the first layer 8.
  • the extensions of the second inversion columns 16 may be formed at intervals from the lower end of the second layer 9 to the upper end of the second layer 9.
  • the absolute value of the extension angle ⁇ a may be greater than 0° and less than 90°.
  • the extension angle ⁇ a may have a value that falls within any one of the following ranges: greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the absolute value of the extension angle ⁇ a is typically set to a value that falls within any one of the following ranges: 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • the second extension direction De2 may be inclined from the a-axis toward one side (left side of the paper) or the other side (right side of the paper) of the m-axis in a plan view.
  • the second reversal columns 16 have a second extension direction De2 that forms an extension angle ⁇ a with the a-axis when the a-axis is set as the reference (0°).
  • FIG. 12A shows a layout example in which the absolute value of the second extension angle ⁇ 2 is approximately 45° ( ⁇ 1)
  • FIG. 12B shows a layout example in which the absolute value of the second extension angle ⁇ 2 is approximately 30° ( ⁇ 1)
  • FIG. 12C shows a layout example in which the absolute value of the second extension angle ⁇ 2 is approximately 60° ( ⁇ 1).
  • the absolute value of the second extension angle ⁇ 2 may be greater than the absolute value of the first extension angle ⁇ 1, or may be less than the absolute value of the first extension angle ⁇ 1.
  • the second inversion columns 16 may have a layout that is asymmetrical with the first inversion columns 14 about the a-axis in a plan view per unit area (i.e., a partial plan view).
  • the second inversion columns 16 may have a layout that is asymmetrical with the first inversion columns 14 about the vertical axis in a plan view per unit area (i.e., a partial plan view).
  • first to sixth embodiment examples of the multiple first reversing columns 14 and multiple second reversing columns 16 are shown with reference to Figures 13A to 13F.
  • the multiple first reversing columns 14 and multiple second reversing columns 16 according to the first to third basic embodiments may have at least one of the multiple features shown in the first to sixth embodiment examples.
  • the multiple first reversing columns 14 and multiple second reversing columns 16 according to the first to third basic embodiments may have a feature that combines multiple (two or more) features shown in the first to sixth embodiment examples.
  • the n-type impurity concentration of the inversion intermediate column 18 is preferably adjusted by at least one type of pentavalent element.
  • the pentavalent element of the inversion intermediate column 18 may be the same type as the pentavalent element of the first inversion column 14, etc., or may be a different type from the pentavalent element of the first inversion column 14, etc.
  • the pentavalent element of the inversion intermediate column 18 may be at least one type of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • the pentavalent element of the inversion intermediate column 18 is preferably nitrogen or phosphorus.
  • the multiple inverted intermediate columns 18 each have an intermediate thickness TM.
  • the intermediate thickness TM is preferably equal to or greater than the distance between the upper end of the first layer 8 and the upper end of the first inverted column 14.
  • the intermediate thickness TM may be 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the intermediate thickness TM may have a value that falls within any one of the ranges of 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the intermediate pitch PM may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the intermediate pitch PM may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the intermediate pitch PM is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the second inversion column 16 has an extension located within the first layer 8 and is connected to the inversion intermediate column 18 within the first layer 8. In other words, it is preferable that the second inversion column 16 is electrically connected to the first inversion column 14 via the inversion intermediate column 18 within the first layer 8. In this case, the second inversion column 16, together with the first inversion column 14 and the inversion intermediate column 18, forms a single three-dimensional lattice-shaped inversion column that extends continuously in the stacking direction.
  • the extension of the second inversion column 16 may be connected to both the inversion intermediate column 18 and the first inversion column 14 within the first layer 8.
  • the concentration gradient in the region between the first inversion column 14 and the second inversion column 16 is mitigated by the inversion intermediate column 18, improving the accuracy of the charge balance.
  • the multiple inverting intermediate columns 18 are arranged in the first arrangement direction Da1 and formed in a band extending in the first extension direction De1.
  • the multiple inverting intermediate columns 18 may be arranged in the second arrangement direction Da2 and formed in a band extending in the second extension direction De2.
  • the multiple second inverting columns 16 may be connected to the multiple inverting intermediate columns 18 in a one-to-one correspondence.
  • FIG. 13B is a cross-sectional perspective view showing a plurality of first inversion columns 14 and a plurality of second inversion columns 16 according to the second embodiment.
  • the SiC semiconductor device 1A in addition to the plurality of first inversion columns 14 and a plurality of second inversion columns 16, the SiC semiconductor device 1A includes a p-type non-inversion intermediate column 19 interposed between the first non-inversion column 15 and the second non-inversion column 17.
  • Each non-inverted intermediate column 19 may include a single or multiple p-type area elements that form a peak value (peak portion) of the concentration gradient.
  • the single area element is formed in the area between the upper end of the first layer 8 and the upper end of the first non-inverted column 15 and is connected to the upper end of the first non-inverted column 15.
  • the trivalent element of the non-inverted intermediate column 19 may be the same type as the trivalent element of the first non-inverted column 15, etc., or may be a different type from the trivalent element of the first non-inverted column 15, etc.
  • the trivalent element of the non-inverted intermediate column 19 may be at least one of boron, aluminum, gallium, and indium.
  • the multiple non-inverted intermediate columns 19 may have the aforementioned intermediate width WM, intermediate thickness TM, and intermediate pitch PM.
  • the second non-inverted column 17 preferably has an extension located in the first layer 8 and is connected to the non-inverted intermediate column 19 in the first layer 8.
  • the second non-inverted column 17 preferably is electrically connected to the first non-inverted column 15 via the non-inverted intermediate column 19 in the first layer 8.
  • the extension of the second non-inverting column 17 may be connected to both the non-inverting intermediate column 19 and the first non-inverting column 15 in the first layer 8.
  • the concentration gradient in the region between the first non-inverting column 15 and the second non-inverting column 17 is mitigated by the non-inverting intermediate column 19, improving the accuracy of the charge balance.
  • multiple non-inverting intermediate columns 19 are arranged in the first arrangement direction Da1 and formed in a band extending in the first extension direction De1.
  • multiple non-inverting intermediate columns 19 may be arranged in the second arrangement direction Da2 and formed in a band extending in the second extension direction De2.
  • multiple non-inverting intermediate columns 19 may be connected to multiple second non-inverting columns 17 in a one-to-one correspondence.
  • Fig. 13C is a cross-sectional perspective view showing a first inverted column 14 and a second inverted column 16 according to a third embodiment.
  • the SiC semiconductor device 1A has a first inverted column 14 exposed from the upper end of the first layer 8, and a first non-inverted column 15 exposed from the upper end of the first layer 8.
  • the first inversion column 14 may have a concentration gradient in which a portion of the gradually increasing portion 20 is exposed from the upper end of the first layer 8.
  • the first inversion column 14 may have a concentration gradient in which a portion of the peak portion 21 is exposed from the upper end of the first layer 8.
  • the first inversion column 14 may have a gradual portion 22 exposed from the upper end of the first layer 8.
  • the first inversion column 14 has a peak value P at the upper end of the first layer 8, and has a concentration gradient that gradually decreases toward the lower end side of the first layer 8.
  • the second non-inverted column 17 (second impurity region 13) preferably has an extension located within the first layer 8 and is connected to the first non-inverted column 15 within the first layer 8.
  • the concentration gradient formed in the region between the first non-inverted column 15 and the second non-inverted column 17 is mitigated by the exposed portion of the first non-inverted column 15, improving the accuracy of the charge balance.
  • the upper end of the first layer 8 may be partially removed by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the upper end of the first layer 8 comprises an etched surface, and the first inversion column 14 is exposed from the etched surface.
  • the second layer 9 is laminated on top of the etched surface of the first layer 8.
  • the second non-inverted column 17 (second impurity region 13) may have a concentration gradient in which a portion of the gradually increasing portion 20 is exposed from the upper end of the second layer 9.
  • the second non-inverted column 17 may have a concentration gradient in which a portion of the peak portion 21 is exposed from the upper end of the second layer 9.
  • the second non-inverted column 17 may have a gradual portion 22 exposed from the upper end of the second layer 9.
  • the second non-inverted column 17 has a peak value P at the upper end of the second layer 9, and has a concentration gradient that gradually decreases toward the lower end side of the second layer 9.
  • Such a configuration can be obtained by partially removing the upper end of the second layer 9 after the formation of the second inverted column 16 (second non-inverted column 17) until part or all of the increasing portion 20 of the second inverted column 16 (second non-inverted column 17) disappears.
  • the upper end of the second layer 9 may be partially removed by a grinding method.
  • the grinding method may be a mechanical polishing method and/or a chemical mechanical polishing method.
  • the upper end of the second layer 9 is composed of a grinding surface, and the second inverted column 16 is exposed from the grinding surface.
  • the buffer layer 26 includes SiC single crystals and has n-type conductivity.
  • the buffer layer 26 is stacked on the base layer 6.
  • the buffer layer 26 extends in a layered manner in the horizontal direction, forming the middle part of the chip 2 and forming part of the first to fourth side surfaces 5A to 5D.
  • the buffer layer 26 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the base layer 6.
  • the extension of the first inversion column 14 is preferably located on the upper end side of the buffer layer 26 relative to the intermediate part of the thickness range of the buffer layer 26.
  • the extension of the first inversion column 14 includes a tapered portion 23.
  • the extension of the first inversion column 14 may include a part of the gradual portion 22 and the tapered portion 23.
  • the top layer 30 is laminated on the second layer 9.
  • the top layer 30 extends in a layered manner in the horizontal direction, forming the first main surface 3 and forming parts of the first to fourth side surfaces 5A to 5D.
  • the top layer 30 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the second layer 9.
  • the top axis channel CHT is composed of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the top axis channel CHT extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the top axis channel CHT is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the SiC semiconductor device 1A includes a plurality of p-type body regions 32 formed in the active region 10.
  • the plurality of body regions 32 are formed in the surface layer portion of the first main surface 3 so as to overlap the plurality of second non-inverted columns 17 in the stacking direction.
  • the plurality of body regions 32 are arranged at intervals in the second array direction Da2 so as to overlap the plurality of second non-inverted columns 17 in a one-to-one correspondence in the stacking direction, and are each formed in a band shape extending in the second extension direction De2.
  • Each of the body regions 32 is formed wider than the second non-inverted column 17 directly below, and is formed at a distance from the adjacent second non-inverted columns 17 toward the second non-inverted column 17 directly below.
  • the body regions 32 expose a portion of the first layer 8 and/or a portion of the second inverted column 16 from the region of the first main surface 3 between the adjacent second non-inverted columns 17.
  • the body regions 32 unlike the second non-inverted columns 17 etc., do not have a gradual portion 22 having a thickness of 0.5 ⁇ m or more, and have a concentration gradient including a gradually increasing portion 20, a peak portion 21 and a gradually decreasing portion 23 within a range of 0.5 ⁇ m.
  • the body regions 32 may have a peak value of a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the SiC semiconductor device 1A includes one or more p-type contact regions 34 formed in the surface layer of each of the body regions 32 in the active region 10.
  • the contact region 34 may be referred to as a "backgate region.”
  • one contact region 34 is formed in a region between adjacent source regions 33 in the surface layer of each body region 32.
  • the plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32.
  • the p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second inversion columns 16.
  • the plurality of contact regions 34 may have a p-type impurity concentration (peak value) of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less as a peak value.
  • the multiple gate structures 35 are arranged offset from the multiple second non-inversion columns 17 toward the multiple second inversion columns 16, and overlap the multiple second inversion columns 16 in a one-to-one correspondence in the stacking direction.
  • the multiple gate structures 35 are each arranged to straddle two adjacent body regions 32, and each cover the multiple source regions 33 located in one and the other body regions 32.
  • the multiple field regions 38 intersect with multiple second inversion columns 16 and multiple second non-inversion columns 17 in the portion extending in the first extension direction De1, and intersect with multiple first inversion columns 14 and multiple first non-inversion columns 15 in the portion extending in the second extension direction De2.
  • the field regions 38 may have a thickness approximately equal to the thickness of the body regions 32. In this case, the field regions 38 may be formed simultaneously with the body regions 32. Of course, the field regions 38 may have a thickness greater than the thickness of the body regions 32. The field regions 38 may also have a thickness less than the thickness of the body regions 32.
  • the p-type impurity concentration of the multiple field regions 38 is preferably adjusted by at least one type of trivalent element.
  • the trivalent element of the field region 38 may be the same type as the trivalent element of the second non-inversion column 17, etc., or may be a different type from the trivalent element of the second non-inversion column 17, etc.
  • the trivalent element of the field region 38 may be at least one type of boron, aluminum, gallium, and indium.
  • the field regions 38 preferably have a width different from the width of the second non-inverted columns 17.
  • the electric field relaxation effect of the field regions 38 is preferably adjusted separately from the second non-inverted columns 17. It is particularly preferable that the width of the field regions 38 is greater than the width of the second non-inverted columns 17.
  • the width of the field regions 38 may be smaller than the width of the second non-inverted columns 17.
  • the width of the field regions 38 may also be approximately equal to the width of the second non-inverted columns 17.
  • the SiC semiconductor device 1A includes an interlayer insulating film 40 covering the first main surface 3.
  • the interlayer insulating film 40 may be referred to as an "insulating film,” an "interlayer film,” an “intermediate insulating film,” or the like.
  • the interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42.
  • the first insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 41 includes a silicon oxide film made of an oxide of the chip 2 (second layer 9).
  • the first insulating film 41 selectively covers the first main surface 3 in the active region 10 and the peripheral region 11.
  • the first insulating film 41 covers the region outside the gate insulating film 36 in the active region 10 and is connected to the gate insulating film 36.
  • the first insulating film 41 covers a plurality of field regions 38 in the peripheral region 11.
  • the gate pad 45 is arranged in a region along the center of the first side surface 5A on the periphery of the active region 10.
  • the gate pad 45 may be arranged in a region along any of the centers of the first to fourth side surfaces 5A to 5D.
  • the gate pad 45 may be arranged at any corner of the active region 10 in a planar view.
  • the gate pad 45 may be arranged in the center of the active region 10 in a planar view.
  • the gate pad 45 is formed in a rectangular shape in a planar view.
  • the breakdown voltage that can be applied between the source pad 47 and the drain pad 48 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to any one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIG. 19 is a schematic diagram showing a wafer 50 used in the manufacture of the SiC semiconductor device 1A.
  • the wafer 50 is a substrate for the base layer 6 and contains a SiC single crystal.
  • the wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.
  • a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like.
  • Each device region 55 corresponds to the SiC semiconductor device 1A.
  • Each of the plurality of device regions 55 is set to have a rectangular shape in a plan view.
  • step S1 in FIG. 20 the aforementioned wafer 50 preparation process is performed (step S1 in FIG. 20).
  • a determination process is performed as to whether or not an n-type buffer layer 26 (see FIG. 13E) formation process is performed (step S2 in FIG. 20). If a buffer layer 26 is to be formed (step S2 in FIG. 20: YES), the buffer layer 26 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth (step S3 in FIG. 20). If a buffer layer 26 formation process is not performed (step S2 in FIG. 20: NO), this process is omitted.
  • the crystal orientation of the first layer 8 includes a process for measuring the off angle ⁇ off of the first layer 8. In other words, this process includes a process for measuring the crystal orientation of the first axis channel CH1 of the first layer 8.
  • the diffraction angle 2 ⁇ is fixed and the incident angle ⁇ is varied within a small angular range to measure a rocking curve that represents the intensity of the diffracted X-ray L2 (the intensity profile of the diffracted X-ray L2).
  • the rocking curve has the intensity of the diffracted X-ray L2 on the vertical axis and the incident angle ⁇ on the horizontal axis.
  • the incident angle ⁇ is determined as the angle position at which the intensity of the diffracted X-ray L2 reaches its peak value.
  • the first measurement point Po1 is set in the center of the first layer 8.
  • the second measurement point Po2 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to one side in the second direction Y (the opposite side from the mark 54).
  • the third measurement point Po3 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to one side in the first direction X (to the right of the mark 54).
  • the fourth measurement point Po4 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the second direction Y (the side toward the mark 54).
  • the fifth measurement point Po5 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the first direction X (to the left of the mark 54).
  • the average value of the off angle ⁇ off of the first to fifth measurement points Po1 to Po5 was 4.036°, and the standard deviation of these off angles ⁇ off was 0.009° ( ⁇ 0.01°). From this, it can be understood that the in-plane variation of the off angle ⁇ off occurring at the upper end of the first layer 8 (first wafer main surface 51 of wafer 50) is extremely small, and is not enough to interfere with the channeling implantation process.
  • the measurement point may be any one or more (all) of the first to fifth measurement points Po1 to Po5.
  • the measurement point may be only the first measurement point Po1.
  • the off angle ⁇ off may be measured at multiple points on the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50) and an implantation angle may be set in the channeling implantation process according to the in-plane variation of the off angle ⁇ off.
  • the manufacturing man-hours manufactured costs
  • the in-plane error of the first inversion column 14 formed in the first layer 8 is appropriately suppressed.
  • the off-angle ⁇ off of the first layer 8 is approximately equal to the off-angle ⁇ off of the wafer 50 and the off-angle ⁇ off of the buffer layer 26. Therefore, the crystal orientation measurement process may be performed on the wafer 50 or the buffer layer 26 prior to the formation process of the first layer 8. However, from the standpoint of ensuring accuracy, it is preferable that the crystal orientation measurement process be performed on the first layer 8.
  • a trivalent element is introduced into the first layer 8 with a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle ⁇ off) (see also FIG. 7).
  • a trivalent element is implanted along the vertical direction Z perpendicular to the upper end of the first layer 8 (first wafer main surface 51).
  • the wafer 50 may be supported horizontally and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1.
  • the wafer 50 may be supported tilted by the off angle ⁇ off from the horizontal and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1.
  • a plurality of first inversion columns 14 having a predetermined thickness are formed at a predetermined depth (see also Figures 6A to 6E).
  • the implantation energy of the trivalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection temperature of the trivalent element may be adjusted in the range of 0°C to 1500°C.
  • the injection temperature may have a value that belongs to any one of the following ranges: 0°C to 25°C, 25°C to 50°C, 50°C to 100°C, 100°C to 250°C, 250°C to 500°C, 500°C to 750°C, 750°C to 1000°C, 1000°C to 1250°C, and 1250°C to 1500°C.
  • the injection angle of the trivalent element is preferably set within a range of ⁇ 2° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the injection angle of the trivalent element is set within a range of ⁇ 1° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).
  • the trivalent element is introduced along the first axial channel CH1, in which the atomic rows are relatively sparse in plan view.
  • the trivalent element travels through the first axial channel CH1 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the first layer 8.
  • the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.
  • a trivalent element belonging to the heavy elements heavier than carbon is introduced into the first layer 8.
  • the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium).
  • the trivalent element is aluminum.
  • an annealing method may be used to electrically activate the trivalent element and repair lattice defects and the like that have occurred in the first layer 8.
  • the annealing temperature for the first layer 8 may be 500°C or higher and 2000°C or lower.
  • a step of forming a first mask 60 having a predetermined pattern is performed (step S7 in FIG. 20).
  • the first mask 60 is preferably an organic mask (resist mask).
  • the first mask 60 is disposed on the upper end of the first layer 8 and has a plurality of first openings 61 exposing areas in the first layer 8 where a plurality of first inversion columns 14 are to be formed.
  • the multiple first openings 61 are formed at intervals in the first array direction Da1 over the entire surface of the upper end of the first layer 8, and are each partitioned into stripes extending in the first extension direction De1.
  • the multiple first openings 61 cross the multiple device regions 55 and the multiple lines to be cut 56 in the first extension direction De1, exposing the multiple device regions 55 and the multiple lines to be cut 56 in a stripe pattern.
  • the multiple first openings 61 expose both the portion of the upper end of the first layer 8 that is located within the active region 10 and the portion that is located within the peripheral region 11 in each device region 55.
  • the implantation angle of the pentavalent element into the first layer 8 is controlled, and the pentavalent element is introduced into the first layer 8 along the first axial channel CH1 (the c-axis of the SiC single crystal in this embodiment) with a predetermined implantation energy (see also Figures 6A to 6E).
  • a predetermined implantation energy see also Figures 6A to 6E.
  • the wafer 50 may be supported horizontally and the pentavalent element may be introduced into the first layer 8 along the first axial channel CH1.
  • the wafer 50 may be supported tilted by the off angle ⁇ off from the horizontal and the pentavalent element may be introduced into the first layer 8 along the first axial channel CH1.
  • a plurality of first inversion columns 14 having a predetermined thickness are formed at a predetermined depth (see also Figures 6A to 6E).
  • the implantation energy of the pentavalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection energy for the first inversion column 14 may be approximately equal to the injection energy for the first impurity region 12, or may be different from the injection energy for the first impurity region 12.
  • the injection energy for the first inversion column 14 may be equal to or greater than the injection energy for the first impurity region 12.
  • the injection energy for the first inversion column 14 may also be less than the injection energy for the first impurity region 12.
  • the injection temperature of the pentavalent element may be adjusted in the range of 0°C to 1500°C.
  • the injection temperature may have a value that belongs to any one of the following ranges: 0°C to 25°C, 25°C to 50°C, 50°C to 100°C, 100°C to 250°C, 250°C to 500°C, 500°C to 750°C, 750°C to 1000°C, 1000°C to 1250°C, and 1250°C to 1500°C.
  • the injection temperature for the first inversion column 14 may be approximately equal to the injection temperature for the first impurity region 12, or may be different from the injection temperature for the first impurity region 12.
  • the injection temperature for the first inversion column 14 may be equal to or higher than the injection temperature for the first impurity region 12.
  • the injection temperature for the first inversion column 14 may also be lower than the injection temperature for the first impurity region 12.
  • first extension direction De1 is a direction other than the a-axis direction and the m-axis direction (see also Figures 12A to 12C, etc.), there is no need to strictly control the alignment misalignment of the multiple first inversion columns 14 with respect to the crystal orientation of the SiC single crystal.
  • the pentavalent element may be electrically activated by an annealing method, and at the same time, lattice defects and the like that have occurred in the first layer 8 may be repaired.
  • the annealing temperature for the first layer 8 may be 500°C or higher and 2000°C or lower. This forms a plurality of first inversion columns 14 and a plurality of first non-inversion columns 15, and at the same time, a first superjunction structure SJ1 is formed.
  • the annealing method for the multiple first inversion columns 14 may also serve as the annealing method for the first impurity region 12 described above. In this case, the annealing method for the first impurity region 12 before the process of forming the first inversion columns 14 may be omitted.
  • a determination step is performed as to whether or not a thickness adjustment step for the first layer 8 is to be performed (step S9 in FIG. 20). If the thickness of the first layer 8 is to be adjusted (step S9 in FIG. 20: YES), the first layer 8 is thinned from the upper end side (step S10 in FIG. 20).
  • the multiple openings are formed at intervals in the first array direction Da1 over the entire surface of the upper end of the first layer 8, and are each partitioned into stripes extending in the first extension direction De1.
  • the multiple openings cross the multiple device regions 55 and the multiple lines to be cut 56 in the first extension direction De1, exposing the multiple device regions 55 and the multiple lines to be cut 56 in a striped pattern.
  • the multiple openings expose both the portion of the upper end of the first layer 8 that is located within the active region 10 and the portion that is located within the peripheral region 11 in each device region 55.
  • the multiple inverted intermediate columns 18 are arranged at intervals in the first arrangement direction Da1 across the entire area of the first layer 8, and are each formed to extend in a stripe shape in the first extension direction De1. In other words, the multiple inverted intermediate columns 18 are formed in a stripe shape so as to cross the multiple device regions 55 and the multiple cutting lines 56 in the first extension direction De1. After the process of forming the multiple inverted intermediate columns 18, the mask (not shown) is removed.
  • a process for forming the second impurity region 13 is performed (step S14 in FIG. 20).
  • the process for forming the second impurity region 13 includes a channeling injection process of a trivalent element (p-type impurity) into the second layer 9.
  • the trivalent element is introduced into the entire second layer 9.
  • the channeling injection process is performed based on the data (information) of the off angle ⁇ off described above.
  • the implantation energy of the trivalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection energy for the second impurity region 13 may be approximately equal to the injection energy for the first impurity region 12, or may be different from the injection energy for the first impurity region 12.
  • the injection energy for the second impurity region 13 may be equal to or greater than the injection energy for the first impurity region 12.
  • the injection energy for the second impurity region 13 may be less than the injection energy for the first impurity region 12.
  • the injection temperature of the trivalent element may be adjusted in the range of 0°C to 1500°C.
  • the injection temperature may have a value that belongs to any one of the following ranges: 0°C to 25°C, 25°C to 50°C, 50°C to 100°C, 100°C to 250°C, 250°C to 500°C, 500°C to 750°C, 750°C to 1000°C, 1000°C to 1250°C, and 1250°C to 1500°C.
  • the injection angle of the trivalent element is preferably set within a range of ⁇ 2° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the injection angle of the trivalent element is set within a range of ⁇ 1° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).
  • a trivalent element belonging to the heavy elements heavier than carbon is introduced into the second layer 9.
  • the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium).
  • the trivalent element is aluminum.
  • a process for forming a second mask 62 having a predetermined pattern is carried out (step S15 in FIG. 20).
  • the second mask 62 is preferably an organic mask (resist mask).
  • the second mask 62 is disposed on the upper end of the second layer 9 and has a plurality of second openings 63 exposing areas in the second layer 9 where a plurality of second inversion columns 16 are to be formed.
  • the second openings 63 are formed at intervals in a second arrangement direction Da2 different from the first arrangement direction Da1 over the entire surface of the upper end of the second layer 9, and are each partitioned into strips extending in a second extension direction De2 different from the first extension direction De1.
  • the second openings 63 cross the device regions 55 and the lines to be cut 56 in the second extension direction De2, exposing the device regions 55 and the lines to be cut 56 in a stripe pattern.
  • the second openings 63 expose both a portion of the upper end of the second layer 9 that is located within the active region 10 and a portion that is located within the peripheral region 11 in each device region 55.
  • a process for forming a plurality of second inversion columns 16 is carried out (step S16 in FIG. 20).
  • the process for forming a plurality of second inversion columns 16 includes a channeling injection process of a pentavalent element (n-type impurity) into the second layer 9.
  • the channeling injection process is carried out based on the data (information) of the off angle ⁇ off described above.
  • the injection angle of the pentavalent element into the second layer 9 is controlled, and the pentavalent element is introduced into the second layer 9 along the second axial channel CH2 (the c-axis of the SiC single crystal in this embodiment) with a predetermined injection energy (see also Figures 6A to 6E).
  • a predetermined injection energy see also Figures 6A to 6E.
  • the wafer 50 may be supported horizontally and the pentavalent element may be introduced into the second layer 9 along the second axial channel CH2.
  • the wafer 50 may be supported tilted by the off angle ⁇ off from the horizontal and the pentavalent element may be introduced into the second layer 9 along the second axial channel CH2.
  • a plurality of second inversion columns 16 having a predetermined thickness are formed at a predetermined depth (see also Figures 6A to 6E).
  • the implantation energy of the pentavalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection temperature for the second inversion column 16 may be approximately equal to the injection temperature for the second impurity region 13, or may be different from the injection temperature for the second impurity region 13.
  • the injection temperature for the second inversion column 16 may be equal to or higher than the injection temperature for the second impurity region 13.
  • the injection temperature for the second inversion column 16 may also be lower than the injection temperature for the second impurity region 13.
  • the pentavalent element is introduced along the second axial channel CH2, in which the atomic rows are relatively sparse in plan view.
  • the pentavalent element travels through the second axial channel CH2 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the second layer 9.
  • the pentavalent element is preferably arsenic or antimony.
  • the process error of the multiple second reversal columns 16 caused by the shadowing of the multiple second openings 63 is different from the process error of the multiple first reversal columns 14 caused by the shadowing of the multiple first openings 61. Therefore, it is preferable that the absolute value of the second extension angle ⁇ 2 is approximately equal to the absolute value of the first extension angle ⁇ 1. In this case, the process error of the multiple second reversal columns 16 is approximately the same as the process error of the multiple first reversal columns 14. Therefore, the accuracy of the charge balance is improved.
  • the SiC semiconductor device 1B includes an active surface 71, an outer surface 72, and first to fourth connecting surfaces 73A to 73D formed on the first main surface 3.
  • the active surface 71, the outer surface 72, and the first to fourth connecting surfaces 73A to 73D define an active plateau 74 on the first main surface 3.
  • the lower ends of the second non-inverted columns 17 are located in a region closer to the lower end of the second layer 9 than the depth position of the outer peripheral surface 72 in the thickness direction of the second layer 9.
  • the upper ends of the second non-inverted columns 17 are located in a region closer to the active surface 71 than the outer peripheral surface 72 in the thickness direction of the second layer 9.
  • FIG. 28 is a plan view showing a main portion of active region 10.
  • FIG. 29 is a cross-sectional perspective view showing gate structure 35 according to the first embodiment.
  • SiC semiconductor device 1B includes MIS structure 31 formed in active region 10. The following components are described as components of SiC semiconductor device 1B, but are also components of MIS structure 31.
  • Each gate structure 35 includes a trench 75, an insulating film 76, and a buried electrode 77.
  • the trench 75 is formed in the active surface 71 and defines the wall surface of the gate structure 35.
  • the insulating film 76 covers the wall surface of the trench 75.
  • the insulating film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 76 includes a silicon oxide film made of an oxide of the chip 2.
  • the buried electrode 77 is embedded in the trench 75 with the insulating film 76 in between, and faces the channel with the insulating film 76 in between.
  • the buried electrode 77 may include p-type or n-type conductive polysilicon.
  • the contact regions 34 are interposed between the adjacent source regions 33 and extend in a strip shape along the gate structures 35.
  • the contact regions 34 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the second non-inverted columns 17 across a portion of the body region 32 in the stacking direction.
  • Figure 30 is a perspective view showing the configuration of the outer peripheral region 11.
  • Figure 31A is a cross-sectional view in the first direction X showing a main part of the outer peripheral region 11.
  • Figure 31B is a cross-sectional view in the second direction Y showing a main part of the outer peripheral region 11.
  • the multiple first inversion columns 14 and the multiple second inversion columns 16 are omitted from the illustration.
  • the SiC semiconductor device 1B includes a p-type well region 78 formed in the surface layer portion of the outer peripheral surface 72.
  • the well region 78 is formed at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the outer peripheral surface 72 toward the active surface 71 in a plan view, and extends in a band shape along the active surface 71.
  • the well region 78 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 71 in a plan view.
  • the well region 78 is pulled out from the surface layer portion of the outer peripheral surface 72 toward the first to fourth connection surfaces 73A to 73D, and extends along the surface layers of the first to fourth connection surfaces 73A to 73D.
  • the well region 78 is electrically connected to the body region 32 at the surface portion of the active surface 71, and is electrically connected to the second non-inverted columns 17 at the first to fourth connection surfaces 73A to 73D.
  • the well region 78 is formed at a distance from the lower end of the second layer 9 toward the outer peripheral surface 72, and faces the first layer 8 with a portion of the second layer 9 in between.
  • the bottom of the well region 78 is located closer to the lower end of the second layer 9 than the bottom wall of the gate structure 35. It is preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the lower ends of the second non-inverted columns 17. It is particularly preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the middle portions of the thickness ranges of the second non-inverted columns 17.
  • the well region 78 is composed of a random impurity region introduced into the surface layer of the second layer 9 by a random implantation method for the second layer 9 (see also FIG. 7).
  • the well region 78 has a thickness in the direction along the second axial channel CH2 that is less than the second region thickness TR2 of the second inversion column 16.
  • the thickness of the well region 78 is less than the first region thickness TR1 of the first inversion column 14.
  • the SiC semiconductor device 1B includes at least one (preferably 2 to 20) p-type field region 38 formed in the surface layer of the outer peripheral surface 72 in the outer peripheral region 11.
  • the multiple field regions 38 are formed in the surface layer of the outer peripheral surface 72 in a manner similar to that of the SiC semiconductor device 1A.
  • the multiple field regions 38 intersect with multiple second inverted columns 16 and multiple second non-inverted columns 17 in the portion extending in the first extension direction De1 in a plan view, and intersect with multiple first inverted columns 14 and multiple first non-inverted columns 15 in the portion extending in the second extension direction De2.
  • the SiC semiconductor device 1B includes the aforementioned interlayer insulating film 40 that covers the first main surface 3.
  • the interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42.
  • the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D.
  • the first insulating film 41 is connected to the insulating film 76 on the active surface 71, exposing the buried electrode 77.
  • the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D, sandwiching the first insulating film 41 between them.
  • the second insulating film 42 covers the multiple gate structures 35 in the active region 10.
  • the second insulating film 42 covers the multiple field regions 38 and well regions 78 in the outer peripheral region 11, sandwiching the first insulating film 41 between them.
  • the second insulating film 42 is continuous with the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D).
  • the second insulating film 42 may be formed at a distance inward from the periphery of the outer peripheral surface 72, exposing the periphery of the first main surface 3 together with the first insulating film 41.
  • the SiC semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40.
  • the plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (buried electrodes 77), and a plurality of contact openings 43 that expose a plurality of source regions 33.
  • the plurality of contact openings 43 for the source regions 33 are formed in the regions between the plurality of adjacent gate structures 35, and expose the plurality of source regions 33 and the plurality of contact regions 34.
  • the gate pad 45 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view.
  • the gate pad 45 is disposed in a region close to the center of one side of the active surface 71 (the second connection surface 73B in this embodiment) in a plan view.
  • the gate pad 45 may also be disposed at a corner of the active surface 71 or in the center of the active surface 71 in a plan view.
  • FIG. 32 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment.
  • the multiple gate structures 35 according to the first embodiment described above were arranged shifted from the multiple second non-inverting columns 17 toward the multiple second inverting columns 16.
  • the multiple gate structures 35 according to the second embodiment are arranged so as to overlap the multiple second non-inverting columns 17 in the stacking direction.
  • the multiple gate structures 35 overlap the multiple second non-inverting columns 17 in a one-to-one correspondence in the stacking direction.
  • FIG. 33 is a cross-sectional perspective view showing a gate structure 35 according to a third embodiment.
  • the multiple gate structures 35 according to the third embodiment each have a layout that does not require consideration of misalignment with respect to the multiple second inverting columns 16 and the multiple second non-inverting columns 17.
  • the multiple gate structures 35 extend in a direction other than the second extension direction De2 so as to intersect with the multiple second inversion columns 16 and the multiple second non-inversion columns 17.
  • the multiple gate structures 35 are arranged at intervals in the first arrangement direction Da1 of the first inversion column 14, and extend in the first extension direction De1 of the first inversion column 14.
  • the first arrangement direction Da1 is the a-axis direction (first direction X)
  • the first extension direction De1 is the m-axis direction (second direction Y).
  • each gate structure 35 may face multiple first non-inverted columns 15 in the stacking direction.
  • the multiple gate structures 35 may be arranged offset from the multiple first inverted columns 14 in the first array direction Da1 and face either one or both of the first inverted columns 14 and the first non-inverted columns 15 in the stacking direction.
  • the angle (absolute value) between the extension direction of the gate structure 35 and the second extension direction De2 may be greater than 0° and less than 90°.
  • the angle (absolute value) of the gate structure 35 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the angle (absolute value) of the gate structure 35 may be set to a value belonging to any one of the ranges of 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • the buried electrode 77 faces the second inversion columns 16 and the second non-inversion columns 17 in the stacking direction and the horizontal direction, sandwiching the insulating film 76 between them.
  • the aforementioned source regions 33 and contact regions 34 face the second inversion columns 16 and the second non-inversion columns 17 in the stacking direction, sandwiching a portion of the body region 32 between them.
  • FIG. 34 is a cross-sectional perspective view showing a gate structure 35 according to the fourth embodiment.
  • the multiple gate structures 35 according to the fourth embodiment each have a configuration that contributes to narrowing the pitch.
  • the multiple gate structures 35 according to the fourth embodiment are particularly effective in realizing a narrower pitch for the multiple second inverted columns 16 and the multiple second non-inverted columns 17.
  • FIG. 34 shows an example in which the gate structure 35 according to the first embodiment described above is replaced with the gate structure 35 according to the fourth embodiment, but the configuration of the gate structure 35 according to the fourth embodiment is also applicable to the configurations of the gate structures 35 according to the second and third embodiments.
  • the multiple gate structures 35 each include a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80.
  • the trench 75 has a form similar to that of the first embodiment.
  • the insulating film 76 is formed at a distance from the first main surface 3 (active surface 71) to the bottom wall side of the trench 75, exposing a surface portion of the first main surface 3 (active surface 71) at the opening end of the trench 75. It is preferable that the upper end of the insulating film 76 is located on the first main surface 3 side relative to the intermediate depth range of the trench 75.
  • the buried electrode 77 is buried in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the bottom wall of the trench 75, and defines an open recess that is recessed toward the bottom wall of the trench 75 at the opening end of the trench 75.
  • the buried electrode 77 exposes the surface portion of the first main surface 3 (active surface 71) and the upper end of the insulating film 76 at the opening end of the trench 75. It is preferable that the upper end of the buried electrode 77 is located on the first main surface 3 side relative to the intermediate portion of the depth range of the trench 75.
  • the buried insulator 80 is buried in the trench 75 (open recess) so as to expose the first principal surface 3 (active surface 71), and covers the insulating film 76 and buried electrode 77 within the trench 75.
  • the buried insulator 80 is buried in the trench 75 at a distance from the first principal surface 3 (active surface 71) toward the buried electrode 77, and exposes the surface portion of the first principal surface 3 (active surface 71) at the open end of the trench 75.
  • the upper end of the buried insulator 80 is preferably located on the first main surface 3 side relative to the intermediate portion of the depth range of the trench 75.
  • the buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the buried insulator 80 preferably includes a silicon oxide film.
  • the multiple source regions 33 described above are each formed in a region between multiple adjacent gate structures 35 in the surface layer portion of the first main surface 3 (active surface 71).
  • the multiple source regions 33 are arranged at intervals along the multiple gate structures 35 so as to be connected to the multiple gate structures 35 located on both sides.
  • the multiple source regions 33 arranged along one sidewall of the gate structure 35 face the multiple source regions 33 arranged along the other sidewall of the gate structure 35 in a one-to-one correspondence.
  • the multiple source regions 33 are arranged in a matrix in a plan view.
  • the multiple source regions 33 on one side may face the regions between the multiple source regions 33 on the other side in a one-to-one correspondence.
  • the multiple source regions 33 may be arranged in a staggered pattern in a planar view.
  • the multiple source regions 33 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 between them.
  • the aforementioned contact regions 34 are formed in the regions between adjacent gate structures 35 on the surface layer of the first main surface 3 (active surface 71).
  • the contact regions 34 are arranged at intervals along the gate structures 35 so as to be connected to the gate structures 35 located on both sides.
  • the multiple contact regions 34 are arranged alternately with the multiple source regions 33 along the multiple gate structures 35. More specifically, the multiple contact regions 34 arranged along one sidewall of the gate structure 35 face the multiple contact regions 34 arranged along the other sidewall of the gate structure 35 in a one-to-one correspondence.
  • the multiple source regions 33 are also arranged in a matrix in a planar view.
  • the multiple contact regions 34 on one side may face the regions between the multiple source regions 33 on the other side (i.e., the multiple source regions 33) in a one-to-one correspondence.
  • the multiple contact regions 34 may be arranged in a staggered pattern in a planar view.
  • the multiple contact regions 34 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 between them.
  • the aforementioned interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42.
  • the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D.
  • the first insulating film 41 covers the peripheral portion of the active surface 71 and exposes the multiple gate structures 35 collectively in the inner portion of the active surface 71. Specifically, the first insulating film 41 is connected to the insulating film 76 at both ends of the multiple gate structures 35, exposing the buried electrodes 77. The first insulating film 41 also covers the outer peripheral surface 72 and the first to fourth connection surfaces 73A to 73D in the same manner as in the first embodiment.
  • the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D across the first insulating film 41.
  • the second insulating film 42 covers the peripheral portion of the active surface 71, exposing the multiple gate structures 35 collectively at the inner portion of the active surface 71.
  • the second insulating film 42 penetrates into the trench 75 from above the first main surface 3 (active surface 71) at both ends of the multiple gate structures 35, and is connected to the buried insulator 80 within the trench 75.
  • the interlayer insulating film 40 includes a plurality of contact openings 43 (not shown) that expose both ends (buried electrodes 77) of the plurality of gate structures 35, and a single contact opening 43 that collectively exposes the inner portions (buried insulator 80) of the plurality of gate structures 35, the plurality of source regions 33, and the plurality of contact regions 34.
  • the aforementioned gate pad 45, the aforementioned multiple gate wirings 46, and the aforementioned drain pad 48 have the same configuration as in the first embodiment.
  • the aforementioned source pad 47 penetrates into the single contact opening 43 from above the interlayer insulating film 40, and collectively covers the inner parts (buried insulator 80) of the multiple gate structures 35, the multiple source regions 33, and the multiple contact regions 34 within the single contact opening 43.
  • the source pad 47 is electrically insulated from the multiple gate structures 35 (buried electrodes 77) by the buried insulator 80, and is electrically connected to the multiple source regions 33 and multiple contact regions 34 at the first main surface 3 (active surface 71).
  • the source pad 47 has a buried portion buried in the trench 75. The buried portion of the source pad 47 faces the buried electrode 77 within the trench 75 with the buried insulator 80 in between, and is electrically connected to the multiple source regions 33 and multiple contact regions 34 at the opening end of the trench 75.
  • FIG. 35 is a cross-sectional perspective view showing a gate structure 35 according to the fifth embodiment.
  • the gate structures 35 according to the fifth embodiment each have a configuration that is a modification of the gate structures 35 according to the fourth embodiment.
  • the configuration of the gate structure 35 according to the fifth embodiment is also applicable to the configurations of the gate structures 35 according to the first to third embodiments.
  • the multiple gate structures 35 each include a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80.
  • the trench 75 has a similar configuration to that of the first embodiment.
  • the insulating film 76 includes an upper insulating film 81 and a lower insulating film 82.
  • the upper insulating film 81 is formed as an insulating film for channel control, and covers the wall surface on the opening side of the trench 75 relative to the bottom of the body region 32.
  • the upper insulating film 81 has a portion that crosses the boundary between the second inversion column 16 and the body region 32 and covers the second inversion column 16. In this case, it is preferable that the coverage area of the upper insulating film 81 relative to the body region 32 is larger than the coverage area of the upper insulating film 81 relative to the second inversion column 16.
  • the upper insulating film 81 may include a silicon oxide film. It is preferable that the upper insulating film 81 includes a silicon oxide film made of an oxide of the chip 2.
  • the upper insulating film 81 may have a thickness of 1 nm or more and 100 nm or less. The thickness of the upper insulating film 81 may have a value that belongs to any one of the following ranges: 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the lower insulating film 82 covers the wall surface on the bottom wall side of the trench 75 relative to the bottom of the body region 32.
  • the lower insulating film 82 covers the second inversion column 16.
  • the coverage area of the lower insulating film 82 relative to the second inversion column 16 is larger than the coverage area of the upper insulating film 81 relative to the body region 32.
  • the lower insulating film 82 may include a silicon oxide film.
  • the lower insulating film 82 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.
  • the lower insulating film 82 has a thickness greater than that of the upper insulating film 81.
  • the thickness of the lower insulating film 82 is preferably 10 to 50 times the thickness of the upper insulating film 81.
  • the buried electrode 77 has a multi-electrode structure (double electrode structure) including an upper electrode 83, a lower electrode 84, and an intermediate insulating film 85.
  • the upper electrode 83 is buried in the opening side of the trench 75 with an insulating film 76 in between.
  • the upper electrode 83 is buried in the opening side of the trench 75 with an upper insulating film 81 in between, and faces the body region 32 with the upper insulating film 81 in between.
  • the upper electrode 83 is applied with a gate potential as a control potential.
  • the upper electrode 83 controls the inversion and non-inversion of the channel in the body region 32 in response to the gate potential.
  • the upper electrode 83 may include p-type or n-type conductive polysilicon.
  • the lower electrode 84 is embedded in the bottom wall side of the trench 75 with the insulating film 76 in between. Specifically, the lower electrode 84 is embedded in the bottom wall side of the trench 75 with the lower insulating film 82 in between, and faces the second inversion column 16 with the lower insulating film 82 in between. In other words, the lower electrode 84 is embedded in the bottom wall side of the trench 75 with respect to the bottom of the body region 32. Although specific illustration is omitted, the lower electrode 84 is drawn out to the opening side of the trench 75 in part of the trench 75 (both ends in this embodiment).
  • the facing area of the lower electrode 84 with respect to the second inversion column 16 is larger than the facing area of the upper electrode 83 with respect to the body region 32.
  • the lower electrode 84 extends in a wall shape along the depth direction of the trench 75.
  • the lower electrode 84 has an upper end that protrudes from the lower insulating film 82 toward the upper electrode 83, and is engaged with the lower end of the upper electrode 83.
  • the upper end of the lower electrode 84 faces the upper insulating film 81 (body region 32) horizontally, sandwiching the lower end of the upper electrode 83 therebetween.
  • the lower electrode 84 may be applied with a gate potential or a source potential.
  • a gate potential When a gate potential is applied to the lower electrode 84, the lower electrode 84 has the same potential as the upper electrode 83. Therefore, the voltage drop between the upper electrode 83 and the lower electrode 84 is suppressed. This suppresses electric field concentration on the gate structure 35.
  • the lower electrode 84 when a source potential is applied to the lower electrode 84, the lower electrode 84 can function as a field electrode. Therefore, the parasitic capacitance between the lower electrode 84 (field electrode) and the second layer 9 is reduced. This suppresses the decrease in switching speed caused by the parasitic capacitance.
  • the lower electrode 84 may include p-type or n-type conductive polysilicon.
  • the buried insulator 80 is buried in the trench 75 (open recess) so as to expose the first principal surface 3 (active surface 71), and covers the upper insulating film 81 and the upper electrode 83 within the recess.
  • the buried insulator 80 is buried in the trench 75 at a distance from the first principal surface 3 (active surface 71) toward the upper electrode 83, and exposes the surface portion of the first principal surface 3 (active surface 71) at the open end of the trench 75.
  • the aforementioned multiple source regions 33 have portions exposed from the sidewall of trench 75 at the opening end of trench 75, and face upper electrode 83 and buried insulator 80 across upper insulating film 81.
  • the aforementioned multiple contact regions 34 have portions exposed from the sidewall of trench 75 at the opening end of trench 75, and face upper electrode 83 and buried insulator 80 across upper insulating film 81.
  • FIG. 36 is a plan view showing a SiC semiconductor device 1C relating to the third embodiment.
  • FIG. 37A is a cross-sectional view taken along line XXXVIIA-XXXVIIA shown in FIG. 36.
  • FIG. 37B is a cross-sectional view taken along line XXXVIIB-XXXVIIB shown in FIG. 36.
  • FIG. 38A is a plan view showing an example layout of chip 2 (first layer 8).
  • FIG. 38B is a plan view showing an example layout of chip 2 (second layer 9).
  • FIG. 39 is a perspective view showing an example layout of chip 2.
  • FIG. 40 is a perspective view showing the configuration of peripheral region 11. In FIG. 40, is omitted from the illustration.
  • the second inversion columns 96 are extended from the active region 10 to the outer circumferential region 11 (see FIG. 3B). That is, the second inversion columns 96 are extended from a portion of the second layer 9 located in the active region 10 to a portion of the second layer 9 located in the outer circumferential region 11.
  • the second inversion columns 96 are also arranged at intervals in the second array direction Da2 in the outer circumferential region 11, and are each formed in a band shape extending in the second extension direction De2. That is, the second inversion columns 96 intersect with the first inversion columns 14 and the first non-inversion columns 15 in the outer circumferential region 11 as well.
  • the distance between the upper end of the second layer 9 and the upper end of the second inversion column 96 may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the upper end of the second layer 9 and the upper end of the second inversion column 96 may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the lower end of the first inverted column 98 may be formed at a distance from the lower end of the first layer 8 toward the upper end, and may face the base layer 6 across a portion (lower end) of the first layer 8.
  • the lower end of the first inverted column 98 may be approximately coincident with the lower end of the first layer 8 and connected to the base layer 6.

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Recrystallisation Techniques (AREA)
PCT/JP2023/046703 2022-12-28 2023-12-26 ＳｉＣ半導体装置 Ceased WO2024143382A1 (ja)

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CN202380088390.XA CN120419307A (zh) 2022-12-28 2023-12-26 SiC半导体装置
DE112023004893.2T DE112023004893T5 (de) 2022-12-28 2023-12-26 Sic-halbleiterbauelement
US19/243,722 US20250318213A1 (en) 2022-12-28 2025-06-20 Sic semiconductor device

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020047623A (ja) * 2018-09-14 2020-03-26 株式会社東芝 半導体装置
JP2020191327A (ja) * 2019-05-20 2020-11-26 株式会社豊田中央研究所 半導体装置とその製造方法
JP2021089916A (ja) * 2019-12-02 2021-06-10 富士電機株式会社 炭化珪素半導体装置の製造方法、炭化珪素基板の製造方法および炭化珪素基板
JP2022093100A (ja) * 2020-12-11 2022-06-23 株式会社デンソー 炭化珪素半導体装置およびその製造方法
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020047623A (ja) * 2018-09-14 2020-03-26 株式会社東芝 半導体装置
JP2020191327A (ja) * 2019-05-20 2020-11-26 株式会社豊田中央研究所 半導体装置とその製造方法
JP2021089916A (ja) * 2019-12-02 2021-06-10 富士電機株式会社 炭化珪素半導体装置の製造方法、炭化珪素基板の製造方法および炭化珪素基板
JP2022093100A (ja) * 2020-12-11 2022-06-23 株式会社デンソー 炭化珪素半導体装置およびその製造方法
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

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