WO2024143381A1 - ＳｉＣ半導体装置 - Google Patents

ＳｉＣ半導体装置 Download PDF

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Publication number
WO2024143381A1
WO2024143381A1 PCT/JP2023/046702 JP2023046702W WO2024143381A1 WO 2024143381 A1 WO2024143381 A1 WO 2024143381A1 JP 2023046702 W JP2023046702 W JP 2023046702W WO 2024143381 A1 WO2024143381 A1 WO 2024143381A1
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Prior art keywords
region
regions
column
less
semiconductor layer
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to DE112023004896.7T priority Critical patent/DE112023004896T5/de
Priority to JP2024567872A priority patent/JPWO2024143381A1/ja
Priority to CN202380088377.4A priority patent/CN120419306A/zh
Publication of WO2024143381A1 publication Critical patent/WO2024143381A1/ja
Priority to US19/243,740 priority patent/US20250318183A1/en
Anticipated expiration legal-status Critical
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Definitions

  • Patent document 1 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.
  • the present disclosure provides a novel SiC semiconductor device.
  • the present disclosure provides a SiC semiconductor device including a SiC layer including a main surface, a trench structure formed on the main surface and extending in a first extension direction in a planar view, and a planar electrode type gate structure disposed on the main surface and extending in a second extension direction other than the first extension direction in a planar view.
  • the present disclosure provides a SiC semiconductor device including a first conductivity type SiC layer including a main surface and having an axial channel along the stacking direction, a trench structure formed on the main surface and dividing a bottom of the SiC layer from a lower region, a column region of a second conductivity type formed in the lower region and extending along the axial channel, and a planar electrode type gate structure disposed on the main surface and overlapping the trench structure and the column region in the stacking direction.
  • FIG. 20A is a cross-sectional perspective view showing an example of a manufacturing method for a SiC semiconductor device.
  • FIG. 20B is a cross-sectional perspective view showing a step subsequent to that of FIG. 20A.
  • FIG. 20C is a cross-sectional perspective view showing a step subsequent to FIG. 20B.
  • FIG. 20D is a cross-sectional perspective view showing a step subsequent to FIG. 20C.
  • FIG. 20E is a cross-sectional perspective view showing a step subsequent to FIG. 20D.
  • FIG. 20F is a cross-sectional perspective view showing a step subsequent to FIG. 20E.
  • FIG. 20A is a cross-sectional perspective view showing an example of a manufacturing method for a SiC semiconductor device.
  • FIG. 20B is a cross-sectional perspective view showing a step subsequent to that of FIG. 20A.
  • FIG. 20C is a cross-sectional perspective view showing a step subsequent to FIG. 20B.
  • FIG. 20D is
  • FIG. 20G is a cross-sectional perspective view showing a step subsequent to FIG. 20F.
  • FIG. 20H is a cross-sectional perspective view showing a step subsequent to FIG. 20G.
  • FIG. 20I is a cross-sectional perspective view showing a step subsequent to FIG. 20H.
  • FIG. 20J is a cross-sectional perspective view showing a step subsequent to FIG. 20I.
  • FIG. 20K is a cross-sectional perspective view showing a step subsequent to FIG. 20J.
  • FIG. 20L is a cross-sectional perspective view showing a step subsequent to FIG. 20K.
  • FIG. 20M is a cross-sectional perspective view showing a step subsequent to FIG. 20L.
  • FIG. 20N is a cross-sectional perspective view showing a step subsequent to FIG. 20M.
  • FIG. 20N is a cross-sectional perspective view showing a step subsequent to FIG. 20M.
  • FIG. 23 is a cross-sectional perspective view showing a SiC semiconductor device according to a first modification.
  • FIG. 24 is a cross-sectional perspective view showing a SiC semiconductor device according to a second modification.
  • FIG. 25 is a cross-sectional perspective view showing a SiC semiconductor device according to a third modification.
  • FIG. 26 is a cross-sectional perspective view showing a SiC semiconductor device according to a fourth modification.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • FIG. 1 is a plan view showing a SiC semiconductor device 1 according to a specific embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a plan view showing an example layout of a chip 2.
  • FIG. 4 is a perspective view showing an example layout of a chip 2.
  • FIG. 5 is a plan view showing an active region 8.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the base layer 6 has a first axis channel C1 along the stacking direction.
  • the first axis channel C1 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the base layer 6, and is surrounded by atomic rows that form a crystal axis that extends in the stacking direction (crystal growth direction).
  • the first axis channel C1 consists of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal.
  • the first axis channel C1 extends along the c-axis and has the off-direction Do and off-angle ⁇ o described above.
  • the first axis channel C1 is inclined from the vertical axis toward the off-direction Do by the off-angle ⁇ o.
  • the base layer 6 may have a peak n-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction.
  • the n-type impurity concentration of the base layer 6 is preferably adjusted by a single type of pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted by a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted by nitrogen.
  • the base layer 6 has a first thickness T1.
  • the first thickness T1 may be 5 ⁇ m or more and 300 ⁇ m or less.
  • the first thickness T1 may have a value belonging to any one of the following ranges: 5 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 250 ⁇ m or less, and 250 ⁇ m or more and 300 ⁇ m or less.
  • the first thickness T1 is preferably 50 ⁇ m or more and 250 ⁇ m or less.
  • the chip 2 includes a semiconductor layer 7 made of single crystal SiC that is stacked on the base layer 6.
  • the semiconductor layer 7 may also be called a "SiC layer,” “semiconductor region,” etc.
  • the semiconductor layer 7 extends in a layered manner in the horizontal direction and forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the base layer 6.
  • the semiconductor layer 7 has a lower end and an upper end.
  • the lower end of the semiconductor layer 7 is the starting point of crystal growth, and the upper end of the semiconductor layer 7 is the end point of crystal growth.
  • the lower end of the semiconductor layer 7 is also the bottom of the semiconductor layer 7. Since the semiconductor layer 7 is grown continuously from the base layer 6, the lower end of the semiconductor layer 7 coincides with the upper end of the base layer 6.
  • the boundary between the base layer 6 and the semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and/or determined from other configurations and elements.
  • the semiconductor layer 7 has an off-direction Do and an off-angle ⁇ o that are approximately the same as the off-direction Do and the off-angle ⁇ o of the base layer 6.
  • the semiconductor layer 7 has a second axis channel C2 along the stacking direction.
  • the second axis channel C2 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the semiconductor layer 7, and is surrounded by atomic rows along a crystal axis that extends in the stacking direction (crystal growth direction).
  • the second axis channel C2 is a region in which the atomic rows extend in the stacking direction and the atomic rows (atomic distance/atomic density) in the horizontal direction are sparse in a planar view. It is preferable that the second axis channel C2 is a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.
  • the second axis channel C2 consists of a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the second axis channel C2 extends along the c-axis and has an off-direction Do and an off-angle ⁇ o. In other words, the second axis channel C2 is inclined from the vertical axis toward the off-direction Do by the off-angle ⁇ o. Furthermore, the second axis channel C2 approximately coincides with the first axis channel C1.
  • the n-type impurity concentration of the semiconductor layer 7 is preferably adjusted with at least nitrogen.
  • the semiconductor layer 7 preferably contains nitrogen and a pentavalent element other than nitrogen.
  • the semiconductor layer 7 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.
  • the semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1.
  • the second thickness T2 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the second thickness T2 may have a value that belongs to any one of the following ranges: 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, and 8 ⁇ m or more and 10 ⁇ m or less.
  • the second thickness T2 is preferably 2 ⁇ m or more and 8 ⁇ m or less.
  • the active surface 10 is formed in the active region 8. That is, the active surface 10 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.
  • the active surface 10 has a flat surface extending in the first direction X and the second direction Y.
  • the active surface 10 is formed by a c-plane (Si-plane).
  • the active surface 10 is formed in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the outer peripheral surface 11 has an outer peripheral depth DO.
  • the outer peripheral depth DO may be 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the outer peripheral depth DO may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the outer peripheral depth DO is preferably 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the high concentration region 15 extends from the outer periphery region 9 towards the first to fourth side faces 5A to 5D and is exposed from the first to fourth side faces 5A to 5D.
  • the high concentration region 15 may be formed in the semiconductor layer 7 with a space inward from the first to fourth side faces 5A to 5D.
  • the peripheral portion of the high concentration region 15 may be located in the active region 8 or in the outer periphery region 9.
  • the dose of the pentavalent element is 1 ⁇ 10 13 cm ⁇ 2 .
  • the thickness of the semiconductor layer 7 is about 5 ⁇ m.
  • the concentration gradient when the high concentration region 15 is formed by implantation energy of 1500 KeV or more and 2500 KeV or less is shown by a dashed line.
  • the high concentration region 15 has a thickness of 2.1 ⁇ m or more and 2.4 ⁇ m or less, and has an upper end spaced from the first major surface 3 toward the lower end side of the semiconductor layer 7, and a lower end spaced from the lower end of the semiconductor layer 7 toward the upper end side.
  • the high concentration region 15 has a concentration gradient that gradually decreases from the upper end side toward the lower end side.
  • the thickness (depth) of the high concentration region 15 increases with increasing injection energy.
  • the depth position of the upper end of the high concentration region 15 relative to the first main surface 3 increases with increasing injection energy.
  • the thicknesses of the first gradually increasing portion 16, the first peak portion 17, the first gradual portion 18, and the first gradually decreasing portion 19 increase with increasing injection energy.
  • the first peak value P1 of the high concentration region 15 decreases with increasing injection energy. This is because the pentavalent element is introduced into deep regions with increasing injection energy, increasing the n-type impurity concentration in those deep regions.
  • the depth position of the upper end of the high concentration region 15 relative to the first main surface 3 decreases as the implantation energy decreases.
  • the thicknesses of the first gradually increasing portion 16, the first peak portion 17, the first gradual portion 18, and the first gradually decreasing portion 19 decrease as the implantation energy decreases.
  • the first peak value P1 of the high concentration region 15 increases as the implantation energy decreases. This is because the pentavalent element is captured in a shallower region as the implantation energy decreases.
  • the multiple trench structures 20 are formed at intervals from the bottom of the high concentration region 15 toward the first main surface 3 (active surface 10), and face a part (lower end) of the semiconductor layer 7 across a part (lower end) of the high concentration region 15.
  • the lower region 7a is formed by a part (lower end) of the semiconductor layer 7 and a part (lower end) of the high concentration region 15.
  • the trench pitch PT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench pitch PT may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the trench pitch PT is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • Each trench structure 20 includes a trench 21, an insulating film 22, and a buried electrode 23.
  • the trench 21 is formed in the active surface 10 and defines the walls (side walls and bottom wall) of the trench structure 20. It is preferable that the bottom wall of the trench 21 has a portion that extends flat.
  • the insulating film 22 covers the wall surface of the trench 21.
  • the insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 22 includes a silicon oxide film made of an oxide of the chip 2.
  • the buried electrode 23 is buried in the trench 21 and faces the semiconductor layer 7 across the insulating film 22. In this embodiment, the buried electrode 23 faces the high concentration region 15 across the insulating film 22.
  • the buried electrode 23 may contain p-type or n-type conductive polysilicon.
  • the SiC semiconductor device 1 includes a plurality of p-type column regions 24 formed at intervals in the horizontal direction in the semiconductor layer 7. Specifically, the plurality of column regions 24 are formed in the lower region 7a in the semiconductor layer 7. In other words, the plurality of column regions 24 are formed in the thickness range between the lower end of the semiconductor layer 7 and the bottom walls of the plurality of trench structures 20.
  • the multiple column regions 24 overlap the multiple trench structures 20 in the stacking direction. Specifically, the multiple column regions 24 overlap the multiple trench structures 20 in a one-to-one correspondence in the stacking direction.
  • the multiple column regions 24 are formed in the active region 8 at intervals inward from the periphery of the active surface 10 (first to fourth connection surfaces 12A to 12D).
  • both ends of the multiple column regions 24 may be located on the inner side of the active region 8 relative to both ends of the multiple trench structures 20. With respect to the second direction Y, both ends of the multiple column regions 24 may be located on the peripheral side of the active region 8 relative to both ends of the multiple trench structures 20.
  • the multiple column regions 24 have upper ends located on the bottom wall side of the trench structure 20 and lower ends located on the lower end side of the semiconductor layer 7.
  • the upper ends of the multiple column regions 24 are located in a region on the bottom wall side of the trench structure 20 relative to the intermediate part of the thickness range of the lower region 7a
  • the lower ends of the multiple column regions 24 are located in a region on the lower end side of the semiconductor layer 7 relative to the intermediate part of the thickness range of the lower region 7a.
  • the upper ends of the multiple column regions 24 face the multiple trench structures 20 with a portion of the high concentration region 15 in between.
  • the upper ends of the multiple column regions 24 are electrically connected to the high concentration region 15, which has a relatively high concentration.
  • the upper ends of the multiple column regions 24 may also be connected to the bottom walls of the multiple trench structures 20.
  • the lower ends of the multiple column regions 24 are pulled out across the bottom of the high concentration region 15 into the semiconductor layer 7.
  • the multiple column regions 24 include a portion located in the region between the bottom of the high concentration region 15 and the bottom walls of the multiple trench structures 20, and a portion located in the region between the lower end of the semiconductor layer 7 and the bottom of the high concentration region 15.
  • the lower ends of the multiple column regions 24 are electrically connected to the relatively low concentration semiconductor layer 7.
  • the cross-sectional area of the portions of the plurality of column regions 24 located within the high concentration region 15 is preferably larger than the cross-sectional area of the portions of the plurality of column regions 24 located within the semiconductor layer 7.
  • the cross-sectional area of the portions of the plurality of column regions 24 located within the high concentration region 15 may be smaller than the cross-sectional area of the portions of the plurality of column regions 24 located within the semiconductor layer 7.
  • the lower ends of the multiple column regions 24 are formed at intervals from the lower end of the semiconductor layer 7 toward the bottom side of the high concentration region 15, and face the base layer 6 across a part of the semiconductor layer 7.
  • the lower ends of the multiple column regions 24 may cross the boundary between the semiconductor layer 7 and the base layer 6 and be located within the base layer 6.
  • the lower ends of the multiple column regions 24 may cross the bottom of the high concentration region 15 within the base layer 6.
  • the bottom distance between the bottom end of the semiconductor layer 7 and the bottom ends of the plurality of column regions 24 may be 0 ⁇ m or more and 2 ⁇ m or less.
  • the bottom distance may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the lower ends of the multiple column regions 24 may be formed at intervals from the bottom of the high-concentration region 15 toward the bottom wall of the trench structure 20.
  • the multiple column regions 24 may be electrically connected to the high-concentration region 15 at both their upper and lower ends.
  • the multiple column regions 24 are made of p-type channeling regions that extend along the second axis channel C2 in a cross-sectional view.
  • the column regions 24 are impurity regions that are introduced parallel or nearly parallel to the region (second axis channel C2) surrounded by atomic rows along the low-index crystal axis in the semiconductor layer 7, and extend at an angle with respect to the first main surface 3.
  • the multiple column regions 24 therefore have an off direction Do and an off angle ⁇ o that are approximately the same as the off direction Do and off angle ⁇ o of the second axis channel C2. In other words, the multiple column regions 24 are inclined from the vertical axis toward the off direction Do by the off angle ⁇ o.
  • the multiple column regions 24 consist of a single region having a thickness (depth) that crosses the middle portion of the lower region 7a along the second axis channel C2.
  • the plurality of column regions 24 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of the column region 24 is preferably adjusted with at least one kind of trivalent element. It is particularly preferable that the p-type impurity concentration of the column region 24 is adjusted with a trivalent element belonging to the heavy elements heavier than carbon.
  • the column region 24 contains a trivalent element other than boron (at least one of aluminum, gallium, and indium).
  • the p-type impurity concentration of the column region 24 is adjusted by aluminum.
  • the multiple column regions 24 each have a column width WC in the first array direction Da1.
  • the column width WC may be approximately equal to the trench width WT.
  • the column width WC may be greater than the trench width WT.
  • the column width WC may be less than the trench width WT.
  • the column width WC may be less than the trench depth DT.
  • the column width WC may be greater than the trench depth DT.
  • the column width WC is preferably less than the second thickness T2 of the semiconductor layer 7.
  • the column width WC is preferably less than the thickness of the high concentration region 15.
  • the column width WC may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the column width WC may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the multiple column regions 24 each have a column thickness TC (region depth).
  • the column thickness TC is preferably less than the second thickness T2 of the semiconductor layer 7.
  • the column thickness TC is preferably less than the thickness of the high concentration region 15.
  • the column thickness TC is preferably greater than the trench width WT.
  • the column thickness TC is preferably equal to or greater than the trench depth DT. It is particularly preferable that the column thickness TC is greater than the trench depth DT. Of course, the column thickness TC may be less than the trench depth DT.
  • the column thickness TC may be 1 to 5 times the trench depth DT.
  • the ratio TC/DT of the column thickness TC to the trench depth DT may be in any one of the following ranges: 1 to 1.5, 1.5 to 2, 2 to 2.5, 2.5 to 3, 3 to 3.5, 3.5 to 4, 4 to 4.5, and 4.5 to 5.
  • the column thickness TC is preferably greater than the column width WC.
  • each of the column regions 24 preferably has an aspect ratio TC/WC that extends vertically in a columnar shape along the second axial channel C2.
  • the aspect ratio TC/WC is the ratio of the column thickness TC to the column width WC.
  • the column thickness TC is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the column thickness TC may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the column pitch PC may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the column pitch PC may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the column pitch PC is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • FIG. 14 is a graph showing an example of the p-type concentration gradient in the column region 24.
  • the vertical axis indicates the p-type impurity concentration in the column region 24, and the horizontal axis indicates the depth along the second axis channel C2 with the bottom wall of the trench structure 20 as the reference (zero point).
  • a region having a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more is defined as the column region 24, and is shown as a graph.
  • the values of the impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of the column region 24 based on the concentration gradient, and are not shown with the intention of uniquely limiting the configuration of the column region 24.
  • the impurity concentration, thickness, etc. are adjusted to various values depending on the implantation conditions of the trivalent element (dose amount, implantation temperature, implantation energy, etc.), etc.
  • Figure 14 is a graph showing the case where the column region 24 is formed by the channeling injection method.
  • Figure 14 shows the concentration gradient of the column region 24 when a predetermined trivalent element (here, aluminum) is introduced into the lower region 7a parallel or nearly parallel to the second axial channel C2 with an injection energy of 500 KeV or more and 800 KeV or less.
  • a predetermined trivalent element here, aluminum
  • the dose of the trivalent element is 1 ⁇ 10 13 cm ⁇ 2 .
  • the trench depth DT is about 1 ⁇ m, and the thickness of the lower region 7 a is about 4 ⁇ m.
  • the concentration gradient when the column region 24 is formed by implantation energy of 1500 KeV or more and 2500 KeV or less is shown by a dashed line.
  • the column region 24 has a thickness of 2.5 ⁇ m or more and 2.8 ⁇ m or less, and has an upper end spaced from the bottom wall of the trench structure 20 toward the lower end of the semiconductor layer 7, and a lower end spaced from the lower end of the semiconductor layer 7 toward the upper end.
  • the p-type impurity concentration of the column region 24 has a concentration gradient from the upper end side to the lower end side, including a second gradually increasing portion 25, a second peak portion 26, a second gradual portion 27, and a second gradually decreasing portion 28.
  • the second gradually increasing portion 25 is a portion that forms the upper end of the column region 24, and the p-type impurity concentration gradually increases from the upper end side to the lower end side at a relatively steep rate of increase up to the second peak portion 26.
  • the second gradually increasing portion 25 is located within the high concentration region 15 and is electrically connected to the high concentration region 15.
  • the second peak portion 26 is a portion having a second peak value P2 (maximum value) of the p-type impurity concentration.
  • the second peak portion 26 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend).
  • the second peak portion 26 is electrically connected to the high concentration region 15.
  • the second peak value P2 is located closer to the lower end of the semiconductor layer 7 than the first peak value P1 of the high concentration region 15.
  • the second gradual portion 27 is defined by a portion having a concentration drop rate of 50% or less in a thickness range of at least 0.5 ⁇ m.
  • the second gradual portion 27 has a thickness of 1 ⁇ m or more and 1.3 ⁇ m or less, and has a concentration drop rate of 50% or less in that thickness range.
  • the second gradual portion 27 is located in the high concentration region 15 and is electrically connected to the high concentration region 15.
  • the second gradual portion 27 may have a portion located in a thickness range between the lower end of the semiconductor layer 7 and the lower end of the high concentration region 15, and be electrically connected to the semiconductor layer 7.
  • the second slack portion 27 occupies a thickness range of 1/4 or more of the column region 24. Specifically, the proportion of the second slack portion 27 in the column region 24 is 1/3 or more. The proportion of the second slack portion 27 in the column region 24 is typically 1/2 or less (less than 1/2). Of course, the proportion of the second slack portion 27 in the column region 24 may be 1/2 or more.
  • the second tapered portion 28 is a portion that forms the lower end of the column region 24.
  • the second tapered portion 28 has a concentration decrease rate that is greater than the concentration decrease rate in the second gradual portion 27, and is a portion in which the p-type impurity concentration gradually decreases from the second gradual portion 27 toward the lower end.
  • the concentration decrease rate per unit thickness of the second tapered portion 28 is greater than the concentration decrease rate per unit thickness of the second gradual portion 27.
  • the second tapered portion 28 is located in a thickness range between the lower end of the semiconductor layer 7 and the lower end of the high concentration region 15, and is electrically connected to the semiconductor layer 7.
  • the thickness (depth) of the column region 24 increases with increasing injection energy.
  • the depth position of the upper end of the column region 24 relative to the bottom wall of the trench structure 20 increases with increasing injection energy.
  • the thicknesses of the second increasing portion 25, the second peak portion 26, the second gradual portion 27, and the second decreasing portion 28 increase with increasing injection energy.
  • the second peak value P2 of the column region 24 decreases with increasing injection energy. This is because the trivalent element is introduced into the deep region with increasing injection energy, increasing the p-type impurity concentration in the deep region.
  • the depth position of the upper end of the column region 24 relative to the bottom wall of the trench structure 20 decreases as the implantation energy decreases.
  • the thicknesses of the second increasing portion 25, the second peak portion 26, the second gradual portion 27, and the second decreasing portion 28 decrease as the implantation energy decreases.
  • the second peak value P2 of the column region 24 increases as the implantation energy decreases. This is because the introduction of trivalent elements is inhibited in shallow regions as the implantation energy decreases.
  • a trivalent element is introduced into the semiconductor layer 7 instead of a pentavalent element, so it should be noted that even if the same process conditions as those for the high concentration region 15 are imposed, the concentration profile and thickness (depth) of the column region 24 are different from those of the high concentration region 15. Therefore, in order to achieve an appropriate charge balance, it is preferable to set the process conditions for the column region 24 and the process conditions for the high concentration region 15 separately.
  • the SiC semiconductor device 1 includes a plurality of n-type drift regions 29 formed in the semiconductor layer 7.
  • Each of the plurality of drift regions 29 is composed of an area partitioned by a plurality of column regions 24 in the semiconductor layer 7.
  • the plurality of drift regions 29 are arranged at intervals in the first array direction Da1 in the semiconductor layer 7, and are each formed in a strip shape extending in the first extension direction De1.
  • the multiple drift regions 29 are arranged at intervals in the m-axis direction (first direction X) and extend in the a-axis direction (second direction Y) of the SiC single crystal.
  • the multiple drift regions 29 are formed in stripes extending in the a-axis direction (second direction Y).
  • the extension direction of the multiple drift regions 29 coincides with the off-direction Do of the semiconductor layer 7.
  • the multiple drift regions 29 are formed by a part of the semiconductor layer 7 and a part of the high concentration region 15.
  • the part of the multiple drift regions 29 that includes the high concentration region 15 is made of an n-type channeling region that extends along the second axial channel C2.
  • the state of having charge balance means that, for adjacent column regions 24, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the drift regions 29.
  • n-type drift regions 29 semiconductor layer 7 whose concentration is adjusted by high concentration regions 15 form a charge balance with multiple p-type column regions 24 whose concentration is adjusted.
  • the multiple drift regions 29 form a superjunction structure with the multiple column regions 24 in the lower region 7a.
  • the SiC semiconductor device 1 includes a plurality of p-type body regions 30 formed in a surface layer portion of the first main surface 3 (active surface 10).
  • the plurality of body regions 30 are respectively formed in regions between a plurality of adjacent trench structures 20 in the surface layer portion of the first main surface 3 (active surface 10).
  • the plurality of body regions 30 are arranged at intervals along the first extension direction De1, and are connected to the plurality of trench structures 20 located on both sides.
  • the multiple body regions 30 arranged along one sidewall of the trench structure 20 face the multiple body regions 30 arranged along the other sidewall of the trench structure 20 in a one-to-one correspondence.
  • the multiple body regions 30 are arranged in a matrix with gaps in the first array direction Da1 and the first extension direction De1 in a plan view.
  • the outermost body regions 30 located on the peripheral side of the active surface 10 may be formed on the surface layer of the active surface 10 at intervals inward from the peripheral edge of the active surface 10 (the first to fourth connection surfaces 12A to 12D). It is preferable that the outermost body regions 30 are formed on the surface layer of the active surface 10 at intervals inward from both ends of the multiple trench structures 20. Of course, the outermost body regions 30 may be located closer to the peripheral side of the active surface 10 than both ends of the multiple trench structures 20. In this case, the outermost body regions 30 may be exposed from the first to fourth connection surfaces 12A to 12D.
  • the p-type impurity concentration of the body region 30 is preferably adjusted with at least one trivalent element.
  • the trivalent element of the body region 30 may be at least one of boron, aluminum, gallium, and indium.
  • the multiple surface drift regions 31 arranged along one sidewall of the trench structure 20 face the multiple surface drift regions 31 arranged along the other sidewall of the trench structure 20 in a one-to-one correspondence.
  • the multiple surface drift regions 31 are arranged in a matrix with gaps in the first array direction Da1 and the first extension direction De1 in a plan view.
  • the intermediate regions 32 are formed at intervals along the first extension direction De1 (second direction Y) directly below the corresponding trench structures 20. Specifically, the intermediate regions 32 are arranged at intervals in the first extension direction De1 (second direction Y) so as to be positioned on a virtual straight line connecting the body regions 30 in the first array direction Da1 (first direction X) in a plan view.
  • the multiple intermediate regions 32 on one side face the multiple intermediate regions 32 on the other side in a one-to-one correspondence in the first array direction Da1 (first direction X), sandwiching a part of the semiconductor layer 7 (a part of the high concentration region 15).
  • the multiple intermediate regions 32 on one side may also face the region between the multiple intermediate regions 32 on the other side in a one-to-one correspondence in the first array direction Da1.
  • the intermediate regions 32 are electrically connected to the body region 30 in the surface portion of the first principal surface 3 (active surface 10). In other words, the intermediate regions 32 electrically connect the column regions 24 to the body region 30. This prevents the column regions 24 from being electrically floating.
  • the intermediate regions 32 reduce the electric field for the trench structure 20.
  • the intermediate regions 32 do not necessarily need to form a charge balance with the drift regions 29.
  • the intermediate regions 32 may form a plurality of pn junctions having a charge balance with the drift regions 29.
  • the intermediate regions 32 are random regions introduced into the surface layers of the drift regions 29 by a random injection method into the semiconductor layer 7.
  • the intermediate regions 32 have a thickness less than the thickness of the column regions 24 in the direction along the second axial channel C2.
  • the intermediate regions 32 do not have a second slow portion 27 having a thickness of 0.5 ⁇ m or more in either direction along the second axial channel C2.
  • the multiple source regions 33 arranged along one sidewall of the trench structure 20 face the multiple source regions 33 arranged along the other sidewall of the trench structure 20 in a one-to-one correspondence.
  • the multiple source regions 33 are arranged in a matrix with gaps in the first array direction Da1 and the first extension direction De1 in a plan view.
  • the contact regions 34 are formed in the regions between the adjacent source regions 33 in the surface layer of the body regions 30.
  • the contact regions 34 are electrically connected to the intermediate regions 32 via the body regions 30. In other words, the contact regions 34 are electrically connected to the column regions 24 via the intermediate regions 32.
  • the multiple contact regions 34 are connected to the multiple trench structures 20 located on both sides.
  • the multiple contact regions 34 arranged along one sidewall of the trench structure 20 face the multiple contact regions 34 arranged along the other sidewall of the trench structure 20 in a one-to-one correspondence.
  • the multiple contact regions 34 are arranged in a matrix with gaps in the first array direction Da1 and the first extension direction De1 in a plan view.
  • the multiple contact regions 34 are preferably positioned on a virtual straight line connecting the multiple intermediate regions 32 in the first array direction Da1 (first direction X) in a plan view.
  • the multiple contact regions 34 may be connected to the intermediate regions 32 within the body region 30.
  • the multiple contact regions 34 may be offset from the multiple intermediate regions 32 in the first extension direction De1.
  • the multiple contact regions 34 may be connected to the multiple intermediate regions 32, or may be formed at a distance from the multiple intermediate regions 32.
  • the well region 35 is composed of a random region introduced into the surface layer of the semiconductor layer 7 by a random injection method into the semiconductor layer 7.
  • the well region 35 has a thickness less than the thickness of the high concentration region 15 in the direction along the second axial channel C2.
  • the thickness of the well region 35 is also less than the thickness of the column region 24.
  • the p-type impurity concentration of the well region 35 may be higher than the p-type impurity concentration of the body region 30. Of course, the p-type impurity concentration of the well region 35 may be lower than the body region 30. The p-type impurity concentration of the well region 35 may be approximately equal to the p-type impurity concentration of the intermediate region 32. Of course, the p-type impurity concentration of the well region 35 may be higher than the p-type impurity concentration of the intermediate region 32, or may be lower than the intermediate region 32.
  • the p-type impurity concentration of the well region 35 is preferably adjusted by at least one type of trivalent element.
  • the trivalent element of the well region 35 may be the same type as the trivalent element of the column region 24, or may be a different type from the trivalent element of the column region 24.
  • the trivalent element of the well region 35 may be at least one type of boron, aluminum, gallium, and indium.
  • the multiple field regions 36 are formed in a band shape extending along the active region 8 in a plan view.
  • the multiple field regions 36 each have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y.
  • the multiple field regions 36 are formed in a ring shape (specifically, a square ring shape) surrounding the active region 8 (i.e., the multiple column regions 24) in a plan view.
  • the multiple field regions 36 are formed in the semiconductor layer 7 at intervals from the lower end of the semiconductor layer 7 toward the outer circumferential surface 11, and form a pn junction with the semiconductor layer 7. It is preferable that the multiple field regions 36 have a bottom located on the outer circumferential surface 11 side relative to the intermediate part of the thickness range of the semiconductor layer 7. It is preferable that the multiple field regions 36 are formed at intervals from the bottom of the high concentration region 15 toward the outer circumferential surface 11, and form a pn junction with the high concentration region 15.
  • the field regions 36 are formed at intervals from the column regions 24 toward the periphery of the chip 2. Therefore, the field regions 36 do not face the column regions 24 in the stacking direction.
  • the field regions 36 are located closer to the bottom of the semiconductor layer 7 (high concentration region 15) than the bottom wall of the trench structure 20.
  • the bottoms of the field regions 36 may be located closer to the bottom of the semiconductor layer 7 (high concentration region 15) than the depth positions of the upper ends of the column regions 24.
  • the bottoms of the field regions 36 may be located closer to the bottom wall of the trench structure 20 than the depth positions of the upper ends of the column regions 24.
  • the multiple field regions 36 are made of random regions introduced into the surface layer of the semiconductor layer 7 by a random injection method into the semiconductor layer 7.
  • the multiple field regions 36 have a thickness less than the thickness of the high concentration region 15 in the direction along the second axial channel C2.
  • the thickness of the multiple field regions 36 is less than the thickness of the column region 24.
  • the field regions 36 do not have a gentle portion having a thickness of 0.5 ⁇ m or more.
  • the field regions 36 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of the field regions 36 may be approximately equal to the p-type impurity concentration of the body region 30.
  • the p-type impurity concentration of the field regions 36 may be higher than the p-type impurity concentration of the body region 30.
  • the p-type impurity concentration of the field regions 36 may be lower than the p-type impurity concentration of the body region 30.
  • the p-type impurity concentration of the multiple field regions 36 is preferably adjusted by at least one type of trivalent element.
  • the trivalent element of the field region 36 may be the same type as the trivalent element of the column region 24, or may be a different type from the trivalent element of the column region 24.
  • the trivalent element of the field region 36 may be at least one type of boron, aluminum, gallium, and indium.
  • the field regions 36 preferably have a width different from the column width WC of the column region 24.
  • the electric field relaxation effect of the field regions 36 is preferably adjusted separately from the column regions 24. It is particularly preferable that the width of the field regions 36 is greater than the column width WC.
  • the width of the field regions 36 may be smaller than the column width WC.
  • the width of the column region 24 may be approximately equal to the column width WC.
  • the multiple field regions 36 are preferably formed at a pitch different from the column pitch PC of the column region 24. It is particularly preferable that the pitch of the multiple field regions 36 is larger than the column pitch PC. The pitch of the multiple field regions 36 may be smaller than the column pitch PC. The pitch of the multiple field regions 36 may be approximately equal to the column pitch PC.
  • the SiC semiconductor device 1 includes multiple gate structures 37 of a planar electrode type arranged on the first main surface 3 (active surface 10).
  • the gate structures 37 may be referred to as "planar gate structures.”
  • a potential (second potential) different from the potential (first potential) applied to the trench structure 20 is applied to the multiple gate structures 37.
  • a gate potential is applied to the multiple gate structures 37 as a control potential.
  • the multiple gate structures 37 are spaced apart inward from the periphery (first to fourth connection surfaces 12A to 12D) of the active surface 10 in the active region 8.
  • the multiple gate structures 37 are arranged at intervals on the first main surface 3 so as to overlap with the multiple channels Ch in the stacking direction, and control the inversion and non-inversion of the multiple channels Ch in the body region 30 in response to the gate potential.
  • the multiple gate structures 37 intersect (specifically, perpendicular to) the multiple trench structures 20, the multiple column regions 24, and the multiple drift regions 29 in a plan view, and cover multiple channels Ch adjacent in the first array direction Da1 (second extension direction De2). Looking at one trench structure 20, the multiple gate structures 37 intersect one trench structure 20 at multiple points. The multiple gate structures 37 are electrically insulated from the multiple trench structures 20 at the intersections with the multiple trench structures 20.
  • the multiple gate structures 37 are arranged offset in the first extension direction De1 (second array direction Da2) from a virtual straight line connecting the multiple intermediate regions 32 in the first array direction Da1 (first direction X) in a planar view. Therefore, the multiple gate structures 37 are located in a region between the multiple intermediate regions 32 in a planar view. Of course, the multiple gate structures 37 may have a portion located on the virtual straight line connecting the multiple intermediate regions 32 in the first array direction Da1 (first direction X).
  • the gate structure 37 has a gate width WG in the second array direction Da2.
  • the gate width WG is preferably larger than the column width WC.
  • the gate width WG is preferably larger than the column pitch PC.
  • the gate width WG is preferably larger than the trench width WT.
  • the gate width WG is preferably larger than the trench pitch PT.
  • the gate width WG may be less than the column width WC.
  • the gate width WG may be less than the column pitch PC.
  • the gate width WG may be less than the trench width WT.
  • the gate width WG may be less than the trench pitch PT.
  • the gate pitch PG may be greater than the trench width WT.
  • the gate pitch PG may be less than the trench width WT.
  • the gate pitch PG may be less than the trench depth DT.
  • the gate pitch PG may be greater than the trench depth DT.
  • the gate pitch PG may be greater than the trench pitch PT.
  • the gate pitch PG may be less than the trench pitch PT.
  • the gate pitch PG is less than the first thickness T1.
  • the gate pitch PG may be less than the second thickness T2.
  • the gate pitch PG may be greater than the second thickness T2.
  • the gate pitch PG may be less than the thickness of the high concentration region 15.
  • the gate pitch PG may be greater than the thickness of the high concentration region 15.
  • Each gate structure 37 has a layered structure including a gate insulating film 38 and a gate electrode 39 layered in this order from the first main surface 3 side.
  • the gate insulating film 38 has a portion that covers the first main surface 3 in a film-like manner, and a portion that covers the multiple trench structures 20 in a film-like manner.
  • the gate insulating film 38 covers the wall surface (side wall), insulating film 22, and buried electrode 23 of the trench 21 in a film-like manner.
  • the first insulating film 42 covers the well region 35 and the multiple field regions 36 on the outer peripheral surface 11.
  • the first insulating film 42 is continuous with the first to fourth side surfaces 5A to 5D.
  • the first insulating film 42 may be formed at a distance inward from the periphery of the outer peripheral surface 11, exposing the semiconductor layer 7 from the periphery of the outer peripheral surface 11.
  • the first insulating film 42 covers the body region 30 and well region 35 on the first to fourth connection surfaces 12A to 12D.
  • the second insulating film 43 covers the multiple trench structures 20 (buried electrodes 23) and multiple gate structures 37 (gate electrodes 39) in the active region 8.
  • the second insulating film 43 covers the well region 35 and multiple field regions 36 in the peripheral region 9, sandwiching the first insulating film 42 between them.
  • the second insulating film 43 is continuous with the first to fourth side surfaces 5A to 5D.
  • the second insulating film 43 may be formed at a distance inward from the periphery of the peripheral surface 11, exposing the peripheral portion of the first main surface 3 together with the first insulating film 42.
  • the SiC semiconductor device 1 includes a plurality of contact openings 44 formed in the interlayer insulating film 41.
  • the plurality of contact openings 44 includes a plurality of contact openings 44 (not shown) that expose a plurality of gate structures 37 (gate electrodes 39), and a plurality of contact openings 44 that expose a plurality of trench structures 20 (buried electrodes 23) and a plurality of source regions 33.
  • the sidewall structure 45 is formed in a band shape extending along at least one of the first to fourth connection surfaces 12A to 12D.
  • the sidewall structure 45 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connection surfaces 12A to 12D so as to surround the active surface 10 in a plan view.
  • the gate pad 50 is disposed on a portion of the interlayer insulating film 41 that covers the active region 8. Specifically, the gate pad 50 is disposed on the active surface 10 at a distance from the outer peripheral surface 11 in a plan view. The gate pad 50 is disposed in a region close to the center of one side of the active surface 10 (the second connection surface 12B in this embodiment) in a plan view.
  • the gate pad 50 may be disposed in a region along any of the central portions of the first to fourth connection surfaces 12A to 12D.
  • the gate pad 50 may be disposed at any corner of the active surface 10 in a planar view.
  • the gate pad 50 may also be disposed at the central portion of the active surface 10 in a planar view.
  • the gate pad 50 is formed in a quadrangular shape in a planar view.
  • the second gate wiring 51B is pulled out from the gate pad 50 toward the third connection surface 12C and extends in a line along the periphery of the active surface 10 so as to intersect (specifically, perpendicular to) a portion (specifically, the other end) of the multiple gate structures 37.
  • the second gate wiring 51B penetrates the interlayer insulating film 41 via the multiple contact openings 44 and is electrically connected to the other end of the multiple gate structures 37 (gate electrodes 39).
  • the breakdown voltage that can be applied between the source pad 52 and the drain pad 53 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to any one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIG. 18 is a schematic diagram showing a wafer 60 used in the manufacture of a SiC semiconductor device 1.
  • the wafer 60 is a substrate for the base layer 6 and contains a SiC single crystal.
  • the wafer 60 is formed in a flat disk shape. Of course, the wafer 60 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 60 has a first wafer main surface 61 on one side, a second wafer main surface 62 on the other side, and a wafer side surface 63 connecting the first wafer main surface 61 and the second wafer main surface 62.
  • the first wafer main surface 61 corresponds to the upper end of the base layer 6, and the second wafer main surface 62 corresponds to the lower end of the base layer 6.
  • the first wafer main surface 61 and the second wafer main surface 62 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 61 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 62 is formed by the carbon surface of the SiC single crystal.
  • the wafer 60 (the first wafer main surface 61 and the second wafer main surface 62) has the off-direction Do and off-angle ⁇ o described above.
  • the wafer 60 has a mark 64 on the wafer side surface 63 that indicates the crystal orientation of the SiC single crystal.
  • the mark 64 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 61 in a plan view.
  • the mark 64 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction.
  • the mark 64 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.
  • FIG. 18 an orientation flat extending in the m-axis direction (first direction X) in a plan view is shown.
  • a plurality of device regions 65 and a plurality of cutting lines 66 are set on the wafer 60 by alignment marks or the like.
  • Each device region 65 is an area corresponding to a SiC semiconductor device 1.
  • Each of the plurality of device regions 65 is set to have a rectangular shape in a plan view.
  • the multiple device regions 65 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 65 are each set at intervals inward from the periphery of the first wafer main surface 61 in a plan view.
  • the multiple cutting lines 66 are set in a lattice extending along the first direction X and the second direction Y to partition the multiple device regions 65.
  • FIG. 19 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device 1.
  • FIGS. 20A to 20R are cross-sectional perspective views showing an example of a method for manufacturing a SiC semiconductor device 1.
  • FIGS. 21A to 21B are schematic diagrams for explaining the crystal orientation measurement process.
  • FIGS. 22A to 22B are schematic diagrams for explaining the ion implantation process.
  • FIGS. 20A to 20R show cross-sectional perspective views of a portion of an active region 8 of one device region 65.
  • the aforementioned wafer 60 preparation process is carried out (step S1 in FIG. 19).
  • the semiconductor layer 7 formation process is carried out (step S2 in FIG. 19).
  • the semiconductor layer 7 is formed starting from the first wafer main surface 61 (wafer 60) by epitaxial growth.
  • the crystal orientation of the semiconductor layer 7 includes a process for measuring the off angle ⁇ o of the semiconductor layer 7. In other words, this process includes a process for measuring the crystal orientation of the second axis channel C2 of the semiconductor layer 7.
  • the wafer 60 is cut from an ingot (SiC ingot), which is a crystalline mass, but there is a risk that an error will occur in the off-angle ⁇ o due to process error. If an error occurs in the off-angle ⁇ o of the wafer 60, a process error will also occur in the off-angle ⁇ o of the semiconductor layer 7, which will become an obstacle during the channeling injection process. Therefore, it is preferable that data (information) on the off-angle ⁇ o is obtained prior to the channeling injection process, and the channeling injection process is carried out based on the data (information) on the off-angle ⁇ o.
  • the crystal orientation of the semiconductor layer 7 is measured by an X-ray diffraction method (so-called ⁇ -2 ⁇ measurement method) using an X-ray diffraction device 67.
  • the X-ray diffraction device 67 may be referred to as an "XRD (X-ray Diffraction) device.”
  • the diffraction angle 2 ⁇ is fixed and the incident angle ⁇ is varied within a small angular range to measure a rocking curve that represents the intensity of the diffracted X-ray L2 (the intensity profile of the diffracted X-ray L2).
  • the rocking curve has the intensity of the diffracted X-ray L2 on the vertical axis and the incident angle ⁇ on the horizontal axis.
  • the incident angle ⁇ is determined as the angle position at which the intensity of the diffracted X-ray L2 reaches its peak value.
  • the fourth measurement point Po4 is set on the periphery of the semiconductor layer 7 at a distance from the first measurement point Po1 to the other side in the second direction Y (the side toward the mark 64).
  • the fifth measurement point Po5 is set on the periphery of the semiconductor layer 7 at a distance from the first measurement point Po1 to the other side in the first direction X (to the left of the mark 64).
  • the measurement results of the incident angle ⁇ , diffraction angle 2 ⁇ , and off angle ⁇ o at the first to fifth measurement points Po1 to Po5 are shown in the following Table 1.
  • the off angle ⁇ o is calculated using the incident angle ⁇ and diffraction angle 2 ⁇ by the formula " ⁇ -(2 ⁇ 1/2)".
  • the injection angle of the trivalent element is preferably set within a range of ⁇ 2° with respect to the axis along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the injection angle of the trivalent element is set within a range of ⁇ 1° with respect to the axis along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).
  • the base insulating film 75 serves as the base for the insulating film 22, the gate insulating film 38, and the first insulating film 42.
  • the base insulating film 75 may be formed by either or both of a CVD (Chemical Vapor Deposition) method and an oxidation treatment method.
  • a process for forming the drain pad 53 is carried out (step S23 in FIG. 19).
  • the drain pad 53 is formed by depositing a metal film on the second wafer main surface 62 by a sputtering method.
  • the wafer 60 is then cut along a number of planned cutting lines 66 (step S24 in FIG. 19).
  • a number of SiC semiconductor devices 1 are manufactured from one wafer 60.
  • FIG. 23 is a cross-sectional perspective view showing SiC semiconductor device 1 according to a first modified example.
  • the first arrangement direction Da1 of the multiple trench structures 20 is the m-axis direction (first direction X)
  • the first extension direction De1 of the multiple trench structures 20 is the a-axis direction (second direction Y).
  • the aforementioned gate pad 50 (multiple gate wirings 51) is electrically connected to the multiple trench structures 20 and the multiple gate structures 37.
  • the multiple gate wirings 51 penetrate the interlayer insulating film 41 via the multiple contact openings 44, and are connected to either or both of the multiple buried electrodes 23 and the multiple gate electrodes 39. This configuration is realized by adjusting the layout of the multiple contact openings 44.
  • a channel Ch is further formed along the sidewall of the trench structure 20 in the region of the body region 30 between the source region 33 and the drift region 29.

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
PCT/JP2023/046702 2022-12-28 2023-12-26 ＳｉＣ半導体装置 Ceased WO2024143381A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012142537A (ja) * 2010-12-16 2012-07-26 Mitsubishi Electric Corp 絶縁ゲート型バイポーラトランジスタとその製造方法
JP2019176077A (ja) * 2018-03-29 2019-10-10 ローム株式会社 半導体装置
US20210202724A1 (en) * 2019-12-30 2021-07-01 Mqsemi Ag Fortified trench planar mos power transistor
JP2021190711A (ja) * 2020-05-26 2021-12-13 ヒュンダイ・モービス・カンパニー・リミテッド パワー半導体素子およびその製造方法
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012142537A (ja) * 2010-12-16 2012-07-26 Mitsubishi Electric Corp 絶縁ゲート型バイポーラトランジスタとその製造方法
JP2019176077A (ja) * 2018-03-29 2019-10-10 ローム株式会社 半導体装置
US20210202724A1 (en) * 2019-12-30 2021-07-01 Mqsemi Ag Fortified trench planar mos power transistor
JP2021190711A (ja) * 2020-05-26 2021-12-13 ヒュンダイ・モービス・カンパニー・リミテッド パワー半導体素子およびその製造方法
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

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