WO2024142884A1 - 電子装置および電子装置の製造方法 - Google Patents

電子装置および電子装置の製造方法 Download PDF

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Publication number
WO2024142884A1
WO2024142884A1 PCT/JP2023/044243 JP2023044243W WO2024142884A1 WO 2024142884 A1 WO2024142884 A1 WO 2024142884A1 JP 2023044243 W JP2023044243 W JP 2023044243W WO 2024142884 A1 WO2024142884 A1 WO 2024142884A1
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Prior art keywords
layer
electronic device
wiring layer
bonding
manufacturing
Prior art date
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Ceased
Application number
PCT/JP2023/044243
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English (en)
French (fr)
Japanese (ja)
Inventor
寛之 新開
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
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Rohm Co Ltd
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Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2024567414A priority Critical patent/JPWO2024142884A1/ja
Publication of WO2024142884A1 publication Critical patent/WO2024142884A1/ja
Priority to US19/243,981 priority patent/US20250318053A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder
    • H05K3/3485—Application of solder paste, slurry or powder
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10522—Adjacent components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/1075—Shape details
    • H05K2201/10757—Bent leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers

Definitions

  • FIG. 8 is a partially enlarged cross-sectional view of a joint portion of an electronic component in the electronic device shown in FIG. 1, which is an enlarged portion of a part (the joint portion of the electronic component) of FIG.
  • FIG. 9 is an enlarged cross-sectional view of a bonding portion of an electronic component in the electronic device shown in FIG. 1 according to another embodiment.
  • FIG. 10 is a bottom view of a semiconductor element constituting the electronic device shown in FIG.
  • FIG. 11 is an enlarged cross-sectional view taken along line XI-XI of FIG.
  • FIG. 12 is a cross-sectional view showing a step of the method for manufacturing the electronic device according to the first embodiment.
  • FIG. 13 is a cross-sectional view showing a step of the method for manufacturing the electronic device according to the first embodiment.
  • an object A is formed on an object B
  • an object A is formed on (an object B)
  • an object A is formed directly on an object B
  • an object A is formed on an object B with another object interposed between the object A and the object B” unless otherwise specified.
  • an object A is disposed on an object B” and “an object A is disposed on (an object B)” include “an object A is disposed directly on an object B” and “an object A is disposed on (an object B) with another object interposed between the object A and the object B” unless otherwise specified.
  • an object A is located on (an object B) includes “an object A is in contact with an object B and is located on (an object B)” and “an object A is located on (an object B) with another object interposed between the object A and the object B".
  • an object A overlaps an object B includes “an object A overlaps the entire object B” and “an object A overlaps a part of an object B” unless otherwise specified.
  • FIGS. 1 to 11 show an electronic device A10 according to a first embodiment.
  • the electronic device A10 includes a semiconductor element 1, a plurality of electronic components 19, a support member 2, a wiring layer 30, a barrier metal 35, a plurality of bonding layers 41, a plurality of bonding layers 42, a plurality of terminals 5, and a sealing resin 6.
  • the semiconductor element 1 is a component that is the core of the electronic device A10's functions.
  • the semiconductor element 1 is, for example, an integrated circuit such as an LSI. Unlike this example, the semiconductor element 1 may be a voltage control element such as an LDO (Low Drop Out), an amplification element such as an operational amplifier, or a discrete element such as a transistor or a diode.
  • the semiconductor element 1 is rectangular in plan view.
  • the semiconductor element 1 is supported by a support member 2.
  • the semiconductor element 1 overlaps the support member 2 in plan view.
  • the semiconductor element 1 has an element principal surface 10a and an element rear surface 10b.
  • the element principal surface 10a and the element rear surface 10b are spaced apart in the thickness direction z.
  • the element principal surface 10a and the element rear surface 10b face in opposite directions to each other.
  • the element principal surface 10a faces the support member 2.
  • the support member 2 supports the semiconductor element 1 and the multiple electronic components 19.
  • the support member 2 includes, for example, a resin material.
  • the resin material is, for example, the same as the sealing resin 6, but may be different from the sealing resin 6.
  • the support member 2 may also include a filler such as silica mixed into the aforementioned resin material.
  • the support member 2 may include a single crystal intrinsic semiconductor (for example, silicon (Si)) instead of a resin material.
  • the support member 2 is rectangular in plan view.
  • the thickness (dimension along the thickness direction z) of the support member 2 is not limited in any way, but is, for example, 30 ⁇ m or more and 200 ⁇ m or less.
  • the support member 2 has a main surface 21, a back surface 22, and multiple side surfaces 23.
  • the main surface 21 and the back surface 22 are spaced apart in the thickness direction z.
  • the main surface 21 and the back surface 22 face in opposite directions.
  • the main surface 21 is the upper surface of the support member 2, and the back surface 22 is the lower surface of the support member 2.
  • the main surface 21 faces the semiconductor element 1 (element main surface 10a).
  • the back surface 22 faces the wiring board when the electronic device A10 is mounted on the wiring board.
  • the main surface 21 is covered with the sealing resin 6, and the back surface 22 is exposed from the sealing resin 6.
  • the wiring layer 30 is a conductor disposed inside the electronic device A10.
  • the wiring layer 30 contains, for example, Cu.
  • the wiring layer 30 is, for example, a laminate of a seed layer (containing, for example, titanium (Ti)) and a metal layer (containing, for example, Cu), but may be a single layer made of a conductor.
  • the wiring layer 30 contains a plurality of pattern wiring parts separated from each other.
  • the plurality of pattern wiring parts include those that are conductive to the semiconductor element 1, those that are conductive to any of the plurality of electronic components 19, and those that are not conductive to either the semiconductor element 1 or the plurality of electronic components 19.
  • the wiring layer 30 is formed on the main surface 21 and is in contact with the main surface 21.
  • the thickness (dimension along the thickness direction z) of the wiring layer 30 is 3 ⁇ m or more and 100 ⁇ m or less.
  • the wiring layer 30 includes an interposed portion 321 and an extending portion 322.
  • the interposed portion 321 is a portion of the wiring layer 30 that is interposed between the support member 2 and the electronic component 19 in the thickness direction z.
  • the extending portion 322 is connected to the interposed portion 321.
  • the extending portion 322 is a portion of the wiring layer 30 that is disposed outside the electronic component 19 in a plan view.
  • the plurality of barrier metals 35 are each formed on the wiring layer 30.
  • Each barrier metal 35 contains a metal different from that of the wiring layer 30.
  • Each barrier metal 35 contains nickel (Ni) as the metal.
  • Ni nickel
  • Each of the plurality of barrier metals 35 is smaller than the wiring layer 30 in a plan view. Therefore, as shown in FIG. 8 or FIG. 9, a step occurs between each barrier metal 35 and the wiring layer 30. In this embodiment, in a plan view, the wiring layer 30 protrudes outward from the barrier metal 35 more than the barrier metal 35.
  • the plurality of barrier metals 35 include one interposed between the bonding layer 41 and the wiring layer 30 and one interposed between the bonding layer 42 and the wiring layer 30. Note that the plurality of barrier metals 35 may not include one interposed between the bonding layer 41 and the wiring layer 30.
  • the thickness of each barrier metal 35 is 1 ⁇ m or more and 10 ⁇ m or less.
  • Each of the multiple bonding layers 41 bonds the wiring layer 30 to one of the multiple rewirings 14 of the semiconductor element 1.
  • the semiconductor element 1 is electrically connected to the wiring layer 30 via the multiple bonding layers 41.
  • Each of the multiple bonding layers 41 is a conductive bonding material.
  • the multiple bonding layers 41 are, for example, solder.
  • the solder contains an alloy (for example, an Sn-silver (Ag) alloy) that contains tin (Sn) in its composition, and contains flux. Note that the composition of each of the multiple bonding layers 41 is not limited to this example.
  • the thickness (dimension along the thickness direction z) of each bonding layer 41 is not limited in any way, but is, for example, 15 ⁇ m or more and 100 ⁇ m or less.
  • Each of the multiple bonding layers 42 includes an alloy layer stacked on the barrier metal 35.
  • the alloy layer includes Sn in its composition, and is, for example, a Sn-Ag alloy. Note that the composition of each of the multiple bonding layers 42 is not limited to this example.
  • Each bonding layer 42 is, for example, a solder.
  • Each bonding layer 42 may or may not contain flux.
  • the thickness (dimension along the thickness direction z) of each bonding layer 42 is not limited in any way, but is, for example, 1 ⁇ m or more and 20 ⁇ m or less.
  • each of the multiple bonding layers 42 includes a fillet portion 421.
  • the fillet portion 421 contacts the lateral electrode 191a.
  • the side surface of the fillet portion 421 is convexly curved, but it may be concavely curved or may not be curved.
  • Each of the multiple terminals 5 is conductive to the wiring layer 30 and is a conductor exposed to the outside of the electronic device A10.
  • Each of the multiple terminals 5 serves as a terminal when mounting the electronic device A10 on a wiring board. As shown in FIGS. 5 to 7, each of the multiple terminals 5 penetrates the support member 2 in the thickness direction z.
  • the multiple terminals 5 include those that are conductive to the semiconductor element 1 through the wiring layer 30, those that are conductive to one of the multiple electronic components 19 and the semiconductor element 1 through the wiring layer 30, those that are conductive to one of the multiple electronic components 19 through the wiring layer 30, and those that are not conductive to either the semiconductor element 1 or the multiple electronic components 19.
  • all of the multiple terminals 5 are disposed outside the semiconductor element 1 in a planar view and do not overlap either the semiconductor element 1 or the multiple electronic components 19 in a planar view. Unlike this example, some of the multiple terminals 5 may overlap either the semiconductor element 1 or the multiple electronic components 19 in a planar view.
  • each of the multiple terminals 5 includes a columnar portion 51 and an external electrode portion 52.
  • the columnar portion 51 and external electrode portion 52 described below are common to each terminal 5 unless otherwise specified.
  • the lower surface of the columnar portion 51 (surface facing downward in the thickness direction z) is exposed from the support member 2.
  • the lower surface of this columnar portion 51 is, for example, flush with the rear surface 22 of the support member 2.
  • the side of the columnar portion 51 (the surface facing the first direction x or the second direction y) of all terminals 5 is covered by the support member 2, but unlike this example, some terminals 5 may have exposed sides of the columnar portion 51.
  • the external electrode portion 52 contacts the portion of the columnar portion 51 that is exposed from the back surface 22 of the support member 2.
  • the external electrode portion 52 protrudes from the back surface 22.
  • the external electrode portion 52 is formed by electroless plating.
  • the external electrode portion 52 is composed of multiple metal layers, for example, a Ni layer, a palladium (Pd) layer, and a gold (Au) layer stacked in this order from the side in contact with the columnar portion 51.
  • the external electrode portion 52 can also be composed of multiple metal layers, such as a Ni layer and an Au layer stacked in this order from the side in contact with the columnar portion 51, or multiple metal layers, such as a Cu layer, an Ag layer, and an Sn layer stacked in this order.
  • the material and formation method of the external electrode portion 52 are not limited to these examples.
  • the resin main surface 61 and the resin back surface 62 are separated in the thickness direction z.
  • the resin main surface 61 and the resin back surface 62 face opposite each other in the thickness direction z.
  • the resin main surface 61 faces the same direction as the main surface 21 in the thickness direction z
  • the resin back surface 62 faces the same direction as the back surface 22 in the thickness direction z.
  • the resin back surface 62 is in contact with the main surface 21.
  • the resin back surface 62 has projections and recesses according to the shape of the wiring layer 30.
  • each of the multiple resin side surfaces 63 is sandwiched between the resin main surface 61 and the resin back surface 62 in the thickness direction z and is connected to them.
  • the multiple resin side surfaces 63 are flush with a corresponding one of the multiple side surfaces 23.
  • Figures 12 to 23 are cross-sectional views showing a step in the method for manufacturing electronic device A10. These cross-sectional views correspond to the cross-section shown in Figure 7. Note that the cross-sectional views shown in Figures 22 and 23 are opposite in thickness direction z to the cross-sectional views shown in Figures 12 to 21.
  • the wiring layer 30 is formed, for example, by the following process.
  • a seed layer is formed on the main surface 821 and each columnar portion 51.
  • the seed layer is formed, for example, by a sputtering method.
  • a Ti layer and a Cu layer are laminated in this order as the seed layer.
  • a resist is patterned on the seed layer, and a metal layer is formed by electrolytic plating.
  • the metal layer contains Cu.
  • the resist and unnecessary seed layer seed layer exposed from the metal layer
  • the wiring layer 30 is formed.
  • the plurality of barrier layers 350 and the plurality of plating layers 351 are formed in the region where the semiconductor element 1 is bonded and the region where the plurality of electronic components 19 are bonded, respectively.
  • Each formed barrier layer 350 is smaller than the wiring layer 30 in a plan view.
  • a plurality of electronic components 19 are mounted, and then the plurality of electronic components 19 are bonded.
  • the terminals 191 of the electronic components 19 and the bonding layer 420 are placed in correspondence with each other.
  • reflow is performed with each electronic component 19 placed.
  • Each bonding layer 420 melts due to the heat caused by this reflow.
  • the plating layer 351 also melts due to the heat caused by the reflow, and the plating layer 351 and each bonding layer 420 are mixed together.
  • the melted bonding layer 420 and plating layer 351 are cooled.
  • each bonding layer 420 and each plating layer 351 solidifies, and each electronic component 19 is bonded.
  • the bonding layer 420 and the plating layer 351 are integrated to become the bonding layer 42. Therefore, as shown in FIG. 19, each bonding layer 42 comes into contact with a corresponding barrier layer 350, and the barrier layer 350 becomes the barrier metal 35. As shown in FIG. 19, a fillet portion 421 is formed in each bonding layer 42 that is formed.
  • the plating layer 351 also melts due to the heat caused by the reflow, and the plating layer 351 and each bonding layer 410 are mixed together.
  • the melted bonding layer 410 and plating layer 351 are cooled.
  • each bonding layer 410 and plating layer 351 solidifies, and the semiconductor element 1 is bonded.
  • the bonding layer 410 and plating layer 351 are integrated to become the bonding layer 41. Therefore, as shown in FIG. 20, each bonding layer 41 comes into contact with the corresponding barrier layer 350, and the barrier layer 350 becomes the barrier metal 35.
  • a second resin layer 86 is formed.
  • the second resin layer 86 is formed above the support member 2 so as to cover the semiconductor element 1, the electronic components 19, and the wiring layer 30.
  • the second resin layer 86 is formed, for example, by molding.
  • the second resin layer 86 is a synthetic resin, for example, with a black epoxy resin as the main component.
  • the second resin layer 86 may be made of another insulating resin material instead of the synthetic resin.
  • the second resin layer 86 is a member that will later become the sealing resin 6.
  • the second resin layer 86 has a top surface 861 facing one side in the thickness direction z. The top surface 861 corresponds to the resin main surface 61 of the sealing resin 6.
  • the support substrate 80 is removed.
  • the support substrate 80 is ground from the rear surface 80b side of the substrate.
  • the support substrate 80 is ground from the rear surface 80b side of the substrate.
  • the grinding is continued even after the support substrate 80 is removed, thereby reducing the height of the support member 2 and the columnar portion 51. This reduction in height does not have to be performed.
  • the external electrode portion 52 is formed.
  • the external electrode portion 52 is formed on the top surface of the columnar portion 51 exposed from the rear surface 22.
  • the external electrode portion 52 is formed, for example, by electroless plating. In this electroless plating, a Ni layer, a Pd layer, and an Au layer are laminated in this order from the side in contact with the columnar portion 51. In this way, a plurality of terminals 5 are formed, each of which includes a columnar portion 51 and an external electrode portion 52.
  • the functions and effects of the electronic device A10 and the manufacturing method for the electronic device A10 are as follows.
  • the bonding layer 42 if the bonding layer 42 is insufficient in thickness, the bonding strength of the electronic component 19 is reduced. As described above, if the bonding layer 42 spreads along the wiring layer 30, there is a risk that the thickness of the bonding layer 42 will be insufficient. However, as described above, in the electronic device A10, the bonding layer 42 can be prevented from spreading along the wiring layer 30, and therefore the thickness of the bonding layer 42 can be prevented from becoming insufficient. In other words, the electronic device A10 can prevent a decrease in the bonding strength of the electronic component 19, and therefore a decrease in reliability.
  • a barrier metal 35 is interposed between the wiring layer 30 and the bonding layer 42.
  • the area in which the bonding layer 42 contacts the wiring layer 30 can be reduced.
  • the bonding layer 42 is solder and the wiring layer 30 contains Cu
  • the wiring layer 30 may penetrate into the bonding layer 42 in the area where the bonding layer 42 and the wiring layer 30 are in direct contact. This penetration may cause a conduction failure in the wiring layer 30.
  • the barrier metal 35 can reduce the contact area between the bonding layer 42 and the wiring layer 30, so that the conduction failure in the wiring layer 30 can be reduced. In other words, the electronic device A10 can reduce a decrease in reliability.
  • the resist 892 is removed.
  • the method for removing the resist 892 is not limited in any way. This forms the base 312, the barrier layer 350, and the plating layer 351. Immediately after removing the resist 892, the base 312, the barrier layer 350, and the plating layer 351 completely overlap each other in a plan view, as shown in FIG. 29. Also, as shown in FIG. 29, the seed layer 301 remains formed without being removed.
  • Appendix 8 The electronic device according to claim 1, further comprising a sealing resin that covers the electronic components.
  • Appendix 9. preparing a support member having a main surface facing in one direction in a thickness direction; a wiring layer forming step of forming a wiring layer on the main surface; a barrier layer forming step of forming a barrier layer on the wiring layer; a plating layer forming step of forming a plating layer on the barrier layer; a bonding layer forming step of forming a bonding layer on the plating layer; a mounting step of mounting an electronic component on the bonding layer; a bonding process of melting the bonding layer by reflow and solidifying the molten bonding layer by cooling to bond the electronic component; having The method for manufacturing an electronic device, wherein the plating layer contains tin and silver.
  • the wiring layer includes a main body portion formed on the main surface and a pedestal portion protruding from the main body portion to the one side in the thickness direction, 10.
  • the barrier layer is formed on the pedestal portion.
  • the wiring layer forming step includes a first process of forming a seed layer on the main surface, a second process of forming a metal layer on a part of the seed layer by electrolytic plating using the seed layer as a conductive path, and a third process of forming the pedestal portion on a part of the metal layer, The method for manufacturing an electronic device described in Appendix 10, wherein the main body portion has a laminated structure of the portion of the seed layer and the metal layer.
  • Appendix 12 Further comprising an etching step of performing etching after the plating layer forming step and before the bonding layer forming step, 12.
  • Appendix 13. 13 The method for manufacturing an electronic device according to claim 9, wherein the barrier layer and the wiring layer contain different metals.
  • Appendix 14. the barrier layer comprises nickel; 14.
  • Appendix 15. 15.
  • Appendix 17. the electronic component has side electrodes disposed on both ends in a direction perpendicular to the thickness direction, 17.
  • a fillet is formed in the bonding layer by the bonding step, the fillet being in contact with the side electrode.
  • Appendix 18. 18.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
PCT/JP2023/044243 2022-12-28 2023-12-11 電子装置および電子装置の製造方法 Ceased WO2024142884A1 (ja)

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US19/243,981 US20250318053A1 (en) 2022-12-28 2025-06-20 Electronic device and method for manufacturing electronic device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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JP2002246510A (ja) * 2001-02-20 2002-08-30 Hitachi Cable Ltd 配線基板及びテープキャリア並びにこれを用いた半導体装置
JP2011228422A (ja) * 2010-04-19 2011-11-10 Dainippon Printing Co Ltd 部品内蔵配線板、部品内蔵配線板の製造方法
JP2022092505A (ja) * 2020-12-10 2022-06-22 凸版印刷株式会社 基板ユニット、基板ユニットの製造方法及び半導体装置の製造方法

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