WO2024116612A1 - 窒化物半導体デバイス - Google Patents

窒化物半導体デバイス Download PDF

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WO2024116612A1
WO2024116612A1 PCT/JP2023/036963 JP2023036963W WO2024116612A1 WO 2024116612 A1 WO2024116612 A1 WO 2024116612A1 JP 2023036963 W JP2023036963 W JP 2023036963W WO 2024116612 A1 WO2024116612 A1 WO 2024116612A1
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layer
semiconductor layer
nitride semiconductor
semiconductor device
insulating film
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French (fr)
Japanese (ja)
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聡之 田村
直生 鳥居
雅弘 小川
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Panasonic Holdings Corp
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/477—Vertical HEMTs or vertical HHMTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/478—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/114—PN junction isolations
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

  • This disclosure relates to nitride semiconductor devices.
  • Nitride semiconductors such as GaN (gallium nitride) are wide band gap semiconductors that have the advantage of a high dielectric breakdown field and a high electron saturation drift velocity compared to existing Si (silicon) semiconductors and GaAs (gallium arsenide). This makes them advantageous for achieving high voltage resistance and high output, and research and development of power transistors using nitride semiconductors is being actively conducted.
  • GaN gallium nitride
  • Patent Document 1 discloses a vertical field effect transistor (FET) having a regrowth layer positioned so as to cover an opening provided in a GaN-based laminate, and a gate electrode positioned on the regrowth layer along the regrowth layer.
  • a channel is formed by two-dimensional electron gas (2DEG) generated in the regrowth layer.
  • 2DEG two-dimensional electron gas
  • a silicon oxide film, a silicon nitride film, an aluminum oxide film, or the like is formed as an insulating film in contact with the semiconductor surface.
  • Patent Document 1 has an issue of low operational reliability, as the device may not turn on normally under certain device operating conditions. There is also an issue with the off characteristics, in that leakage current increases when the device is off.
  • the present disclosure therefore provides a nitride semiconductor device with high operational reliability and improved off-state characteristics.
  • a nitride semiconductor device includes a substrate, a first semiconductor layer of a first conductivity type disposed above the substrate, a second semiconductor layer that is undoped and has a larger band gap than the first semiconductor layer and is disposed above the first semiconductor layer, a third semiconductor layer of a second conductivity type disposed above the second semiconductor layer, a fourth semiconductor layer including a channel and at least a portion of which is disposed above the third semiconductor layer, a gate electrode disposed above the first semiconductor layer, the gate electrode overlapping in a plan view with a first opening that penetrates the second semiconductor layer and the third semiconductor layer to reach the first semiconductor layer, a source electrode disposed at a distance from the gate electrode, a drain electrode disposed below the substrate, and an insulating film disposed above the gate electrode, and a groove provided at an end portion of the nitride semiconductor device, the insulating film covering the bottom and sidewalls of the groove that penetrates the third semiconductor layer to reach the second semiconductor layer.
  • the present disclosure makes it possible to provide a nitride semiconductor device with high operational reliability and improved off-state characteristics.
  • FIG. 1 is a cross-sectional view of a nitride semiconductor device according to the first embodiment.
  • FIG. 2 is a plan view of the nitride semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view of a termination portion of a nitride semiconductor device according to a comparative example.
  • FIG. 4 is a cross-sectional view of a termination portion of the nitride semiconductor device according to the first embodiment.
  • FIG. 5 is a diagram showing the relationship between the Al composition ratio and the leakage current in the nitride semiconductor device according to the first embodiment.
  • FIG. 6 is a cross-sectional view of a nitride semiconductor device according to the second embodiment.
  • FIG. 7 is a cross-sectional view of a nitride semiconductor device according to the third embodiment.
  • FIG. 8 is a cross-sectional view of a nitride semiconductor device according to the fourth embodiment.
  • An insulating film is formed between the gate electrode and the field plate of the transistor section of the nitride semiconductor device disclosed in Patent Document 1.
  • a part of the p-type semiconductor layer and the n-type semiconductor layer is removed to expose the side section of the pn junction interface.
  • An insulating film is formed so as to cover the surface of the exposed n-type semiconductor layer and the side section of the pn junction interface.
  • the insulating film of the transistor section and the insulating film of the termination section are formed simultaneously, and for example, a silicon nitride (SiN) film formed by a plasma chemical vapor deposition (CVD) method or a silicon oxide (SiO 2 ) film formed by a spin coating method is used.
  • SiN silicon nitride
  • CVD plasma chemical vapor deposition
  • SiO 2 silicon oxide
  • the spin-coating method is used for forming SiO 2 films, etc.
  • the SiO 2 films formed by the spin-coating method are highly amorphous and tend to generate unintended charges in the film.
  • the transistor section of a nitride semiconductor device if an insulating film in which charges are generated exists between the field plate connected to the source electrode and the gate electrode, it becomes difficult to apply the gate potential normally. As a result, switching problems such as the device not turning on normally occur depending on the device driving conditions.
  • the present disclosure provides a nitride semiconductor device that improves off-characteristics by suppressing the increase in leakage current, and has high operational reliability by suppressing switching issues.
  • the nitride semiconductor device includes a substrate, a first semiconductor layer of a first conductivity type disposed above the substrate, a second semiconductor layer that is undoped and has a larger band gap than the first semiconductor layer and is disposed above the first semiconductor layer, a third semiconductor layer of a second conductivity type disposed above the second semiconductor layer, a fourth semiconductor layer including a channel and at least a portion of which is disposed above the third semiconductor layer, a gate electrode disposed above the first semiconductor layer, the gate electrode overlapping in a plan view with a first opening that penetrates the second semiconductor layer and the third semiconductor layer to reach the first semiconductor layer, a source electrode disposed at a distance from the gate electrode, a drain electrode disposed below the substrate, and an insulating film disposed above the gate electrode, and a groove provided at an end portion of the nitride semiconductor device, the insulating film covering the bottom and sidewalls of the groove that penetrates the third semiconductor layer to reach the second semiconductor layer.
  • the bottom of the groove becomes the upper surface of the undoped second semiconductor layer, and the pn junction interface between the first semiconductor layer and the third semiconductor layer is not exposed on the sidewall of the groove.
  • This makes it possible to prevent damage caused when forming the insulating film from entering the pn junction interface.
  • This makes it possible to suppress the leakage current at the end portion when it is off, thereby improving the off characteristics.
  • a plasma chemical vapor deposition method or the like can be used to form the insulating film. This makes it possible to form an insulating film with high crystallinity, and suppresses the generation of charges in the film. This makes it possible to suppress the deterioration of the switching characteristics and improve the reliability of the operation. In this way, according to this aspect, a nitride semiconductor device with high operational reliability and improved off characteristics can be realized.
  • the nitride semiconductor device according to the second aspect of the present disclosure is, for example, the nitride semiconductor device according to the first aspect, in which the second semiconductor layer contains AlGaN as a main component.
  • the third semiconductor layer and the first semiconductor layer are GaN layers
  • a potential barrier can be formed by utilizing the band gap difference between GaN and AlGaN, and leakage current during off-state can be suppressed.
  • the difference in etching rate between GaN and AlGaN can be utilized to facilitate control of etching during formation of the grooves. Since a sufficient thickness of the second semiconductor layer can be left, the effect of suppressing leakage current during off-state can be enhanced.
  • the nitride semiconductor device according to the third aspect of the present disclosure is, for example, the nitride semiconductor device according to the first or second aspect, in which the first semiconductor layer contains GaN as a main component, and the Al composition ratio of the second semiconductor layer is 10% or more.
  • the nitride semiconductor device according to the fourth aspect of the present disclosure is, for example, a nitride semiconductor device according to any one of the first to third aspects, in which the bottom of the groove is flush with the interface between the second semiconductor layer and the third semiconductor layer, or is located near the interface below the interface.
  • the nitride semiconductor device according to the fifth aspect of the present disclosure is, for example, the nitride semiconductor device according to any one of the first to fourth aspects, further comprising a fifth semiconductor layer that is arranged between the first and second semiconductor layers, has a smaller band gap than the second semiconductor layer, and is undoped, and the first opening further penetrates the fifth semiconductor layer.
  • the two-dimensional electron gas generated near the heterointerface between the second semiconductor layer and the fifth semiconductor layer makes it easier to spread the current laterally in the nitride semiconductor device. This makes it possible to achieve low resistance when the device is on.
  • a nitride semiconductor device is, for example, a nitride semiconductor device according to any one of the first to fifth aspects, in which the fourth semiconductor layer includes a plurality of semiconductor films having different bandgaps, the channel is a two-dimensional electron gas generated at the interface between the plurality of semiconductor films, and a portion of the fourth semiconductor layer is disposed along the inner surface between the inner surface of the first opening and the gate electrode.
  • the nitride semiconductor device according to the seventh aspect of the present disclosure is, for example, the nitride semiconductor device according to the sixth aspect, further comprising a sixth semiconductor layer of the second conductivity type disposed between the fourth semiconductor layer and the gate electrode.
  • the nitride semiconductor device according to the eighth aspect of the present disclosure is, for example, a nitride semiconductor device according to any one of the first to fifth aspects, further comprising a gate insulating film disposed along an inner surface of the first opening between the inner surface of the first opening and the gate electrode, and the first opening penetrates the fourth semiconductor layer.
  • the insulating film has a single layer structure or a multilayer structure containing SiN.
  • each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of each figure do not necessarily match.
  • the same reference numerals are used for substantially the same configuration, and duplicate explanations are omitted or simplified.
  • the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system.
  • the x-axis and y-axis are directions parallel to a first side of the rectangle and a second side perpendicular to the first side.
  • the z-axis is the thickness direction of the substrate.
  • the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate.
  • the thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction.”
  • the direction parallel to the main surface of the substrate may also be referred to as the "horizontal direction.”
  • the side of the substrate on which the gate electrode and source electrode are provided (positive side of the z-axis) is considered to be the "upper” or “upper side”
  • the side of the substrate on which the drain electrode is provided (negative side of the z-axis) is considered to be the "lower” or “lower side”.
  • the terms “above” and “below” do not refer to the upward (vertically upward) and downward (vertically downward) directions in an absolute spatial sense, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms “above” and “below” are not only used when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged in close contact with each other and are in contact with each other.
  • planar view refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, i.e., a view of the main surface of the substrate from the front.
  • ordinal numbers such as “first” and “second” do not refer to the number or order of components, unless otherwise specified, but are used for the purpose of avoiding confusion between and distinguishing between components of the same type.
  • AlGaN refers to ternary mixed crystal Al x Ga 1-x N (0 ⁇ x ⁇ 1).
  • multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, for example, AlInN, GaInN, etc.
  • Al x Ga 1-x-y In y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, and 0 ⁇ x+y ⁇ 1), which is an example of a nitride semiconductor, is abbreviated as AlGaInN.
  • FIG. 1 is a cross-sectional view of a nitride semiconductor device 1 according to this embodiment.
  • FIG. 2 is a plan view of a nitride semiconductor device 1 according to this embodiment.
  • FIG. 1 shows a cross section taken along line I-I in FIG. 2. Note that FIG. 1 shows a schematic separation between a transistor portion 2 and a termination portion 3.
  • the nitride semiconductor device 1 includes a transistor section 2 and a termination section 3.
  • the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a barrier layer 14, a current blocking layer 16, a gate opening 20, a semiconductor multilayer film 21, a threshold adjustment layer 28, a source opening 30, a source electrode 32, a gate electrode 34, a drain electrode 36, an insulating film 42, and a source wiring 44.
  • the semiconductor multilayer film 21 is a laminate of an electron transit layer 22 and an electron supply layer 24, and includes a two-dimensional electron gas (2DEG) 26 as a channel region.
  • the nitride semiconductor device 1 also includes a groove section 40 provided in the termination section 3.
  • the transistor portion 2 is a region that includes a FET, and is a region that includes the center of the nitride semiconductor device 1, as shown in FIG. 2.
  • the transistor portion 2 is a portion that becomes a current path between the source and drain when the transistor portion 2 is on.
  • the transistor portion 2 is a region in which, in a plan view, a gate opening 20, a semiconductor multilayer film 21, a threshold adjustment layer 28, a source electrode 32, and a gate electrode 34 are arranged.
  • a plurality of source electrodes 32 each having a shape elongated in one direction in plan view are arranged in a stripe pattern, and a gate opening 20, a semiconductor multilayer film 21, a threshold adjustment layer 28, and a gate electrode 34 are arranged between each source electrode.
  • a plurality of source electrodes 32 each having a hexagonal shape in plan view may be arranged so as to fill a plane with gaps between them.
  • the termination portion 3 is a region other than the transistor portion 2, and is provided in a ring shape surrounding the transistor portion 2.
  • the termination portion 3 is a portion that does not become a current path between the source and drain when on.
  • the termination portion 3 can be considered as a region outside the outermost portion of the source electrode 32.
  • the termination portion 3 does not include the gate opening 20, the semiconductor multilayer film 21, the threshold adjustment layer 28, the source electrode 32, the gate electrode 34, etc. Note that the semiconductor multilayer film 21 and the threshold adjustment layer 28 may be arranged in the termination portion 3 as long as they are electrically isolated from the source electrode 32. Even in this case, the groove portion 40 reaches the barrier layer 14.
  • the nitride semiconductor device 1 is a device having a stacked structure of semiconductor layers containing nitride semiconductors such as GaN and AlGaN as the main components.
  • a contains B as the main component means that the content of B in A is 50% or more.
  • the nitride semiconductor device 1 has a heterostructure of an AlGaN film and a GaN film.
  • spontaneous polarization or piezoelectric polarization on the (0001) plane generates a high concentration of two-dimensional electron gas 26 at the heterointerface. Therefore, even in an undoped state, the interface has a characteristic of having a sheet carrier concentration of 1 ⁇ 10 13 cm ⁇ 2 or more.
  • the nitride semiconductor device 1 is a field effect transistor (FET) that uses a two-dimensional electron gas 26 generated at the AlGaN/GaN heterointerface as a channel.
  • FET field effect transistor
  • the nitride semiconductor device 1 is a so-called vertical FET.
  • the nitride semiconductor device 1 is a normally-off type FET.
  • the on and off of the device is controlled by adjusting the potential applied to the gate electrode 34.
  • the source electrode 32 is grounded (i.e., the potential is 0 V), and a positive potential is applied to the drain electrode 36.
  • the potential applied to the drain electrode 36 is, for example, 100 V or more and 1200 V or less, but is not limited to this.
  • 0 V or a negative potential for example, -5 V
  • a positive potential for example, +5 V
  • a current flows from the drain electrode 36 through the substrate 10, the drift layer 12, and the semiconductor multilayer film 21 to the source electrode 32.
  • the nitride semiconductor device 1 may be a normally-on type FET.
  • composition Each of the components of the nitride semiconductor device 1 will be described in detail below.
  • the substrate 10 is made of a nitride semiconductor, and has a first main surface 10a and a second main surface 10b facing each other as shown in FIG. 1.
  • the first main surface 10a is the main surface (upper surface) on the side on which the drift layer 12 is formed. Specifically, the first main surface 10a approximately coincides with the c-plane.
  • the second main surface 10b is the main surface (lower surface) on the side on which the drain electrode 36 is formed.
  • the planar shape of the substrate 10 is, for example, rectangular, but is not limited to this.
  • the substrate 10 is, for example, a substrate made of n + type GaN having a thickness of 300 ⁇ m and a carrier concentration of 1 ⁇ 10 18 cm ⁇ 3 .
  • the n type and p type indicate the conductivity type of the semiconductor.
  • the n + type represents a state in which a semiconductor is doped with a high concentration of n-type dopants, that is, a so-called heavy dope.
  • the n ⁇ type represents a state in which a semiconductor is doped with a low concentration of n-type dopants, that is, a so-called light dope.
  • the n type, n + type, and n ⁇ type are examples of the first conductivity type.
  • the p type, p + type, and p ⁇ type are examples of the second conductivity type.
  • the second conductivity type is a conductivity type of the opposite polarity to the first conductivity type.
  • the substrate 10 does not have to be a nitride semiconductor substrate.
  • the substrate 10 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.
  • the drift layer 12 is an example of a first nitride semiconductor layer of a first conductivity type disposed above the substrate 10.
  • the conductivity type of the drift layer 12 is the same as that of the substrate 10.
  • the drift layer 12 contains GaN as a main component.
  • the carrier concentration and film thickness of the drift layer 12 are important parameters that determine the breakdown voltage of the nitride semiconductor device 1, and are adjusted according to the operating voltage. For example, when the rated voltage is 650 V, an n-type GaN layer having a thickness of 8 ⁇ m and a carrier concentration of 1 ⁇ 10 16 cm ⁇ 3 is formed as the drift layer 12. Note that Si is generally used as an impurity exhibiting n-type conductivity.
  • the donor concentration of the drift layer 12 is not limited to the above example, and may be, for example, in the range of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less.
  • the carbon concentration (C concentration) of the drift layer 12 is in the range of 1 ⁇ 10 15 cm ⁇ 3 or more and 2 ⁇ 10 17 cm ⁇ 3 or less.
  • the drift layer 12 is provided, for example, in contact with the first main surface 10a of the substrate 10.
  • the drift layer 12 is formed on the first main surface 10a of the substrate 10 by crystal growth, for example, by metal organic vapor phase epitaxy (MOVPE) or hydride vapor phase epitaxy (HVPE).
  • MOVPE metal organic vapor phase epitaxy
  • HVPE hydride vapor phase epitaxy
  • the barrier layer 14 is an example of a second nitride semiconductor layer that is disposed above the drift layer 12, has a larger band gap than the drift layer 12, and is undoped.
  • the barrier layer 14 contains AlGaN as a main component.
  • the Al composition ratio (content) of the barrier layer 14 is 10% or more. Alternatively, the Al composition ratio may be 15% or more.
  • the barrier layer 14 is an undoped AlGaN layer that is not intentionally doped with impurities.
  • undoped means that GaN is not doped with dopants such as Si or Mg that change the polarity of the GaN to n-type or p-type. Note that “undoped” may also include cases where a very small amount of doping is performed so that it does not contribute to conductivity.
  • the barrier layer 14 is provided in contact with the upper surface of the drift layer 12.
  • the barrier layer 14 is formed on the drift layer 12 by crystal growth using, for example, the MOVPE method, the HVPE method, or the like.
  • the barrier layer 14 only needs to have a band gap larger than that of the material constituting the drift layer 12.
  • the barrier layer 14 may be a nitride semiconductor layer of a quaternary alloy such as AlGaInN.
  • the current blocking layer 16 is an example of a third nitride semiconductor layer of a second conductivity type disposed above the barrier layer 14.
  • the current blocking layer 16 is, for example, a layer made of p-type GaN.
  • the current blocking layer 16 has, for example, a thickness of 400 nm and a carrier concentration of 1 ⁇ 10 17 cm ⁇ 3 .
  • the current blocking layer 16 is provided in contact with the upper surface of the barrier layer 14.
  • the current blocking layer 16 is formed on the barrier layer 14 by crystal growth, for example, by MOVPE, HVPE, or the like.
  • the current blocking layer 16 may be composed of multiple layers including at least a p-type semiconductor layer.
  • the current blocking layer 16 may include a p-type GaN layer and a high-resistance semiconductor layer provided on the p-type GaN layer.
  • the high-resistance semiconductor layer is a layer with a higher resistance than the p-type GaN layer, and is, for example, a GaN layer doped with an element that increases resistance, such as carbon (C).
  • the current blocking layer 16 suppresses leakage current between the source electrode 32 and the drain electrode 36.
  • a reverse voltage is applied to the pn junction formed by the current blocking layer 16 and the drift layer 12, specifically when the drain electrode 36 has a higher potential than the source electrode 32, a depletion layer extends to the drift layer 12. This allows the nitride semiconductor device 1 to withstand high voltages.
  • the drain electrode 36 in both the off state and the on state, the drain electrode 36 has a higher potential than the source electrode 32, except in the case of reverse conduction. This allows the nitride semiconductor device 1 to withstand high voltages.
  • the current blocking layer 16 is in contact with the source electrode 32. Therefore, the current blocking layer 16 is fixed at the same potential as the source electrode 32.
  • the gate opening 20 is an example of a first opening that penetrates the current blocking layer 16 and the barrier layer 14 to reach the drift layer 12.
  • the bottom 20a of the gate opening 20 is part of the upper surface of the drift layer 12. As shown in FIG. 1, the bottom 20a is located below the lower surface of the barrier layer 14. The lower surface of the barrier layer 14 corresponds to the interface between the barrier layer 14 and the drift layer 12.
  • the bottom 20a is, for example, parallel to the first major surface 10a of the substrate 10.
  • the gate opening 20 is formed so that the opening area increases as it is farther away from the substrate 10. Specifically, the sidewall 20b of the gate opening 20 is inclined at an angle. As shown in FIG. 1, the cross-sectional shape of the gate opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.
  • the inclination angle of the sidewall 20b relative to the bottom 20a is, for example, in the range of 30° to 45°.
  • the smaller the inclination angle the closer the sidewall 20b is to the c-plane, which improves the film quality of the electron transit layer 22 and other layers formed along the sidewall 20b by crystal regrowth.
  • the larger the inclination angle the more the gate opening 20 is prevented from becoming too large, which allows the nitride semiconductor device 1 to be made smaller.
  • the gate opening 20 is formed by successively depositing the drift layer 12, barrier layer 14, and current blocking layer 16 in this order on the first main surface 10a of the substrate 10, and then removing a portion of each of the current blocking layer 16 and the barrier layer 14 so as to partially expose the drift layer 12. At this time, by removing a surface portion of the drift layer 12 by a predetermined thickness, for example 300 nm, the bottom 20a of the gate opening 20 is formed below the lower surface of the barrier layer 14.
  • the current blocking layer 16 and the barrier layer 14 are removed by dry etching such as inductively coupled plasma etching (ICP), and a chlorine-based gas is often used as the process gas.
  • ICP inductively coupled plasma etching
  • a chlorine-based gas is often used as the process gas.
  • the semiconductor multilayer film 21 is an example of a fourth nitride semiconductor layer that includes a channel and at least a portion of which is disposed above the current blocking layer 16. Specifically, the semiconductor multilayer film 21 includes multiple semiconductor films with different bandgaps. The two-dimensional electron gas 26 that is generated at the interface between the multiple semiconductor films is the channel. The channel refers to at least a portion of the current path formed between the source and drain.
  • a portion of the semiconductor multilayer film 21 is disposed along the inner surface of the gate opening 20 between the inner surface of the gate opening 20 and the gate electrode 34. Another portion of the semiconductor multilayer film 21 is disposed above the current blocking layer 16.
  • the semiconductor multilayer film 21 is a laminated film of an electron transit layer 22 and an electron supply layer 24.
  • the electron transit layer 22 and the electron supply layer 24 are examples of multiple semiconductor films with different band gaps.
  • the electron transit layer 22 is an example of a first regrown layer provided along the inner surface of the gate opening 20. Specifically, a part of the electron transit layer 22 is provided along the bottom 20a and sidewall 20b of the gate opening 20, and the other part of the electron transit layer 22 is provided on the upper surface of the current blocking layer 16.
  • the electron transit layer 22 is, for example, a film made of undoped GaN with a thickness of 150 nm. Note that the electron transit layer 22 does not have to be undoped, and may be made n-type by, for example, Si doping.
  • the electron transit layer 22 is in contact with the drift layer 12 at the bottom 20a and sidewall 20b of the gate opening 20.
  • the electron transit layer 22 is in contact with the end faces of the barrier layer 14 and the current blocking layer 16 at the sidewall 20b of the gate opening 20. Furthermore, the electron transit layer 22 is in contact with the top surface of the current blocking layer 16.
  • the electron transit layer 22 is formed by crystal regrowth after the gate opening 20 is formed.
  • the electron transit layer 22 has a channel region. Specifically, a two-dimensional electron gas 26 is generated near the interface between the electron transit layer 22 and the electron supply layer 24.
  • the two-dimensional electron gas 26 functions as a channel for the electron transit layer 22.
  • the two-dimensional electron gas 26 is diagrammatically shown by a dashed line.
  • the two-dimensional electron gas 26 is bent along the interface between the electron transit layer 22 and the electron supply layer 24, i.e., along the inner surface of the gate opening 20.
  • an AlN film with a thickness of about 1 nm may be provided as a second regrown layer between the electron transit layer 22 and the electron supply layer 24.
  • the AlN film can suppress alloy scattering and improve the mobility of the channel.
  • the electron supply layer 24 is an example of a third regrowth layer provided along the inner surface of the gate opening 20.
  • the electron transit layer 22 and the electron supply layer 24 are provided in this order from the substrate 10 side.
  • the electron supply layer 24 is formed with a shape that follows the upper surface of the electron transit layer 22 and has a substantially uniform thickness.
  • the electron supply layer 24 is, for example, a film made of undoped AlGaN with a thickness of 50 nm.
  • the electron supply layer 24 is formed by crystal regrowth following the process of forming the electron transit layer 22.
  • the electron supply layer 24 has a larger band gap than the electron transit layer 22. Therefore, an AlGaN/GaN heterointerface is formed between the electron supply layer 24 and the electron transit layer 22. This generates a two-dimensional electron gas 26 in the electron transit layer 22.
  • the electron supply layer 24 supplies electrons to a channel region (i.e., two-dimensional electron gas 26) formed in the electron transit layer 22.
  • a high concentration of two-dimensional electron gas (2DEG) 26 is generated by spontaneous polarization or piezoelectric polarization on the (0001) plane.
  • the two-dimensional electron gas 26 is a layer with high electron mobility, and this layer functions as a channel under the gate.
  • the semiconductor multilayer film 21 is an n-type semiconductor layer with a large number of electrons, and is a semiconductor layer of the same conductivity type as the substrate 10 and the drift layer 12.
  • the electron transit layer 22 and the electron supply layer 24 are successively deposited by regrowth using the MOVPE method and the HVPE method, and then patterned.
  • the threshold adjustment layer 28 is an example of a sixth semiconductor layer of the second conductivity type disposed between the semiconductor multilayer film 21 and the gate electrode 34. Specifically, the threshold adjustment layer 28 is provided between the gate electrode 34 and the electron supply layer 24. The threshold adjustment layer 28 is formed to a shape that conforms to the upper surface of the electron supply layer 24 and to a substantially uniform thickness.
  • the threshold adjustment layer 28 is, for example, a nitride semiconductor layer made of p-type GaN or AlGaN having a thickness of 100 nm and a carrier concentration of 1 ⁇ 10 17 cm ⁇ 3 .
  • Mg can be used as an impurity exhibiting p-type conductivity.
  • the threshold adjustment layer 28 is formed by forming a film by regrowth using the MOVPE method or the HVPE method following the step of forming the electron supply layer 24, and then patterning.
  • the threshold adjustment layer 28 By providing the threshold adjustment layer 28, the potential of the conduction band edge of the channel portion is raised. This makes it possible to increase the threshold voltage of the nitride semiconductor device 1. This allows the nitride semiconductor device 1 to be realized as a normally-off type FET. In other words, when a potential of 0 V is applied to the gate electrode 34, the nitride semiconductor device 1 can be turned off. Note that the threshold adjustment layer 28 does not necessarily have to be provided.
  • the source opening 30 is an example of a second opening that penetrates the semiconductor multilayer film 21 and reaches the current blocking layer 16 at a position away from the gate opening 20.
  • the source opening 30 is located at a position away from the gate electrode 34 in a plan view.
  • the bottom 30a of the source opening 30 is part of the upper surface of the current blocking layer 16. As shown in FIG. 1, the bottom 30a is located below the lower surface of the semiconductor multilayer film 21. The lower surface of the semiconductor multilayer film 21 corresponds to the interface between the semiconductor multilayer film 21 and the current blocking layer 16. The bottom 30a is, for example, parallel to the first major surface 10a of the substrate 10.
  • the source opening 30 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, the sidewall 30b of the source opening 30 is perpendicular to the bottom 30a. In other words, the cross-sectional shape of the source opening 30 is rectangular.
  • the source opening 30 may be formed so that the opening area increases as it moves away from the substrate 10.
  • the sidewall 30b of the source opening 30 may be inclined obliquely.
  • the cross-sectional shape of the source opening 30 may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid.
  • the inclination angle of the sidewall 30b with respect to the bottom 30a may be, for example, in the range of 30° to 60°.
  • the inclination angle of the sidewall 30b of the source opening 30 may be larger than the inclination angle of the sidewall 20b of the gate opening 20.
  • the inclination of the sidewall 30b at an angle increases the contact area between the source electrode 32 and the electron transit layer 22 (two-dimensional electron gas 26), making it easier to make an ohmic connection.
  • the two-dimensional electron gas 26 is exposed to the sidewall 30b of the source opening 30, and is connected to the source electrode 32 at the exposed portion.
  • the source electrode 32 is disposed at a distance from the gate electrode 34.
  • the source electrode 32 is provided along the inner surface of the source opening 30.
  • the source electrode 32 is connected to each of the electron supply layer 24, the electron transit layer 22, and the current blocking layer 16.
  • the source electrode 32 is ohmically connected to each of the electron transit layer 22 and the electron supply layer 24.
  • the source electrode 32 is in direct contact with the two-dimensional electron gas 26 at the side wall 30b. This makes it possible to reduce the contact resistance between the source electrode 32 and the two-dimensional electron gas 26 (channel).
  • the source electrode 32 is formed using a conductive material such as a metal.
  • the material of the source electrode 32 may be, for example, Ti/Al, which is ohmic-connected to the n-type GaN layer by heat treatment.
  • the source electrode 32 is formed by patterning a conductive film formed by, for example, sputtering or EB deposition.
  • the gate electrode 34 is disposed above the threshold adjustment layer 28 and overlaps the gate opening 20 in a plan view. Specifically, the gate electrode 34 is provided in contact with the upper surface of the threshold adjustment layer 28 so as to cover the gate opening 20.
  • the gate electrode 34 is formed, for example, with a shape that conforms to the upper surface of the threshold adjustment layer 28 and with a substantially uniform film thickness. Alternatively, the gate electrode 34 may be formed so as to fill a recess in the upper surface of the threshold adjustment layer 28.
  • the gate electrode 34 is formed using a conductive material such as a metal.
  • the gate electrode 34 is formed using palladium (Pd).
  • the material of the gate electrode 34 may be a material that is ohmic-connected to the p-type GaN layer, such as nickel (Ni)-based material, tungsten silicide (WSi), or gold (Au).
  • the gate electrode 34 is formed by patterning a conductive film formed by, for example, sputtering or EB deposition after the threshold adjustment layer 28 is formed, after the source opening 30 is formed, or after the source electrode 32 is formed.
  • the drain electrode 36 is disposed below the substrate 10. Specifically, the drain electrode 36 is provided on the opposite side to the drift layer 12. More specifically, the drain electrode 36 is provided in contact with the second main surface 10b of the substrate 10.
  • the drain electrode 36 is formed using a conductive material such as a metal. As with the material of the source electrode 32, the material for the drain electrode 36 may be a material that forms an ohmic connection with the n-type GaN layer, such as Ti/Al.
  • the drain electrode 36 is formed, for example, by patterning a conductive film formed by sputtering or EB deposition.
  • the semiconductor multilayer film 21 and the threshold adjustment layer 28 are not provided in the termination portion 3.
  • the semiconductor multilayer film 21 and the threshold adjustment layer 28 in the termination portion 3 are removed at the same time as the source opening 30 is formed.
  • a part of the current blocking layer 16 is also removed.
  • the top surface of the current blocking layer 16 is located at the same height as the bottom portion 30a of the source opening 30.
  • the same height means that the distance from the first main surface 10a of the substrate 10 is the same. The reason they are at the same height is because they are formed at the same time, and they do not have to be at the same height if the termination portion is formed separately from the source opening.
  • the termination portion 3 has a groove portion 40.
  • the groove portion 40 is an isolation trench for partitioning and isolating the transistor portion 2.
  • the groove portion 40 penetrates the current blocking layer 16 and reaches the barrier layer 14.
  • the groove portion 40 has a bottom portion 40a and a sidewall 40b.
  • the groove portion 40 is a step portion having a sidewall 40b only on the transistor portion 2 side.
  • the bottom portion 40a of the groove portion 40 is connected to the end face of the nitride semiconductor device 1.
  • the groove portion 40 is provided in a ring shape surrounding the transistor portion 2.
  • the bottom 40a of the groove 40 is part of the upper surface of the barrier layer 14. As shown in FIG. 1, the bottom 40a is flush with the interface between the barrier layer 14 and the current blocking layer 16. The bottom 40a is, for example, parallel to the first major surface 10a of the substrate 10. The bottom 40a may be located below the interface between the barrier layer 14 and the current blocking layer 16.
  • the insulating film 42 is disposed above the gate electrode 34. Specifically, the insulating film 42 covers almost the entire area of the transistor portion 2, and has an end disposed in the termination portion 3. The insulating film 42 is disposed so as to cover the bottom 40a and sidewall 40b of the groove portion 40. The insulating film 42 is provided with a contact hole 43 for exposing the source electrode 32. The insulating film 42 contacts and covers each of the gate electrode 34, the threshold adjustment layer 28, and the electron supply layer 24. The insulating film 42 is disposed so as not to expose electrodes and semiconductor layers other than the source electrode 32 exposed in the contact hole 43.
  • the insulating film 42 contains nitride as a main component.
  • the insulating film 42 is not a highly amorphous film formed by, for example, a spin-coating method, but is a silicon nitride film formed by, for example, a plasma chemical vapor deposition method.
  • the insulating film 42 has a single-layer structure of silicon nitride. Silicon nitride has high crystallinity and can suppress the generation of unintended charges in the film. This makes it possible to suppress one of the problems, the phenomenon of normal switching under specific driving conditions. This can increase the reliability of the operation of the nitride semiconductor device 1.
  • the source wiring 44 is disposed above the insulating film 42.
  • the source wiring 44 is provided so as to contact and cover the upper surface of the insulating film 42.
  • the source wiring 44 penetrates the insulating film 42 and is connected to the source electrode 32.
  • the source wiring 44 is provided so as to fill the contact hole 43, and electrically connects the multiple source electrodes 32 to each other.
  • the source wiring 44 is formed using a conductive material such as a metal.
  • the source wiring 44 may be made of the same material as the source electrode 32.
  • the source wiring 44 is also provided in the termination portion 3. Specifically, the source wiring 44 overlaps with the groove portion 40 in a plan view.
  • the source wiring 44 functions as a field plate when a source potential is supplied. This makes it possible to reduce the electric field applied to the pn junction interface in the termination portion 3, thereby suppressing an increase in leakage current when the device is off.
  • barrier layer 14 The role of the barrier layer 14 will be explained below, in comparison with the comparative example shown in Figure 3.
  • FIG. 3 is a cross-sectional view of the termination 3 of a nitride semiconductor device 1x according to a comparative example.
  • the nitride semiconductor device 1x according to the comparative example does not have a barrier layer 14. That is, the current blocking layer 16 exhibiting p-type conductivity and the drift layer 12 exhibiting n-type conductivity are in contact with each other. The current blocking layer 16 is removed until the drift layer 12 is exposed, thereby forming a groove 40. That is, the bottom 40a of the groove 40 is the upper surface of the drift layer 12, and the interface between the drift layer 12 and the current blocking layer 16 is exposed on the sidewall 40b of the groove 40.
  • An insulating film 42 is provided so as to cover the bottom 40a and the sidewall 40b.
  • a depletion layer 50 containing almost no electrons 52 or holes 51 is formed at the interface between the p-type current blocking layer 16 and the n-type drift layer 12. For this reason, the leakage current during the off state (specifically, when a positive voltage is applied to the drain electrode 36 with respect to the source wiring 44) is small.
  • a silicon nitride film is formed as the insulating film 42 by, for example, plasma chemical vapor deposition, on the portion of the pn junction interface between the p-type current blocking layer 16 and the n-type drift layer 12 exposed to the sidewall 40b, damage occurs. This damage generates traps that become leakage paths in the depletion layer 50 of the pn junction. The traps cause leakage paths along the sidewall 40b, increasing the leakage current during the off state.
  • FIG. 4 is a cross-sectional view of the termination portion 3 of the nitride semiconductor device 1 according to this embodiment.
  • the barrier layer 14 is an undoped AlGaN layer, and has a larger band gap than the drift layer 12. There are few electrons and holes supplied from impurities in the barrier layer 14. In addition, due to the potential barrier formed between the barrier layer 14 and the drift layer 12, the probability that electrons present in the drift layer 12 will be distributed in the barrier layer 14 is also very small.
  • the band gap of the barrier layer 14 is the same as that of the drift layer 12, even if the barrier layer 14 is undoped, electrons may diffuse from the drift layer 12, resulting in a layer containing a relatively large number of electrons.
  • the barrier layer 14 also functions as an etching stopper layer when forming the groove 40.
  • etching rate (speed) of the barrier layer 14 is slower than that of the current blocking layer 16
  • etching can be easily stopped in the barrier layer 14 after the current blocking layer 16 has been completely removed by etching.
  • the drift layer 12 is not exposed at the bottom 40a of the groove 40.
  • the surface portion of the barrier layer 14 may be removed by etching. In this case, the bottom 40a of the groove 40 will be located below the interface between the current blocking layer 16 and the barrier layer 14.
  • a silicon nitride film is formed as the insulating film 42 for such a groove portion 40 using, for example, plasma chemical vapor deposition, even if traps are generated on the exposed surface, the layer in which the holes 51 exist and the layer in which the electrons 52 exist are separated, so no leakage path that would cause an increase in leakage current is generated. As a result of the above effects, this configuration can suppress one of the issues of an increase in leakage current when the device is off.
  • the drift layer 12 is often made of GaN, in which case the Al composition ratio of the barrier layer 14 is, for example, 10% or more. Alternatively, the Al composition ratio of the barrier layer 14 may be 15% or more.
  • FIG. 5 is a diagram showing the relationship between the Al composition ratio and the leakage current of the nitride semiconductor device 1 according to this embodiment.
  • the horizontal axis represents the voltage applied between the source and drain.
  • the vertical axis represents the leakage current flowing between the source and drain.
  • the comparative example shows the characteristics of a nitride semiconductor device 1x that does not have a barrier layer 14, as shown in Figure 3. It can be seen that the leakage current increases as the voltage increases.
  • Examples 1 and 2 show the characteristics of the nitride semiconductor device 1.
  • Examples 1 and 2 have the same configuration, except that the barrier layer 14 is an AlGaN layer and has a different Al composition ratio. Specifically, in Example 1, the Al composition ratio of the barrier layer 14 is 10%. As is clear from FIG. 5, an Al composition ratio of 10% suppresses the leakage current compared to the comparative example. The higher the Al composition ratio, the larger the potential barrier can be, so by setting the Al composition ratio of the barrier layer 14 to, for example, 10% or more, the effect of suppressing the increase in leakage current can be improved.
  • Example 2 the Al composition ratio of the barrier layer 14 is 15%. As can be seen from FIG. 5, compared to Example 1, Example 2 with an Al composition ratio of 15% is able to suppress the leakage current better. Therefore, by setting the Al composition ratio of the barrier layer 14 to, for example, 15% or more, the effect of suppressing the increase in leakage current can be further improved. However, if the Al composition ratio becomes very large, there is a problem that cracks will occur in the barrier layer 14. For this reason, for example, the Al composition ratio of the barrier layer 14 may be set to, for example, 50% or less.
  • the bottom 40a of the groove 40 is flush with the interface between the current blocking layer 16 and the barrier layer 14, or is located below the interface and in the vicinity of the interface. This increases the distance between the top surface of the barrier layer 14 and the drift layer 12, where many electrons are present, and further enhances the effect of suppressing leakage current when the device is off.
  • the definition of “near the interface” is explained below. When removing the current blocking layer 16 by etching, ideally it would be stopped just at the interface with the barrier layer 14, but due to the manufacturing process, in practice the barrier layer 14 is etched slightly before stopping.
  • the “near the interface” is defined as the area from the interface between the current blocking layer 16 and the barrier layer 14 to the top surface of the barrier layer 14 that is exposed after the barrier layer 14 has been etched slightly. The specific depth is within approximately 30 nm from the interface between the current blocking layer 16 and the barrier layer 14.
  • the barrier layer 14 contains Al
  • the etch can be easily stopped at the interface between the current blocking layer 16 and the barrier layer 14. This is because, for example, when dry etching is performed with a gas containing oxygen, the etching rate of the AlGaN layer is much slower than that of the GaN layer. This is effective in stopping the etch at or near the interface between the current blocking layer 16 and the barrier layer 14 described above.
  • the nitride semiconductor device 1 can suppress the occurrence of switching problems that arise under specific operating conditions of the nitride semiconductor device, and can also suppress an increase in leakage current that occurs when the insulating film 42 is formed on the termination portion 3. Therefore, according to this embodiment, a vertical nitride semiconductor device 1 with high operational reliability and improved off characteristics can be realized.
  • the peripheral structure of the gate electrode is different from that in the first embodiment.
  • the nitride semiconductor device has a MISFET (insulated gate field effect transistor) structure with a gate insulating film.
  • MISFET insulated gate field effect transistor
  • FIG. 6 is a cross-sectional view of a nitride semiconductor device 101 according to this embodiment.
  • the nitride semiconductor device 101 differs from the nitride semiconductor device 1 shown in FIG. 1 in that it has a gate opening 120, a channel layer 121, and a gate insulating film 128 instead of the gate opening 20, the semiconductor multilayer film 21, and the threshold adjustment layer 28.
  • the channel layer 121 is an example of a fourth nitride semiconductor layer that includes a channel and at least a portion of which is disposed above the current blocking layer 16. Specifically, the channel layer 121 contacts and covers the upper surface of the current blocking layer 16.
  • the channel layer 121 is, for example, an n-type GaN layer.
  • the channel layer 121 contains a large amount of n-type impurities and has a low resistance.
  • the channel layer 121 may include multiple semiconductor films with different bandgaps, as in the first embodiment.
  • the channel layer 121 may include an AlGaN layer and a GaN layer, and may include a two-dimensional electron gas 26 generated near the AlGaN/GaN heterointerface as a channel.
  • the channel layer 121 is formed successively by crystal growth using a method such as MOVPE or HVPE, following the formation of the drift layer 12, barrier layer 14, and current blocking layer 16. Impurities may be doped into the channel layer 121 by ion implantation after crystal growth.
  • the gate opening 120 is an example of a first opening, and penetrates the channel layer 121. Specifically, the gate opening 120 penetrates the channel layer 121, the current blocking layer 16, and the barrier layer 14 to reach the drift layer 12.
  • the bottom 120a of the gate opening 120 is part of the upper surface of the drift layer 12.
  • the bottom 120a is located below the lower surface of the barrier layer 14.
  • the lower surface of the barrier layer 14 corresponds to the interface between the barrier layer 14 and the drift layer 12.
  • the bottom 120a is, for example, parallel to the first major surface 10a of the substrate 10.
  • the gate opening 120 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, the sidewall 120b of the gate opening 120 is perpendicular to the bottom 120a. In other words, the cross-sectional shape of the gate opening 120 is rectangular.
  • the gate opening 120 may be formed so that the opening area increases as it is farther from the substrate 10, similar to the gate opening 20 of the first embodiment.
  • the sidewall 120b of the gate opening 120 may be inclined obliquely.
  • the cross-sectional shape of the gate opening 120 may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid.
  • the gate insulating film 128 is disposed along the inner surface of the gate opening 120 between the inner surface of the gate opening 120 and the gate electrode 34. Specifically, the gate insulating film 128 and the gate electrode 34 are provided in this order along the inner surface of the gate opening 120. More specifically, a portion of the gate insulating film 128 is provided along the bottom 120a and sidewall 120b of the gate opening 120. The other portion of the gate insulating film 128 is provided on the upper surface of the channel layer 121. The gate insulating film 128 is in contact with the end faces of the barrier layer 14, the current blocking layer 16, and the channel layer 121 at the sidewall 120b of the gate opening 120.
  • the gate insulating film 128 is, for example, an insulating oxide film such as a silicon nitride film, a silicon oxide film, or an aluminum oxide film.
  • the gate insulating film 128 may have a single-layer structure or a multilayer structure.
  • the drift layer 12 to the channel layer 121 are continuously formed, and then the gate opening 120 is formed. That is, unlike the first embodiment, crystal regrowth is not performed. Instead of crystal regrowth, the gate opening 120 is formed, and then the gate insulating film 128 is formed.
  • the gate insulating film 128 is formed, for example, by a plasma CVD method, an ALD method, a sputtering method, or the like.
  • an inversion channel is formed in the current blocking layer 16 at the interface with the gate insulating film 128 by applying a positive voltage to the gate electrode 34. This allows the channel layer 121 and drift layer 12 to become conductive, turning on the nitride semiconductor device 101.
  • a current flows from the drain electrode 36 through the substrate 10, the drift layer 12, the interface between the current blocking layer 16 and the gate insulating film 128, and the channel layer 121 to the source electrode 32.
  • the insulating film 42 formed between the gate electrode 34 and the source wiring 44 can be a silicon nitride film formed by, for example, plasma chemical vapor deposition, rather than a highly amorphous film formed by a spin coating method or the like. This makes it possible to suppress the occurrence of switching problems that arise under specific driving conditions.
  • the termination portion 3 since the termination portion 3 has the same structure as in the first embodiment, an increase in leakage current can be suppressed even if a silicon nitride film is formed by using a plasma chemical vapor deposition method or the like as the insulating film 42.
  • the nitride semiconductor device 101 can suppress the occurrence of switching problems that arise under specific driving conditions, and can also suppress an increase in leakage current that occurs when the insulating film 42 is formed on the termination portion 3. Therefore, according to this embodiment, a vertical nitride semiconductor device 101 with high operational reliability and improved off characteristics can be realized.
  • the third embodiment differs from the first embodiment in that an undoped semiconductor layer is provided between the barrier layer and the drift layer.
  • the following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.
  • FIG. 7 is a cross-sectional view of a nitride semiconductor device 201 according to this embodiment.
  • the nitride semiconductor device 201 differs from the nitride semiconductor device 1 shown in FIG. 1 in that, in addition to the configuration thereof, it includes a current spreading layer 218.
  • the current spreading layer 218 is an example of a fifth nitride semiconductor layer that is undoped and has a smaller band gap than the barrier layer 14, and is disposed between the drift layer 12 and the barrier layer 14.
  • the gate opening 20 penetrates the current blocking layer 16, the barrier layer 14, and the current spreading layer 218.
  • the current spreading layer 218 is, for example, an undoped GaN layer.
  • the barrier layer 14 and the current spreading layer 218 form a heterointerface, and a highly mobile two-dimensional electron gas (2DEG) is formed near the heterointerface in the current spreading layer 218.
  • 2DEG highly mobile two-dimensional electron gas
  • the two-dimensional electron gas makes it easier for the current to spread laterally, so the resistance when the current flows from the drain electrode 36 to the gate opening 20 is reduced. This enables the nitride semiconductor device 201 to have a low resistance when it is on.
  • the insulating film 42 formed between the gate electrode 34 and source wiring 44 of the transistor portion 2, and the configuration of the termination portion 3 are the same as in the first embodiment. Therefore, similar to the first embodiment, it is possible to suppress the occurrence of switching problems that arise under specific driving conditions of the nitride semiconductor device 201, and also to suppress an increase in leakage current that occurs when the insulating film 42 is formed in the termination portion 3. Therefore, according to this embodiment, it is possible to realize a vertical nitride semiconductor device 201 with high operational reliability and improved off-characteristics.
  • the current spreading layer 218 may be provided in the nitride semiconductor device 101 having the MISFET structure described in the second embodiment. In this case as well, it is possible to achieve low resistance when the device is on, as described above.
  • the fourth embodiment differs from the first embodiment in that the insulating film has a multi-layer structure.
  • the following description will focus on the differences with the first embodiment, and the description of the commonalities will be omitted or simplified.
  • FIG. 8 is a cross-sectional view of a nitride semiconductor device 301 according to this embodiment. As shown in FIG. 8, the nitride semiconductor device 301 differs from the nitride semiconductor device 1 shown in FIG. 1 in that it includes an insulating film 342 instead of the insulating film 42.
  • the insulating film 342 has a layered structure of a material selected from the group consisting of, for example, SiN, SiO2 , HfO2 , Al2O3 , ZrO2 , AlN, HfON, and ZrON. Specifically, as shown in Fig. 8, the insulating film 342 has a lower insulating film 342a and an upper insulating film 342b. Here, a layered structure of two insulating films is shown, but a layered structure of three or more insulating films may also be used.
  • the lower insulating film 342a is the bottommost insulating film.
  • the lower insulating film 342a is in contact with the gate electrode 34, the threshold adjustment layer 28, and the electron supply layer 24.
  • the lower insulating film 342a is SiN.
  • the lower insulating film 342a is formed by, for example, plasma chemical vapor deposition or sputtering.
  • the upper insulating film 342b is, for example, a SiO2 film formed by a spin coating method. Alternatively, the upper insulating film 342b may be a film made of Al2O3 formed by an ALD method. The upper insulating film 342b may be an insulating film formed by a plasma enhanced chemical vapor deposition method.
  • the bottommost lower insulating film 342a by providing highly crystalline SiN created by plasma chemical vapor deposition or the like as the bottommost lower insulating film 342a, it is possible to suppress one of the issues of normal switching under specific driving conditions.
  • the insulating film 342 by forming the insulating film 342 into a layered structure, it is possible to select the optimal film for each insulating film, further improving the reliability of the device.
  • the insulating film 342 having a laminated structure may be provided in the nitride semiconductor device 101 or 201 according to the second and third embodiments.
  • the source opening 30 does not have to be provided.
  • the source electrode 32 is provided on the upper surface of the semiconductor multilayer film 21 at a position away from the threshold adjustment layer 28. Since the process of forming the source opening 30 can be omitted, the manufacturing process can be simplified.
  • the insulating film 42 or 342 may have a different configuration between the transistor portion 2 and the terminal portion 3.
  • the insulating film covering the gate electrode 34 in the transistor portion 2 and the insulating film covering the groove portion 40 in the terminal portion 3 may be formed using different materials.
  • the insulating film covering the gate electrode 34 may have a layered structure, while the insulating film covering the groove portion 40 may have a single-layer structure.
  • the insulating film covering the gate electrode 34 may have a single-layer structure, while the insulating film covering the groove portion 40 may have a layered structure.
  • the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) is gradually reduced from the substrate 10 side to the barrier layer 14 side.
  • the donor concentration may be controlled by Si, which acts as a donor, or by carbon, which acts as an acceptor that compensates for Si.
  • the drift layer 12 may have a stacked structure of multiple nitride semiconductor layers with different impurity concentrations.
  • the termination portion 3 does not have to include an end face of the nitride semiconductor device 1.
  • the termination portion 3 is a portion for isolating the transistor portion 2 from other devices.
  • Other elements may be disposed in the adjacent region of the transistor portion 2 on either side of the termination portion 3.
  • the first conductivity type may be p-type, p + type, or p - type
  • the second conductivity type may be n-type, n + type, or n - type.
  • the present disclosure can be used as a nitride semiconductor device with improved off-state characteristics and switching characteristics, and can be used in power devices such as power transistors used in inverter circuits and power supply circuits in consumer devices such as televisions, in-vehicle devices, and industrial devices.
  • Termination section 10 Substrate 10a First main surface 10b Second main surface 12 Drift layer 14 Barrier layer 16 Current blocking layer 20, 120 Gate opening 20a, 30a, 40a, 120a Bottom 20b, 30b, 40b, 120b Side wall 21 Semiconductor multilayer film 22 Electron transit layer 24 Electron supply layer 26 Two-dimensional electron gas 28 Threshold adjustment layer 30 Source opening 32 Source electrode 34 Gate electrode 36 Drain electrode 40 Groove 42, 342 Insulating film 43 Contact hole 44 Source wiring 50 Depletion layer 51 Hole 52 Electron 121 Channel layer 128 Gate insulating film 218 Current diffusion layer 342a Lower insulating film 342b Upper insulating film

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  • Junction Field-Effect Transistors (AREA)
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