WO2024114821A1 - 存储器修复方法及电路 - Google Patents

存储器修复方法及电路 Download PDF

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Publication number
WO2024114821A1
WO2024114821A1 PCT/CN2023/136219 CN2023136219W WO2024114821A1 WO 2024114821 A1 WO2024114821 A1 WO 2024114821A1 CN 2023136219 W CN2023136219 W CN 2023136219W WO 2024114821 A1 WO2024114821 A1 WO 2024114821A1
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bit
write
state
data
electrically connected
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PCT/CN2023/136219
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English (en)
French (fr)
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熊保玉
沈岙
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浙江驰拓科技有限公司
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Publication of WO2024114821A1 publication Critical patent/WO2024114821A1/zh

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  • the present disclosure relates to the field of magnetic storage technology, and in particular to a memory repair method and circuit.
  • the memory repair method and circuit provided by the present disclosure can repair storage bits with a smaller area.
  • the present disclosure provides a memory repair method, the method comprising:
  • the target bit to be read or written includes a bit in the write-destroyed state, determining a data state corresponding to the bit in the write-destroyed state;
  • writing and destroying the tailing state bits in the memory bit cells includes:
  • a write-destruction voltage higher than a write voltage is applied to the trailing-state bit to break down the trailing-state bit.
  • inverting the read and written data includes:
  • the written data is inverted and stored in the target bit, and the corresponding flag bit is set;
  • the method before writing and destroying the tailing state bits in the memory bit cells, the method further comprises:
  • the bit is determined to be the tailing state bit.
  • determining whether the target bit to be read or written has a bit in a write-destroyed state includes:
  • the resistance of the target bit is obtained, and when there is a bit whose resistance is lower than a predetermined resistance among the target bits, the bit whose resistance is lower than the predetermined resistance is determined to be the bit in the write-destroyed state.
  • the present disclosure provides a memory repair circuit, the circuit comprising:
  • a write-destroy module used for writing and destroying the tailing state bits in the memory bit
  • a judgment module used for judging whether there is a write-destroyed bit in the target bit to be read or written during the reading and writing process
  • a read/write module for determining the data state corresponding to the bit in the write-destroy state when the target bit to be read/written exists; and for inverting the read/write data when the data state corresponding to the bit in the write-destroy state is the same as the bit state of the write-destroy state; and for keeping the read/write data unchanged when the data state corresponding to the bit in the write-destroy state is different from the bit state of the write-destroy state.
  • the write-destruct module includes:
  • a first NAND gate wherein a first input end of the first NAND gate is connected to a write-destroy enable signal, a second input end of the first NAND gate is connected to a write-enable signal, and an output end of the first NAND gate controls a switch MOS tube of a write-destroy voltage source, wherein the voltage source is electrically connected to a magnetic tunnel junction and is used to write-destroy the magnetic tunnel junction;
  • a second NAND gate wherein a first input terminal of the second NAND gate is electrically connected to an output terminal of the first NAND gate
  • a first inverter wherein an output end of the first inverter is electrically connected to a second input end of the second NAND gate, and the output end of the first inverter controls a switch MOS tube of a bit source line;
  • a second inverter wherein an output end of the second inverter is electrically connected to an input end of the first inverter, an input end of the second inverter is connected to the write enable signal, and an output end of the second inverter controls a switch MOS tube connecting two ends of the magnetic tunnel junction to a common voltage source;
  • a third inverter wherein the input end of the third inverter is electrically connected to the output end of the second NAND gate, and the output end of the third inverter controls the bit line switch MOS tube of the bit element.
  • the judging module includes:
  • a reference current mirror having an array current output line, a reference current output line and a judgment current output line; the array current output line is electrically connected to the target bit, the reference current output line is electrically connected to a reference resistor, and the judgment current output line is electrically connected to the judgment resistor;
  • a first voltage amplifier wherein a first input terminal of the first voltage amplifier is electrically connected to the array current output line for receiving the divided voltage of the target bit; a second input terminal of the first voltage amplifier is electrically connected to the reference current line for receiving the divided voltage of the reference resistor; and an output terminal of the first voltage amplifier is used to output the storage data of the target bit;
  • a second voltage amplifier wherein the first input terminal of the second voltage amplifier is electrically connected to the array current output line for receiving the divided voltage of the target bit, and the second input terminal of the second voltage amplifier is electrically connected to the judgment current output line for receiving the divided voltage of the judgment resistor; the second voltage amplifier is used to output the write/destroy status of the target bit.
  • the resistance value of the reference resistor is between the high resistance value and the low resistance value of the target bit
  • the resistance value of the determination resistor is between the low resistance value and the write-destructed resistance value of the target bit.
  • the read-write module includes a reading unit, and the reading unit includes:
  • an inverter wherein an input terminal of the inverter is electrically connected to an output terminal of the first voltage amplifier
  • a buffer wherein an input terminal of the buffer is electrically connected to an output terminal of the first voltage amplifier
  • a data selector wherein a first input terminal of the data selector is electrically connected to an output terminal of the inverter, a second input terminal of the data selector is electrically connected to an output terminal of the buffer, a control terminal of the data selector is electrically connected to a readout amplifier of a flag bit, and an output terminal of the data selector is used to output a read result.
  • the read-write module includes a writing unit, and the writing unit includes:
  • a data selector wherein an output end of the data selector is electrically connected to the write driver
  • a buffer wherein an output end of the buffer is electrically connected to the first input end of the data selector, and an input end of the buffer is electrically connected to a write data source;
  • an inverter wherein an output terminal of the inverter is electrically connected to the second input terminal of the data selector, and an input terminal of the inverter is electrically connected to the write data source;
  • An AND gate wherein a first input terminal of the AND gate is electrically connected to the write data source, and a second input terminal of the AND gate is electrically connected to the second voltage amplifier;
  • An OR gate wherein the output end of the OR gate is electrically connected to the control end of the data selector, and the multiple input ends of the OR gate are electrically connected to the output ends of multiple AND gates respectively.
  • the technical solution provided by the present disclosure adopts a method of writing and destroying the tailing bit so that the tailing bit has a lower resistance, and when writing, the written data is judged whether to flip according to the corresponding relationship between the data and the corresponding bit, so that the bits in the write-destroyed state are always written with data in a low resistance state, and during the reading process, it is determined whether the read data needs to be flipped according to the set state.
  • the repair efficiency can be greatly improved, and the occupied area is extremely small, which can effectively reduce the chip cost and improve the chip yield.
  • FIG1 is a flow chart of a memory repair method according to an embodiment of the present disclosure
  • FIG2 is a schematic diagram of a memory repair circuit according to another embodiment of the present disclosure.
  • FIG3 is a schematic diagram of a write-destruct module of a memory repair circuit according to another embodiment of the present disclosure.
  • FIG4 is a schematic diagram of a memory repair circuit determination module according to another embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a memory repair circuit reading unit according to another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a memory repair circuit write unit according to another embodiment of the present disclosure.
  • the present disclosure provides a memory repair method, as shown in FIG1 , the method comprising:
  • Step 100 writing and destroying the tailing state bits in the memory bit cells
  • write destruction refers to applying a voltage higher than the normal write voltage to both ends of the magnetic tunnel junction to break down the barrier layer of the magnetic tunnel junction.
  • the write destruction state after the breakdown will become an irreversible breakdown state to distinguish between the 0 state and the 1 state of the bit, and its resistance will be much smaller than the resistance of the normal magnetic tunnel junction.
  • Step 200 during the reading and writing process, determining whether there is a bit in a write-destroyed state among the target bits to be read or written;
  • determining whether a target bit for reading or writing is in a write-destroyed state requires detecting the resistance of each bit. When it is detected that the target bit is much smaller than the normal resistance of the magnetic tunnel junction, the corresponding bit can be confirmed to be a write-destroyed bit.
  • Step 300 when there is a bit in the write-destroyed state among the target bits to be read or written, determine the data state corresponding to the bit in the write-destroyed state;
  • the write-destroyed bit when there is a write-destroyed bit in the target bit of the read or write, since the write-destroyed bit has only an extremely low resistance state, in order to prevent storage errors, when the written data corresponds to the write-destroyed bit in a high resistance state, the overall data is inverted so that the inverted data corresponds to the write-destroyed bit in a low resistance state. When reading, the read data is inverted again to obtain the original written data.
  • the write-destroyed bit can only have an extremely low resistance state, which is the same as the state of the written data, therefore, during the writing process, the data is kept unchanged for writing, and during the reading process, the data is also kept unchanged for reading.
  • Step 410 when the data state corresponding to the bit in the write-destroyed state is the same as the bit state in the write-destroyed state, the read and written data are inverted;
  • the bits in the write-destroyed state have only extremely low resistance
  • the data when writing data, if the state of the written data corresponding to the bits in the write-destroyed state is high resistance, the data can be inverted as a whole, and when reading the data, the data can be inverted again, thereby achieving accurate writing and reading of the data.
  • Step 420 When the data state corresponding to the bit in the write-destroyed state is different from the bit state in the write-destroyed state, the read and written data is kept unchanged.
  • the bits in the write-destroyed state have only extremely low resistance
  • the data when writing data, if the state of the written data corresponding to the write-destroyed state bit is low resistance, the data can be written unchanged, and when reading the data, the data can also be kept unchanged, thereby achieving accurate writing and reading of data.
  • the technical solution provided by the embodiment of the present disclosure adopts a method of writing and destroying the tailing bit so that the tailing bit has a lower resistance.
  • the written data is judged whether to flip according to the corresponding relationship between the data and the corresponding bit, so that the bits in the write-destroyed state are always written with data in a low resistance state, and in the reading process, According to the set state, it is determined whether the read data needs to be flipped. In this way, the repair efficiency can be greatly improved, and the occupied area is very small, which can effectively reduce the chip cost and improve the chip yield.
  • writing and destroying the tailing state bits in the memory bit cells includes:
  • a write-destroy voltage higher than the write voltage is applied to the tailing state bit to break down the bit.
  • a higher voltage is used to break down the barrier layer of the magnetic tunnel junction so that the magnetic tunnel junction no longer changes in resistance with the write operation.
  • the voltage used for write-destroy is at least higher than the write voltage.
  • the read and written data are inverted, including:
  • the written data is inverted and stored in the target bit, and the corresponding flag is set;
  • the bits in the write-destroy state have extremely low resistance and do not change resistance with the write operation, when reading data, the bits in the write-destroy state can only be read in a low resistance state.
  • the entire data is inverted and then written, so that the data written in the write-destroy state becomes a low resistance state.
  • the flag bit is also set so that when reading, it is known that the read data needs to be inverted.
  • an inversion indication is obtained according to the setting state of the flag bit, and the read data is inverted according to the indication.
  • the negation indication indicates that the read data needs to be negated, that is, the read data needs to be negated as a whole.
  • the method before writing and destroying the tailing state bits in the memory bit, the method further includes:
  • the flip voltage of the trailing state bit is usually higher than the flip voltage of the normal bit. Therefore, when the bit is detected, a write voltage is applied, and the bit that can be flipped normally is a normal bit, and the bit that cannot be flipped normally is a trailing state bit.
  • the bit When the bit is not flipped, the bit is determined to be a tailing state bit.
  • the bit when the bit is not flipped, it indicates that a normal write voltage cannot perform a write operation on the bit, that is, the bit is not a tailing state bit.
  • determining whether the target bit to be read or written has a bit in a write-destroyed state includes:
  • the resistance of the target bit is obtained, and when the resistance of the target bit is lower than a predetermined resistance bit, the corresponding bit is determined to be a bit in a write-destroyed state.
  • a bit in a write-destroyed state generally has a very small resistance
  • by obtaining the resistance of the target bit it is possible to determine which bit in the target bit is a write-destroyed state bit.
  • Bit refers to the bit corresponding to the data that needs to be written.
  • the target bit is multiple groups of bits, and each group will correspond to a flag bit.
  • the flag bit of each group can identify the bits in this group. In the judgment process, when there is a bit in the write-destroyed state in a group of bits, it will be set in the corresponding flag bit.
  • the present disclosure also provides a memory repair circuit, as shown in FIG2 , wherein the circuit includes:
  • a write-destroy module used for writing and destroying the tailing state bits in the memory bit
  • write destruction refers to applying a voltage higher than the normal write voltage to both ends of the magnetic tunnel junction to break down the barrier layer of the magnetic tunnel junction.
  • the write destruction state after the breakdown will become an irreversible breakdown state to distinguish between the 0 state and the 1 state of the bit, and its resistance will be much smaller than the resistance of the normal magnetic tunnel junction.
  • a judgment module used for judging whether there is a write-destroyed bit in the target bit to be read or written during the reading and writing process
  • determining whether a target bit for reading or writing is in a write-destroyed state requires detecting the resistance of each bit. When it is detected that the target bit is much smaller than the normal resistance of the magnetic tunnel junction, the corresponding bit can be confirmed to be a write-destroyed bit.
  • the read/write module is used to determine the data state corresponding to the bit in the write-destroy state when there is a bit in the write-destroy state among the target bits to be read/written; and to invert the read/write data when the data state corresponding to the bit in the write-destroy state is the same as the bit state of the write-destroy state; and to keep the read/write data unchanged when the data state corresponding to the bit in the write-destroy state is different from the bit state of the write-destroy state.
  • the write-destroyed bit when there is a write-destroyed bit in the target bit of the read or write, since the write-destroyed bit has only an extremely low resistance state, in order to prevent storage errors, when the written data corresponds to the write-destroyed bit in a high resistance state, the overall data is inverted so that the inverted data corresponds to the write-destroyed bit in a low resistance state. When reading, the read data is inverted again to obtain the original written data.
  • the write-destroyed bit can only have an extremely low resistance state, which is the same as the state of the written data, therefore, during the writing process, the data is kept unchanged for writing, and during the reading process, the data is also kept unchanged for reading. Since the bit in the write-destroyed state has only a very low resistance, when writing data, if the state of the written data corresponding to the write-destroyed state bit is high resistance,
  • the data can be inverted as a whole, and when reading the data, the data can be inverted again to achieve accurate writing and reading of the data. Since the bits in the write-destroyed state have only extremely low resistance, when writing data, if the data to be written is in the state of low resistance of the corresponding write-destroyed state bit, the data can be kept unchanged for writing, and when reading the data, the data can also be kept unchanged, so that accurate writing and reading of the data can be achieved.
  • the technical solution provided by the disclosed embodiment adopts the method of writing and destroying the tailing bit so that the tailing bit has a lower resistance, and when writing, the written data is judged whether to flip according to the corresponding relationship between the data and the corresponding bit, so that the bits in the write-destroyed state are always written with data in a low resistance state, and during the reading process, it is determined whether the read data needs to be flipped according to the set state.
  • the repair efficiency can be greatly improved, and the occupied area is extremely small, which can effectively reduce the chip cost and improve the chip yield.
  • the write-destroy module includes:
  • a first NAND gate wherein a first input end of the first NAND gate is connected to a write-destroy enable signal, a second input end of the first NAND gate is connected to a write-enable signal, and an output end of the first NAND gate controls a switch MOS tube of a write-destroy voltage source, wherein the voltage source is electrically connected to a magnetic tunnel junction and is used to write-destroy the magnetic tunnel junction;
  • a second NAND gate wherein a first input terminal of the second NAND gate is electrically connected to an output terminal of the first NAND gate
  • a first inverter wherein an output end of the first inverter is electrically connected to a second input end of the second NAND gate, and the output end of the first inverter controls a switch MOS tube of a bit source line;
  • a second inverter wherein an output end of the second inverter is electrically connected to an input end of the first inverter, an input end of the second inverter is connected to a write enable signal, and an output end of the second inverter controls a switch MOS tube connecting two ends of a magnetic tunnel junction to a common voltage source;
  • a third inverter wherein the input end of the third inverter is electrically connected to the output end of the second NAND gate, and the output end of the third inverter controls the bit line switch MOS tube of the bit element.
  • the writing and destroying module in this embodiment works as follows:
  • the write-break bit operation is performed, M1 is closed, M2 is opened, and M3 is opened. In this mode, the voltage loaded on both ends of the MTJ can break down the MTJ for a short time, realizing the write-break function.
  • the judgment module includes:
  • a reference current mirror having an array current output line, a reference current output line and a judgment current output line; the array current output line is electrically connected to the bit, the reference current output line is electrically connected to the reference resistor, and the judgment current output line is electrically connected to the judgment resistor;
  • a first voltage amplifier wherein a first input terminal of the first voltage amplifier is electrically connected to the array current output line for receiving the divided voltage of the bit; a second input terminal of the first voltage amplifier is electrically connected to the reference current line for receiving the divided voltage of the reference resistor; and an output terminal of the first voltage amplifier is used to output the stored data of the bit;
  • a second voltage amplifier wherein the first input terminal of the second voltage amplifier is electrically connected to the array current output line for receiving the divided voltage of the bit, and the second input terminal of the second voltage amplifier is electrically connected to the judgment current output line for receiving the divided voltage of the judgment resistor; the second voltage amplifier is used to output the write/destroy status of the bit.
  • the array currentInventray, the reference current Iref and the judgment current Ired are separated by the reference current mirror. Due to the current mirror effect, the three currents are almost the same at this time.
  • the branch whereInventray is located and the branch where Iref is located are connected to the voltage-type sensitive amplifier SA1, that is, the first voltage amplifier, and the branch whereaboutray and Ired are located are connected to the voltage-type sensitive amplifier SA2, that is, the second voltage amplifier, wherein the Iref branch is connected to a reference resistor with a resistance value between the MTJ RAP state and the RP state, wherein the Ired branch is connected to a judgment resistor with a resistance value between the MTJ break down and the MTJ RP state.
  • the resistance relationship is: MTJ RAP state>MTJ RP state>MTJ break down state, that is, MTJ high resistance state>MTJ low resistance state>MTJ write-destructed state. Since the resistance of each branch downstream is different, the voltage of the access point is also different. The voltage of the two points can be compared by the voltage-type sensitive amplifier. When the voltage of the access point of the branch whereInventray is located is higher than the access point of the branch where Iref is located, it means that the resistance inInventray is greater than the reference resistance and is in the RAP state. Therefore, the read data is 1.
  • SA2 can output the comparison result between the array resistance and the judgment bit reference resistance. If the array resistance is greater than the judgment resistance, it means that this unit is a normal unit, and the output is 1. After the inverter, the judgment bit is 0.
  • the array resistance is less than the judgment resistance, it means that this bit is in the break down state and the output is 0. After the inverter, the judgment bit is 1.
  • the advantage of using a voltage amplifier is that it can compare and output two results at the same time.
  • the resistance of the reference resistor is between the high resistance and low resistance of the bit
  • the resistance of the determination resistor is between the low resistance and write-destructed resistance of the bit.
  • the read-write module includes a reading unit, and the reading unit includes:
  • an inverter wherein an input terminal of the inverter is electrically connected to an output terminal of the first voltage amplifier
  • a buffer wherein an input terminal of the buffer is electrically connected to an output terminal of the first voltage amplifier
  • a data selector wherein a first input terminal of the data selector is electrically connected to an output terminal of the inverter, a second input terminal of the data selector is electrically connected to an output terminal of the buffer, a control terminal of the data selector is electrically connected to a readout amplifier of a flag bit, and an output terminal of the data selector is used to output a read result.
  • the read flag result is used to select the read data. If the flag is high, the inverter branch output is selected and the output data is inverted. If the flag is low, the buffer branch output is selected.
  • the read-write module includes a write unit, and the write unit includes:
  • a data selector wherein an output end of the data selector is electrically connected to the write driver
  • a buffer wherein an output end of the buffer is electrically connected to the first input end of the data selector, and an input end of the buffer is electrically connected to a write data source;
  • an inverter wherein an output terminal of the inverter is electrically connected to the second input terminal of the data selector, and an input terminal of the inverter is electrically connected to a write data source;
  • An AND gate wherein a first input terminal of the AND gate is electrically connected to the write data source, and a second input terminal of the AND gate is electrically connected to a second voltage amplifier;
  • An OR gate wherein the output end of the OR gate is electrically connected to the control end of the data selector, and the multiple input ends of the OR gate are electrically connected to the output ends of the multiple AND gates respectively.
  • the read judgment result is used to select the data to be written. If the bits in the group are all normal bits, the buffer branch data is selected for writing, and the flag bit in the group is written as 0. If there is a write-destroyed bit in the group, and the write data corresponding to the write-destroyed bit is 0, the buffer branch data is still selected for writing, and the flag bit in the group is written as 0. If there is a write-destroyed bit in the group, and the write data corresponding to the write-destroyed bit is 1, the write data of this group is inverted and written, and the flag bit is written as 1. The reason is that the punctured bit can only read 0. When the write data is 1, it is inverted when writing and inverted again when reading, so that the write and read data of the bad bit are always 0, thereby achieving the purpose of repair.
  • the write-destroyed state bits are judged each time reading and writing, and the chip can be repaired continuously. Furthermore, the tailing state bits of the chip can be judged after a predetermined time interval or a predetermined number of reading and writing times, so as to better perform continuous repair.
  • the read judgment bit operation is performed first.
  • the judgment bit read out of a normal bit is 0, and the judgment bit read out of a destroyed or damaged bit is 1.
  • the read operation needs to read out all the data including the Flag, and output according to the situation of the Flag in the group, corresponding to the inverted write situation.
  • the read Flag 1, then the read data needs to be inverted before output.
  • the actual output data is consistent with the written data, completing the repair function.
  • the output is as follows:

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Abstract

本公开提供一种存储器修复方法，该方法包括：对存储器位元中的拖尾态位元进行写毁；在读写过程中，判断读写的目标位元是否存在写毁态的位元；当读写的所述目标位元存在所述写毁态的位元时，判断所述写毁态的位元对应的数据状态；当写毁态的位元对应的数据状态与写毁态的位元状态相同时，对读写的数据进行取反；当写毁态的位元对应的数据状态与写毁态的位元状态不同时，保持读写的数据不变。本公开还提供了一种存储器修复电路。本公开提供的存储器修复方法及电路，能够以较小的面积实现对存储位元的修复。

Description

存储器修复方法及电路
相关申请的交叉引用
本公开要求于2022年12月02日提交中国专利局，申请号为202211554276.5，申请名称为“存储器修复方法及电路”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及磁存储技术领域，尤其涉及一种存储器修复方法及电路。
背景技术
当现有MRAM制作工艺不够成熟的条件下，阵列的制作会形成很多有问题的单元，有些拖尾位元难以翻转，失去了MRAM的特征，有些单元在正常读写的过程中损坏，导致无法使用。这些单元严重影响阵列的良率，要想使用存在问题的阵列，必须将这些有问题的单元处理或者替换为能正常读写的单元。所以产生许多的修复方法，常用的方法有使用行列的冗余单元进行修复，或者使用ECC进行算法上的修复。
在目前的阵列结构中，采用冗余修复，每次只能替换整行或者整列，由于可能待修复的只有几个单元，但是要用一整行一千多个单元来做替换，对于修复来说有些浪费。且修复能力较弱，只能实现较小范围的修复。若用1位ECC进行修复，修复能力不够，若用两位ECC进行修复，则会占用很大面积，造成成本升高等问题。
发明内容
本公开提供的存储器修复方法及电路，能够以较小的面积实现对存储位元的修复。
第一方面，本公开提供一种存储器修复方法，所述方法包括：
对存储器位元中的拖尾态位元进行写毁；
在读写过程中，判断读写的目标位元是否存在写毁态的位元；
当读写的所述目标位元存在所述写毁态的位元时，判断所述写毁态的位元对应的数据状态；
当所述写毁态的位元对应的所述数据状态与写毁态的位元状态相同时，对读写的数据进行取反；
当所述写毁态的位元对应的所述数据状态与所述写毁态的位元状态不同时，保持所述读写的数据不变。
可选地，对存储器位元中的拖尾态位元进行写毁包括：
对所述拖尾态位元施加高于写入电压的写毁电压，以击穿所述拖尾态位元。
可选地，当所述写毁态的位元对应的所述数据状态与写毁态的所述位元状态相同时，对读写的数据进行取反，包括：
在写入数据时，对写入的数据进行取反后存储至所述目标位元，并对对应的标志位进行置位；
在读出数据时，依据所述标志位的置位状态获取取反指示，并依据所述取反指示对读出的数据进行取反。
可选地，在对存储器位元中的拖尾态位元进行写毁之前，所述方法还包括：
对所述存储器的各位元施加写电压，并获取所述存储器中各位元的翻转结果；
当所述位元发生翻转时，确定所述位元为正常位元；
当所述位元未发生翻转时，确定所述位元为所述拖尾态位元。
可选地，在读写过程中，判断读写的目标位元是否存在写毁态的位元，包括：
获取所述目标位元的电阻，当目标位元存在电阻低于预定电阻的位元时，确定电阻低于所述预定电阻的所述位元为所述写毁态的位元。
第二方面，本公开提供一种存储器修复电路，所述电路包括：
写毁模块，用于对存储器位元中的拖尾态位元进行写毁；
判断模块，用于在读写过程中，判断读写的目标位元是否存在写毁态的位元；
读写模块，用于当读写的所述目标位元存在所述写毁态的位元时，判断所述写毁态的位元对应的数据状态；并在所述写毁态的位元对应的所述数据状态与所述写毁态的位元状态相同时，对读写的数据进行取反；在所述写毁态的位元对应的所述数据状态与所述写毁态的位元状态不同时，保持所述读写的数据不变。
可选地，所述写毁模块包括：
第一与非门，所述第一与非门的第一输入端与写毁使能信号连接，所述第一与非门的第二输入端与写使能信号连接，所述第一与非门的输出端控制写毁电压源的开关MOS管，所述电压源与磁隧道结电连接，用于将所述磁隧道结写毁；
第二与非门，所述第二与非门的第一输入端与所述第一与非门的输出端电连接；
第一反相器，所述第一反相器的输出端与所述第二与非门的第二输入端电连接，所述第一反相器的输出端控制位元源线的开关MOS管；
第二反相器，所述第二反相器的输出端与所述第一反相器的输入端电连接，所述第二反相器的输入端与所述写使能信号连接，所述第二反相器的输出端控制所述磁隧道结两端与公共电压源连接的开关MOS管；
第三反相器，所述第三反相器的输入端与所述第二与非门的输出端电连接，所述第三反相器的输出端控制位元的位线开关MOS管。
可选地，所述判断模块包括：
基准电流镜，所述基准电流镜具有阵列电流输出线、参考电流输出线和判断电流输出线；所述阵列电流输出线与所述目标位元电连接，所述参考电流输出线与参考电阻电连接，所述判断电流输出线与判断电阻电连接；
第一电压放大器，所述第一电压放大器的第一输入端与所述阵列电流输出线电连接，用于接收所述目标位元的分压；所述第一电压放大器第二输入端与参考电流线电连接，用于接收所述参考电阻的分压；所述第一电压放大器的输出端用于输出所述目标位元的存储数据；
第二电压放大器，所述第二电压放大器的第一输入端与所述阵列电流输出线电连接，用于接收所述目标位元的分压，所述第二电压放大器的第二输入端与所述判断电流输出线电连接，用于接收所述判断电阻的分压；所述第二电压放大器用于输出所述目标位元的写毁状态。
可选地，所述参考电阻的阻值介于所述目标位元的高阻态阻值与低阻态阻值之间，所述判断电阻的阻值介于所述目标位元的所述低阻态阻值与写毁态阻值之间。
可选地，所述读写模块包括读取单元，所述读取单元包括：
反相器，所述反相器的输入端与所述第一电压放大器的输出端电连接；
缓冲器，所述缓冲器的输入端与所述第一电压放大器的输出端电连接；
数据选择器，所述数据选择器的第一输入端与所述反相器的输出端电连接，所述数据选择器的第二输入端与所述缓冲器的输出端电连接，所述数据选择器的控制端与标志位的读出放大器电连接，所述数据选择器的输出端用于输出读取结果。
可选地，所述读写模块包括写入单元，所述写入单元包括：
数据选择器，所述数据选择器的输出端与写驱动器电连接；
缓冲器，所述缓冲器的输出端与所述数据选择器的第一输入端电连接，所述缓冲器的输入端与写入数据源电连接；
反相器，所述反相器的输出端与所述数据选择器的第二输入端电连接，所述反相器的输入端与所述写入数据源电连接；
与门，所述与门的第一输入端与所述写入数据源电连接，所述与门的第二输入端与所述第二电压放大器电连接；
或门，所述或门的输出端与所述数据选择器的控制端电连接，所述或门的多个输入端分别与多个与门的输出端电连接。
本公开提供的技术方案，采用将拖尾位元写毁的方式，使拖尾位元具备较低的电阻，并在写入时，依据数据与对应位元的对应关系，对写入的数据进行是否翻转的判断，使写毁态的位元是始终写入的都是低电阻状态的数据，并在读出过程中，依据置位状态，确定读出的数据是否需要翻转。这种方式下，能够大大的提高修复效率，并且，占用的面积极小，可以有效的极低芯片成本，提高芯片良率。
附图说明
图1为本公开一实施例存储器修复方法的流程图；
图2为本公开另一实施例存储器修复电路的示意图；
图3为本公开另一实施例存储器修复电路写毁模块的示意图；
图4为本公开另一实施例存储器修复电路判断模块的示意图；
图5为本公开另一实施例存储器修复电路读取单元的示意图；
图6为本公开另一实施例存储器修复电路写入单元的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种存储器修复方法，如图1所示，所述方法包括：
步骤100，对存储器位元中的拖尾态位元进行写毁；
在一些实施例中，写毁是指采用高于正常写电压的电压值施加在磁隧道结的两端，使磁隧道结的势垒层被击穿，击穿之后的写毁态将变成不可逆的击穿态以区别位元的0态与1态，其电阻将远小于正常磁隧道结的电阻。
步骤200，在读写过程中，判断读写的目标位元是否存在写毁态的位元；
在一些实施例中，判断读写的目标位元是否存在写毁态的位元需要对每个位元的电阻进行检测，当检测到其中的目标位元远小于磁隧道结的正常电阻时，即可确认对应的位元为写毁态的位元。
步骤300，当读写的目标位元存在写毁态的位元时，判断写毁态的位元对应的数据状态；
在一些实施例中，当读写的目标位元存在写毁态的位元时，由于写毁态的位元只有极低的电阻状态，为了使得存储不会出现错误，当写入的数据对应写毁态的位元为高阻态时，将整体数据进行取反，使取反后的数据对应写毁态的位元为低阻态，在读取时，将读取的数据再次进行取反，即可得到原始的写入数据。当写入的数据对应写毁位元为低阻态时，由于写毁位元只能具有极低的阻态，与写入的数据状态相同，因此，在写入过程中，保持数据不变进行写入，在读出时，也保持数据不变进行读出。
步骤410，当写毁态的位元对应的数据状态与写毁态的位元状态相同时，对读写的数据进行取反；
在一些实施例中，由于写毁态的位元仅具有极低的电阻，因此，当写入数据时，如果写入的数据在对应写毁态位元的状态为高电阻时，可以对数据整体进行取反，在读出数据时，对数据再次进行取反，即可实现数据的准确写入和读出。
步骤420，当写毁态的位元对应的数据状态与写毁态的位元状态不同时，保持读写的数据不变。
在一些实施例中，由于写毁态的位元仅具有极低的电阻，因此，当写入数据时，如果写入的数据在对应写毁态位元的状态为低电阻时，可以保持数据不变进行写入，在读出数据时，也保持数据不变，即可实现数据的准确写入和读出。
本公开实施例提供的技术方案，采用将拖尾位元写毁的方式，使拖尾位元具备较低的电阻，并在写入时，依据数据与对应位元的对应关系，对写入的数据进行是否翻转的判断，使写毁态的位元是始终写入的都是低电阻状态的数据，并在读出过程中， 依据置位状态，确定读出的数据是否需要翻转。这种方式下，能够大大的提高修复效率，并且，占用的面积极小，可以有效的极低芯片成本，提高芯片良率。
作为一种可选的实施方式，对存储器位元中的拖尾态位元进行写毁包括：
对拖尾态位元施加高于写入电压的写毁电压，以击穿所述位元。
在一些实施例中，在对拖尾态位元进行写毁操作时，以较高的电压击穿磁隧道结的势垒层，使磁隧道结不在随着写操作发生阻值变化。写毁时所用的电压至少要高于写入电压。
作为一种可选的实施方式，当写毁态的位元对应的数据状态与写毁态的位元状态相同时，对读写的数据进行取反，包括：
在写入数据时，对写入的数据进行取反后存储至目标位元，并对对应的标志进行置位；
在一些实施例中，由于写毁态的位元具有极低的电阻，且不随写操作发生阻值变化，因此，在读取数据时，写毁态的位元只能读取到低阻态的状态。为了准确的存储数据，当写入数据在对应写毁态的数据为高阻值状态时，对整体数据进行取反再写入，从而，使写毁态写入的数据变为低阻态。在写入时，还会对标志位进行置位，以便在读取时获知读出的数据需要取反。
在读出数据时，依据标志位的置位状态获取取反指示，并依据指示对读出的数据进行取反。
在一些实施例中，对于写毁态位元存储高阻值数据时，取反指示表示出了读出的数据需要取反，即，读出的数据需要整体进行取反。
作为一种可选的实施方式，对存储器位元中的拖尾态位元进行写毁之前，还包括：
对存储器的各位元施加写电压，并获取各位元的翻转结果；
在一些实施例中，拖尾态位元的翻转电压通常会高于正常位元的翻转电压，因此，在对位元进行检测时，施加写电压，能够正常发生翻转的位元即为正常位元，不能正常发生翻转的位元即为拖尾态位元。
当位元发生翻转时，确定所述位元为正常位元；
在一些实施例中，当位元发生翻转时，表明正常的写电压能够对位元进行写操作，即，该位元为正常位元。
当位元未发生翻转时，确定所述位元为拖尾态位元。
在一些实施例中，当位元未发生翻转时，表明正常的写电压不能对位元进行写操作，即，该位元未拖尾态位元。
作为一种可选地额实施方式，在读写过程中，判断读写的目标位元是否存在写毁态的位元，包括：
获取目标位元的电阻，当目标位元存在电阻低于预定电阻位元时，确定对应位元为写毁态的位元。
在一些实施例中，由于写毁态的位元通常具有极小的电阻，因此，采用获取目标位元电阻的方式，能够确定目标位元中的哪个位元为写毁态位元。目标
位元是指当前需要写入的数据所对应的位元，通常情况下目标位元为多组位元，每个组将对应一个标志位。每个组的标志位可以对本组的位元进行标识。在判断的过程中，当一组位元中具有写毁态的位元时，将在对应的标志位中进行置位标识。
本公开实施例还提供一种存储器修复电路，如图2所示，所述电路包括：
写毁模块，用于对存储器位元中的拖尾态位元进行写毁；
在一些实施例中，写毁是指采用高于正常写电压的电压值施加在磁隧道结的两端，使磁隧道结的势垒层被击穿，击穿之后的写毁态将变成不可逆的击穿态以区别位元的0态与1态，其电阻将远小于正常磁隧道结的电阻。
判断模块，用于在读写过程中，判断读写的目标位元是否存在写毁态的位元；
在一些实施例中，判断读写的目标位元是否存在写毁态的位元需要对每个位元的电阻进行检测，当检测到其中的目标位元远小于磁隧道结的正常电阻时，即可确认对应的位元为写毁态的位元。
读写模块，用于当读写的目标位元存在写毁态的位元时，判断写毁态的位元对应的数据状态；并在写毁态的位元对应的数据状态与写毁态的位元状态相同时，对读写的数据进行取反；在写毁态的位元对应的数据状态与写毁态的位元状态不同时，保持读写的数据不变。
在一些实施例中，当读写的目标位元存在写毁态的位元时，由于写毁态的位元只有极低的电阻状态，为了使得存储不会出现错误，当写入的数据对应写毁态的位元为高阻态时，将整体数据进行取反，使取反后的数据对应写毁态的位元为低阻态，在读取时，将读取的数据再次进行取反，即可得到原始的写入数据。当写入的数据对应写毁位元为低阻态时，由于写毁位元只能具有极低的阻态，与写入的数据状态相同，因此，在写入过程中，保持数据不变进行写入，在读出时，也保持数据不变进行读出。 由于写毁态的位元仅具有极低的电阻，因此，当写入数据时，如果写入的数据在对应写毁态位元的状态为高电阻时，
可以对数据整体进行取反，在读出数据时，对数据再次进行取反，即可实现数据的准确写入和读出。由于写毁态的位元仅具有极低的电阻，因此，当写入数据时，如果写入的数据在对应写毁态位元的状态为低电阻时，可以保持数据不变进行写入，在读出数据时，也保持数据不变，即可实现数据的准确写入和读出。
本公开实施例提供的技术方案，采用将拖尾位元写毁的方式，使拖尾位元具备较低的电阻，并在写入时，依据数据与对应位元的对应关系，对写入的数据进行是否翻转的判断，使写毁态的位元是始终写入的都是低电阻状态的数据，并在读出过程中，依据置位状态，确定读出的数据是否需要翻转。这种方式下，能够大大的提高修复效率，并且，占用的面积极小，可以有效的极低芯片成本，提高芯片良率。
作为一种可选的实施方式，如图3所示，所述写毁模块包括：
第一与非门，所述第一与非门的第一输入端与写毁使能信号连接，所述第一与非门的第二输入端与写使能信号连接，所述第一与非门的输出端控制写毁电压源的开关MOS管，所述电压源与磁隧道结电连接，用于将所述磁隧道结写毁；
第二与非门，所述第二与非门的第一输入端与第一与非门的输出端电连接；
第一反相器，所述第一反相器的输出端与所述第二与非门的第二输入端电连接，所述第一反相器的输出端控制位元源线的开关MOS管；
第二反相器，所述第二反相器的输出端与所述第一反相器的输入端电连接，所述第二反相器的输入端与写使能信号连接，所述第二反相器的输出端控制磁隧道结两端与公共电压源连接的开关MOS管；
第三反相器，所述第三反相器的输入端与第二与非门的输出端电连接，所述第三反相器的输出端控制位元的位线开关MOS管。
在一些实施例中，本实施方式中的写毁模块工作过程如下：
当write enable和TM_BREAK_Enable信号都为低，此时不进行操作，此位未被选择。M1关闭，M2关，M3关。
当write enable信号为高，TM_BREAK_Enable信号低时，此时进行normal读写操作，M1打开，M2打开，M3关闭。
当write enable信号为高，TM_BREAK_Enable信号也为高时，此时进行写毁bit操作，M1关闭，M2打开，M3打开。此模式下加载在MTJ两端的电压可以将MTJ短时击穿，实现写毁功能。
作为一种可选的实施方式，如图4所示，所述判断模块包括：
基准电流镜，所述基准电流镜具有阵列电流输出线、参考电流输出线和判断电流输出线；所述阵列电流输出线与所述位元电连接，所述参考电流输出线与参考电阻电连接，所述判断电流输出线与判断电阻电连接；
第一电压放大器，所述第一电压放大器的第一输入端与阵列电流输出线电连接，用于接收所述位元的分压；所述第一电压放大器第二输入端与参考电流线电连接，用于接收所述参考电阻的分压；所述第一电压放大器的输出端用于输出所述位元的存储数据；
第二电压放大器，所述第二电压放大器的第一输入端与阵列电流输出线电连接，用于接收所述位元的分压，所述第二电压放大器第二输入端与判断电流输出线电连接，用于接收所述判断电阻的分压；所述第二电压放大器用于输出所述位元的写毁状态。
在本实施方式中，采用两个电压型放大器以及电流镜结构，通过基准电流镜分出阵列电流Iarray，参考电流Iref以及判断电流Ired，由于电流镜作用，此时三个电流几乎相同，将Iarray所在支路和Iref所在支路接入电压型灵敏放大器SA1，即第一电压放大器，将Iarray和Ired所在支路接入电压型灵敏放大器SA2，即第二电压放大器，其中Iref支路接一个阻值介于MTJ RAP态和RP态之间的参考电阻，其中Ired支路接一个阻值介于MTJ break down和MTJ RP态的判断电阻。电阻关系为：MTJ RAP态＞MTJ RP态＞MTJ break down态，即MTJ高阻值态＞MTJ低阻值态＞MTJ写毁态。由于各支路下游的电阻不同，接入点的电压也不同，通过电压型灵敏放大器可比较两点电压，当Iarray所在支路接入点电压高于Iref所在支路接入点时，说明Iarray中的电阻大于参考电阻，为RAP态。所以读出数据为1，当Iarray所在支路接入点电压低于Iref所在支路接入点时，说明Iarray中的电阻小于参考电阻，为RP态。所以读出数据为0。同理，SA2可输出阵列电阻与判断位参考电阻的比较结果，若阵列电阻大于判断电阻，则说明此单元为正常单元，输出为1，经过反相器得到判断位为0。
若阵列电阻小于判断电阻，则说明此位元为break down态，输出为0。经过反相器得到判断位为1。采用电压型放大器的优点为可以同时进行比较，输出两个结果。当SA1＝1，SA2＝1，阵列位元为rap态，当SA1＝0，SA2＝1，阵列位元为rp态，当SA1＝0，SA2＝0，阵列位元为break down态。不存在SA1＝1，SA2＝0这种情况。
作为一种可选的实施方式，所述参考电阻的阻值介于所述位元的高阻态阻值与低阻态阻值之间，所述判断电阻的阻值介于所述位元的低阻态阻值与写毁态阻值之间。
作为一种可选的实施方式，如图5所示，所述读写模块包括读取单元，所述读取单元包括：
反相器，所述反相器的输入端与第一电压放大器的输出端电连接；
缓冲器，所述缓冲器的输入端与第一电压放大器的输出端电连接；
数据选择器，所述数据选择器的第一输入端与所述反相器的输出端电连接，所述数据选择器的第二输入端与所述缓冲器的输出端电连接，所述数据选择器的控制端与标志位的读出放大器电连接，所述数据选择器的输出端用于输出读取结果。
在本实施方式中，用读出的标志位结果对读出的数据进行选择，若标志位为高，则选择反相器支路输出，将输出的数据取反，若标志位为低，则选择buffer支路输出。
作为一种可选的实施方式，如图6所示，所述读写模块包括写入单元，所述写入单元包括：
数据选择器，所述数据选择器的输出端与写驱动器电连接；
缓冲器，所述缓冲器的输出端与所述数据选择器的第一输入端电连接，所述缓冲器的输入端与写入数据源电连接；
反相器，所述反相器的输出端与所述数据选择器的第二输入端电连接，所述反相器的输入端与写入数据源电连接；
与门，所述与门的第一输入端与所述写入数据源电连接，所述与门的第二输入端与第二电压放大器电连接；
或门，所述或门的输出端与所述数据选择器的控制端电连接，或门的多个输入端分别与多个与门的输出端电连接。
本实施方式中，用读出的判断果对写入的数据进行选择，如果组内的位元都是正常位元，则选择buffer支路数据写入，将组内标志位写0。如果组内存在写毁态位元，且写毁态位元对应的写入数据为0，则还是选择buffer支路数据写入，将组内标志位写0。如果组内存在写毁态位元，且写毁态位元对应的写入数据为1，则将本组的写入数据都取反写入，且将标志位写1。原因是被击穿的位元只能读出0，当写入数据为1时，通过写入时取反，读出时再取反，使得坏位元的写入与读出数据始终为0，以此达到修复的目的。
在本实施方式中，通过上述的各电路、模块以及单元之间的配合，每次读写都进行写毁态位元的判断，可以持续进行芯片的修复。进一步地，可以在预定的时间间隔或者预定读写次数间隔后，对芯片进行拖尾态位元的判断，以便更好的进行持续修复。
如下提供了一种具体的示例性写入过程：
当进行写操作时，先进行读判断位操作，正常的位元读出的判断位为0，写毁或损坏的位元读出的判断位为1。例如下表中的情形：
由于DATA2的值为1，表明Data2位元为写毁态位元，所以读出的判断结果中，Data2对应的判断结果为高。此时需要对比写入Data2的数据，如此时待写入数据为1010，Data2对应的写入数据为1。根据逻辑电路，当判断位为高，且写入对应位元的数据为高时，将此组的写入数据取反，并将Flag置为1写入。其写入情况如下：
若当判断结果为高，写入对应位元的数据为低时，或者组内判断位都为低时，则FLAG＝0，直接将数据写入，写入情况如下：
如下提供了一种具体的示例性读出过程：
读操作需要将包含Flag在内的数据都读取出来，根据组内Flag的情况进行输出，对应取反写入情况，此时读出的Flag＝1，则需要将读出的数据取反后再输出，实际输出数据与写入数据一致，完成修复功能。输出情况如下：

当Flag＝0时，则直接将数据输出。
上述的示例性过程中，假定每4个位元配置一个标志位，为一个数据组，本领域技术人员应当能够理解，位元与标志位的数量可以定位任意位数，本实施例仅作为示范。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应该以权利要求的保护范围为准。

Claims (11)

  1. 一种存储器修复方法，其中，所述方法包括：
    对存储器位元中的拖尾态位元进行写毁；
    在读写过程中，判断读写的目标位元是否存在写毁态的位元；
    当读写的所述目标位元存在所述写毁态的位元时，判断所述写毁态的位元对应的数据状态；
    当所述写毁态的位元对应的所述数据状态与写毁态的位元状态相同时，对读写的数据进行取反；
    当所述写毁态的位元对应的所述数据状态与所述写毁态的位元状态不同时，保持所述读写的数据不变。
  2. 根据权利要求1所述的方法，其中，对存储器位元中的拖尾态位元进行写毁包括：
    对所述拖尾态位元施加高于写入电压的写毁电压，以击穿所述拖尾态位元。
  3. 根据权利要求1所述的方法，其中，当所述写毁态的位元对应的所述数据状态与写毁态的位元状态相同时，对读写的数据进行取反，包括：
    在写入数据时，对写入的数据进行取反后存储至所述目标位元，并对对应的标志位进行置位；
    在读出数据时，依据所述标志位的置位状态获取取反指示，并依据所述取反指示对读出的数据进行取反。
  4. 根据权利要求1所述的方法，其中，在对存储器位元中的拖尾态位元进行写毁之前，所述方法还包括：
    对所述存储器的各位元施加写电压，并获取所述存储器中各位元的翻转结果；
    当所述位元发生翻转时，确定所述位元为正常位元；
    当所述位元未发生翻转时，确定所述位元为所述拖尾态位元。
  5. 根据权利要求1所述的方法，其中，在读写过程中，判断读写的目标位元是否存在写毁态的位元，包括：
    获取所述目标位元的电阻，当目标位元存在电阻低于预定电阻的位元时，确定电阻低于所述预定电阻的所述位元为所述写毁态的位元。
  6. 一种存储器修复电路，其中，所述电路包括：
    写毁模块，用于对存储器位元中的拖尾态位元进行写毁；
    判断模块，用于在读写过程中，判断读写的目标位元是否存在写毁态的位元；
    读写模块，用于当读写的所述目标位元存在所述写毁态的位元时，判断所述写毁态的位元对应的数据状态；并在所述写毁态的位元对应的所述数据状态与写毁态的位元状态相同时，对读写的数据进行取反；在所述写毁态的位元对应的所述数据状态与所述写毁态的位元状态不同时，保持所述读写的数据不变。
  7. 根据权利要求6所述的存储器修复电路，其中，所述写毁模块包括：
    第一与非门，所述第一与非门的第一输入端与写毁使能信号连接，所述第一与非门的第二输入端与写使能信号连接，所述第一与非门的输出端控制写毁电压源的开关MOS管，所述电压源与磁隧道结电连接，用于将所述磁隧道结写毁；
    第二与非门，所述第二与非门的第一输入端与所述第一与非门的输出端电连接；
    第一反相器，所述第一反相器的输出端与所述第二与非门的第二输入端电连接，所述第一反相器的输出端控制位元源线的开关MOS管；
    第二反相器，所述第二反相器的输出端与所述第一反相器的输入端电连接，所述第二反相器的输入端与所述写使能信号连接，所述第二反相器的输出端控制所述磁隧道结两端与公共电压源连接的开关MOS管；
    第三反相器，所述第三反相器的输入端与所述第二与非门的输出端电连接，所述第三反相器的输出端控制位元的位线开关MOS管。
  8. 根据权利要求6所述的存储器修复电路，其中，所述判断模块包括：
    基准电流镜，所述基准电流镜具有阵列电流输出线、参考电流输出线和判断电流输出线；所述阵列电流输出线与所述目标位元电连接，所述参考电流输出线与参考电阻电连接，所述判断电流输出线与判断电阻电连接；
    第一电压放大器，所述第一电压放大器的第一输入端与所述阵列电流输出线电连接，用于接收所述目标位元的分压；所述第一电压放大器第二输入端与参考电流线电连接，用于接收所述参考电阻的分压；所述第一电压放大器的输出端用于输出所述目标位元的存储数据；
    第二电压放大器，所述第二电压放大器的第一输入端与所述阵列电流输出线电连接，用于接收所述目标位元的分压，所述第二电压放大器的第二输入端与所述判断电流输出线电连接，用于接收所述判断电阻的分压；所述第二电压放大器用于输出所述目标位元的写毁状态。
  9. 根据权利要求8所述的存储器修复电路，其中，所述参考电阻的阻值介于所述目标位元的高阻态阻值与低阻态阻值之间，所述判断电阻的阻值介于所述目标位元的所述低阻态阻值与写毁态阻值之间。
  10. 根据权利要求8所述的存储器修复电路，其中，所述读写模块包括读取单元，所述读取单元包括：
    反相器，所述反相器的输入端与所述第一电压放大器的输出端电连接；
    缓冲器，所述缓冲器的输入端与所述第一电压放大器的输出端电连接；
    数据选择器，所述数据选择器的第一输入端与所述反相器的输出端电连接，所述数据选择器的第二输入端与所述缓冲器的输出端电连接，所述数据选择器的控制端与标志位的读出放大器电连接，所述数据选择器的输出端用于输出读取结果。
  11. 根据权利要求8所述的存储器修复电路，其中，所述读写模块包括写入单元，所述写入单元包括：
    数据选择器，所述数据选择器的输出端与写驱动器电连接；
    缓冲器，所述缓冲器的输出端与所述数据选择器的第一输入端电连接，所述缓冲器的输入端与写入数据源电连接；
    反相器，所述反相器的输出端与所述数据选择器的第二输入端电连接，所述反相器的输入端与所述写入数据源电连接；
    与门，所述与门的第一输入端与所述写入数据源电连接，所述与门的第二输入端与所述第二电压放大器电连接；
    或门，所述或门的输出端与所述数据选择器的控制端电连接，所述或门的多个输入端分别与多个与门的输出端电连接。
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