WO2024114031A1 - 一种背接触电池及其制造方法、光伏组件 - Google Patents

一种背接触电池及其制造方法、光伏组件 Download PDF

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WO2024114031A1
WO2024114031A1 PCT/CN2023/118062 CN2023118062W WO2024114031A1 WO 2024114031 A1 WO2024114031 A1 WO 2024114031A1 CN 2023118062 W CN2023118062 W CN 2023118062W WO 2024114031 A1 WO2024114031 A1 WO 2024114031A1
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layer
doped semiconductor
passivation
semiconductor layer
doped
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PCT/CN2023/118062
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English (en)
French (fr)
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张东威
吴帅
李云朋
叶枫
方亮
徐希翔
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隆基绿能科技股份有限公司
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Publication of WO2024114031A1 publication Critical patent/WO2024114031A1/zh

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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure relates to the technical field of solar cells, and in particular to a back-contact cell and a manufacturing method thereof, and a photovoltaic module.
  • Passivated back-contact solar cells refer to solar cells with a passivated contact structure in which both the positive and negative electrodes are located on the back of the cell, with no metal electrode blocking the front. Passivated back-contact solar cells have a large light absorption area and a low carrier recombination rate, which has attracted extensive attention from the photovoltaic academic and industrial communities and has become a hot development direction for high-efficiency solar cell technology.
  • the purpose of the present disclosure is to provide a back-contact cell and a method for manufacturing the same, as well as a photovoltaic module, for simultaneously preventing leakage at the lateral interface and the longitudinal interface between the first doped semiconductor layer and the second doped semiconductor layer, thereby improving the photoelectric conversion efficiency of the back-contact cell.
  • the present disclosure provides a back-contact cell, the back-contact cell comprising: a silicon substrate, a first passivation layer and a first doped semiconductor layer sequentially stacked on a backlight surface of the silicon substrate along a thickness direction of the silicon substrate; a second passivation layer and a second doped semiconductor layer sequentially stacked on the backlight surface along a thickness direction of the silicon substrate.
  • the conductor layer covers a portion of the first passivation layer and the first doped semiconductor layer, and the second doped semiconductor layer has an opposite conductivity type to the first doped semiconductor layer.
  • An insulating layer is arranged on the backlight surface. The insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer from the first doped semiconductor layer.
  • the first passivation layer and the first doped semiconductor layer are sequentially stacked on the backlight surface along the thickness direction of the silicon substrate.
  • the passivation contact structure formed by the first passivation layer and the first doped semiconductor layer can achieve excellent interface passivation and carrier selective collection, which is beneficial to improve the photoelectric conversion efficiency of the back contact battery.
  • the passivation contact structure formed by the second passivation layer and the second doped semiconductor layer also has the beneficial effects of the above-mentioned first passivation layer and the first doped semiconductor layer, which will not be repeated here.
  • the stacked second passivation layer and the second doped semiconductor layer cover the stacked first passivation layer and the partial area of the first doped semiconductor layer.
  • the back contact battery provided by the present disclosure also includes an insulating layer arranged on the backlight surface. The insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer from the first doped semiconductor layer. It can be understood that the insulating layer can not only separate the second passivation layer and the first doped semiconductor layer along the thickness direction of the silicon substrate, but also separate the second passivation layer and the first doped semiconductor layer along the direction parallel to the backlight surface.
  • the insulating layer can prevent the carriers in the second doped semiconductor layer from passing through the second passivation layer to enter the first doped semiconductor layer through the tunneling effect, and can also prevent the carriers in the first doped semiconductor layer from passing through the second passivation layer to enter the second doped semiconductor layer through the tunneling effect, that is, the insulating layer can prevent the carriers collected by the second doped semiconductor layer from recombining with the carriers collected by the first doped semiconductor layer of the opposite conductivity type, thereby preventing leakage from occurring at the lateral interface and the longitudinal interface of the first doped semiconductor layer and the second doped semiconductor layer at the same time, thereby facilitating the improvement of the photoelectric conversion efficiency of the back contact battery.
  • the first passivation layer is a tunneling passivation layer
  • the first doped semiconductor layer is a doped polysilicon layer.
  • the patterning method is to combine photolithography with wet etching, and ink printing with wet etching. In comparison, the cost of patterning by laser etching is lower and more suitable for mass production.
  • the step of forming the stacked first passivation layer and the first doped semiconductor layer is earlier than the step of forming the stacked second passivation layer and the second doped semiconductor layer.
  • amorphous silicon materials are easy to form polycrystalline silicon or single crystal silicon at high temperatures, and the chemical properties of tunneling passivation materials and polycrystalline silicon are relatively stable at high temperatures, compared with the stacked intrinsic amorphous silicon layer and the doped amorphous silicon layer, the stacked tunneling passivation layer and the doped polycrystalline silicon layer are less sensitive to high-temperature laser thermal damage, and can reduce the impact on the passivation effect during the laser film opening process, further increasing the process window and reducing the process difficulty.
  • the first passivation layer is a tunneling passivation layer and the first doped semiconductor layer is a doped polycrystalline silicon layer
  • a laser etching process can be used to pattern the passivation material layer for manufacturing the first passivation layer and the doped semiconductor material layer for manufacturing the first doped semiconductor layer, thereby reducing the manufacturing cost of the back contact battery while ensuring that the first passivation layer and the first doped semiconductor layer have good film quality, which is beneficial to improving the yield and electrical performance of the back contact battery.
  • both the tunnel passivation layer and the doped polysilicon layer can be formed by deposition using low-pressure chemical vapor deposition equipment.
  • the intrinsic amorphous silicon layer and the doped amorphous silicon layer need to be deposited using chemical vapor deposition equipment.
  • the cost of low-pressure chemical vapor deposition equipment is lower than the cost of chemical vapor deposition equipment, when the first passivation layer can also be a tunnel passivation layer, and the first doped semiconductor layer can also be a doped polysilicon layer, the passivation material layer used to manufacture the first passivation layer and the doped semiconductor material layer used to manufacture the first doped semiconductor layer can be deposited by low-pressure chemical vapor deposition equipment, thereby reducing the manufacturing cost of the back contact battery.
  • the second passivation layer is an intrinsic amorphous silicon layer
  • the second doped semiconductor layer is a doped amorphous silicon layer.
  • the intrinsic amorphous silicon layer has a better passivation effect than the tunnel passivation layer. Based on this, compared with the second passivation layer being the tunnel passivation layer and the second doped semiconductor layer being the doped polysilicon layer, when the second passivation layer is the intrinsic amorphous silicon layer and the second doped semiconductor layer, the recombination rate of carriers of opposite conductivity types at the interface between the silicon substrate and the second passivation layer can be further reduced, and the photoelectric conversion efficiency of the back contact cell can be further improved.
  • the back contact cell further comprises: In the direction away from the silicon substrate, an aluminum oxide layer and a silicon nitride layer are sequentially stacked on the light-facing surface of the silicon substrate.
  • the back contact cell further comprises: a silicon oxide layer and a silicon nitride layer are sequentially stacked on the light-facing surface of the silicon substrate in a direction away from the silicon substrate.
  • the stacked aluminum oxide layer and silicon nitride layer can passivate the light-facing surface, reduce the recombination rate of carriers at the light-facing surface, and further improve the photoelectric conversion efficiency of the back contact battery.
  • silicon nitride can play a role in anti-reflection, which is conducive to refracting more light from the light-facing surface into the silicon substrate, further improving the utilization rate of light by the back contact battery.
  • the velvet surface of the light-facing surface of the silicon substrate can be selected from velvet surfaces with smaller pyramid sizes, and velvet surfaces with smaller sizes have better light trapping effects, further improving the silicon substrate's absorption of light.
  • the beneficial effects of the stacked silicon oxide layer and silicon nitride layer can refer to the beneficial effects analysis of the stacked aluminum oxide layer and silicon nitride layer described above, which will not be repeated here.
  • the aluminum oxide layer, silicon nitride layer and silicon oxide layer can all be deposited by atomic layer deposition equipment.
  • the intrinsic amorphous silicon layer needs to be deposited by chemical vapor deposition equipment. Based on this, since the cost of atomic layer deposition equipment is lower than that of chemical vapor deposition equipment, when an aluminum oxide layer (or silicon oxide layer) and a silicon nitride layer are formed on the light-facing surface as a passivation anti-reflection layer, an aluminum oxide (or silicon oxide) and silicon nitride layer can be deposited on the light-facing surface by atomic layer deposition equipment, thereby reducing the manufacturing cost of the back contact battery.
  • the insulating layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence.
  • the insulating layer includes a silicon oxide layer and a silicon nitride layer stacked in sequence.
  • the aluminum oxide layer, the silicon nitride layer and the silicon oxide layer all have good dielectric properties, which is conducive to the insulating layer separating the second passivation layer from the first doped semiconductor layer, thereby
  • the parallel resistance of the back contact battery can be increased, and the leakage risk of the back contact battery can be reduced.
  • aluminum oxide, silicon nitride and silicon oxide can also be used to manufacture a film layer with a passivation effect and/or an anti-reflection effect on the light-facing surface.
  • the material of the insulating layer is the same as the material of the passivation anti-reflection layer, so that the passivation anti-reflection layer can be formed on the light-facing surface while forming the insulating layer, which is conducive to simplifying the manufacturing process of the back contact battery and improving the manufacturing efficiency of the back contact battery.
  • the thickness of the insulating layer is 75nm to 125nm.
  • the thickness of the insulating layer is within this range, which can prevent the partial carriers collected by the second doped semiconductor layer from being recombined with the carriers collected by the first doped semiconductor layer of opposite conductivity type through the second passivation layer and the insulating layer in turn through the tunneling effect due to the small thickness of the insulating layer, thereby ensuring that the insulating layer has good insulating properties.
  • the insulating layer not only separates the second passivation layer from the first doped semiconductor layer along the direction of the silicon substrate, but also separates the second passivation layer from the first doped semiconductor layer along the direction parallel to the backlight surface of the silicon substrate.
  • the portion of the insulating layer located at the longitudinal junction of the second passivation layer and the first doped semiconductor layer, the first doped semiconductor layer and the second doped semiconductor layer are distributed above the backlight surface along the direction parallel to the backlight surface.
  • the thickness of the insulating layer is large, the cross-sectional area of the portion of the insulating layer located at the longitudinal junction of the second passivation layer and the first doped semiconductor layer is large, and the surface area of the backlight surface is a constant.
  • the thickness of the insulating layer is 75nm to 125nm, it can also prevent the cross-sectional area of at least one of the first doped semiconductor layer and the second doped semiconductor layer from being reduced due to the large thickness of the insulating layer, thereby affecting its carrier collection ability, ensuring that the carriers generated after the silicon substrate absorbs photons are promptly conducted out by the first doped semiconductor layer and the second doped semiconductor layer, thereby further improving the photoelectric conversion efficiency of the back contact battery.
  • the light-facing surface of the silicon substrate is a velvet surface
  • the width of the tower base of the velvet surface is 1 ⁇ m to 3 ⁇ m.
  • the smaller the width of the velvet base the better the light-trapping effect of the velvet.
  • the width of the light-facing surface is relatively small, and the light-facing surface has a higher light-trapping effect.
  • a passivation reflective layer made of amorphous silicon materials such as aluminum oxide and silicon oxide that matches the velvet with a smaller base width can be formed on the light-facing surface, so that more light can be transmitted into the silicon substrate through the light-facing surface, further improving the back contact electrode. The photoelectric conversion efficiency of the cell.
  • the present disclosure further provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.
  • the present disclosure also provides a method for manufacturing a back-contact battery, which comprises: first, providing a silicon substrate. Next, forming a first passivation layer and a first doped semiconductor layer stacked in sequence on the backlight surface of the silicon substrate along the thickness direction of the silicon substrate. Next, forming an insulating layer on the backlight surface. Next, forming a second passivation layer and a second doped semiconductor layer stacked in sequence on the backlight surface along the thickness direction of the silicon substrate. The stacked second passivation layer and the second doped semiconductor layer cover a partial area of the stacked first passivation layer and the first doped semiconductor layer, and the conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer.
  • the insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer and the first doped semiconductor layer.
  • beneficial effects of the third aspect of the present disclosure can be analyzed by referring to the beneficial effects of the first aspect, and will not be repeated here.
  • forming a first passivation layer and a first doped semiconductor layer in a stacked arrangement includes: first, sequentially forming a passivation material layer covering the backlight surface and an intrinsic semiconductor material layer located on the passivation material layer. Next, performing a diffusion treatment on the intrinsic semiconductor material layer so that the intrinsic semiconductor material layer forms a doped semiconductor material layer, and a doped glass layer is formed on the doped semiconductor material layer. Next, using a laser etching process, a portion of the doped glass layer located on the doped semiconductor material layer is removed. The remaining portion of the doped glass layer forms a mask layer.
  • the portion of the doped semiconductor material layer exposed outside the mask layer and the portion of the passivation material layer exposed outside the mask layer are sequentially removed to form a first passivation layer and a first doped semiconductor layer in a stacked arrangement.
  • the intrinsic semiconductor material layer located on the passivation material layer is diffused, the intrinsic semiconductor material layer is transformed into a doped semiconductor material layer, and a doped glass layer is formed on the surface of the doped semiconductor material layer.
  • the doped glass layer can be, for example, a phospho-silicate glass layer (PSG) or a borosilicate glass layer. (Boro silicate Glass, abbreviated as BSG), etc.
  • the remaining portion of the doped glass layer can form a mask layer, so that the doped semiconductor material layer and the passivation material layer can be patterned without the need to form additional mask layers such as silicon nitride, which simplifies the manufacturing process of the back contact battery and reduces the manufacturing cost of the back contact battery.
  • the method for manufacturing a back-contact cell further includes: removing the doped glass layer, the doped semiconductor material layer, and the passivation material layer on the light-facing surface and the side surface of the silicon substrate.
  • the light-facing surface of the silicon substrate is subjected to a texturing treatment so that the light-facing surface is a velvet surface. The mask layer is removed.
  • the mask layer used is obtained by patterning the doped glass layer formed on the doped semiconductor material layer during the diffusion process using a laser etching process, rather than a mask layer such as silicon nitride formed by additional deposition and other processes after obtaining the stacked first passivation layer and the first doped semiconductor layer. This can further simplify the manufacturing process of the back contact battery and reduce the manufacturing cost of the back contact battery.
  • the thickness of the above-mentioned doped glass layer is 40nm to 60nm.
  • the thickness of the doped glass layer is within this range, which can prevent the mask layer formed by the remaining part of the doped glass layer from having a poor protective effect due to the small thickness of the doped glass layer, which makes it difficult to protect the first doped semiconductor layer and the first passivation layer located thereunder in the corresponding operation, thereby ensuring that the first doped semiconductor layer and the first passivation layer have good film-forming quality and improving the yield of the back contact battery.
  • it can also prevent problems such as reduced manufacturing efficiency and increased manufacturing costs due to the large thickness of the doped glass layer, which is conducive to improving the mass production of the back contact battery.
  • the diffusion time of the above diffusion treatment is 60 min to 120 min, and the diffusion temperature is 800° C. to 900° C.
  • the beneficial effects in this case are similar to the beneficial effects described above when the thickness of the doped glass layer is 40 nm to 60 nm, and can be referred to above, and will not be repeated here.
  • forming a first passivation layer and a first doped semiconductor layer in a stacked manner includes: first, sequentially forming a passivation material layer covering the backlight surface and a doped semiconductor material layer located on the passivation material layer. Next, using a laser etching process, The material layer and the passivation material layer are patterned to form a first passivation layer and a first doped semiconductor layer that are stacked.
  • the first passivation layer is a tunneling passivation layer
  • the first doped semiconductor layer is a doped polysilicon layer.
  • the beneficial effects in this case can be referred to the beneficial effects analysis of the first passivation layer being a tunneling passivation layer and the first doped semiconductor layer being a doped polysilicon layer described above, and will not be repeated here.
  • FIG1 is a schematic longitudinal cross-sectional view of a structure of a passivated back-contact solar cell in the related art
  • FIG2 is a schematic longitudinal cross-sectional view of another structure of a passivated back-contact solar cell in the related art
  • FIG3 is a structural schematic diagram 1 of a back contact battery during the manufacturing process provided by an embodiment of the present disclosure
  • FIG4 is a second structural schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG5 is a third structural schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG6 is a fourth structural schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG7 is a fifth structural diagram of a back contact battery during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG8 is a sixth structural diagram of a back contact battery during manufacturing provided by an embodiment of the present disclosure.
  • FIG9 is a seventh structural diagram of a back contact battery during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG10 is a structural schematic diagram 8 of a back contact battery during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG11 is a ninth structural diagram of a back contact battery during manufacturing provided by an embodiment of the present disclosure.
  • FIG12 is a structural schematic diagram 10 of a back contact battery during the manufacturing process provided by an embodiment of the present disclosure
  • FIG13 is a structural schematic diagram 11 of a back contact battery during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG14 is a structural schematic diagram 12 of a back contact battery during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG15 is a thirteenth structural diagram of a back contact battery during manufacturing provided by an embodiment of the present disclosure.
  • FIG. 16 is a structural schematic diagram fourteen of a back-contact battery manufacturing process provided in an embodiment of the present disclosure.
  • 11 is a silicon substrate
  • 12 is a passivation material layer
  • 121 is a first passivation layer
  • 13 is an intrinsic semiconductor material layer
  • 14 is a doped semiconductor material layer
  • 141 is a first doped semiconductor layer
  • 15 is a doped glass layer
  • 151 is a mask layer
  • 16 is an insulating material layer
  • 161 is an insulating layer
  • 17 is a second passivation layer
  • 18 is a second doped semiconductor layer
  • 19 is an aluminum oxide layer
  • 20 is a silicon nitride layer
  • 21 is a transparent conductive material layer
  • 211 is a first transparent conductive layer
  • 212 is a second transparent conductive layer
  • 22 is a first electrode
  • 23 is a second electrode.
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them.
  • the layer/element may be "under” the other layer/element.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • “multiple” means two or more, unless otherwise clearly and specifically defined.
  • "Several” means one or more, unless otherwise clearly and specifically defined.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • installed should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • Passivated back-contact solar cells refer to solar cells with a passivated contact structure in which both the positive and negative electrodes are located on the back of the cell, with no metal electrode blocking the front. Passivated back-contact solar cells have a large light absorption area and a low carrier recombination rate, which has attracted extensive attention from the photovoltaic academic and industrial communities and has become a hot development direction for high-efficiency solar cell technology.
  • the passivated back contact type solar cell in the related art generally includes a silicon substrate 11, a first passivation contact structure and a second passivation contact structure.
  • the first passivation contact structure and the second passivation contact structure are alternately distributed on the backlight surface.
  • the second passivation contact structure covers part of the first passivation contact structure. region.
  • the first passivation contact structure and the second passivation contact structure each include a passivation layer and a doped semiconductor layer stacked in sequence.
  • the corresponding types of carriers can pass through the passivation layers included in the first passivation contact structure and the second passivation contact structure respectively through the tunneling effect, and are conducted to the corresponding electrodes through the corresponding doped semiconductor layers included in the first passivation contact structure and the second passivation contact structure, thereby forming a photocurrent.
  • the thickness of the passivation layer included in the first passivation contact structure and the second passivation contact structure in the passivation back contact solar cell in the related art is usually small when designing.
  • the conductivity type of the doped semiconductor layer included in the first passivation contact structure and the second passivation contact structure is opposite.
  • the second passivation contact structure covers a part of the first passivation contact structure, even if an insulating layer is provided at the longitudinal junction of the first passivation contact structure and the second passivation contact structure along the thickness direction of the silicon substrate, the insulating layer can only separate the first passivation contact structure and the second passivation contact structure in the longitudinal direction.
  • the two are only separated by the passivation layer (for example, by the intrinsic semiconductor layer).
  • the thinner passivation layer makes it difficult to achieve the isolation of the carriers in the doped semiconductor layer of the first passivation contact structure and the carriers in the doped semiconductor layer of the second passivation contact structure, resulting in a high recombination rate of carriers of opposite conductivity types at the lateral interface between the two, and there is a risk of leakage, which further affects the performance improvement of the passivation back contact solar cell.
  • the embodiments of the present disclosure provide a back-contact battery.
  • the back-contact battery includes: a silicon substrate 11 , a first passivation layer 121 , a first doped semiconductor layer 141 , a second passivation layer 17 , a second doped semiconductor layer 18 and an insulating layer 161 .
  • the first passivation layer 121 and the first doped semiconductor layer 141 are sequentially stacked on the backlight surface of the silicon substrate 11.
  • the second passivation layer 17 and the second doped semiconductor layer 18 are sequentially stacked on the backlight surface.
  • the stacked second passivation layer 17 and the second doped semiconductor layer 18 cover a portion of the stacked first passivation layer 121 and the first doped semiconductor layer 141, and the conductivity type of the second doped semiconductor layer 18 and the first doped semiconductor layer 141 is opposite.
  • the insulating layer 161 is disposed on the backlight surface.
  • the insulating layer 161 is at least located between the second passivation layer 17 and the first doped semiconductor layer 141, and is used to separate the second passivation layer 17 from the first doped semiconductor layer 141.
  • the silicon substrate can be an N-type silicon substrate or a P-type silicon substrate.
  • the specific structure of the silicon substrate can be set according to the actual application scenario.
  • the silicon substrate 11 can be a silicon substrate on which no film layer is formed, and both the backlight surface and the light-facing surface are polished surfaces.
  • the silicon substrate 11 can also be a silicon substrate on which no film layer is formed, and the light-facing surface is a velvet surface.
  • the velvet structure has a good light trapping effect
  • the light-facing surface of the silicon substrate 11 is a velvet surface
  • more light can be refracted from the light-facing surface into the silicon substrate 11, thereby facilitating the improvement of the photoelectric conversion efficiency of the back contact battery.
  • the width of the tower base of the velvet surface can be set according to actual needs, and is not specifically limited here.
  • the material and thickness of the first passivation layer and the first doped semiconductor layer, as well as the doping type and doping concentration of the doping elements in the first doped semiconductor layer can be set according to actual needs, as long as they can be applied to the back contact battery provided in the embodiment of the present disclosure.
  • the first passivation layer may be an intrinsic amorphous silicon layer
  • the first doped semiconductor layer may be a doped amorphous silicon layer.
  • the first passivation layer and the first doped semiconductor layer may form a heterogeneous contact structure. Based on this, since the heterogeneous contact structure has a passivation effect superior to that of the tunnel passivation contact structure, when the stacked first passivation layer and the first doped semiconductor layer form a heterogeneous contact structure, the carrier recombination rate at the interface between the silicon substrate and the first passivation layer may be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the back contact cell.
  • the first passivation layer may also be a tunnel passivation layer
  • the first doped semiconductor layer may also be a doped polysilicon layer.
  • the passivation material layer 12 for manufacturing the first passivation layer 121 and the doped semiconductor material layer 14 for manufacturing the first doped semiconductor layer 141.
  • the cost of patterning by laser etching process is lower and more suitable for mass production.
  • the formation steps of the stacked first passivation layer 121 and the first doped semiconductor layer 141 are earlier than the stacked second passivation layer 17 and the second doped semiconductor layer 18.
  • the amorphous silicon material is easy to form polycrystalline silicon or single crystal silicon at high temperature, and the chemical properties of the tunneling passivation material and polycrystalline silicon at high temperature are relatively stable, compared with the stacked intrinsic amorphous silicon layer and the doped amorphous silicon layer, the stacked tunneling passivation layer and the doped polycrystalline silicon layer are less sensitive to high-temperature laser thermal damage, and can reduce the influence on the passivation effect during the laser film opening process, further increasing the process window and reducing the process difficulty.
  • the first passivation layer 121 is a tunneling passivation layer and the first doped semiconductor layer 141 is a doped polycrystalline silicon layer
  • a laser etching process can be used to pattern the passivation material layer 12 for manufacturing the first passivation layer 121 and the doped semiconductor material layer 14 for manufacturing the first doped semiconductor layer 141, so as to reduce the manufacturing cost of the back contact battery while ensuring that the first passivation layer 121 and the first doped semiconductor layer 141 have good film quality, which is beneficial to improving the yield and electrical performance of the back contact battery.
  • both the tunnel passivation layer and the doped polysilicon layer can be formed by deposition using low-pressure chemical vapor deposition equipment.
  • the intrinsic amorphous silicon layer and the doped amorphous silicon layer need to be deposited using chemical vapor deposition equipment.
  • the cost of low-pressure chemical vapor deposition equipment is lower than the cost of chemical vapor deposition equipment, when the first passivation layer can also be a tunnel passivation layer, and the first doped semiconductor layer can also be a doped polysilicon layer, the passivation material layer used to manufacture the first passivation layer and the doped semiconductor material layer used to manufacture the first doped semiconductor layer can be deposited by low-pressure chemical vapor deposition equipment, thereby reducing the manufacturing cost of the back contact battery.
  • the material of the tunnel passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide.
  • the specific material of the tunnel passivation layer can be set according to actual needs.
  • the material and thickness of the second passivation layer and the second doped semiconductor layer, as well as the doping type and doping concentration of the doping element in the second doped semiconductor layer can be set according to actual needs.
  • the conductivity type of the second doped semiconductor layer and the first doped semiconductor layer is opposite.
  • the second doped semiconductor can be a P-type doped semiconductor layer doped with boron or other elements
  • the first doped semiconductor layer can be an N-type doped semiconductor layer doped with phosphorus or other elements.
  • the second doped semiconductor layer can be an N-type doped semiconductor layer
  • the first doped semiconductor layer can be a P-type doped semiconductor layer.
  • the second passivation layer may be a tunnel passivation layer, and the second doped semiconductor layer may be Alternatively, the second passivation layer may also be an intrinsic amorphous silicon layer, and the second doped semiconductor layer may also be a doped amorphous silicon layer.
  • the second doped semiconductor layer is a doped polysilicon layer
  • the second passivation layer is an intrinsic amorphous silicon layer
  • the second doped semiconductor layer is a doped amorphous silicon layer
  • the second passivation layer being a tunneling passivation layer and the second doped semiconductor layer being a doped polysilicon layer
  • the second passivation layer is an intrinsic amorphous silicon layer and the second doped semiconductor layer
  • the recombination rate of carriers of opposite conductivity types at the interface between the silicon substrate and the second passivation layer can be further reduced, and the photoelectric conversion efficiency of the back contact battery can be further improved.
  • the area in which the stacked second passivation layer and the second doped semiconductor layer cover the stacked first passivation layer and the first doped semiconductor layer can be set according to the actual application scenario, and is not specifically limited here.
  • the insulating layer can be a single-layer structure formed by one or more insulating materials, or the insulating layer can also be a multi-layer composite structure formed by multiple insulating materials.
  • the specific structure of the insulating layer can be set according to actual needs.
  • the above-mentioned insulating material can be any material with insulating properties.
  • the thickness of the insulating layer and the formation range of the insulating layer on the backlight surface can be set according to actual needs, as long as the insulating layer can be at least located between the second passivation layer and the first doped semiconductor layer, and the second passivation layer and the first doped semiconductor layer can be separated by the insulating layer.
  • the insulating layer 161 can not only separate the second passivation layer 17 and the first doped semiconductor layer 141 along the thickness direction of the silicon substrate 11, but also separate the second passivation layer 17 and the first doped semiconductor layer 141 along the direction parallel to the backlight surface.
  • the insulating layer 161 can prevent the carriers in the second doped semiconductor layer 18 from passing through the second passivation layer 17 to enter the first doped semiconductor layer 141 through the tunneling effect, and can also prevent the carriers in the first doped semiconductor layer 141 from passing through the second passivation layer 17 to enter the second doped semiconductor layer 18 through the tunneling effect.
  • the insulating layer 161 can block the carriers collected by the second doped semiconductor layer 18 from being separated from the conductive type.
  • the carriers collected by the first doped semiconductor layer 141 of opposite type are recombined, thereby preventing leakage at the lateral interface and the vertical interface between the first doped semiconductor layer 141 and the second doped semiconductor layer 18, thereby facilitating the improvement of the photoelectric conversion efficiency of the back contact battery.
  • the thickness of the insulating layer is 75nm to 125nm. In this case, the thickness of the insulating layer is within this range, which can prevent the part of the carriers collected by the second doped semiconductor layer from being recombined with the carriers collected by the first doped semiconductor layer of opposite conductivity type through the second passivation layer and the insulating layer in turn through the tunneling effect due to the small thickness of the insulating layer, thereby ensuring that the insulating layer has good insulation performance.
  • the insulating layer 161 not only separates the second passivation layer 17 from the first doped semiconductor layer 141 along the thickness direction of the silicon substrate 11, but also separates the second passivation layer 17 from the first doped semiconductor layer 141 along the direction parallel to the backlight surface of the silicon substrate 11. Therefore, the insulating layer 161 is located at the longitudinal junction of the second passivation layer 17 and the first doped semiconductor layer 141, and the first doped semiconductor layer 141 and the second doped semiconductor layer 18 are distributed above the backlight surface along the direction parallel to the backlight surface.
  • the thickness of the insulating layer 161 is large, the cross-sectional area of the portion of the insulating layer 161 located at the longitudinal junction of the second passivation layer 17 and the first doped semiconductor layer 141 is large, and the surface area of the backlight surface is a constant.
  • the thickness of the insulating layer 161 when the thickness of the insulating layer 161 is 75nm to 125nm, it can also prevent the cross-sectional area of one of the first doped semiconductor layer 141 and the second doped semiconductor layer 18 from being reduced due to the large thickness of the insulating layer 161, thereby affecting its carrier collection ability, ensuring that the carriers generated after the silicon substrate 11 absorbs photons are promptly conducted out by the first doped semiconductor layer 141 and the second doped semiconductor layer 18, thereby further improving the photoelectric conversion efficiency of the back contact battery.
  • the thickness of the insulating layer may also be set to other appropriate values according to different application scenario requirements.
  • the back contact cell further includes: an aluminum oxide layer 19 and a silicon nitride layer 20 stacked sequentially on the light-facing surface of the silicon substrate 11 in a direction away from the silicon substrate 11.
  • the back contact cell further includes: a silicon oxide layer and a silicon nitride layer stacked sequentially on the light-facing surface of the silicon substrate in a direction away from the silicon substrate.
  • the thicknesses of the aluminum oxide layer, silicon nitride layer, and silicon oxide layer can be set according to actual needs and are not specifically limited here.
  • the stacked aluminum oxide layer and the silicon nitride layer can be opposite to each other.
  • the light surface is passivated to reduce the recombination rate of carriers on the light-facing surface, further improving the photoelectric conversion efficiency of the back contact battery.
  • the silicon nitride layer can play an anti-reflection role, which is conducive to refracting more light from the light-facing surface into the silicon substrate, further improving the utilization rate of light by the back contact battery.
  • the velvet of the light-facing surface of the silicon substrate can be selected from velvet with a smaller pyramid size, and the velvet with a smaller size has a better light trapping effect, further improving the absorption of light by the silicon substrate.
  • the beneficial effects of the stacked silicon oxide layer and silicon nitride layer can refer to the beneficial effects analysis of the stacked aluminum oxide layer and silicon nitride layer described above, which will not be repeated here.
  • the aluminum oxide layer, silicon nitride layer and silicon oxide layer can all be deposited and formed by atomic layer deposition equipment.
  • the intrinsic amorphous silicon layer needs to be deposited and formed by chemical vapor deposition equipment. Based on this, because the cost of atomic layer deposition equipment is lower than that of chemical vapor deposition equipment, when an aluminum oxide layer (or silicon oxide layer) and a silicon nitride layer are formed on the light-facing surface as a passivation anti-reflection layer, an aluminum oxide (or silicon oxide) and silicon nitride layer can be deposited on the light-facing surface by atomic layer deposition equipment, thereby reducing the manufacturing cost of the back contact battery.
  • the material of the film layer with passivation and anti-reflection functions formed on the light-facing surface may also be set to other suitable materials.
  • the film layer with passivation and anti-reflection functions formed on the light-facing surface may also include at least one of a silicon oxynitride layer, a titanium oxide layer and a silicon oxycarbide layer.
  • the insulating layer 161 includes an aluminum oxide layer and a silicon nitride layer stacked in sequence.
  • the insulating layer 161 includes a silicon oxide layer and a silicon nitride layer stacked in sequence.
  • the aluminum oxide layer, silicon nitride layer and silicon oxide layer all have good dielectric properties, which is conducive to the insulating layer separating the second passivation layer from the first doped semiconductor layer, thereby increasing the parallel resistance of the back contact battery and reducing the leakage risk of the back contact battery.
  • Aluminum oxide, silicon nitride and silicon oxide can also be used to manufacture a film layer with passivation and/or anti-reflection effect on the light-facing surface.
  • the material of the insulating layer is the same as the material of the passivation anti-reflection layer, so that the passivation anti-reflection layer can be formed on the light-facing surface at the same time as the insulating layer is formed, which is conducive to simplifying the manufacturing process of the back contact battery and improving the manufacturing efficiency of the back contact battery.
  • the insulating layer in addition to the silicon oxide layer, silicon nitride layer and aluminum oxide layer, in order to make the material of the insulating layer the same as that of the passivation anti-reflection layer, the insulating layer can also be set to other materials of the film layer with passivation and anti-reflection functions as described above.
  • the light-facing surface of the silicon substrate 11 is a velvet surface
  • the width of the tower base of the velvet surface is 1 ⁇ m to 3 ⁇ m.
  • the width of the tower base of the velvet surface is 1 ⁇ m to 3 ⁇ m, the width of the tower base of the light-facing surface is relatively small, and the light-facing surface has a higher light trapping effect, which can further improve the photoelectric conversion efficiency of the back contact battery.
  • the passivation layer formed on the light-facing surface is usually an amorphous silicon layer.
  • it is usually necessary to form it on a velvet structure with a relatively large base width.
  • the larger the base width of the velvet the worse the light trapping effect of the velvet.
  • the higher the reflectivity of the light-facing surface the higher the reflectivity of the light-facing surface.
  • the amorphous silicon passivation layer located on the light-facing surface in the existing heterojunction back contact cells is poorly compatible with the velvet with a smaller base width, and it is difficult to reduce the reflectivity of the light-facing surface to light while improving the passivation effect of the light-facing surface.
  • a passivation reflective layer made of amorphous silicon materials such as aluminum oxide and silicon oxide that matches the velvet surface with a smaller width of the tower base can be formed on the light-facing surface. This can not only improve the passivation effect of the backlight surface, but also allow more light to be transmitted through the light-facing surface into the silicon substrate, thereby further improving the photoelectric conversion efficiency of the back-contact cell provided in the embodiment of the present disclosure.
  • the back contact cell provided by the embodiment of the present disclosure may further include a first transparent conductive layer 211, a second transparent conductive layer 212, a first electrode 22, and a second electrode 23.
  • the first transparent conductive layer 211 is at least formed on the first doped semiconductor layer 141, and the first electrode 23 is
  • the pole 22 is located on the portion of the first transparent conductive layer 211 corresponding to the first doped semiconductor layer 141, so as to lead out the carriers collected by the first doped semiconductor layer 141.
  • the second transparent conductive layer 212 is formed on the second doped semiconductor layer 18, and the second transparent conductive layer 212 and the first transparent conductive layer 211 are insulated from each other.
  • the second electrode 23 is located on the second transparent conductive layer 212, so as to lead out the carriers collected by the second doped semiconductor layer 18.
  • the material of the first transparent conductive layer or the second transparent conductive layer can be fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, indium hydroxide, etc.
  • the thickness of the first transparent conductive layer and the second transparent conductive layer can be set according to actual needs and is not specifically limited here.
  • the material of the first electrode and the second electrode can be a conductive material such as silver, aluminum, copper, nickel, etc.
  • an embodiment of the present disclosure further provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.
  • the embodiments of the present disclosure also provide a method for manufacturing a back-contact battery.
  • the manufacturing process will be described below based on the cross-sectional views of the back-contact battery manufacturing process shown in FIG. 3 to FIG. 16.
  • the manufacturing method of the back-contact battery includes the following steps:
  • a silicon substrate 11 is provided.
  • the specific structure of the silicon substrate 11 can be referred to above and will not be described again here.
  • the doped silicon substrate can be polished in a tank cleaning device using an alkaline cleaning solution such as KOH to obtain a silicon base.
  • an alkaline cleaning solution such as KOH
  • the backlight side and the light-facing side of the polished silicon substrate are both flat polished surfaces, which facilitates the subsequent formation of a structure that meets the process requirements based on the flat polished surface, thereby improving the yield of the back-contact battery.
  • a first passivation layer 121 and a first doped semiconductor layer 141 are sequentially stacked on the backlight surface of the silicon substrate 11 along the thickness direction of the silicon substrate 11.
  • the materials and thickness of the first passivation layer 121 and the first doped semiconductor layer 141 can be referred to above and will not be repeated here.
  • the first passivation layer and the first doped semiconductor layer formed in a stacked arrangement may include The steps are as follows: as shown in FIG4 , a passivation material layer 12 covering the backlight surface and an intrinsic semiconductor material layer 13 located on the passivation material layer 12 are sequentially formed. As shown in FIG5 , the intrinsic semiconductor material layer is diffused so that the intrinsic semiconductor material layer forms a doped semiconductor material layer 14, and a doped glass layer 15 is formed on the doped semiconductor material layer 14. Next, a laser etching process is used to remove part of the doped glass layer located on the doped semiconductor material layer. The remaining part of the doped glass layer forms a mask layer.
  • the part of the doped semiconductor material layer exposed outside the mask layer and the part of the passivation material layer exposed outside the mask layer are sequentially removed to form a first passivation layer 121 and a first doped semiconductor layer 141 stacked.
  • the formation process of the first passivation layer and the first doped semiconductor layer can be determined according to the materials of the two.
  • a low pressure chemical vapor deposition (LPCVD) and other processes can be used to sequentially form a passivation material layer 12 covering the backlight surface and an intrinsic semiconductor material layer 13 located on the passivation material layer 12.
  • LPCVD low pressure chemical vapor deposition
  • other processes can be used to sequentially form a passivation material layer 12 covering the backlight surface and an intrinsic semiconductor material layer 13 located on the passivation material layer 12.
  • LPCVD low pressure chemical vapor deposition
  • other processes can be used to sequentially form a passivation material layer 12 covering the backlight surface and an intrinsic semiconductor material layer 13 located on the passivation material layer 12.
  • a plated passivation material layer and a plated intrinsic semiconductor material layer are also formed on the side and light-facing surface of the silicon substrate 11.
  • the intrinsic semiconductor material layer 13 is diffused by a diffusion device. Specifically, as shown in FIG5 , when the intrinsic semiconductor material layer located on the passivation material layer 12 is diffused, the intrinsic semiconductor material layer is transformed into a doped semiconductor material layer 14, and a doped glass layer 15 is formed on the surface of the doped semiconductor material layer 14.
  • the processing conditions of the diffusion treatment can be determined according to the doping concentration of the doping elements in the first doped semiconductor layer 141, the thickness and density of the doped glass layer 15 to be formed, and the actual application scenario, and are not specifically limited here.
  • the above-mentioned plated intrinsic semiconductor material layer will also form a plated doped semiconductor material layer, and a plated doped glass layer will be formed on the plated doped semiconductor material layer.
  • the doped glass layer 15 is patterned by a laser etching process, the remaining part of the doped glass layer can form a mask layer.
  • the mask layer covers the portion of the doped semiconductor material layer corresponding to the formation of the first doped semiconductor layer.
  • the mask layer used in the process is obtained by patterning the doped glass layer.
  • the specific material of the above-mentioned doped glass layer can be determined according to the material and doping type of the first doped semiconductor layer.
  • the doped glass layer is a phosphorus silicon glass layer.
  • the doped glass layer is a borosilicate glass layer.
  • the thickness of the doped glass layer can be set according to actual needs, as long as the mask layer formed by the doped glass layer can have a corresponding masking function.
  • the thickness of the doped glass layer may be 40 nm to 60 nm.
  • the thickness of the doped glass layer may be 40 nm, 45 nm, 50 nm, 55 nm or 60 nm.
  • the thickness of the doped glass layer is relatively moderate, which can prevent the mask layer formed by the remaining part of the doped glass layer from having a poor protective effect due to the small thickness of the doped glass layer, thereby preventing the first doped semiconductor layer and the first passivation layer located thereunder from being difficult to protect in the corresponding operation, thereby ensuring that the first doped semiconductor layer and the first passivation layer have good film-forming quality and improving the yield of the back-contact battery.
  • it can also prevent problems such as reduced manufacturing efficiency and increased manufacturing costs due to the large thickness of the doped glass layer, which is conducive to improving the mass production of the back-contact battery.
  • the diffusion time of the above diffusion treatment can be 60 min to 120 min, and the diffusion temperature can be 800° C. to 900° C.
  • the diffusion time can be 60 min, 70 min, 80 min, 90 min, 100 min, 110 min or 120 min.
  • the diffusion temperature can be 810° C., 820° C., 830° C., 840° C., 850° C., 860° C., 870° C., 880° C., 890° C. or 900° C.
  • the diffusion temperature and the diffusion time will affect the thickness of the doped glass layer formed during the diffusion process and the density of the doped glass layer. Specifically, within a certain range, the longer the diffusion time and the higher the diffusion temperature, the thicker the doped glass layer formed and the higher the density, and the correspondingly stronger the masking effect of the mask layer formed by the doped glass layer. On the contrary, within a certain range, the shorter the diffusion time and the lower the diffusion temperature, the thinner the thickness of the doped glass layer formed and the lower the density, and the correspondingly weaker the masking effect of the mask layer formed by the doped glass layer.
  • the diffusion time is 60 min to 120 min and the diffusion temperature is When the temperature is 800°C to 900°C, it can prevent the first doped semiconductor layer and the first passivation layer located thereunder from being difficult to protect during the corresponding operation due to the short diffusion time and the low diffusion temperature, ensure that the first doped semiconductor layer and the first passivation layer have good film-forming quality, and improve the yield of the back-contact battery. At the same time, it can also prevent the problems of reduced manufacturing efficiency and increased manufacturing costs due to the long diffusion time and the high diffusion temperature, which is conducive to improving the mass production of the back-contact battery.
  • ion implantation or doping source coating and advancement processes may also be used to form the doped semiconductor material layer.
  • a suitable process for forming the doped semiconductor material layer may be selected according to the actual application scenario requirements.
  • the first passivation layer is a tunnel passivation layer and the first doped semiconductor layer is a doped polysilicon layer
  • a plasma enhanced chemical vapor deposition process can also be used to form the doped polysilicon layer.
  • the doped polysilicon layer can also be crystallized by in-situ annealing to reduce the stress in the doped polysilicon layer and improve the film quality of the doped polysilicon layer.
  • the first passivation layer can be a tunnel passivation layer
  • the first doped semiconductor layer can be a doped polysilicon layer.
  • a laser etching process can be used to pattern the doped semiconductor material layer and the passivation material layer to form a stacked first passivation layer 121 and a first doped semiconductor layer 141.
  • the beneficial effects in this case can be analyzed with reference to the beneficial effects of the first passivation layer 121 being a tunnel passivation layer and the first doped semiconductor layer 141 being a doped polysilicon layer described above, and will not be repeated here.
  • the light-facing surface of the silicon substrate can be a polished surface or a velvet surface.
  • the above-mentioned mask layer is formed on the first doped semiconductor layer, after forming the first passivation layer and the first doped semiconductor layer arranged in a stacked manner, and before performing subsequent operations, the above-mentioned method for manufacturing a back-contact battery further includes the steps of: as shown in FIG7 , removing the wrap-around doped glass layer, the wrap-around doped semiconductor material layer and the wrap-around passivation material layer located on the light-facing surface and side surfaces of the silicon substrate 11.
  • a chain cleaning device can be used, and the above-mentioned wrap-around doped glass layer, the wrap-around doped semiconductor material layer and the wrap-around passivation material layer can be removed by roller-carrying liquid or floating on water. Passivation material layer.
  • the light-facing surface of the silicon substrate 11 is subjected to a texturing treatment so that the light-facing surface is a velvet surface.
  • the portion of the backlight surface exposed outside the mask layer 151 will also form a velvet surface.
  • the solution and treatment conditions used for the texturing treatment can be determined according to the actual application scenario, and are not specifically limited here.
  • an HF solution can be used to remove the mask layer 151.
  • the concentration of the HF solution and the removal time can be set according to actual needs.
  • the mask layer used is obtained by patterning the doped glass layer formed on the doped semiconductor material layer during the diffusion process using a laser etching process, rather than a mask layer such as silicon nitride formed by additional deposition and other processes after obtaining the stacked first passivation layer and the first doped semiconductor layer. This can further simplify the manufacturing process of the back contact battery and reduce the manufacturing cost of the back contact battery.
  • the back contact battery manufactured by the manufacturing method provided in the embodiment of the present disclosure includes: a silicon substrate, a first passivation layer, a first doped semiconductor layer, a second passivation layer, a second doped semiconductor layer and an insulating layer.
  • the stacked second passivation layer 17 and the second doped semiconductor layer 18 cover a portion of the stacked first passivation layer 121 and the first doped semiconductor layer 141.
  • the insulating layer 161 is at least located between the second passivation layer 17 and the first doped semiconductor layer 141, and is used to separate the second passivation layer 17 and the first doped semiconductor layer 141.
  • the manufacturing method of the back contact battery further includes the step of: forming an insulating layer on the backlight surface.
  • a plasma enhanced atomic layer deposition process or the like may be used to form an insulating material layer 16 covering the backlight surface and the first doped semiconductor layer 141.
  • a laser etching process or the like may be used to pattern the insulating material layer 16 to expose the area where the backlight surface contacts the second passivation layer 17 to be formed subsequently.
  • the insulating material layer 16 covers the portion of the corresponding area of the stacked first passivation layer 121 and the first doped semiconductor layer 141 to form an insulating layer.
  • the corresponding area is an area where the stacked first passivation layer 121 and the first doped semiconductor layer 141 are adjacent to the stacked second passivation layer and the second doped semiconductor layer.
  • the insulating material layer when the insulating material layer is patterned by laser etching, after exposing the area where the backlight surface contacts the second passivation layer to be formed subsequently, the insulating material layer can be patterned by laser etching. Under the masking effect of the remaining part of the insulating material layer, a wet etching process is used to clean and repair the surface of the area damaged by high-temperature laser etching, thereby reducing the defect recombination rate of carriers at the interface and improving the density of the second passivation layer formed on the area, further improving the passivation effect of the second passivation layer on the area, and improving the photoelectric conversion efficiency of the back contact battery.
  • a second passivation layer 17 and a second doped semiconductor layer 18 are sequentially stacked on the backlight surface along the thickness direction of the silicon substrate 11.
  • the stacked second passivation layer 17 and the second doped semiconductor layer 18 cover a portion of the stacked first passivation layer 121 and the first doped semiconductor layer 141, and the second doped semiconductor layer 18 and the first doped semiconductor layer 141 have opposite conductivity types.
  • the information such as the material and thickness of the second passivation layer 17 and the second doped semiconductor layer 18 can be referred to in the previous text, and will not be repeated here.
  • chemical vapor deposition and other processes can be used to sequentially form a passivation material and a doped semiconductor material covering the backlight surface and the remaining portion of the insulating material layer 16.
  • laser etching and other processes can be used to pattern the passivation material and the doped semiconductor material so that the remaining passivation material forms the second passivation layer 17, and the remaining doped semiconductor material forms the second doped semiconductor layer 18.
  • wet etching and other processes can be used to pattern the remaining portion of the insulating material layer 16 to expose a portion of the first doped semiconductor layer 141. Among them, the remaining insulating material layer forms an insulating layer 161.
  • the manufactured back contact cell when the manufactured back contact cell further includes a first transparent conductive layer, a second transparent conductive layer, a first electrode, and a second electrode, as shown in FIG14 , a process such as physical vapor deposition can be used to form a transparent conductive material layer 21 covering the first doped semiconductor layer 141 and the second doped semiconductor layer 18.
  • a process such as laser etching can be used to form an insulating groove penetrating the transparent conductive layer, the second doped semiconductor layer 18, and the second passivation layer 17 to separate the portion of the transparent conductive material layer located on the first doped semiconductor layer 141 from the portion of the transparent conductive material layer located on the second doped semiconductor layer 18.
  • the portion of the transparent conductive material layer located on the first doped semiconductor layer 141 forms the first transparent conductive layer 211
  • the portion of the transparent conductive material layer located on the second doped semiconductor layer 18 forms the second transparent conductive layer 212.
  • a process such as screen printing can be used to form a first electrode 22 located on the first transparent conductive layer 211 and a second electrode 23 located on the second transparent conductive layer 212.
  • the present disclosure also provides the following specific embodiments to further illustrate the method for manufacturing the back contact battery of the present disclosure, and the specific operation steps are as follows:
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • Step 1 Place the N-type silicon wafer or P-type silicon wafer into a tank-type polishing and cleaning machine for polishing.
  • the polishing solution is a KOH solution with a concentration of 5.5% to 6.5%.
  • the temperature of the polishing solution is 81°C to 87°C.
  • the process time is 290s to 310s.
  • the surface morphology of the silicon substrate is a square structure with a size of 19 ⁇ m to 23 ⁇ m, and the reflectivity of the backlight surface of the silicon substrate after the polishing process is 40% to 44%.
  • Step 2 In a low pressure chemical vapor deposition (LPCVD) furnace, a tunneling oxide material layer covering the backlight surface of the silicon substrate and an intrinsic polysilicon material layer on the tunneling oxide material layer are formed.
  • the thickness of the tunneling oxide material layer is 1.2nm to 1.8nm
  • the thickness of the intrinsic polysilicon material layer is 70nm to 170nm.
  • a passivation material layer and a polysilicon material layer are formed on the side and light-facing surface of the silicon substrate in sequence.
  • Step 3 In a phosphorus diffusion furnace, the intrinsic polysilicon material (Poly) layer is phosphorus doped, so that the intrinsic polysilicon material layer forms an N-type doped polysilicon material layer.
  • the diffusion square resistance of the N-type doped polysilicon material layer is 70 ⁇ /sq to 110 ⁇ /sq.
  • a phosphorus silicon glass layer is formed on the N-type doped polysilicon material layer and the coated polysilicon material layer.
  • Step 4 Use laser etching technology to pattern the portion of the phosphosilicate glass layer corresponding to the backlight surface, the tunneling oxide material layer and the N-type doped polysilicon material layer to expose the area corresponding to the backlight surface and the P+ region.
  • the remaining portion of the tunneling oxide material layer forms the first passivation layer, and the remaining portion of the N-type doped polysilicon material layer forms the first doped semiconductor layer.
  • the portion of the phosphosilicate glass layer located on the first doped semiconductor layer forms a mask layer.
  • Step 5 In a chain cleaning machine, place the light-facing surface of the silicon substrate facing downward into the HF tank, and use a roller-liquid or water-floating cleaning mode to remove the phosphosilicate glass layer located on the side and light-facing surface of the silicon substrate, as well as the plated passivation material layer and the plated polysilicon material layer at room temperature through a 9.5% to 10.5% HF solution.
  • the removal time is 55s to 65s.
  • the silicon substrate formed with the first passivation layer, the first doped semiconductor layer and the mask layer is placed in a tank cleaning machine for an alkaline texturing process.
  • the texturing solution includes a KOH solution with a concentration of 2.5% to 3.5%, and a texturing additive solution.
  • the temperature of the texturing solution is 80°C to 84°C, and the process time is 570s to 65s. 630s.
  • the etching amount is 0.5g to 0.7g, and the reflectivity of the light-facing surface of the silicon substrate after the texturing treatment is 9% to 11%.
  • the width of the tower base on the light-facing surface is a small velvet microstructure of 1 ⁇ m to 3 ⁇ m.
  • the P+ area on the backlight side and the light-facing surface are texturing treated at the same time.
  • enter the HF tank to remove the mask layer.
  • the concentration of the HF solution is 9.5% to 10.5%, and it is treated at room temperature for 95s to 105s.
  • Step 6 In the plasma enhanced atomic layer deposition (PEALD) equipment, aluminum oxide layer and silicon nitride layer are deposited on the backlight side and the light-facing side in sequence.
  • the thickness of the aluminum oxide layer is 5nm to 15nm, and the thickness of the silicon nitride layer is 70nm to 110nm.
  • Step 7 Use a laser to pattern the aluminum oxide layer and silicon nitride layer on the backlight surface to remove the aluminum oxide layer and silicon nitride layer located on the P+ region.
  • the patterning process is designed corresponding to the screen pattern, and the laser type can be selected from green light nanosecond, ultraviolet picosecond, green light picosecond, and ultraviolet nanosecond.
  • Step 8 Perform a polishing process in a tank polishing and cleaning machine.
  • the polishing solution is a KOH solution with a concentration of 5.5% to 6.5%
  • the temperature of the polishing solution is 81°C to 87°C
  • the process time is 170s to 190s to remove the laser damage generated in the seventh step.
  • the laser grooved area is polished.
  • it is treated in a HF solution with a concentration of 1%wt for 25s to 35s.
  • Step 9 In a chemical vapor deposition device, an intrinsic amorphous silicon material layer and a boron-doped P-type doped amorphous silicon material layer covering the backlight surface are sequentially formed, wherein the thickness of the intrinsic amorphous silicon material layer is 5nm to 20nm, and the thickness of the P-type doped amorphous silicon material layer is 10nm to 30nm.
  • Step 10 Use a laser to pattern the intrinsic amorphous silicon material layer and the P-type doped amorphous silicon material layer so that the remaining portion of the intrinsic amorphous silicon material layer forms a second passivation layer, and the remaining portion of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer.
  • the laser type can be green nanosecond, ultraviolet picosecond, green picosecond, ultraviolet nanosecond.
  • Step 11 In the chain cleaning machine, place the backlight side of the silicon substrate facing down into the HF tank.
  • the concentration of the HF solution is 29% to 31%, and it is treated at room temperature for 175s to 185s.
  • the cleaning mode is roller liquid method or water drift method.
  • the exposed parts of the aluminum oxide layer and silicon nitride layer on the backlight side are removed to expose part of the first doped semiconductor layer.
  • the remaining parts of the aluminum oxide layer and silicon nitride layer on the backlight side form an insulating layer.
  • Step 12 In a physical vapor deposition device, a transparent conductive material layer is formed covering the backlight surface, and the thickness of the transparent conductive material layer is 60nm to 100nm.
  • Step 13 Use a laser etching process to remove the local transparent conductive material layer, the second doped semiconductor layer and the second passivation layer to achieve insulation between the N+ region and the P+ region.
  • Step 14 Form the first electrode and the second electrode by screen printing or other processes. The final structure is shown in FIG16 .
  • the present disclosure also provides the following comparative example for manufacturing a back contact battery, and the specific operation steps are as follows:
  • Step 1 Place the N-type silicon wafer or P-type silicon wafer into a tank-type polishing and cleaning machine for polishing.
  • the polishing solution is a KOH solution with a concentration of 5.5% to 6.5%.
  • the temperature of the polishing solution is 81°C to 87°C.
  • the process time is 290s to 310s.
  • the surface morphology of the silicon substrate is a square structure with a size of 19 ⁇ m to 23 ⁇ m, and the reflectivity of the backlight surface of the silicon substrate after the polishing process is 40% to 44%.
  • Step 2 Use plasma enhanced chemical vapor deposition equipment to form a first silicon nitride layer covering the backlight surface of the silicon substrate.
  • the thickness of the first silicon nitride layer is 190nm to 210nm, and the refractive index is 2.3% to 2.5%.
  • the side and light-facing surface of the silicon substrate will be formed with a coating of silicon nitride layer.
  • Step 3 In the tank cleaning machine, the silicon substrate formed with the first silicon nitride layer and the surrounding silicon nitride layer is placed in the HF tank.
  • the concentration of the HF solution is 0.5% to 1.5%. And it is treated at room temperature for 25s to 35s to remove the surrounding silicon nitride layer.
  • the silicon substrate with the first silicon nitride layer formed on the backlight side is placed in the alkaline tank for texturing.
  • the texturing solution includes a KOH solution with a concentration of 2% to 3% and a texturing additive solution.
  • the temperature of the texturing solution is 80°C to 84°C.
  • the process time is 760s to 800s.
  • the tank containing a mixed solution of HNO3 and HF for velvet smoothing a mixed solution of HNO3 and HF for velvet smoothing.
  • the total etching amount after velvet smoothing is 1.7g to 1.9g.
  • the reflectivity of the light-facing surface of the silicon substrate is 11% to 13%.
  • the tower base width on the light-facing surface is a large velvet microstructure of 3 ⁇ m to 5 ⁇ m.
  • the first silicon nitride layer remaining on the backlight surface is removed by treating in a HF bath with a concentration of 8% wt at room temperature for 290s to 310s.
  • Step 4 In a chemical vapor deposition device, a first intrinsic amorphous silicon material layer, a phosphorus-doped N-type doped amorphous silicon material layer, a second silicon nitride layer, and a second intrinsic Amorphous silicon material layer: wherein the thickness of the first intrinsic amorphous silicon material layer is 5nm to 20nm, the thickness of the N-type doped amorphous silicon material layer is 10nm to 30nm, the thickness of the second silicon nitride layer is 170nm to 230nm, and the thickness of the second intrinsic amorphous silicon material layer is 10nm to 30nm.
  • Step 5 Use a laser to pattern the second intrinsic amorphous silicon material layer to expose the P+ region.
  • the laser type can be green light nanosecond, ultraviolet picosecond, green light picosecond, ultraviolet nanosecond;
  • Step 6 In a tank cleaning device, the silicon substrate formed with the first intrinsic amorphous silicon material layer, the N-type doped amorphous silicon material layer, the second silicon nitride layer and the second intrinsic amorphous silicon material layer is placed in an HF tank, the concentration of the HF solution is 7.5% to 8.5%, and is treated at room temperature for 190s to 210s to remove the exposed portion of the second silicon nitride layer.
  • the etching solution includes: KOH with a concentration of 0.4% to 0.6%, and H2O2 solution with a concentration of 0.1% to 0.2%, the temperature of the etching solution is 25°C, and the process time is 390s to 410s.
  • Step 7 In a chemical vapor deposition device, a third intrinsic silicon material layer and a boron-doped P-type doped amorphous silicon material layer are sequentially formed on the backlight surface. A fourth intrinsic amorphous silicon material layer and a third silicon nitride layer are sequentially formed on the light-facing surface.
  • the thickness of the third intrinsic amorphous silicon material layer is 5nm to 30nm
  • the thickness of the P-type doped amorphous silicon material layer is 10nm to 25nm
  • the thickness of the fourth intrinsic amorphous silicon material layer is 5nm to 20nm
  • the thickness of the third silicon nitride layer is 80nm to 105nm.
  • Step 8 Use a laser to pattern the third intrinsic silicon material layer and the P-type doped amorphous silicon material layer on the backlight surface, so that the remaining portion of the third intrinsic silicon material layer forms a second passivation layer, and the remaining portion of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer.
  • the laser type can be selected from green nanosecond, ultraviolet picosecond, green picosecond, and ultraviolet nanosecond.
  • Step 9 Use HF solution to remove the exposed portion of the second silicon nitride layer to expose a portion of the first doped semiconductor layer and to form an insulating layer on the portion of the second silicon nitride layer located on the first doped semiconductor layer.
  • concentration of the HF solution is 7% to 9%, and the treatment is performed at room temperature for 380s to 420s.
  • Step 10 In a chemical vapor deposition device, a transparent conductive material is formed covering the backlight surface.
  • the thickness of the transparent conductive material layer is 60nm to 100nm.
  • Step 11 Use a laser to etch the lateral junction between the first doped semiconductor layer and the second doped semiconductor layer to remove the local transparent conductive material layer, the local second passivation layer and the local second doped semiconductor layer, so that the portion of the transparent conductive material layer located on the first doped semiconductor layer forms a first transparent conductive layer, and the portion of the transparent conductive material layer located on the second doped semiconductor layer forms a second transparent conductive layer.
  • Step 12 Form the first electrode and the second electrode by screen printing or other processes. The final structure is shown in FIG1 .
  • Step 1 Place the N-type silicon wafer or P-type silicon wafer into a tank-type polishing and cleaning machine for polishing.
  • the polishing solution is a KOH solution with a concentration of 5.5% to 6.5%.
  • the temperature of the polishing solution is 81°C to 87°C.
  • the process time is 290s to 310s.
  • the surface morphology of the silicon substrate is a square structure with a size of 19 ⁇ m to 23 ⁇ m, and the reflectivity of the backlight surface of the silicon substrate after the polishing process is 40% to 44%.
  • Step 2 In a low-pressure chemical vapor deposition furnace, a tunneling oxide material layer covering the backlight surface of the silicon substrate and an intrinsic polysilicon material layer located on the tunneling oxide material layer are formed.
  • the thickness of the tunneling oxide material layer is 1.2nm to 1.8nm
  • the thickness of the intrinsic polysilicon material layer is 70nm to 170nm.
  • a passivation material layer and a polysilicon material layer are formed on the side and light-facing surface of the silicon substrate in sequence.
  • Step 3 In a phosphorus diffusion furnace, phosphorus is doped into the intrinsic polysilicon material layer, so that the intrinsic polysilicon material layer forms an N-type doped polysilicon material layer.
  • the diffusion square resistance of the N-type doped polysilicon material layer is 70 ⁇ /sq to 110 ⁇ /sq.
  • a phosphorus silicon glass layer is formed on the N-type doped polysilicon material layer and the coated polysilicon material layer.
  • Step 4 Using a plasma chemical vapor deposition setup, a silicon nitride layer is formed covering the backlight surface.
  • the thickness of the silicon nitride layer is 40nm to 60nm, and its refractive index is 2.3% to 2.5%.
  • Step 5 Use a laser to pattern the silicon nitride layer on the backlight surface to expose the area of the backlight surface corresponding to the P+ region.
  • the laser type can be green light nanosecond, ultraviolet picosecond, green light picosecond, ultraviolet nanosecond.
  • Step 6 In the tank cleaning machine, the formed structure enters the HF tank to remove the phosphorus silicon glass The part of the glass layer exposed outside the silicon nitride on the backlight side.
  • the concentration of the HF solution is 0.5% to 1.5%, and it is treated at room temperature for 25s to 35s. Then, it enters the alkaline tank for texturing treatment to texturize the exposed areas on the light-facing side and the backlight side.
  • the texturing solution includes KOH with a concentration of 2.5% to 3.5%, and a texturing additive solution.
  • the temperature of the texturing solution is 80°C to 84°C, and the process time is 570s to 630s.
  • the texturing etching amount is 0.5g to 0.7g.
  • the reflectivity of the light-facing side is 9% to 11%
  • the base width of the light-facing side is a small velvet microstructure of 1 ⁇ m to 3 ⁇ m.
  • Step 7 In a plasma enhanced atomic layer deposition device, an aluminum oxide layer and a silicon nitride layer are sequentially formed on the light-facing surface.
  • the thickness of the aluminum oxide layer is 5nm to 15nm
  • the thickness of the silicon nitride layer is 70nm to 110nm. Then, the exposed area of the backlight surface is polished by treating it in a 1%wt HF solution for 30s.
  • Step 8 In a chemical vapor deposition device, an intrinsic amorphous silicon material layer and a boron-doped P-type doped amorphous silicon material layer covering the backlight surface are sequentially formed, wherein the thickness of the intrinsic amorphous silicon material layer is 5nm to 30nm, and the thickness of the P-type doped amorphous silicon layer is 10nm to 25nm.
  • Step 9 Use a laser to pattern the intrinsic amorphous silicon material layer and the P-type doped amorphous silicon material layer so that the remaining portion of the intrinsic amorphous silicon material layer forms a second passivation layer, and the remaining portion of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer.
  • the laser type can be green nanosecond, ultraviolet picosecond, green picosecond, ultraviolet nanosecond.
  • Step 10 Use HF solution to remove the exposed part of the silicon nitride layer to expose a part of the first doped semiconductor layer, wherein the concentration of the HF solution is 7% to 9% and the treatment is carried out at room temperature for 380s to 420s.
  • Step 11 In a physical vapor deposition device, a transparent conductive material layer is formed covering the backlight surface, and the thickness of the transparent conductive material layer is 60nm to 100nm.
  • Step 12 Use a laser etching process to remove the local transparent conductive material layer, the second doped semiconductor layer and the second passivation layer to achieve insulation between the N+ region and the P+ region.
  • Step 13 Form the first electrode and the second electrode by screen printing or other processes. The final structure is shown in FIG2 .
  • Table 1 tests the back-contact cells manufactured by the above-mentioned Example 1, Comparative Example 1 and Comparative Example 2, and compares the parameters of the above-mentioned three back-contact cells.
  • the insulating layer 161 is at least located between the second passivation layer 17 and the first doped semiconductor layer 141. Moreover, along the direction away from the silicon substrate 11, the insulating layer 161 includes an aluminum oxide layer and a silicon nitride layer. As shown in FIG1 , in the back contact cell manufactured in Comparative Example 1, the insulating layer 161 of silicon nitride material is formed only at the longitudinal junction between the first doped semiconductor layer 141 and the second passivation layer 17.
  • the doped glass layer and the insulating layer 161 located on the doped glass layer are formed only at the longitudinal junction between the first doped semiconductor layer 141 and the second passivation layer 17.
  • Table 1 it can be seen from Table 1 that the parallel resistance and short-circuit current of the back-contact battery manufactured in Example 1 are higher than the parallel resistance and short-circuit current corresponding to the back-contact batteries manufactured in Comparative Example 1 and Comparative Example 2, respectively, and the open circuit voltage of the back-contact battery manufactured in Example 1 is lower than the open circuit voltage corresponding to the back-contact batteries manufactured in Comparative Example 1 and Comparative Example 2, which is beneficial to reduce the leakage risk of the back-contact battery, and thus makes the conversion efficiency of the back-contact battery manufactured in Example 1 higher than the conversion efficiency corresponding to the back-contact batteries manufactured in Comparative Example 1 and Comparative Example 2.
  • an aluminum oxide layer and a silicon nitride layer located on the aluminum oxide layer are sequentially formed on the light-facing surface along the direction away from the silicon substrate.
  • an amorphous silicon passivation layer and a silicon nitride layer located on the amorphous silicon passivation layer are sequentially formed on the light-facing surface along the direction away from the silicon substrate. Based on this, since amorphous silicon has light absorption characteristics, the amorphous silicon passivation layer located on the light-facing surface will produce parasitic absorption, resulting in a reduction in the light incident on the silicon substrate.
  • the amorphous silicon passivation layer is difficult to match with the light-facing surface with a small velvet structure, while the aluminum oxide layer can match with the light-facing surface with a small velvet structure.
  • the light-facing surface tower base width and light-facing surface reflectivity of the back-contact cell manufactured in Example 1 are respectively smaller than the light-facing surface tower base width and light-facing surface reflectivity corresponding to the back-contact cell manufactured in Comparative Example 1, thereby facilitating the enhancement of the light trapping effect of the light-facing surface, making it more More light is incident on the silicon substrate, which ultimately makes the conversion efficiency of the back-contact cell manufactured in Example 1 greater than the corresponding conversion efficiency of the back-contact cell manufactured in Comparative Example 1.
  • the first passivation layer 121 and the first doped semiconductor layer 141 constitute a tunneling passivation contact structure.
  • the second passivation layer 17 and the second doped semiconductor layer 18 constitute a heterogeneous contact structure.
  • the first passivation layer 121 and the first doped semiconductor layer 141 constitute a heterogeneous contact structure.
  • the second passivation layer 17 and the second doped semiconductor layer 18 also constitute a heterogeneous contact structure.
  • the chemical properties of the tunneling passivation contact structure are more stable, so after the laser film opening process, the passivation effect on the tunneling passivation contact structure is relatively small.
  • the N+ region laser process window of the back contact battery manufactured in Example 1 is larger than the N+ region laser process window corresponding to the back contact battery manufactured in Comparative Example 1.

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Abstract

本公开公开了一种背接触电池及其制造方法、光伏组件，涉及太阳能电池技术领域，用于同时防止第一掺杂半导体层和第二掺杂半导体层的横向界面和纵向界面处产生漏电。所述背接触电池包括：硅基底、第一钝化层、第一掺杂半导体层、第二钝化层、第二掺杂半导体层和绝缘层。第一钝化层和第一掺杂半导体层依次层叠设置于硅基底具有的背光面上。第二钝化层和第二掺杂半导体层依次层叠设置于背光面上。层叠设置的第二钝化层和第二掺杂半导体层覆盖层叠设置的第一钝化层和第一掺杂半导体层的部分区域，第二掺杂半导体层和第一掺杂半导体层的导电类型相反。绝缘层至少位于第二钝化层和第一掺杂半导体层之间，用于将第二钝化层和第一掺杂半导体层间隔开。

Description

一种背接触电池及其制造方法、光伏组件
相关申请的交叉引用
本公开要求在2022年11月29日提交中国专利局、申请号为202211516779.3、名称为“一种背接触电池及其制造方法、光伏组件”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及太阳能电池技术领域，尤其涉及一种背接触电池及其制造方法、光伏组件。
背景技术
钝化背接触式太阳能电池指正电极和负电极都处于电池的背面，正面没有金属电极遮挡，并且具有钝化接触结构的太阳能电池。因钝化背接触式太阳能电池具有较大的吸光面积、以及较低的载流子背面复合速率等优势，使其受到光伏学术界及工业界的广泛关注，成为高效太阳能电池技术的热门发展方向。
但是，在现有的钝化背接触式太阳能电池中，载流子收集类型相反的两类钝化接触结构中的一类覆盖在另一类的部分区域上时，二者难以通过较薄的钝化层隔离开，漏电流风险较大，进而影响钝化背接触式太阳能电池的性能进一步提高。
发明内容
本公开的目的在于提供一种背接触电池及其制造方法、光伏组件，用于同时防止第一掺杂半导体层和第二掺杂半导体层的横向界面和纵向界面处产生漏电，利于提高背接触电池的光电转换效率。
第一方面，本公开提供了一种背接触电池，该背接触电池包括：硅基底，沿硅基底的厚度方向，依次层叠设置于硅基底具有的背光面上的第一钝化层和第一掺杂半导体层。沿硅基底的厚度方向，依次层叠设置于背光面上的第二钝化层和第二掺杂半导体层。其中，层叠设置的第二钝化层和第二掺杂半 导体层覆盖层叠设置的第一钝化层和第一掺杂半导体层的部分区域，第二掺杂半导体层和第一掺杂半导体层的导电类型相反。设置于背光面上的绝缘层。绝缘层至少位于第二钝化层和第一掺杂半导体层之间，用于将第二钝化层和第一掺杂半导体层间隔开。
采用上述技术方案的情况下，沿硅基底的厚度方向，第一钝化层和第一掺杂半导体层依次层叠设置于背光面上。其中，由第一钝化层和第一掺杂半导体层形成的钝化接触结构可以实现优异的界面钝化和载流子选择性收集，利于提高背接触电池的光电转换效率。同理，由第二钝化层和第二掺杂半导体层形成的钝化接触结构也具有上述第一钝化层和第一掺杂半导体层具有的有益效果，此处不再赘述。
另外，上述层叠设置的第二钝化层和第二掺杂半导体层覆盖层叠设置的第一钝化层和第一掺杂半导体层的部分区域。并且，本公开提供的背接触电池还包括设置于背光面上的绝缘层。该绝缘层至少位于第二钝化层和第一掺杂半导体层之间，用于将第二钝化层和第一掺杂半导体层间隔开。可以理解的是，该绝缘层不仅可以沿着硅基底的厚度方向将第二钝化层和第一掺杂半导体层间隔开，还可以沿平行于背光面的方向将第二钝化层和第一掺杂半导体层间隔开。在此情况下，绝缘层可以避免第二掺杂半导体层中的载流子通过隧穿效应穿过第二钝化层进入第一掺杂半导体层，同时也可以避免第一掺杂半导体层中的载流子通过隧穿效应穿过第二钝化层进入第二掺杂半导体层，也就是说，绝缘层可以阻挡第二掺杂半导体层收集的载流子与导电类型相反的第一掺杂半导体层收集的载流子发生复合，从而实现同时防止第一掺杂半导体层和第二掺杂半导体层的横向界面和纵向界面处产生漏电，进而利于提高背接触电池的光电转换效率。
作为一种可能的实现方式，上述第一钝化层为隧穿钝化层，第一掺杂半导体层为掺杂多晶硅层。
采用上述技术方案的情况下，在实际的制造过程中，为仅在背光面的特定区域上形成第一钝化层和第一掺杂半导体层，需要对制造第一钝化层的钝化材料层、以及制造第一掺杂半导体层的掺杂半导体材料层进行图案化处理。而与光刻结合湿法刻蚀、以及油墨印刷结合湿法刻蚀实现图案化处理的方式 相比，采用激光刻蚀工艺实现图案化处理的成本较低，更适于量产。并且，因层叠设置的第二钝化层和第二掺杂半导体层覆盖层叠设置的第一钝化层和第一掺杂半导体层的部分区域，故在实际制造过程中，层叠设置的第一钝化层和第一掺杂半导体层的形成步骤早于层叠设置的第二钝化层和第二掺杂半导体层的形成步骤。在上述情况下，因非晶硅材料在高温下容易形成多晶硅或单晶硅，而隧穿钝化材料和多晶硅在高温下的化学性质相对稳定，故与层叠设置的本征非晶硅层和掺杂非晶硅层相比，层叠设置的隧穿钝化层和掺杂多晶硅层对高温的激光热损伤敏感程度较小，在激光开膜工艺时可以减小对钝化效果的影响，进一步增大了工艺窗口，降低了工艺难度，因此当第一钝化层为隧穿钝化层，且第一掺杂半导体层为掺杂多晶硅层时，可以采用激光刻蚀工艺实现对制造第一钝化层的钝化材料层、以及制造第一掺杂半导体层的掺杂半导体材料层进行图案化处理，从而能够在降低背接触电池制造成本的同时，确保第一钝化层和第一掺杂半导体层具有良好的成膜质量，利于提高背接触电池的良率和电学性能。
另外，隧穿钝化层和掺杂多晶硅层均可以采用低压化学气相沉积设备沉积形成。而本征非晶硅层和掺杂非晶硅层需要采用化学气相沉积设备沉积形成。基于此，因低压化学气相沉积设备的成本低于化学气相沉积设备的成本，故当第一钝化层也可以为隧穿钝化层，且第一掺杂半导体层也可以为掺杂多晶硅层时，可以通过低压化学气相沉积设备沉积用于制造第一钝化层的钝化材料层、以及用于制造第一掺杂半导体层的掺杂半导体材料层，从而能够降低背接触电池的制造成本。
作为一种可能的实现方式，上述第二钝化层为本征非晶硅层，第二掺杂半导体层为掺杂非晶硅层。
采用上述技术方案的情况下，本征非晶硅层具有比隧穿钝化层更好的钝化效果。基于此，与第二钝化层为隧穿钝化层、且第二掺杂半导体层为掺杂多晶硅层相比，当第二钝化层为本征非晶硅层、且第二掺杂半导体层时，可以进一步降低导电类型相反的载流子在硅基底与第二钝化层之间的界面处的复合速率，进一步提高背接触电池的光电转换效率。
作为一种可能的实现方式，上述背接触电池还包括：沿背离硅基底的方 向，依次层叠设置于硅基底具有的向光面上的氧化铝层和氮化硅层。或，背接触电池还包括：沿背离硅基底的方向，依次层叠设置于硅基底具有的向光面上的氧化硅层和氮化硅层。
采用上述技术方案的情况下，层叠设置的氧化铝层和氮化硅层可以对向光面进行钝化，降低载流子在向光面处的复合速率，进一步提高背接触电池的光电转换效率。并且，氮化硅可以起到减反的作用，有利于使得更多的光线由向光面折射至硅基底内，进一步提高背接触电池对光线的利用率。在此基础上，采用沉积工艺在具有尺寸较小的绒面结构的向光面上形成非晶硅材料的钝化层时，容易在绒面结构顶部发生外延生长，使得非晶硅材料位于绒面结构顶部的部分的厚度比非晶硅材料位于绒面结构基部的部分的厚度大，而导致形成的非晶硅材料的钝化层各区域的厚度不一致，降低了该钝化层对向光面的钝化效果，同时还会影响向光面上其它膜层的形成。而与非晶硅材料的钝化层相比，在小绒面结构的向光面上沉积氧化铝材料的钝化层时不会发生外延生长，使得氧化铝材料的钝化层的钝化效果较好，因而硅基底向光面的绒面可以选用金字塔尺寸较小的绒面，而尺寸较小的绒面有更好的陷光效果，进一步提高硅基底对光的吸收。另外，上述层叠设置的氧化硅层和氮化硅层具有的有益效果可以参考前文所述的层叠设置的氧化铝层和氮化硅层的有益效果分析，此处不再赘述。
再者，氧化铝层、氮化硅层和氧化硅层均可以采用原子层沉积设备沉积形成。而本征非晶硅层需要采用化学气相沉积设备沉积形成。基于此，因原子层沉积设备的成本低于化学气相沉积设备的成本，故当在向光面上形成氧化铝层(或氧化硅层)和氮化硅层作为钝化减反层时，可以通过原子层沉积设备沉积在向光面上形成氧化铝(或氧化硅)和氮化硅层，从而能够降低背接触电池的制造成本。
作为一种可能的实现方式，沿背离硅基底的方向，绝缘层包括依次层叠设置的氧化铝层和氮化硅层。或，沿背离硅基底的方向，绝缘层包括依次层叠设置的氧化硅层和氮化硅层。
采用上述技术方案的情况下，氧化铝层、氮化硅层和氧化硅层均具有良好的介电特性，利于绝缘层将第二钝化层与第一掺杂半导体层间隔开，进而 可以提高背接触电池的并联电阻，降低了背接触电池的漏电风险。并且，氧化铝、氮化硅和氧化硅还可以用于制造位于向光面上具有钝化作用和/或减反射作用的膜层。基于此，当绝缘层包括层叠设置的氧化铝层和氮化硅层，或层叠设置的氧化硅层和氮化硅层时，绝缘层的材料与钝化减反层的材料相同，从而可以在形成绝缘层的同时，在向光面上形成钝化减反层，利于简化背接触电池的制造过程，提高背接触电池制造效率。
作为一种可能的实现方式，上述绝缘层的厚度为75nm至125nm。绝缘层的厚度在此范围内，可以防止因绝缘层的厚度较小而可能导致第二掺杂半导体层收集的部分载流子可以通过隧穿效应依次穿过第二钝化层和绝缘层与导电类型相反的第一掺杂半导体层收集的载流子发生复合，确保绝缘层具有良好的绝缘性能。同时，绝缘层不仅沿着硅基底的方向将第二钝化层与第一掺杂半导体层间隔开，还可以沿着平行于硅基底背光面的方向将第二钝化层与第一掺杂半导体层间隔开，因此绝缘层位于第二钝化层和第一掺杂半导体层的纵向交界处的部分、第一掺杂半导体层和第二掺杂半导体层沿着平行于背光面的方向分布于背光面的上方。在此情况下，可以理解的是，当绝缘层的厚度较大时，绝缘层位于第二钝化层和第一掺杂半导体层的纵向交界处的部分的横截面积较大，而背光面的表面积为定值，因此当绝缘层的厚度为75nm至125nm时，还可以防止因绝缘层的厚度较大，而导致第一掺杂半导体层和第二掺杂半导体层中的至少一者的横截面积减小，进而影响其载流子收集能力，确保硅基底吸收光子后所产生的载流子及时被第一掺杂半导体层和第二掺杂半导体层所导出，进一步提高背接触电池的光电转换效率。
作为一种可能的实现方式，上述硅基底具有的向光面为绒面。绒面的塔基宽度为1μm至3μm。
采用上述技术方案的情况下，在一定的范围内，绒面的塔基宽度越小，绒面的陷光作用越好。基于此，当硅基底的向光面为绒面、且绒面的塔基宽度为1μm至3μm时，向光面的塔基宽度相对较小，该向光面具有较高的陷光效果。在此情况下，在实际的应用过程中，可以通过在向光面上形成氧化铝、氧化硅等非晶硅材料、且与塔基宽度较小的绒面相匹配的钝化反射层，从而能够使得更多的光线通过向光面透射至硅基底内，进一步提高背接触电 池的光电转换效率。
第二方面，本公开还提供了一种光伏组件，该光伏组件包括上述第一方面及其各种实现方式提供的背接触电池。
本公开中第二方面及其各种实现方式的有益效果，可以参考第一方面及其各种实现方式中的有益效果分析，此处不再赘述。
第三方面，本公开还提供了一种背接触电池的制造方法，该背接触电池的制造方法包括：首先，提供一硅基底。接下来，沿硅基底的厚度方向，形成依次层叠设置于硅基底具有的背光面上的第一钝化层和第一掺杂半导体层。接下来，在背光面上形成绝缘层。接下来，沿硅基底的厚度方向，形成依次层叠设置于背光面上的第二钝化层和第二掺杂半导体层。其中，层叠设置的第二钝化层和第二掺杂半导体层覆盖层叠设置的第一钝化层和第一掺杂半导体层的部分区域，第二掺杂半导体层和第一掺杂半导体层的导电类型相反。绝缘层至少位于第二钝化层和第一掺杂半导体层之间，用于将第二钝化层和第一掺杂半导体层间隔开。
本公开中第三方面的有益效果，可以参考第一方面的有益效果分析，此处不再赘述。
作为一种可能的实现方式，形成层叠设置的第一钝化层和第一掺杂半导体层，包括：首先，依次形成覆盖在背光面上的钝化材料层、以及位于钝化材料层上的本征半导体材料层。接下来，对本征半导体材料层进行扩散处理，以使得本征半导体材料层形成掺杂半导体材料层、以及在掺杂半导体材料层上形成掺杂玻璃层。接下来，采用激光刻蚀工艺，去除位于掺杂半导体材料层上的部分掺杂玻璃层。其中，掺杂玻璃层的剩余部分形成掩膜层。接下来，在掩膜层的掩膜作用下，依次去除掺杂半导体材料层暴露在掩膜层之外的部分、以及钝化材料层暴露在掩膜层之外的部分，形成层叠设置的第一钝化层和第一掺杂半导体层。
采用上述技术方案的情况下，在实际的应用过程中，在对位于钝化材料层上的本征半导体材料层进行扩散处理时，本征半导体材料层转变为掺杂半导体材料层，且在掺杂半导体材料层的表面形成掺杂玻璃层，掺杂玻璃层例如可以为磷硅玻璃层(Phospho Silicate Glass，可缩写为PSG)或硼硅玻璃层 (Boro silicate Glass，可缩写为BSG)等。在此情况下，采用激光刻蚀工艺去除位于掺杂半导体材料层上的部分掺杂玻璃层后，该掺杂玻璃层的剩余部分可以形成掩膜层，从而无须额外形成氮化硅等其它掩膜层就能够实现对掺杂半导体材料层和钝化材料层的图案化处理，简化背接触电池的制造过程的同时，还可以降低背接触电池的制造成本。
作为一种可能的实现方式，形成层叠设置的第一钝化层和第一掺杂半导体层后，在背光面上形成绝缘层前，背接触电池的制造方法还包括：去除位于硅基底的向光面和侧面上的绕镀掺杂玻璃层、绕镀掺杂半导体材料层和绕镀钝化材料层。接下来，在掩膜层的掩膜作用下，对硅基底具有的向光面进行制绒处理，以使得向光面为绒面。去除掩膜层。
采用上述技术方案的情况下，如前文所述，在制绒处理过程中，所使用的掩膜层是采用激光刻蚀工艺，对扩散处理过程中形成在掺杂半导体材料层上的掺杂玻璃层进行图案化处理所获得，并非在获得层叠设置的第一钝化层和第一掺杂半导体层后而额外通过沉积等工艺形成的氮化硅等掩膜层，从而可以进一步简化背接触电池的制造过程，降低背接触电池的制造成本。
作为一种可能的实现方式，上述掺杂玻璃层的厚度为40nm至60nm。在此情况下，掺杂玻璃层的厚度在此范围内，可以防止因掺杂玻璃层的厚度较小使得以该掺杂玻璃层的剩余部分形成的掩膜层的保护作用较差，而导致难以在相应操作中保护位于其下方的第一掺杂半导体层和第一钝化层，确保第一掺杂半导体层和第一钝化层具有良好的成膜质量，提高背接触电池的良率。同时，还可以防止因掺杂玻璃层的厚度较大而导致制造效率降低、以及制造成本增大等问题，利于提升背接触电池的量产性。
作为一种可能的实现方式，上述扩散处理的扩散时间为60min至120min，扩散温度为800℃至900℃。该情况下具有的有益效果与前文所述的当掺杂玻璃层的厚度为40nm至60nm时的有益效果相似，可以参考上述，此处不再赘述。
作为一种可能的实现方式，形成层叠设置的第一钝化层和第一掺杂半导体层，包括：首先，依次形成覆盖在背光面上的钝化材料层、以及位于钝化材料层上的掺杂半导体材料层。接下来，采用激光刻蚀工艺，对掺杂半导体 材料层和钝化材料层进行图案化处理，形成层叠设置的第一钝化层和第一掺杂半导体层。其中，第一钝化层为隧穿钝化层，第一掺杂半导体层为掺杂多晶硅层。该情况下具有的有益效果可以参考前文所述的第一钝化层为隧穿钝化层，且第一掺杂半导体层为掺杂多晶硅层的有益效果分析，此处不再赘述。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为相关技术中钝化背接触式太阳能电池的一种结构纵向断面示意图；
图2为相关技术中钝化背接触式太阳能电池的另一种结构纵向断面示意图；
图3为本公开实施例提供的一种背接触电池的制造过程中的结构示意图一；
图4为本公开实施例提供的一种背接触电池的制造过程中的结构示意图二；
图5为本公开实施例提供的一种背接触电池的制造过程中的结构示意图三；
图6为本公开实施例提供的一种背接触电池的制造过程中的结构示意图四；
图7为本公开实施例提供的一种背接触电池的制造过程中的结构示意图五；
图8为本公开实施例提供的一种背接触电池的制造过程中的结构示意图六；
图9为本公开实施例提供的一种背接触电池的制造过程中的结构示意图七；
图10为本公开实施例提供的一种背接触电池的制造过程中的结构示意图八；
图11为本公开实施例提供的一种背接触电池的制造过程中的结构示意图九；
图12为本公开实施例提供的一种背接触电池的制造过程中的结构示意图十；
图13为本公开实施例提供的一种背接触电池的制造过程中的结构示意图十一；
图14为本公开实施例提供的一种背接触电池的制造过程中的结构示意图十二；
图15为本公开实施例提供的一种背接触电池的制造过程中的结构示意图十三；
图16为本公开实施例提供的一种背接触电池的制造过程中的结构示意图十四。
附图标记：
11为硅基底，12为钝化材料层，121为第一钝化层，13为本征半导体材料层，14为掺杂半导体材料层，141为第一掺杂半导体层，15为掺杂玻璃层，151为掩膜层，16为绝缘材料层，161为绝缘层，17为第二钝化层，18为第二掺杂半导体层，19为氧化铝层，20为氮化硅层，21为透明导电材料层，211为第一透明导电层，212为第二透明导电层，22为第一电极，23为第二电极。
具体实施例
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并 且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。为了使本公开所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本公开进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本公开，并不用于限定本公开。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。“若干”的含义是一个或一个以上，除非另有明确具体的限定。
在本公开的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
钝化背接触式太阳能电池指正电极和负电极都处于电池的背面，正面没有金属电极遮挡，并且具有钝化接触结构的太阳能电池。因钝化背接触式太阳能电池具有较大的吸光面积、以及较低的载流子背面复合速率等优势，使其受到光伏学术界及工业界的广泛关注，成为高效太阳能电池技术的热门发展方向。
具体的，如图1和图2所示，相关技术中的钝化背接触式太阳能电池通常包括硅基底11、第一钝化接触结构和第二钝化接触结构。其中，沿平行于硅基底11具有的背光面的方向，上述第一钝化接触结构和第二钝化接触结构交替分布在背光面上。并且第二钝化接触结构覆盖第一钝化接触结构的部分 区域上。具体的，沿背离硅基底11的方向，第一钝化接触结构和第二钝化接触结构均包括依次层叠设置的钝化层和掺杂半导体层。基于此，在钝化背接触式太阳能电池处于工作过程中，相应类型的载流子可以通过隧穿效应分别穿过第一钝化接触结构和第二钝化接触结构包括的钝化层，并经第一钝化接触结构和第二钝化接触结构包括的相应掺杂半导体层传导至相应电极，从而形成光电流。
但是，如图1和图2所示，为了降低载流子的隧穿电阻，相关技术中的钝化背接触式太阳能电池在设计时，通常上述第一钝化接触结构和第二钝化接触结构包括的钝化层的厚度均较小。而第一钝化接触结构和第二钝化接触结构包括的掺杂半导体层的导电类型相反。在此情况下，当第二钝化接触结构覆盖第一钝化接触结构的部分区域时，即使沿着硅基底的厚度方向，在第一钝化接触结构和第二钝化接触结构的纵向交界处设置绝缘层，但是绝缘层只能在纵向将第一钝化接触结构和第二钝化接触结构间隔开，在第一钝化接触结构和第二钝化接触结构的横向交界处，二者仅通过钝化层间隔开(例如通过本征半导体层隔离开)，然而较薄的钝化层难以实现第一钝化接触结构的掺杂半导体层中载流子和第二钝化接触结构的掺杂半导体层中载流子的隔离，导致导电类型相反的载流子在二者的横向界面处的复合速率较高，存在漏电风险，进而影响钝化背接触式太阳能电池的性能进一步提高。
为了解决上述技术问题，第一方面，本公开实施例提供了一种背接触电池。如图13所示，该背接触电池包括：硅基底11、第一钝化层121、第一掺杂半导体层141、第二钝化层17、第二掺杂半导体层18和绝缘层161。
如图13所示，沿硅基底11的厚度方向，第一钝化层121和第一掺杂半导体层141依次层叠设置于硅基底11具有的背光面上。沿硅基底11的厚度方向，第二钝化层17和第二掺杂半导体层18依次层叠设置于背光面上。其中，层叠设置的第二钝化层17和第二掺杂半导体层18覆盖层叠设置的第一钝化层121和第一掺杂半导体层141的部分区域，第二掺杂半导体层18和第一掺杂半导体层141的导电类型相反。绝缘层161设置于背光面上。绝缘层161至少位于第二钝化层17和第一掺杂半导体层141之间，用于将第二钝化层17和第一掺杂半导体层141间隔开。
具体来说，从导电类型方面来讲，上述硅基底可以为N型硅基底或P型硅基底。从结构方面来讲，上述硅基底的具体结构可以根据实际应用场景设置。例如：如图3所示，上述硅基底11可以为其上未形成有任何膜层、且背光面和向光面均为抛光面的硅衬底。或者，如图13所示，上述硅基底11还可以为其上未形成有任何膜层、且向光面为绒面的硅衬底。其中，相比于抛光面，因绒面结构具有良好的陷光作用，故在硅基底11的向光面为绒面的情况下，可以使得更多的光线由向光面折射至硅基底11内，进而利于提高背接触电池的光电转换效率。具体的，在硅基底11的向光面为绒面的情况下，该绒面的塔基宽度可以根据实际需求进行设置，此处不做具体限定。
对于上述第一钝化层和第一掺杂半导体层来说，第一钝化层和第一掺杂半导体层的材料和厚度、以及第一掺杂半导体层内掺杂元素的掺杂种类和掺杂浓度可以根据实际需求进行设置，只要能够应用至本公开实施例提供的背接触电池中均可。
例如：第一钝化层可以为本征非晶硅层，第一掺杂半导体层可以为掺杂非晶硅层。此时，第一钝化层和第一掺杂半导体层可以组成异质接触结构。基于此，因异质接触结构具有优于隧穿钝化接触结构的钝化效果，故在层叠设置的第一钝化层和第一掺杂半导体层组成异质接触结构的情况下，可以进一步降低硅基底与第一钝化层界面处的载流子复合速率，利于提高背接触电池的光电转换效率。
又例如：第一钝化层也可以为隧穿钝化层，第一掺杂半导体层也可以为掺杂多晶硅层。在此情况下，在实际的制造过程中，如图5至图7所示，为仅在背光面的特定区域上形成第一钝化层121和第一掺杂半导体层141，需要对制造第一钝化层121的钝化材料层12、以及制造第一掺杂半导体层141的掺杂半导体材料层14进行图案化处理。而与光刻结合湿法刻蚀、以及油墨印刷结合湿法刻蚀实现图案化处理的方式相比，采用激光刻蚀工艺实现图案化处理的成本较低，更适于量产。并且，如图13所示，因层叠设置的第二钝化层17和第二掺杂半导体层18覆盖层叠设置的第一钝化层121和第一掺杂半导体层141的部分区域，故在实际制造过程中，层叠设置的第一钝化层121和第一掺杂半导体层141的形成步骤早于层叠设置的第二钝化层17和第二掺 杂半导体层18的形成步骤。在上述情况下，因非晶硅材料在高温下容易形成多晶硅或单晶硅，而隧穿钝化材料和多晶硅在高温下的化学性质相对稳定，故与层叠设置的本征非晶硅层和掺杂非晶硅层相比，层叠设置的隧穿钝化层和掺杂多晶硅层对高温的激光热损伤敏感程度较小，在激光开膜工艺时可以减小对钝化效果的影响，进一步增大了工艺窗口，降低了工艺难度，因此当第一钝化层121为隧穿钝化层，且第一掺杂半导体层141为掺杂多晶硅层时，可以采用激光刻蚀工艺实现对制造第一钝化层121的钝化材料层12、以及制造第一掺杂半导体层141的掺杂半导体材料层14进行图案化处理，从而能够在降低背接触电池制造成本的同时，确保第一钝化层121和第一掺杂半导体层141具有良好的成膜质量，利于提高背接触电池的良率和电学性能。
另外，隧穿钝化层和掺杂多晶硅层均可以采用低压化学气相沉积设备沉积形成。而本征非晶硅层和掺杂非晶硅层需要采用化学气相沉积设备沉积形成。基于此，因低压化学气相沉积设备的成本低于化学气相沉积设备的成本，故当第一钝化层也可以为隧穿钝化层，且第一掺杂半导体层也可以为掺杂多晶硅层时，可以通过低压化学气相沉积设备沉积用于制造第一钝化层的钝化材料层、以及用于制造第一掺杂半导体层的掺杂半导体材料层，从而能够降低背接触电池的制造成本。
具体的，上述隧穿钝化层的材料可以包括氧化硅、氧化铝、氧化钛、二氧化铪、氧化镓、五氧化二钽、五氧化铌、氮化硅、碳氮化硅、氮化铝、氮化钛、氮碳化钛中的一种或多种。隧穿钝化层的具体材料可以根据实际需求进行设置。
对于上述第二钝化层和第二掺杂半导体层来说，第二钝化层和第二掺杂半导体层的材料和厚度、以及第二掺杂半导体层内掺杂元素的掺杂种类和掺杂浓度可以根据实际需求进行设置。其中，第二掺杂半导体层和第一掺杂半导体层的导电类型相反。基于此，在实际的应用过程中，可以是第二掺杂半导体为掺杂有硼或其它元素的P型掺杂半导体层，第一掺杂半导体层为掺杂有磷或其它元素的N型掺杂半导体层。或者，也可以是第二掺杂半导体层为N型掺杂半导体层，第一掺杂半导体层为P型掺杂半导体层。
另外，上述第二钝化层可以为隧穿钝化层，且第二掺杂半导体层可以为 掺杂多晶硅层。或者，第二钝化层也可以为本征非晶硅层，且第二掺杂半导体层也可以为掺杂非晶硅层。
值得注意的是，在第一钝化层为隧穿钝化层、第二掺杂半导体层为掺杂多晶硅层，并且第二钝化层为本征非晶硅层、以及第二掺杂半导体层为掺杂非晶硅层的情况下，不仅可以采用激光刻蚀工艺实现对制造第一钝化层的钝化材料层、以及制造第一掺杂半导体层的掺杂半导体材料层进行图案化处理，确保第一钝化层和第一掺杂半导体层具有良好的成膜质量，并增大工艺窗口的同时，因本征非晶硅层具有比隧穿钝化层更好的钝化效果。基于此，与第二钝化层为隧穿钝化层、且第二掺杂半导体层为掺杂多晶硅层相比，当第二钝化层为本征非晶硅层、且第二掺杂半导体层时，可以进一步降低导电类型相反的载流子在硅基底与第二钝化层之间的界面处的复合速率，进一步提高背接触电池的光电转换效率。
再者，层叠设置的第二钝化层和第二掺杂半导体层覆盖层叠设置的第一钝化层和第一掺杂半导体层的面积可以根据实际应用场景设置，此处不做具体限定。
对于上述绝缘层来说，该绝缘层可以是由一种或多种绝缘材料制造形成的单层结构，或者绝缘层也可以是由多种绝缘材料制造形成的多层复合结构。具体的，绝缘层的具体结构可以根据实际需求进行设置。上述绝缘材料可以为任一具有绝缘性能的材料。另外，该绝缘层的厚度、以及绝缘层在背光面上的形成范围可以根据实际需求进行设置，只要能够使得绝缘层至少位于第二钝化层和第一掺杂半导体层之间，并能够通过该绝缘层将第二钝化层和第一掺杂半导体层间隔开均可。
由上述内容可知，如图13所示，该绝缘层161不仅可以沿着硅基底11的厚度方向将第二钝化层17和第一掺杂半导体层141间隔开，还可以沿平行于背光面的方向将第二钝化层17和第一掺杂半导体层141间隔开。在此情况下，绝缘层161可以避免第二掺杂半导体层18中的载流子通过隧穿效应穿过第二钝化层17进入第一掺杂半导体层141，同时也可以避免第一掺杂半导体层141中的载流子通过隧穿效应穿过第二钝化层17进入第二掺杂半导体层18，也就是说，绝缘层161可以阻挡第二掺杂半导体层18收集的载流子与导电类 型相反的第一掺杂半导体层141收集的载流子发生复合，从而实现同时防止第一掺杂半导体层141和第二掺杂半导体层18的横向界面和纵向界面处产生漏电，进而利于提高背接触电池的光电转换效率。
作为一种可能的实现方式，上述绝缘层的厚度为75nm至125nm。在此情况下，该绝缘层的厚度在此范围内，可以防止因绝缘层的厚度较小而可能导致第二掺杂半导体层收集的部分载流子可以通过隧穿效应依次穿过第二钝化层和绝缘层与导电类型相反的第一掺杂半导体层收集的载流子相复合，确保绝缘层具有良好的绝缘性能。同时，如图13所示，绝缘层161不仅沿着硅基底11的厚度方向将第二钝化层17与第一掺杂半导体层141间隔开，还可以沿着平行于硅基底11背光面的方向将第二钝化层17与第一掺杂半导体层141间隔开，因此绝缘层161位于第二钝化层17和第一掺杂半导体层141的纵向交界处的部分、第一掺杂半导体层141和第二掺杂半导体层18沿着平行于背光面的方向分布于背光面的上方。在此情况下，可以理解的是，当绝缘层161的厚度较大时，绝缘层161位于第二钝化层17和第一掺杂半导体层141的纵向交界处的部分的横截面积较大，而背光面的表面积为定值，因此当绝缘层161的厚度为75nm至125nm时，还可以防止因绝缘层161的厚度较大，而导致第一掺杂半导体层141和第二掺杂半导体层18中的一者的横截面积减小，进而影响其载流子收集能力，确保硅基底11吸收光子后所产生的载流子及时被第一掺杂半导体层141和第二掺杂半导体层18所导出，进一步提高背接触电池的光电转换效率。
当然，也可以根据不同的应用场景要求，将绝缘层的厚度设置为其它合适数值。
作为一种可能的实现方式，如图13所示，上述背接触电池还包括：沿背离硅基底11的方向，依次层叠设置于硅基底11具有的向光面上的氧化铝层19和氮化硅层20。或，背接触电池还包括：沿背离硅基底的方向，依次层叠设置于硅基底具有的向光面上的氧化硅层和氮化硅层。
具体的，上述氧化铝层、氮化硅层和氧化硅层的厚度可以根据实际需求进行设置，此处不做具体限定。
采用上述技术方案的情况下，层叠设置的氧化铝层和氮化硅层可以对向 光面进行钝化，降低载流子在向光面处的复合速率，进一步提高背接触电池的光电转换效率。并且，氮化硅层可以起到减反的作用，有利于使得更多的光线由向光面折射至硅基底内，进一步提高背接触电池对光线的利用率。在此基础上，采用沉积工艺在具有尺寸较小的绒面结构的向光面上形成非晶硅材料的钝化层时，容易在绒面结构顶部发生外延生长，使得非晶硅材料位于绒面结构顶部的部分的厚度比非晶硅材料位于绒面结构基部的部分的厚度大，而导致形成的非晶硅材料的钝化层各区域的厚度不一致，降低了该钝化层对向光面的钝化效果，同时还会影响向光面上其它膜层的形成。而与非晶硅材料的钝化层相比，在小绒面结构的向光面上沉积氧化铝材料的钝化层时不会发生外延生长，使得氧化铝材料的钝化层的钝化效果较好，因而硅基底向光面的绒面可以选用金字塔尺寸较小的绒面，而尺寸较小的绒面有更好的陷光效果，进一步提高硅基底对光的吸收。另外，上述层叠设置的氧化硅层和氮化硅层具有的有益效果可以参考前文所述的层叠设置的氧化铝层和氮化硅层的有益效果分析，此处不再赘述。另外，氧化铝层、氮化硅层和氧化硅层均可以采用原子层沉积设备沉积形成。而本征非晶硅层需要采用化学气相沉积设备沉积形成。基于此，因原子层沉积设备的成本低于化学气相沉积设备的成本，故当在向光面上形成氧化铝层(或氧化硅层)和氮化硅层作为钝化减反层时，可以通过原子层沉积设备沉积在向光面上形成氧化铝(或氧化硅)和氮化硅层，从而能够降低背接触电池的制造成本。
需要说明的是，除了氧化硅层、氮化硅层和氧化铝层外，形成在向光面上具有钝化和减反射功能的膜层的材料还可以设置为其它合适材料。例如：形成在向光面上具有钝化和减反射功能的膜层还可以包括氮氧化硅层、氧化钛层和碳氧化硅层中的至少一层。
作为一种可能的实现方式，如图13所示，沿背离硅基底11的方向，绝缘层161包括依次层叠设置的氧化铝层和氮化硅层。或，沿背离硅基底11的方向，绝缘层161包括依次层叠设置的氧化硅层和氮化硅层。
采用上述技术方案的情况下，氧化铝层、氮化硅层和氧化硅层均具有良好的介电特性，利于绝缘层将第二钝化层与第一掺杂半导体层间隔开，进而可以提高背接触电池的并联电阻，降低了背接触电池的漏电风险。并且，氧 化铝、氮化硅和氧化硅还可以用于制造位于向光面上具有钝化作用和/或减反射作用的膜层。基于此，当绝缘层包括层叠设置的氧化铝层和氮化硅层，或层叠设置的氧化硅层和氮化硅层时，绝缘层的材料与钝化减反层的材料相同，从而可以在形成绝缘层的同时，在向光面上形成钝化减反层，利于简化背接触电池的制造过程，提高背接触电池制造效率。
可以理解的是，除了氧化硅层、氮化硅层和氧化铝层外，为使得绝缘层的材料与钝化减反层的材料相同，绝缘层还可以设置为前文所述的具有钝化和减反射功能的膜层的其它材料。
作为一种可能的实现方式，如图13所示，上述硅基底11具有的向光面为绒面。并且，该绒面的塔基宽度为1μm至3μm。
采用上述技术方案的情况下，在一定的范围内，绒面的塔基宽度越小，绒面的陷光作用越好。基于此，当硅基底的向光面为绒面、且绒面的塔基宽度为1μm至3μm时，向光面的塔基宽度相对较小，该向光面具有较高的陷光效果，可以进一步提高背接触电池的光电转换效率。
需要说明的是，现有的异质结背接触电池中，其向光面上形成的钝化层通常为非晶硅层。并且，如前文所述，为保证位于向光面上的非晶硅层对向光面的钝化效果，通常需要将其形成在塔基宽度相对较大的绒面结构。而在一定的范围内，绒面的塔基宽度越大，绒面的陷光作用越差。相应的，向光面的反射率越高。由此可见，现有的异质结背接触电池中位于向光面上的非晶硅钝化层与塔基宽度较小的绒面的兼容性较差，难以在提高向光面钝化效果的同时，降低向光面对光线的反射率。在此情况下，在实际的应用过程中，当本公开实施例提供的背接触电池的背光面形成有层叠设置的本征非晶硅层和掺杂非晶硅层时，可以通过在向光面上形成氧化铝、氧化硅等非晶硅材料、且与塔基宽度较小的绒面相匹配的钝化反射层，从而既能够提高背光面的钝化效果，也能够使得更多的光线通过向光面透射至硅基底内，进一步提高本公开实施例提供的背接触电池的光电转换效率。
在一些情况下，如图16所示，本公开实施例提供的背接触电池还可以包括第一透明导电层211、第二透明导电层212、第一电极22和第二电极23。其中，第一透明导电层211至少形成在第一掺杂半导体层141上，且第一电 极22位于第一透明导电层211对应第一掺杂半导体层141的部分上，以便于将第一掺杂半导体层141收集的载流子导出。上述第二透明导电层212形成在第二掺杂半导体层18上，且第二透明导电层212和第一透明导电层211相互绝缘。第二电极23位于第二透明导电层212上，以便于将第二掺杂半导体层18收集的载流子导出。
其中，第一透明导电层或第二透明导电层的材料可以为掺氟氧化锡、掺铝氧化锌、掺锡氧化铟、掺钨氧化铟、掺钼氧化铟、掺铈氧化铟和氢氧化铟等。第一透明导电层和第二透明导电层的厚度可以根据实际需求进行设置，此处不做具体限定。上述第一电极和第二电极的材质可以为银、铝、铜、镍等导电材料。
第二方面，本公开实施例还提供了一种光伏组件，该光伏组件包括上述第一方面及其各种实现方式提供的背接触电池。
本公开中第二方面及其各种实现方式的有益效果，可以参考第一方面及其各种实现方式中的有益效果分析，此处不再赘述。
第三方面，本公开实施例还提供了一种背接触电池的制造方法。下文将根据图3至图16示出的背接触电池的制造过程中的断面图，对制造过程进行描述。具体的，该背接触电池的制造方法包括以下步骤：
首先，如图1所示，提供一硅基底11。该硅基底11的具体结构可以参考前文，此处不再赘述。
在实际的应用过程中，可以在槽式清洗设备内，并采用KOH等碱性清洗溶液对掺杂后的硅衬底进行抛光处理，获得硅基底。在此情况下，与未经过处理的裸硅衬底相比，经抛光处理后的硅基底的背光面和向光面均为平坦的抛光面，便于后续基于平坦的抛光面形成满足工艺要求的结构，提高背接触电池的良率。
如图7所示，沿硅基底11的厚度方向，形成依次层叠设置于硅基底11具有的背光面上的第一钝化层121和第一掺杂半导体层141。具体的，第一钝化层121和第一掺杂半导体层141的材料和厚度等信息可以参考前文，此处不再赘述。
示例性的，上述形成层叠设置的第一钝化层和第一掺杂半导体层可以包 括步骤：如图4所示，依次形成覆盖在背光面上的钝化材料层12、以及位于钝化材料层12上的本征半导体材料层13。如图5所示，对本征半导体材料层进行扩散处理，以使得本征半导体材料层形成掺杂半导体材料层14、以及在掺杂半导体材料层14上形成掺杂玻璃层15。接着，采用激光刻蚀工艺，去除位于掺杂半导体材料层上的部分掺杂玻璃层。其中，掺杂玻璃层的剩余部分形成掩膜层。最后，如图6和图7所示，在掩膜层151的掩膜作用下，依次去除掺杂半导体材料层暴露在掩膜层之外的部分、以及钝化材料层暴露在掩膜层之外的部分，形成层叠设置的第一钝化层121和第一掺杂半导体层141。
在实际的应用过程中，可以根据第一钝化层和第一掺杂半导体层的材料确定二者的形成工艺。例如：在第一钝化层为隧穿钝化层，第一掺杂半导体层为掺杂多晶硅的情况下，如图4所示，可以采用低压化学气相沉积(Low Pressure Chemical Vapor Deposition，可缩写为LPCVD)等工艺，依次形成覆盖在背光面上的钝化材料层12、以及位于钝化材料层12上的本征半导体材料层13。其中，在形成钝化材料层12和本征半导体材料层13的过程中，也会在硅基底11的侧面和向光面形成绕镀钝化材料层和绕镀本征半导体材料层。接着，通过扩散设备对本征半导体材料层13进行扩散处理。具体的，如图5所示，在对位于钝化材料层12上的本征半导体材料层进行扩散处理时，本征半导体材料层转变为掺杂半导体材料层14，且在掺杂半导体材料层14的表面形成掺杂玻璃层15。其中，扩散处理的处理条件可以根据第一掺杂半导体层141内掺杂元素的掺杂浓度、所要形成的掺杂玻璃层15的厚度和致密程度、以及实际应用场景确定，此处不做具体限定。当然，经扩散处理后，也会使得上述绕镀本征半导体材料层形成绕镀掺杂半导体材料层，并在绕镀掺杂半导体材料层上形成绕镀掺杂玻璃层。然后，采用激光刻蚀工艺，对掺杂玻璃层15进行图案化处理后，该掺杂玻璃层的剩余部分可以形成掩膜层。该掩膜层覆盖在掺杂半导体材料层对应形成第一掺杂半导体层的部分上。如图6所示，在掩膜层151的掩膜作用下，可以采用激光刻蚀、湿法刻蚀或干法刻蚀等工艺，对掺杂半导体材料层和钝化材料层进行图案化处理，形成层叠设置的第一钝化层121和第一掺杂半导体层141。
值得注意的是，在对掺杂半导体材料层和钝化材料层进行图案化处理的 过程中所使用的掩膜层是对掺杂玻璃层进行图案化处理所获得的。换句话说，无须额外形成氮化硅等其它掩膜层就能够实现对掺杂半导体材料层和钝化材料层的图案化处理，简化背接触电池的制造过程的同时，还可以降低背接触电池的制造成本。
具体的，上述掺杂玻璃层的具体材料可以根据第一掺杂半导体层的材料和掺杂类型进行确定。例如：在第一掺杂半导体层为掺杂有磷的N型掺杂多晶硅层时，掺杂玻璃层为磷硅玻璃层。又例如：在第一掺杂半导体层为掺杂有硼的P型掺杂多晶硅层时，掺杂玻璃层为硼硅玻璃层。
另外，掺杂玻璃层的厚度可以根据实际需求进行设置，只要能够使得通过掺杂玻璃层形成的掩膜层具有相应的掩膜作用均可。
示例性的，掺杂玻璃层的厚度可以为40nm至60nm。例如：掺杂玻璃层的厚度可以为40nm、45nm、50nm、55nm或60nm。在此情况下，掺杂玻璃层的厚度较为适中，可以防止因掺杂玻璃层的厚度较小使得以该掺杂玻璃层的剩余部分形成的掩膜层的保护作用较差而导致难以在相应操作中保护位于其下方的第一掺杂半导体层和第一钝化层，确保第一掺杂半导体层和第一钝化层具有良好的成膜质量，提高背接触电池的良率。同时，还可以防止因掺杂玻璃层的厚度较大而导致制造效率降低、以及制造成本增大等问题，利于提升背接触电池的量产性。
另外，上述扩散处理的扩散时间可以为60min至120min，扩散温度可以为800℃至900℃。例如：扩散时间可以为60min、70min、80min、90min、100min、110min或120min。扩散温度可以为810℃、820℃、830℃、840℃、850℃、860℃、870℃、880℃、890℃或900℃。
可以理解的是，扩散温度的高低、以及扩散时间的长短会影响扩散过程中形成的掺杂玻璃层的厚度、以及掺杂玻璃层的致密性。具体的，在一定的范围内，扩散时间越长、且扩散温度越高，形成的掺杂玻璃层的厚度越大、且致密性越高，相应的通过该掺杂玻璃层所形成的掩膜层的掩膜作用越强。相反的，在一定的范围内，扩散时间越短、且扩散温度越低，形成的掺杂玻璃层的厚度越小、且致密性越低，相应的通过该掺杂玻璃层所形成的掩膜层的掩膜作用越弱。在此情况下，当扩散时间为60min至120min，且扩散温度 为800℃至900℃时，可以防止因扩散时间较短、且扩散温度较低而导致难以在相应操作中保护位于其下方的第一掺杂半导体层和第一钝化层，确保第一掺杂半导体层和第一钝化层具有良好的成膜质量，提高背接触电池的良率。同时，还可以防止因扩散时间较长、且扩散温度较高而导致制造效率降低、以及制造成本增大等问题，利于提升背接触电池的量产性。
需要说明的是，除了采用对本征半导体材料层进行扩散处理，以使其形成掺杂半导体材料层之外，还可以采用离子注入或掺杂源涂布推进等工艺实现掺杂半导体材料层的形成。可以根据实际应用场景需求选择合适的掺杂半导体材料层的形成工艺。
另外，如前文所述，在第一钝化层为隧穿钝化层，并且第一掺杂半导体层为掺杂多晶硅层的情况下，除了采用低压化学气相沉积工艺和扩散工艺形成掺杂多晶硅层之外，还可以采用等离子体增强化学气相沉积工艺形成掺杂多晶硅层。并且，在形成掺杂多晶硅层还可以通过原位退火的方式对掺杂多晶硅层进行晶化处理，以减小掺杂多晶硅层内的应力，提高掺杂多晶硅层的成膜质量。
再者，如前文所述，第一钝化层可以为隧穿钝化层，并且第一掺杂半导体层可以为掺杂多晶硅层。基于此，如图5所示，在依次形成覆盖在背光面上的钝化材料层12、以及位于钝化材料层12上的掺杂半导体材料层14后，如图6所示，可以采用激光刻蚀工艺，对掺杂半导体材料层和钝化材料层进行图案化处理，形成层叠设置的第一钝化层121和第一掺杂半导体层141。该情况下具有的有益效果可以参考前文所述的第一钝化层121为隧穿钝化层，且第一掺杂半导体层141为掺杂多晶硅层的有益效果分析，此处不再赘述。
示例性的，如前文所述，硅基底的向光面可以为抛光面，也可以为绒面。其中，在硅基底的向光面为绒面、且在采用第一掺杂半导体层上形成有上述掩膜层的情况下，在形成层叠设置的第一钝化层和第一掺杂半导体层后，并在进行后续操作前，上述背接触电池的制造方法还包括步骤：如图7所示，去除位于硅基底11的向光面和侧面上的绕镀掺杂玻璃层、绕镀掺杂半导体材料层和绕镀钝化材料层。示例性的，可以采用链式清洗设备，并以滚轮带液或水上漂的方式，去除上述绕镀掺杂玻璃层、绕镀掺杂半导体材料层和绕镀 钝化材料层。接下来，如图8所示，在掩膜层151的掩膜作用下，对硅基底11具有的向光面进行制绒处理，以使得向光面为绒面。其中，背光面暴露在掩膜层151之外的部分也会形成绒面。另外，制绒处理所采用的溶液、以及处理条件可以根据实际应用场景进行确定，此处不做具体限定。接着，如图9所示，可以采用HF溶液，去除掩膜层151。该HF溶液的浓度、以及去除时间可以根据实际需求设置。
采用上述技术方案的情况下，如前文所述，在制绒处理过程中，所使用的掩膜层是采用激光刻蚀工艺，对扩散处理过程中形成在掺杂半导体材料层上的掺杂玻璃层进行图案化处理所获得，并非在获得层叠设置的第一钝化层和第一掺杂半导体层后而额外通过沉积等工艺形成的氮化硅等掩膜层，从而可以进一步简化背接触电池的制造过程，降低背接触电池的制造成本。
需要说明的是，如前文所述，本公开实施例提供的制造方法所制造的背接触电池包括：硅基底、第一钝化层、第一掺杂半导体层、第二钝化层、第二掺杂半导体层和绝缘层。其中，如图13所示，层叠设置的第二钝化层17和第二掺杂半导体层18覆盖层叠设置的第一钝化层121和第一掺杂半导体层141的部分区域。并且，绝缘层161至少位于第二钝化层17和第一掺杂半导体层141之间，用于将第二钝化层17和第一掺杂半导体层141间隔开。在上述情况下，如图11所示，在形成层叠设置的第一钝化层121和第一掺杂半导体层141后，并在形成层叠设置的第二钝化层和第二掺杂半导体层前，上述背接触电池的制造方法还包括步骤：在背光面上形成绝缘层。
示例性的，如图10所示，可以采用等离子体增强原子层沉积等工艺，形成覆盖在背光面和第一掺杂半导体层141上的绝缘材料层16。接着，如图11所示，可以采用激光刻蚀等工艺，对绝缘材料层16进行图案化处理，以暴露出背光面与后续形成的第二钝化层17相接触的区域。其中，绝缘材料层16覆盖在层叠设置的第一钝化层121和第一掺杂半导体层141相应区域的部分形成绝缘层。该相应区域为层叠设置的第一钝化层121和第一掺杂半导体层141与层叠设置的第二钝化层和第二掺杂半导体层相邻的区域。
需要说明的是，在采用激光刻蚀工艺对绝缘材料层进行图案化处理的情况下，在暴露出背光面与后续形成的第二钝化层相接触的区域后，可以在绝 缘材料层的剩余部分的掩膜作用下，并采用湿法刻蚀工艺对该区域因高温激光刻蚀而导致损伤的表面进行清洗修复，降低载流子在该界面处的缺陷复合速率的同时，还可以提高形成在区域上的第二钝化层的致密性，进一步提高第二钝化层对该区域的钝化效果，提升背接触电池的光电转换效率。
如图13所示，沿硅基底11的厚度方向，形成依次层叠设置于背光面上的第二钝化层17和第二掺杂半导体层18。其中，层叠设置的第二钝化层17和第二掺杂半导体层18覆盖层叠设置的第一钝化层121和第一掺杂半导体层141的部分区域，第二掺杂半导体层18和第一掺杂半导体层141的导电类型相反。具体的，第二钝化层17和第二掺杂半导体层18的材料和厚度等信息可以参考前文，此处不再赘述。
在实际的应用过程中，如图12所示，可以采用化学气相沉积等工艺，依次形成覆盖在背光面和绝缘材料层16的剩余部分上的钝化材料和掺杂半导体材料。接着，如图13所示，可以采用激光刻蚀等工艺，对钝化材料和掺杂半导体材料进行图案化处理，使得剩余的钝化材料形成第二钝化层17，以及剩余的掺杂半导体材料形成第二掺杂半导体层18。最后，可以在第二掺杂半导体层18的掩膜作用下，采用湿法刻蚀等工艺，对绝缘材料层16的剩余部分进行图案化处理，以暴露出部分第一掺杂半导体层141。其中，剩余的绝缘材料层形成绝缘层161。
在一些情况下，如前文所述，当所制造的背接触电池还包括第一透明导电层、第二透明导电层、第一电极和第二电极时，如图14所示，可以采用物理气相沉积等工艺，形成覆盖在第一掺杂半导体层141和第二掺杂半导体层18上的透明导电材料层21。接着，如图15所示，可以采用激光刻蚀等工艺，形成贯穿透明导电层、第二掺杂半导体层18和第二钝化层17的绝缘槽，以将透明导电材料层位于第一掺杂半导体层141上的部分与透明导电材料层位于第二掺杂半导体层18上的部分间隔开。其中，透明导电材料层至少位于第一掺杂半导体层141上的部分形成第一透明导电层211，透明导电材料层位于第二掺杂半导体层18上的部分形成第二透明导电层212。最后，如图16所示，可以采用丝网印刷等工艺形成位于第一透明导电层211上的第一电极22，以及位于第二透明导电层212上的第二电极23。
本公开还提供了以下具体实施例来进一步说明本公开所述背接触电池的制造方法，具体操作步骤如下：
实施例1：
第一步：将N型硅片或者P型硅片投入槽式抛光清洗机中进行抛光工艺。其中，抛光溶液是浓度为5.5％至6.5％的KOH溶液。抛光溶液的温度81℃至87℃。工艺时间为290s至310s。经抛光工艺后，硅基底表面形貌为尺寸19μm至23μm的方块结构，并且经抛光工艺后硅基底的背光面的反射率40％至44％。
第二步：在低压化学气相沉积(Low Pressure Chemical Vapor Deposition，可缩写为LPCVD)炉中形成覆盖硅基底具有的背光面上的隧穿氧化材料层、以及位于隧穿氧化材料层上的本征多晶硅材料层。其中，隧穿氧化材料层的厚度为1.2nm至1.8nm，本征多晶硅材料层的厚度为70nm至170nm。另外，硅基底的侧面和向光面依次形成有绕镀钝化材料层和绕镀多晶硅材料层。
第三步：在磷扩散炉中，对本征多晶硅材料(Poly)层进行磷掺杂，使得本征多晶硅材料层形成N型掺杂多晶硅材料层。该N型掺杂多晶硅材料层的扩散方阻为70Ω/sq至110Ω/sq。其中，经扩散处理后，N型掺杂多晶硅材料层、以及绕镀多晶硅材料层上均形成有磷硅玻璃层。
第四步：使用激光刻蚀工艺，对磷硅玻璃层对应背光面的部分、隧穿氧化材料层和N型掺杂多晶硅材料层进行图案化处理，暴露出背光面与P+区对应的区域。其中，隧穿氧化材料层的剩余部分形成第一钝化层，N型掺杂多晶硅材料层的剩余部分形成第一掺杂半导体层。磷硅玻璃层位于第一掺杂半导体层上的部分形成掩膜层。
第五步：在链式清洗机中，将硅基底的向光面朝下进入HF槽中，以滚轮带液方式或者水上漂方式的清洗模式，通过浓度为9.5％至10.5％的HF溶液，并在常温下，去除磷硅玻璃层位于硅基底的侧面和向光面上的部分、以及去除绕镀钝化材料层和绕镀多晶硅材料层。其中，去除时间为55s至65s。然后，将形成有第一钝化层、第一掺杂半导体层和掩膜层的硅基底进入槽式清洗机中进行碱制绒工艺。其中，制绒溶液包括浓度为2.5％至3.5％的KOH溶液、以及制绒添加剂溶液。制绒溶液的温度为80℃至84℃，工艺时间为570s至 630s。刻蚀量为0.5g至0.7g，经制绒处理后硅基底具有的向光面的反射率为9％至11％。向光面的塔基宽度为1μm至3μm的小绒面微观结构。此时，背光面的P+区和向光面同时完成制绒处理。最后，进入HF槽中去除掩膜层，该HF溶液的浓度为9.5％至10.5％，并在常温下处理95s至105s。
第六步：在等离子体增强原子层沉积(Plasma Enhanced Atomic Layer Deposition，可缩写为PEALD)设备中，在背光面和向光面上依次沉积氧化铝层和氮化硅层。氧化铝层的厚度为5nm至15nm，氮化硅层的厚度为70nm至110nm。
第七步：使用激光器，对位于背光面上氧化铝层和氮化硅层进行图案化处理，以去除氧化铝层和氮化硅层位于P+区上的部分。其中，图案化处理对应丝网图形进行设计，激光器类型可以选用绿光纳秒、紫外皮秒、绿光皮秒、紫外纳秒。
第八步：在槽式抛光清洗机中进行抛光工艺。抛光溶液是浓度为5.5％至6.5％的KOH溶液，抛光溶液的温度为81℃至87℃，工艺时间为170s至190s，以去除第七步产生的激光损伤。同时，进行激光开槽区域抛光处理。最后，在浓度为1％wt的HF溶液中处理25s至35s。
第九步：在化学气相沉积设备中，依次形成覆盖在背光面上的本征非晶硅材料层和掺杂硼的P型掺杂非晶硅材料层。其中，本征非晶硅材料层的厚度为5nm至20nm，P型掺杂非晶硅材料层的厚度为10nm至30nm。
第十步：使用激光器，对本征非晶硅材料层和P型掺杂非晶硅材料层进行图案化处理，以使得本征非晶硅材料层的剩余部分形成第二钝化层，并使得P型掺杂非晶硅材料层的剩余部分形成第二掺杂半导体层。其中，激光器类型可以选用绿光纳秒、紫外皮秒、绿光皮秒、紫外纳秒。
第十一步：在链式清洗机中，将硅基底的背光面朝下进入HF槽中。其中，HF溶液的浓度为29％至31％，并在常温下处理175s至185s，清洗模式为滚轮带液方式或者水上漂方式。将激光刻蚀处理后，位于背光面上的氧化铝层和氮化硅层暴露出的部分进行去除，以暴露出第一掺杂半导体层的部分区域。最后，依次进入水槽和烘干槽分别进行清洗烘干。其中，背光面上的氧化铝层和氮化硅层的剩余部分形成绝缘层。
第十二步：在物理气相沉积设备中，形成覆盖在背光面上的透明导电材料层。该透明导电材料层的厚度为60nm至100nm。
第十三步：使用激光刻蚀工艺，去除局部透明导电材料层、第二掺杂半导体层和第二钝化层，以实现N+区和P+区绝缘。
第十四步：采用丝网印刷等工艺形成第一电极和第二电极。最终形成的结构参见图16。
进一步地，本公开还提供了如下对比例制造背接触电池，具体操作步骤如下：
对比例1：
第一步：将N型硅片或者P型硅片投入槽式抛光清洗机中进行抛光工艺。其中，抛光溶液是浓度为5.5％至6.5％的KOH溶液。抛光溶液的温度81℃至87℃。工艺时间为290s至310s。经抛光工艺后，硅基底表面形貌为尺寸19μm至23μm的方块结构，并且经抛光工艺后硅基底的背光面的反射率40％至44％。
第二步：使用等离子体增强化学气相沉积设备，形成覆盖在硅基底的背光面上的第一氮化硅层。该第一氮化硅层的厚度为190nm至210nm，折射率为2.3％至2.5％。其中，硅基底的侧面和向光面会形成有绕镀氮化硅层。
第三步：在槽式清洗机中，将形成有第一氮化硅层、以及绕镀氮化硅层的硅基底进入HF槽中。其中，HF溶液的浓度为0.5％至1.5％。并在常温下处理25s至35s，以去除绕镀氮化硅层。接着，将背光面形成有第一氮化硅层的硅基底进入碱槽进行制绒处理。制绒溶液包括浓度为2％至3％的KOH溶液、以及制绒添加剂溶液。制绒溶液的温度为80℃至84℃。工艺时间为760s至800s。然后，进入承装有HNO3与HF混合溶液的槽内进行绒面圆滑处理。混合溶液的配比为HNO3:HF＝1:100。经绒面圆滑处理后总体刻蚀量为1.7g至1.9g。硅基底向光面的反射率为11％至13％。向光面上的塔基宽度为3μm至5μm的大绒面微观结构。最后，在浓度为8％wt的HF槽中，并在常温下处理290s至310s，以去除背光面残留的第一氮化硅层。
第四步：在化学气相沉积设备中，依次形成覆盖在背光面上的第一本征非晶硅材料层、掺杂磷的N型掺杂非晶硅材料层、第二氮化硅层和第二本征 非晶硅材料层。其中，第一本征非晶硅材料层的厚度为5nm至20nm，N型掺杂非晶硅材料层的厚度为10nm至30nm，第二氮化硅层的厚度为170nm至230nm，第二本征非晶硅材料层的厚度为10nm至30nm。
第五步：使用激光器，对第二本征非晶硅材料层进行图案化处理，以暴露出P+区。其中，激光器类型可以选用绿光纳秒、紫外皮秒、绿光皮秒、紫外纳秒；
第六步：在槽式清洗设备中，将形成有第一本征非晶硅材料层、N型掺杂非晶硅材料层、第二氮化硅层和第二本征非晶硅材料层的硅基底进入HF槽中，HF溶液的浓度为7.5％至8.5％，并在常温下处理190s至210s，以去除第二氮化硅层暴露的部分。接着，进入碱槽进行刻蚀处理，以去除第一本征非晶硅材料层和N型掺杂非晶硅材料层暴露在外的部分，使得第一本征非晶硅材料层的剩余部分形成第一钝化层、以及使得N型掺杂非晶硅材料层形成第一掺杂半导体层。其中，刻蚀溶液包括：浓度为0.4％至0.6％的KOH、以及浓度为0.1％至0.2％的H2O2溶液，刻蚀溶液的温度25℃，工艺时间为390s至410s。
第七步：在化学气相沉积设备中，依次形成覆盖在背光面上的第三本征硅材料层和掺杂硼的P型掺杂非晶硅材料层。并在向光面依次形成第四本征非晶硅材料层和第三氮化硅层。其中，第三本征非晶硅材料层的厚度为5nm至30nm，P型掺杂非晶硅材料层的厚度为10nm至25nm，第四本征非晶硅材料层的厚度为5nm至20nm，第三氮化硅层的厚度为80nm至105nm。
第八步：使用激光器，对背光面上的第三本征硅材料层和P型掺杂非晶硅材料层进行图案化处理，以使得第三本征硅材料层的剩余部分形成第二钝化层，以及使得P型掺杂非晶硅材料层的剩余部分形成第二掺杂半导体层。其中，激光器类型可以选用绿光纳秒、紫外皮秒、绿光皮秒、紫外纳秒。
第九步：使用HF溶液去除将第二氮化硅层暴露的部分去除，以暴露出第一掺杂半导体层的部分区域、以及使得第二氮化硅层位于第一掺杂半导体层上的部分形成绝缘层。其中，HF溶液的浓度为7％至9％，并在常温下处理380s至420s。
第十步：在化学气相沉积设备中，形成覆盖在背光面上的透明导电材料 层。该透明导电材料层的厚度为60nm至100nm。
第十一步：使用激光器，对第一掺杂半导体层和第二掺杂半导体层的横向交界处进行刻蚀，去除局部透明导电材料层、局部第二钝化层和局部第二掺杂半导体层，以使得透明导电材料层位于第一掺杂半导体层上的部分形成第一透明导电层、以及使得透明导电材料层位于第二掺杂半导体层上的部分形成第二透明导电层。
第十二步：采用丝网印刷等工艺形成第一电极和第二电极。最终形成的结构参见图1。
对比例2：
第一步：将N型硅片或者P型硅片投入槽式抛光清洗机中进行抛光工艺。其中，抛光溶液是浓度为5.5％至6.5％的KOH溶液。抛光溶液的温度81℃至87℃。工艺时间为290s至310s。经抛光工艺后，硅基底表面形貌为尺寸19μm至23μm的方块结构，并且经抛光工艺后硅基底的背光面的反射率40％至44％。
第二步：在低压化学气相沉积炉中，形成覆盖硅基底具有的背光面上的隧穿氧化材料层、以及位于隧穿氧化材料层上的本征多晶硅材料层。其中，隧穿氧化材料层的厚度为1.2nm至1.8nm，本征多晶硅材料层的厚度为70nm至170nm。另外，硅基底的侧面和向光面依次形成有绕镀钝化材料层和绕镀多晶硅材料层。
第三步：在磷扩散炉中，对本征多晶硅材料层进行磷掺杂，使得本征多晶硅材料层形成N型掺杂多晶硅材料层。该N型掺杂多晶硅材料层的扩散方阻为70Ω/sq至110Ω/sq。其中，经扩散处理后，N型掺杂多晶硅材料层、以及绕镀多晶硅材料层上均形成有磷硅玻璃层。
第四步：使用等离子体化学气相沉积设置，形成覆盖在背光面的氮化硅层。该氮化硅层的厚度为40nm至60nm，其折射率为2.3％至2.5％。
第五步：使用激光器，对位于背光面上的氮化硅层进行图案化处理，以暴露出背光面与P+区相对应的区域。其中，激光器类型可以选用绿光纳秒、紫外皮秒、绿光皮秒、紫外纳秒。
第六步：在槽式清洗机中，将已形成的结构进入HF槽中，以去除磷硅玻 璃层暴露在背光面的氮化硅之外的部分。HF溶液的浓度为0.5％至1.5％，并在常温下处理25s至35s。接着，进入碱槽进行制绒处理，以对向光面和背光面暴露出来的区域进行制绒。制绒溶液包括浓度为2.5％至3.5％的KOH、以及制绒添加剂溶液。制绒溶液的温度80℃至84℃，工艺时间为570s至630s。制绒刻蚀量为0.5g至0.7g。制绒处理后向光面的反射率为9％至11％，且向光面的塔基宽度为1μm至3μm的小绒面微观结构。
第七步：在等离子体增强原子层沉积设备中，依次形成覆盖在向光面上的氧化铝层和氮化硅层。其中，氧化铝层的厚度为5nm至15nm，氮化硅层的厚度为70nm至110nm。然后在浓度为1％wt的HF溶液中处理30s，以对背光面暴露的区域进行抛光处理。
第八步：在化学气相沉积设备中，依次形成覆盖在背光面上的本征非晶硅材料层和掺杂硼的P型掺杂非晶硅材料层。其中，本征非晶硅材料层的厚度为5nm至30nm，P型掺杂非晶硅层的厚度为10nm至25nm。
第九步：使用激光器，对本征非晶硅材料层和P型掺杂非晶硅材料层进行图案化处理，以使得本征非晶硅材料层的剩余部分形成第二钝化层，以及使得P型掺杂非晶硅材料层的剩余部分形成第二掺杂半导体层。其中，激光器类型可以选用绿光纳秒、紫外皮秒、绿光皮秒、紫外纳秒。
第十步：使用HF溶液进行去除氮化硅层暴露在外的部分，以露出第一掺杂半导体层的部分区域。其中，HF溶液的浓度为7％至9％，并在常温下处理380s至420s。
第十一步：在物理气相沉积设备中，形成覆盖在背光面上的透明导电材料层。该透明导电材料层的厚度为60nm至100nm。
第十二步：使用激光刻蚀工艺，去除局部透明导电材料层、第二掺杂半导体层和第二钝化层，以实现N+区和P+区绝缘。
第十三步：采用丝网印刷等工艺形成第一电极和第二电极。最终形成的结构参见图2。
其中，表1对通过上述实施例1、对比例1和对比例2所制造的背接触电池进行测试，并对上述三种背接触电池的参数进行比较。
表1：实施例1、对比例1和对比例2所制造的背接触电池各项参数比较
如图16所示，实施例1制造的背接触电池中，绝缘层161至少位于第二钝化层17和第一掺杂半导体层141之间。并且，沿着背离硅基底11的方向，绝缘层161包括氧化铝层和氮化硅层。而如图1所示，对比例1制造的背接触电池中，只在第一掺杂半导体层141与第二钝化层17的纵向交界处形成有氮化硅材料的绝缘层161。如图2所示，对比例2制造的背接触电池中，只在第一掺杂半导体层141与第二钝化层17的纵向交界处形成有掺杂玻璃层、以及位于掺杂玻璃层上的绝缘层161。基于此，由表1可以看出，实施例1制造的背接触电池的并联电阻和短路电流分别高于对比例1和对比例2制造的背接触电池对应的并联电阻和短路电流，并且，实施例1制造的背接触电池的开路电压小于对比例1和对比例2制造的背接触电池对应的开路电压，从而利于降低背接触电池的漏电风险，进而使得实施例1制造的背接触电池的转化效率高于对比例1和对比例2制造的背接触电池对应的转化效率。
另外，如图16所示，实施例1制造的背接触电池中，沿着背离硅基底的方向，向光面上依次形成有氧化铝层、以及位于氧化铝层上的氮化硅层。而如图1所示，对比例1制造的背接触电池中，沿着背离硅基底的方向，向光面上依次形成有非晶硅钝化层、以及位于非晶硅钝化层上的氮化硅层。基于此，因位于非晶硅具有吸光特性，故位于向光面上的非晶硅钝化层会产生寄生吸收，导致入射至硅基底内的光线减少。并且，如前文所述非晶硅钝化层难以与具有小绒面结构的向光面相匹配，而氧化铝层可以与小绒面结构的向光面相匹配。在此情况下，由表1可以看出，实施例1制造的背接触电池的向光面塔基宽度和向光面反射率分别小于对比例1制造的背接触电池对应的向光面塔基宽度和向光面反射率，从而利于增强向光面的陷光效果，使得更 多的光线入射至硅基底内，最终使得实施例1制造的背接触电池的转化效率大于对比例1制造的背接触电池对应的转化效率。
再者，如图16所示，实施例1制造的背接触电池中，第一钝化层121和第一掺杂半导体层141组成隧穿钝化接触结构。第二钝化层17和第二掺杂半导体层18组成异质接触结构。而如图1所示，对比例1制造的背接触电池中，第一钝化层121和第一掺杂半导体层141组成异质接触结构。同时第二钝化层17和第二掺杂半导体层18也组成异质接触结构。基于此，如前文所述，在高温下，与异质接触结构相比，隧穿钝化接触结构的化学性质更为稳定，因此在激光开膜工艺后，对隧穿钝化接触结构的钝化效果较小。并且，由表1可以看出，实施例1制造的背接触电池的N+区激光工艺窗口大于对比例1制造的背接触电池对应的N+区激光工艺窗口。
综上所述，由表1可以看出，实施例1制造的背接触电池的填充因子高于通过对比例1和对比例2制造的背接触电池对应的填充因子，即实施例1制造的背接触电池的品质优于对比例1和对比例2制造的背接触电池。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (13)

  1. 一种背接触电池，其特征在于，包括：硅基底，
    沿所述硅基底的厚度方向，依次层叠设置于所述硅基底具有的背光面上的第一钝化层和第一掺杂半导体层；
    沿所述硅基底的厚度方向，依次层叠设置于所述背光面上的第二钝化层和第二掺杂半导体层；其中，层叠设置的所述第二钝化层和所述第二掺杂半导体层覆盖层叠设置的所述第一钝化层和所述第一掺杂半导体层的部分区域，所述第二掺杂半导体层和所述第一掺杂半导体层的导电类型相反；
    设置于所述背光面上的绝缘层；所述绝缘层至少位于所述第二钝化层和所述第一掺杂半导体层之间，用于将所述第二钝化层和所述第一掺杂半导体层间隔开。
  2. 根据权利要求1所述的背接触电池，其特征在于，所述第一钝化层为隧穿钝化层，所述第一掺杂半导体层为掺杂多晶硅层。
  3. 根据权利要求2所述的背接触电池，其特征在于，所述第二钝化层为本征非晶硅层，所述第二掺杂半导体层为掺杂非晶硅层。
  4. 根据权利要求1所述的背接触电池，其特征在于，所述背接触电池还包括：沿背离所述硅基底的方向，依次层叠设置于所述硅基底具有的向光面上的氧化铝层和氮化硅层；或，
    所述背接触电池还包括：沿背离所述硅基底的方向，依次层叠设置于所述硅基底具有的向光面上的氧化硅层和氮化硅层。
  5. 根据权利要求1～4任一项所述的背接触电池，其特征在于，沿背离所述硅基底的方向，所述绝缘层包括依次层叠设置的氧化铝层和氮化硅层；或，
    沿背离所述硅基底的方向，所述绝缘层包括依次层叠设置的氧化硅层和氮化硅层。
  6. 根据权利要求1～4任一项所述的背接触电池，其特征在于，所述绝缘层的厚度为75nm至125nm。
  7. 根据权利要求1～4任一项所述的背接触电池，其特征在于，所述硅基底具有的向光面为绒面；所述绒面的塔基宽度为1μm至3μm。
  8. 一种光伏组件，其特征在于，包括如权利要求1～7任一项所述的背接 触电池。
  9. 一种背接触电池的制造方法，其特征在于，包括：
    提供一硅基底；
    沿所述硅基底的厚度方向，形成依次层叠设置于所述硅基底具有的背光面上的第一钝化层和第一掺杂半导体层；
    在所述背光面上形成绝缘层；
    沿所述硅基底的厚度方向，形成依次层叠设置于所述背光面上的第二钝化层和第二掺杂半导体层；其中，层叠设置的所述第二钝化层和所述第二掺杂半导体层覆盖层叠设置的所述第一钝化层和所述第一掺杂半导体层的部分区域，所述第二掺杂半导体层和所述第一掺杂半导体层的导电类型相反；所述绝缘层至少位于所述第二钝化层和所述第一掺杂半导体层之间，用于将所述第二钝化层和所述第一掺杂半导体层间隔开。
  10. 根据权利要求9所述的背接触电池的制造方法，其特征在于，形成层叠设置的所述第一钝化层和所述第一掺杂半导体层，包括：
    依次形成覆盖在所述背光面上的钝化材料层、以及位于所述钝化材料层上的本征半导体材料层；
    对所述本征半导体材料层进行扩散处理，以使得所述本征半导体材料层形成掺杂半导体材料层、以及在所述掺杂半导体材料层上形成掺杂玻璃层；
    采用激光刻蚀工艺，去除位于所述掺杂半导体材料层上的部分所述掺杂玻璃层；其中，所述掺杂玻璃层的剩余部分形成掩膜层；
    在所述掩膜层的掩膜作用下，依次去除所述掺杂半导体材料层暴露在所述掩膜层之外的部分、以及所述钝化材料层暴露在所述掩膜层之外的部分，形成层叠设置的所述第一钝化层和所述第一掺杂半导体层。
  11. 根据权利要求10所述的背接触电池的制造方法，其特征在于，所述掺杂玻璃层的厚度为40nm至60nm；和/或，
    所述扩散处理的扩散时间为60min至120min，扩散温度为800℃至900℃。
  12. 根据权利要求10所述的背接触电池的制造方法，其特征在于，形成层叠设置的所述第一钝化层和所述第一掺杂半导体层后，在所述背光面上形 成所述绝缘层前，所述背接触电池的制造方法还包括：
    去除位于所述硅基底的向光面和侧面上的绕镀掺杂玻璃层、绕镀掺杂半导体材料层和绕镀钝化材料层；
    在所述掩膜层的掩膜作用下，对所述硅基底具有的向光面进行制绒处理，以使得所述向光面为绒面；
    去除所述掩膜层。
  13. 根据权利要求9～12任一项所述的背接触电池的制造方法，其特征在于，形成层叠设置的所述第一钝化层和所述第一掺杂半导体层，包括：
    依次形成覆盖在所述背光面上的钝化材料层、以及位于所述钝化材料层上的掺杂半导体材料层；
    采用激光刻蚀工艺，对所述掺杂半导体材料层和所述钝化材料层进行图案化处理，形成层叠设置的所述第一钝化层和所述第一掺杂半导体层；其中，所述第一钝化层为隧穿钝化层，所述第一掺杂半导体层为掺杂多晶硅层。
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