WO2024113153A1 - 移位寄存器单元、驱动控制电路、显示装置及驱动方法 - Google Patents

移位寄存器单元、驱动控制电路、显示装置及驱动方法 Download PDF

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WO2024113153A1
WO2024113153A1 PCT/CN2022/134975 CN2022134975W WO2024113153A1 WO 2024113153 A1 WO2024113153 A1 WO 2024113153A1 CN 2022134975 W CN2022134975 W CN 2022134975W WO 2024113153 A1 WO2024113153 A1 WO 2024113153A1
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transistor
node
coupled
signal terminal
signal
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PCT/CN2022/134975
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English (en)
French (fr)
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王本莲
龙跃
郑海
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/134975 priority Critical patent/WO2024113153A1/zh
Publication of WO2024113153A1 publication Critical patent/WO2024113153A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display technology, and in particular to a shift register unit, a drive control circuit, a display device and a drive method.
  • the array substrate row drive technology integrates the drive control circuit on the array substrate of the display panel to form a scan drive for the display panel.
  • the drive control circuit is usually composed of multiple cascaded shift register units. If the output of the shift register unit is unstable, it will cause display abnormality.
  • a shift register unit comprising:
  • an input circuit configured to provide a signal at an input signal terminal to a first node in response to a signal at a first clock signal terminal
  • control circuit configured to control a signal of the second node
  • a first output circuit configured to provide a signal from a first reference voltage signal terminal to an output signal terminal in response to a signal from the first node
  • a second output circuit configured to provide a signal at a second reference voltage signal terminal to the output signal terminal in response to a signal at the second node
  • the noise reduction circuit is configured to respond to the signal at the noise reduction signal terminal, provide the signal at the third reference voltage signal terminal to the second node, and control the second output circuit to stop outputting the signal.
  • the noise reduction circuit includes: a first transistor
  • the gate of the first transistor is coupled to the noise reduction signal terminal, the first electrode of the first transistor is coupled to the third reference voltage signal terminal, and the second electrode of the first transistor is coupled to the second node.
  • the first node includes: a first sub-node and a second sub-node;
  • the shift register unit further includes: a conduction circuit; the first sub-node is coupled to the second sub-node through the conduction circuit; the conduction circuit is configured to conduct the first sub-node to the second sub-node in response to a signal at a fourth reference voltage signal terminal;
  • the input circuit is further configured to provide the signal at the input signal terminal to the first sub-node in response to the signal at the first clock signal terminal;
  • the first output circuit is further configured to provide the signal of the first reference voltage signal terminal to the output signal terminal in response to the signal of the second sub-node.
  • control circuit includes: a first control circuit, a second control circuit, and a third control circuit;
  • the first control circuit is configured to provide a fifth reference voltage signal terminal to a third node in response to a signal at the first clock signal terminal, and to provide a signal at the first clock signal terminal to the third node in response to a signal at the first sub-node;
  • the second control circuit is configured to control a signal of the second sub-node and a signal of the fourth node
  • the third control circuit is configured to provide a signal from the second clock signal terminal to the second node in response to a signal from the fourth node and the second clock signal terminal, and to provide a signal from the second reference voltage signal terminal to the second node in response to a signal from the first subnode.
  • the first control circuit includes: a second transistor and a third transistor;
  • the gate of the second transistor is coupled to the first clock signal terminal, the first electrode of the second transistor is coupled to the fifth reference voltage signal terminal, and the second electrode of the second transistor is coupled to the third node;
  • the gate of the third transistor is coupled to the first subnode, the first electrode of the third transistor is coupled to the third node, and the second electrode of the third transistor is coupled to the first clock signal terminal.
  • the second control circuit is further configured to provide the signal of the third node to the fourth node in response to the signal of the fourth reference voltage signal terminal, and to provide the signal of the second reference voltage signal terminal to the fifth node in response to the signal of the third node, and to provide the signal of the second clock signal terminal to the fifth node in response to the signal of the second sub-node.
  • the second control circuit includes: a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor;
  • the gate of the fourth transistor is coupled to the fourth reference voltage signal terminal, the first electrode of the fourth transistor is coupled to the third node, and the second electrode of the fourth transistor is coupled to the fourth node;
  • the gate of the fifth transistor is coupled to the third node, the first electrode of the fifth transistor is coupled to the second reference voltage signal terminal, and the second electrode of the fifth transistor is coupled to the fifth node;
  • the gate of the sixth transistor is coupled to the second sub-node, the first electrode of the sixth transistor is coupled to the fifth node, and the second electrode of the sixth transistor is coupled to the second clock signal terminal;
  • a first electrode of the first capacitor is coupled to the fifth node, and a second electrode of the first capacitor is coupled to the second sub-node.
  • the second control circuit is further configured to provide the signal of the third node to the fourth node in response to the fourth reference voltage signal terminal, and to provide the signal of the second reference voltage signal terminal to the fifth node in response to the signal of the fourth node, and to provide the signal of the second clock signal terminal to the fifth node in response to the signal of the second sub-node.
  • the second control circuit includes: a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor;
  • the gate of the fourth transistor is coupled to the fourth reference voltage signal terminal, the first electrode of the fourth transistor is coupled to the third node, and the second electrode of the fourth transistor is coupled to the fourth node;
  • the gate of the fifth transistor is coupled to the fourth node, the first electrode of the fifth transistor is coupled to the second reference voltage signal terminal, and the second electrode of the fifth transistor is coupled to the fifth node;
  • the gate of the sixth transistor is coupled to the second sub-node, the first electrode of the sixth transistor is coupled to the fifth node, and the second electrode of the sixth transistor is coupled to the second clock signal terminal;
  • a first electrode of the first capacitor is coupled to the fifth node, and a second electrode of the first capacitor is coupled to the second sub-node.
  • the third control circuit includes: a seventh transistor, an eighth transistor, a ninth transistor and a second capacitor;
  • the gate of the seventh transistor is coupled to the fourth node, the first electrode of the seventh transistor is coupled to the second clock signal terminal, and the second electrode of the seventh transistor is coupled to the first electrode of the eighth transistor;
  • the gate of the eighth transistor is coupled to the second clock signal terminal, and the second electrode of the eighth transistor is coupled to the second node;
  • the gate of the ninth transistor is coupled to the first sub-node, the first electrode of the ninth transistor is coupled to the second node, and the second electrode of the ninth transistor is coupled to the second reference signal terminal;
  • a first electrode of the second capacitor is coupled to the fourth node, and a second electrode of the second capacitor is coupled to a first electrode of the eighth transistor.
  • the input circuit includes a tenth transistor
  • a gate of the tenth transistor is coupled to the first clock signal terminal, a first electrode of the tenth transistor is coupled to the input signal terminal, and a second electrode of the tenth transistor is coupled to the first sub-node.
  • the first output circuit includes: an eleventh transistor
  • the gate of the eleventh transistor is coupled to the second sub-node, the first electrode of the eleventh transistor is coupled to the output signal terminal, and the second electrode of the eleventh transistor is coupled to the first reference voltage signal terminal.
  • the gate of the twelfth transistor is coupled to the second node, the first electrode of the twelfth transistor is coupled to the second reference voltage signal terminal, and the second electrode of the twelfth transistor is coupled to the output signal terminal;
  • a first electrode of the third capacitor is coupled to the second node, and a second electrode of the third capacitor is coupled to the second reference voltage signal terminal.
  • the conduction circuit includes: a thirteenth transistor
  • a gate of the thirteenth transistor is coupled to the fourth reference voltage signal terminal, a first electrode of the thirteenth transistor is coupled to the first sub-node, and a second electrode of the thirteenth transistor is coupled to the second sub-node.
  • the second reference voltage signal terminal and the third reference voltage signal terminal are the same signal terminal.
  • the present disclosure also provides a shift register unit, including:
  • an input circuit the input circuit being coupled to an input signal terminal and a first node and configured to provide a signal from the input signal terminal to the first node;
  • control circuit being coupled to the second node and configured to control the second node
  • a first output transistor wherein a gate of the first output transistor is coupled to the second node, a first electrode of the first output transistor is coupled to a second reference voltage signal terminal, a second electrode of the first output transistor is coupled to an output signal terminal, and is configured to provide a signal of the second reference voltage signal terminal to the output signal terminal in response to a signal of the second node;
  • a noise reduction transistor wherein the gate of the noise reduction transistor is coupled to the noise reduction signal terminal, the first electrode of the noise reduction transistor is coupled to the third reference voltage signal terminal, the second electrode of the noise reduction transistor is coupled to the second node, and is configured to provide the signal of the third reference voltage signal terminal to the second node in response to the signal of the noise reduction signal terminal.
  • a third capacitor is further included, wherein a first electrode of the third capacitor is coupled to the second reference voltage signal terminal, and a second electrode of the third capacitor is coupled to the second electrode of the noise reduction transistor.
  • a second output transistor is further included, wherein a gate of the second output transistor is coupled to the first node, a first electrode of the output transistor is coupled to the first reference voltage signal terminal, and a second electrode of the output transistor is coupled to the output signal terminal, and is configured to provide a signal from the first reference voltage signal terminal to the output signal terminal in response to a signal from the first node.
  • the second reference voltage signal terminal and the third reference voltage signal terminal are the same signal terminal.
  • the embodiment of the present disclosure also provides a driving control circuit, comprising a plurality of the above-mentioned shift register units connected in cascade;
  • the input signal terminal of the first stage shift register unit is coupled to the frame trigger signal terminal;
  • the input signal terminal of the next stage shift register unit is coupled to the output signal terminal of the previous stage shift register unit.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned drive control circuit.
  • the embodiment of the present disclosure further provides a driving method of the above-mentioned shift register unit, comprising:
  • the first output circuit responds to the signal of the first node by providing the signal of the first reference voltage signal terminal to the output signal terminal, and the noise reduction circuit responds to the signal of the noise reduction signal terminal by providing the signal of the third reference voltage signal terminal to the second node, thereby controlling the second output circuit to stop outputting the signal.
  • FIG1 is a schematic diagram of some structures of a shift register unit provided in an embodiment of the present disclosure.
  • FIG2 is a flow chart of a driving method of a shift register unit provided in an embodiment of the present disclosure
  • FIG3 is a timing diagram of some signals provided by an embodiment of the present disclosure.
  • FIG4 is another schematic diagram of the structure of the shift register unit provided by the embodiment of the present disclosure.
  • FIG5 is a schematic diagram of some further structures of a shift register unit provided in an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of some further structures of a shift register unit provided in an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of some further structures of a shift register unit provided in an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of some further structures of a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of some structures of the drive control circuit provided in the embodiment of the present disclosure.
  • the present disclosure provides a shift register unit, as shown in FIG1 , comprising:
  • the input circuit 10 is configured to provide a signal from the input signal terminal IP to the first node N1 in response to a signal from the first clock signal terminal CK;
  • a control circuit 20 configured to control a signal of a second node N2;
  • the first output circuit 30 is configured to provide a signal from the first reference voltage signal terminal V1 to the output signal terminal OT in response to a signal from the first node N1;
  • the second output circuit 40 is configured to provide the signal of the second reference voltage signal terminal V2 to the output signal terminal OT in response to the signal of the second node N2;
  • the noise reduction circuit 50 is configured to respond to the signal of the noise reduction signal terminal VEL, provide the signal of the third reference voltage signal terminal V3 to the second node N2, and control the second output circuit 40 to stop outputting the signal.
  • the output signal terminal can output a driving signal to the coupled signal, thereby realizing the driving process of the coupled signal.
  • the noise reduction circuit can control the second output circuit to stop outputting the signal in the second stage, thereby preventing the first output circuit and the second output circuit from being turned on at the same time, avoiding the short circuit of the first reference voltage signal terminal and the second reference voltage signal terminal, reducing the screen flickering, and improving the display effect.
  • the short circuit of the first reference voltage signal terminal and the second reference voltage signal terminal can also be avoided, reducing the screen flickering and improving the display effect.
  • the noise reduction circuit 50 includes: a first transistor T1; the gate of the first transistor T1 is coupled to the noise reduction signal terminal VEL, the first electrode of the first transistor T1 is coupled to the third reference voltage signal terminal V3, and the second electrode of the first transistor T1 is coupled to the second node N2.
  • the first transistor T1 can be turned on under the control of the effective level of the noise reduction signal transmitted by the noise reduction signal terminal VEL, and can be turned off under the control of the invalid level of the noise reduction signal.
  • the first transistor T1 is set as a P-type transistor, then the effective level of the noise reduction signal is a low level, and the invalid level of the noise reduction signal is a high level.
  • the first transistor T1 is set as an N-type transistor, then the effective level of the noise reduction signal is a high level, and the invalid level of the noise reduction signal is a low level.
  • the first node N1 includes: a first subnode N1-1 and a second subnode N1-2.
  • the shift register unit further includes: a conduction circuit 60; the first subnode N1-1 is coupled to the second subnode N1-2 through the conduction circuit 60; the conduction circuit 60 is configured to conduct the first subnode N1-1 and the second subnode N1-2 in response to the signal of the fourth reference voltage signal terminal V4;
  • the input circuit 10 is further configured to provide a signal from the input signal terminal IP to the first sub-node N1-1 in response to a signal from the first clock signal terminal CK;
  • the first output circuit 30 is further configured to provide a signal of the first reference voltage signal terminal V1 to the output signal terminal OT in response to a signal of the second sub-node N1 - 2 .
  • the control circuit 20 includes: a first control circuit 201 , a second control circuit 202 , and a third control circuit 203 ;
  • the first control circuit 201 is configured to provide the fifth reference voltage signal terminal V5 to the third node N3 in response to the signal of the first clock signal terminal CK, and to provide the signal of the first clock signal terminal CK to the third node N3 in response to the signal of the first sub-node N1-1;
  • the second control circuit 202 is configured to control the signal of the second sub-node N1-2 and the signal of the fourth node N4;
  • the third control circuit 203 is configured to provide the signal of the second clock signal terminal CB to the second node N2 in response to the signal of the fourth node N4 and the second clock signal terminal CB, and to provide the signal of the second reference voltage signal terminal V2 to the second node N2 in response to the signal of the first subnode N1-1.
  • the first control circuit 201 includes: a second transistor T2 and a third transistor T3;
  • the gate of the second transistor T2 is coupled to the first clock signal terminal CK, the first electrode of the second transistor T2 is coupled to the fifth reference voltage signal terminal V5, and the second electrode of the second transistor T2 is coupled to the third node N3;
  • a gate of the third transistor T3 is coupled to the first subnode N1 - 1 , a first electrode of the third transistor T3 is coupled to the third node N3 , and a second electrode of the third transistor T3 is coupled to the first clock signal terminal CK.
  • the second transistor T2 can be turned on under the control of the effective level of the first clock signal transmitted by the first clock signal terminal CK, and can be turned off under the control of the ineffective level of the first clock signal.
  • the second transistor T2 is set as an N-type transistor, then the effective level of the first clock signal is a high level, and the ineffective level of the first clock signal is a low level.
  • the second transistor T2 is set as a P-type transistor, then the effective level of the first clock signal is a low level, and the ineffective level of the first clock signal is a high level.
  • the third transistor T3 can be turned on under the control of the effective level of the signal transmitted by the first subnode N1-1, and can be turned off under the control of the invalid level of the signal.
  • the third transistor T3 is set as an N-type transistor, the effective level of the signal is a high level, and the invalid level of the signal is a low level.
  • the third transistor T3 is set as a P-type transistor, the effective level of the signal is a low level, and the invalid level of the signal is a high level.
  • the second control circuit 202 is further configured to provide the signal of the third node N3 to the fourth node N4 in response to the signal of the fourth reference voltage signal terminal V4, and to provide the signal of the second reference voltage signal terminal V2 to the fifth node N5 in response to the signal of the third node N3, and to provide the signal of the second clock signal terminal CB to the fifth node N5 in response to the signal of the second sub-node N1-2.
  • the second control circuit 202 includes: a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a first capacitor C1 ;
  • a gate of the fourth transistor T4 is coupled to the fourth reference voltage signal terminal V4, a first electrode of the fourth transistor T4 is coupled to the third node N3, and a second electrode of the fourth transistor T4 is coupled to the fourth node N4;
  • a gate of the fifth transistor T5 is coupled to the third node N3, a first electrode of the fifth transistor T5 is coupled to the second reference voltage signal terminal V2, and a second electrode of the fifth transistor T5 is coupled to the fifth node N5;
  • a gate of the sixth transistor T6 is coupled to the second sub-node N1-2, a first electrode of the sixth transistor T6 is coupled to the fifth node N5, and a second electrode of the sixth transistor T6 is coupled to the second clock signal terminal CB;
  • a first electrode of the first capacitor C1 is coupled to the fifth node N5 , and a second electrode of the first capacitor C1 is coupled to the second sub-node N1 - 2 .
  • the fourth transistor T4 can be turned on under the control of the effective level of the fourth reference voltage signal transmitted by the fourth reference voltage signal terminal V4, and can be turned off under the control of the invalid level of the fourth reference voltage signal.
  • the fourth transistor T4 is set as an N-type transistor, then the effective level of the fourth reference voltage signal is a high level, and the invalid level of the fourth reference voltage signal is a low level.
  • the fourth transistor T4 is set as a P-type transistor, then the effective level of the fourth reference voltage signal is a low level, and the invalid level of the fourth reference voltage signal is a high level.
  • the fifth transistor T5 can be turned on under the control of the effective level of the signal transmitted by the third node N3, and can be turned off under the control of the invalid level of the signal.
  • the fifth transistor T5 is set as an N-type transistor, the effective level of the signal is a high level, and the invalid level of the signal is a low level.
  • the fifth transistor T5 is set as a P-type transistor, the effective level of the signal is a low level, and the invalid level of the signal is a high level.
  • the sixth transistor T6 can be turned on under the control of the effective level of the signal transmitted by the second subnode N1-2, and can be turned off under the control of the invalid level of the signal.
  • the sixth transistor T6 is set as an N-type transistor, the effective level of the signal is a high level, and the invalid level of the signal is a low level.
  • the sixth transistor T6 is set as a P-type transistor, the effective level of the signal is a low level, and the invalid level of the signal is a high level.
  • the third control circuit 203 includes: a seventh transistor T7 , an eighth transistor T8 , a ninth transistor T9 , and a second capacitor C2 ;
  • a gate of the seventh transistor T7 is coupled to the fourth node N4, a first electrode of the seventh transistor T7 is coupled to the second clock signal terminal CB, and a second electrode of the seventh transistor T7 is coupled to a first electrode of the eighth transistor T8;
  • a gate of the eighth transistor T8 is coupled to the second clock signal terminal CB, and a second electrode of the eighth transistor T8 is coupled to the second node N2;
  • a gate of the ninth transistor T9 is coupled to the first sub-node N1-1, a first electrode of the ninth transistor T9 is coupled to the second node N2, and a second electrode of the ninth transistor T9 is coupled to the second reference signal terminal V2;
  • a first electrode of the second capacitor C2 is coupled to the fourth node N4 , and a second electrode of the second capacitor C2 is coupled to a first electrode of the eighth transistor T8 .
  • the seventh transistor T7 can be turned on under the control of the effective level of the signal transmitted by the fourth node N4, and can be turned off under the control of the invalid level of the signal.
  • the seventh transistor T7 is set as a P-type transistor, the effective level of the signal is a low level, and the invalid level of the signal is a high level.
  • the seventh transistor T7 is set as an N-type transistor, the effective level of the signal is a high level, and the invalid level of the signal is a low level.
  • the eighth transistor T8 can be turned on under the control of the effective level of the second clock signal transmitted by the second clock signal terminal CB, and can be turned off under the control of the invalid level of the second clock signal.
  • the eighth transistor T8 is set as an N-type transistor, then the effective level of the second clock signal is a high level, and the invalid level of the second clock signal is a low level.
  • the eighth transistor T8 is set as a P-type transistor, then the effective level of the second clock signal is a low level, and the invalid level of the second clock signal is a high level.
  • the ninth transistor T9 can be turned on under the control of the effective level of the signal transmitted by the first subnode N1-1, and can be turned off under the control of the invalid level of the signal.
  • the ninth transistor T9 is set as an N-type transistor, the effective level of the signal is a high level, and the invalid level of the signal is a low level.
  • the ninth transistor T9 is set as a P-type transistor, the effective level of the signal is a low level, and the invalid level of the signal is a high level.
  • the input circuit 10 includes a tenth transistor T10; the gate of the tenth transistor T10 is coupled to the first clock signal terminal CK, the first electrode of the tenth transistor T10 is coupled to the input signal terminal IP, and the second electrode of the tenth transistor T10 is coupled to the first subnode N1-1.
  • the tenth transistor T10 can be turned on under the control of the effective level of the first clock signal transmitted by the first clock signal terminal CK, and can be turned off under the control of the ineffective level of the first clock signal.
  • the tenth transistor T10 is set as an N-type transistor, then the effective level of the first clock signal is a high level, and the ineffective level of the first clock signal is a low level.
  • the tenth transistor T10 is set as a P-type transistor, then the effective level of the first clock signal is a low level, and the ineffective level of the first clock signal is a high level.
  • the first output circuit 30 includes: an eleventh transistor T11;
  • a gate of the eleventh transistor T11 is coupled to the second sub-node N1 - 2 , a first electrode of the eleventh transistor T11 is coupled to the output signal terminal OT, and a second electrode of the eleventh transistor T11 is coupled to the first reference voltage signal terminal V1 .
  • the eleventh transistor T11 can be turned on under the control of the effective level of the signal transmitted by the second subnode N1-2, and can be turned off under the control of the invalid level of the signal.
  • the eleventh transistor T11 is set as an N-type transistor, then the effective level of the signal is a high level, and the invalid level of the signal is a low level.
  • the eleventh transistor T11 is set as a P-type transistor, then the effective level of the signal is a low level, and the invalid level of the signal is a high level.
  • the second output circuit 40 includes: a twelfth transistor T12 and a third capacitor C3;
  • a gate of the twelfth transistor T12 is coupled to the second node N2, a first electrode of the twelfth transistor T12 is coupled to the second reference voltage signal terminal V2, and a second electrode of the twelfth transistor T12 is coupled to the output signal terminal OT;
  • a first electrode of the third capacitor C3 is coupled to the second node N2 , and a second electrode of the third capacitor C3 is coupled to the second reference voltage signal terminal V2 .
  • the twelfth transistor T12 can be turned on under the control of the effective level of the signal transmitted by the second node N2, and can be turned off under the control of the invalid level of the signal.
  • the twelfth transistor T12 is set as an N-type transistor, then the effective level of the signal is a high level, and the invalid level of the signal is a low level.
  • the twelfth transistor T12 is set as a P-type transistor, then the effective level of the signal is a low level, and the invalid level of the signal is a high level.
  • the conduction circuit 60 includes: a thirteenth transistor T13;
  • a gate of the thirteenth transistor T13 is coupled to the fourth reference voltage signal terminal V4 , a first electrode of the thirteenth transistor T13 is coupled to the first sub-node N1 - 1 , and a second electrode of the thirteenth transistor T13 is coupled to the second sub-node N1 - 2 .
  • the thirteenth transistor T13 can be turned on under the control of the effective level of the fourth reference voltage signal transmitted by the fourth reference voltage signal terminal V4, and can be turned off under the control of the invalid level of the fourth reference voltage signal.
  • the thirteenth transistor T13 is set as an N-type transistor, then the effective level of the fourth reference voltage signal is a high level, and the invalid level of the fourth reference voltage signal is a low level.
  • the thirteenth transistor T13 is set as a P-type transistor, then the effective level of the fourth reference voltage signal is a low level, and the invalid level of the fourth reference voltage signal is a high level.
  • the second reference voltage signal terminal V2 and the third reference voltage signal terminal V3 are loaded with the same signal.
  • the second reference voltage signal terminal V2 and the third reference voltage signal terminal V3 can be the same signal terminal, which can reduce the number of signal lines and reduce the difficulty of wiring.
  • the first electrode of the above transistor can be used as its source, and the second electrode can be used as its drain; or, the first electrode can be used as its drain, and the second electrode can be used as its source, without making a specific distinction here.
  • the transistor mentioned in the embodiments of the present disclosure can be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), and no limitation is made here.
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the above transistors can all be set as P-type transistors
  • the first reference voltage signal terminal V1 can be configured to load a constant first reference voltage, and the first reference voltage is generally a negative value.
  • the second reference voltage signal terminal V2 can load a constant second reference voltage, and the second reference voltage can generally be a positive value.
  • the fourth reference voltage signal terminal V4 can be configured to load a constant fourth reference voltage, and the fourth reference voltage is generally a negative value.
  • the value of the first reference voltage can be made smaller than the value of the fourth reference voltage, so that the shift register unit provided by the embodiment of the present disclosure can prevent the screen from flickering while ensuring that the output signal is more stable.
  • the fifth reference voltage signal terminal V5 can be configured to load a constant fifth reference voltage.
  • the value of the fifth reference voltage can be made smaller than the value of the fourth reference voltage, so that the shift register unit provided by the embodiment of the present disclosure can prevent the screen from flickering while ensuring that the output signal is more stable.
  • the value of the fifth reference voltage may be similar to or the same as the value of the first reference voltage, or may be different.
  • the specific values of the above voltages can be designed and determined according to the actual application environment, and are not limited here.
  • the above transistors can all be set as N-type transistors, and are not limited here.
  • the embodiment of the present disclosure provides a driving method of the above-mentioned shift register unit, which includes:
  • the first output circuit responds to the signal of the first node and provides the signal of the first reference voltage signal end to the output signal end.
  • the noise reduction circuit responds to the signal of the noise reduction signal end and provides the signal of the third reference voltage signal end to the second node, thereby controlling the second output circuit to stop outputting the signal.
  • the embodiment of the present disclosure provides a driving method of the above-mentioned shift register unit, including: S100, in the first stage, a second level signal is loaded to the input signal terminal; a second level signal is loaded to the first clock signal terminal, a first level signal is loaded to the second clock signal terminal, and a first level signal is loaded to the noise reduction signal terminal, so that the output signal terminal outputs the first level signal;
  • S300 a third stage, loading a second level signal on the input signal terminal; loading a first level signal on the first clock signal terminal, loading a second level signal on the second clock signal terminal, loading a second level signal on the noise reduction signal terminal, and causing the output signal terminal to output a second level signal;
  • S400 a fourth stage, loading a first level signal on the input signal terminal; loading a second level signal on the first clock signal terminal, loading a first level signal on the second clock signal terminal, loading a second level signal on the noise reduction signal terminal, and causing the output signal terminal to output a second level signal;
  • the first level signal is a low level signal
  • the second level signal is a high level signal
  • the first level signal is a high level signal
  • the second level signal is a low level signal
  • the noise reduction stage may include: a second stage, a third stage, and a fourth stage.
  • the implementation method of the noise reduction stage can be determined according to the needs of the practical application and is not limited here.
  • ip represents the input signal of the input signal terminal IP
  • ck represents the first clock signal of the first clock signal terminal CK
  • cb represents the second clock signal of the second clock signal terminal CB
  • ot represents the output signal of the output signal terminal OT
  • vel represents the noise reduction signal of the noise reduction signal terminal VEL.
  • the fourth transistor T4 and the thirteenth transistor T13 are coupled to the fourth reference voltage signal terminal V4, and the fourth reference voltage signal terminal V4 inputs a low-level signal, the fourth transistor T4 and the thirteenth transistor T13 are in a normally-on state. For ease of description, the following will no longer analyze the states of the fourth transistor T4 and the thirteenth transistor T13 at any time.
  • the input signal ip provides a high level
  • the second clock signal cb provides a high level
  • the first clock signal ck provides a low level
  • the noise reduction signal vel provides a low level
  • the tenth transistor T10 is turned on
  • the high level of the input signal ip is provided to the first subnode N1-1 and the second subnode N1-2
  • the third transistor T3, the sixth transistor T6, the ninth transistor T9 and the eleventh transistor T11 are all turned off.
  • the second transistor T2 is turned on
  • the third node N3 and the fourth node N4 are both low levels
  • the seventh transistor T7 is turned on
  • the eighth transistor T8 is turned off.
  • the first transistor T1 is turned on, the second node N2 is high
  • the twelfth transistor T12 is also turned off, then the signal output by the output signal terminal OT is maintained at a low level.
  • the input signal ip provides a high level
  • the second clock signal cb provides a low level
  • the first clock signal ck provides a high level
  • the noise reduction signal vel provides a high level
  • the tenth transistor T10 is turned off, the first subnode N1-1 and the second subnode N1-2 remain at a high level
  • the third transistor T3, the sixth transistor T6, the ninth transistor T9, and the eleventh transistor T11 are all turned off.
  • the first transistor T1 is turned off, the second transistor T2 is turned off, the third node N3 and the fourth node N4 remain at a low level, the seventh transistor T7 is turned on, the eighth transistor T8 is turned on, the second node N2 is a low level, the twelfth transistor T12 is turned on, and the signal output by the output signal terminal OT is a high level.
  • the input signal ip provides a high level
  • the second clock signal cb provides a high level
  • the first clock signal ck provides a low level
  • the noise reduction signal vel provides a high level
  • the tenth transistor T10 is turned on
  • the high level of the input signal ip is provided to the first subnode N1-1 and the second subnode N1-2
  • the third transistor T3, the sixth transistor T6, the ninth transistor T9 and the eleventh transistor T11 are all turned off.
  • the first transistor T1 is turned off
  • the second transistor T2 is turned on
  • the third node N3 and the fourth node N4 are both low levels
  • the seventh transistor T7 is turned on
  • the eighth transistor T8 is turned off.
  • the second node N2 remains at a low level
  • the twelfth transistor T12 is turned on
  • the signal output by the output signal terminal OT is a high level.
  • the input signal ip provides a low level
  • the second clock signal cb provides a low level
  • the first clock signal ck provides a high level
  • the noise reduction signal vel provides a high level
  • the tenth transistor T10 is turned off, the first subnode N1-1 and the second subnode N1-2 remain at a high level
  • the third transistor T3, the sixth transistor T6, the ninth transistor T9, and the eleventh transistor T11 are all turned off.
  • the first transistor T1 is turned off, the second transistor T2 is turned off, the third node N3 and the fourth node N4 remain at a low level, the seventh transistor T7 is turned on, the eighth transistor T8 is turned on, the second node N2 is a low level, the twelfth transistor T12 is turned on, and the signal output by the output signal terminal OT is a high level.
  • the input signal ip provides a low level
  • the second clock signal cb provides a high level
  • the first clock signal ck provides a low level
  • the noise reduction signal vel provides a low level
  • the tenth transistor T10 is turned on
  • the low level of the input signal ip is provided to the first subnode N1-1 and the second subnode N1-2
  • the third transistor T3, the sixth transistor T6, the ninth transistor T9 and the eleventh transistor T11 are all turned on.
  • the first transistor T1 is turned off
  • the second transistor T2 is turned on
  • the third node N3 and the fourth node N4 are both low levels
  • the seventh transistor T7 is turned on
  • the eighth transistor T8 is turned off.
  • the second node N2 is a high level
  • the twelfth transistor T12 is turned off
  • the signal output by the output signal terminal OT is a low level.
  • the disclosed embodiment also provides another structural diagram of a shift register unit, as shown in Figure 4, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the second control circuit 202 is further configured to provide the signal of the third node N3 to the fourth node N4 in response to the fourth reference voltage signal terminal V4, and to provide the signal of the second reference voltage signal terminal V2 to the fifth node N5 in response to the signal of the fourth node N4, and to provide the signal of the second clock signal terminal CB to the fifth node N5 in response to the signal of the second sub-node N1-2.
  • the second control circuit 202 includes: a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a first capacitor C1 ;
  • a gate of the fourth transistor T4 is coupled to the fourth reference voltage signal terminal V4, a first electrode of the fourth transistor T4 is coupled to the third node N3, and a second electrode of the fourth transistor T4 is coupled to the fourth node N4;
  • a gate of the fifth transistor T5 is coupled to the fourth node N4, a first electrode of the fifth transistor T5 is coupled to the second reference voltage signal terminal V2, and a second electrode of the fifth transistor T5 is coupled to the fifth node N5;
  • a gate of the sixth transistor T6 is coupled to the second subnode N1-2, a first electrode of the sixth transistor T6 is coupled to the fifth node N5, and a second electrode of the sixth transistor T6 is coupled to the second clock signal terminal CB;
  • a first electrode of the first capacitor C1 is coupled to the fifth node N5 , and a second electrode of the first capacitor C1 is coupled to the second sub-node N1 - 2 .
  • the fifth transistor T5 is controlled by the signal of the fourth node N4 to be turned on and off.
  • the rest of the working process can refer to the description of the above embodiment, which will not be repeated here.
  • the disclosed embodiment also provides another structural diagram of a shift register unit, as shown in Figure 5, which is a variation of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the value of the first reference voltage may be the same as the value of the fourth reference voltage.
  • the first reference voltage signal terminal V1 and the fourth reference voltage signal terminal V4 may be the same signal terminal, which may reduce the number of signal lines and reduce the difficulty of wiring.
  • the gate of the eleventh transistor T11 is coupled to the second subnode N1-2, the first electrode of the eleventh transistor T11 is coupled to the output signal terminal OT, and the second electrode of the eleventh transistor T11 is coupled to the fourth reference voltage signal terminal V4.
  • the eleventh transistor T11 when the eleventh transistor T11 is turned on, the signal of the fourth reference voltage signal terminal V4 is provided to the output signal terminal OT.
  • the rest of the working process can refer to the description of the above embodiment, which will not be repeated here.
  • the disclosed embodiment also provides another structural diagram of a shift register unit, as shown in Figure 6, which is a variation of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the value of the fifth reference voltage may be the same as the value of the fourth reference voltage.
  • the fifth reference voltage signal terminal V5 and the fourth reference voltage signal terminal V4 may be the same signal terminal, which may reduce the number of signal lines and reduce the difficulty of wiring.
  • the gate of the second transistor T2 is coupled to the first clock signal terminal CK
  • the first electrode of the second transistor T2 is coupled to the fourth reference voltage signal terminal V4
  • the second electrode of the second transistor T2 is coupled to the third node N3.
  • the signal of the fourth reference voltage signal terminal V4 is provided to the third node N3.
  • the rest of the working process can refer to the description of the above embodiment, which will not be repeated here.
  • the disclosed embodiment also provides another structural diagram of a shift register unit, as shown in Figure 7, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the value of the first reference voltage may be the same as the value of the fourth reference voltage.
  • the first reference voltage signal terminal V1 and the fourth reference voltage signal terminal V4 may be the same signal terminal, which may reduce the number of signal lines and reduce the difficulty of wiring.
  • the gate of the eleventh transistor T11 is coupled to the second subnode N1-2, the first electrode of the eleventh transistor T11 is coupled to the output signal terminal OT, and the second electrode of the eleventh transistor T11 is coupled to the fourth reference voltage signal terminal V4.
  • the eleventh transistor T11 when the eleventh transistor T11 is turned on, the signal of the fourth reference voltage signal terminal V4 is provided to the output signal terminal OT.
  • the rest of the working process can refer to the description of the above embodiment, which will not be repeated here.
  • the disclosed embodiment also provides another structural diagram of a shift register unit, as shown in Figure 8, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the value of the fifth reference voltage may be the same as the value of the fourth reference voltage.
  • the fifth reference voltage signal terminal V5 and the fourth reference voltage signal terminal V4 may be the same signal terminal, which may reduce the number of signal lines and reduce the difficulty of wiring.
  • the gate of the second transistor T2 is coupled to the first clock signal terminal CK
  • the first electrode of the second transistor T2 is coupled to the fourth reference voltage signal terminal V4
  • the second electrode of the second transistor T2 is coupled to the third node N3.
  • the signal of the fourth reference voltage signal terminal V4 is provided to the third node N3.
  • the rest of the working process can refer to the description of the above embodiment, which will not be repeated here.
  • the present disclosure also provides a shift register unit, including:
  • An input circuit (such as the above-mentioned input circuit 10), the input circuit is coupled to an input signal terminal (such as the above-mentioned input signal terminal IP) and a first node (such as the above-mentioned first node N1), and is configured to provide a signal of the input signal terminal to the first node;
  • an input signal terminal such as the above-mentioned input signal terminal IP
  • a first node such as the above-mentioned first node N1
  • control circuit (such as the control circuit 20 described above), the control circuit is coupled to the second node (such as the N2 described above), and is configured to control the second node;
  • a first output transistor (e.g., the twelfth transistor T12 described above), wherein a gate of the first output transistor is coupled to the second node, a first electrode of the first output transistor is coupled to a second reference voltage signal terminal (e.g., the second reference voltage signal terminal V2 described above), a second electrode of the first output transistor is coupled to an output signal terminal (e.g., the OUT described above), and is configured to provide a signal of the second reference voltage signal terminal to the output signal terminal in response to a signal of the second node;
  • a noise reduction transistor e.g., the first transistor T1 mentioned above
  • the gate of the noise reduction transistor is coupled to the noise reduction signal terminal (e.g., the VEL mentioned above)
  • the first electrode of the noise reduction transistor is coupled to the third reference voltage signal terminal (e.g., the V3 mentioned above)
  • the second electrode of the noise reduction transistor is coupled to the second node, and is configured to provide the signal of the third reference voltage signal terminal to the second node in response to the signal of the noise reduction signal terminal.
  • a third capacitor (such as the third capacitor C3 mentioned above) is further included, wherein a first electrode of the third capacitor is coupled to the second reference voltage signal terminal, and a second electrode of the third capacitor is coupled to the second electrode of the noise reduction transistor.
  • a second output transistor (for example, the eleventh transistor T11 mentioned above) is also included, the gate of the second output transistor is coupled to the first node, the first electrode of the output transistor is coupled to the first reference voltage signal terminal (for example, the first reference voltage signal terminal V1 mentioned above), the second electrode of the output transistor is coupled to the output signal terminal, and is configured to provide the signal of the first reference voltage signal terminal to the output signal terminal in response to the signal of the first node.
  • the second reference voltage signal terminal eg. the second reference voltage signal terminal V2 mentioned above
  • the third reference voltage signal terminal eg, the third reference voltage signal terminal V3 mentioned above
  • An embodiment of the present disclosure provides a driving control circuit, comprising a plurality of cascaded shift register units; the input signal end of the first-stage shift register unit is coupled to the frame trigger signal end; in each adjacent bipolar shift register unit, the input signal end of the next-stage shift register unit is coupled to the output signal end of the previous-stage shift register unit.
  • the drive control circuit includes a plurality of cascaded shift register units SR1, SR2, SR3, ... SRn-2, SRn-1 and SRn; wherein n is a natural number. The value of n depends on the actual design requirements.
  • the shift register unit adopts the shift register unit illustrated in FIG1 or FIG4 to FIG8 , and each shift register unit includes an input signal terminal IP, an output signal terminal OT, a noise reduction signal terminal VEL, a first clock signal terminal CK and a second clock signal terminal CB.
  • each endpoint is connected to the signal marked by the timing diagram shown in Figure 3: the input signal terminal IP of the shift register unit SR1 is coupled to the frame trigger signal terminal stv, and in each of the remaining shift register units, the output signal terminal OT of the previous shift register unit is coupled to the input signal terminal IP of the next shift register unit, that is, the signal output by the output signal terminal of the shift register unit SR1 can be used as the signal of the input signal terminal of the shift register unit SR2, and the signal output by the output signal terminal of the shift register unit SR2 can be used as the signal of the input signal terminal of the shift register unit SR3...
  • the signal at the output signal terminal of the shift register unit SRn-1 can be used as the signal of the input signal terminal of the shift register unit SRn, until there is no next-level shift register unit.
  • the noise reduction signal terminal VEL is connected to the noise reduction signal vell
  • the first clock signal terminal CK is connected to the first clock signal ckl
  • the second clock signal terminal CB is connected to the second clock signal cbl.
  • the timing of the gate drive device shown in Figure 9 can be inferred based on the connection relationship of each shift register unit and the timing shown in Figure 3, and will not be repeated here.
  • the embodiment of the present disclosure further provides a display device, comprising a plurality of pixel units, a plurality of signal lines, and the above-mentioned drive control circuit provided by the embodiment of the present disclosure.
  • the output signal end of a shift register unit in the above-mentioned drive control circuit is coupled to at least one signal line of the plurality of signal lines.
  • the principle of solving the problem by the display device is similar to that of the above-mentioned drive control circuit, so the implementation of the display device can refer to the implementation of the above-mentioned drive control circuit, and the repeated parts will not be repeated here.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.
  • the display device may include multiple pixel units, multiple gate lines and data lines, and each pixel unit may include multiple sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels.
  • the above-mentioned display device provided in the embodiment of the present disclosure may be an organic light-emitting display device, or may also be a liquid crystal display device, which is not limited here.
  • a plurality of gate lines are also provided with corresponding drive control circuits; a gate line is coupled to an output signal terminal of a shift register unit in the drive control circuit.
  • the TFT in the sub-pixel can be coupled to the gate line, and the drive control circuit can be used as a gate drive circuit, and the gate drive circuit is coupled to the gate line and is used to provide a gate scan signal to the TFT in the sub-pixel.
  • the TFT in the sub-pixel can be an N-type transistor or a P-type transistor, which is not limited here.
  • the display device when the above-mentioned display device provided in the embodiments of the present disclosure is an organic light-emitting display device, the display device further includes a plurality of light-emitting control signal lines; a driving control circuit is correspondingly provided for the plurality of light-emitting control signal lines; and a light-emitting control signal line is coupled to an output signal terminal of a shift register unit in the driving control circuit.
  • a plurality of gate lines are also correspondingly provided with a driving control circuit; and a gate line is coupled to an output signal terminal of a shift register unit in the driving control circuit.
  • an organic light-emitting display device a plurality of organic light-emitting diodes and a pixel circuit connected to each organic light-emitting diode are generally provided.
  • a light-emitting control transistor for controlling the light emission of the organic light-emitting diode and a scanning control transistor for controlling the input of a data signal are generally provided in the pixel circuit.
  • the light-emitting control transistor may be coupled to the light-emitting control signal line, and the scanning control transistor may be coupled to the gate line.
  • the organic light-emitting display device may include the above-mentioned driving control circuit provided by the embodiment of the present disclosure, and the driving control circuit may be used as a light-emitting driving circuit, and the light-emitting driving circuit is coupled to the light-emitting control transistor and is used to provide a light-emitting control signal of the light-emitting control transistor.
  • the driving control circuit may also be used as a gate driving circuit, and the gate driving circuit is coupled to the gate line and is used to provide a gate scanning signal of the scanning control transistor.
  • the organic light-emitting display device may also include two of the above-mentioned driving control circuits provided in the embodiments of the present disclosure, wherein one of the driving control circuits may be used as a light-emitting driving circuit, coupled to a light-emitting control transistor, and applied to provide a light-emitting control signal for the light-emitting control transistor; and the other driving control circuit may be used as a gate driving circuit, coupled to a gate line, and applied to provide a gate scanning signal for a scanning control transistor, which is not limited here.

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Abstract

提供移位寄存器单元(SRn)、驱动控制电路、显示装置及驱动方法，包括：输入电路(10)，被配置为响应于第一时钟信号端(CK)的信号，将输入信号端(IP)的信号提供给第一节点(N1)；控制电路(20)，被配置为控制第二节点(N2)的信号；第一输出电路(30)，被配置为响应于第一节点(N1)的信号，将第一参考电压信号端(V1)的信号提供给输出信号端(OT)；第二输出电路(40)，被配置为响应于第二节点(N2)的信号，将第二参考电压信号端(V2)的信号提供给输出信号端(OT)；降噪电路(50)，被配置为响应于降噪信号端(VEL)的信号，将第三参考电压信号端(V3)的信号提供给第二节点(N2)，控制第二输出电路(40)停止输出信号。

Description

移位寄存器单元、驱动控制电路、显示装置及驱动方法 技术领域
本发明涉及显示技术领域，尤其涉及移位寄存器单元、驱动控制电路、显示装置及驱动方法。
背景技术
随着显示技术的飞速发展，显示面板呈现出了高集成度和低成本的发展趋势。其中，阵列基板行驱动技术(Gate Driver on Array，GOA)将驱动控制电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动。目前，驱动控制电路通常由多个级联的移位寄存器单元构成。若移位寄存器单元输出不稳定，则会导致显示异常。
发明内容
本公开一些实施例提供的移位寄存器单元，包括：
输入电路，被配置为响应于第一时钟信号端的信号，将输入信号端的信号提供给第一节点；
控制电路，被配置为控制第二节点的信号；
第一输出电路，被配置为响应于所述第一节点的信号，将第一参考电压信号端的信号提供给输出信号端；
第二输出电路，被配置为响应于所述第二节点的信号，将第二参考电压信号端的信号提供给所述输出信号端；
降噪电路，被配置为响应于降噪信号端的信号，将第三参考电压信号端的信号提供给所述第二节点，控制所述第二输出电路停止输出信号。
在本公开提供的一些可能的实施方式中，所述降噪电路包括：第一晶体管；
所述第一晶体管的栅极与所述降噪信号端耦接，所述第一晶体管的第一 极与所述第三参考电压信号端耦接，所述第一晶体管的第二极与所述第二节点耦接。
在本公开提供的一些可能的实施方式中，所述第一节点包括：第一子节点以及第二子节点；
所述移位寄存器单元还包括：导通电路；所述第一子节点通过所述导通电路与所述第二子节点耦接；所述导通电路被配置为响应于第四参考电压信号端的信号，将所述第一子节点与所述第二子节点导通；
所述输入电路进一步被配置为响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第一子节点；
所述第一输出电路进一步被配置为响应于所述第二子节点的信号，将所述第一参考电压信号端的信号提供给所述输出信号端。
在本公开提供的一些可能的实施方式中，所述控制电路包括：第一控制电路、第二控制电路以及第三控制电路；
所述第一控制电路被配置为响应于所述第一时钟信号端的信号，将第五参考电压信号端提供给第三节点，以及响应于所述第一子节点的信号，将所述第一时钟信号端的信号提供给所述第三节点；
所述第二控制电路被配置为控制所述第二子节点的信号以及第四节点的信号；
所述第三控制电路被配置为响应于所述第四节点和第二时钟信号端的信号，将所述第二时钟信号端的信号提供给所述第二节点，以及响应于所述第一子节点的信号，将所述第二参考电压信号端的信号提供给所述第二节点。
在本公开提供的一些可能的实施方式中，所述第一控制电路包括：第二晶体管以及第三晶体管；
所述第二晶体管的栅极与所述第一时钟信号端耦接，所述第二晶体管的第一极与所述第五参考电压信号端耦接，所述第二晶体管的第二极与所述第三节点耦接；
所述第三晶体管的栅极与所述第一子节点耦接，所述第三晶体管的第一 极与所述第三节点耦接，所述第三晶体管的第二极与所述第一时钟信号端耦接。
在本公开提供的一些可能的实施方式中，所述第二控制电路进一步被配置为响应于所述第四参考电压信号端的信号，将所述第三节点的信号提供给所述第四节点，以及响应于所述第三节点的信号，将所述第二参考电压信号端的信号提供给第五节点，以及响应于所述第二子节点的信号，将所述第二时钟信号端的信号提供给所述第五节点。
在本公开提供的一些可能的实施方式中，所述第二控制电路包括：第四晶体管、第五晶体管、第六晶体管以及第一电容；
所述第四晶体管的栅极与所述第四参考电压信号端耦接，所述第四晶体管的第一极与所述第三节点耦接，所述第四晶体管的第二极与所述第四节点耦接；
所述第五晶体管的栅极与所述第三节点耦接，所述第五晶体管的第一极与所述第二参考电压信号端耦接，所述第五晶体管的第二极与所述第五节点耦接；
所述第六晶体管的栅极与所述第二子节点耦接，所述第六晶体管的第一极与所述第五节点耦接，所述第六晶体管的第二极与所述第二时钟信号端耦接；
所述第一电容的第一电极与所述第五节点耦接，所述第一电容的第二电极与所述第二子节点耦接。
在本公开提供的一些可能的实施方式中，所述第二控制电路进一步被配置为响应于所述第四参考电压信号端，将所述第三节点的信号提供给所述第四节点，以及响应于所述第四节点的信号，将所述第二参考电压信号端的信号提供给第五节点，以及响应于所述第二子节点的信号，将所述第二时钟信号端的信号提供给所述第五节点。
在本公开提供的一些可能的实施方式中，所述第二控制电路包括：第四晶体管、第五晶体管、第六晶体管以及第一电容；
所述第四晶体管的栅极与所述第四参考电压信号端耦接，所述第四晶体管的第一极与所述第三节点耦接，所述第四晶体管的第二极与所述第四节点耦接；
所述第五晶体管的栅极与所述第四节点耦接，所述第五晶体管的第一极与所述第二参考电压信号端耦接，所述第五晶体管的第二极与所述第五节点耦接；
所述第六晶体管的栅极与所述第二子节点耦接，所述第六晶体管的第一极与所述第五节点耦接，所述第六晶体管的第二极与所述第二时钟信号端耦接；
所述第一电容的第一电极与所述第五节点耦接，所述第一电容的第二电极与所述第二子节点耦接。
在本公开提供的一些可能的实施方式中，所述第三控制电路包括：第七晶体管、第八晶体管、第九晶体管以及第二电容；
所述第七晶体管的栅极与所述第四节点耦接，所述第七晶体管的第一极与所述第二时钟信号端耦接，所述第七晶体管的第二极与所述第八晶体管的第一极耦接；
所述第八晶体管的栅极与所述第二时钟信号端耦接，所述第八晶体管的第二极与所述第二节点耦接；
所述第九晶体管的栅极与所述第一子节点耦接，所述第九晶体管的第一极与所述第二节点耦接，所述第九晶体管的第二极与所述第二参考信号端耦接；
所述第二电容的第一电极与所述第四节点耦接，所述第二电容的第二电极与所述第八晶体管的第一极耦接。
在本公开提供的一些可能的实施方式中，所述输入电路包括第十晶体管；
所述第十晶体管的栅极与所述第一时钟信号端耦接，所述第十晶体管的第一极与所述输入信号端耦接，所述第十晶体管的第二极与所述第一子节点耦接。
在本公开提供的一些可能的实施方式中，所述第一输出电路包括：第十一晶体管；
所述第十一晶体管的栅极与所述第二子节点耦接，所述第十一晶体管的第一极与所述输出信号端耦接，所述第十一晶体管的第二极与所述第一参考电压信号端耦接。
在本公开提供的一些可能的实施方式中，所述第二输出电路包括：第十二晶体管以及第三电容；
所述第十二晶体管的栅极与所述第二节点耦接，所述第十二晶体管的第一极与所述第二参考电压信号端耦接，所述第十二晶体管的第二极与所述输出信号端耦接；
所述第三电容的第一电极与所述第二节点耦接，所述第三电容的第二电极与所述第二参考电压信号端耦接。
在本公开提供的一些可能的实施方式中，所述导通电路包括：第十三晶体管；
所述第十三晶体管的栅极与所述第四参考电压信号端耦接，所述第十三晶体管的第一极与所述第一子节点耦接，所述第十三晶体管的第二极与所述第二子节点耦接。
在本公开提供的一些可能的实施方式中，所述第二参考电压信号端与所述第三参考电压信号端为同一信号端。
本公开实施例还提供了一种移位寄存器单元，包括：
输入电路，所述输入电路与输入信号端以及第一节点耦接，被配置为将所述输入信号端的信号提供给所述第一节点；
控制电路，所述控制电路与第二节点耦接，被配置为控制所述第二节点；
第一输出晶体管，所述第一输出晶体管的栅极与所述第二节点耦接，所述第一输出晶体管的第一极与第二参考电压信号端耦接，所述第一输出晶体管的第二极与输出信号端耦接，被配置为响应于所述第二节点的信号，将所述第二参考电压信号端的信号提供给所述输出信号端；
降噪晶体管，所述降噪晶体管的栅极与降噪信号端耦接，所述降噪晶体管的第一极与第三参考电压信号端耦接，所述降噪晶体管的第二极与所述第二节点耦接，被配置为响应于所述降噪信号端的信号，将所述第三参考电压信号端的信号提供给所述第二节点。
在本公开提供的一些可能的实施方式中，还包括第三电容，所述第三电容的第一电极与所述第二参考电压信号端耦接，所述第三电容的第二电极与所述降噪晶体管的第二极耦接。
在本公开提供的一些可能的实施方式中，还包括第二输出晶体管，所述第二输出晶体管的栅极与所述第一节点耦接，所述输出晶体管的第一极与所述第一参考电压信号端耦接，所述输出晶体管的第二极与所述输出信号端耦接，被配置为响应于所述第一节点的信号，将所述第一参考电压信号端的信号提供给所述输出信号端。
在本公开提供的一些可能的实施方式中，所述第二参考电压信号端与所述第三参考电压信号端为同一信号端。
本公开实施例还提供了驱动控制电路，包括级联的多个上述的移位寄存器单元；
第一级移位寄存器单元的所述输入信号端与帧触发信号端耦接；
每相邻的两极移位寄存器单元中，下一级移位寄存器单元的所述输入信号端与上一级移位寄存器单元的所述输出信号端耦接。
本公开实施例还提供了显示装置，包括上述的驱动控制电路。
本公开实施例还提供了一种上述的移位寄存器单元的驱动方法，包括：
降噪阶段，所述第一输出电路响应于所述第一节点的信号，将所述第一参考电压信号端的信号提供给所述输出信号端，所述降噪电路响应于所述降噪信号端的信号，将所述第三参考电压信号端的信号提供给所述第二节点，控制所述第二输出电路停止输出信号。
附图说明
图1为本公开实施例提供的移位寄存器单元的一些结构示意图；
图2为本公开实施例提供的移位寄存器单元的驱动方法流程图；
图3为本公开实施例提供的一些信号时序图；
图4为本公开实施例提供的移位寄存器单元的另一些结构示意图；
图5为本公开实施例提供的移位寄存器单元的又一些结构示意图；
图6为本公开实施例提供的移位寄存器单元的又一些结构示意图；
图7为本公开实施例提供的移位寄存器单元的又一些结构示意图；
图8为本公开实施例提供的移位寄存器单元的又一些结构示意图；
图9为本公开实施例提供的驱动控制电路的一些结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本发明内容。并且自始至终相同或类似的标号表示相同或类似的元 件或具有相同或类似功能的元件。
本公开实施例提供一种移位寄存器单元，如图1所示，包括：
输入电路10，被配置为响应于第一时钟信号端CK的信号，将输入信号端IP的信号提供给第一节点N1；
控制电路20，被配置为控制第二节点N2的信号；
第一输出电路30，被配置为响应于第一节点N1的信号，将第一参考电压信号端V1的信号提供给输出信号端OT；
第二输出电路40，被配置为响应于第二节点N2的信号，将第二参考电压信号端V2的信号提供给输出信号端OT；
降噪电路50，被配置为响应于降噪信号端VEL的信号，将第三参考电压信号端V3的信号提供给第二节点N2，控制第二输出电路40停止输出信号。
在本公开实施例中，通过输入电路、控制电路、第一输出电路、第二输出电路以及降噪电路的相互配合，可以使输出信号端向耦接的信号输出驱动信号，实现对耦接的信号的驱动过程。并且，通过设置降噪电路，可以在第二阶段使降噪电路控制第二输出电路停止输出信号，从而阻止了第一输出电路和第二输出电路同时导通，避免第一参考电压信号端和第二参考电压信号端短路，降低画面闪烁，提高显示效果。以及，在异常掉电或初始化情况下，由于降噪电路的作用，也可以避免第一参考电压信号端和第二参考电压信号端短路，降低画面闪烁，提高了显示效果。
在本公开实施例中，如图1所示，降噪电路50包括：第一晶体管T1；第一晶体管T1的栅极与降噪信号端VEL耦接，第一晶体管T1的第一极与第三参考电压信号端V3耦接，第一晶体管T1的第二极与第二节点N2耦接。
示例性地，第一晶体管T1可以在降噪信号端VEL传输的降噪信号的有效电平的控制下导通，可以在降噪信号的无效电平的控制下截止。示例性地，第一晶体管T1设置为P型晶体管，则降噪信号有效电平为低电平，降噪信号的无效电平为高电平。或者，第一晶体管T1设置为N型晶体管，则降噪信号的有效电平为高电平，降噪信号的无效电平为低电平。
在本公开实施例中，如图1所示，第一节点N1包括：第一子节点N1-1以及第二子节点N1-2。移位寄存器单元还包括：导通电路60；第一子节点N1-1通过导通电路60与第二子节点N1-2耦接；导通电路60被配置为响应于第四参考电压信号端V4的信号，将第一子节点N1-1第二子节点N1-2导通；
输入电路10进一步被配置为响应于第一时钟信号端CK的信号，将输入信号端IP的信号提供给第一子节点N1-1；
第一输出电路30进一步被配置为响应于第二子节点N1-2的信号，将第一参考电压信号端V1的信号提供给输出信号端OT。
在本公开实施例中，如图1所示，控制电路20包括：第一控制电路201、第二控制电路202以及第三控制电路203；
第一控制电路201被配置为响应于第一时钟信号端CK的信号，将第五参考电压信号端V5提供给第三节点N3，以及响应于第一子节点N1-1的信号，将第一时钟信号端CK的信号提供给第三节点N3；
第二控制电路202被配置为控制第二子节点N1-2的信号以及第四节点N4的信号；
第三控制电路203被配置为响应于第四节点N4和第二时钟信号端CB的信号，将第二时钟信号端CB的信号提供给第二节点N2，以及响应于第一子节点N1-1的信号，将第二参考电压信号端V2的信号提供给第二节点N2。
在本公开实施例中，如图1所示，第一控制电路201包括：第二晶体管T2以及第三晶体管T3；
第二晶体管T2的栅极与第一时钟信号端CK耦接，第二晶体管T2的第一极与第五参考电压信号端V5耦接，第二晶体管T2的第二极与第三节点N3耦接；
第三晶体管T3的栅极与第一子节点N1-1耦接，第三晶体管T3的第一极与第三节点N3耦接，第三晶体管T3的第二极与第一时钟信号端CK耦接。
示例性地，第二晶体管T2可以在第一时钟信号端CK传输的第一时钟信号的有效电平的控制下导通，可以在第一时钟信号的无效电平的控制下截止。 示例性地，第二晶体管T2设置为N型晶体管，则第一时钟信号的有效电平为高电平，第一时钟信号的无效电平为低电平。或者，第二晶体管T2设置为P型晶体管，则第一时钟信号效电平为低电平，第一时钟信号的无效电平为高电平。
示例性地，第三晶体管T3可以在第一子节点N1-1传输的信号的有效电平的控制下导通，可以在信号的无效电平的控制下截止。示例性地，第三晶体管T3设置为N型晶体管，则信号的有效电平为高电平，信号的无效电平为低电平。或者，第三晶体管T3设置为P型晶体管，则信号的有效电平为低电平，信号的无效电平为高电平。
在本公开实施例中，如图1所示，第二控制电路202进一步被配置为响应于第四参考电压信号端V4的信号，将第三节点N3的信号提供给第四节点N4，以及响应于第三节点N3的信号，将第二参考电压信号端V2的信号提供给第五节点N5，以及响应于第二子节点N1-2的信号，将第二时钟信号端CB的信号提供给第五节点N5。
在本公开实施例中，如图1所示，第二控制电路202包括：第四晶体管T4、第五晶体管T5、第六晶体管T6以及第一电容C1；
第四晶体管T4的栅极与第四参考电压信号端V4耦接，第四晶体管T4的第一极与第三节点N3耦接，第四晶体管T4的第二极与第四节点N4耦接；
第五晶体管T5的栅极与第三节点N3耦接，第五晶体管T5的第一极与第二参考电压信号端V2耦接，第五晶体管T5的第二极与第五节点N5耦接；
第六晶体管T6的栅极与第二子节点N1-2耦接，第六晶体管T6的第一极与第五节点N5耦接，第六晶体管T6的第二极与第二时钟信号端CB耦接；
第一电容C1的第一电极与第五节点N5耦接，第一电容C1的第二电极与第二子节点N1-2耦接。
示例性地，第四晶体管T4可以在第四参考电压信号端V4传输的第四参考电压信号的有效电平的控制下导通，可以在第四参考电压信号的无效电平的控制下截止。示例性地，第四晶体管T4设置为N型晶体管，则第四参考电 压信号的有效电平为高电平，第四参考电压信号的无效电平为低电平。或者，第四晶体管T4设置为P型晶体管，则第四参考电压信号的有效电平为低电平，第四参考电压信号的无效电平为高电平。
示例性地，第五晶体管T5可以在第三节点N3传输的信号的有效电平的控制下导通，可以在信号的无效电平的控制下截止。示例性地，第五晶体管T5设置为N型晶体管，则信号的有效电平为高电平，信号的无效电平为低电平。或者，第五晶体管T5设置为P型晶体管，则信号的有效电平为低电平，信号的无效电平为高电平。
示例性地，第六晶体管T6可以在第二子节点N1-2传输的信号的有效电平的控制下导通，可以在信号的无效电平的控制下截止。示例性地，第六晶体管T6设置为N型晶体管，则信号的有效电平为高电平，信号的无效电平为低电平。或者，第六晶体管T6设置为P型晶体管，则信号的有效电平为低电平，信号的无效电平为高电平。
在本公开实施例中，如图1所示，第三控制电路203包括：第七晶体管T7、第八晶体管T8、第九晶体管T9以及第二电容C2；
第七晶体管T7的栅极与第四节点N4耦接，第七晶体管T7的第一极与第二时钟信号端CB耦接，第七晶体管T7的第二极与第八晶体管T8的第一极耦接；
第八晶体管T8的栅极与第二时钟信号端CB耦接，第八晶体管T8的第二极与第二节点N2耦接；
第九晶体管T9的栅极与第一子节点N1-1耦接，第九晶体管T9的第一极与第二节点N2耦接，第九晶体管T9的第二极与第二参考信号端V2耦接；
第二电容C2的第一电极与第四节点N4耦接，第二电容C2的第二电极与第八晶体管T8的第一极耦接。
示例性地，第七晶体管T7可以在第四节点N4传输的信号的有效电平的控制下导通，可以在信号的无效电平的控制下截止。示例性地，第七晶体管T7设置为P型晶体管，则信号有效电平为低电平，信号的无效电平为高电平。 或者，第七晶体管T7设置为N型晶体管，则信号有效电平为高电平，信号的无效电平为低电平。
示例性地，第八晶体管T8可以在第二时钟信号端CB传输的第二时钟信号的有效电平的控制下导通，可以在第二时钟信号的无效电平的控制下截止。示例性地，第八晶体管T8设置为N型晶体管，则第二时钟信号的有效电平为高电平，第二时钟信号的无效电平为低电平。或者，第八晶体管T8设置为P型晶体管，则第二时钟信号效电平为低电平，第二时钟信号的无效电平为高电平。
示例性地，第九晶体管T9可以在第一子节点N1-1传输的信号的有效电平的控制下导通，可以在信号的无效电平的控制下截止。示例性地，第九晶体管T9设置为N型晶体管，则信号的有效电平为高电平，信号的无效电平为低电平。或者，第九晶体管T9设置为P型晶体管，则信号的有效电平为低电平，信号的无效电平为高电平。
在本公开实施例中，如图1所示，输入电路10包括第十晶体管T10；第十晶体管T10的栅极与第一时钟信号端CK耦接，第十晶体管T10的第一极与输入信号端IP耦接，第十晶体管T10的第二极与第一子节点N1-1耦接。
示例性地，第十晶体管T10可以在第一时钟信号端CK传输的第一时钟信号的有效电平的控制下导通，可以在第一时钟信号的无效电平的控制下截止。示例性地，第十晶体管T10设置为N型晶体管，则第一时钟信号的有效电平为高电平，第一时钟信号的无效电平为低电平。或者，第十晶体管T10设置为P型晶体管，则第一时钟信号效电平为低电平，第一时钟信号的无效电平为高电平。
在本公开实施例中，如图1所示，第一输出电路30包括：第十一晶体管T11；
第十一晶体管T11的栅极与第二子节点N1-2耦接，第十一晶体管T11的第一极与输出信号端OT耦接，第十一晶体管T11的第二极与第一参考电压信号端V1耦接。
示例性地，第十一晶体管T11可以在第二子节点N1-2传输的信号的有效电平的控制下导通，可以在信号的无效电平的控制下截止。示例性地，第十一晶体管T11设置为N型晶体管，则信号的有效电平为高电平，信号的无效电平为低电平。或者，第十一晶体管T11设置为P型晶体管，则信号的有效电平为低电平，信号的无效电平为高电平。
在本公开实施例中，如图1所示，第二输出电路40包括：第十二晶体管T12以及第三电容C3；
第十二晶体管T12的栅极与第二节点N2耦接，第十二晶体管T12的第一极与第二参考电压信号端V2耦接，第十二晶体管T12的第二极与输出信号端OT耦接；
第三电容C3的第一电极与第二节点N2耦接，第三电容C3的第二电极与第二参考电压信号端V2耦接。
示例性地，第十二晶体管T12可以在第二节点N2传输的信号的有效电平的控制下导通，可以在信号的无效电平的控制下截止。示例性地，第十二晶体管T12设置为N型晶体管，则信号的有效电平为高电平，信号的无效电平为低电平。或者，第十二晶体管T12设置为P型晶体管，则信号的有效电平为低电平，信号的无效电平为高电平。
在本公开实施例中，如图1所示，导通电路60包括：第十三晶体管T13；
第十三晶体管T13的栅极与第四参考电压信号端V4耦接，第十三晶体管T13的第一极与第一子节点N1-1耦接，第十三晶体管T13的第二极与第二子节点N1-2耦接。
示例性地，第十三晶体管T13可以在第四参考电压信号端V4传输的第四参考电压信号的有效电平的控制下导通，可以在第四参考电压信号的无效电平的控制下截止。示例性地，第十三晶体管T13设置为N型晶体管，则第四参考电压信号的有效电平为高电平，第四参考电压信号的无效电平为低电平。或者，第十三晶体管T13设置为P型晶体管，则第四参考电压信号的有效电平为低电平，第四参考电压信号的无效电平为高电平。
在本公开实施例中，第二参考电压信号端V2与第三参考电压信号端V3上加载相同的信号。示例性地，第二参考电压信号端V2与第三参考电压信号端V3可以为同一信号端，这样可以降低信号线的数量，降低布线难度。
在具体实施时，根据信号的流通方向，上述晶体管的第一极可以作为其源极，第二极可以作为其漏极；或者，第一极作为其漏极，第二极作为其源极，在此不作具体区分。
需要说明的是本公开实施例中提到的晶体管可以是薄膜晶体管(Thin Film Transistor，TFT)，也可以是金属氧化物半导体场效应管(Metal Oxide Scmiconductor，MOS)，在此不做限定。
在本公开实施例中，上述晶体管可以均设置为P型晶体管，第一参考电压信号端V1可以被配置为加载恒定的第一参考电压，并且第一参考电压一般为负值。以及，第二参考电压信号端V2可以加载恒定的第二参考电压，并且第二参考电压一般可以为正值。
在本公开实施例中，第四参考电压信号端V4可以被配置为加载恒定的第四参考电压，并且第四参考电压一般为负值。示例性地，可以使第一参考电压的值小于第四参考电压的值，这样可以使本公开实施例提供的移位寄存器单元在防止画面闪烁的同时，可以保证输出信号更为稳定。
在本公开实施例中，第五参考电压信号端V5可以被配置为加载恒定的第五参考电压。示例性地，可以使第五参考电压的值小于第四参考电压的值，这样可以使本公开实施例提供的移位寄存器单元在防止画面闪烁的同时，可以保证输出信号更为稳定。
在本公开实施例中，可以使第五参考电压的值与第一参考电压的值相似或相同。当然也可以不同。
在实际应用中，上述电压具体数值可以根据实际应用环境来设计确定，在此不作限定。当然，上述晶体管可以均设置为N型晶体管，在此不作限定。
本公开实施例提供一种上述的移位寄存器单元的驱动方法，其中，包括：
降噪阶段，第一输出电路响应于第一节点的信号，将第一参考电压信号 端的信号提供给输出信号端，降噪电路响应于降噪信号端的信号，将第三参考电压信号端的信号提供给第二节点，控制第二输出电路停止输出信号。
如图2所示，本公开实施例提供一种上述的移位寄存器单元的驱动方法，包括：S100、第一阶段，对输入信号端加载第二电平信号；对第一时钟信号端加载第二电平信号，对第二时钟信号端加载第一电平信号，对降噪信号端加载第一电平信号，使输出信号端输出第一电平信号；
S200、第二阶段，对输入信号端加载第二电平信号；对第一时钟信号端加载第二电平信号，对第二时钟信号端加载第一电平信号，对降噪信号端加载第二电平信号，使输出信号端输出第二电平信号；
S300、第三阶段，对输入信号端加载第二电平信号；对第一时钟信号端加载第一电平信号，对第二时钟信号端加载第二电平信号，对降噪信号端加载第二电平信号，使输出信号端输出第二电平信号；
S400、第四阶段，对输入信号端加载第一电平信号；对第一时钟信号端加载第二电平信号，对第二时钟信号端加载第一电平信号，对降噪信号端加载第二电平信号，使输出信号端输出第二电平信号；
S500、第五阶段，对输入信号端加载第一电平信号；对第一时钟信号端加载第一电平信号，对第二时钟信号端加载第二电平信号，对降噪信号端加载第一电平信号，使输出信号端输出第一电平信号。
示例性的，在移位寄存器单元中的晶体管均为P型晶体管时，第一电平信号为低电平信号，第二电平信号为高电平信号。或者，在移位寄存器单元中的晶体管均为N型晶体管时，第一电平信号为高电平信号，第二电平信号为低电平信号。
示例性的，降噪阶段可以包括：第二阶段、第三阶段以及第四阶段。
当然，在实际应用中，降噪阶段可的实施方式可以根据实际应用的需求进行确定，在此不作限定。
下面以图1所示的移位寄存器单元为例，结合图3所示的信号时序图，对本公开实施例提供的像素驱动电路的工作过程作以描述。
其中，ip代表输入信号端IP的输入信号，ck代表第一时钟信号端CK的第一时钟信号，cb代表第二时钟信号端CB的第二时钟信号，ot代表输出信号端OT的输出信号，vel代表降噪信号端VEL的降噪信号。
由于第四晶体管T4和第十三晶体管T13的栅极都与第四参考电压信号端V4耦接，第四参考电压信号端V4输入的为低电平信号，因此第四晶体管T4和第十三晶体管T13为常导通状态，为便于描述，下文不再就任意时刻第四晶体管T4和第十三晶体管T13的状态做分析。
第一阶段F1，输入信号ip提供高电平，第二时钟信号cb提供高电平，第一时钟信号ck提供低电平，降噪信号vel提供低电平，则第十晶体管T10打开，输入信号ip的高电平提供给第一子节点N1-1和第二子节点N1-2，第三晶体管T3、第六晶体管T6、第九晶体管T9以及第十一晶体管T11均截止。并且，第二晶体管T2打开，第三节点N3和第四节点N4均为低电平，第七晶体管T7导通，第八晶体管T8截止。第一晶体管T1导通，第二节点N2为高电平，第十二晶体管T12也截止，则输出信号端OT输出的信号维持为低电平。
第二阶段F2，输入信号ip提供高电平，第二时钟信号cb提供低电平，第一时钟信号ck提供高电平，降噪信号vel提供高电平，则第十晶体管T10截止，第一子节点N1-1和第二子节点N1-2保持为高电平，第三晶体管T3、第六晶体管T6、第九晶体管T9以及第十一晶体管T11均截止。并且，第一晶体管T1截止，第二晶体管T2截止，第三节点N3和第四节点N4保持为低电平，第七晶体管T7导通，第八晶体管T8导通，则第二节点N2为低电平，第十二晶体管T12导通，则输出信号端OT输出的信号为高电平。
第三阶段F3，输入信号ip提供高电平，第二时钟信号cb提供高电平，第一时钟信号ck提供低电平，降噪信号vel提供高电平，则第十晶体管T10打开，输入信号ip的高电平提供给第一子节点N1-1和第二子节点N1-2，第三晶体管T3、第六晶体管T6、第九晶体管T9以及第十一晶体管T11均截止。并且，第一晶体管T1截止，第二晶体管T2打开，第三节点N3和第四节点 N4均为低电平，第七晶体管T7导通，第八晶体管T8截止。第二节点N2保持低电平，第十二晶体管T12导通，则输出信号端OT输出的信号为高电平。
第四阶段F4，输入信号ip提供低电平，第二时钟信号cb提供低电平，第一时钟信号ck提供高电平，降噪信号vel提供高电平，则第十晶体管T10截止，第一子节点N1-1和第二子节点N1-2保持为高电平，第三晶体管T3、第六晶体管T6、第九晶体管T9以及第十一晶体管T11均截止。并且，第一晶体管T1截止，第二晶体管T2截止，第三节点N3和第四节点N4保持为低电平，第七晶体管T7导通，第八晶体管T8导通，则第二节点N2为低电平，第十二晶体管T12导通，则输出信号端OT输出的信号为高电平。
第五阶段F5，输入信号ip提供低电平，第二时钟信号cb提供高电平，第一时钟信号ck提供低电平，降噪信号vel提供低电平，则第十晶体管T10打开，输入信号ip的低电平提供给第一子节点N1-1和第二子节点N1-2，第三晶体管T3、第六晶体管T6、第九晶体管T9以及第十一晶体管T11均导通。并且，第一晶体管T1截止，第二晶体管T2打开，第三节点N3和第四节点N4均为低电平，第七晶体管T7导通，第八晶体管T8截止。第二节点N2为高电平，第十二晶体管T12截止，则输出信号端OT输出的信号为低电平。
本公开实施例还提供了移位寄存器单元的另一种结构示意图，如图4所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开实施例中，如图4所示，第二控制电路202进一步被配置为响应于第四参考电压信号端V4，将第三节点N3的信号提供给第四节点N4，以及响应于第四节点N4的信号，将第二参考电压信号端V2的信号提供给第五节点N5，以及响应于第二子节点N1-2的信号，将第二时钟信号端CB的信号提供给第五节点N5。
在本公开实施例中，如图4所示，第二控制电路202包括：第四晶体管T4、第五晶体管T5、第六晶体管T6以及第一电容C1；
第四晶体管T4的栅极与第四参考电压信号端V4耦接，第四晶体管T4 的第一极与第三节点N3耦接，第四晶体管T4的第二极与第四节点N4耦接；
第五晶体管T5的栅极与第四节点N4耦接，第五晶体管T5的第一极与第二参考电压信号端V2耦接，第五晶体管T5的第二极与第五节点N5耦接；
第六晶体管T6的栅极与第二子节点N1-2耦接，第六晶体管T6的第一极与第五节点N5耦接，第六晶体管T6的第二极与第二时钟信号端CB耦接；
第一电容C1的第一电极与第五节点N5耦接，第一电容C1的第二电极与第二子节点N1-2耦接。
基于上述实施例，第五晶体管T5受第四节点N4的信号的控制，实现导通和截止。其余工作过程可以参照上述实施例的描述，在此不作赘述。
本公开实施例还提供了移位寄存器单元的又一种结构示意图，如图5所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开实施例中，也可以使第一参考电压的值与第四参考电压的值相同。示例性地，可以使第一参考电压信号端V1与第四参考电压信号端V4为同一信号端，这样可以降低信号线的数量，降低布线难度。示例性的，如图5所示，第十一晶体管T11的栅极与第二子节点N1-2耦接，第十一晶体管T11的第一极与输出信号端OT耦接，第十一晶体管T11的第二极与第四参考电压信号端V4耦接。
基于上述实施例，第十一晶体管T11导通时，将第四参考电压信号端V4的信号提供给输出信号端OT。其余工作过程可以参照上述实施例的描述，在此不作赘述。
本公开实施例还提供了移位寄存器单元的又一种结构示意图，如图6所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开实施例中，也可以使第五参考电压的值与第四参考电压的值相同。示例性地，可以使第五参考电压信号端V5与第四参考电压信号端V4为同一信号端，这样可以降低信号线的数量，降低布线难度。例如，如图6所 示，第二晶体管T2的栅极与第一时钟信号端CK耦接，第二晶体管T2的第一极与第四参考电压信号端V4耦接，第二晶体管T2的第二极与第三节点N3耦接。
基于上述实施例，第二晶体管T2导通时，将第四参考电压信号端V4的信号提供给第三节点N3。其余工作过程可以参照上述实施例的描述，在此不作赘述。
本公开实施例还提供了移位寄存器单元的又一种结构示意图，如图7所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开实施例中，也可以使第一参考电压的值与第四参考电压的值相同。示例性地，可以使第一参考电压信号端V1与第四参考电压信号端V4为同一信号端，这样可以降低信号线的数量，降低布线难度。示例性的，如图7所示，第十一晶体管T11的栅极与第二子节点N1-2耦接，第十一晶体管T11的第一极与输出信号端OT耦接，第十一晶体管T11的第二极与第四参考电压信号端V4耦接。
基于上述实施例，第十一晶体管T11导通时，将第四参考电压信号端V4的信号提供给输出信号端OT。其余工作过程可以参照上述实施例的描述，在此不作赘述。
本公开实施例还提供了移位寄存器单元的又一种结构示意图，如图8所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开实施例中，也可以使第五参考电压的值与第四参考电压的值相同。示例性地，可以使第五参考电压信号端V5与第四参考电压信号端V4为同一信号端，这样可以降低信号线的数量，降低布线难度。例如，如图8所示，第二晶体管T2的栅极与第一时钟信号端CK耦接，第二晶体管T2的第一极与第四参考电压信号端V4耦接，第二晶体管T2的第二极与第三节点N3耦接。
基于上述实施例，第二晶体管T2导通时，将第四参考电压信号端V4的信号提供给第三节点N3。其余工作过程可以参照上述实施例的描述，在此不作赘述。
本公开实施例还提供了一种移位寄存器单元，包括：
输入电路(例如上述的输入电路10)，输入电路与输入信号端(例如上述的输入信号端IP)以及第一节点(例如上述的第一节点N1)耦接，被配置为将输入信号端的信号提供给第一节点；
控制电路(例如上述的控制电路20)，控制电路与第二节点(例如上述的N2)耦接，被配置为控制第二节点；
第一输出晶体管(例如上述的第十二晶体管T12)，第一输出晶体管的栅极与第二节点耦接，第一输出晶体管的第一极与第二参考电压信号端(例如上述的第二参考电压信号端V2)耦接，第一输出晶体管的第二极与输出信号端(例如上述的OUT)耦接，被配置为响应于第二节点的信号，将第二参考电压信号端的信号提供给输出信号端；
降噪晶体管(例如上述的第一晶体管T1)，降噪晶体管的栅极与降噪信号端(例如上述的VEL)耦接，降噪晶体管的第一极与第三参考电压信号端(例如上述的V3)耦接，降噪晶体管的第二极与第二节点耦接，被配置为响应于降噪信号端的信号，将第三参考电压信号端的信号提供给第二节点。
并且，该实施例中的移位寄存器单元的工作过程可以参照上述描述，在此不作赘述。
在本公开实施例中，还包括第三电容(例如上述的第三电容C3)，第三电容的第一电极与第二参考电压信号端耦接，第三电容的第二电极与降噪晶体管的第二极耦接。
在本公开实施例中，还包括第二输出晶体管(例如上述的第十一晶体管T11)，第二输出晶体管的栅极与第一节点耦接，输出晶体管的第一极与第一参考电压信号端(例如上述的第一参考电压信号端V1)耦接，输出晶体管的第二极与输出信号端耦接，被配置为响应于第一节点的信号，将第一参考电 压信号端的信号提供给输出信号端。
在本公开实施例中，第二参考电压信号端(例如上述的第二参考电压信号端V2)与第三参考电压信号端(例如上述的第三参考电压信号端V3)为同一信号端。
本公开实施例提供一种驱动控制电路，包括级联的多个移位寄存器单元；第一级移位寄存器单元的输入信号端与帧触发信号端耦接；每相邻的两极移位寄存器单元中，下一级移位寄存器单元的输入信号端与上一级移位寄存器单元的输出信号端耦接。
示例性的，如图9所示，驱动控制电路包括多个级联的移位寄存器单元SR1、SR2、SR3……SRn-2、SRn-1和SRn；其中n为自然数。其中，n的取值取决于实际的设计需要。该移位寄存器单元采用如图1或图4至图8示例的移位寄存器单元，每一移位寄存器单元包括输入信号端IP、输出信号端OT、降噪信号端VEL、第一时钟信号端CK和第二时钟信号端CB。其中，各端点接入如图3所示的时序图所标记的信号：移位寄存器单元SR1的输入信号端IP与帧触发信号端stv耦接，其余的每一级移位寄存器单元中，上一级移位寄存器单元的输出信号端OT与下一级移位寄存器单元的输入信号端IP耦接，即，移位寄存器单元SR1输出信号端输出的信号可以作为移位寄存器单元SR2的输入信号端的信号，移位寄存器单元SR2的输出信号端输出的信号可以作为移位寄存器单元SR3的输入信号端的信号……移位寄存器单元SRn-1的输出信号端的信号可以作为移位寄存器单元SRn的输入信号端的信号，直到无下一级移位寄存器单元为止。降噪信号端VEL接入降噪信号vell，第一时钟信号端CK接入第一时钟信号ckl，第二时钟信号端CB接入第二时钟信号cbl。图9所示栅极驱动装置的时序可以根据各移位寄存器单元的连接关系及图3所示的时序进行推理得到，在此不再赘述。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括多个像素单元，多条信号线以及本公开实施例提供的上述驱动控制电路。其中，上述驱动控制电路中的一个移位寄存器单元的输出信号端与该多条信号线中的 至少一条信号线耦接。该显示装置解决问题的原理与前述驱动控制电路相似，因此该显示装置的实施可以参见前述驱动控制电路的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
在具体实施时，显示装置可以包括多个像素单元，多条栅线和数据线，每个像素单元可以包括多个子像素，例如红色子像素、绿色子像素以及蓝色子像素。本公开实施例提供的上述显示装置可以为有机发光显示装置，或者也可以为液晶显示装置，在此不作限定。
在本公开实施例中，多条栅线也对应设置有驱动控制电路；一条栅线与驱动控制电路中的一个移位寄存器单元的输出信号端耦接。例如，在本公开实施例提供的上述显示装置为液晶显示装置时，子像素中的TFT可以与栅线耦接，并且使上述驱动控制电路可以作为栅极驱动电路，且该栅极驱动电路与栅线耦接，应用于给子像素中的TFT提供栅极扫描信号。需要说明的是，子像素中的TFT可以为N型晶体管或P型晶体管，在此不作限定。
在本公开一些实施例中，在本公开实施例提供的上述显示装置为有机发光显示装置时，显示装置还包括多条发光控制信号线；多条发光控制信号线对应设置有驱动控制电路；一条发光控制信号线与驱动控制电路中的一个移位寄存器单元的输出信号端耦接。以及，多条栅线也对应设置有驱动控制电路；一条栅线与驱动控制电路中的一个移位寄存器单元的输出信号端耦接。例如，在有机发光显示装置中，一般设置有多个有机发光二极管以及与各有机发光二极管连接的像素电路。一般像素电路中设置有用于控制有机发光二极管发光的发光控制晶体管和用于控制数据信号输入的扫描控制晶体管。
在具体实施时，发光控制晶体管可以与发光控制信号线耦接，扫描控制晶体管可以与栅线耦接，该有机发光显示装置可以包括一个本公开实施例提 供的上述驱动控制电路，该驱动控制电路可以作为发光驱动电路，且该发光驱动电路与发光控制晶体管耦接，应用于提供发光控制晶体管的发光控制信号。或者，该驱动控制电路也可以作为栅极驱动电路，且该栅极驱动电路与栅线耦接，应用于提供扫描控制晶体管的栅极扫描信号。
当然，该有机发光显示装置也可以包括两个本公开实施例提供的上述驱动控制电路，其中一个驱动控制电路可以作为发光驱动电路，与发光控制晶体管耦接，应用于提供发光控制晶体管的发光控制信号；则另一个驱动控制电路作为栅极驱动电路，与栅线耦接，应用于提供扫描控制晶体管的栅极扫描信号，在此不作限定。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (22)

  1. 一种移位寄存器单元，其中，包括：
    输入电路，被配置为响应于第一时钟信号端的信号，将输入信号端的信号提供给第一节点；
    控制电路，被配置为控制第二节点的信号；
    第一输出电路，被配置为响应于所述第一节点的信号，将第一参考电压信号端的信号提供给输出信号端；
    第二输出电路，被配置为响应于所述第二节点的信号，将第二参考电压信号端的信号提供给所述输出信号端；
    降噪电路，被配置为响应于降噪信号端的信号，将第三参考电压信号端的信号提供给所述第二节点，控制所述第二输出电路停止输出信号。
  2. 如权利要求1所述的移位寄存器单元，其中，所述降噪电路包括：第一晶体管；
    所述第一晶体管的栅极与所述降噪信号端耦接，所述第一晶体管的第一极与所述第三参考电压信号端耦接，所述第一晶体管的第二极与所述第二节点耦接。
  3. 如权利要求1或2所述的移位寄存器单元，其中，所述第一节点包括：第一子节点以及第二子节点；
    所述移位寄存器单元还包括：导通电路；所述第一子节点通过所述导通电路与所述第二子节点耦接；所述导通电路被配置为响应于第四参考电压信号端的信号，将所述第一子节点与所述第二子节点导通；
    所述输入电路进一步被配置为响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第一子节点；
    所述第一输出电路进一步被配置为响应于所述第二子节点的信号，将所述第一参考电压信号端的信号提供给所述输出信号端。
  4. 如权利要求3所述的移位寄存器单元，其中，所述控制电路包括：第 一控制电路、第二控制电路以及第三控制电路；
    所述第一控制电路被配置为响应于所述第一时钟信号端的信号，将第五参考电压信号端提供给第三节点，以及响应于所述第一子节点的信号，将所述第一时钟信号端的信号提供给所述第三节点；
    所述第二控制电路被配置为控制所述第二子节点的信号以及第四节点的信号；
    所述第三控制电路被配置为响应于所述第四节点和第二时钟信号端的信号，将所述第二时钟信号端的信号提供给所述第二节点，以及响应于所述第一子节点的信号，将所述第二参考电压信号端的信号提供给所述第二节点。
  5. 如权利要求4所述的移位寄存器单元，其中，所述第一控制电路包括：第二晶体管以及第三晶体管；
    所述第二晶体管的栅极与所述第一时钟信号端耦接，所述第二晶体管的第一极与所述第五参考电压信号端耦接，所述第二晶体管的第二极与所述第三节点耦接；
    所述第三晶体管的栅极与所述第一子节点耦接，所述第三晶体管的第一极与所述第三节点耦接，所述第三晶体管的第二极与所述第一时钟信号端耦接。
  6. 如权利要求4或5所述的移位寄存器单元，其中，所述第二控制电路进一步被配置为响应于所述第四参考电压信号端的信号，将所述第三节点的信号提供给所述第四节点，以及响应于所述第三节点的信号，将所述第二参考电压信号端的信号提供给第五节点，以及响应于所述第二子节点的信号，将所述第二时钟信号端的信号提供给所述第五节点。
  7. 如权利要求6所述的移位寄存器单元，其中，所述第二控制电路包括：第四晶体管、第五晶体管、第六晶体管以及第一电容；
    所述第四晶体管的栅极与所述第四参考电压信号端耦接，所述第四晶体管的第一极与所述第三节点耦接，所述第四晶体管的第二极与所述第四节点耦接；
    所述第五晶体管的栅极与所述第三节点耦接，所述第五晶体管的第一极与所述第二参考电压信号端耦接，所述第五晶体管的第二极与所述第五节点耦接；
    所述第六晶体管的栅极与所述第二子节点耦接，所述第六晶体管的第一极与所述第五节点耦接，所述第六晶体管的第二极与所述第二时钟信号端耦接；
    所述第一电容的第一电极与所述第五节点耦接，所述第一电容的第二电极与所述第二子节点耦接。
  8. 如权利要求4或5所述的移位寄存器单元，其中，所述第二控制电路进一步被配置为响应于所述第四参考电压信号端，将所述第三节点的信号提供给所述第四节点，以及响应于所述第四节点的信号，将所述第二参考电压信号端的信号提供给第五节点，以及响应于所述第二子节点的信号，将所述第二时钟信号端的信号提供给所述第五节点。
  9. 如权利要求8所述的移位寄存器单元，其中，所述第二控制电路包括：第四晶体管、第五晶体管、第六晶体管以及第一电容；
    所述第四晶体管的栅极与所述第四参考电压信号端耦接，所述第四晶体管的第一极与所述第三节点耦接，所述第四晶体管的第二极与所述第四节点耦接；
    所述第五晶体管的栅极与所述第四节点耦接，所述第五晶体管的第一极与所述第二参考电压信号端耦接，所述第五晶体管的第二极与所述第五节点耦接；
    所述第六晶体管的栅极与所述第二子节点耦接，所述第六晶体管的第一极与所述第五节点耦接，所述第六晶体管的第二极与所述第二时钟信号端耦接；
    所述第一电容的第一电极与所述第五节点耦接，所述第一电容的第二电极与所述第二子节点耦接。
  10. 如权利要求4-9任一项所述的移位寄存器单元，其中，所述第三控制 电路包括：第七晶体管、第八晶体管、第九晶体管以及第二电容；
    所述第七晶体管的栅极与所述第四节点耦接，所述第七晶体管的第一极与所述第二时钟信号端耦接，所述第七晶体管的第二极与所述第八晶体管的第一极耦接；
    所述第八晶体管的栅极与所述第二时钟信号端耦接，所述第八晶体管的第二极与所述第二节点耦接；
    所述第九晶体管的栅极与所述第一子节点耦接，所述第九晶体管的第一极与所述第二节点耦接，所述第九晶体管的第二极与所述第二参考信号端耦接；
    所述第二电容的第一电极与所述第四节点耦接，所述第二电容的第二电极与所述第八晶体管的第一极耦接。
  11. 如权利要求3-10任一项所述的移位寄存器单元，其中，所述输入电路包括第十晶体管；
    所述第十晶体管的栅极与所述第一时钟信号端耦接，所述第十晶体管的第一极与所述输入信号端耦接，所述第十晶体管的第二极与所述第一子节点耦接。
  12. 如权利要求3-11任一项所述的移位寄存器单元，其中，所述第一输出电路包括：第十一晶体管；
    所述第十一晶体管的栅极与所述第二子节点耦接，所述第十一晶体管的第一极与所述输出信号端耦接，所述第十一晶体管的第二极与所述第一参考电压信号端耦接。
  13. 如权利要求1-12任一项所述的移位寄存器单元，其中，所述第二输出电路包括：第十二晶体管以及第三电容；
    所述第十二晶体管的栅极与所述第二节点耦接，所述第十二晶体管的第一极与所述第二参考电压信号端耦接，所述第十二晶体管的第二极与所述输出信号端耦接；
    所述第三电容的第一电极与所述第二节点耦接，所述第三电容的第二电 极与所述第二参考电压信号端耦接。
  14. 如权利要求3-13任一项所述的移位寄存器单元，其中，所述导通电路包括：第十三晶体管；
    所述第十三晶体管的栅极与所述第四参考电压信号端耦接，所述第十三晶体管的第一极与所述第一子节点耦接，所述第十三晶体管的第二极与所述第二子节点耦接。
  15. 如权利要求1-14任一项所述的移位寄存器单元，其中，所述第二参考电压信号端与所述第三参考电压信号端为同一信号端。
  16. 一种移位寄存器单元，其中，包括：
    输入电路，所述输入电路与输入信号端以及第一节点耦接，被配置为将所述输入信号端的信号提供给所述第一节点；
    控制电路，所述控制电路与第二节点耦接，被配置为控制所述第二节点；
    第一输出晶体管，所述第一输出晶体管的栅极与所述第二节点耦接，所述第一输出晶体管的第一极与第二参考电压信号端耦接，所述第一输出晶体管的第二极与输出信号端耦接，被配置为响应于所述第二节点的信号，将所述第二参考电压信号端的信号提供给所述输出信号端；
    降噪晶体管，所述降噪晶体管的栅极与降噪信号端耦接，所述降噪晶体管的第一极与第三参考电压信号端耦接，所述降噪晶体管的第二极与所述第二节点耦接，被配置为响应于所述降噪信号端的信号，将所述第三参考电压信号端的信号提供给所述第二节点。
  17. 如权利要求16所述的移位寄存器单元，其中，还包括第三电容，所述第三电容的第一电极与所述第二参考电压信号端耦接，所述第三电容的第二电极与所述降噪晶体管的第二极耦接。
  18. 如权利要求17所述的移位寄存器单元，其中，还包括第二输出晶体管，所述第二输出晶体管的栅极与所述第一节点耦接，所述输出晶体管的第一极与所述第一参考电压信号端耦接，所述输出晶体管的第二极与所述输出信号端耦接，被配置为响应于所述第一节点的信号，将所述第一参考电压信 号端的信号提供给所述输出信号端。
  19. 如权利要求16所述的移位寄存器单元，其中，所述第二参考电压信号端与所述第三参考电压信号端为同一信号端。
  20. 一种驱动控制电路，其中，包括级联的多个如权利要求1-19任一项所述的移位寄存器单元；
    第一级移位寄存器单元的所述输入信号端与帧触发信号端耦接；
    每相邻的两极移位寄存器单元中，下一级移位寄存器单元的所述输入信号端与上一级移位寄存器单元的所述输出信号端耦接。
  21. 一种显示装置，其中，包括如权利要求20所述的驱动控制电路。
  22. 一种如权利要求1-19任一项所述的移位寄存器单元的驱动方法，其中，包括：
    降噪阶段，所述第一输出电路响应于所述第一节点的信号，将所述第一参考电压信号端的信号提供给所述输出信号端，所述降噪电路响应于所述降噪信号端的信号，将所述第三参考电压信号端的信号提供给所述第二节点，控制所述第二输出电路停止输出信号。
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