WO2024109053A1 - 三维堆叠结构和电子设备 - Google Patents

三维堆叠结构和电子设备 Download PDF

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Publication number
WO2024109053A1
WO2024109053A1 PCT/CN2023/104032 CN2023104032W WO2024109053A1 WO 2024109053 A1 WO2024109053 A1 WO 2024109053A1 CN 2023104032 W CN2023104032 W CN 2023104032W WO 2024109053 A1 WO2024109053 A1 WO 2024109053A1
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chip
conductive
silicon via
silicon
present application
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PCT/CN2023/104032
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English (en)
French (fr)
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梁芮
杨春城
刘曙光
景蔚亮
张师伟
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华为技术有限公司
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Publication of WO2024109053A1 publication Critical patent/WO2024109053A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular to a three-dimensional stacked structure and an electronic device.
  • a three-dimensional (3D) stacking structure is usually adopted, and through-silicon vias (TSVs) are set on the chip. Multiple stacked chips are connected through the through-silicon vias to achieve signal exchange.
  • the through-silicon vias are arranged in an array, and the orthographic projections of each through-silicon via coincide with each other along the chip stacking direction.
  • both the business signal such as a data signal or a control signal
  • the power signal are sent through the back of the bottom chip and transmitted to the upper chip through the through-silicon via.
  • the three-dimensional stacking structure provided in the embodiment of the present application can improve the signal transmission performance.
  • the present application adopts the following technical solutions:
  • an embodiment of the present application provides a three-dimensional stacked structure, which includes: a plurality of stacked chips, a first chip and a second chip among the plurality of chips being provided with at least one through-silicon via; a first dielectric layer being provided between the first chip and the second chip, a first conductive structure being provided in the first dielectric layer; a first through-silicon via in at least one through-silicon via of the first chip being connected to a signal port on the second chip through the first conductive structure; wherein the first through-silicon via is disconnected from a second through-silicon via in at least one through-silicon via of the second chip, and an orthographic projection of the second through-silicon via onto the first through-silicon via at least partially overlaps with the first through-silicon via.
  • the first through silicon via and the second through silicon via are disconnected, for example, the first through silicon via and the second through silicon via are not electrically connected through a conductive object.
  • the three-dimensional stacked structure provided in the embodiment of the present application is configured to provide a conductive structure in the dielectric layer between the first chip (e.g., a chip that sends signals or directly connects to external signals) and the second chip (e.g., a chip that receives signals), so that the first through silicon via on the first chip and the second through silicon via on the second chip are disconnected from each other (the orthographic projection of the second through silicon via onto the first through silicon via at least partially overlaps with the first through silicon via).
  • the signal sent by the first chip or the signal input from the outside can be directly transmitted to the signal port of the second chip through the first through silicon via and the conductive structure, and the second chip does not need to be disconnected from the third chip stacked on the second chip.
  • the second chip can also transmit other signals to the third chip through the second through silicon via, and the other signals can be, for example, power signals or other transmitted signals.
  • the embodiment of the present application can be provided with the above-mentioned conductive structure, so that there is no need to set up an additional wiring layer for transmitting power signals on the second chip and a conductive line in the chip, thereby simplifying the process complexity; in addition, by providing the above-mentioned conductive structure, when it is necessary to transmit a power signal to the second chip, there is no need to pass through the second silicon through via, thereby avoiding additional voltage drop loss. Therefore, the 3D stacking structure provided in the embodiment of the present application can improve signal transmission performance.
  • the second chip includes a first surface away from the first chip and a second surface close to the first chip, wherein the second surface of the second chip is provided with a first conductive circuit; a third through silicon via in at least one through silicon via of the second chip is horizontally spaced apart from the second through silicon via, and the second through silicon via is connected to the third through silicon via through the first conductive circuit.
  • a fourth through silicon via in at least one through silicon via of the first chip has an orthographic projection onto the third through silicon via, which at least partially overlaps with the third through silicon via; a second conductive structure is further provided in the first dielectric layer, and the third through silicon via is connected to the fourth through silicon via through the second conductive structure.
  • a second conductive circuit is further disposed on the second surface of the second chip, and the first conductive structure is connected to the signal port via the second conductive circuit; wherein the first conductive circuit and the second conductive circuit are isolated from each other.
  • the first chip includes a first surface close to the second chip and a second surface away from the second chip, and the first surface of the first chip is provided with a third conductive circuit and a fourth conductive circuit; the third conductive circuit is used to connect the first silicon via with the first conductive structure; the fourth conductive circuit is used to connect the fourth silicon via with the second conductive structure; wherein the third conductive circuit and the fourth conductive circuit are isolated from each other.
  • the multiple chips also include a third chip, a second dielectric layer is arranged between the third chip and the first chip, and a third conductive structure is arranged in the second dielectric layer; a fifth through silicon via is also arranged in the third chip, and the fifth through silicon via is connected to the first through silicon via through the third conductive structure, wherein an orthographic projection of the first through silicon via onto the fifth through silicon via at least partially overlaps with the fifth through silicon via.
  • the first conductive structure includes a first conductive via and a second conductive via; the first conductive via is used to connect the second conductive via and the signal port; the second conductive via is used to connect the first conductive via and the first through silicon via.
  • the first conductive structure further includes two first pads and a second pad that overlap each other; and the first conductive via is connected to the second conductive via through the first pad and the second pad.
  • the first conductive circuit and the second conductive circuit are metal layers or redistribution layers.
  • an embodiment of the present application provides an electronic device, which includes the three-dimensional stacked structure as described in the first aspect, and the electronic device also includes a printed circuit board, and the three-dimensional structure is arranged on the printed circuit board through the surface of the first chip away from the second chip.
  • FIG1 is a schematic diagram of a 3D stacking structure in the prior art provided by an embodiment of the present application.
  • FIG2 is a schematic diagram of a 3D stacking structure provided in an embodiment of the present application.
  • FIG3 is another schematic diagram of a 3D stacking structure provided in an embodiment of the present application.
  • FIG4A is a schematic diagram of a conductive structure in a 3D stacked structure provided in an embodiment of the present application.
  • FIG4B is a partial enlarged schematic diagram of the conductive structure shown in FIG4A provided in an embodiment of the present application;
  • FIG5A is another schematic diagram of a conductive structure in a 3D stacked structure provided in an embodiment of the present application.
  • FIG5B is a partial enlarged schematic diagram of the conductive structure shown in FIG5A provided in an embodiment of the present application;
  • FIG. 6 is another schematic diagram of a 3D stacking structure provided in an embodiment of the present application.
  • a and/or B in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist.
  • a and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone.
  • first and second and the like in the description and drawings of the embodiments of the present application are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects.
  • FIG 1 is a schematic diagram of a 3D stacking structure provided in the prior art.
  • chip 1, chip 2 and chip 3 are shown, wherein chip 2 and chip 3 are stacked on chip 1 in sequence.
  • Chip 1 and chip 2 each include three through silicon vias.
  • the through silicon vias included in chips 1 to 2 are arranged in an array in the 3D stacking structure.
  • the figure only lists the number of TSVs in the X direction as 3, and the number in the Y direction is not listed.
  • the through silicon via on chip 2 the orthographic projection to chip 1, coincides with the through silicon via on chip 1.
  • the different chips are connected through silicon vias and pads.
  • business signals such as data signals or control signals
  • power signals are both sent through the back of the bottom chip and transmitted to the upper chip through silicon vias.
  • chip 1 in Figure 1 needs to provide a specific business signal to chip 2, that is, the business signal is transmitted one-to-one, and the other chips do not receive the business signal.
  • chip 1 is connected to the redistribution layer on the lower surface of chip 2 through the through silicon via a2 and the pad in chip 1, and the redistribution layer on the lower surface of chip 2 transmits the received signal to the corresponding pin on chip 2.
  • the through silicon via b2 at the position corresponding to the through silicon via a2 on chip 2 is disconnected from the chip 3, that is, the through silicon via b2 no longer transmits the service signal, thereby resulting in a waste of the through silicon via.
  • the through silicon via b2 that no longer transmits the service signal may be used to transmit the power signal. In this case, it is usually necessary to set a conductive circuit on the lower surface of chip 2, between the through silicon via b2 and the redistribution layer on the lower surface of chip 2.
  • the conductive circuit is used to isolate the through silicon via b2 from the redistribution layer on the lower surface, and the conductive circuit connects the power port on chip 2 with the through silicon via b2.
  • the conductive circuit can be the back-end wiring layer of chip 2, and its structure includes one or more layers of metal wires or metal connection holes.
  • the power signal is transmitted on the back of chip 1, and is transmitted to the power supply port on chip 2 (as shown by the black line in the figure) through the silicon via a1, pad, silicon via b1, wiring layer arranged on the upper surface of chip 2, silicon via b2, and conductive line on the lower surface of chip 2 on chip 1.
  • the transmission of power signal through the wiring layer on the upper surface of chip 2 and silicon via b2 will cause excessive resistance due to the excessively long lead, resulting in additional voltage drop loss.
  • the three-dimensional stacked structure provided in the embodiment of the present application is configured to provide a conductive structure in the dielectric layer between the first chip (i.e., the chip that sends signals or directly connects to external signals) and the second chip (i.e., the chip that receives signals), thereby disconnecting the first through silicon via on the first chip and the second through silicon via on the second chip (the orthographic projection of the second through silicon via onto the first through silicon via at least partially overlaps with the first through silicon via).
  • the signal sent by the first chip or the signal input from the outside can be directly transmitted to the signal port of the second chip through the first through silicon via and the conductive structure, and the second chip does not need to be disconnected from the third chip stacked on the second chip.
  • the second chip can also transmit other signals to the third chip through the second through silicon via, and the other signals can be, for example, power signals or other transmitted signals.
  • the embodiment of the present application can be provided with the above-mentioned conductive structure, so that there is no need to set up an additional wiring layer for transmitting power signals on the second chip and a conductive line in the chip, thereby simplifying the process complexity; in addition, by providing the above-mentioned conductive structure, when it is necessary to transmit a power signal to the second chip, there is no need to pass through the second silicon through via, thereby avoiding additional voltage drop loss. Therefore, the 3D stacking structure provided by the embodiment of the present application can improve signal transmission performance.
  • the 3D stacking structure provided in the embodiment of the present application can be a wafer-wafer (WoW, Wafer on Wafer) stacking structure, a chip-wafer (CoW, chip on wafer) stacking structure, and a chip-chip (CoC, Chip on Chip) stacking structure.
  • multiple chips with different functions can be arranged, such as but not limited to logic chips, memory chips, communication chips or sensor chips.
  • multiple chips can be stacked in sequence, and silicon through holes are connected between the chips along the stacking direction. Connected to achieve signal exchange. It should be noted that the 3D stacking structure can stack more or fewer chips.
  • the embodiment of the present application does not specifically limit the number of chips stacked in the 3D stacking structure, and is set according to the needs of the scene.
  • the chip described in the embodiment of the present application can be a bare chip (Die), or a bare chip and other chips or components (active devices or passive devices, etc.) formed by simple packaging, or a chip packaging structure formed after packaging, which is not limited here.
  • the chips included in the 3D stacking structure shown in the embodiment of the present application may include but are not limited to: System on chip (System on chip), memory (Memory), discrete devices, application processing chips (Application Processor, AP), micro-electro-mechanical systems (Micro-Electro-Mechanical System, MEMS), microwave radio frequency chips, application-specific integrated circuits (Application Specific Integrated Circuit, referred to as ASIC) and other chips.
  • the above-mentioned application processing chip or application-specific integrated circuit can be a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), an artificial intelligence processor, for example, a neural network processor (Network Processing Unit, NPU), etc.
  • the memory may be a cache, a random access memory (RAM), a read only memory (ROM) or other memory.
  • Discrete devices may include, but are not limited to, field effect transistors, bipolar transistors, etc.
  • the chip-chip stacking structure is taken as an example, and the 3D stacking structure provided in the embodiment of the present application is described in detail through the embodiments shown in Figures 2 to 6.
  • FIG 2 is a structural schematic diagram of the 3D stacking structure provided in an embodiment of the present application.
  • three chips, chip 1, chip 2 and chip 3, are shown.
  • Chip 2 is stacked on chip 1
  • chip 3 is stacked on chip 2.
  • the 3D stacking structure can stack more or fewer chips.
  • the embodiment of the present application does not specifically limit the number of chips stacked in the 3D stacking structure, and is set according to the needs of the scene.
  • a dielectric layer is arranged between every two stacked chips, and the medium in the dielectric layer is, for example, silicon oxide, silicon nitride, and silicon carbonitride, which is used to isolate the chips from each other and provide support and protection for the chips.
  • a dielectric layer S1 is arranged between chip 1 and chip 2, and a dielectric layer S2 is arranged between chip 2 and chip 3.
  • chip 1 includes through silicon via a1, through silicon via a2, and through silicon via a3, and each through silicon via passes through the upper surface and the lower surface of chip 1;
  • chip 2 includes through silicon via b1, through silicon via b2, and through silicon via b3, and each through silicon via passes through the upper surface and the lower surface of chip 2.
  • the TSVs on chip 1 and chip 2 are arranged in an array, that is, the orthographic projection of TSV b1 onto TSV a1 at least partially overlaps with TSV a1, the orthographic projection of TSV b2 onto TSV a2 at least partially overlaps with TSV a2; the orthographic projection of TSV b3 onto TSV a3 at least partially overlaps with TSV a3, and FIG2 schematically shows that the orthographic projection of TSV b1 onto TSV a1 overlaps with TSV a1, the orthographic projection of TSV b2 onto TSV a2 overlaps with TSV a2, and the orthographic projection of TSV b3 onto TSV a3 overlaps with TSV a3.
  • a conductive structure 21 is provided in each of the above-mentioned dielectric layers, and the conductive structure 21 is used to connect the conductive lines on two adjacent chips.
  • the conductive structure 21 can be provided on the side of the through silicon via, that is, the conductive structure is located outside the projection range of the through silicon via.
  • chip 1 needs to transmit a signal (such as a signal generated by itself or a signal input from the outside) to a circuit structure or component on chip 2, and the remaining circuits or components on chip 2 and chip 3 do not receive the signal, that is, the signal is a one-to-one transmission between a component on chip 1 and a component on chip 2.
  • chip 1 needs to transmit the signal to chip 2 through silicon via a2.
  • the conductive structure 21 is embedded in the dielectric layer S1 and is located on the side of the through silicon via a2 and the through silicon via b2.
  • FIG2 shows that the conductive structure 21 is located between the through silicon via a2 and the through silicon via a3.
  • a conductive line r1 is provided on the upper surface of chip 1, and the conductive structure 21 is connected to the conductive material in the through silicon via a2 through the conductive line r1.
  • a conductive circuit r2 is provided on the lower surface of the chip 2, and the conductive structure 21 is connected to the signal port on the chip 2 through the conductive circuit r2 to transmit signals to the components or circuits on the chip 2.
  • the conductive circuit r2 is not connected to any through silicon via on the chip 2.
  • no conductive structure is provided between the through silicon via a2 and the through silicon via b2, or it can be said that the through silicon via a2 and the through silicon via b2 are not electrically connected through a conductive object, or the interconnection between the through silicon via a2 and the through silicon via b2 is disconnected.
  • the signal emitted by the chip 1 is directly transmitted to the component in the chip 2 for receiving the signal through the through silicon via a2, the conductive structure 21 and the conductive circuit on the chip 2.
  • the signal port may also be referred to as a signal lead-out terminal, which is connected to a conductive module inside the chip (e.g., a source or drain of a field effect transistor) or a module of an integrated circuit.
  • the signal port may include, for example, but is not limited to, a pad, a solder ball, or a metal trace, etc.
  • the signal port may also be a module inside the chip, such as a source or drain of a field effect transistor.
  • a signal port wiring layer and a conductive through hole for connecting the signal port wiring layer and the conductive circuit r2 are also provided on the side of the surface of the signal port close to the conductive circuit r2 (the signal port wiring layer and the conductive through hole are not shown in the figure), so that the signal port is connected to the conductive circuit r2 through the signal port wiring layer and the conductive through hole.
  • the orthographic projection of the signal port on the second chip partially overlaps with the first through silicon via. In the present embodiment, the orthographic projection of the signal port on the second chip does not overlap with the first through silicon via at all.
  • the embodiment of the present application disconnects the TSV a2 on chip 1 from the TSV b2 on chip 2 and sets a conductive structure 21 next to the TSV, so that the TSV b2 on chip 2 can be connected to other TSVs (such as the TSV a1 on chip 1 ) to transmit other signals and avoid waste of TSVs.
  • the prior art shown in FIG. 1 in which the TSV a2 on chip 1 is directly interconnected with the TSV b2 on chip 2 and the TSV b2 on chip 2 is disconnected from the TSV on chip 3 , the embodiment of the present application disconnects the TSV a2 on chip 1 from the TSV b2 on chip 2 and sets a conductive structure 21 next to the TSV, so that the TSV b2 on chip 2 can be connected to other TSVs (such as the TSV a1 on chip 1 ) to transmit other signals and avoid waste of TSVs.
  • the power signal when it is necessary to transmit a power signal to chip 2, the power signal can also be directly transmitted to chip 2 through the through silicon via a1.
  • the through silicon via b1 and the through silicon via b2 it can avoid excessive resistance caused by too long leads and reduce voltage drop losses. Therefore, the 3D stacked structure provided in the embodiment of the present application can improve signal transmission performance.
  • a conductive line r3 is provided on the lower surface of chip 2 (i.e., the side of chip 2 close to chip 1), and the conductive line r3 is connected to the through silicon via b2. It should be noted that the conductive line r3 is not connected to the conductive line r2 provided on the lower surface of chip 2, so that the through silicon via b2 is disconnected from the through silicon via b1. In addition, the conductive line r3 is also connected to the through silicon via a1 on chip 1. In this way, chip 2 is connected to chip 1 through the conductive line r3 and the through silicon via a1.
  • the power signal transmitted from the lower surface of chip 1 is transmitted to the power port on chip 2 through the through silicon via a1 and the conductive line r3.
  • chip 3 is connected to chip 1 through the through silicon via b2, the conductive line r3 and the through silicon via a1.
  • the signal transmitted through the through silicon via a1 can be transmitted to chip 3 through the conductive line r3 and the through silicon via b2, thereby improving the utilization rate of the through silicon via b2.
  • the conductive circuit r1, conductive circuit r2 and conductive circuit r3 described in the embodiment of the present application may be a metal layer on which a patterned conductive circuit is arranged; in addition, in other possible implementations, the conductive circuit r1, conductive circuit r2 and conductive circuit r3 described in the embodiment of the present application may also be a redistribution layer, and the embodiment of the present application does not make any specific limitation on this.
  • a conductive structure 22 is also provided in the dielectric layer S1 and the dielectric layer S2.
  • the conductive structure 22 is provided between two through silicon vias in the same column, and between the through silicon via and the chip, so as to achieve the connection between two adjacent through silicon vias in the same column, and the connection between the through silicon via and the chip, thereby achieving the connection between the chips.
  • the orthographic projection of the through silicon via to the conductive structure 22 at least partially covers the conductive structure 22.
  • a conductive structure 22 is provided between the through silicon via a1 and the through silicon via b1.
  • the orthographic projection of the through silicon via a1 or the through silicon via b1 to the conductive structure 22 covers the conductive structure 22.
  • Conductive structures 22 are provided between the through silicon via b1, the through silicon via b2, and the through silicon via b3 and the chip 3, respectively, to connect the through silicon vias on the chip 2 and the conductive circuits on the chip 3.
  • conductive circuits can be provided on the upper surface of chip 1, the upper surface of chip 2 and the lower surface of chip 3 along the chip stacking direction to achieve the connection between the silicon through vias on each layer of chips and the chips, and the connection between each chip.
  • the upper surface of chip 1 is also provided with a conductive circuit r4
  • the upper surface of chip 2 is also provided with a conductive circuit r5
  • the lower surface of chip 3 is also provided with a conductive circuit r6.
  • the conductive circuit r1 on the upper surface of chip 1 is not connected to the conductive circuit r4, so that the silicon through via a1 and the silicon through via a2 are isolated from each other.
  • the conductive circuit r4 is connected to the silicon through via a1, and the conductive structure 22 between the silicon through via a1 and the silicon through via b1;
  • the conductive circuit r5 is used to connect the silicon through vias on chip 2, and the conductive structure 22 between chip 2 and chip 3.
  • the above conductive circuits can be patterned conductive circuits formed by a metal layer or a rewiring layer.
  • the number of conductive circuits and the connection relationship between the conductive circuits shown in FIG. 3 are schematic, which are set based on the one-to-one signal transmission path and the power signal transmission path, and the embodiments of the present application do not make specific limitations.
  • the conductive structure 21 and the conductive structure 22 shown in Figures 2 and 3 can be implemented in a variety of ways.
  • the conductive structure 21 can be formed by a bonding pad and a through hole connecting the bonding pad and the chip, as shown in Figure 4A.
  • Figure 4B is a partial enlarged schematic diagram of the conductive structure 21 shown in Figure 4A.
  • the conductive structure 21 includes a bonding pad 211, a bonding pad 212, a conductive through hole 213 for connecting the bonding pad 211 and the silicon through via, and a conductive through hole 214 for connecting the bonding pad 212 to a component on the chip 3.
  • the bonding pad 211 and the bonding pad 212 are completely overlapped, or ...
  • the pads 211 and 212 are partially staggered and overlapped to form a conductive path.
  • the conductive through hole 213 is used to connect the pad 211 with the conductive line r1 on the upper surface of the chip 1, and the conductive through hole 214 is used to connect the pad 212 with the conductive line r2 on the lower surface of the chip 2.
  • only one pad 211 may be set on the conductive structure 21, and no pad 212 is set, and the conductive through hole 213 and the conductive through hole 214 are both connected to the pad 211.
  • only one conductive through hole 214 may be set on the conductive structure 21, and no conductive through hole 213 is set, and the pad 212 is connected to this through hole 214, and the pads 212 and the pads 214 are completely overlapped, or partially staggered and overlapped.
  • only one conductive through hole 213 may be provided on the conductive structure 21, and no conductive through hole 214 may be provided.
  • the pad 211 is connected to the through hole 214, and the pad 212 and the pad 214 are completely overlapped, or partially overlapped.
  • the remaining conductive structures 21 and 22 shown in FIG4A are the same or similar to the conductive structure 21 connecting the silicon through via a2 and the signal port on the chip 2 shown in FIG4B, and will not be described in detail.
  • the other structures in FIG4A and the connection relationship between the structures are the same as those in FIG2, and specific reference is made to the description of the relevant structures in FIG2, and will not be described in detail.
  • the conductive structure 21 may be formed only by conductive through holes, as shown in FIG5A. Taking the conductive structure 21 used to connect the silicon through via a2 on the chip 1 and the signal port on the chip 2 as an example, a more detailed description is given in combination with FIG5B. Among them, FIG5B is a partially enlarged schematic diagram of the conductive structure 21 shown in FIG5A. As shown in FIG5B, the conductive structure 21 includes a conductive through hole 213 and a conductive through hole 214. Among them, the conductive through hole 213 and the conductive through hole 214 are overlapped to form a conductive path.
  • the conductive through hole 213 is used to connect the conductive through hole 214 with the conductive line r1, and the conductive through hole 214 is used to connect the conductive through hole 213 with the conductive line r2.
  • only one conductive through hole 213 may be set on the conductive structure 21, and the conductive line r1 and the conductive line r2 are connected through the conductive through hole 213.
  • the remaining conductive structures 21 and 22 shown in FIG5A are the same or similar to the conductive structure 21 for connecting the through silicon via a2 and the signal port on the chip 2 shown in FIG4B , and will not be described in detail.
  • the other structures in FIG5A and the connection relationship between the structures are the same as those in FIG2 , and specific reference is made to the description of the relevant structures in FIG2 , and will not be described in detail.
  • the area covered by the projection of any one of the through silicon vias may not be provided with any structure, such as the area between through silicon via a2 and through silicon via b2 on the dielectric layer in FIG. 2 .
  • the area covered by the projection of any one of the silicon vias may be provided with only a pad but no conductive via, thereby disconnecting the connection between the two silicon vias by disconnecting the connection between the conductive via and the silicon via, such as the area between silicon via a2 and silicon via b2 on the dielectric layer in Figure 4A.
  • Figure 6 is another structural schematic diagram of the 3D stacking structure provided by the embodiment of the present application. Different from the 3D stacking structure shown in Figure 2, the 3D stacking structure shown in Figure 6 is stacked with four chips, chip 1 to chip 4. Except for the topmost chip, four silicon through holes are provided on each of the remaining chips. The silicon through holes on each chip are arranged in an array, and each two chips are separated by a dielectric layer.
  • conductive structures 21 are provided in the dielectric layer S1, the dielectric layer S2 and the dielectric layer S3, and each conductive structure 21 is respectively provided on the side of the silicon through hole to realize the signal from the bottom of the 3D stacking structure (that is, the side close to the bottom surface of chip 1) to each layer of chip one-to-one transmission.
  • the conductive structure 21 located in the dielectric layer S1 is provided on the side of the second column of silicon through holes;
  • the conductive structure 21 located in the dielectric layer S2 is provided on the side of the third column of silicon through holes;
  • the conductive structure 21 located in the dielectric layer S3 is provided on the side of the fourth column of silicon through holes.
  • the interconnection between TSV a2 and TSV b2 is disconnected, the interconnection between TSV b3 and TSV c3 is disconnected, and the interconnection between TSV c4 and TSV d4 is disconnected.
  • the signal transmitted from the back of chip 1 that is designated to reach chip 2 is transmitted to the signal port on chip 2 through TSV a2 and the conductive structure 21 on the side of TSV a2;
  • the signal transmitted from the back of chip 1 that is designated to reach chip 3 is transmitted to the signal port on chip 3 through TSV a3, TSV b3 and the conductive structure 21 on the side of TSV b3;
  • the signal transmitted from the back of chip 1 that is designated to reach chip 4 is transmitted to the signal port on chip 4 through TSV a4, TSV b4 and TSV c4 and the conductive structure 21 on the side of TSV c4.
  • conductive structures 22 are provided in dielectric layer S1, dielectric layer S2 and dielectric layer S3. As shown in FIG6 , except that conductive structures 22 are not provided between the above-mentioned disconnected through silicon vias, conductive structures 22 are provided between the remaining through silicon vias and between the through silicon vias and chips to achieve interconnection between the through silicon vias and between the chips.
  • conductive structures 22 are provided between through silicon via a1 and through silicon via b1, between through silicon via b1 and through silicon via c1, between through silicon via c1 and chip 4, between through silicon via b2 and through silicon via c2, between through silicon via c2 and chip 4, between through silicon via a3 and through silicon via b3, between through silicon via c3 and chip 4, between through silicon via a4 and through silicon via b4, and between through silicon via b4 and through silicon via c4.
  • the upper surface of chip 1, the upper surface and lower surface of chip 2, the upper surface and lower surface of chip 3, and the lower surface of chip 4 are all provided with conductive circuits, and the conductive circuits on each chip are connected to the silicon through vias on the same chip.
  • the conductive circuits can be, for example, metallized conductive circuits or redistribution layers. It can be understood that the number of conductive circuits shown in FIG.
  • the connection relationship between each conductive circuit is schematic, which is set based on the path of one-to-one signal transmission and the transmission path of the power signal, and the embodiment of the present application does not make specific limitations.
  • the power signal when the back side of the chip 1 transmits a power signal, the power signal can be transmitted through silicon via a1, silicon via b1, silicon via c1, silicon via b2, silicon via c2, silicon via c3 and conductive structure 22, which can avoid the waste of silicon vias compared with the prior art shown in FIG1. It can be understood that the above power signal can also be replaced by other signals.
  • the embodiment of the present application also provides an electronic device, which may include, for example, but not limited to a chip or a chipset or a circuit board equipped with a chip or a chipset.
  • the electronic device may be a terminal device, for example, but not limited to a portable computer (such as a mobile phone), a laptop, a wearable electronic device (such as a smart watch), a tablet computer, an augmented reality (AR) or virtual reality (VR) device, or an electric toothbrush.
  • the electronic device may also be a server device, for example.
  • the electronic device shown in the present application includes a 3D stacking structure as shown in any embodiment of Figures 2 to 6.
  • a printed circuit board may be provided on the electronic device, so that the chip stacking structure shown in Figures 2, 3 or 6 is provided on the printed circuit board through the back of the chip 1. That is to say, the back of the chip 1 is provided on the printed circuit board through solder balls, pads or glue.
  • a power supply, a common ground, etc. are also provided on the printed circuit board, and the power supply or common ground, etc., supply power to the stacked upper chip through the silicon through-hole a1 in the chip 1.

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Abstract

本申请实施例公开了一种三维堆叠结构和电子设备，该三维堆叠结构包括：堆叠设置的多个芯片，多个芯片中的第一芯片和第二芯片均设置有至少一个硅通孔；第一介质层，设置于第一芯片与第二芯片之间，，第一介质层中设置有第一导电结构；第一芯片的至少一个硅通孔中的第一硅通孔，通过第一导电结构，与第二芯片上的信号端口连接；其中，第一硅通孔与第二芯片的至少一个硅通孔中的第二硅通孔之间断开连接，第二硅通孔向第一硅通孔的正投影，与第一硅通孔至少部分重合，该三维堆叠结构可以提高信号传输性能。

Description

三维堆叠结构和电子设备
本申请要求在2022年11月23日提交中国专利局、申请号为202211470579.9、发明名称为“三维堆叠结构和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种三维堆叠结构和电子设备。
背景技术
随着通信、人工智能等技术的发展，大量的数据流动与转移的需求越来越大，支持诸如5G应用、人工智能等应用的硬件需要具有高速计算、低延时、多带宽以及系统集成等功能。为了满足硬件设备的功能需求，业界提出采用异构芯片来提高硬件设备或系统的电学性能。
现有异构芯片技术中，通常采用三维(3D，three dimensional)堆叠结构，在芯片上设置硅通孔(TSV，Through-Silicon Via)，多个堆叠芯片之间通过硅通孔连通，以实现信号交流。通常，硅通孔呈阵列排布，沿芯片堆叠方向，各硅通孔的正投影重合。在该种结构中，业务信号(例如数据信号或者控制信号)与电源信号均通过底层芯片的背面发出，通过硅通孔向上层芯片传输。当采用一对一信号传输时，也即位于底层的芯片将信号传输至上层某一指定的芯片之后，该指定芯片上的硅通孔与其上层芯片之间的互联断开。从而，沿芯片堆叠方向，该指定芯片上的硅通孔以及其上层芯片的硅通孔将不再进行信号传输。或者其他场景中，业界采用该指定芯片上的硅通孔以及指定芯片上的横向重布线层，向上述指定芯片传输电源信号。然而，当上述硅通孔不再进行信号传输时，将导致硅通孔的浪费；此外，通过指定芯片上的硅通孔以及重布线层向指定芯片传输电源信号，会由于引线过长导致电阻过大，带来额外的压降损失。由此，如何对3D堆叠结构进行优化，以减少硅通孔的浪费、降低压降损失，成为需要解决的问题。
发明内容
本申请实施例提供的三维堆叠结构，可以提高信号传输性能。为达到上述目的，本申请采用如下技术方案：
第一方面，本申请实施例了一种三维堆叠结构，该三维堆叠结构包括：堆叠设置的多个芯片，所述多个芯片中的第一芯片和第二芯片均设置有至少一个硅通孔；第一介质层，设置于所述第一芯片与所述第二芯片之间，所述第一介质层中设置有第一导电结构；所述第一芯片的至少一个硅通孔中的第一硅通孔，通过所述第一导电结构，与所述第二芯片上的信号端口连接；其中，所述第一硅通孔与所述第二芯片的至少一个硅通孔中的第二硅通孔之间断开连接，所述第二硅通孔向所述第一硅通孔的正投影，与所述第一硅通孔至少部分重合。
本申请实施例中，第一硅通孔与第二硅通孔之间断开连接，例如为第一硅通孔与第二硅通孔之间未通过导电物体形成电连接。
本申请实施例提供的三维堆叠结构，通过在第一芯片(例如发送信号或直连外界信号的芯片)与第二芯片(例如接收信号的芯片)之间的介质层中设置导电结构，将第一芯片上的第一硅通孔、与第二芯片上的第二硅通孔之间互联断开(第二硅通孔向第一硅通孔的正投影，与第一硅通孔至少部分重合)。从而，第一芯片所发送的信号或外界输入的信号，可以通过第一硅通孔以及该导电结构直接传输至第二芯片的信号端口中，第二芯片与堆叠于第二芯片之上的第三芯片之间不需要断开，第二芯片还可以通过第二硅通孔与第三芯片之间进行其他信号的传输，该其他信号例如可以为电源信号，也可以为其他的传输的信号。这样一来，可以提高芯片上硅通孔的利用率；此外，当需要向第二芯片传输电源信号时，本申请实施例通过设置上述导电结构，可以不需要在第二芯片上额外设置用于传输电源信号的布线层和芯片中的导电线路，简化工艺复杂度；另外，本申请实施例通过设置上述导电结构，当需要向第二芯片传输电源信号时，可以不需要经过第二硅通孔，从而可以避免额外的压降损失。由 此，本申请实施例提供的3D堆叠结构，可以提高信号传输性能。
在一种可能的实现方式中，所述第二芯片包括远离所述第一芯片的第一表面和靠近所述第一芯片的第二表面，其中，所述第二芯片的第二表面设置有第一导电线路；所述第二芯片的至少一个硅通孔中的第三硅通孔，与所述第二硅通孔水平间隔设置，所述第二硅通孔与所述第三硅通孔通过所述第一导电线路连接。
在一种可能的实现方式中，所述第一芯片的至少一个硅通孔中的第四硅通孔，向所述第三硅通孔的正投影，与所述第三硅通孔至少部分重合；所述第一介质层中还设置有第二导电结构，所述第三硅通孔通过所述第二导电结构与所述第四硅通孔连接。
在一种可能的实现方式中，所述第二芯片的第二表面还设置有第二导电线路，所述第一导电结构通过所述第二导电线路与所述信号端口连接；其中，所述第一导电线路与所述第二导电线路之间相互隔离。
在一种可能的实现方式中，所述第一芯片包括靠近所述第二芯片的第一表面和远离所述第二芯片的第二表面，所述第一芯片的第一表面设置有第三导电线路和第四导电线路；所述第三导电线路用于连通所述第一硅通孔与所述第第一导电结构；所述第四导电线路用于连通所述第四硅通孔与所述第二导电结构；其中，所述第三导电线路与所述第四导电线路之间相互隔离。
在一种可能的实现方式中，所述多个芯片还包括第三芯片，所述第三芯片和所述第一芯片之间设置有第二介质层，所述第二介质层中设置有第三导电结构；所述第三芯片中还设置有第五硅通孔，所述第五硅通孔通过所述第三导电结构与所述第一硅通孔连接，其中，所述第一硅通孔向所述第五硅通孔的正投影，与所述第五硅通孔至少部分重合。
在一种可能的实现方式中，所述第一导电结构包括第一导电通孔和第二导电通孔；所述第一导电通孔用于连接所述第二导电通孔与所述信号端口；所述第二导电通孔用于连接所述第一导电通孔与所述第一硅通孔。
在一种可能的实现方式中，所述第一导电结构还包括两个相互交叠的第一焊盘和第二焊盘；第一导电通孔通过所述第一焊盘和所述第二焊盘与所述第二导电通孔连接。
在一种可能的实现方式中，所述第一导电线路和所述第二导电线路，为金属层或者重布线层。
第二方面，本申请实施例了一种电子设备，该电子设备包括如第一方面所述的三维堆叠结构，所述电子设备还包括印刷电路板，所述三维结构通过所述第一芯片远离所述第二芯片的表面，设置于所述印刷电路板上。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请实施例的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的现有技术中3D堆叠结构示意图；
图2为本申请实施例提供的3D堆叠结构的一个示意图；
图3为本申请实施例提供的3D堆叠结构的又一个示意图；
图4A为本申请实施例提供的3D堆叠结构中导电结构的一个示意图；
图4B为本申请实施例提供的如图4A所示的导电结构的局部放大示意图；
图5A为本申请实施例提供的3D堆叠结构中导电结构的又一个示意图；
图5B为本申请实施例提供的如图5A所示的导电结构的局部放大示意图；
图6为本申请实施例提供的一种3D堆叠结构的又一个示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请实施例一部分实施例，而不是全部的实施例。基于本申请实施例中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请实施例保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
本申请实施例的说明书以及附图中的术语“第一”和“第二”等是用于区别不同的对象，或者用于区别对同一对象的不同处理，而不是用于描述对象的特定顺序。
此外，本申请实施例的描述中所提到的术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选的还包括其他没有列出的步骤或单元，或可选的还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。
需要说明的是，本申请实施例的描述中，“示例性地”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性地”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优先或更具优势。确切而言，使用“示例性地”或者“例如”等词旨在以具体方式呈现相关概念。
请参考图1，图1是现有技术中提供的3D堆叠结构的一个示意图。在图1中，示出了芯片1、芯片2和芯片3，其中芯片2和芯片3依次堆叠于芯片1之上。芯片1和芯片2分别包括三个硅通孔，如图1所示，芯片1～芯片2所包括的硅通孔，在3D堆叠结构呈阵列排布，图中仅列出X方向TSV数量为3，Y方向数量未列出。从图1中可以看出，芯片2上的硅通孔，向芯片1的正投影，与芯片1上的硅通孔重合。此外，不同的芯片之间需要互联，以形成信号传输通路时，该不同芯片之间，通过硅通孔和焊盘连接。如图1所示的3D堆叠结构中，通常，业务信号(例如数据信号或者控制信号)与电源信号均通过底层芯片的背面发出，通过硅通孔向上层芯片传输。例如，图1中芯片1需要将特定的业务信号提供至芯片2，也即该业务信号一对一传输，其余芯片不接收该业务信号，则芯片1通过芯片1中的硅通孔a2以及焊盘，与芯片2下表面的重布线层连接，芯片2下表面的重布线层将接收到的信号传输至芯片2上相应引脚上。
如图1所示的3D堆叠结构，由于芯片3不需要接收从芯片1的硅通孔a2传输的业务信号，则芯片2上、与硅通孔a2对应位置处的硅通孔b2，与芯片3之间互联断开，也即硅通孔b2不再进行业务信号传输，由此，导致硅通孔的浪费。其他场景中，上述不再传输业务信号的硅通孔b2，有可能被用来传输电源信号。该种情况下，通常需要在芯片2的下表面、硅通孔b2与芯片2下表面的重布线层之间设置导电线路，该导电线路用于将硅通孔b2与下表面的重布线层隔离开，该导电线路将芯片2上的电源端口与硅通孔b2连通。该导电线路可以是芯片2的后道布线层，其结构包含一层或几层金属线或金属连接孔。芯片1的背面传输电源的信号，通过芯片1上的硅通孔a1、焊盘、硅通孔b1、设置于芯片2上表面的布线层、硅通孔b2、芯片2下表面的导电线路传输至芯片2上的供电端口(如图中的黑线所示)。然而，通过芯片2上表面的布线层以及硅通孔b2进行电源信号的传输，会由于引线过长导致电阻过大，带来额外的压降损失。
本申请实施例提供的三维堆叠结构，通过在第一芯片(也即发送信号或直连外界信号的芯片)与第二芯片(也即接收信号的芯片)之间的介质层中设置导电结构，将第一芯片上的第一硅通孔、与第二芯片上的第二硅通孔之间互联断开(第二硅通孔向第一硅通孔的正投影，与第一硅通孔至少部分重合)。从而，第一芯片所发送的信号或外界输入的信号，可以通过第一硅通孔以及该导电结构直接传输至第二芯片的信号端口中，第二芯片与堆叠于第二芯片之上的第三芯片之间不需要断开，第二芯片还可以通过第二硅通孔与第三芯片之间进行其他信号的传输，该其他信号例如可以为电源信号，也可以为其他的传输的信号。这样一来，可以提高芯片上硅通孔的利用率；此外，当需要向第二芯片传输电源信号时，本申请实施例通过设置上述导电结构，可以不需要在第二芯片上额外设置用于传输电源信号的布线层和芯片中的导电线路，简化工艺复杂度；另外，本申请实施例通过设置上述导电结构，当需要向第二芯片传输电源信号时，可以不需要经过第二硅通孔，从而可以避免额外的压降损失。由此，本申请实施例提供的3D堆叠结构，可以提高信号传输性能。
本申请实施例提供的3D堆叠结构，可以为晶圆-晶圆(WoW，Wafer on Wafer)堆叠结构，可以为芯片-晶圆(CoW，chip on wafer)堆叠结构，还可以为芯片-芯片(CoC，Chip on Chip)堆叠结构。该3D堆叠结构中，可以设置有多个不同功能的芯片，例如包括但不限于逻辑芯片、存储芯片、通信芯片或传感器芯片等。该3D堆叠结构中，可以依次堆叠多个芯片，沿堆叠方向，各芯片之间通过硅通孔 连通，以实现信号交流。需要说明的是，3D堆叠结构可以堆叠更多或更少的芯片，本申请实施例不对3D堆叠结构中所堆叠的芯片的数目进行具体限定，根据场景的需要设置。本申请实施例中所述的芯片可以为裸芯片(Die)，也可以是裸芯片与其他芯片或部件(有源器件或无源器件等)通过简单封装后形成的芯片，还可以是经过封装之后形成的芯片封装结构，此处不作限定。此外，本申请实施例所示的3D堆叠结构所包括的芯片可以包括但不限于：片上系统(System on chip)、存储器(Memory)、分立器件、应用处理芯片(Application Processor,AP)、微机电系统(Micro-Electro-Mechanical System，MEMS)、微波射频芯片、专用集成电路(ApplicationSpecific Integrated Circuit，简称ASIC)等芯片。上述应用处理芯片或专用集成电路在具体应用中可以是中央处理器(Central Processing Unit,CPU)、图像处理器(Graphics Processing Unit,GPU)、人工智能处理器，例如，神经网络处理器(Network Processing Unit，NPU)等。存储器可以是高速缓冲存储器(cache)、随机存取存储器(Random Access Memory，RAM)、只读存储器(Read Only Memory，ROM)或其他存储器。分立器件例如可以包括但不限于例如场效应晶体管、双极性晶体管等。本申请实施例中以芯片-芯片堆叠结构为例，通过图2-图6所示的实施例，对本申请实施例提供的3D堆叠结构进行详细描述。
请参考图2，图2是本申请实施例提供的3D堆叠结构的一个结构示意图。在图2中，示出了芯片1、芯片2和芯片3该三个芯片。芯片2堆叠于芯片1之上，芯片3堆叠于芯片2之上。需要说明的是，3D堆叠结构可以堆叠更多或更少的芯片，本申请实施例不对3D堆叠结构中所堆叠的芯片的数目进行具体限定，根据场景的需要设置。每两个堆叠芯片之间设置有介质层，该介质层中的介质例如为氧化硅，氮化硅，碳氮化硅，以用于对各芯片之间进行隔离以及对芯片提供支撑和保护。芯片1和芯片2之间设置有介质层S1，芯片2和芯片3之间设置有介质层S2。
在图2中，每一个芯片上设置有三个硅通孔，各硅通孔贯穿芯片的上表面和下表面。例如，芯片1包括硅通孔a1、硅通孔a2和硅通孔a3，每一个硅通孔均贯穿芯片1的上表面和下表面；芯片2包括硅通孔b1、硅通孔b2和硅通孔b3，每一个硅通孔均贯穿芯片2的上表面和下表面。此外，芯片1和芯片2上的硅通孔呈阵列排布，也即是说，硅通孔b1向硅通孔a1的正投影，与硅通孔a1至少部分重合，硅通孔b2向硅通孔a2的正投影，与硅通孔a2至少部分重合；硅通孔b3向硅通孔a3的正投影，与硅通孔a3至少部分重合，图2中示意性的示出了硅通孔b1向硅通孔a1的正投影，与硅通孔a1重合，硅通孔b2向硅通孔a2的正投影，与硅通孔a2重合，硅通孔b3向硅通孔a3的正投影，与硅通孔a3重合。
在图2中，为了使得信号能够在各芯片之间传输，上述各介质层中设置有导电结构21，导电结构21用于连接两相邻芯片上的导电线路。该导电结构21可以设置于硅通孔的侧边，也即导电结构位于硅通孔的投影范围之外。假设芯片1需要将信号(例如自身产生的信号或者外部输入的信号)传输给芯片2上的某一电路结构或部件，芯片2上的其余电路或部件以及芯片3均不接收该信号，也即信号为芯片1上某一部件与芯片2上某一部件之间的一对一传输。此外，芯片1需要通过硅通孔a2将信号传输至芯片2上。则导电结构21嵌入介质层S1中，且位于硅通孔a2以及硅通孔b2的侧边，图2中示出了导电结构21位于硅通孔a2和硅通孔a3之间。如图2所示，芯片1的上表面设置有导电线路r1，导电结构21通过导电线路r1与硅通孔a2中的导电材料连接。此外，芯片2的下表面设置有导电线路r2，导电结构21通过导电线路r2与芯片2上的信号端口连接，以向芯片2上的部件或电路传输信号。需要说明的是，导电线路r2与芯片2上的任意硅通孔均不连通。进一步的，硅通孔a2和硅通孔b2之间不设置导电结构，也可以说硅通孔a2和硅通孔b2之间未通过导电物体形成电连接，或者说硅通孔a2和硅通孔b2之间的互联断开。从而，芯片1发出的信号通过硅通孔a2、导电结构21以及芯片2上的导电线路，直接传输至芯片2中用于接收信号的部件上。
本申请实施例中，信号端口也可以称为信号引出端，其与芯片内部的导电模块(例如场效应晶体管的源极或漏极)或者集成电路的某一模块连接。信号端口例如可以包括但不限于焊盘、焊球或者金属走线等。另外，在其他场景中，信号端口也可以为芯片内部的某一模块，例如场效应晶体管的源极或漏极。当信号端口为芯片内部的某一模块时，信号端口的表面靠近导电线路r2的一侧还设置有信号端口布线层和用于连接信号端口布线层以及导电线路r2的导电通孔(图中未示出该信号端口布线层以及导电通孔)，从而信号端口通过该信号端口布线层以及导电通孔与导电线路r2连接。
一种可能的实现方式中，第二芯片上的信号端口的正投影与第一硅通孔部分重合；一种可能的实 现方式中，第二芯片上的信号端口的正投影与第一硅通孔完全不重合。
从图2中可以看出，与图1所示的现有技术中直接将芯片1上的硅通孔a2与芯片2上的硅通孔b2进行互联、将芯片2上的硅通孔b2与芯片3上的硅通孔互联断开相比，本申请实施例通过将芯片1上的硅通孔a2与芯片2上的硅通孔b2之间的互联断开，在硅通孔旁边设置导电结构21，可以使得芯片2上的硅通孔b2可以与其他硅通孔(例如芯片1上的硅通孔a1)连通，以进行其他信号的传输，避免硅通孔的浪费。此外，图1所示的现有技术中，由于硅通孔a2与芯片2上的硅通孔b2之间仍然连通，当硅通孔传输电源信号时，则需要在硅通孔a2背面重新设置导电线路，以将信号引至芯片2上的电源端口。这就增加了3D堆叠结构的工艺制备复杂度。而本申请实施例中，通过将芯片1上的硅通孔a2与芯片2上的硅通孔b2之间的互联断开，与图1所示的现有技术相比，可以不需要在芯片2的背面额外设置用于传输电源信号的导电线路，从而降低3D堆叠结构的工艺制备复杂度。另外，本申请实施例中，当需要向芯片2传输电源信号时，还可以将电源信号通过硅通孔a1直接传输至芯片2上，与现有技术中需要通过硅通孔a1、硅通孔b1以及硅通孔b2传输相比，可以避免引线过长导致电阻过大，降低压降损失。由此，本申请实施例提供的3D堆叠结构，可以提高信号传输性能。
请继续参考图2，如图2所示，在芯片2的下表面(也即芯片2上靠近芯片1的一侧)设置有导电线路r3，该导电线路r3与硅通孔b2连通。需要说明的是，导电线路r3与芯片2的下表面上设置的导电线路r2不连通，从而使得硅通孔b2与硅通孔b1之间断开。另外，导电线路r3还与芯片1上的硅通孔a1连通。这样一来，芯片2与芯片1之间通过导电线路r3以及硅通孔a1连通。芯片1的下表面传输的电源信号，通过硅通孔a1以及导电线路r3传输至芯片2上的电源端口。另外，芯片3与芯片1之间通过硅通孔b2、导电线路r3以及硅通孔a1连通，当芯片1需要向芯片3传输信号时，通过硅通孔a1传输的信号可以经过导电线路r3以及硅通孔b2传输芯片3，从而可以提高硅通孔b2的利用率。
需要说明的是，本申请实施例中所述的导电线路r1、导电线路r2和导电线路r3，可以为金属层，该金属层上设置有图案化的导电线路；此外，在其他可能的实现方式中，本申请实施例中所述的导电线路r1、导电线路r2和导电线路r3，也可以为重布线层，本申请实施例对此不做具体限定。
本申请实施例中，除了硅通孔a2与硅通孔b2之间断开连接之外，其余位于同一列的硅通孔之间均连通。如图2所示，介质层S1和介质层S2中还设置有导电结构22。该导电结构22，设置于同一列的两个硅通孔之间、以及硅通孔与芯片之间，以实现同一列相邻两个硅通孔之间的连通、以及硅通孔与芯片间的连通，进而实现芯片间的连通。其中，硅通孔向导电结构22的正投影，至少部分覆盖导电结构22。具体的，如图2所示，在硅通孔a1和硅通孔b1之间设置有导电结构22。硅通孔a1或者硅通孔b1向导电结构22的正投影，覆盖导电结构22。在硅通孔b1、硅通孔b2以及硅通孔b3与芯片3之间，均分别设置有导电结构22，以连通芯片2上的硅通孔以及芯片3上的导电线路。
进一步的，本申请实施例一种可能的实现方式中，除了在芯片1的上表面设置有导电线路r1、芯片2的下表面设置有导电线路r2、导电线路r3之外，沿芯片堆叠方向，在芯片1的上表面、芯片2的上表面以及芯片3的下表面均可以设置有导电线路，以实现各层芯片上硅通孔与芯片之间的连通、以及各芯片之间的连通。具体参考图3，如图3所示，芯片1的上表面还设置有导电线路r4，芯片2的上表面还设置有到导电线路r5，芯片3的下表面还设置有导电线路r6。其中，芯片1上表面的导电线路r1与导电线路r4之间不相连接，以使得硅通孔a1与硅通孔a2之间相互隔离。导电线路r4与硅通孔a1、以及硅通孔a1和硅通孔b1之间的导电结构22连通；导电线路r5用于连通芯片2上的各硅通孔、以及芯片2与芯片3之间的导电结构22。需要说明的是，以上各导电线路可以是由金属层形成的图案化导电线路，也可以是重布线层。此外，还需要说明的是，图3所示的导电线路的数目、各导电线路之间的连接关系为示意性的，其基于信号一对一传输的路径以及电源信号的传输路径来设置，本申请实施例不做具体限定。
本申请实施例中，如图2和图3所示的导电结构21以及导电结构22，可以通过多种方式实现。在第一种可能的实现方式中，导电结构21可以由焊盘(bonding pad)以及连接焊盘与芯片的通孔形成，如图4A所示。以用于连接芯片1上的硅通孔a2与芯片2上的信号端口的导电结构21为例，结合图4B，进行更为详细的描述。其中，图4B为如图4A所示的导电结构21的局部放大示意图。如图4B所示，导电结构21包括焊盘211、焊盘212、用于连接焊盘211与硅通孔的导电通孔213以及用于连接焊盘212与芯片3上的部件的导电通孔214形成。其中，焊盘211与焊盘212完全重叠设置，或者焊 盘211与212部分错位重叠设置，以形成导电通路。导电通孔213用于连通焊盘211与芯片1上表面的导电线路r1，导电通孔214用于连通焊盘212与芯片2下表面的导电线路r2。在其他可能的场景中，导电结构21上可以仅设置一个焊盘211，不设置焊盘212，导电通孔213和导电通孔214均连接至焊盘211。在其他可能的场景中，导电结构21上可以仅设置一个导电通孔214，不设置导电通孔213，焊盘212连接到此通孔214上，焊盘212与焊盘214完全重叠设置，或部分错位重叠设置。在其他可能的场景中，导电结构21上可以仅设置一个导电通孔213，不设置导电通孔214，焊盘211连接到此通孔214上，焊盘212与焊盘214完全重叠设置，或部分错位重叠设置。图4A中所示的其余导电结构21与导电结构22，与图4B所示的连接硅通孔a2与芯片2上的信号端口的导电结构21相同或相类似，不再赘述。图4A中其他结构以及各结构之间的连接关系与图2中的相同，具体参考图2中相关结构的描述，不再赘述。
在第二种可能的实现方式中，导电结构21可以仅由导电通孔形成，如图5A所示。以用于连接芯片1上的硅通孔a2与芯片2上的信号端口的导电结构21为例，结合图5B，进行更为详细的描述。其中，图5B为如图5A所示的导电结构21的局部放大示意图。如图5B所示，导电结构21包括导电通孔213和导电通孔214。其中，导电通孔213与导电通孔214重叠设置，以形成导电通路。导电通孔213用于连通导电通孔214与导电线路r1，导电通孔214用于连通导电通孔213与导电线路r2。在其他可能的场景中，导电结构21上可以仅设置一个导电通孔213，导电线路r1与导电线路r2通过导电通孔213连通。图5A中所示的其余导电结构21与导电结构22，与图4B所示的连接硅通孔a2与芯片2上的信号端口的导电结构21相同或相类似，不再赘述。图5A中其他结构以及各结构之间的连接关系与图2中的相同，具体参考图2中相关结构的描述，不再赘述。
另外，在一种可能的实现方式中，3D堆叠结构中不再相互连接的两硅通孔之间的介质层上，其中任意一个硅通孔的投影覆盖的区域，可以不设置任何结构，如图2中、介质层上硅通孔a2与硅通孔b2之间的区域。
在其他可能的实现方式中，当本申请实施例中所述的导电结构21和导电结构22如图4A所示时，3D堆叠结构中不再相互连接的两硅通孔之间的介质层上，其中任意一个硅通孔的投影覆盖的区域，可以仅设置有焊盘，但不设置导电通孔，从而通过断开导电通孔与硅通孔之间的连接，来断开两硅通孔之间的连接，如图4A中、介质层上硅通孔a2与硅通孔b2之间的区域。
请继续参考图6，图6是本申请实施例提供的3D堆叠结构的又一个结构示意图。与图2所示的3D堆叠结构不同的是，如图6所示的3D堆叠结构堆叠有芯片1～芯片4四个芯片，除最上层芯片之外，其余每一个芯片上设置有四个硅通孔，各芯片上的硅通孔呈阵列排布，每两个芯片之间分别通过介质层分隔开来。在图6中，在介质层S1、介质层S2和介质层S3中均设置有导电结构21，各导电结构21分别设置于硅通孔的侧边，以实现信号由3D堆叠结构的底部(也即靠近芯片1底面的一侧)分别向各层芯片一对一传输。如图6所示，位于介质层S1中的导电结构21，设置于第二列硅通孔侧边；位于介质层S2中的导电结构21，设置于第三列硅通孔侧边；位于介质层S3中的导电结构21，设置于第四列硅通孔侧边。从而，硅通孔a2与硅通孔b2之间的互连断开，硅通孔b3与硅通孔c3之间的互连断开，硅通孔c4与硅通孔d4之间的互连断开。芯片1的背面传输的指定到达芯片2信号，通过硅通孔a2以及硅通孔a2侧边的导电结构21，传输至芯片2上的信号端口；芯片1的背面传输的指定到达芯片3信号，通过硅通孔a3、硅通孔b3以硅通孔b3侧边的导电结构21，传输至芯片3上的信号端口；芯片1的背面传输的指定到达芯片4信号，通过硅通孔a4、硅通孔b4、硅通孔c4以硅通孔c4侧边的导电结构21，传输至芯片4上的信号端口。此外，在介质层S1、介质层S2和介质层S3中均设置有导电结构22，如图6所示，除了上述互连断开的硅通孔之间不设置导电结构22之外，其余各硅通孔之间、硅通孔与芯片之间均设置有导电结构22，以实现硅通孔之间以及芯片之间的互连。具体的，硅通孔a1与硅通孔b1之间、硅通孔b1与硅通孔c1之间、硅通孔c1与芯片4之间、硅通孔b2与硅通孔c2之间、硅通孔c2与芯片4之间、硅通孔a3与硅通孔b3之间、硅通孔c3与芯片4之间、硅通孔a4与硅通孔b4之间以及硅通孔b4与硅通孔c4之间，均设置有导电结构22。此外，为了进一步实现硅通孔之间以及芯片之间的互连，芯片1的上表面、芯片2的上表面与下表面、芯片3的上表面与下表面以及芯片4的下表面，均设置有导电线路，每个芯片上的导电线路均与同芯片上的硅通孔连接。该导电线路例如可以为金属化的导电线路或者重布线层。可以理解的是，图6所示的导电线路的数目、 各导电线路之间的连接关系为示意性的，其基于信号一对一传输的路径以及电源信号的传输路径来设置，本申请实施例不做具体限定。图6所示的示例中，当芯片1的背面传输电源信号时，该电源信号可以通过硅通孔a1、硅通孔b1、硅通孔c1、硅通孔b2、硅通孔c2、硅通孔c3以及导电结构22进行传输，与图1所示的现有技术相比，可以避免硅通孔的浪费。可以理解，上述电源信号也可以替换为其他信号。
本申请实施例还提供一种电子设备，该电子设备例如可以包括但不限于芯片或芯片组或搭载有芯片或芯片组的电路板等。一种场景中，该电子设备可以是一个终端设备，例如可以包括但不限于便携式计算机(如手机)、笔记本电脑、可穿戴电子设备(如智能手表)、平板电脑、增强现实(augmentedreality，AR)或虚拟现实(virtual reality，VR)设备或者电动牙刷等。一种场景中，该电子设备例如还可以为服务器设备。具体的，本申请所示的电子设备包括如图2～图6任意实施例所示的3D堆叠结构。其中，电子设备上可以设置有印刷电路板，从而，如图2、图3或者图6所示的芯片堆叠结构，通过芯片1的背面设置于印刷电路板上。也即是说，芯片1的背面通过焊球、焊盘或者胶等设置于印刷电路板上。此外，印刷电路板上还设置有电源、公共地等，该电源或公共地等通过芯片1中的硅通孔a1，向所堆叠的上层芯片供电。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (10)

  1. 一种三维堆叠结构，其特征在于，包括：
    堆叠设置的多个芯片，所述多个芯片中的第一芯片和第二芯片均设置有至少一个硅通孔；
    第一介质层，设置于所述第一芯片与所述第二芯片之间，所述第一介质层中设置有第一导电结构；
    所述第一芯片的至少一个硅通孔中的第一硅通孔，通过所述第一导电结构，与所述第二芯片上的信号端口连接；
    其中，所述第一硅通孔与所述第二芯片的至少一个硅通孔中的第二硅通孔之间断开连接，所述第二硅通孔向所述第一硅通孔的正投影，与所述第一硅通孔至少部分重合。
  2. 根据权利要求1所述的三维堆叠结构，其特征在于，所述第二芯片包括远离所述第一芯片的第一表面和靠近所述第一芯片的第二表面，其中，所述第二芯片的第二表面设置有第一导电线路；
    所述第二芯片的至少一个硅通孔中的第三硅通孔，与所述第二硅通孔水平间隔设置，所述第二硅通孔与所述第三硅通孔通过所述第一导电线路连接。
  3. 根据权利要求2所述的三维堆叠结构，其特征在于，所述第一芯片的至少一个硅通孔中的第四硅通孔，向所述第三硅通孔的正投影，与所述第三硅通孔至少部分重合；
    所述第一介质层中还设置有第二导电结构，所述第三硅通孔通过所述第二导电结构与所述第四硅通孔连接。
  4. 根据权利要求2或3所述的三维堆叠结构，其特征在于，所述第二芯片的第二表面还设置有第二导电线路，所述第一导电结构通过所述第二导电线路与所述信号端口连接；
    其中，所述第一导电线路与所述第二导电线路之间相互隔离。
  5. 根据权利要求3所述的三维堆叠结构，其特征在于，所述第一芯片包括靠近所述第二芯片的第一表面和远离所述第二芯片的第二表面，所述第一芯片的第一表面设置有第三导电线路和第四导电线路；
    所述第三导电线路用于连通所述第一硅通孔与所述第一导电结构；
    所述第四导电线路用于连通所述第四硅通孔与所述第二导电结构；
    其中，所述第三导电线路与所述第四导电线路之间相互隔离。
  6. 根据权利要求1-5任一项所述的三维堆叠结构，其特征在于，所述多个芯片还包括第三芯片，所述第三芯片和所述第一芯片之间设置有第二介质层，所述第二介质层中设置有第三导电结构；
    所述第三芯片中还设置有第五硅通孔，所述第五硅通孔通过所述第三导电结构与所述第一硅通孔连接，其中，所述第一硅通孔向所述第五硅通孔的正投影，与所述第五硅通孔至少部分重合。
  7. 根据权利要求1-6任一项所述的三维堆叠结构，其特征在于，所述第一导电结构包括第一导电通孔和第二导电通孔；
    所述第一导电通孔用于连接所述第二导电通孔与所述信号端口；
    所述第二导电通孔用于连接所述第一导电通孔与所述第一硅通孔。
  8. 根据权利要求7所述的三维堆叠结构，其特征在于，所述第一导电结构还包括两个相互交叠的第一焊盘和第二焊盘；
    所述第一导电通孔通过所述第一焊盘和所述第二焊盘与所述第二导电通孔连接。
  9. 根据权利要求4所述的三维堆叠结构，其特征在于，所述第一导电线路和所述第二导电线路，为金属层或者重布线层。
  10. 一种电子设备，其特征在于，所述电子设备包括如权利要求1-9任一项所述的三维堆叠结构；
    所述电子设备还包括印刷电路板，所述三维结构通过所述第一芯片远离所述第二芯片的表面，设置于所述印刷电路板上。
PCT/CN2023/104032 2022-11-23 2023-06-29 三维堆叠结构和电子设备 WO2024109053A1 (zh)

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CN102263089A (zh) * 2010-05-27 2011-11-30 海力士半导体有限公司 具有多芯片结构的半导体集成电路
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