WO2024103962A1 - 微显示器件及制备方法 - Google Patents

微显示器件及制备方法 Download PDF

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Publication number
WO2024103962A1
WO2024103962A1 PCT/CN2023/120972 CN2023120972W WO2024103962A1 WO 2024103962 A1 WO2024103962 A1 WO 2024103962A1 CN 2023120972 W CN2023120972 W CN 2023120972W WO 2024103962 A1 WO2024103962 A1 WO 2024103962A1
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Prior art keywords
layer
opening
passivation layer
doped semiconductor
led
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PCT/CN2023/120972
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English (en)
French (fr)
Inventor
庄永漳
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镭昱光电科技(苏州)有限公司
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Publication of WO2024103962A1 publication Critical patent/WO2024103962A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings

Definitions

  • the present application relates to the field of Micro-LED manufacturing technology, and specifically to a micro display device and a preparation method thereof.
  • Microdisplay devices also known as micro light-emitting diodes, are a type of high-density integrated LED arrays obtained by thinning and miniaturizing the LED structure. Because each independent LED unit can emit light by itself, the photoelectric conversion efficiency is greatly improved, and low-energy or high-brightness display device design can be realized.
  • microdisplay devices in order to produce multiple completely electrically isolated LED units, it is usually necessary to expose contacts to achieve electrical connection between the LED units and the drive substrate, but during the electrical connection process, it is easy to cause short circuits at the contacts, which directly affects the display effect of the microdisplay device.
  • a micro display device and a preparation method wherein a passivation layer is provided to avoid contact short circuit.
  • a micro display device comprising:
  • a driving substrate wherein the driving substrate comprises a plurality of contacts
  • first passivation layer located on the driving substrate, the first passivation layer being provided with a second opening corresponding to the location of the contact point, the second opening allowing the first passivation layer to expose the contact point;
  • the metal layer being located on the first passivation layer, the metal layer being provided with a first opening corresponding to the position of the second opening, the first opening enabling the metal layer to expose the contact;
  • a plurality of LED units wherein the LED units are located on the metal layer and arranged in an array, the first electrode layer of the LED units is electrically connected to the metal layer, and the contact points are located between adjacent LED units;
  • a conductive layer wherein the conductive layer electrically connects the contact point with the corresponding second electrode layer of the LED unit through the second opening and the first opening, so that the LED unit is driven alone through the contact point.
  • the first electrode layer is a first doped semiconductor layer
  • the second electrode layer is a second doped semiconductor layer
  • the LED unit further includes an active layer located between the first doped semiconductor layer and the second doped semiconductor layer; the second doped semiconductor layers of adjacent LED units are electrically isolated from each other; and the contacts are electrically connected to the corresponding second doped semiconductor layers of the LED units.
  • a second passivation layer is included, and the second passivation layer is located on the LED unit;
  • the second passivation layer has a third opening exposing the second doped semiconductor layer, and the second opening is formed by etching the second passivation layer and the first passivation layer;
  • the conductive layer is located on the second passivation layer, and the conductive layer electrically connects the second doped semiconductor layer and the contact through the third opening and the second opening.
  • the material of the first passivation layer is at least one or more of SiN, SiO 2 , Al 2 O 3 , and TiO 2 ; the material of the metal layer is at least one or more of Cr, Ti, Au, Ni, Al, Pt, Sn, In, and Cu.
  • a diameter of the second opening is smaller than a diameter of the first opening.
  • the driving substrate is a silicon-based CMOS driving board or a thin film field effect transistor driving board.
  • the material of the first passivation layer is the same as the material of the second passivation layer. By setting the same material, it is convenient to directly open holes in the first passivation layer and the second passivation layer in a one-step process.
  • the size of the LED unit is 0.1-5 microns.
  • the material of the first passivation layer is at least one or more of SiO 2 , Al 2 O 3 , and SiN.
  • the present application also provides a method for preparing a micro display device, comprising:
  • the driving substrate comprising a plurality of contacts
  • LED units wherein the LED unit array is arranged on the metal layer, the first electrode layer of the LED unit is electrically connected to the metal layer, and the contact point is located between adjacent LED units;
  • a conductive layer is formed, and the conductive layer electrically connects the contact point with the corresponding second electrode layer of the LED unit through the second opening and the first opening, so that the LED unit is driven alone through the contact point.
  • the first electrode layer is a first doped semiconductor layer
  • the second electrode layer is a second doped semiconductor layer
  • the LED unit further includes an active layer located between the first doped semiconductor layer and the second doped semiconductor layer; the second doped semiconductor layers of adjacent LED units are electrically isolated from each other; and the contacts are electrically connected to the corresponding second doped semiconductor layers of the LED units.
  • the method before the step of providing the LED unit, the method further includes:
  • the metal layer is formed on the first passivation layer, and the substrate and the driving substrate are bonded to make the LED epitaxial layer located on the first passivation layer.
  • the step of providing an LED unit comprises:
  • Ions are implanted into the LED epitaxial layer to form the LED unit.
  • the method before setting the second opening to expose the contact, the method further comprises:
  • a second passivation layer is formed, wherein the second passivation layer is located on the LED unit; the second passivation layer has a third opening exposing the second doped semiconductor layer, and the second opening is formed by etching the second passivation layer and the first passivation layer; the electrode layer is located on the second passivation layer; the electrode layer electrically connects the second doped semiconductor layer to the contact through the third opening and the second opening.
  • the first passivation layer is formed on the driving substrate by CVD.
  • the first passivation layer is formed on the driving substrate by PVD.
  • the first passivation layer is located between the metal layer and the driving substrate, so that the contacts on the driving substrate are isolated from the metal layer, thereby avoiding short circuits between the contacts; the metal layer is used for bonding the LED unit to the driving substrate, and the bonding methods include adhesive bonding, metal-to-metal bonding, metal oxide bonding, wafer-to-wafer bonding, etc.
  • the active layer may be a multi-quantum well structure for confining electron and hole carriers to the quantum well region.
  • the carriers undergo radiative recombination and emit photons, converting electrical energy into light energy.
  • the first and second doped semiconductor layers may include one or more layers based on II-VI materials such as ZnSe or ZnO or III-V materials such as GaN, AlN, InN, InGaN, GaP, AlInGaP, AlGaAs and alloys thereof.
  • II-VI materials such as ZnSe or ZnO or III-V materials
  • III-V materials such as GaN, AlN, InN, InGaN, GaP, AlInGaP, AlGaAs and alloys thereof.
  • the LED unit may be a stepped structure, which further disconnects and electrically isolates the first doped semiconductor layers of adjacent LED units from each other; and the metal layers between adjacent LED units are disconnected from each other and the first opening is formed by etching the metal layer.
  • the second passivation layer is used to protect and insulate the LED unit.
  • the conductive layer is used to connect the LED unit and the driving substrate and realize the function of independent driving.
  • the etching includes dry etching or wet etching.
  • the LED units are micro light emitting diodes, and the LED units are arranged in an array; the first passivation layer and the metal layer correspond to the LED units one by one, respectively, to ensure that each LED unit and the contact point will not be short-circuited.
  • the second passivation layer includes a first segment located on the LED unit, a second segment located on the metal layer, and a third segment located on the first passivation layer; the second segment is integrally connected to the first segment, the third segment is integrally connected to the second segment, and the third segment is located on a side of the second segment away from the first segment; wherein the first segment covers the first doped semiconductor layer and the second doped semiconductor layer.
  • the size of the LED unit is 0.1-5 micrometers.
  • the LED units are arranged periodically, and the spacing between adjacent pixels is 1-10 micrometers.
  • the micro display device of the present application forms electrical isolation between the contact and the metal layer by setting the first passivation layer, thereby preventing the contact from directly contacting the metal layer. Even if the first opening size is too small or the position is deviated during the preparation process, it will not cause a short circuit between the contact and the metal layer.
  • the present invention does not need to enlarge the first opening size or sacrifice the LED unit size, thereby improving the light-emitting area and display effect of the micro display device.
  • the method of the present application sets a first passivation layer so that the contact and the metal layer are separated, and a certain distance is formed between the contact and the metal layer, thereby reducing the probability of the contact directly contacting the metal layer. Even if the problem of small opening size or offset opening position is encountered during the preparation process, it will not cause a short circuit of the contact.
  • FIG1 is a schematic cross-sectional view of a micro display device according to some embodiments of the present application.
  • FIG2 is a partial enlarged schematic diagram of point G in FIG1;
  • FIG3 is a schematic diagram of an LED epitaxial layer structure of some embodiments of the present application.
  • FIG4 is a schematic structural diagram of a driving substrate in some embodiments of the present application.
  • FIG5 is a schematic diagram of the structure after a metal layer is formed in some embodiments of the present application.
  • FIG6 is a schematic diagram of the structure after forming a first passivation layer in some embodiments of the present application.
  • FIG7 is a schematic diagram of the structure of an LED epitaxial layer and a driving substrate after bonding in some embodiments of the present application;
  • FIG8 is a schematic diagram of the structure after removing the upper substrate of the LED epitaxial layer in some embodiments of the present application.
  • FIG9 is a schematic diagram of the structure of some embodiments of the present application after forming an LED unit
  • FIG10 is a schematic diagram of a structure after a first opening is formed on a metal layer in some embodiments of the present application.
  • FIG11 is a schematic diagram of the structure after forming a second passivation layer in some embodiments of the present application.
  • FIG12 is a schematic structural diagram of a second passivation layer in some embodiments of the present application.
  • FIG13 is a schematic diagram of the structure after forming a third opening in some embodiments of the present application.
  • FIG14 is a schematic diagram of the structure after forming an electrode layer in some embodiments of the present application.
  • FIG15 is a schematic diagram of the structure of the opening being too small and the contact position deviation in the existing preparation process
  • FIG16 is a schematic diagram of a structure in which a large opening size leads to a small size of an LED unit in an existing preparation process
  • the numbers in the figure are: 100-micro display device, 101-driving substrate, 102-first passivation layer, 103-metal layer, 104-LED unit, 105-second passivation layer, 106-conductive layer, 110-LED epitaxial layer, 111-substrate, 1011-contact, 1021-second opening, 1031-first opening, 1041-first doped semiconductor layer, 1042-active layer, 1043-second doped semiconductor layer, 1051-first section, 1052-second section, 1053-third section, 10511-third opening.
  • the disclosure of the present application provides many different embodiments or examples to realize the different structures of the present application.
  • the parts and settings of specific examples are described in the present application. Of course, they are only examples, and the purpose is not to limit the present application.
  • the present application can repeat reference numbers and/or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and/or settings discussed.
  • the various specific processes and material examples provided by the present application but those of ordinary skill in the art can be aware of the application of other processes and/or the use of other materials.
  • the term can be understood at least in part according to the usage of the above application.
  • the term “one or more” used in the present application depends at least in part on the above application, and can be used to describe any component, structure or feature in the singular, or can be used to describe the combination of components, structures or features in the plural.
  • terms such as “one”, “one” or “the” can also be understood at least in part to convey singular usage or convey plural usage depending on the above application.
  • the term “based on" can be understood as not necessarily intended to convey a set of exclusive factors, but at least in part depending on the above application can instead allow the presence of additional factors that do not necessarily have to be clearly described.
  • spatially relative terms such as “below,” “beneath,” “lower,” “above,” “upper,” etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the drawings.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings.
  • the device may be otherwise oriented, rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein may be likewise interpreted accordingly.
  • the term "layer” used in this application refers to a material portion including an area with a certain thickness.
  • the layer can extend over the entire lower or upper structure, or can have a degree less than the scope of the lower or upper structure.
  • the layer can be a region of a homogeneous or inhomogeneous continuous structure, and its thickness is less than the thickness of the continuous structure.
  • the layer can be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes therebetween.
  • the layer can extend horizontally, vertically and/or along a tapered surface.
  • the substrate can be a layer, one or more layers can be included therein, and/or one or more layers can be provided thereon, above and/or below.
  • a layer can include multiple layers.
  • the semiconductor layer can include one or more doped or undoped semiconductor layers, and can have the same or different materials.
  • the positional relationship of "upper” and “lower” in the present application corresponds to the upper and lower parts in FIG. 1 respectively.
  • the upper part in FIG. 1 is the light emitting direction
  • the upper surface of the LED unit 104 is the light emitting surface
  • the side surface is adjacent to the light emitting surface.
  • the side surface here is the non-light emitting side.
  • the term driving substrate 101 used in this application refers to the material on which subsequent material layers are added.
  • the driving substrate 101 itself can be patterned.
  • the material added to the top of the driving substrate 101 can be patterned or can remain unpatterned.
  • the driving substrate 101 can include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc.
  • the driving substrate 101 can be made of a non-conductive material, such as glass, plastic or sapphire wafer.
  • the substrate can have a semiconductor device or circuit formed therein.
  • the driving substrate 101 can be, for example, but not limited to, a display substrate including a CMOS (Complementary Metal Oxide Semiconductor), a complementary metal oxide semiconductor backplane or a TFT glass substrate.
  • CMOS Complementary Metal Oxide Semiconductor
  • the LED epitaxial layer 110 forms an LED unit 104 on the driving substrate 101.
  • the functional epitaxial layer is partially patterned/etched, and a thin continuous functional layer and metal layer 103 are allowed to remain to avoid potential functional pixel peeling.
  • the manufacturing method in the present application can further reduce physical damage to the sidewalls of the functional pixels, reduce damage to the quantum well structure serving as the light-emitting region of the LED unit 104, and improve the optical and electrical properties of the functional pixels.
  • micro refers to the descriptive size of certain devices or structures according to the embodiments of the present application.
  • micro display device used in this article is intended to represent a scale of 100 nanometers to 100 microns.
  • embodiments of the present application are not necessarily limited to this, and certain aspects of the embodiments can be applicable to larger and possibly smaller size scales.
  • the micro display device of the present application uses Micro-LED (Micro light-emitting diode, micro light-emitting diode structure), and the size of the micro light-emitting diode is reduced to 100 nanometers to 100 microns.
  • Micro-LED Micro light-emitting diode, micro light-emitting diode structure
  • the Micro-LED array is highly integrated, and the distance between the LED units of the Micro-LED in the array is further reduced to the order of 5 microns.
  • the display method of Micro-LED is to connect Micro-LEDs of 5 microns or even smaller sizes to the driving panel to achieve precise control of the brightness of each Micro-LED.
  • the structure of the LED unit 104 in the present application can be a common cathode or a common anode or an independent structure.
  • FIG1 shows a cross-sectional schematic diagram of a micro display device of some embodiments
  • FIG2 shows a partially enlarged schematic diagram of an LED unit 104.
  • the micro display device includes a driving substrate 101 and a plurality of LED units 104 located on the driving substrate 101, and a plurality of contacts 1011 are arranged on the driving substrate 101; a first passivation layer 102 is arranged between the LED units 104 and the driving substrate 101, the first passivation layer 102 is located on the driving substrate 101 and connected to the driving substrate 101, and a second opening 1021 corresponding to the position of the contact 1011 is arranged on the first passivation layer 102, and the second opening 1021 disconnects the first passivation layer 102 and exposes the contact 1011; a metal layer 102 is arranged between the first passivation layer 102 and the LED units 104.
  • the metal layer 103 is located on the first passivation layer 102 and connected to the first passivation layer 102.
  • the metal layer 103 is provided with a first opening 1031 corresponding to the position of the second opening 1021.
  • the first opening 1031 disconnects the metal layer 103 and corresponds one-to-one with the first passivation layer 102.
  • the LED units 104 are located on the metal layer 103 and arranged in an array.
  • the contacts 1011 are located between adjacent LED units 104. The contacts 1011 are electrically connected to the corresponding LED units 104 through the second opening 1021, so that the LED units 104 are driven individually through the contacts 1011.
  • the plurality of LED units 104 specifically refers to at least two or more LED units 104 .
  • the LED unit 104 has a first electrode layer and a second electrode layer, the first electrode layer is a first doped semiconductor layer 1041, the second electrode layer is a second doped semiconductor layer 1043, the first doped semiconductor layer 1041 is located on the metal layer 103, and the second doped semiconductor layer 1043 is located on the first doped semiconductor layer 1041; the LED unit 104 is formed by patterning the second doped semiconductor layer 1043, or etching the second doped semiconductor layer 1043 to form a mesa structure, or ion implanting the second doped semiconductor layer 1043.
  • An active layer 1042 is formed between the first doped semiconductor layer 1041 and the second doped semiconductor layer 1043 of each LED unit 104, and the active layer 1042 is a multi-quantum well layer MQW, and electrons and holes recombine in the quantum well region to generate photons to achieve light emission.
  • the first doped semiconductor layer 1041 between adjacent LED units 104 may be integrally connected, in which case the first doped semiconductor layer 1041 is an anode, the second doped semiconductor layer 1043 is a cathode, and a common anode structure is adopted, that is, the first doped semiconductor layer 1041 is a continuous functional layer structure, the first doped semiconductor layer 1041 extends across multiple LED units 104 and forms a common anode of these LED units 104, the second doped semiconductor layer 1043 is partially patterned or the second doped semiconductor layer 1043 is etched to form a step, and the second doped semiconductor layers 1043 of different LED units 104 are electrically isolated, so that each LED unit 104 can have a cathode with a voltage level different from that of other units.
  • the first doped semiconductor layer 1041 between adjacent LED units 104 can also be disconnected, so that the micro display device adopts a common cathode structure.
  • the first doped semiconductor layer 1041 and the second doped semiconductor layer 1043 may include one or more of II-VI materials (such as ZnSe or ZnO) or III-V materials (such as GaN, AlN, InN, InGaN, GaP, AlInGaP, AlGaAs and alloys thereof).
  • the first doped semiconductor layer 1041 is preferably P-type gallium nitride
  • the second doped semiconductor layer 1043 is preferably N-type gallium nitride.
  • the first passivation layer 102 is located between the driving substrate 101 and the metal layer 103, so that the contact 1011 on the driving substrate 101 is separated from the metal layer 103, avoiding the short circuit between the contact 1011 and the metal layer 103 caused by the offset of the opening position; the first passivation layer 102 may include SiO2 , Al2O3 , SiN or other suitable materials.
  • the metal layer 103 is an adhesive material layer for bonding the driving substrate 101 and the LED unit 104.
  • the metal layer 103 may include a conductive material such as a metal or a metal alloy.
  • the metal layer 103 may include Au, Sn, In, Cu or Ti.
  • a second passivation layer 105 is further disposed on the LED unit 104, as shown in FIG12 , and the second passivation layer 105 is used to protect the LED unit 104.
  • the second passivation layer 105 includes a first section 1051, a second section 1052, and a third section 1053.
  • the first section 1051 is located on the LED unit 104, covering the first doped semiconductor layer 1041 and the second doped semiconductor layer 1043.
  • the second section 1052 is located on the metal layer 103, and the third section 1053 is located on the first passivation layer 102.
  • the first section 1051, the second section 1052, and the third section 1053 are integrally connected to form the second passivation layer 105.
  • the second section 1052 is integrally connected to the first section 1051, and the third section 1053 is integrally connected to the second section 1052.
  • the third section 1053 is located on a side of the second section 1052 away from the first section 1051.
  • the second passivation layer 105 may include SiO 2 , Al 2 O 3 , SiN, or other suitable materials.
  • the second passivation layer 105 also includes polyimide, SU-8 photoresist or other photo-patternable polymers.
  • the second passivation layer 105 and the first passivation layer 102 can be made of the same material to facilitate direct hole formation in a one-step process.
  • a conductive layer 106 is further provided on the second passivation layer 105, a third opening 10511 is provided in the first section 1051 to expose the second doped semiconductor layer 1043, and a second opening 1021 is formed by directly etching the third section 1053 to expose the contact; the conductive layer 106 electrically connects the second doped semiconductor layer 1043 with the contact 1011 through the third opening 10511 and the second opening 1021, and the LED unit 104 is a micro light emitting diode, each LED unit 104 is independently driven by a different driving circuit, and each LED unit 104 can work independently.
  • the third opening 10511 is located at the center of the light emitting surface of each LED unit 104, and the second opening 1021 is located at the gap between adjacent LED units 104, and the contact 1011 is located at the center of the second opening 1021.
  • the conductive layer 106 is made of a conductive material, such as indium tin oxide ITO, Cr, Ti, Pt, Au, Al, Cu, Ge or Ni.
  • the material of the first passivation layer 102 is at least one or more of SiN, SiO 2 , Al 2 O 3 , and TiO 2 ; the material of the metal layer 103 is at least one or more of Cr, Ti, Au, Ni, Al, Pt, Sn, In, and Cu.
  • the diameter of the second opening 1021 is smaller than the diameter of the first opening 1031. Since the diameter of the second opening 1021 is smaller than the diameter of the first opening 1031, after forming the second passivation layer 105, the second passivation layer 105 and the first passivation layer 102 can be directly etched at the same time to form the second opening 1021, so that the second opening 1021 is located in the first opening 1031, and the passivation layer is etched in one step to greatly simplify the preparation process.
  • the first passivation layer 102 can be etched into holes first, and then the second passivation layer 105 can be etched into holes, as long as the holes are located in the first opening 1031. In this way, it can be ensured that a part of the second passivation layer 105 covers the metal layer 103 to prevent it from short-circuiting.
  • the size of the LED unit 104 is 0.1-10 microns.
  • 3 to 14 show cross-sectional views of different stages in the process of preparing the micro display device structure.
  • FIG3 and FIG4 schematic diagrams of the structures of the LED epitaxial layer 110 and the driving substrate 101 are respectively given, and a substrate 111 is provided on the LED epitaxial layer 110, and a contact 1011 is provided on the driving substrate 101.
  • the driving substrate 101 is provided, and a driving circuit is formed in the driving substrate 101, and the driving circuit includes the contact 1011; and a substrate 111 is provided, and an LED epitaxial layer 110 is formed on the substrate 111, and the LED epitaxial layer 110 includes a first doped semiconductor layer 1041, a second doped semiconductor layer 1043 and an active layer 1042.
  • the driving substrate 101 is a silicon-based CMOS backplane or a thin film field effect transistor.
  • Silicon-based CMOS is a chip made of silicon.
  • the substrate 111 is a semiconductor material, such as silicon, gallium nitride, etc., or the substrate 111 is a non-conductive material, such as sapphire or glass.
  • the first doped semiconductor layer 1041 is P-type gallium nitride
  • the second doped semiconductor layer 1043 is N-type gallium nitride.
  • a metal layer 103 is formed on the LED epitaxial layer 110.
  • the metal layer 103 may include a conductive material, such as a metal or a metal alloy.
  • the metal layer 103 may include Cr, Ti, Au, Ni, Al, Pt, Sn, In, Cu.
  • the metal layer 103 is prepared by deposition, electroplating, etc.
  • a first passivation layer 102 is formed on the driving substrate 101.
  • the first passivation layer 102 is formed on the driving substrate 101 by CVD or PVD.
  • the first passivation layer 102 may include SiN, SiO 2 , Al 2 O 3 , TiO 2 or other suitable materials.
  • the metal layer 103 may be made of metal material.
  • the metal layer 103 on the first passivation layer 102 is connected to the metal layer 103 on the LED epitaxial layer 110 by metal-to-metal bonding.
  • the LED epitaxial layer 110 on the substrate 111 is turned over, and the metal layer 103 on the first passivation layer 102 is aligned with the metal layer 103 on the LED epitaxial layer 110.
  • the metal layers 103 and 103 are fused into a layer structure through metal bonding to achieve bonding between the LED epitaxial layer 110 and the driving substrate 101.
  • the metal layer 103 is located on the first passivation layer 102.
  • the present application can prevent the influence of the driving substrate 101 at the bottom due to the excessive temperature during metal-to-metal bonding by setting the first passivation layer 102.
  • the introduction of the first passivation layer 102 can prevent the driving substrate 101 from warping, so as to achieve the effect of improving bonding and protecting the substrate.
  • the substrate 111 is removed and the LED epitaxial layer 110 is thinned.
  • the substrate 111 removal method includes but is not limited to laser lift-off, dry etching, wet etching, mechanical polishing, etc.; the thinning operation includes dry etching, wet etching or mechanical polishing.
  • the MESA pattern is designed according to the patterned mask, and the second doped semiconductor layer 1043 and the first doped semiconductor layer 1041 are removed to form a functionalized step structure, thereby obtaining LED units 104, which are distributed in an array.
  • the removal method includes dry etching or wet etching.
  • a first opening 1031 is provided on the metal layer 103 to expose the first passivation layer 102 , and the position of the first opening 1031 corresponds to the position of the contact 1011 ; the opening is provided by etching, and the etching method includes ion beam etching and the like.
  • a second passivation layer 105 is disposed on the entire surface of the LED unit 104.
  • the second passivation layer 105 includes a first section 1051 located on the LED unit 104, a second section 1052 located on the metal layer 103, and a third section 1053 located on the first passivation layer 102; the first section 1051, the second section 1052, and the third section 1053 are sequentially connected to form a whole.
  • the second passivation layer 105 can protect the LED unit 104.
  • the second passivation layer 105 is formed by chemical vapor deposition. Among them, the first section 1051 covers the first doped semiconductor layer 1041 and the second doped semiconductor layer 1043; the third section 1053 is located in the first opening 1031 and covers the first passivation layer 102.
  • a third opening 10511 is provided on the first section 1051 to expose the second doped semiconductor layer 1043, and the third section 1053 and the first passivation layer 102 located under the third section 1053 are etched to form a second opening 1021, and the contact 1011 is exposed. Since the third section 1053 is controlled to be located within the first opening 1031, it can be ensured that after the third section 1053 is subsequently etched, part of the passivation layer covers the metal layer 103, thereby preventing a short circuit caused by the connection between the metal layer 103 and the LED unit 104 when the electrode layer is subsequently deposited.
  • the third opening 10511 and the second opening 1021 can be formed by a photolithography process.
  • a conductive layer 106 is formed in the third opening 10511, in the second opening 1021, and on a portion of the second passivation layer 105.
  • the conductive layer 106 connects the second doped semiconductor layer 1043 to the contact 1011.
  • the driving substrate 101 can control the voltage and current of the second doped semiconductor layer 1043 through the contact 1011. At this time, the conductive layer 106 is separated by the passivation layer 105 to avoid direct contact with the metal layer 103.
  • the preparation process of the present application sets a first passivation layer 102, so that the contact 1011 and the metal layer 103 are separated, so that a certain distance is formed between the contact 1011 and the metal layer 103, thereby reducing the probability of the contact 1011 directly contacting the metal layer 103. Even if the problem of small opening size or hole position deviation is encountered in the preparation process, it will not cause a short circuit of the contact 1011, and it is achieved that there is no need to expand the size of the opening for exposing the contact 1011 to avoid the short circuit problem.
  • the present application does not need to expand the size of the first opening, does not sacrifice the size of the LED unit, and improves the light-emitting area and display effect of the micro-display device.

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Abstract

公布一种微显示器件及制备方法，微显示器件包括驱动基板，驱动基板包括多个触点；位于驱动基板上的第一钝化层，第一钝化层上设置有暴露触点的第二开孔；位于第一钝化层上的金属层，金属层上设置有对应第二开孔的第一开孔；阵列排布在金属层上的多个LED单元；导电层，导电层通过第二开孔以及第一开孔将触点与对应的LED单元电性连接。本申请通过设置的第一钝化层，使触点与金属层之间形成了电性隔离，防止触点直接与金属层接触，即便在制备过程中遇到第一开孔尺寸过小或位置偏差的问题时，也不会造成触点与金属层之间的短路，不用扩大第一开孔尺寸，不用牺牲LED单元尺寸，提升了微显示器件发光区面积与显示效果。

Description

微显示器件及制备方法
本申请要求于2022年11月16日提交中国专利局、申请号为CN202211436959.0、申请名称为“微显示器件及制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及Micro-LED制造技术领域，具体涉及一种微显示器件及制备方法。
 背景技术
微显示器件又称微型发光二极管，是一类通过将LED结构进行薄膜化、微小化后得到的高密度集成的LED阵列，因每个独立的LED单元都能自发光，极大地提高了光电转化效率，可以实现低能量或高亮度的显示器件设计。当制造微显示器件时，为了产生多个完全电隔离的LED单元，通常需要暴露触点以实现LED单元与驱动基板的电性连接，但在电性连接过程中容易导致触点短路，从而直接影响微显示器件的显示效果。
 技术问题
提供一种微显示器件及制备方法，通过设置钝化层以避免触点短路。
 技术解决方案
第一方面，提供一种微显示器件，包括：
驱动基板，所述驱动基板包括多个触点；
第一钝化层，所述第一钝化层位于所述驱动基板上，所述第一钝化层上设置与所述触点所在位置对应的第二开孔，所述第二开孔使所述第一钝化层暴露所述触点；
金属层，所述金属层位于所述第一钝化层上，所述金属层上设置与所述第二开孔所在位置对应的第一开孔，所述第一开孔使所述金属层暴露所述触点；
多个LED单元，所述LED单元位于所述金属层上且阵列排布，所述LED单元的第一电极层与所述金属层电性连接，所述触点位于相邻的所述LED单元之间；
导电层，所述导电层通过所述第二开孔以及所述第一开孔将所述触点与对应的所述LED单元的第二电极层电性连接，使得所述LED单元通过所述触点单独被驱动。
在一些实施例中，所述第一电极层为第一掺杂型半导体层、所述第二电极层为第二掺杂型半导体层，所述LED单元还包括位于所述第一掺杂型半导体层以及所述第二掺杂型半导体层之间的有源层；所述相邻的LED单元的第二掺杂型半导体层相互电隔离；所述触点与对应的所述LED单元的第二掺杂型半导体层电性连接。
在一些实施例中，包括第二钝化层，所述第二钝化层位于所述LED单元上；
所述第二钝化层具有暴露所述第二掺杂型半导体层的第三开孔，通过对所述第二钝化层和所述第一钝化层刻蚀以形成所述第二开孔；
所述导电层位于所述第二钝化层上，所述导电层通过所述第三开孔和所述第二开孔将所述第二掺杂型半导体层与所述触点电性连接。
在一些实施例中，所述第一钝化层的材质为SiN、SiO 2、Al 2O 3、TiO 2中的至少一种或多种；所述金属层的材质为Cr、Ti、Au、Ni、Al、Pt、Sn、In、Cu中的至少一种或多种。通过采用上述的第一钝化层和金属层，可以防止触点与金属层短路。
在一些实施例中，所述第二开孔的直径小于所述第一开孔的直径。
在一些实施例中，所述驱动基板是硅基CMOS驱动板或薄膜场效应管驱动板。
在一些实施例中，所述第一钝化层的材质与所述第二钝化层的材质相同，通过设置相同的材质，可以方便采用一步工艺直接对第一钝化层和第二钝化层进行开孔。
在一些实施例中，所述LED单元的尺寸为0.1~5微米。
在一些实施例中，所述第一钝化层的材质为SiO 2、Al 2O 3、SiN中的至少一种或多种。
第二方面，本申请实施例还提供一种微显示器件的制备方法，包括：
提供驱动基板，所述驱动基板包括多个触点；
形成第一钝化层，所述第一钝化层位于所述驱动基板上；
形成金属层，所述金属层位于所述第一钝化层上；
提供LED单元，所述LED单元阵列排布于所述金属层上，所述LED单元的第一电极层与所述金属层电性连接，所述触点位于相邻的所述LED单元之间；
在所述金属层对应所述触点的位置设置第一开孔以暴露所述第一钝化层；
在所述第一钝化层对应所述触点的位置设置第二开孔以暴露所述触点；
形成导电层，所述导电层通过所述第二开孔以及所述第一开孔将所述触点与对应的所述LED单元的第二电极层电性连接，使得所述LED单元通过所述触点单独被驱动。
在一些实施例中，所述第一电极层为第一掺杂型半导体层、所述第二电极层为第二掺杂型半导体层，所述LED单元还包括位于所述第一掺杂型半导体层以及所述第二掺杂型半导体层之间的有源层；所述相邻的LED单元的第二掺杂型半导体层相互电隔离；所述触点与对应的所述LED单元的第二掺杂型半导体层电性连接。
在一些实施例中，在提供LED单元的步骤之前，还包括：
提供衬底，所述衬底上设置有LED外延层；
在所述LED外延层上形成所述金属层；
在所述第一钝化层上形成所述金属层，将所述衬底和所述驱动基板键合，以使所述LED外延层位于所述第一钝化层上。
在一些实施例中，所述提供LED单元的步骤包括：
对所述LED外延层进行刻蚀形成所述LED单元；或者，
对所述LED外延层进行离子注入形成所述LED单元。
在一些实施例中，在设置所述第二开孔以暴露所述触点之前，还包括：
形成第二钝化层，所述第二钝化层位于所述LED单元上；所述第二钝化层具有暴露所述第二掺杂型半导体层的第三开孔，通过对所述第二钝化层和所述第一钝化层刻蚀以形成所述第二开孔；所述电极层位于所述第二钝化层上；所述电极层通过所述第三开孔和所述第二开孔将所述第二掺杂型半导体层与所述触点电性连接。
在一些实施例中，所述第一钝化层通过CVD方式形成于所述驱动基板上。
在一些实施例中，所述第一钝化层通过PVD方式形成于所述驱动基板上。
在一些实施例中，第一钝化层位于金属层和驱动基板之间，使驱动基板上的触点与金属层之间产生隔离，避免了触点之间的短路；金属层用于LED单元与驱动基板的键合，键合方式包括粘合剂键合、金属到金属键合、金属氧化物键合、晶圆到晶圆键合等。
在一些实施例中，有源层具体可以为多量子阱结构，用于限制电子和空穴载流子到量子阱区域，当电子和空穴发生复合后，载流子发生辐射复合后将发射出光子，把电能转化为光能。
在一些实施例中，所述第一掺杂型半导体层和第二掺杂型半导体层可以包括基于II-VI材料诸如ZnSe或ZnO或III-V材料诸如GaN、AlN、InN、InGaN、GaP、AlInGaP、AlGaAs及其合金的一个或多个层。
在一些实施例中，LED单元可以为台阶结构，所述台阶结构还使相邻的LED单元的第一掺杂型半导体层相互断开且电隔离；通过刻蚀所述金属层使相邻所述LED单元之间的所述金属层彼此断开并形成所述第一开孔。
在一些实施例中，第二钝化层用于对LED单元进行保护和绝缘。
在一些实施例中，导电层用于连接LED单元和驱动基板，并实现单独驱动的功能。
在一些实施例中，所述刻蚀包括干法刻蚀或湿法刻蚀。
在一些实施例中，所述LED单元为微型发光二极管，所述LED单元呈阵列排布；第一钝化层和金属层分别与LED单元一一对应，保证每个LED单元与触点不会发生短路。
在一些实施例中，所述第二钝化层包括位于所述LED单元上的第一段、位于所述金属层上的第二段和位于所述第一钝化层上的第三段；所述第二段与所述第一段一体连接，所述第三段与所述第二段一体连接，所述第三段位于所述第二段远离所述第一段的一侧；其中，所述第一段覆盖所述第一掺杂型半导体层和所述第二掺杂型半导体层。
在一些实施例中，所述LED单元的尺寸为0.1~5微米。LED单元呈周期性排布，相邻所述像素点的间距为1~10微米。
 有益效果
本申请的微显示器件，通过设置的第一钝化层，使触点与金属层之间形成了电性隔离，防止触点直接与金属层接触，即便在制备过程中遇到第一开孔尺寸过小或位置偏差的问题时，也不会造成触点与金属层之间的短路，本发明不用扩大第一开孔尺寸，不用牺牲LED单元尺寸，提升了微显示器件发光区面积与显示效果。
本申请的方法通过设置第一钝化层，使得触点与金属层被隔断，触点与金属层之间形成了一定的距离，减少了触点直接与金属层接触的几率，即便在制备过程中遇到开孔尺寸小或开孔位置偏移的问题时，也不会造成触点的短路。
 附图说明
图1是本申请的一些实施例的微显示器件的截面示意图；
图2是图1中G处的局部放大示意图；
图3是本申请的一些实施例的LED外延层结构示意图；
图4是本申请的一些实施例的驱动基板的结构示意图；
图5是本申请的一些实施例形成金属层后的结构示意图；
图6是本申请的一些实施例形成第一钝化层后的结构示意图；
图7是本申请的一些实施例的LED外延层与驱动基板键合后的结构示意图；
图8是本申请的一些实施例的移除LED外延层上衬底后的结构示意图；
图9是本申请的一些实施例形成LED单元后的结构示意图；
图10是本申请的一些实施例的在金属层上形成第一开孔后的结构示意图；
图11是本申请的一些实施例形成第二钝化层后的结构示意图；
图12是本申请的一些实施例的第二钝化层的结构示意图；
图13是本申请的一些实施例形成第三开孔后的结构示意图；
图14是本申请的一些实施例形成电极层后的结构示意图；
图15为现有制备工艺中开孔过小与触点位置偏差的结构示意图；
图16为现有制备工艺中开孔尺寸大导致LED单元尺寸小的结构示意图；
图中的标号分别为：100-微显示器件、101-驱动基板、102-第一钝化层、103-金属层、104-LED单元、105-第二钝化层、106-导电层、110-LED外延层、111-衬底、1011-触点、1021-第二开孔、1031-第一开孔、1041-第一掺杂型半导体层、1042-有源层、1043-第二掺杂型半导体层、1051-第一段、1052-第二段、1053-第三段、10511-第三开孔。
本申请的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的公开提供了许多不同的实施例或例子用来实现本申请的不同结构。为了简化本申请的公开，本申请中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
通常，可以至少部分地根据上本申请的用法来理解术语。例如，本申请所使用的术语“一个或多个”至少部分地取决于上本申请，可以用于以单数形式描述任何部件、结构或特征，或者可用于以复数形式描述部件、结构或特征的组合。类似地，诸如“一”、“一个”或“该”的术语也可以至少部分地取决于上本申请理解为传达单数用法或传达复数用法。另外，术语“基于…”可以理解为不一定旨在传达一组排他的因素，而是至少部分地取决于上本申请可以代替地允许存在不一定必须明确描述的附加因素。
应容易理解，本申请中的“在…上”、“在…之上”和“在…上面”的含义应该以最广义的方式解释，使得“在…上”不仅意味着“直接在某物上”，而且还意味着包括存在两者之间的中间部件或层的“在某物上”，并且“在某物之上”或“在某物上面”不仅意味着“在某物之上”或“在某物上面”的含义，而且也包括不存在两者之间的中间部件或层的“在某物之上”或“在某物上面”的含义。
此外，为了便于描述，本申请中可能使用诸如“在…下面”、“在…之下”、“下部”、“在…之上”、“上部”等空间相对术语来描述一个元件或部件与附图中所示的另一元件或部件的关系。除了在图中描述的方位之外，空间相对术语还意图涵盖装置在使用或操作中的不同方位。设备可以以其他方式定向旋转90°或以其他定向，并且在本申请中使用的空间相对描述语可以被同样地相应地解释。
本申请中所使用的术语“层”是指包括具有一定厚度的区域的材料部分。层可以在整个下层或上层结构上延伸，或者可以具有小于下层或上层结构的范围的程度。此外，层可以是均质或不均质连续结构的区域，其厚度小于连续结构的厚度。例如，层可以位于连续结构的顶表面和底表面之间或在其之间的任何一对水平平面之间。层可以水平地、垂直地和/或沿着锥形表面延伸。基板可以是一层，可以在其中包括一个或多个层，和/或可以在其上、之上和/或之下具有一个或多个层。一层可以包括多层。例如，半导体层可以包括一个或多个掺杂或未掺杂的半导体层，并且可以具有相同或不同的材料。
申请人发现，在制备微显示器件中需要在金属层103上开孔以暴露触点1011来用于电性连接，但常规的刻蚀工艺无法保证开孔的位置与触点1011完全对应，有时会造成开孔位置偏差，如图15所示，从而导致触点1011与金属层103接触而造成短路；因此，在刻蚀中需要有较大的开孔防止开孔位置的偏差导致触点1011之间的相互短路，如图16所示，但较大的开孔势必为影响LED单元104的尺寸，LED单元104尺寸较小将直接降低显示效果。
因此，需要设计一种新的微器件结构以及提供微器件结构的制备方法来避免上述的问题。
本申请中“上”、“下”位置关系分别与附图1中的上、下方对应，附图1中上方为出光方向，LED单元104的上表面为出光面，与出光面相邻的是侧面，这里的侧面为非出光侧。
本申请中使用的术语驱动基板101是指在其上添加后续材料层的材料。驱动基板101本身可以被图案化。添加到驱动基板101顶部的材料可以被图案化或可以保持未图案化。此外，驱动基板101可以包括各种各样的半导体材料，诸如硅、碳化硅、氮化镓、锗、砷化镓、磷化铟等。可替选地，驱动基板101可以由非导电材料制成，诸如玻璃、塑料或蓝宝石晶片。进一步可替选地，基板可以具有在其中形成的半导体装置或电路。驱动基板101例如可以是但不限于包括CMOS（Complementary Metal Oxide Semiconductor），互补金属氧化物半导体背板或TFT玻璃基板的显示基板。然后，LED外延层110在驱动基板101上形成LED单元104。在一些实施例中，功能外延层被部分地图案化/蚀刻，并且允许保留薄的连续功能层和金属层103以避免潜在的功能性像素剥离。另外，本申请中的制造方法可以进一步减少功能性像素的侧壁物理损伤，减少作为LED单元104的发光区域的量子阱结构的损坏，并改善功能性像素的光学和电学性质。
本申请中使用的微显示器件中，“微”是指根据本申请的实施例的某些装置或结构的描述性尺寸。本文中使用的术语“微显示器件”旨在表示100纳米至100微米的规模。然而，应明白，本申请的实施例不一定限于此，并且实施例的某些方面可以适用于更大的以及可能更小的尺寸规模。
本申请的微显示器件使用Micro-LED（Micro light-emitting diode，微型发光二极管结构），微型发光二极管的尺寸缩小到100纳米至100微米。在Micro-LED中，Micro-LED阵列高度集成，阵列中的Micro-LED的LED单元的距离进一步缩小至5微米量级。Micro-LED的显示方式是将5微米尺寸甚至更小尺寸的Micro-LED连接到驱动面板上，实现对每个Micro-LED放光亮度的精确控制。在一些实施例中，本申请中的LED单元104的结构可以是共阴极的或者共阳极的或者各自独立的结构。
图1示出了一些实施例的微显示器件的截面示意图，图2示出了LED单元104的局部放大示意图。微显示器件包括驱动基板101和位于驱动基板101上的多个LED单元104，驱动基板101上设置有多个触点1011；LED单元104与驱动基板101之间设置有第一钝化层102，第一钝化层102位于驱动基板101上并与驱动基板101连接，第一钝化层102上设置与触点1011所在位置对应的第二开孔1021，第二开孔1021使第一钝化层102断开并暴露触点1011；在第一钝化层102与LED单元104之间设置有金属层103，金属层103位于第一钝化层102上并与第一钝化层102连接，金属层103上设置与第二开孔1021所在位置对应的第一开孔1031，第一开孔1031使金属层103断开并与第一钝化层102一一对应；LED单元104位于金属层103上且阵列排布，触点1011位于相邻的LED单元104之间，触点1011通过第二开孔1021与对应的LED单元104电性连接，使得LED单元104通过触点1011单独被驱动。
在一些实施例中，多个LED单元104具体是指至少两个以上的LED单元104。
参见图2，在一些实施例中，LED单元104具有第一电极层和第二电极层，第一电极层为第一掺杂型半导体层1041，第二电极层第二掺杂型半导体层1043，第一掺杂型半导体层1041位于金属层103上，第二掺杂型半导体层1043位于第一掺杂型半导体层1041上；通过将第二掺杂型半导体层1043进行图案化，或者对第二掺杂型半导体层1043进行刻蚀形成台面结构，或者对第二掺杂型半导体层1043进行离子注入，形成LED单元104。每个LED单元104的第一掺杂型半导体层1041和第二掺杂型半导体层1043之间形成有源层1042，有源层1042为多量子阱层MQW，电子和空穴在量子阱区域复合产生光子，实现发光。
在一些实施例中，相邻LED单元104之间的第一掺杂型半导体层1041可以是一体连接的，此时第一掺杂型半导体层1041为阳极，第二掺杂型半导体层1043为阴极，采用共阳极结构，即第一掺杂型半导体层1041为连续的功能层结构，第一掺杂型半导体层1041跨多个LED单元104延伸并形成这些LED单元104的公共阳极，将第二掺杂型半导体层1043部分进行图案化或者对第二掺杂型半导体层1043进行刻蚀形成台阶，不同LED单元104的第二掺杂型半导体层1043之间电隔离，因而每个LED单元104都可以具有与其他单元不同的电压水平的阴极。当然，相邻LED单元104之间的第一掺杂型半导体层1041也可以是断开的，使微显示器件采用共阴极结构。
在一些实施例中，第一掺杂型半导体层1041和第二掺杂型半导体层1043可以包括基于II-VI材料（诸如ZnSe或ZnO）或III-V材料（诸如GaN、AlN、InN、InGaN、GaP、AlInGaP、AlGaAs及其合金）中的一个或多个。第一掺杂型半导体层1041优选为P型氮化镓，第二掺杂型半导体层1043优选为N型氮化镓。
在一些实施例中，第一钝化层102位于驱动基板101与金属层103之间，使驱动基板101上得触点1011与金属层103被隔开，避免了开孔位置偏移导致的触点1011与金属层103的短路；第一钝化层102可以包括SiO 2、A1 2O 3、SiN或其它合适的材料。
在一些实施例中，金属层103是用于键合驱动基板101和LED单元104的粘合材料层。金属层103可以包括导电材料，诸如金属或金属合金。在一些实施例中，金属层103可以包括Au、Sn、In、Cu或Ti。
在一些实施例中，在LED单元104上还设置有第二钝化层105，参见图12，第二钝化层105用于保护和LED单元104。第二钝化层105包括第一段1051、第二段1052和第三段1053，第一段1051位于LED单元104上，覆盖第一掺杂型半导体层1041和第二掺杂型半导体层1043，第二段1052位于金属层103上，第三段1053位于第一钝化层102上，第一段1051、第二段1052和第三段1053一体连接形成第二钝化层105，第二段1052与第一段1051一体连接，第三段1053与第二段1052一体连接，第三段1053位于第二段1052远离第一段1051的一侧。第二钝化层105可以包括SiO 2、A1 2O 3、SiN或其它合适的材料。第二钝化层105还包括聚酰亚胺、SU-8光刻胶或其他可光图案化的聚合物。第二钝化层105和第一钝化层102的材质可以是相同的，以方便通过一步工艺直接成孔。
在一些实施例中，在第二钝化层105上还设有导电层106，在第一段1051设置第三开孔10511以暴露第二掺杂型半导体层1043，同时通过直接对第三段1053刻蚀形成第二开孔1021以暴露触点；导电层106通过第三开孔10511和第二开孔1021将第二掺杂型半导体层1043与触点1011电性连接，LED单元104为微型发光二极管，每个LED单元104都被不同的驱动电路独立驱动，每个LED单元104可独立工作。在一些实施例中，第三开孔10511位于每个LED单元104的出光面的中心处，并且第二开孔1021位于相邻LED单元104的间隙处，且触点1011位于第二开孔1021的中心处。导电层106采用导电材料，诸如铟锡氧化物ITO、Cr、Ti、Pt、Au、A1、Cu、Ge或Ni。
在一些实施例中，第一钝化层102的材质为SiN、SiO 2、Al 2O 3、TiO 2中的至少一种或多种；金属层103的材质为Cr、Ti、Au、Ni、Al、Pt、Sn、In、Cu中的至少一种或多种。通过采用上述的第一钝化层102和金属层103，可以防止触点1011与金属层103短路。
在一些实施例中，第二开孔1021的直径小于第一开孔1031的直径，由于第二开孔1021的直径小于第一开孔1031的直径，因此在形成第二钝化层105后，可以直接同时对第二钝化层105和第一钝化层102进行刻蚀，形成第二开孔1021，使第二开孔1021位于第一开孔1031内，实现对钝化层的一步刻蚀，以大幅简化制备工艺。当然，在一些其它的工艺中，也可以先对第一钝化层102进行刻蚀成孔，再对第二钝化层105进行刻蚀成孔，只要满足所成的孔位于第一开孔1031内即可，这样可以保证第二钝化层105的一部分包覆金属层103，防止其短路。
在一些实施例中，LED单元104的尺寸为0.1~10微米。
图3至图14示出了微显示器件结构制备过程中不同阶段的截面图。
参见图3和图4，分别给出了LED外延层110和驱动基板101的结构示意图，了LED外延层110上设有衬底111，驱动基板101上设置有触点1011。提供驱动基板101，在驱动基板101中形成驱动电路，并且驱动电路包括触点1011；再提供衬底111，在衬底111上形成LED外延层110，并且该LED外延层110包括第一掺杂型半导体层1041、第二掺杂型半导体层1043和有源层1042。
在一些实施例中，驱动基板101是硅基CMOS背板或薄膜场效应管。硅基CMOS以硅为材料的芯片，在一些实施例中，衬底111是半导体材料，如硅、氮化镓等，或者衬底111是非导电材料，如蓝宝石或玻璃。在一些实施例中，第一掺杂型半导体层1041为P型氮化镓，第二掺杂型半导体层1043为N型氮化镓。
参见图5，在LED外延层110上形成金属层103，金属层103可以包括导电材料，诸如金属或金属合金。在一些实施例中，金属层103可以包括Cr、Ti、Au、Ni、Al、Pt、Sn、In、Cu。在一些实施例中，金属层103通过沉积、电镀等方式制备。
参见图6，在驱动基板101上形成第一钝化层102，第一钝化层102通过CVD或PVD方式形成于所述驱动基板101上。第一钝化层102可以包括SiN、SiO 2、Al 2O 3、TiO 2或其它合适的材料。同时，为了实现金属层103位于第一钝化层102上，还需要进一步在第一钝化层102上设置金属层103，金属层103可以为金属材质，通过金属与金属的键合使得第一钝化层102上的金属层103与LED外延层110上的金属层103连接。
参见图7，将衬底111上的LED外延层110翻转，将第一钝化层102上的金属层103与LED外延层110上的金属层103对准，金属层103和金属层103通过金属键融合成一层结构，实现LED外延层110与驱动基板101的键合，此时金属层103位于第一钝化层102上。进一步参见图7，本申请由于设置了第一钝化层102，可以防止金属与金属键合时因温度过高而对底部的驱动基板101造成的影响，这是因为金属键合时温度过高，当温度冷却后会使得驱动基板101产生翘曲，但引入第一钝化层102后可以防止驱动基板101的翘曲，以达到提升键合，保护基板的效果。
参见图8，移除衬底111并对LED外延层110进行减薄，衬底111移除方法包括但不限于激光剥离、干法刻蚀、湿法刻蚀、机械抛光等；减薄操作包括干法刻蚀、湿法刻蚀或者机械抛光。
参见图9，照图形化掩膜设计MESA图形，去除第二掺杂型半导体层1043和第一掺杂型半导体层1041，形成功能化的台阶结构，得到LED单元104，LED单元104呈阵列分布。其中，去除方式包括干法刻蚀或湿法刻蚀。
参见图10，在金属层103上设置第一开孔1031，以暴露出第一钝化层102，第一开孔1031的位置与触点1011的位置对应；设置开孔的方式为刻蚀，刻蚀方法包括离子束刻蚀等。
参见图11和图12，在LED单元104上的整面设置第二钝化层105，第二钝化层105包括位于LED单元104上得第一段1051、位于金属层103上的第二段1052和位于第一钝化层102上的第三段1053；第一段1051、第二段1052和第三段1053依次连接形成整体。第二钝化层105可以对LED单元104进行保护。第二钝化层105通过化学气相沉积形成。其中，第一段1051覆盖第一掺杂型半导体层1041和第二掺杂型半导体层1043；第三段1053位于第一开孔1031内并覆盖第一钝化层102。
参见图13，在第一段1051上设置第三开孔10511以暴露出第二掺杂型半导体层1043，同时刻蚀第三段1053和位于第三段1053下的第一钝化层102形成第二开孔1021，并暴露出触点1011。由于控制第三段1053是位于第一开孔1031内的，可以保证后续对第三段1053刻蚀后，有部分的钝化层将金属层103包覆，防止后续沉积电极层时金属层103与LED单元104连接而造成的短路。第三开孔10511和第二开孔1021可以通过光刻过程形成。
参见图14，在第三开孔10511内、第二开孔1021内以及部分第二钝化层105上形成导电层106，导电层106将第二掺杂型半导体层1043与触点1011连接，驱动基板101可以通过触点1011来控制第二掺杂型半导体层1043的电压和电流。此时，导电层106被钝化层105隔开，避免了与金属层103直接接触。
本申请的制备工艺，设置第一钝化层102，使得触点1011与金属层103被隔断，使触点1011与金属层103之间形成了一定的距离，减少了触点1011直接与金属层103接触的几率，即便在制备过程中遇到开孔尺寸小或开孔位置偏差的问题时，也不会造成触点1011的短路，实现了不用扩大用于暴露触点1011的开孔的尺寸来避免短路问题，本申请不用扩大第一开孔尺寸，不用牺牲LED单元尺寸，提升了微显示器件发光区面积与显示效果。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请进行了详细介绍，本申请中应用了具体个例对本申请的原理及实施例进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (15)

  1. 一种微显示器件，包括：
    驱动基板（101），所述驱动基板（101）包括多个触点（1011）；
    第一钝化层（102），位于所述驱动基板（101）上，所述第一钝化层（102）上设置有与所述触点（1011）所在位置对应的第二开孔（1021），所述第二开孔（1021）暴露所述触点（1011）；
    金属层（103），位于所述第一钝化层（102）上，所述金属层（103）上设置有与所述第二开孔（1021）所在位置对应的第一开孔（1031），所述第一开孔（1031）暴露所述触点（1011）；
    多个LED单元（104），位于所述金属层（103）上且阵列排布，所述LED单元（104）的第一电极层与所述金属层（103）电性连接，所述触点（1011）位于相邻的所述LED单元（104）之间；
    导电层（106），通过所述第二开孔（1021）以及所述第一开孔（1031）将所述触点（1011）与对应的所述LED单元（104）的第二电极层电性连接，使得所述LED单元（104）通过所述触点（1011）单独被驱动。
  2. 根据权利要求1所述的微显示器件，其中，所述第一电极层为第一掺杂型半导体层（1041）、所述第二电极层为第二掺杂型半导体层（1043），所述LED单元（104）还包括位于所述第一掺杂型半导体层（1041）以及所述第二掺杂型半导体层（1043）之间的有源层（1042）；所述相邻的LED单元（104）的第二掺杂型半导体层（1043）相互电隔离；所述触点（1011）与对应的所述LED单元的第二掺杂型半导体层（1043）电性连接。
  3. 根据权利要求2所述的微显示器件，包括：
    第二钝化层（105），位于所述LED单元（104）上；所述第二钝化层（105）具有暴露所述第二掺杂型半导体层（1043）的第三开孔（10511），通过对所述第二钝化层（105）和所述第一钝化层（102）刻蚀以形成所述第二开孔（1021）；
    所述导电层（106）位于所述第二钝化层（105）上；所述导电层（106）通过所述第三开孔（10511）将所述第二掺杂型半导体层（1043）与所述触点（1011）电性连接。
  4. 根据权利要求1所述的微显示器件，其中，所述第一钝化层（102）的材质为SiN、SiO 2 、Al 2 O 3 、TiO 2 中的至少一种或多种；所述金属层（103）的材质为Cr、Ti、Au、Ni、Al、Pt、Sn、In、Cu中的至少一种或多种。
  5. 根据权利要求1所述的微显示器件，其中，所述第一钝化层（102）上的第二开孔（1021）的直径小于所述金属层（103）上第一开孔（1031）的直径。
  6. 根据权利要求3所述的微显示器件，其中，所述第一钝化层（102）的材质与所述第二钝化层（105）的材质相同。
  7. 根据权利要求1所述的微显示器件，其中，所述LED单元（104）的尺寸为0.1~10微米。
  8. 一种微显示器件的制备方法，包括：
    提供驱动基板（101），所述驱动基板（101）包括多个触点（1011）；
    在所述驱动基板（101）上形成第一钝化层（102）；
    形成金属层（103），位于所述第一钝化层（102）上；
    提供多个LED单元（104），阵列排布于所述金属层（103）上，所述LED单元（104）的第一电极层与所述金属层（103）电性连接，所述触点（1011）位于相邻的所述LED单元（104）之间；
    在所述金属层（103）对应所述触点（1011）的位置设置第一开孔（1031）以暴露所述第一钝化层（102）；
    在所述第一钝化层（102）对应所述触点（1011）的位置设置第二开孔（1021）以暴露所述触点（1011）；
    形成导电层（106），所述导电层（106）通过所述第二开孔（1021）以及所述第一开孔（1031）将所述触点（1011）与对应的所述LED单元（104）的第二电极层电性连接，使得所述LED单元（104）通过所述触点（1011）单独被驱动。
  9. 根据权利要求8所述的微显示器件的制备方法，其中，所述第一电极层为第一掺杂型半导体层（1041）、所述第二电极层为第二掺杂型半导体层（1043），所述LED单元（104）还包括位于所述第一掺杂型半导体层（1041）以及所述第二掺杂型半导体层（1043）之间的有源层（1042）；所述相邻的LED单元（104）的第二掺杂型半导体层（1043）相互电隔离；所述触点（1011）与对应的所述LED单元的第二掺杂型半导体层（1043）电性连接。
  10. 根据权利要求8所述的微显示器件的制备方法，其中，在提供LED单元（104）的步骤之前，还包括：
    提供衬底（111），所述衬底（111）上设置有LED外延层（110）；
    在所述LED外延层（110）上形成所述金属层（103）；
    在所述第一钝化层（102）上形成所述金属层（103），将所述衬底（111）和所述驱动基板（101）键合，以使所述LED外延层（110）位于所述第一钝化层（102）上。
  11. 根据权利要求10所述的微显示器件的制备方法，其中，所述提供LED单元（104）的步骤包括：
    对所述LED外延层（110）进行刻蚀形成所述LED单元（104）。
  12. 根据权利要求10所述的微显示器件的制备方法，其中，所述提供LED单元（104）的步骤包括：
    对所述LED外延层（110）进行离子注入形成所述LED单元（104）。
  13. 根据权利要求9所述的微显示器件的制备方法，其中，在设置所述第二开孔（1021）以暴露所述触点（1011）之前，还包括：
    在所述LED单元（104）上形成第二钝化层（105）；所述第二钝化层（105）具有暴露所述第二掺杂型半导体层（1043）的第三开孔（10511）；通过对所述第二钝化层（105）和所述第一钝化层（102）刻蚀以形成所述第二开孔（1021）；所述导电层（106）位于所述第二钝化层（105）上；所述导电层（106）通过所述第三开孔（10511）将所述第二掺杂型半导体层（1043）与所述触点（1011）电性连接。
  14. 根据权利要求8所述的微显示器件的制备方法，其中，所述第一钝化层（102）通过CVD方式形成于所述驱动基板（101）上。
  15. 根据权利要求8所述的微显示器件的制备方法，其中，所述第一钝化层（102）通过PVD方式形成于所述驱动基板（101）上。
PCT/CN2023/120972 2022-11-16 2023-09-25 微显示器件及制备方法 WO2024103962A1 (zh)

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