WO2024103720A1 - 一种数据传输方法、装置、电子设备及非易失性可读存储介质 - Google Patents

一种数据传输方法、装置、电子设备及非易失性可读存储介质 Download PDF

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Publication number
WO2024103720A1
WO2024103720A1 PCT/CN2023/101164 CN2023101164W WO2024103720A1 WO 2024103720 A1 WO2024103720 A1 WO 2024103720A1 CN 2023101164 W CN2023101164 W CN 2023101164W WO 2024103720 A1 WO2024103720 A1 WO 2024103720A1
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Prior art keywords
transmission
request
data block
target
data
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PCT/CN2023/101164
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English (en)
French (fr)
Inventor
李辉
李长飞
赵帅
刘清林
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浪潮电子信息产业股份有限公司
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Publication of WO2024103720A1 publication Critical patent/WO2024103720A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present application relates to the field of data transmission, and in particular to a data transmission method, device, electronic device and non-volatile readable storage medium.
  • the communication field of computer systems includes a high-speed communication method based on PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) link, which has developed from PCIE3.0 to PCIE5.0, and the communication capacity of the transmission link has been greatly improved.
  • PCIE peripheral component interconnect express, a high-speed serial computer expansion bus standard
  • the communication capacity of the transmission link has been greatly improved.
  • the data transmission performance of a single DMA (Direct Memory Access) engine has gradually reached a bottleneck.
  • DMA Direct Memory Access
  • the current way to accelerate the DMA engine is: manufacturers improve the hardware's DMA engine handling capacity during production to achieve acceleration of the DMA engine, but the hardware's DMA engine's handling capacity has little room for improvement and is very difficult to improve.
  • the purpose of the present application is to provide a data transmission method, device, electronic device and non-volatile readable storage medium, which divide the target data block and use multiple DMA engines to process the same target data block at the same time, thereby improving the processing speed of the target data block and improving the data transmission capability of the server.
  • the present application provides a data transmission method, the method comprising:
  • the transmission request includes a source address, a target address and a length of the target data block
  • the multiple sub-data blocks are distributed to the multiple DMA engines, so that each DMA engine transfers the sub-data block corresponding to itself to the target address, so as to complete the transmission of the target data block.
  • the transmission request when the transmission request includes multiple items, after receiving the transmission request, it also includes:
  • Each transfer request is processed in the order in which it is arranged.
  • multiple transmission requests are arranged in chronological order, including:
  • Each transfer request is processed in the order in which it is arranged, including:
  • Each transfer request is processed in the order in which it is written to the request queue.
  • the method further includes:
  • the process proceeds to the step of obtaining the next transmission request from the request queue.
  • the method further includes:
  • multiple transmission requests are sequentially written into a request queue in chronological order, and the request queue follows a first-in-first-out principle, including:
  • the application is used to write multiple transfer requests into the request queue in a time sequence in a single-threaded access manner, wherein the request queue is used to isolate the application and the DMA engine, and the application performs single-threaded access to the DMA engine through the request queue.
  • multiple transmission requests are sequentially written into the request queue in chronological order, including:
  • the request queue When the request queue is in a locked state, the request queue is determined to be in an access state, and the current transmission request is written into the request queue after waiting for a preset time until the request queue is in an idle state;
  • the request queue When the request queue is in an unlocked state, it is determined that the request queue is in an idle state, and the current transmission request is directly written into the request queue.
  • the method further includes:
  • the query is stopped, and when the transmission request corresponding to the first target address is written into the request queue, the transmission request corresponding to the first target address is written after the transmission request corresponding to the second target address with which there is an overlap, as the next transmission request of the transmission request corresponding to the second target address.
  • querying each transmission request in sequence from the tail end to the head end of the request queue, and determining whether the second target address corresponding to each transmission request overlaps with the first target address includes:
  • the second target address in the request queue is consistent with the first target address, it is determined that the second target address corresponding to each transmission request overlaps with the first target address; if the second target address in the request queue is not consistent with the first target address, it is determined that the second target address corresponding to each transmission request does not overlap with the first target address.
  • the method further includes:
  • the transmission request corresponding to the first target address is written to the head end of the request queue.
  • a preset DMA engine is used to transfer the target data block corresponding to the transfer request with the priority.
  • the method before using a preset DMA engine to transmit a target data block corresponding to a transmission request with a priority, the method further includes:
  • one or more DMA engines among the DMA engines currently allowed to be used are set as preset DMA engines.
  • the target data block is divided into a plurality of sub-data blocks according to the length of the target data block, including:
  • the data length of each sub-data block is not greater than the optimal data transmission length of the DMA engine.
  • the transmission efficiency of the DMA engine when transmitting a data block not greater than an optimal transmission data length is greater than a target transmission efficiency.
  • the target data block is divided into a plurality of sub-data blocks according to the target data block length and the optimal transmission data length of the DMA engine, including:
  • the target data block is evenly divided into a plurality of sub-data blocks with the same data block length.
  • distributing the multiple sub-data blocks to multiple DMA engines includes:
  • each DMA engine corresponds to more than one sub-data block, it also includes:
  • the DMA engine is controlled to sequentially transmit the sub-data blocks corresponding to itself.
  • the present application also provides a data transmission device, the device comprising:
  • a request receiving unit is configured to receive a transmission request, wherein the transmission request includes a source address, a target address and a length of a target data block;
  • a division unit is configured to obtain a target data block from a source address and divide the target data block into a plurality of sub-data blocks according to a length of the target data block;
  • the distribution unit is configured to distribute the plurality of sub-data blocks to the plurality of DMA engines, so that each DMA engine transfers the sub-data block corresponding to itself to the target address, so as to complete the transmission of the target data block.
  • the present application further provides an electronic device, including:
  • a memory arranged to store a computer program
  • the processor is configured to implement the steps of the data transmission method as described above when storing a computer program.
  • the present application also provides a non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the data transmission method as mentioned above are implemented.
  • the present application provides a data transmission method, which relates to the field of data transmission.
  • a transmission request is received, which includes the source address, target address and target data block length of the target data block; the target data block is obtained from the source address, and the target data block is divided into multiple sub-data blocks according to the length of the target data block; the multiple sub-data blocks are distributed to multiple DMA engines, so that each DMA engine transfers the sub-data block corresponding to itself to the target address to complete the transmission of the target data block.
  • the target data block is divided, and multiple DMA engines are used to perform the transmission of the same sub-data block at the same time.
  • the target data block is processed, which improves the processing speed of the target data block and improves the data transmission capacity of the server.
  • the present application also provides a data transmission device, apparatus and non-volatile readable storage medium, which have the same beneficial effects as the data transmission method described above.
  • FIG1 is a schematic diagram of a flow chart of a data transmission method provided by the present application.
  • FIG2 is a working principle diagram of a DMA engine provided by the present application.
  • FIG3 is a schematic diagram of a flow chart of another data transmission method provided by the present application.
  • FIG4 is a structural block diagram of a data transmission device provided by the present application.
  • FIG5 is a structural block diagram of an electronic device provided in the present application.
  • the core of this application is to provide a data transmission method, device, electronic device and non-volatile readable storage medium, which divide the target data block and use multiple DMA engines to process the same target data block at the same time, thereby improving the processing speed of the target data block and improving the server data transmission capability.
  • FIG. 1 is a flow chart of a data transmission method provided by the present application.
  • the method is applied to a server including multiple DMA engines, and the method includes:
  • S11 receiving a transmission request, the transmission request including a source address, a target address and a length of a target data block;
  • FIG. 2 is a working principle diagram of a DMA engine provided by this application.
  • the transfer request issued by the application includes the source address, destination address and data block size of data blocks 1, 2, 3 and 4, which are submitted to the DMA engine, and the DMA engine is started, so that the DMA engine transfers the four data blocks from the source address to the destination address in turn.
  • the address is moved to the corresponding target address.
  • S12 Obtain a target data block from the source address, and divide the target data block into a plurality of sub-data blocks according to the length of the target data block;
  • Figure 3 is a flow chart of another data transmission method provided by the present application. If the amount of data that needs to be transmitted in the server at a certain moment is large, the handling capacity of a single DMA engine may reach a bottleneck, and at this time, the data transmission cannot be completed.
  • the target data block corresponding to the transfer request is divided into multiple sub-data blocks of smaller lengths so that they can be distributed to multiple DMA engines to jointly complete the transmission of the target data block, thereby improving the efficiency of data transmission.
  • S13 Distribute the multiple sub-data blocks to the multiple DMA engines, so that each DMA engine transfers the sub-data block corresponding to itself to the target address, so as to complete the transmission of the target data block.
  • each DMA engine moves the sub-data block corresponding to itself from the source address to the target address, thereby realizing the transmission of the target data block.
  • the target data block is divided into a plurality of sub-data blocks according to the length of the target data block, including:
  • the data length of each sub-data block is not greater than the optimal data transmission length of the DMA engine.
  • each DMA engine corresponds to an optimal transmission data length for its own transmission.
  • the transmission efficiency of the DMA engine is higher when transmitting a data block that is not greater than the optimal transmission data length. Therefore, in this application, when dividing the target data block, the target data block is divided according to the target data block length and the optimal transmission data length of the DMA engine to divide it into multiple sub-data blocks, and ensure that the length of each sub-data block is not greater than the optimal transmission data length of the DMA engine to ensure the transmission efficiency of the DMA engine.
  • the target data block is divided into a plurality of sub-data blocks according to the target data block length and the optimal transmission data length of the DMA engine, including:
  • the target data block is evenly divided into a plurality of sub-data blocks with the same data block length.
  • this embodiment takes into account the load balancing principle.
  • the lengths of multiple sub-data blocks are set to the same length.
  • the length and size of the data blocks received by the DMA engine can be made the same to a certain extent, thereby achieving load balancing as much as possible and allowing multiple DMA engines to work synchronously as much as possible.
  • distributing multiple sub-data blocks to multiple DMA engines includes:
  • the sub-data blocks are evenly distributed to each DMA engine to ensure load balancing between each DMA engine, so that multiple DMA engines can work as synchronously as possible.
  • the method further includes:
  • the DMA engine is controlled to sequentially transmit the sub-data blocks corresponding to itself.
  • each DMA engine corresponds to more than one sub-data block, then, in order to ensure the correctness of the data in each target address, when each DMA engine in the present application processes the sub-data block corresponding to itself, it is necessary to ensure that each DMA processes each sub-data block in sequence.
  • the length (i.e., size) of a target data block is 16K
  • the number of DMA engines is 2
  • the optimal transmission data length corresponding to each DMA engine is 4K.
  • the target data block is divided, it is divided into 4 sub-data blocks with a data length of 4K, and then 2 sub-data blocks are allocated to each DMA engine.
  • Each DMA engine transmits the 2 sub-data blocks corresponding to itself in sequence, which can be: after transmitting the first sub-data block, the second sub-data block is transmitted.
  • the method further includes:
  • Each transfer request is processed in the order in which it is arranged.
  • the present application needs to arrange the transfer requests in chronological order, and process each transfer request in sequence according to the corresponding arrangement order, so as to ensure that the DMA engine only processes one transfer request at the same time, that is, there is only one write operation to the same target address at the same time, which can avoid the data in the target address from being damaged.
  • arranging the multiple transmission requests in chronological order includes:
  • Each transfer request is processed in the order in which it is arranged, including:
  • Each transfer request is processed in the order in which it is written to the request queue.
  • This embodiment aims to limit the optional implementation methods for arranging each transmission request.
  • a request queue is used in this application to arrange each transmission request, and multiple transmission requests are written into the request queue in chronological order. Since the request queue in this application follows the first-in-first-out principle, when obtaining each transmission request in the request queue, each transmission request can only be processed in chronological order (that is, the order in which it is written into the queue) from the request queue.
  • the method in this application can prevent the data in the target address from being damaged.
  • the method further includes:
  • the process proceeds to the step of obtaining the next transmission request from the request queue.
  • the DMA engine when the DMA engine transmits the target data block corresponding to the current transfer request, it will also determine whether the transmission of the current target data block is completed. When it is not completed, it means that the DMA engine is currently in the state of transmitting the target data block corresponding to the current transfer request; if the next transfer request is directly obtained from the request queue, the target address corresponding to the next transfer request may overlap with the target address corresponding to the current transfer request (that is, there are repeated addresses). At this time, the DMA engine may write data to the same address at the same time, which may cause the data corresponding to the overlapping address to be damaged.
  • the process of the application sending a transfer request is a process of a single thread accessing the DMA engine. If multiple threads access the DMA engine at the same time, there will be a competition problem caused by calling the DMA engine at the same time to move data.
  • a request queue is set between the application (i.e., thread) and the DMA engine.
  • This request queue can also realize isolation between the application and the DMA engine, so that the application cannot directly access the DMA engine and must access the DMA engine through the request queue.
  • This request queue can realize the sorting of various transfer requests, thereby avoiding the competition problem caused by multiple threads calling the DMA engine at the same time.
  • writing multiple transmission requests into the request queue in sequence according to the time sequence includes:
  • the request queue When the request queue is in a locked state, the request queue is determined to be in an access state, and the current transmission request is written into the request queue after waiting for a preset time until the request queue is in an idle state;
  • the request queue When the request queue is in an unlocked state, it is determined that the request queue is in an idle state, and the current transmission request is directly written into the request queue.
  • the request queue when writing a transmission request to a request queue, it is necessary to determine whether the request queue is in a locked state.
  • the request queue is in a locked state when it is accessed, and in an unlocked state when the request queue is not accessed.
  • the request queue is in an unlocked state, it is determined that the request queue is not currently being accessed, that is, the request queue is in an idle state, and the transmission request can be written directly to the request queue at this time, and there will be no overlap of target addresses.
  • the sequence between each transmission request can be guaranteed, and the overlapping target addresses can be read and written in sequence. That is, only one thread is accessing the request queue at the same time, that is, only one transmission request is allowed to be written to the request queue at the same time, which can avoid data errors corresponding to the overlapping parts of the target address.
  • the method further includes:
  • the query is stopped, and when the transmission request corresponding to the first target address is written into the request queue, the transmission request corresponding to the first target address is written after the transmission request corresponding to the second target address with which there is an overlap, as the next transmission request of the transmission request corresponding to the second target address.
  • the target data block when transmitting the target data block, there may be some target data blocks with higher priority (such as the target data block has a priority set in advance).
  • the target data block has a priority set in advance.
  • the target data block corresponding to the transmission request is determined to be a high-priority target data block.
  • the first target address corresponding to the transmission request is obtained, and then the first target address is compared with the second target address corresponding to each transmission request in the request queue (compared one by one from the tail end to the head end) to determine whether the second target address corresponding to the transmission request overlaps with the first target address.
  • the address of the overlapping part needs to be written at least twice, and has a sequence, that is, the transmission request corresponding to the second target address needs to be written once, and the transmission request corresponding to the first target address needs to be written once. Therefore, even if the priority of the transmission request corresponding to the first target address is higher, it cannot be higher than the transmission request corresponding to the second target address that overlaps with the first target address, otherwise it will cause data errors in the overlapping part of the target address. Therefore, when writing the transmission request corresponding to the first target address into the request queue, it can only be written after the transmission request corresponding to the second target address to ensure data security and avoid data damage.
  • the transmission request corresponding to the second target address in the present application is the first transmission request that overlaps with the first target address that is queried from the tail end to the head end of the request queue.
  • the query is stopped, because no matter whether the target address corresponding to the transmission request before this transmission request overlaps with the first target address, the transmission request corresponding to the second target address needs to write the overlapping address once.
  • stopping the query can also reduce the power consumption of the processor to a certain extent.
  • the method further includes:
  • the transmission request corresponding to the first target address is written to the head end of the request queue.
  • the transmission request corresponding to the first target address can be written to the head end of the request queue so that the transmission request can be processed earlier without causing data damage in each address.
  • the method when obtaining a transmission request from a request queue, the method further includes:
  • a preset DMA engine is used to transfer the target data block corresponding to the transfer request with the priority.
  • a separate preset DMA engine may be set for transmission requests with priorities, and the preset DMA engine is only responsible for transmitting transmission requests with priorities.
  • the preset DMA engine is used to process the transfer request with a priority, that is, the preset DMA engine is used to transmit the target data block corresponding to the transfer request with a priority.
  • the transmission request can be processed according to the above conventional steps.
  • the processing speed of the target data block can be improved, thereby improving the data transmission capability of the server.
  • FIG. 4 is a structural block diagram of a data transmission device provided by the present application.
  • the system device includes:
  • the request receiving unit 41 is configured to receive a transmission request, wherein the transmission request includes a source address, a target address and a length of a target data block;
  • the dividing unit 42 is configured to obtain a target data block from a source address and divide the target data block into a plurality of sub-data blocks according to the length of the target data block;
  • the distribution unit 43 is configured to distribute the multiple sub-data blocks to the multiple DMA engines, so that each DMA engine transfers the sub-data block corresponding to itself to the target address, so as to complete the transmission of the target data block.
  • it also includes:
  • an arranging unit configured to arrange the multiple transmission requests in a time sequence
  • the sequential processing unit is configured to process each transmission request in sequence according to the arrangement order.
  • the arranging unit may be configured to write the multiple transmission requests into the request queue in sequence according to the time sequence, and the request queue follows the first-in-first-out principle;
  • the sequential processing unit may be configured to process each transmission request in sequence according to the order in which the request queue is written.
  • it also includes:
  • the first judgment unit is configured to judge whether the multiple DMA engines have completed the transmission of the target data block; if the multiple DMA engines have completed the transmission of the target data block, the step of obtaining the next transmission request from the request queue is entered.
  • the sequential processing unit includes:
  • a second judgment unit is configured to judge whether the request queue is in a locked state when writing the current transmission request into the request queue
  • the first execution unit is configured to determine that the request queue is in an access state when in a locked state, and wait for a preset time until When the request queue is in an idle state, the current transmission request is written into the request queue;
  • the second execution unit is configured to determine that the request queue is in an idle state when in an unlocked state, and directly write the current transmission request into the request queue.
  • it also includes:
  • a third determination unit is configured to determine whether the transmission request has a priority
  • a third execution unit is configured to determine a first target address corresponding to the transmission request with a priority when the transmission request has a priority
  • a fourth determination unit configured to query each transmission request in sequence from the tail end to the head end of the request queue, and determine whether the second target address corresponding to each transmission request overlaps with the first target address
  • the fourth execution unit is configured to stop querying when it is determined that there is an overlap, and when writing the transfer request corresponding to the first target address into the request queue, write the transfer request corresponding to the first target address after the transfer request corresponding to the second target address where there is an overlap, as the next transfer request of the transfer request corresponding to the second target address.
  • it also includes:
  • the fifth execution unit is configured to write the transfer request corresponding to the first target address to the head end of the request queue when it is determined that there is no overlap.
  • the method when obtaining a transmission request from a request queue, the method further includes:
  • a fifth determination unit is configured to determine whether the acquired transmission request has a priority
  • the sixth execution unit is configured to use a preset DMA engine to transmit a target data block corresponding to the transmission request with a priority when the acquired transmission request has a priority.
  • the dividing unit may be configured to divide the target data block into a plurality of sub-data blocks according to the target data block length and the optimal transmission data length of the DMA engine;
  • the data length of each sub-data block is not greater than the optimal data transmission length of the DMA engine.
  • the dividing unit may be configured to evenly divide the target data block into a plurality of sub-data blocks with the same data block length according to the target data block length and the optimal transmission data length of the DMA engine.
  • the distribution unit may be configured to evenly distribute the multiple sub-data blocks to the multiple DMA engines.
  • it also includes:
  • the control unit is configured to control the DMA engines to sequentially transmit the sub-data blocks corresponding to themselves when each DMA engine corresponds to more than one sub-data block.
  • FIG5 is a structural block diagram of an electronic device provided by the present application.
  • the device includes:
  • a memory 51 configured to store computer programs
  • the processor 52 is configured to implement the steps of the above-mentioned data transmission method when storing the computer program.
  • the present application also provides a non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above data transmission method are implemented.
  • the non-volatile readable storage medium can be a transient storage medium or a non-transient storage medium, which is not limited in the present application.
  • the non-volatile readable storage medium please refer to the above embodiment, and the present application will not repeat it here.

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Abstract

本申请公开了一种数据传输方法、装置、电子设备及非易失性可读存储介质，涉及数据传输领域。该方案中，接收传输请求，传输请求中包括目标数据块的源地址、目标地址及目标数据块长度；从源地址中获取目标数据块，并根据目标数据块长度将目标数据块划分为多个子数据块；将多个子数据块分发至多个DMA引擎，以使各个DMA引擎将与自身对应的子数据块传输至目标地址，以完成对目标数据块的传输。通过本申请中的方式，对目标数据块进行划分，并同时利用多个DMA引擎对同一目标数据块进行处理，提高了对目标数据块处理的速度，提高了服务器数据传输的能力。

Description

一种数据传输方法、装置、电子设备及非易失性可读存储介质
相关申请的交叉引用
本申请要求于2022年11月16日提交中国专利局，申请号为202211459291.1，申请名称为“一种数据传输方法、装置、电子设备及介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据传输领域，特别涉及一种数据传输方法、装置、电子设备及非易失性可读存储介质。
背景技术
计算机系统的通信领域包括一种基于PCIE(peripheral component interconnect express，高速串行计算机扩展总线标准)链路的高速通信方式，其已经从PCIE3.0发展到了PCIE5.0，传输链路的通信能力得到的极大的提高。随着通道性能的提升，单个DMA(Direct Memory Access，直接存储器访问)引擎的数据传输性能逐渐达到瓶颈。此时，若想要达到较好的链路通信能力，需要对DMA引擎进行加速。目前对DMA引擎进行加速的方式为：厂商在生产时提升硬件的DMA引擎搬运能力，以实现对DMA引擎的加速，但是硬件的DMA引擎的搬运能力的提升空间很小且提升难度很大。此外，对于已经生产的硬件中的DMA引擎的搬运能力已经无法改变。因此，相关技术中，在计算机系统传输的数据量较大且单个DMA引擎的传输性能达到瓶颈时，存在系统的数据传输能力较低的问题。
发明内容
本申请的目的是提供一种数据传输方法、装置、电子设备及非易失性可读存储介质，对目标数据块进行划分，并同时利用多个DMA引擎对同一目标数据块进行处理，提高了对目标数据块处理的速度，提高了服务器数据传输的能力。
本申请的第一方面，为解决上述技术问题，本申请提供了一种数据传输方法，方法包括：
接收传输请求，传输请求中包括目标数据块的源地址、目标地址及目标数据块长度；
从源地址中获取目标数据块，并根据目标数据块长度将目标数据块划分为多个子数据 块；
将多个子数据块分发至多个DMA引擎，以使各个DMA引擎将与自身对应的子数据块传输至目标地址，以完成对目标数据块的传输。
可选地，传输请求包括多个时，接收传输请求之后，还包括：
将多个传输请求按照时间顺序进行排列；
按照排列顺序依次对各传输请求进行处理。
可选地，将多个传输请求按照时间顺序进行排列，包括：
按照时间顺序将多个传输请求依次写入请求队列，请求队列遵循先入先出原则；
按照排列顺序依次对各个传输请求进行处理，包括：
按照请求队列写入的顺序依次对各传输请求进行处理。
可选地，将多个子数据块分发至多个DMA引擎，以使各个DMA引擎将与自身对应的子数据块传输至目标地址，以完成对目标数据块的传输之后，还包括：
判断多个DMA引擎是否完成对目标数据块的传输；
在多个DMA引擎完成对目标数据块的传输的情况下，则进入从请求队列中获取下一个传输请求的步骤。
可选地，在判断多个DMA引擎是否完成对目标数据块的传输之后，方法还包括：
在多个DMA引擎未完成对目标数据块的传输的情况下，则禁止从请求队列中获取下一个传输请求。
可选地，按照时间顺序将多个传输请求依次写入请求队列，请求队列遵循先入先出原则，包括：
使用应用程序通过单线程访问的方式按照时间顺序将多个传输请求依次写入请求队列，其中，请求队列用于隔离应用程序和DMA引擎，应用程序通过请求队列对DMA引擎进行单线程访问。
可选地，按照时间顺序将多个传输请求依次写入请求队列，包括：
在将当前传输请求写入请求队列时，判断请求队列是否为加锁状态；
在请求队列为加锁状态的情况下，则判定请求队列处于访问状态，等待预设时间直至请求队列处于空闲状态时将当前传输请求写入请求队列；
在请求队列为未加锁状态的情况下，判定请求队列处于空闲状态，直接将当前传输请求写入请求队列。
可选地，接收传输请求之后，还包括：
判断传输请求是否设有优先级；
在传输请求设有优先级的情况下，则确定设有优先级的传输请求对应的第一目标地址；
从请求队列的尾端至首端依次查询各传输请求，并判断各传输请求对应的第二目标地址与第一目标地址是否存在重叠；
在各传输请求对应的第二目标地址与第一目标地址存在重叠的情况下，则停止查询，并在将第一目标地址对应的传输请求写入请求队列时，将第一目标地址对应的传输请求写至存在重叠的第二目标地址对应的传输请求之后，以作为第二目标地址对应的传输请求的下一个传输请求。
可选地，从请求队列的尾端至首端依次查询各传输请求，并判断各传输请求对应的第二目标地址与第一目标地址是否存在重叠，包括：
将第一目标地址与请求队列中的各个传输请求对应的第二目标地址进行比对；
在请求队列中存在第二目标地址与第一目标地址比对一致的情况下，则判断各传输请求对应的第二目标地址与第一目标地址存在重叠；在请求队列中不存在第二目标地址与第一目标地址比对一致的情况下，则判断各传输请求对应的第二目标地址与第一目标地址不存在重叠。
可选地，在判断各传输请求对应的第二目标地址与第一目标地址是否存在重叠之后，还包括：
在各传输请求对应的第二目标地址与第一目标地址不存在重叠的情况下，将第一目标地址对应的传输请求写至请求队列的首端。
可选地，从请求队列中获取传输请求时，还包括：
判断获取到的传输请求是否设有优先级；
在获取到的传输请求设有优先级的情况下，则使用预设DMA引擎对设有优先级的传输请求对应的目标数据块进行传输。
可选地，在使用预设DMA引擎对设有优先级的传输请求对应的目标数据块进行传输之前，方法还包括：
在当前允许使用的多个DMA引擎的个数大于目标数量阈值的情况下，将当前允许使用的DMA引擎中的一个或者多个DMA引擎设置为预设DMA引擎。
可选地，根据目标数据块长度将目标数据块划分为与多个子数据块，包括：
根据目标数据块长度及DMA引擎最优传输数据长度将目标数据块划分为与多个子数据块；
每个子数据块的数据长度不大于DMA引擎最优传输数据长度。
可选地，DMA引擎在传输不大于最优传输数据长度的数据块时的传输效率大于目标传输效率。
可选地，根据目标数据块长度及DMA引擎最优传输数据长度将目标数据块划分为与多个子数据块，包括：
根据目标数据块长度及DMA引擎最优传输数据长度将目标数据块平均划分为数据块长度均相同的多个子数据块。
可选地，将多个子数据块分发至多个DMA引擎，包括：
将多个子数据块平均分发至多个DMA引擎。
可选地，每个DMA引擎对应不止一个子数据块时，还包括：
控制DMA引擎按照顺序依次对和自身对应的子数据块进行传输。
本申请的第二方面，为解决上述技术问题，本申请还提供了一种数据传输装置，装置包括：
请求接收单元，被设置为接收传输请求，传输请求中包括目标数据块的源地址、目标地址及目标数据块长度；
划分单元，被设置为从源地址中获取目标数据块，并根据目标数据块长度将目标数据块划分为多个子数据块；
分发单元，被设置为将多个子数据块分发至多个DMA引擎，以使各个DMA引擎将与自身对应的子数据块传输至目标地址，以完成对目标数据块的传输。
本申请的第三方面，为解决上述技术问题，本申请还提供了一种电子设备，包括：
存储器，被设置为存储计算机程序；
处理器，被设置为在存储计算机程序时，实现如上述的数据传输方法的步骤。
本申请的第四方面，为解决上述技术问题，本申请还提供了一种非易失性可读存储介质，非易失性可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现如上述的数据传输方法的步骤。
本申请提供了一种数据传输方法，涉及数据传输领域。该方案中，接收传输请求，传输请求中包括目标数据块的源地址、目标地址及目标数据块长度；从源地址中获取目标数据块，并根据目标数据块长度将目标数据块划分为多个子数据块；将多个子数据块分发至多个DMA引擎，以使各个DMA引擎将与自身对应的子数据块传输至目标地址，以完成对目标数据块的传输。通过本申请中的方式，对目标数据块进行划分，并同时利用多个DMA引擎对同一 目标数据块进行处理，提高了对目标数据块处理的速度，提高了服务器数据传输的能力。
本申请还提供了一种数据传输装置、装置及非易失性可读存储介质，与上述描述的数据传输方法具有相同的有益效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对现有技术和实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请提供的一种数据传输方法的流程示意图；
图2为本申请提供的一种DMA引擎的工作原理图；
图3为本申请提供的另一种数据传输方法的流程示意图；
图4为本申请提供的一种数据传输装置的结构框图；
图5为本申请提供的一种电子设备的结构框图。
具体实施方式
本申请的核心是提供一种数据传输方法、装置、电子设备及非易失性可读存储介质，对目标数据块进行划分，并同时利用多个DMA引擎对同一目标数据块进行处理，提高了对目标数据块处理的速度，提高了服务器数据传输的能力。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参照图1，图1为本申请提供的一种数据传输方法的流程示意图，该方法应用于包括多个DMA引擎的服务器，方法包括：
S11：接收传输请求，传输请求中包括目标数据块的源地址、目标地址及目标数据块长度；
首先对DMA引擎的工作原理做一个简单的介绍，可参照图2，图2为本申请提供的一种DMA引擎的工作原理图。应用程序下发的传输请求中包括数据块1、2、3和4的源地址、目标地址和数据块大小，将其提交至DMA引擎，启动DMA引擎，以使DMA引擎依次将四个数据块由源地 址搬移到对应的目标地址。
S12：从源地址中获取目标数据块，并根据目标数据块长度将目标数据块划分为多个子数据块；
可选地，请参照图3，图3为本申请提供的另一种数据传输方法的流程示意图，若服务器中某一个时刻需要传输的数据量较大时，单个DMA引擎的搬运能力可能会达到瓶颈，此时，无法完成数据的传输。
为解决此问题，本申请中在接收到传输请求时，将传输请求对应的目标数据块划分为多个长度较小的子数据块，以便将其分发给多个DMA引擎，使其共同完成目标数据块的传输，提高了数据传输的效率。
S13：将多个子数据块分发至多个DMA引擎，以使各个DMA引擎将与自身对应的子数据块传输至目标地址，以完成对目标数据块的传输。
将多个子数据块分发至多个DMA引擎之后，每个DMA引擎将与自身对应的子数据块从源地址搬移至目标地址，从而实现对目标数据块的传输。
作为一种可选的实施例，根据目标数据块长度将目标数据块划分为与多个子数据块，包括：
根据目标数据块长度及DMA引擎最优传输数据长度将目标数据块划分为与多个子数据块；
每个子数据块的数据长度不大于DMA引擎最优传输数据长度。
本实施例旨在限定对目标数据块进行划分的可选实施方式，可选地，通常情况下，每个DMA引擎对应一个自身传输的最优传输数据长度，对应的，DMA引擎传输不大于此最优传输数据长度的数据块时的传输效率较高。因此，本申请中在对目标数据块进行划分时，根据目标数据块长度以及DMA引擎最优传输数据长度对目标数据块进行划分，以将其划分为多个子数据块，并保证每个子数据块的长度不大于DMA引擎的最优传输数据长度，以保证DMA引擎的传输效率。
需要说明的是，同一服务器中的多个DMA引擎对应的最优传输数据长度通常相同，但是也可以设置为不相同，本申请在此不做特别的限定。
作为一种可选的实施例，根据目标数据块长度及DMA引擎最优传输数据长度将目标数据块划分为与多个子数据块，包括：
根据目标数据块长度及DMA引擎最优传输数据长度将目标数据块平均划分为数据块长度均相同的多个子数据块。
可选的，本实施例考虑到负载均衡原则，在将目标数据块划分为子数据块时，将多个子数据块的长度设置为相同长度，此时将其分发至各个DMA引擎时，可以一定程度上使得DMA引擎收到的数据块的长度及大小相同，从而尽可能的实现负载均衡，以尽可能的使得多个DMA引擎同步工作。
作为一种可选的实施例，将多个子数据块分发至多个DMA引擎，包括：
将多个子数据块平均分发至多个DMA引擎。
可选的，本实施例中限定了在对DMA引擎分发子数据块时，将子数据块平均分发至各个DMA引擎，以保证各个DMA引擎之间的负载均衡，使得多个DMA引擎尽可能的同步工作。
作为一种可选的实施例，每个DMA引擎对应不止一个子数据块时，还包括：
控制DMA引擎按照顺序依次对和自身对应的子数据块进行传输。
可选地，将目标数据块进行划分之后，若每个DMA引擎对应不止一个子数据块时，对应的，为保证各目标地址中数据的正确性，本申请中各DMA引擎对和自身对应的子数据块进行处理时，需保证每个DMA按照顺序依次处理各个子数据块。
例如，某目标数据块长度(也即大小)为16K，DMA引擎个数为2，每个DMA引擎对应的最优传输数据长度为4k，此时，对目标数据块进行划分时，划分为数据长度为4k的4个子数据块，然后为每个DMA引擎分配2个子数据块，每个DMA引擎按照顺序依次对和自身对应的2个子数据块进行传输，可以为：在传输完第一个子数据块之后，再传输第二个子数据块。
作为一种可选的实施例，传输请求包括多个时，接收传输请求之后，还包括：
将多个传输请求按照时间顺序进行排列；
按照排列顺序依次对各传输请求进行处理。
可选的，传输请求有多个时，可能会存在多个DMA引擎对同一个目标地址进行写入的情况，此时可能会导致该目标地址的数据被破坏。
因此，在传输请求有多个时，本申请需要将传输请求按照时间顺序进行排列，并且按照对应的排列顺序依次处理各个传输请求，以保证在同一个时刻DMA引擎只处理一个传输请求，也即在同一个时刻对同一个目标地址只有一个写入操作，可以避免目标地址中的数据被损坏。
作为一种可选的实施例，将多个传输请求按照时间顺序进行排列，包括：
按照时间顺序将多个传输请求依次写入请求队列，请求队列遵循先入先出原则；
按照排列顺序依次对各个传输请求进行处理，包括：
按照请求队列写入的顺序依次对各传输请求进行处理。
本实施例旨在限定对各个传输请求的进行排列的可选实现方式，可选地，本申请中使用请求队列对各个传输请求进行排列，将多个传输请求按照时间顺序依次写入请求队列中，由于本申请中的请求队列遵循先入先出原则，因此，对请求队列中的各个传输请求进行获取时，只能按照时间顺序(也即是写入队列的顺序)从请求队列中依次对各个传输请求进行处理。
可见，通过本申请中的方式可以避免目标地址中的数据被损坏。
作为一种可选的实施例，将多个子数据块分发至多个DMA引擎，以使各个DMA引擎将与自身对应的子数据块传输至目标地址，以完成对目标数据块的传输之后，还包括：
判断多个DMA引擎是否完成对目标数据块的传输；
在多个DMA引擎完成对目标数据块的传输的情况下，则进入从请求队列中获取下一个传输请求的步骤。
可选的，为保证DMA引擎每次只针对一个传输请求对应的目标数据块进行处理，避免出现对多个传输请求进行处理时存在的DMA引擎同时对同一目标地址进行写入，进而导致数据损坏的问题。
本申请中，在DMA引擎对当前的传输请求对应的目标数据块进行传输时，还会判断当前的目标数据块的传输是否完成，在其未完成时，表示DMA引擎当前处于对当前的传输请求对应的目标数据块进行传输的状态；若直接从请求队列中获取下一个传输请求，则下一个传输请求对应的目标地址可能会与当前的传输请求对应的目标地址有重叠(也即是存在有重复的地址)，此时，可能会存在DMA引擎同时对同一个地址的数据进行写入，此时可能会导致重叠部分的地址对应的数据损坏。因此，本申请中在判断目标数据块的传输完成时，表示DMA引擎当前已经完成对当前的目标数据块进行传输的过程，也即，表示DMA引擎处于空闲状态，此时再对下一个传输请求进行处理时，可以避免存在目标地址重叠的情况，进而避免数据损坏。
可选的，应用程序下发传输请求的过程为单线程访问DMA引擎的过程，若同一时刻存在多个线程同时访问DMA引擎，则会出现同时调用DMA引擎使其搬移数据带来的竞争问题。
因此，本申请中在应用程序(也即线程)和DMA引擎之间设置了请求队列，此请求队列还可以实现应用程序和DMA引擎之间的隔离，使得应用程序无法直接访问DMA引擎，必须通过请求队列才可以实现对DMA引擎的访问，此请求队列可以实现对各个传输请求的排序，从而可以避免多个线程同时调用DMA引擎带来的竞争问题。
作为一种可选的实施例，按照时间顺序将多个传输请求依次写入请求队列，包括：
在将当前传输请求写入请求队列时，判断请求队列是否为加锁状态；
在请求队列为加锁状态的情况下，则判定请求队列处于访问状态，等待预设时间直至请求队列处于空闲状态时将当前传输请求写入请求队列；
在请求队列为未加锁状态的情况下，判定请求队列处于空闲状态，直接将当前传输请求写入请求队列。
可选的，若存在多线程同时向请求队列写入多个传输请求，且多个传输请求对应的目标地址之间若存在重叠，则可能会导致重叠部分的数据错误。
为避免上述问题，本申请中在将传输请求写入请求队列时，需判断请求队列是否为加锁状态。可选地，请求队列在被访问时为加锁状态，请求队列未被访问时为未加锁状态。因此，在将当前传输请求写入请求队列时，若判定请求队列为加锁状态，则判定请求队列当前正在被访问，也即是，正在有一个传输请求处于写入请求队列的过程中，此时不允许再写入一个传输请求至请求队列中，需等待直至上一个传输请求写入至请求队列的过程完成，也即是，需要等待直至请求队列处于空闲状态时，才能将当前的传输请求写入请求队列。若在当前传输请求写入请求队列时，判定请求队列为未加锁的状态，则判定请求队列当前没有被访问，也即是，请求队列处于空闲状态，此时可以将传输请求直接写入请求队列，且不会存在目标地址重叠的情况。
综上，通过本申请中的方式，可以保证各个传输请求之间的先后顺序，保证重叠的目标地址先后被读写访问，也即，使得请求队列在同一个时刻只有一个线程在访问，也即是，同一时刻请求队列只允许一个传输请求写入，可以避免目标地址的重叠部分对应的数据错误。
作为一种可选的实施例，接收传输请求之后，还包括：
判断传输请求是否设有优先级；
在传输请求设有优先级的情况下，则确定设有优先级的传输请求对应的第一目标地址；
从请求队列的尾端至首端依次查询各传输请求，并判断各传输请求对应的第二目标地址与第一目标地址是否存在重叠；
在各传输请求对应的第二目标地址与第一目标地址存在重叠的情况下，则停止查询，并在将第一目标地址对应的传输请求写入请求队列时，将第一目标地址对应的传输请求写至存在重叠的第二目标地址对应的传输请求之后，以作为第二目标地址对应的传输请求的下一个传输请求。
可选的，在对目标数据块进行传输时，可能还会存在一些优先级较高的目标数据块(如对目标数据块预先设置了优先级)，此时，在上述已经使用请求队列的基础上，如何使用请 求队列以保障对高优先级的目标数据块进行传输是本申请要解决的问题。
可选的，首先，在上述接收到传输请求之后，需判断该传输请求是否设有优先级，若设有优先级，则确定该传输请求对应的目标数据块为高优先级的目标数据块。在确定传输请求设有优先级之后，获取该传输请求对应的第一目标地址，然后将此第一目标地址与请求队列中的各个传输请求对应的第二目标地址进行对比(自尾端至首端逐个比较)，以确定是否存在传输请求对应的第二目标地址与第一目标地址重叠的情况，若存在重叠，则表示重叠部分的地址需要至少被写入两次，且具有先后顺序，分别为第二目标地址对应的传输请求需写入一次、以及第一目标地址对应的传输请求处需要写入一次。因此，即便第一目标地址对应的传输请求的优先级较高，也不能高于与第一目标地址有重叠的第二目标地址对应的传输请求，否则会导致目标地址重叠部分的数据错误。因此，将第一目标地址对应的传输请求写入请求队列时，也只能写在第二目标地址对应的传输请求之后，以保证数据的安全性，避免数据损坏。
需要说明的是，本申请中第二目标地址对应的传输请求为从请求队列的尾端至首端查询到的第一个与第一目标地址有重叠的传输请求。一旦查询到此第一目标地址对应的传输请求，则停止查询，因为无论此传输请求之前的传输请求对应的目标地址是否与第一目标地址有重叠，第二目标地址对应的传输请求处均需要对重叠的地址写入一次。此外，停止查询也可以在一定程度上减少处理器的功耗。
作为一种可选的实施例，在判定不存在重叠之后，还包括：
将第一目标地址对应的传输请求写至请求队列的首端。
可选的，在上述从请求队列的尾端至首端未查询到与第一目标地址有重叠的传输请求，表示请求队列中不存在与第一目标地址对应的传输请求有冲突的传输请求(也即传输请求中对应的目标地址中不存在与第一目标地址重叠的传输请求)。此时，可以将第一目标地址对应的传输请求写入至请求队列的首端，以便更早的对此传输请求进行处理，且不会导致各个地址中的数据损坏。
作为一种可选的实施例，从请求队列中获取传输请求时，还包括：
判断获取到的传输请求是否设有优先级；
在获取到的传输请求设有优先级的情况下，则使用预设DMA引擎对设有优先级的传输请求对应的目标数据块进行传输。
可选的，在服务器中DMA引擎的个数较为充足时，可以为设有优先级的传输请求设置单独的预设DMA引擎，该预设DMA引擎只负责传输设有优先级的传输请求。
可选地，在上述传输请求设有优先级时，将其写入至请求队列之后，在从请求队列中获取某个传输请求，以对此传输请求进行处理时，需判断此传输请求是否为设有优先级的传输请求，若是，则使用预设DMA引擎对设有优先级的传输请求进行处理，也即是，使用预设DMA引擎对设有优先级的传输请求对应的目标数据块进行传输。
若服务器中的DMA引擎的个数相对不充足，也即DMA引擎的个数较少时，此时，从请求队列中获取到设有优先级的传输请求时，按照以上常规步骤对该传输请求进行处理即可。
综上，通过本申请中的方式，对目标数据块进行划分，并同时利用多个DMA引擎对同一目标数据块进行处理，可以提高了对目标数据块处理的速度，进而提高了服务器数据传输的能力。
为解决上述技术问题，本申请还提供了一种数据传输装置，请参照图4，图4为本申请提供的一种数据传输装置的结构框图，该系统装置包括：
请求接收单元41，被设置为接收传输请求，传输请求中包括目标数据块的源地址、目标地址及目标数据块长度；
划分单元42，被设置为从源地址中获取目标数据块，并根据目标数据块长度将目标数据块划分为多个子数据块；
分发单元43，被设置为将多个子数据块分发至多个DMA引擎，以使各个DMA引擎将与自身对应的子数据块传输至目标地址，以完成对目标数据块的传输。
作为一种可选的实施例，还包括：
排列单元，被设置为将多个传输请求按照时间顺序进行排列；
顺序处理单元，被设置为按照排列顺序依次对各传输请求进行处理。
作为一种可选的实施例，排列单元，可以被设置为按照时间顺序将多个传输请求依次写入请求队列，请求队列遵循先入先出原则；
顺序处理单元，可以被设置为按照请求队列写入的顺序依次对各传输请求进行处理。
作为一种可选的实施例，还包括：
第一判断单元，被设置为判断多个DMA引擎是否完成对目标数据块的传输；在多个DMA引擎完成对目标数据块的传输的情况下，则进入从请求队列中获取下一个传输请求的步骤。
作为一种可选的实施例，顺序处理单元包括：
第二判断单元，被设置为在将当前传输请求写入请求队列时，判断请求队列是否为加锁状态；
第一执行单元，被设置为在加锁状态时，判定请求队列处于访问状态，等待预设时间直 至请求队列处于空闲状态时将当前传输请求写入请求队列；
第二执行单元，被设置为在未加锁状态时，判定请求队列处于空闲状态，直接将当前传输请求写入请求队列。
作为一种可选的实施例，还包括：
第三判断单元，被设置为判断传输请求是否设有优先级；
第三执行单元，被设置为在传输请求设有优先级时，确定设有优先级的传输请求对应的第一目标地址；
第四判断单元，被设置为从请求队列的尾端至首端依次查询各传输请求，并判断各传输请求对应的第二目标地址与第一目标地址是否存在重叠；
第四执行单元，被设置为在判定存在重叠时，停止查询，并在将第一目标地址对应的传输请求写入请求队列时，将第一目标地址对应的传输请求写至存在重叠的第二目标地址对应的传输请求之后，以作为第二目标地址对应的传输请求的下一个传输请求。
作为一种可选的实施例，还包括：
第五执行单元，被设置为在判定不存在重叠时，将第一目标地址对应的传输请求写至请求队列的首端。
作为一种可选的实施例，从请求队列中获取传输请求时，还包括：
第五判断单元，被设置为判断获取到的传输请求是否设有优先级；
第六执行单元，被设置为在获取到的传输请求设有优先级时，则使用预设DMA引擎对设有优先级的传输请求对应的目标数据块进行传输。
作为一种可选的实施例，划分单元，可以被设置为根据目标数据块长度及DMA引擎最优传输数据长度将目标数据块划分为与多个子数据块；
每个子数据块的数据长度不大于DMA引擎最优传输数据长度。
作为一种可选的实施例，划分单元可以被设置为根据目标数据块长度及DMA引擎最优传输数据长度将目标数据块平均划分为数据块长度均相同的多个子数据块。
作为一种可选的实施例，分发单元可以被设置为将多个子数据块平均分发至多个DMA引擎。
作为一种可选的实施例，还包括：
控制单元，被设置为在每个DMA引擎对应不止一个子数据块时，控制DMA引擎按照顺序依次对和自身对应的子数据块进行传输。
对于数据传输装置的介绍请参照上述实施例，本申请在此不再赘述。
为解决上述技术问题，本申请还提供了一种电子设备，请参照图5，图5为本申请提供的一种电子设备的结构框图，该装置包括：
存储器51，被设置为存储计算机程序；
处理器52，被设置为在存储计算机程序时，实现如上述的数据传输方法的步骤。
对于电子设备的介绍请参照上述实施例，本申请在此不再赘述。
为解决上述技术问题，本申请还提供了一种非易失性可读存储介质，非易失性可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现如上述的数据传输方法的步骤。其中，非易失性可读存储介质可为暂态存储介质或非暂态存储介质，本申请不再限定。对于非易失性可读存储介质的介绍请参照上述实施例，本申请在此不再赘述。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的状况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其他实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (20)

  1. 一种数据传输方法，其特征在于，所述方法包括：
    接收传输请求，所述传输请求中包括目标数据块的源地址、目标地址及目标数据块长度；
    从所述源地址中获取目标数据块，并根据所述目标数据块长度将所述目标数据块划分为多个子数据块；
    将多个所述子数据块分发至多个直接存储器访问DMA引擎，以使各个所述DMA引擎将与自身对应的子数据块传输至所述目标地址，以完成对所述目标数据块的传输。
  2. 如权利要求1所述的数据传输方法，其特征在于，所述传输请求包括多个时，接收传输请求之后，还包括：
    将多个所述传输请求按照时间顺序进行排列；
    按照排列顺序依次对各所述传输请求进行处理。
  3. 如权利要求2所述的数据传输方法，其特征在于，将多个所述传输请求按照时间顺序进行排列，包括：
    按照时间顺序将多个所述传输请求依次写入请求队列，所述请求队列遵循先入先出原则；
    按照排列顺序依次对各个所述传输请求进行处理，包括：
    按照所述请求队列写入的顺序依次对各所述传输请求进行处理。
  4. 如权利要求3所述的数据传输方法，其特征在于，将多个所述子数据块分发至多个所述DMA引擎，以使各个所述DMA引擎将与自身对应的子数据块传输至所述目标地址，以完成对所述目标数据块的传输之后，还包括：
    判断多个所述DMA引擎是否完成对所述目标数据块的传输；
    在多个所述DMA引擎完成对所述目标数据块的传输的情况下，则进入从所述请求队列中获取下一个所述传输请求的步骤。
  5. 如权利要求4所述的数据传输方法，其特征在于，在所述判断多个所述DMA引擎是否完成对所述目标数据块的传输之后，所述方法还包括：
    在多个所述DMA引擎未完成对所述目标数据块的传输的情况下，则禁止从所述请求队列中获取下一个所述传输请求。
  6. 如权利要求3所述的数据传输方法，其特征在于，所述按照时间顺序将多个所述传输请求依次写入请求队列，所述请求队列遵循先入先出原则，包括：
    使用应用程序通过单线程访问的方式按照时间顺序将多个所述传输请求依次写入所述请求队列，其中，所述请求队列用于隔离所述应用程序和所述DMA引擎，所述应用程序通过所述请求队列对所述DMA引擎进行所述单线程访问。
  7. 如权利要求3所述的数据传输方法，其特征在于，按照时间顺序将多个所述传输请求依次写入请求队列，包括：
    在将当前传输请求写入所述请求队列时，判断所述请求队列是否为加锁状态；
    在所述请求队列为加锁状态的情况下，则判定所述请求队列处于访问状态，等待预设时间直至所述请求队列处于空闲状态时将所述当前传输请求写入所述请求队列；
    在所述请求队列为未加锁状态的情况下，判定所述请求队列处于所述空闲状态，直接将所述当前传输请求写入所述请求队列。
  8. 如权利要求3所述的数据传输方法，其特征在于，接收传输请求之后，还包括：
    判断所述传输请求是否设有优先级；
    在所述传输请求设有优先级的情况下，则确定设有优先级的传输请求对应的第一目标地址；
    从所述请求队列的尾端至首端依次查询各所述传输请求，并判断各所述传输请求对应的第二目标地址与所述第一目标地址是否存在重叠；
    在各所述传输请求对应的第二目标地址与所述第一目标地址存在重叠的情况下，则停止查询，并在将所述第一目标地址对应的传输请求写入所述请求队列时，将所述第一目标地址对应的传输请求写至存在重叠的所述第二目标地址对应的传输请求之后，以作为所述第二目标地址对应的传输请求的下一个传输请求。
  9. 如权利要求8所述的数据传输方法，其特征在于，所述从所述请求队列的尾端至首端依次查询各所述传输请求，并判断各所述传输请求对应的第二目标地址与所述第一目标地址是否存在重叠，包括：
    将所述第一目标地址与所述请求队列中的各个所述传输请求对应的所述第二目标地址进行比对；
    在所述请求队列中存在所述第二目标地址与所述第一目标地址比对一致的情况下，则判断各所述传输请求对应的所述第二目标地址与所述第一目标地址存在重叠；在所述请求队列中不存在所述第二目标地址与所述第一目标地址比对一致的情况下，则判断各所述传输请求对应的所述第二目标地址与所述第一目标地址不存在重叠。
  10. 如权利要求8所述的数据传输方法，其特征在于，在判断各所述传输请求对应的第二目标地址与所述第一目标地址是否存在重叠之后，还包括：
    在各所述传输请求对应的第二目标地址与所述第一目标地址不存在重叠的情况下，将所述第一目标地址对应的传输请求写至所述请求队列的首端。
  11. 如权利要求7所述的数据传输方法，其特征在于，从所述请求队列中获取传输请求时，还包括：
    判断获取到的所述传输请求是否设有优先级；
    在获取到的所述传输请求设有优先级的情况下，则使用预设DMA引擎对设有优先级的所述传输请求对应的目标数据块进行传输。
  12. 如权利要求11所述的数据传输方法，其特征在于，在所述使用预设DMA引擎对设有优先级的所述传输请求对应的目标数据块进行传输之前，所述方法还包括：
    在当前允许使用的多个所述DMA引擎的个数大于目标数量阈值的情况下，将当前允许使用的所述DMA引擎中的一个或者多个所述DMA引擎设置为所述预设DMA引擎。
  13. 如权利要求1-12任一项所述的数据传输方法，其特征在于，根据所述目标数据块长度将所述目标数据块划分为与多个子数据块，包括：
    根据所述目标数据块长度及DMA引擎最优传输数据长度将所述目标数据块划分为与多个子数据块；
    每个所述子数据块的数据长度不大于所述DMA引擎最优传输数据长度。
  14. 如权利要求13任一项所述的数据传输方法，其特征在于，所述DMA引擎在传输不大于所述最优传输数据长度的数据块时的传输效率大于目标传输效率。
  15. 如权利要求13所述的数据传输方法，其特征在于，根据所述目标数据块长度及DMA引擎最优传输数据长度将所述目标数据块划分为与多个子数据块，包括：
    根据所述目标数据块长度及DMA引擎最优传输数据长度将所述目标数据块平均划分为数据块长度均相同的多个子数据块。
  16. 如权利要求15所述的数据传输方法，其特征在于，将多个所述子数据块分发至多个所述DMA引擎，包括：
    将多个所述子数据块平均分发至多个所述DMA引擎。
  17. 如权利要求16所述的数据传输方法，其特征在于，每个所述DMA引擎对应不止一个所述子数据块时，还包括：
    控制所述DMA引擎按照顺序依次对和自身对应的子数据块进行传输。
  18. 一种数据传输装置，其特征在于，所述装置包括：
    请求接收单元，被设置为接收传输请求，所述传输请求中包括目标数据块的源地址、目标地址及目标数据块长度；
    划分单元，被设置为从所述源地址中获取目标数据块，并根据所述目标数据块长度将所述目标数据块划分为多个子数据块；
    分发单元，被设置为将多个所述子数据块分发至多个DMA引擎，以使各个所述DMA引擎将与自身对应的子数据块传输至所述目标地址，以完成对所述目标数据块的传输。
  19. 一种电子设备，其特征在于，包括：
    存储器，被设置为存储计算机程序；
    处理器，被设置为在存储计算机程序时，实现如权利要求1-17任一项所述的数据传输方法的步骤。
  20. 一种非易失性可读存储介质，其特征在于，所述非易失性可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1-17任一项所述的数据传输方法的步骤。
PCT/CN2023/101164 2022-11-16 2023-06-19 一种数据传输方法、装置、电子设备及非易失性可读存储介质 WO2024103720A1 (zh)

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