WO2024103554A1 - 占空比调整电路及存储器 - Google Patents

占空比调整电路及存储器 Download PDF

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Publication number
WO2024103554A1
WO2024103554A1 PCT/CN2023/077269 CN2023077269W WO2024103554A1 WO 2024103554 A1 WO2024103554 A1 WO 2024103554A1 CN 2023077269 W CN2023077269 W CN 2023077269W WO 2024103554 A1 WO2024103554 A1 WO 2024103554A1
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Prior art keywords
signal
duty cycle
adjustment
input end
control
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PCT/CN2023/077269
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English (en)
French (fr)
Inventor
易峰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Definitions

  • the duty cycle determines the ratio of the working time to the total time in a cycle.
  • the duty cycle will also affect the required bandwidth, so it is an important parameter of the clock signal, and an accurate and stable clock signal needs to provide a fixed duty cycle.
  • problems such as long duty cycle locking time, loss of flexibility due to architectural limitations, limited applicable frequency, and low stability.
  • the duty cycle detection module includes: a cache unit, configured to receive and cache an adjustment clock signal; a conversion unit, connected to the cache unit, configured to generate a first voltage based on a high-level duty cycle of the adjustment clock signal and a preset voltage, and to generate a second voltage based on a low-level duty cycle of the adjustment clock signal and a preset voltage; a comparison unit, connected to the conversion unit, configured to compare the voltage magnitudes of the first voltage and the second voltage to generate an identification signal.
  • the driving unit includes: a first D flip-flop, an input terminal for receiving an identification signal, a clock terminal for receiving an update signal, and an output terminal for outputting a selection signal.
  • the tracking input end includes an increase tracking input end and a decrease tracking input end
  • the tracking output end includes an increase tracking output end and a decrease tracking output end
  • the tracking signal generating unit includes: a first tracking AND gate, one input end of which is connected to the output end of the first selector, the other input end is used to receive the search cutoff signal, and the output end is connected to the increase tracking input end of the last-level sub-control unit; the first input end of the first selector is used to receive the identification signal corresponding to the adjusted adjustment clock signal, the second input end is used to receive the inverted signal of the identification signal corresponding to the adjusted adjustment clock signal, and the selection end is used to receive the selection signal; a second tracking AND gate, one input end of which is connected to the output end of the second selector, the other input end is used to receive the search cutoff signal, and the output end is connected to the decrease tracking input end of the last-level sub-control unit; the first input end of the second selector is used to receive the inverted signal of the identification signal corresponding to the
  • the first selector and the second selector output the input signal corresponding to the first input terminal; if the selection signal is at a low level, the first selector and the second selector output the input signal corresponding to the second input terminal.
  • the duty cycle correction module includes: at least one first adjustment unit and at least one second adjustment unit; the first adjustment unit is configured to adjust the duty cycle of the initial clock signal based on the first adjustment control signal and the second adjustment control signal to generate an intermediate clock signal; the second adjustment unit is configured to adjust the duty cycle of the intermediate clock signal based on the inverted signal of the first adjustment control signal and the inverted signal of the second adjustment control signal to generate an adjusted clock signal.
  • FIG1 is a schematic diagram of the structure of a duty cycle adjustment circuit provided by an embodiment of the present disclosure
  • FIG2 is a schematic diagram of the principle of a binary search algorithm provided by an embodiment of the present disclosure
  • FIG3 is a schematic diagram of the structure of a duty cycle detection module provided in an embodiment of the present disclosure.
  • FIG4 is a schematic diagram of the structure of a correction control module provided in an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of the structure of a driving unit provided in an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of the structure of a generation unit provided in an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of the structures of a control unit, a search mark selector and a tracking signal generating unit provided in an embodiment of the present disclosure
  • FIG8 is a schematic diagram of a specific structure of a control unit provided in an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of a specific structure of each sub-control unit provided in an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of the structure of a duty cycle correction module provided in an embodiment of the present disclosure.
  • FIG11 is a schematic structural diagram of a first adjustment unit provided in an embodiment of the present disclosure.
  • FIG12 is a schematic diagram of the structure of a second adjustment unit provided in an embodiment of the present disclosure.
  • FIG13 is a schematic diagram of the structure of a duty cycle adjustment circuit having a phase error detection module and a mode selector provided in an embodiment of the present disclosure.
  • the duty cycle determines the ratio of the working time to the total time in a cycle.
  • the duty cycle will also affect the required bandwidth, so it is an important parameter of the clock signal, and an accurate and stable clock signal needs to provide a fixed duty cycle.
  • FIG. 1 is a schematic diagram of the structure of a duty cycle adjustment circuit provided in the present embodiment
  • FIG. 2 is a schematic diagram of the principle of a binary search algorithm provided in the present embodiment
  • FIG. 3 is a schematic diagram of the structure of a duty cycle detection module provided in the present embodiment
  • FIG. 4 is a schematic diagram of the structure of a correction control module provided in the present embodiment
  • FIG. 5 is a schematic diagram of the structure of a driving unit provided in the present embodiment
  • FIG. 6 is a schematic diagram of the structure of a generating unit provided in the present embodiment
  • FIG. 7 is a schematic diagram of the structure of a control unit, a search identifier selector and a tracking signal generating unit provided in the present embodiment
  • FIG. 1 is a schematic diagram of the structure of a duty cycle adjustment circuit provided in the present embodiment
  • FIG. 2 is a schematic diagram of the principle of a binary search algorithm provided in the present embodiment
  • FIG. 3 is a schematic diagram of the structure of a duty cycle detection module provided in
  • FIG. 8 is a schematic diagram of the specific structure of a control unit provided in the present embodiment
  • FIG. 9 is a schematic diagram of the specific structure of each sub-control unit provided in the present embodiment
  • FIG. 10 is a schematic diagram of the structure of a duty cycle correction module provided in the present embodiment
  • FIG. 11 is a schematic diagram of the structure of a first adjustment unit provided in the present embodiment
  • FIG. 12 is a schematic diagram of the structure of a second adjustment unit provided in the present embodiment
  • FIG. 13 is a schematic diagram of the structure of a duty cycle adjustment circuit with a phase error detection module and a mode selector provided in the present embodiment.
  • the duty cycle adjustment circuit includes:
  • the duty cycle correction module 101 is configured to adjust the duty cycle of the initial clock signal Clk_In based on the adjustment control signal to generate an adjusted clock signal Clk_Out.
  • the duty cycle detection module 102 is configured to obtain the duty cycle of the adjusted clock signal Clk_Out and generate an identification signal based on the duty cycle of the adjusted clock signal.
  • the correction control module 103 is configured to adjust the adjustment control signal based on the binary search algorithm and the value of the identification signal.
  • the duty cycle correction module 101 is further configured to regenerate the adjustment clock signal Clk_Out based on the adjusted adjustment control signal until the duty cycle of the adjusted adjustment clock signal Clk_Out meets the preset duty cycle.
  • the identification signal is used to characterize that the duty cycle of the adjusted clock signal Clk_Out is greater than 50% or less than 50%; in one example, if the duty cycle of the adjusted clock signal Clk_Out is greater than 50%, the value of the identification signal is "0"; if the duty cycle of the adjusted clock signal Clk_Out is less than 50%, the value of the identification signal is "1"; it should be noted that, in other embodiments, if the duty cycle of the adjusted clock signal is greater than 50%, the value of the identification signal can be set to "1"; if the duty cycle of the adjusted clock signal is less than 50%, the value of the identification signal can be set to "0".
  • the duty cycle detection module 102 continuously adjusts the clock signal
  • the correction control module 103 adjusts the generated adjustment control signal based on the value of the identification signal through a binary search algorithm, and the duty cycle correction module 101 continuously adjusts the duty cycle of the initial clock signal Clk_In based on the adjustment control signal to generate an adjusted clock signal Clk_Out whose duty cycle satisfies a preset duty cycle; wherein the duty cycle correction module 101 changes the adjustment amplitude of the duty cycle of the initial clock signal Clk_In based on different adjustment control signals.
  • this embodiment takes a five-bit adjustment control signal as an example for specific description.
  • the initial value of the adjustment control signal is set to "10000".
  • the value of the adjustment control signal is adjusted to "11000” or "01000” based on the identification signal corresponding to the adjusted adjustment clock signal Clk_Out;
  • the adjustment clock signal Clk_Out is adjusted twice, the value of the adjustment control signal is adjusted to "11100", “10100”, “01100” or "00100” based on the identification signal corresponding to the adjusted adjustment clock signal Clk_Out; after the adjustment clock signal Clk_Out is adjusted three times, the value of the adjustment control signal is adjusted based on the identification signal corresponding to the adjusted adjustment clock signal Clk_Out.
  • the value of the adjustment control signal is “11110”, “11010”, “10110”, “10010”, “01110”, “01010”, “00110” or “00010”; after the adjustment clock signal Clk_Out is adjusted four times, based on the identification signal corresponding to the adjusted clock signal Clk_Out, the value of the adjustment control signal is adjusted to be “11111”, “11101”, “11011”, “11001”, “10111”, “10101”, “10011”, “10001”, “01111”, “01101”, “01011”, “01001”, “00111”, “00101", “00011” or "00001", so as to obtain the adjustment clock signal Clk_Out whose duty cycle satisfies the preset duty cycle.
  • the adjustment control signal as 5-bit data as an example, which does not constitute a limitation of this embodiment.
  • the data length of the adjustment control signal can be selected based on the accuracy of the adjustment clock signal Clk_Out or the preset duty cycle to be obtained; it should also be noted that in this embodiment, the preset duty cycle is 50% ⁇ 1%.
  • a binary search algorithm is combined to quickly obtain the adjustment amplitude of the initial clock signal, thereby obtaining an adjusted clock signal whose duty cycle satisfies a preset duty cycle, thereby shortening the acquisition time of the adjusted clock signal whose duty cycle satisfies the preset duty cycle, thereby improving the performance of the memory.
  • the adjustment control signal is 5-bit data
  • the corresponding 5-bit adjustment control signal can be obtained within five adjustment cycles through a binary search algorithm, so that the duty cycle of the generated adjustment clock signal meets the preset duty cycle.
  • the time for obtaining the adjustment clock signal whose duty cycle meets the preset duty cycle is greatly saved.
  • the duty cycle detection module 102 includes: a cache unit 301, configured to receive and cache the adjustment clock signal Clk_Out; a conversion unit 302, connected to the cache unit 301, configured to generate a first voltage based on the high level duty cycle of the adjustment clock signal Clk_Out and a preset voltage, and to generate a second voltage based on the low level duty cycle of the adjustment clock signal and a preset voltage; a comparison unit 303, connected to the conversion unit 302, configured to compare the voltage magnitudes of the first voltage and the second voltage to generate an identification signal.
  • the cache unit 301 outputs the adjustment clock signal Clk_Out and the inverted adjustment clock signal
  • the conversion unit 302 generates a first voltage based on the high level duty cycle of the adjustment clock signal Clk_Out and a preset voltage, and generates a second voltage based on the high level duty cycle of the inverted adjustment clock signal and a preset voltage, that is, generates a second voltage based on the low level duty cycle of the adjustment clock signal Clk_Out and a preset voltage.
  • the high-level duty cycle of the adjusted clock signal Clk_Out is C1
  • the low-level duty cycle is C2.
  • the first voltage preset voltage * C1
  • the duty cycle detection module 102 further includes: a filtering unit 304, which is disposed in a connection path between the conversion unit 302 and the comparison unit 303, and the filtering unit 304 is used to filter the noise signals of the first voltage and the second voltage to ensure the accuracy of the identification signal generated by the comparison unit 303.
  • the correction control module 103 including: a driving unit 201, configured to generate a selection signal corresponding to the identification signal based on the effective pulse of the update signal; a control unit 202, configured to generate a first control signal group using a binary search algorithm, wherein the first control signal group includes a plurality of first sub-control signals; a generating unit 203, configured to generate an adjustment control signal based on the selection signal and the first control signal group.
  • the identification signal initially received by the driving unit 201 is generated based on the initial adjustment control signal Clk_Out, i.e., the identification signal corresponding to the initial clock signal Clk_In. In the subsequent adjustment process, even if the identification signal input to the driving unit 201 changes, the selection signal will not change because the effective pulse of the update signal is no longer sent.
  • the driving unit 201 includes: a first D flip-flop, an input end for receiving an identification signal, a clock end for receiving an update signal, and an output end for outputting a selection signal. Specifically, when the update signal received by the first D flip-flop generates a valid pulse, the selection signal is generated based on the identification signal, and when the value of the identification signal is "1", the value of the corresponding generated selection signal is "1", and when the value of the identification signal is "0", the value of the corresponding generated selection signal is "0".
  • the valid pulse of the update signal is only generated once during the adjustment process of the initial clock signal Clk_In, which is used to record the duty cycle information of the initial clock signal Clk_In, and generate a corresponding selection signal based on the duty cycle information of the initial clock signal Clk_In, so as to realize the subsequent duty cycle adjustment of the initial clock signal Clk_In.
  • the initial clock signal Clk_In when the initial clock signal Clk_In arrives for the first time and the correction control module 103 is not started, the initial clock signal Clk_In generates an initial adjustment control signal through a duty cycle correction module 101 with an initial value.
  • the initial adjustment signal obtains an initial identification signal based on the duty cycle detection module 102.
  • the initial identification signal generates a selection signal under the action of a valid pulse of the update signal.
  • the adjustment control signal includes a first adjustment control signal and a second adjustment control signal
  • the duty cycle adjustment module 101 is controlled and adjusted by two different adjustment control signals to achieve adjustment of the rising edge and the falling edge of the clock signal, thereby achieving duty cycle adjustment of the clock signal.
  • the generation unit 203 includes: a first selection unit group 210, including multiple first selection units, the first input end of each first selection unit is used to receive the corresponding first sub-control signal D ⁇ 4:0>, and the second input end receives the inverted signal DN ⁇ 4:0> of the same first sub-control signal, the first selection unit group 210 is configured to output the second control signal group Lsel ⁇ 4:0> based on the selection signal, the second selection unit 220, the first input end is used to receive the second control signal group, and the second input end is used to receive a low level, the second selection unit 220 is configured to generate a first adjustment control signal CtrlAN ⁇ 4:0> based on the selection signal; a third selection unit 230, the first input end is used to receive a high level, and the second input end is used to receive the second control signal group Lsel ⁇ 4:0>, the third selection unit 230 is configured to generate a second adjustment control signal CtrlBN ⁇ 4:0> based on
  • the first selection unit, the second selection unit 220 and the third selection unit 230 when the selection signal is "1", the first selection unit, the second selection unit 220 and the third selection unit 230 select the input signal of the first input terminal to generate output data; when the selection signal is "0", the first selection unit, the second selection unit 220 and the third selection unit 230 select the input signal of the second input terminal to generate output data.
  • the first selection unit group 210 selects the first sub-control signal D ⁇ 4:0> and outputs the second control signal group Lsel ⁇ 4:0>
  • the second selection unit 220 outputs the first adjustment control signal CtrlAN ⁇ 4:0> based on the high level
  • the third selection unit 230 outputs the second adjustment control signal CtrlBN ⁇ 4:0> based on the second control signal group Lsel ⁇ 4:0>
  • the first selection unit group 210 selects the inverted signal DN ⁇ 4:0> of the first sub-control signal and outputs the second control signal group Lsel ⁇ 4:0>
  • the second selection unit 220 outputs the first adjustment control signal CtrlAN ⁇ 4:0> based on the second control signal group Lsel ⁇ 4:0>
  • the third selection unit 230 outputs the second adjustment control signal CtrlBN ⁇ 4:0> based on the low level.
  • the correction control module 103 further includes: a search identification selector 602, wherein the selection end is used to receive a selection signal, the first input end is used to receive an identification signal corresponding to the adjusted adjustment clock signal, the second input end is used to receive an inverted signal of the identification signal corresponding to the adjusted adjustment clock signal, and the output end is used to output a search identification signal Comp.
  • the search identification signal Comp is used to indicate that the duty cycle of the adjustment clock signal Clk_Out in the next state is greater than 50% or less than 50%.
  • the first sub-control signal D ⁇ 4:0> is the five-bit control signal D ⁇ 0>, D ⁇ 1>, D ⁇ 2>, D ⁇ 3> and D ⁇ 4> output by the control unit 202
  • DN ⁇ 4:0> is the inverted signal of the first sub-control signal D ⁇ 4:0>, including DN ⁇ 0>, DN ⁇ 1>, DN ⁇ 2>, DN ⁇ 3> and DN ⁇ 4>, wherein D ⁇ 0> is inverted with DN ⁇ 0>, D ⁇ 1> is inverted with DN ⁇ 1>, D ⁇ 2> is inverted with DN ⁇ 2>, D ⁇ 3> is inverted with DN ⁇ 3>, and D ⁇ 4> is inverted with DN ⁇ 4>; in conjunction with Figure 2, D ⁇ 4> is used as the highest bit of the adjustment control signal, and D ⁇ 0> is used as the lowest bit of the adjustment control signal.
  • D ⁇ 4> is set to 1, D ⁇ 3> ⁇ D ⁇ 0> are set to 0, and the adjustment clock signal Clk_Out is obtained based on the adjustment control signal "10000"; in the second adjustment cycle, the values of D ⁇ 4> and D ⁇ 3> are adjusted based on the duty cycle of the adjustment clock signal Clk_Out; in the third adjustment cycle, the values of D ⁇ 3> and D ⁇ 2> are adjusted based on the duty cycle of the adjustment clock signal Clk_Out; in the fourth adjustment cycle, the values of D ⁇ 2> and D ⁇ 1> are adjusted based on the duty cycle of the adjustment clock signal Clk_Out; in the fifth adjustment cycle, the values of D ⁇ 1> and D ⁇ 0> are adjusted based on the duty cycle of the adjustment clock signal Clk_Out, so that in the five adjustment cycles, the adjustment clock signal with the duty cycle of the initial clock signal adjusted is quickly obtained based on the binary search algorithm.
  • the duty cycle adjustment circuit obtained in this embodiment obtains DN ⁇ 4:0> by inverting D ⁇ 4:0>, and then controls the second selection unit 220 and the third selection unit 230 to output corresponding adjustment control signals based on the selection signal to implement the application of the binary search algorithm.
  • the first selection unit group 210 is controlled based on the selection signal to select the output D ⁇ 4:0> or DN ⁇ 4:0>, so that the switch of the NMOS tube can be adjusted by outputting data "1", and the switch of the PMOS tube can be adjusted by outputting data "0".
  • a search cutoff signal Count is generated, and the correction control module 103 enters the tracking mode based on the search cutoff signal Count.
  • the control unit 202 includes: a plurality of cascaded sub-control units 211, wherein the output terminal Q of the previous stage sub-control unit 211 is connected to the input terminal Shift of the next stage sub-control unit 211, and the input terminal Shift of the first stage sub-control unit is used to receive a high level; the output terminal Q of each stage sub-control unit 211 is used to output the corresponding first sub-control signal D ⁇ 4:0>; the tracking output terminal Uout/Dout of the next stage sub-control unit 211 is connected to the tracking input terminal Uin/Din of the previous stage sub-control unit 211, and the tracking input terminal of the last stage sub-control unit 211 is used to receive the initial tracking signal; the non-last stage sub-control unit 211 is correspondingly provided with a first type OR gate, and the last stage sub-control unit 211 is correspondingly provided with a second type OR gate, and one input terminal of the second type OR gate is connected to the last The output end of the first-level sub-
  • the data transmitted by the tracking input terminal Uin/Din and the tracking output terminal Uout/Dout of the sub-control unit 211 are used to adjust the first sub-control signal D ⁇ 4:0> output by the output terminal Q of each level of sub-control unit 211, and the search cutoff signal Count is used to stop the sub-control unit 211 from continuing to adjust the output first sub-control signal D ⁇ 4:0>.
  • control unit 202 is further configured to increase the first control signal group or decrease the first control signal group based on the search identification signal.
  • the correction control module 103 further includes: a tracking signal generating unit 601 for generating an initial tracking signal.
  • the tracking input terminal Uin/Din includes an increasing tracking input terminal Uin and a decreasing tracking input terminal Din.
  • the tracking output terminal Uout/Dout includes an increasing tracking output terminal Uout and a decreasing tracking output terminal Dout
  • the tracking signal generating unit 601 includes: a first tracking AND gate 401, one input terminal of which is connected to the output terminal of the first selector, and the other input terminal is used to receive the search cutoff signal Count, and the output terminal is connected to the increasing tracking input terminal Uin of the last-level sub-control unit 211; the first input terminal of the first selector is used to receive the identification signal corresponding to the adjusted adjustment clock signal, the second input terminal is used to receive the inverted signal of the identification signal corresponding to the adjusted adjustment clock signal, and the selection terminal is used to receive the selection signal; a second tracking AND gate 402, one input terminal of which is connected to the output terminal of the second selector, and the other input terminal is used to receive the search cutoff signal Count, and the output terminal is connected to the decreasing tracking input terminal Din of
  • the first selector and the second selector when the selection signal is at a high level, that is, the selection signal is "1”, the first selector and the second selector select the input signal corresponding to the first input terminal to generate output data; when the selection signal is at a low level, that is, the selection signal is "0", the first selector and the second selector select the input terminal signal corresponding to the second input terminal to generate output data.
  • the first selector when the selection signal is "1", the first selector generates output data based on the identification signal corresponding to the adjusted adjustment clock signal and inputs it to the first tracking AND gate 401, and the second selector generates output data based on the inverted signal of the identification signal corresponding to the adjusted adjustment clock signal and inputs it to the second tracking AND gate 402; when the selection signal is "0", the first selector generates output data based on the inverted signal of the identification signal corresponding to the adjusted adjustment clock signal and inputs it to the first tracking AND gate 401, and the second selector generates output data based on the identification signal corresponding to the adjusted adjustment clock signal and inputs it to the second tracking AND gate 402.
  • the sub-control unit 211 includes: a first NAND gate 501, one input end of which is connected to the increase tracking input terminal Uin, and one input end of which is connected to the output end of the fourth D flip-flop 540; the output end of the fourth D flip-flop 540 is also connected to the input end of the first inverter 551; a second NAND gate 502, one input end of which is connected to the decrease tracking input terminal Din, and one input end of which is connected to the output end of the first inverter 551; an XOR gate 520, one input end of which is connected to the increase tracking input terminal Uin, and one input end of which is connected to the decrease tracking input terminal Din; a second inverter 552, one input end of which is connected to the XOR gate 520
  • the output terminal of the third NAND gate 503, one input terminal is connected to the output terminal of the XOR gate 520, one input terminal receives the enable signal of the sub-control unit 211
  • the duty cycle correction module 101 includes: at least one first adjustment unit 901 and at least one second adjustment unit 902, and when the number of the first adjustment units 901 is greater than 1, the first adjustment units 901 are arranged in parallel, and when the number of the second adjustment units 902 is greater than 1, the second adjustment units are arranged in parallel.
  • the number of the first adjustment units 901 and the second adjustment units 902 corresponds to the number of bits of the adjustment control signal
  • each bit data of the adjustment control signal corresponds to the adjustment of the corresponding first adjustment unit 901 and the second adjustment unit 902.
  • the first adjustment unit 901 is configured to adjust the duty cycle of the initial clock signal Clk_In based on the first adjustment control signal CtrlAN ⁇ 4:0> and the second adjustment signal CtrlBN ⁇ 4:0> to generate the intermediate clock signal Clk_M;
  • the second adjustment unit 902 is configured to adjust the duty cycle of the intermediate clock signal Clk_M based on the inverted signal of the first adjustment control signal and the inverted signal of the second adjustment control signal to generate the adjusted clock signal Clk_Out.
  • the sizes of transistors in different first adjustment units 901 and second adjustment units 902 are different, and the duty cycle adjustment capabilities are also different.
  • the first adjustment unit 901 and the second adjustment unit 902 corresponding to CtrlA ⁇ 4>, CtrlB ⁇ 4>, CtrlAN ⁇ 4> and CtrlBN ⁇ 4> generated based on D ⁇ 4> and DN ⁇ 4> have the strongest adjustment capabilities
  • the first adjustment unit 901 and the second adjustment unit 902 corresponding to CtrlA ⁇ 3>, CtrlB ⁇ 3>, CtrlAN ⁇ 3> and CtrlBN ⁇ 3> generated based on D ⁇ 3> and DN ⁇ 3> have the second strongest adjustment capabilities
  • the first adjustment unit 901 and the second adjustment unit 902 corresponding to CtrlA ⁇ 0>, CtrlB ⁇ 0>, CtrlAN ⁇ 0> and CtrlBN ⁇ 0> generated based on D ⁇ 0> and DN ⁇ 0> have the weakest adjustment capabilities.
  • control signal of the second adjustment unit is adjusted by the inverted signal of the first adjustment control signal and the second control signal.
  • the third adjustment control signal and the fourth adjustment control signal can be directly generated based on the correction control module to serve as the control signal of the second adjustment unit, thereby realizing the control of the second adjustment unit.
  • the first adjustment unit 901 includes: a first control P-type transistor, a control end for receiving a corresponding second adjustment control signal CtrlBN ⁇ 4:0>, a first end for receiving a high level, and a second end connected to a first end of the first P-type transistor; the control end of the first P-type transistor is used to receive an initial clock signal Clk_In, and a second end is used to output an intermediate clock signal Clk_M; a first control N-type transistor, a control end for receiving a corresponding first adjustment control signal CtrlAN ⁇ 4:0>, a first end for receiving a low level, and a second end connected to a first end of the first N-type transistor; the control end of the first N-type transistor is used to receive an initial clock signal Clk_In, and a second end is used to output an intermediate clock signal Clk_M.
  • the second adjustment unit 902 includes: a second control P-type transistor, the control end is used to receive the inverted signal CtrlA ⁇ 4:0> of the corresponding first adjustment control signal, the first end is used to receive a high level, and the second end is connected to the first end of the second P-type transistor; the control end of the second P-type transistor is used to receive the intermediate clock signal Clk_M, and the second end is used to output the adjustment clock signal Clk_Out; a second control N-type transistor, the control end is used to receive the inverted signal CtrlB ⁇ 4:0> of the corresponding second adjustment control signal, the first end is used to receive a low level, and the second end is connected to the first end of the second N-type transistor; the control end of the second N-type transistor is used to receive the intermediate clock signal Clk_M, and the second end is used to output the adjustment clock signal Clk_Out.
  • a second control P-type transistor the control end is used to receive the inverted signal CtrlA ⁇ 4
  • FIG. 11 and FIG. 12 are specifically illustrated with one of the first adjustment units 901 and the second adjustment unit 902 in FIG. 10, respectively, ignoring the difference in the input control signal, and the remaining structures are applicable to other first adjustment units 901 and second adjustment units 902.
  • the duty cycle of the initial clock signal is greater than 50%
  • the duty cycle needs to be reduced at this time. That is, the first control P-type transistor in Figure 11 needs to be turned on step by step, and the first control N-type transistor needs to be completely turned off.
  • the second control N-type transistor in Figure 12 needs to be turned on step by step, and the second control P-type transistor needs to be completely turned off; that is, the pull-up capability of the first adjustment unit 901 is enhanced, and the pull-down capability of the second adjustment unit 902 is enhanced, which is reflected in the clock signal, that is, the duty cycle of the initial clock signal Clk_In is reduced to generate the adjustment clock signal Clk_Out.
  • the duty cycle of the initial clock signal is less than 50%
  • the duty cycle needs to be increased at this time. That is, the first control P-type transistor in Figure 11 needs to be completely turned off, and the first control N-type transistor needs to be turned on step by step.
  • the second control N-type transistor in Figure 12 needs to be completely turned off, and the second control P-type transistor needs to be turned on step by step; that is, the first The pull-down capability of the first adjustment unit 902 is enhanced, and the pull-up capability of the second adjustment unit 901 is enhanced, which is reflected in the clock signal, that is, the duty cycle of the initial clock signal Clk_In is increased to generate the adjusted clock signal Clk_Out.
  • D4 is set to 0 and D3 is set to 1, and the comparison result Comp is continued to be waited; and so on, until 5 cycles later, the search cutoff signal Count is pulled high, and the binary search stage is ended.
  • the control word is the control word closest to the 50% duty cycle; next, Uin and Din can start tracking the duty cycle changes of the clock.
  • the relevant structure of the tracking input terminal Uin/Din is not involved; after determining the first control signal group D ⁇ 4:0> based on the binary search algorithm, the relevant structure of the tracking input terminal Uin/Din is used to adjust the first control signal group D ⁇ 4:0> based on the duty cycle change of the clock signal, so as to generate a stable adjusted clock signal Clk_Out with a duty cycle that meets the preset duty cycle within a period of time.
  • the duty cycle adjustment circuit further includes: a phase error detection module 801 for detecting a phase difference between a plurality of adjustment clock signals Clk_Out, and generating a phase identification signal based on the phase difference; a mode selector 802, one input end of which is connected to the duty cycle detection module 102, and the other input end of which is connected to the phase error detection module 801; the mode selector 802 is configured to directly output an identification signal based on the mode selection signal, or to output an identification signal after converting the phase identification signal into a corresponding identification signal.
  • the mode selector 802 is used to select the duty cycle adjustment of a single output clock or the phase difference adjustment between multiple clocks, thereby realizing the multiplexing of the control unit 202, thereby realizing the adjustment of the clock duty cycle and the phase difference adjustment between the clocks based on the binary search algorithm, and saving the layout area of the control unit required for the phase difference adjustment between the clocks, thereby further enhancing the performance of the memory.
  • a binary search algorithm is combined to quickly obtain the adjustment amplitude of the initial clock signal, thereby obtaining an adjusted clock signal whose duty cycle satisfies a preset duty cycle, thereby shortening the acquisition time of the adjusted clock signal whose duty cycle satisfies the preset duty cycle, thereby improving the performance of the memory.
  • the “high level” can be provided by the power supply voltage inside the memory, and the “low level” can be achieved by coupling the ground terminal.
  • Another embodiment of the present disclosure provides a memory, including the duty cycle adjustment circuit provided in the above embodiment, and adjusting the duty cycle of the clock signal based on the duty cycle adjustment circuit to shorten the acquisition time of the adjusted clock signal whose duty cycle meets the preset duty cycle, thereby improving the performance of the memory.
  • the acquisition time of the adjusted clock signal whose duty cycle satisfies the preset duty cycle is shortened, thereby improving the performance of the memory.
  • the memory may be a storage unit or device based on a semiconductor device or component.
  • the memory device may be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

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Abstract

本公开涉及一种占空比调整电路及存储器，占空比调整电路包括：占空比校正模块，被配置为，基于调整控制信号调节初始时钟信号的占空比，以生成调整时钟信号；占空比检测模块，被配置为，获取调整时钟信号的占空比，并基于调整时钟信号的占空比生成标识信号；校正控制模块，被配置为，基于二进制搜索算法和标识信号的值，调整调整控制信号；占空比校正模块还被配置为，基于调整后的调整控制信号重新生成调整时钟信号，直至调整后的调整时钟信号的占空比满足预设占空比；标识信号用于表征调整时钟信号的占空比大于50％或小于50％。

Description

占空比调整电路及存储器
交叉引用
本公开要求于2022年11月14日递交的名称为“占空比调整电路及存储器”、申请号为202211419843.6的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开涉及半导体电路设计领域，特别涉及一种占空比调整电路及存储器。
背景技术
在各种电子系统中，为了控制其中的各个电子装置，如：中央处理器(CPU)、数位信号处理器(DSP)、微处理器(MPU)、微控制器(MCU)等处理器、动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)等存储器的操作以及使其彼此互相通讯，必须产生精确的时钟讯号作为时间基准。甚至在考量高频率系统时，还需要时钟信号的上升沿/下降沿具有较低抖动的稳定性。
占空比(Duty Cycle)决定了周期内工作时间与总时间的比值。占空比会连带影响需求的带宽(bandwidth)，因此是时钟信号的重要参数，并且精确、稳定的时钟信号需要提供固定的占空比。然而，随着电子装置变得越来越复杂，存在占空比锁定时间较长、架构局限丧失灵活性、适用频率受限、低稳定性等各种问题。
发明内容
本公开一实施例提供了一种占空比调整电路，包括：占空比校正模块，被配置为，基于调整控制信号调节初始时钟信号的占空比，以生成调整时钟信号；占空比检测模块，被配置为，获取调整时钟信号的占空比，并基于调整时钟信号的占空比生成标识信号；校正控制模块，被配置为，基于二进制搜索算法和标识信号的值，调整调整控制信号；占空比校正模块还被配置为，基于调整后的调整控制信号重新生成调整时钟信号，直至调整后的调整时钟信号的占空比满足预设占空比；标识信号用于表征调整时钟信号的占空比大于50％或小于50％。
例如，占空比检测模块包括：缓存单元，被配置为，接收并缓存调整时钟信号；转换单元，连接缓存单元，被配置为，基于调整时钟信号的高电平占空比和预设电压生成第一电压，并基于调整时钟信号的低电平占空比和预设电压生成第二电压；比较单元，连接转换单元，被配置为，比较第一电压和第二电压的电压大小，以生成标识信号。
例如，校正控制模块包括：驱动单元，被配置为，基于更新信号的有效脉冲，生成对应于标识信号的选择信号；控制单元，被配置为，采用二进制搜索算法，生成第一控制信号组，第一控制信号组中包括多个第一子控制信号；生成单元，被配置为，基于选择信号和第一控制信号组，生成调整控制信号。
例如，校正控制模块还包括：搜索标识选择器，选择端用于接收选择信号，第一输入端用于接收调整后的调整时钟信号对应的标识信号，第二输入端用于接收调整后的调整时钟信号对应的标识信号的反相信号，输出端用于输出搜索标识信号。
例如，驱动单元包括：第一D触发器，输入端用于接收标识信号，时钟端用于接收更新信号，输出端用于输出选择信号。
例如，调整控制信号包括第一调整控制信号和第二调整控制信号，生成单元，包括：第一选择单元组，包括多个第一选择单元，每一第一选择单元的第一输入端用于接收对应的 第一子控制信号，第二输入端接收相同的第一子控制信号的反相信号，第一选择单元组被配置为，基于选择信号输出第二控制信号组；第二选择单元，第一输入端用于接收第二控制信号组，第二输入端用于接收低电平，被配置为，基于选择信号生成第一调整控制信号；第三选择单元，第一输入端用于接收高电平，第二输入端用于接收第二控制信号组，被配置为，基于选择信号生成第二调整控制信号。
例如，控制单元包括：多个级联的子控制单元，其中，前一级子控制单元的输出端连接下一级子控制单元的输入端，第一级子控制单元的输入端用于接收高电平；每一级子控制单元的输出端用于输出相应的第一子控制信号；后一级子控制单元的追踪输出端连接前一级子控制单元的追踪输入端，最后一级子控制单元的追踪输入端用于接收初始追踪信号；非最后一级子控制单元对应设置第一类或门，最后一级子控制单元对应设置第二类或门；第二类或门的一输入端连接最后一级子控制单元的输出端，另一输入端连接第二D触发器的输出端；第二D触发器的输入端连接第二类或门的输出端，输出端连接第三D触发器的输出端，第三D触发器用于输出搜索截止信号；第一类或门的输出端连接对应的子控制单元的使能端，第一类或门的一输入端连接后一级第一类或门的输出端，另一输入端连接后一级子控制单元的输出端；最后一级第一类或门的一输入端连接最后一级子控制单元的输出端，另一输入端连接第二D触发器的输出端，且最后一级子控制单元的使能端连接第二D触发器的输出端。
例如，控制单元还被配置为，基于搜索标识信号增大第一控制信号组或减小第一控制信号组；校正控制模块，还包括：追踪信号生成单元，用于生成初始追踪信号。
例如，追踪输入端包括增大追踪输入端和减小追踪输入端，追踪输出端包括增大追踪输出端和减小追踪输出端，追踪信号生成单元，包括：第一追踪与门，一输入端连接第一选择器的输出端，另一输入端用于接收搜索截止信号，输出端连接最后一级子控制单元的增大追踪输入端；第一选择器的第一输入端用于接收调整后的调整时钟信号对应的标识信号，第二输入端用于接收调整后的调整时钟信号对应的标识信号的反相信号，选择端用于接收选择信号；第二追踪与门，一输入端连接第二选择器的输出端，另一输入端用于接收搜索截止信号，输出端连接最后一级子控制单元的减小追踪输入端；第二选择器的第一输入端用于接收调整后的调整时钟信号对应的标识信号的反相信号，第二输入端用于接收调整后的调整时钟信号对应的标识信号，选择端用于接收选择信号。
例如，若选择信号为高电平，则第一选择器和第二选择器输出第一输入端对应的输入信号；若选择信号为低电平，则第一选择器和第二选择器输出第二输入端对应的输入信号。
例如，子控制单元，包括：第一与非门，一输入端连接增大追踪输入端，一输入端连接第四D触发器的输出端；第四D触发器的输出端还连接第一反相器的输入端；第二与非门，一输入端连接减小追踪输入端，一输入端连接第一反相器的输出端；异或门，一输入端连接增大追踪输入端，一输入端连接减小追踪输入端；第二反相器，输入端连接异或门的输出端；第三与非门，一输入端连接异或门的输出端，一输入端接收子控制单元的使能信号，一输入端连接第一反相器的输出端；第四与非门，一输入端连接第二反相器的输出端，一输入端连接第四D触发器的输出端，一输入端接收子控制单元的使能信号；第一与门，一输入端接收子控制单元的使能信号的反相信号，一输入端用于接收搜索标识信号，一输入端连接第四D触发器的输出端；第二与门，一输入端接收子控制单元的使能信号的反相信号，一输入端作为子控制单元的输入端，一输入端连接第一反相器的输出端；第一或非门，一输入端连接第一与非门的输出端，一输入端连接减小追踪输入端，输出端作为增大追踪输出端；第二或非门，一输入端连接第二与非门的输出端，一输入端连接增大追踪输入端，输出端作为减小追踪输出端；第三或非门，一输入端连接第一与门的输出端，一输入端连接第二与门的输出端；第五与非门，一输入端连接第三与非门的输出端，一输入端连接第四与非门的输出端，一输入端连接第三或非门的输出端；第四D触发器的输入端连接第五与非门的输出端，输出端用 于输出相应的第一子控制信号。
例如，占空比校正模块包括：至少一个第一调整单元和至少一个第二调整单元；第一调整单元被配置为，基于第一调整控制信号和第二调整控制信号调节初始时钟信号的占空比，以生成中间时钟信号；第二调整单元被配置为，基于第一调整控制信号的反相信号和第二调整控制信号的反相信号调节中间时钟信号的占空比，以生成调整时钟信号。
例如，第一调整单元包括：第一控制P型晶体管，控制端用于接收相应的第二调整控制信号，第一端用于接收高电平，第二端连接第一P型晶体管的第一端；第一P型晶体管的控制端用于接收初始时钟信号，第二端用于输出中间时钟信号；第一控制N型晶体管，控制端用于接收相应的第一调整控制信号，第一端用于接收低电平，第二端连接第一N型晶体管的第一端；第一N型晶体管的控制端用于接收初始时钟信号，第二端用于输出中间时钟信号；第二调整单元，包括：第二控制P型晶体管，控制端用于接收相应的第一调整控制信号的反相信号，第一端用于接收高电平，第二端连接第二P型晶体管的第一端；第二P型晶体管的控制端用于接收中间时钟信号，第二端用于输出调整时钟信号；第二控制N型晶体管，控制端用于接收相应的第二调整控制信号的反相信号，第一端用于接收低电平，第二端连接第二N型晶体管的第一端；第二N型晶体管的控制端用于接收中间时钟信号，第二端用于输出调整时钟信号。
例如，占空比调整电路还包括：相位误差检测模块，用于检测多个调整时钟信号之间的相位差，并基于相位差生成相位标识信号；模式选择器，一输入端连接占空比检测模块，另一输入端连接相位误差检测模块，模式选择器被配置为，基于模式选择信号直接输出标识信号，或将相位标识信号转化为相应的标识信号后，输出标识信号。
本公开另一实施例还提供了一种存储器，包括上述实施例提供的占空比调整电路，并基于占空比调整电路调整时钟信号的占空比。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的占空比调整电路的结构示意图；
图2为本公开一实施例提供的二进制搜索算法的原理示意图；
图3为本公开一实施例提供的占空比检测模块的结构示意图；
图4为本公开一实施例提供的校正控制模块的结构示意图；
图5为本公开一实施例提供的驱动单元的结构示意图；
图6为本公开一实施例提供的生成单元的结构示意图；
图7为本公开一实施例提供的控制单元、搜索标识选择器和追踪信号生成单元的结构示意图；
图8为本公开一实施例提供的控制单元的具体结构示意图；
图9为本公开一实施例提供的每一子控制单元的具体结构示意图；
图10为本公开一实施例提供的占空比校正模块的结构示意图；
图11为本公开一实施例提供的第一调整单元的结构示意图；
图12为本公开一实施例提供的第二调整单元的结构示意图；
图13为本公开一实施例提供的具备相位误差检测模块和模式选择器的占空比调整电路的结构示意图。
具体实施方式
由背景技术可知，占空比(Duty Cycle)决定了周期内工作时间与总时间的比值。占空比会连带影响需求的带宽(bandwidth)，因此是时钟信号的重要参数，并且精确、稳定的时钟信号需要提供固定的占空比。
本公开一实施例提供了一种占空比调整电路，以缩短占空比满足预设占空比的调整时钟信号的获取时间，从而提高存储器的性能。
本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本实施例提供的占空比调整电路的结构示意图，图2为本实施例提供的二进制搜索算法的原理示意图，图3为本实施例提供的占空比检测模块的结构示意图，图4为本实施例提供的校正控制模块的结构示意图，图5为本实施例提供的驱动单元的结构示意图，图6为本实施例提供的生成单元的结构示意图，图7为本实施例提供的控制单元、搜索标识选择器和追踪信号生成单元的结构示意图，图8为本实施例提供的控制单元的具体结构示意图，图9为本实施例提供的每一子控制单元的具体结构示意图，图10为本实施例提供的占空比校正模块的结构示意图图11为本实施例提供的第一调整单元的结构示意图，图12为本实施例提供的第二调整单元的结构示意图，图13为本实施例提供的具备相位误差检测模块和模式选择器的占空比调整电路的结构示意图，以下结合附图对本实施例提供的占空比调整电路进行详细说明，具体如下：
参考图1，占空比调整电路，包括：
占空比校正模块101，被配置为，基于调整控制信号调节初始时钟信号Clk_In的占空比，以生成调整时钟信号Clk_Out。
占空比检测模块102，被配置为，获取调整时钟信号Clk_Out的占空比，并基于调整时钟信号的占空比生成标识信号。
校正控制模块103，被配置为，基于二进制搜索算法和标识信号的值，调整调整控制信号。
占空比校正模块101还被配置为，基于调整后的调整控制信号重新生成调整时钟信号Clk_Out，直至调整后的调整时钟信号Clk_Out的占空比满足预设占空比。
其中，标识信号用于表征调整时钟信号Clk_Out的占空比大于50％或小于50％；在一个例子中，若调整时钟信号Clk_Out的占空比大于50％，标识信号的值为“0”；若调整时钟信号Clk_Out的占空比小于50％，标识信号的值为“1”；需要说明的是，在其他实施例中，若调整时钟信号的占空比大于50％，标识信号的值可以设置为“1”；若调整时钟信号的占空比小于50％，标识信号的值可以设置为“0”。
对于本实施例提供的占空比调整电路，占空比检测模块102不断基于调整时钟信号 Clk_Out的占空比调节标识信号，校正控制模块103基于标识信号的值，通过二进制搜索算法，调整生成的调整控制信号，占空比校正模块101不断基于调整控制信号调节初始时钟信号Clk_In的占空比，以生成占空比满足预设占空比的调整时钟信号Clk_Out；其中，占空比校正模块101基于不同的调整控制信号，改变对初始时钟信号Clk_In的占空比的调节幅度。
对于上述提及的“二进制搜索算法”，本实施例以五位的调整控制信号为例进行具体说明，参考图2，调整控制信号的初始值设置为“10000”，在对调整时钟信号Clk_Out进行一次调节后，基于调节后的调整时钟信号Clk_Out对应的标识信号，调节调整控制信号的值为“11000”或“01000”；在对调整时钟信号Clk_Out进行二次调节后，基于调节后的调整时钟信号Clk_Out对应的标识信号，调节调整控制信号的值为“11100”、“10100”、“01100”或“00100”；在对调整时钟信号Clk_Out进行三次调节后，基于调节后的调整时钟信号Clk_Out对应的标识信号，调节调整控制信号的值为“11110”、“11010”、“10110”、“10010”、“01110”、“01010”、“00110”或“00010”；在对调整时钟信号Clk_Out进行四次调节后，基于调节后的调整时钟信号Clk_Out对应的标识信号，调节调整控制信号的值为“11111”、“11101”、“11011”、“11001”、“10111”、“10101”、“10011”、“10001”、“01111”、“01101”、“01011”、“01001”“00111”、“00101”、“00011”或“00001”，从而获取占空比满足预设占空比的调整时钟信号Clk_Out。需要说明的是，本实施例以调整控制信号为5bit数据为例进行详细说明，并不构成对本实施例的限定，在其他实施例中，可以基于需要获取的调整时钟信号Clk_Out或预设占空比的精度，选择调整控制信号的数据长度；还需要说明的是，在本实施例中，预设占空比为50％±1％。
对于本实施例提供的占空比调整电路，通过结合二进制搜索算法，以快速获取对初始时钟信号的调节幅度，从而获取占空比满足预设占空比的调整时钟信号，缩短了占空比满足预设占空比的调整时钟信号的获取时间，从而提高存储器的性能。
例如，在调整控制信号为5bit数据时，通过二进制搜索算法，在五个调整周期内可获取对应的5bit调整控制信号，以使生成的调整时钟信号的占空比满足预设占空比，相对于步进式调节调整控制信号以逐步增大调整时钟信号的占空比的方式，极大节约了占空比满足预设占空比的调整时钟信号的获取时间。
对于本实施例提供的占空比检测模块102，在一些实施例中，参考图3，占空比检测模块102，包括：缓存单元301，被配置为，接收并缓存调整时钟信号Clk_Out；转换单元302，连接缓存单元301，被配置为，基于调整时钟信号Clk_Out的高电平占空比和预设电压生成第一电压，并基于调整时钟信号的低电平占空比和预设电压生成第二电压；比较单元303，连接转换单元302，被配置为，比较第一电压和第二电压的电压大小，以生成标识信号。在一个例子中，缓存单元301输出调整时钟信号Clk_Out和反相调整时钟信号，转换单元302基于调整时钟信号Clk_Out的高电平占空比和预设电压生成第一电压，并基于反相调整时钟信号的的高电平占空比和预设电压生成第二电压，即基于调整时钟信号Clk_Out的低电平占空比和预设电压生成第二电压。
对于转换单元302，假设调整时钟信号Clk_Out的高电平占空比为C1，低电平占空比为C2，此时，第一电压＝预设电压*C1，第二电压＝预设电压*C2，且C1+C2＝1；在具体的应用中，预设电压可以采用存储器的内部电源电压或外部电压设置，预设电压的值可以为任意电压值。
在一些实施例中，占空比检测模块102还包括：滤波单元304，设置于转换单元302和比较单元303的连接通路中，滤波单元304用于过滤第一电压和第二电压的杂波信号，以确保比较单元303生成标识信号的准确性。
对于本实施例提供的校正控制模块103，在一些实施例中，参考图4，校正控制模块 103，包括：驱动单元201，被配置为，基于更新信号的有效脉冲，生成对应于标识信号的选择信号；控制单元202，被配置为，采用二进制搜索算法，生成第一控制信号组，第一控制信号组中包括多个第一子控制信号；生成单元203，被配置为，基于选择信号和第一控制信号组，生成调整控制信号。需要说明的是，驱动单元201最开始接收的标识信号基于初始调整控制信号Clk_Out产生，即对应于初始时钟信号Clk_In的标识信号，在后续调节过程中，即使输入至驱动单元201的标识信号改变，由于更新信号的有效脉冲已经不再发送，选择信号亦不会发生变化。
对于驱动单元201，在一个例子中，参考图5，驱动单元201包括：第一D触发器，输入端用于接收标识信号，时钟端用于接收更新信号，输出端用于输出选择信号。具体地，当第一D触发器接收的更新信号产生有效脉冲，选择信号基于标识信号生成，当标识信号的值为“1”，对应生成的选择信号的值为“1”，当标识信号的值为“0”，对应生成的选择信号的值为“0”。需要说明的是，更新信号的有效脉冲在对初始时钟信号Clk_In的调节过程中只产生一次，用于记录初始时钟信号Clk_In的占空比信息，并基于初始时钟信号Clk_In的占空比信息生成相应的选择信号，以供后续实现对初始时钟信号Clk_In的占空比调节。
在一个例子中，在初始时钟信号信号Clk_In第一次到来，且校正控制模块103未启动时，初始时钟信号Clk_In经过具有初始值的占空比校正模块101生成初始调整控制信号，初始调整信号基于占空比检测模块102得到初始的标识信号，初始的标识信号在更新信号的有效脉冲作用下，生成选择信号。
对于生成单元203，参考图6，在一个例子中，调整控制信号包括第一调整控制信号和第二调整控制信号，通过两种不同的调整控制信号对占空比调整模块101的控制调节，以实现时钟信号上升沿和下降沿的调节，从而实现对时钟信号的占空比调节。在本示例中，生成单元203，包括：第一选择单元组210，包括多个第一选择单元，每一第一选择单元的第一输入端用于接收对应的第一子控制信号D<4:0>，第二输入端接收相同的第一子控制信号的反相信号DN<4:0>，第一选择单元组210被配置为，基于选择信号输出第二控制信号组Lsel<4:0>，第二选择单元220，第一输入端用于接收第二控制信号组，第二输入端用于接收低电平，第二选择单元220被配置为基于选择信号生成第一调整控制信号CtrlAN<4:0>；第三选择单元230，第一输入端用于接收高电平，第二输入端用于接收第二控制信号组Lsel<4:0>，第三选择单元230被配置为，基于选择信号生成第二调整控制信号CtrlBN<4:0>。
需要说明的是，对于上述提及的第一选择单元、第二选择单元220和第三选择单元230，当选择信号为“1”时，第一选择单元、第二选择单元220和第三选择单元230选择第一输入端的输入信号生成输出数据；当选择信号为“0”时，第一选择单元、第二选择单元220和第三选择单元230选择第二输入端的输入信号生成输出数据。具体地，当选择信号为“1”时，第一选择单元组210选择第一子控制信号D<4:0>输出第二控制信号组Lsel<4:0>，第二选择单元220基于高电平输出第一调整控制信号CtrlAN<4:0>，第三选择单元230基于第二控制信号组Lsel<4:0>输出第二调整控制信号CtrlBN<4:0>；当选择信号为“0”时，第一选择单元组210选择第一子控制信号的反相信号DN<4:0>输出第二控制信号组Lsel<4:0>，第二选择单元220基于第二控制信号组Lsel<4:0>输出第一调整控制信号CtrlAN<4:0>，第三选择单元230基于低电平输出第二调整控制信号CtrlBN<4:0>。
在一些实施例中，参考图7，校正控制模块103，还包括：搜索标识选择器602，选择端用于接收选择信号，第一输入端用于接收调整后的调整时钟信号对应的标识信号，第二输入端用于接收调整后的调整时钟信号对应的标识信号的反相信号，输出端用于输出搜索标识信号Comp。其中，搜索标识信号Comp用于表征下一状态的调整时钟信号Clk_Out的占空比大于50％或小于50％。
结合图7，其中，第一子控制信号D<4:0>即控制单元202输出的五位控制信号D<0>、D<1>、D<2>、D<3>和D<4>，DN<4:0>为第一子控制信号D<4:0>的反相信号，包括DN<0>、DN<1>、DN<2>、DN<3>和DN<4>，其中，D<0>与DN<0>反相，D<1>与DN<1>反相，D<2>与DN<2>反相，D<3>与DN<3>反相，D<4>与DN<4>反相；结合图2，其中D<4>作为调整控制信号的最高位，D<0>作为调整控制信号的最低位。
初始状态下，D<4>置1，D<3>～D<0>取0，基于调整控制信号“10000”获取调整时钟信号Clk_Out；在第二个调整周期中，基于调整时钟信号Clk_Out的占空比调整D<4>和D<3>的值；在第三个调整周期中，基于调整时钟信号Clk_Out的占空比调整D<3>和D<2>的值；在第四个调整周期中，基于调整时钟信号Clk_Out的占空比调整D<2>和D<1>的值；在第五个调整周期中，基于调整时钟信号Clk_Out的占空比调整D<1>和D<0>的值，从而在五个调整周期中，基于二进制搜索算法快速获取对初始时钟信号占空比调节的调整时钟信号。
需要说明的是，由于二进制搜索电路的D4端(也即最高位)只能输出1时才有效，基于这一特性，参考图6，本实施例提供的占空比调整电路通过对D<4:0>进行反相后获取DN<4:0>，然后基于选择信号控制第二选择单元220和第三选择单元230输出相应调整控制信号以实现二进制搜索算法的应用，另外，基于选择信号控制第一选择单元组210选择输出D<4:0>或DN<4:0>，从而既可以通过输出数据“1”对NMOS管的开关进行调节，也可以通过输出数据“0”对PMOS管的开关进行调节。
在一些实施例中，当校正控制模块103输出相应的调整控制信号以输出占空比满足预设占空比的调整时钟信号Clk_Out后，产生搜索截止信号Count，校正控制模块103基于搜索截止信号Count进入追踪模式，参考图7～图9，对本实施例提供的控制单元202进行详细说明，具体如下：
参考图7和图8，控制单元202，包括：多个级联的子控制单元211，其中，前一级子控制单元211的输出端Q连接下一级子控制单元211的输入端Shift，第一级子控制单元的输入端Shift用于接收高电平；每一级子控制单元211的输出端Q用于输出相应的第一子控制信号D<4:0>；后一级子控制单元211的追踪输出端Uout/Dout连接前一级子控制单元211的追踪输入端Uin/Din，最后一级子控制单元211的追踪输入端用于接收初始追踪信号；非最后一级子控制单元211对应设置第一类或门，最后一级子控制单元211对应设置第二类或门，第二类或门的一输入端连接最后一级子控制单元211的输出端，另一输入端连接第二D触发器622的输出端；第二D触发器622的输入端连接第二类或门的输出端，输出端连接第三D触发器623的输出端，第三D触发器623的输出端用于输出搜索截止信号Count；第一类或门的输出端连接对应的子控制单元的使能端Enable，第一类或门的一输入端连接后一级第一类或门的输出端，另一输入端连接后一级子控制单元的输出端Q；最后一级第一类或门的一输入端连接最后一级子控制单元211的输出端，另一输入端连接第二D触发器622的输出端，且最后一级子控制单元211的使能端Enable连接第二D触发器622的输出端。
其中，子控制单元211的追踪输入端Uin/Din和追踪输出端Uout/Dout传输的数据用于调整每一级子控制单元211的输出端Q输出的第一子控制信号D<4:0>，搜索截止信号Count用于停止子控制单元211继续调整输出的第一子控制信号D<4:0>。
在一些实施例中，参考图7，控制单元202还被配置为，基于搜索标识信号增大第一控制信号组或减小第一控制信号组。
在一些实施例中，参考图7，校正控制模块103，还包括：追踪信号生成单元601，用于生成初始追踪信号。
在一个例子中，追踪输入端Uin/Din包括增大追踪输入端Uin和减小追踪输入端Din， 追踪输出端Uout/Dout包括增大追踪输出端Uout和减小追踪输出端Dout，追踪信号生成单元601，包括：第一追踪与门401，一输入端连接第一选择器的输出端，另一输入端用于接收搜索截止信号Count，输出端连接最后一级子控制单元211的增大追踪输入端Uin；第一选择器的第一输入端用于接收调整后的调整时钟信号对应的标识信号，第二输入端用于接收调整后的调整时钟信号对应的标识信号的反相信号，选择端用于接收选择信号；第二追踪与门402，一输入端连接第二选择器的输出端，另一输入端用于接收搜索截止信号Count，输出端连接最后一级子控制单元211的减小追踪输入端Din；第二选择器的第一输入端用于接收调整后的调整时钟信号对应的标识信号的反相信号，第二输入端用于接收调整后的调整时钟信号对应的标识信号，选择端用于接收选择信号。
需要说明的是，对于上述提及的第一选择器和第二选择器，当选择信号为高电平，即选择信号为“1”时，第一选择器和第二选择器选择第一输入端对应的输入信号生成输出数据；当选择信号为低电平，即选择信号为“0”时，第一选择器和第二选择器选择第二输入端对应的输入端信号生成输出数据。具体地，当选择信号为“1”时，第一选择器基于调整后的调整时钟信号对应的标识信号生成输出数据输入至第一追踪与门401，第二选择器基于调整后的调整时钟信号对应的标识信号的反相信号生成输出数据输入置第二追踪与门402；当选择信号为“0”时，第一选择器基于调整后的调整时钟信号对应的标识信号的反相信号生成输出数据输入至第一追踪与门401，第二选择器基于调整后的调整时钟信号对应的标识信号生成输出数据输入置第二追踪与门402。
需要说明的是，在对初始时钟信号Clk_In的占空比调整以调整时钟信号Clk_Out的过程中，不涉及追踪输入端Uin/Din的相关结构，去掉追踪输入端Uin/Din的相关结构后仍可实现基于二进制搜索算法获取占空比满足预设占空比的调整时钟信号Clk_Out。
对于每一子控制单元211，参考图9，在一个例子中，子控制单元211，包括：第一与非门501，一输入端连接增大追踪输入端Uin，一输入端连接第四D触发器540的输出端；第四D触发器540的输出端还连接第一反相器551的输入端；第二与非门502，一输入端连接减小追踪输入端Din，一输入端连接第一反相器551的输出端；异或门520，一输入端连接增大追踪输入端Uin，一输入端连接减小追踪输入端Din；第二反相器552，输入端连接异或门520的输出端；第三与非门503，一输入端连接异或门520的输出端，一输入端接收子控制单元211的使能信号(即作为子控制单元211的使能端Enable)，一输入端连接第一反相器551的输出端；第四与非门504，一输入端连接第二反相器552的输出端，一输入端连接第四D触发器540的输出端，一输入端接收子控制单元211的使能信号(即作为子控制单元211的使能端Enable)；第一与门511，一输入端接收子控制单元的使能信号的反相信号(即作为子控制单元211的反相使能端Enable-)，一输入端用于接收搜索标识信号Comp，一输入端连接第四D触发器540的输出端；第二与门512，一输入端接收子控制单元211的使能信号的反相信号(即作为子控制单元211的反相使能端Enable-)，一输入端作为子控制单元211的输入端，一输入端连接第一反相器551的输出端；第一或非门531，一输入端连接第一与非门501的输出端，一输入端连接减小追踪输入端Din，输出端作为增大追踪输出端Uout；第二或非门532，一输入端连接第二与非门502的输出端，一输入端连接增大追踪输入端Uin，输出端作为减小追踪输出端Dout；第三或非门533，一输入端连接第一与门511的输出端，一输入端连接第二与门512的输出端；第五与非门505，一输入端连接第三与非门503的输出端，一输入端连接第四与非门504的输出端，一输入端连接第三或非门533的输出端；第四D触发器540的输入端连接第五与非门505的输出端，输出端用于输出相应的第一子控制信号。
需要说明的是，除了图8和图9示意的二进制搜索结构，其他二进制搜索结构也可应用于本实施例中以作为控制单元202实现本实施例中所需的二进制搜索算法。
对于本实施例提供的占空比校正模块101，参考图10，在一个例子中，占空比校正模块101，包括：至少一个第一调整单元901和至少一个第二调整单元902，且当第一调整单元901的数量大于1时，第一调整单元901之间为并联设置，当第二调整单元902的数量大于1时，第二调整单元之间为并联设置，需要说明的是，第一调整单元901和第二调整单元902的数量对应于调整控制信号的比特数，且调整控制信号的每一比特数据对应调整相应的第一调整单元901和第二调整单元902。
其中，第一调整单元901被配置为，基于第一调整控制信号CtrlAN<4:0>和第二调整信号CtrlBN<4:0>调节初始时钟信号Clk_In的占空比，以生成中间时钟信号Clk_M；第二调整单元902被配置为，基于第一调整控制信号的反相信号和第二调整控制信号的反相信号调节中间时钟信号Clk_M的占空比，以生成调整时钟信号Clk_Out。
具体地，不同第一调整单元901和第二调整单元902中晶体管的尺寸不同，对占空比的调节能力也不同。基于D<4>和DN<4>生成的CtrlA<4>、CtrlB<4>、CtrlAN<4>和CtrlBN<4>对应控制的第一调整单元901和第二调整单元902中晶体管的调节能力最强，基于D<3>和DN<3>生成的CtrlA<3>、CtrlB<3>、CtrlAN<3>和CtrlBN<3>对应控制的第一调整单元901和第二调整单元902中晶体管的调节能力次之，依次类推，基于基于D<0>和DN<0>生成的CtrlA<0>、CtrlB<0>、CtrlAN<0>和CtrlBN<0>对应控制的第一调整单元901和第二调整单元902中晶体管的调节能力最弱。
需要说明的是，在本实施例第二调整单元的控制信号采用第一调整控制信号和第二控制信号的反相信号调节，在其他实施例中，可以基于校正控制模块直接产生第三调整控制信号和第四调整控制，以作为第二调整单元的控制信号，从而实现对第二调整单元的控制。
在一个具体的例子中，参考图11和图12，第一调整单元901，包括：第一控制P型晶体管，控制端用于接收相应的第二调整控制信号CtrlBN<4:0>，第一端用于接收高电平，第二端连接第一P型晶体管的第一端；第一P型晶体管的控制端用于接收初始时钟信号Clk_In，第二端用于输出中间时钟信号Clk_M；第一控制N型晶体管，控制端用于接收相应的第一调整控制信号CtrlAN<4:0>，第一端用于接收低电平，第二端连接第一N型晶体管的第一端；第一N型晶体管的控制端用于接收初始时钟信号Clk_In，第二端用于输出中间时钟信号Clk_M。
第二调整单元902，包括：第二控制P型晶体管，控制端用于接收相应的第一调整控制信号的反相信号CtrlA<4:0>，第一端用于接收高电平，第二端连接第二P型晶体管的第一端；第二P型晶体管的控制端用于接收中间时钟信号Clk_M，第二端用于输出调整时钟信号Clk_Out；第二控制N型晶体管，控制端用于接收相应的第二调整控制信号的反相信号CtrlB<4:0>，第一端用于接收低电平，第二端连接第二N型晶体管的第一端；第二N型晶体管的控制端用于接收中间时钟信号Clk_M，第二端用于输出调整时钟信号Clk_Out。需要说明的是，图11和图12分别以图10中的其中一个第一调整单元901和第二调整单元902进行具体图示，忽略输入的控制信号差异，其余结构适用于其他第一调整单元901和第二调整单元902。
具体地，假设初始时钟信号的占空比大于50％，此时需要减小占空比。即图11中第一控制P型晶体管需要逐级打开，第一控制N型晶体管需要全部关闭，图12中第二控制N型晶体管需要逐级打开，第二控制P型晶体管需要全部关闭；即第一调整单元901的上拉能力增强，第二调整单元902的下拉能力增强，反映到时钟信号上，即减小初始时钟信号Clk_In的占空比以生成调整时钟信号Clk_Out。假设初始时钟信号的占空比小于50％，此时需要增大占空比。即图11中第一控制P型晶体管需要全部关闭，第一控制N型晶体管需要逐级打开，图12中第二控制N型晶体管需要全部关闭，第二控制P型晶体管需要逐级打开；即第 一调整单元902的下拉能力增强，第二调整单元901的上拉能力增强，反映到时钟信号上，即增大初始时钟信号Clk_In的占空比以生成调整时钟信号Clk_Out。
更具体地，以初始占空比大于50％为例，由于初始时钟信号Clk_In的占空比大于50％，生成的标识信号为“0”，基于图4和图5可知，此时生成的选择信号为“0”，参考图6，将DN<4:0>的值传递给CtrlBN<4:0>；当第一个时钟来临时，基于图2所示的二进制搜索算法D4置为1，按照D<4:0>＝“10000”进行一次占空比校正，等待校正后的调整时钟信号Clk_Out的占空比的比较结果，即搜索标识信号Comp；若Comp＝1(标识信号＝0)，说明占空比仍大于50％；此时基于图2所示的二进制搜索算法将D3也置为1，继续减少占空比；若Comp＝0(标识信号＝1),说明占空比已经小于50％了，甚至可能调节过度了，因此基于图2所示的二进制搜索算法将D4置为0，D3置为1，继续等待比较结果Comp；以此类推，直到5个周期后，将搜索截止信号Count拉高，此时二进制搜索阶段结束，此时的控制字就是最接近50％占空比的控制字；接下来，Uin和Din就可以开始跟踪时钟的占空比变化。
以初始占空比小于50％为例，由于初始时钟信号Clk_In的占空比小于50％，生成的标识信号为“1”，基于图4和图5可知，此时生成的选择信号为“1”，参考图6，将D<4:0>的值传递给CtrlAN<4:0>；当第一个时钟来临时，基于图2所示的二进制搜索算法D4置为1，按照D<4:0>＝“10000”进行一次占空比校正，等待校正后的调整时钟信号Clk_Out的占空比的比较结果，即搜索标识信号Comp；若Comp＝1(标识信号＝1)，说明占空比仍小于50％；此时基于图2所示的二进制搜索算法将D3也置为1，继续增大占空比；若Comp＝0(标识信号＝0),说明占空比已经大于50％了，甚至可能调节过度了，因此基于图2所示的二进制搜索算法将D4置为0，D3置为1，继续等待比较结果Comp；以此类推，直到5个周期后，将搜索截止信号Count拉高，此时二进制搜索阶段结束,此时的控制字就是最接近50％占空比的控制字；接下来，Uin和Din就可以开始跟踪时钟的占空比变化。
需要说明的是，在对初始时钟信号Clk_In的占空比调整以调整时钟信号Clk_Out的过程中，不涉及追踪输入端Uin/Din的相关结构；基于二进制搜索算法确定第一控制信号组D<4:0>后，追踪输入端Uin/Din的相关结构用于基于时钟信号的占空比变化，调节第一控制信号组D<4:0>，以在一段时间内生成稳定且占空比满足预设占空比的调整时钟信号Clk_Out。
在一些实施例中，参考图13，占空比调整电路，还包括：相位误差检测模块801，用于检测多个调整时钟信号Clk_Out之间的相位差，并基于相位差生成相位标识信号，模式选择器802，一输入端连接占空比检测模块102，另一输入端连接相位误差检测模块801，模式选择器802被配置为，基于模式选择信号直接输出标识信号，或将相位标识信号转化为相应的标识信号后，输出标识信号。
通过模式选择器802选择对单一输出时钟的占空比调整或多时钟之间的相位差调整，从而实现了控制单元202的复用，从而基于二进制搜索算法实现对时钟占空比的调整和时钟之间的相位差调整，并节省了对时钟之间的相位差调整所需的控制单元的版图面积，从而进一步增强存储器的性能。
对于本实施例提供的占空比调整电路，通过结合二进制搜索算法，以快速获取对初始时钟信号的调节幅度，从而获取占空比满足预设占空比的调整时钟信号，缩短了占空比满足预设占空比的调整时钟信号的获取时间，从而提高存储器的性能。
需要说明的是，对于本实施例中提到的“高电平”和“低电平”，其中，“高电平”可通过存储器内部的电源电压提供，“低电平”可通过耦合接地端实现。
还需要说明的是，上述实施例所提供的占空比调整电路中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的占空比调整电路实施例。
本公开另一实施例提供一种存储器，包括上述实施例提供的占空比调整电路，并基于占空比调整电路调整时钟信号的占空比，以缩短占空比满足预设占空比的调整时钟信号的获取时间，从而提高存储器的性能。
具体地，通过结合二进制搜索算法，以快速获取对初始时钟信号的调节幅度，从而获取占空比满足预设占空比的调整时钟信号，缩短了占空比满足预设占空比的调整时钟信号的获取时间，从而提高存储器的性能。
在一些例子中，存储器可以是基于半导体装置或组件的存储单元或装置。例如，存储器装置可以是易失性存储器，例如动态随机存取存储器DRAM、同步动态随机存取存储器SDRAM、双倍数据速率同步动态随机存取存储器DDR SDRAM、低功率双倍数据速率同步动态随机存取存储器LPDDR SDRAM、图形双倍数据速率同步动态随机存取存储器GDDR SDRAM、双倍数据速率类型双同步动态随机存取存储器DDR2SDRAM、双倍数据速率类型三同步动态随机存取存储器DDR3SDRAM、双倍数据速率第四代同步动态随机存取存储器DDR4SDRAM、晶闸管随机存取存储器TRAM等；或者可以是非易失性存储器，例如相变随机存取存储器PRAM、磁性随机存取存储器MRAM、电阻式随机存取存储器RRAM等。
本领域的普通技术人员可以理解，上述各实施例是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。

Claims (15)

  1. 一种占空比调整电路，其特征在于，包括：
    占空比校正模块(101)，被配置为，基于调整控制信号调节初始时钟信号的占空比，以生成调整时钟信号；
    占空比检测模块(102)，被配置为，获取所述调整时钟信号的占空比，并基于所述调整时钟信号的占空比生成标识信号；
    校正控制模块(103)，被配置为，基于二进制搜索算法和所述标识信号的值，调整所述调整控制信号；
    所述占空比校正模块(101)还被配置为，基于调整后的所述调整控制信号重新生成所述调整时钟信号，直至调整后的所述调整时钟信号的占空比满足预设占空比；
    所述标识信号用于表征所述调整时钟信号的占空比大于50％或小于50％。
  2. 根据权利要求1所述的占空比调整电路，其特征在于，所述占空比检测模块(102)，包括：
    缓存单元(301)，被配置为，接收并缓存所述调整时钟信号；
    转换单元(302)，连接所述缓存单元(301)，被配置为，基于所述调整时钟信号的高电平占空比和预设电压生成第一电压，并基于所述调整时钟信号的低电平占空比和所述预设电压生成第二电压；
    比较单元(303)，连接所述转换单元(302)，被配置为，比较所述第一电压和所述第二电压的电压大小，以生成所述标识信号。
  3. 根据权利要求1或2所述的占空比调整电路，其特征在于，所述校正控制模块(103)，包括：
    驱动单元(201)，被配置为，基于更新信号的有效脉冲，生成对应于所述标识信号的选择信号；
    控制单元(202)，被配置为，采用所述二进制搜索算法，生成第一控制信号组，所述第一控制信号组中包括多个第一子控制信号；
    生成单元(203)，被配置为，基于所述选择信号和所述第一控制信号组，生成所述调整控制信号。
  4. 根据权利要求3所述的占空比调整电路，其特征在于，所述校正控制模块(103)，还包括：搜索标识选择器(602)，选择端用于接收所述选择信号，第一输入端用于接收调整后的所述调整时钟信号对应的所述标识信号，第二输入端用于接收调整后的所述调整时钟信号对应的所述标识信号的反相信号，输出端用于输出所述搜索标识信号。
  5. 根据权利要求3或4所述的占空比调整电路，其特征在于，所述驱动单元(201)，包括：第一D触发器，输入端用于接收所述标识信号，时钟端用于接收所述更新信号，输出端用于输出所述选择信号。
  6. 根据权利要求3～5任一项所述的占空比调整电路，其特征在于，所述调整控制信号包括第一调整控制信号和第二调整控制信号，所述生成单元，包括：
    第一选择单元组(210)，包括多个第一选择单元，每一第一选择单元的第一输入端用于接收对应的所述第一子控制信号，第二输入端接收相同的所述第一子控制信号的反相信号， 所述第一选择单元组被配置为，基于所述选择信号输出第二控制信号组；
    第二选择单元(220)，第一输入端用于接收所述第二控制信号组，第二输入端用于接收低电平，被配置为，基于所述选择信号生成所述第一调整控制信号；
    第三选择单元(230)，第一输入端用于接收高电平，第二输入端用于接收所述第二控制信号组，被配置为，基于所述选择信号生成所述第二调整控制信号。
  7. 根据权利要求3～6任一项所述的占空比调整电路，其特征在于，所述控制单元(202)，包括：
    多个级联的子控制单元(211)，其中，前一级子控制单元(211)的输出端连接下一级子控制单元(211)的输入端，第一级子控制单元(211)的输入端用于接收高电平；
    每一级子控制单元(211)的输出端用于输出相应的所述第一子控制信号；
    后一级子控制单元(211)的追踪输出端连接前一级子控制单元(211)的追踪输入端，最后一级子控制单元(211)的追踪输入端用于接收初始追踪信号；
    非最后一级子控制单元(211)对应设置第一类或门，最后一级子控制单元(211)对应设置第二类或门；
    所述第二类或门的一输入端连接最后一级子控制单元(211)的输出端，另一输入端连接第二D触发器(622)的输出端，所述第二D触发器(622)的输入端连接所述第二类或门的输出端，输出端连接第三D触发器(623)的输出端，所述第三D触发器(623)用于输出搜索截止信号；
    所述第一类或门的输出端连接对应的子控制单元的使能端，所述第一类或门的一输入端连接后一级第一类或门的输出端，另一输入端连接后一级子控制单元(211)的输出端；
    最后一级第一类或门的一输入端连接最后一级子控制单元(211)的输出端，另一输入端连接所述第二D触发器(622)的输出端，且最后一级子控制单元的使能端连接所述第二D触发器(622)的输出端。
  8. 根据权利要求7所述的占空比调整电路，其特征在于，包括：所述控制单元还被配置为，基于追踪搜索标识信号增大所述第一控制信号组或减小所述第一控制信号组，所述校正控制模块，还包括：追踪信号生成单元(601)，用于生成所述初始追踪信号。
  9. 根据权利要求8所述的占空比调整电路，其特征在于，所述追踪输入端包括增大追踪输入端和减小追踪输入端，所述追踪输出端包括增大追踪输出端和减小追踪输出端，所述追踪信号生成单元(601)，包括：
    第一追踪与门(401)，一输入端连接第一选择器的输出端，另一输入端用于接收所述搜索截止信号，输出端连接最后一级子控制单元(211)的增大追踪输入端；
    所述第一选择器的第一输入端用于接收调整后的所述调整时钟信号对应的所述标识信号，第二输入端用于接收调整后的所述调整时钟信号对应的所述标识信号的反相信号，选择端用于接收所述选择信号；
    第二追踪与门(402)，一输入端连接第二选择器的输出端，另一输入端用于接收所述搜索截止信号，输出端连接最后一级子控制单元(211)的减小追踪输入端；
    所述第二选择器的第一输入端用于接收调整后的所述调整时钟信号对应的所述标识信号的反相信号，第二输入端用于接收调整后的所述调整时钟信号对应的所述标识信号，选择端用于接收所述选择信号。
  10. 根据权利要求9所述的占空比调整电路，其特征在于，包括：
    若所述选择信号为高电平，则所述第一选择器和所述第二选择器输出第一输入端对应的输入信号；
    若所述选择信号为低电平，则所述第一选择器和所述第二选择器输出第二输入端对应的输入信号。
  11. 根据权利要求9所述的占空比调整电路，其特征在于，所述子控制单元(211)，包括：
    第一与非门(501)，一输入端连接所述增大追踪输入端，一输入端连接第四D触发器(540)的输出端；
    所述第四D触发器(540)的输出端还连接第一反相器(551)的输入端；
    第二与非门(502)，一输入端连接所述减小追踪输入端，一输入端连接所述第一反相器(551)的输出端；
    异或门(520)，一输入端连接所述增大追踪输入端，一输入端连接所述减小追踪输入端；
    第二反相器(552)，输入端连接所述异或门(520)的输出端；
    第三与非门(503)，一输入端连接所述异或门(520)的输出端，一输入端接收所述子控制单元(211)的使能信号，一输入端连接所述第一反相器(551)的输出端；
    第四与非门(504)，一输入端连接所述第二反相器(552)的输出端，一输入端连接所述第四D触发器(540)的输出端，一输入端接收所述子控制单元(211)的使能信号；
    第一与门(511)，一输入端接收所述子控制单元(211)的使能信号的反相信号，一输入端用于接收所述搜索标识信号，一输入端连接所述第四D触发器(540)的输出端；
    第二与门(512)，一输入端接收所述子控制单元(211)的使能信号的反相信号，一输入端作为所述子控制单元的输入端，一输入端连接所述第一反相器(551)的输出端；
    第一或非门(531)，一输入端连接所述第一与非门(501)的输出端，一输入端连接所述减小追踪输入端，输出端作为所述增大追踪输出端；
    第二或非门(532)，一输入端连接所述第二与非门(502)的输出端，一输入端连接所述增大追踪输入端，输出端作为所述减小追踪输出端；
    第三或非门(533)，一输入端连接所述第一与门(511)的输出端，一输入端连接所述第二与门(512)的输出端；
    第五与非门(5055)，一输入端连接所述第三与非门(503)的输出端，一输入端连接所述第四与非门(504)的输出端，一输入端连接所述第三或非门(533)的输出端；
    所述第四D触发器(540)的输入端连接所述第五与非门(505)的输出端，输出端用于输出相应的所述第一子控制信号。
  12. 根据权利要求6～11任一项所述的占空比调整电路，其特征在于，所述占空比校正模块，包括：
    至少一个第一调整单元(901)和至少一个第二调整单元(902)；
    所述第一调整单元(901)被配置为，基于所述第一调整控制信号和所述第二调整控制信号调节所述初始时钟信号的占空比，以生成中间时钟信号；
    所述第二调整单元(902)被配置为，基于所述第一调整控制信号的反相信号和所述第二 调整控制信号的反相信号调节所述中间时钟信号的占空比，以生成所述调整时钟信号。
  13. 根据权利要求12所述的占空比调整电路，其特征在于，包括：
    所述第一调整单元(901)，包括：
    第一控制P型晶体管，控制端用于接收相应的所述第二调整控制信号，第一端用于接收高电平，第二端连接第一P型晶体管的第一端；
    所述第一P型晶体管的控制端用于接收所述初始时钟信号，第二端用于输出所述中间时钟信号；
    第一控制N型晶体管，控制端用于接收相应的所述第一调整控制信号，第一端用于接收低电平，第二端连接第一N型晶体管的第一端；
    所述第一N型晶体管的控制端用于接收所述初始时钟信号，第二端用于输出所述中间时钟信号；
    所述第二调整单元(902)，包括：
    第二控制P型晶体管，控制端用于接收相应的所述第一调整控制信号的反相信号，第一端用于接收高电平，第二端连接第二P型晶体管的第一端；
    所述第二P型晶体管的控制端用于接收所述中间时钟信号，第二端用于输出所述调整时钟信号；
    第二控制N型晶体管，控制端用于接收相应的所述第二调整控制信号的反相信号，第一端用于接收低电平，第二端连接第二N型晶体管的第一端；
    所述第二N型晶体管的控制端用于接收所述中间时钟信号，第二端用于输出所述调整时钟信号。
  14. 根据权利要求1～13任一项所述的占空比调整电路，其特征在于，还包括：
    相位误差检测模块(801)，用于检测多个所述调整时钟信号之间的相位差，并基于所述相位差生成相位标识信号；
    模式选择器(802)，一输入端连接所述占空比检测模块(102)，另一输入端连接所述相位误差检测模块(801)，所述模式选择器(802)被配置为，基于模式选择信号直接输出所述标识信号，或将所述相位标识信号转化为相应的所述标识信号后，输出所述标识信号。
  15. 一种存储器，其特征在于，包括权利要求1～14任一项所述的占空比调整电路，并基于所述占空比调整电路调整时钟信号的占空比。
PCT/CN2023/077269 2022-11-14 2023-02-20 占空比调整电路及存储器 Ceased WO2024103554A1 (zh)

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