WO2024099180A1 - 64b/66b编码信号的处理方法、通信设备和存储介质 - Google Patents

64b/66b编码信号的处理方法、通信设备和存储介质 Download PDF

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WO2024099180A1
WO2024099180A1 PCT/CN2023/128550 CN2023128550W WO2024099180A1 WO 2024099180 A1 WO2024099180 A1 WO 2024099180A1 CN 2023128550 W CN2023128550 W CN 2023128550W WO 2024099180 A1 WO2024099180 A1 WO 2024099180A1
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coded
block
coding
coding block
signal
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PCT/CN2023/128550
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English (en)
French (fr)
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苑岩
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中兴通讯股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/06—Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]

Definitions

  • the present application relates to the field of communication technology, and in particular to a 64b/66b coded signal processing method, communication equipment and storage medium.
  • 64b/66b coded signals are generally fixed-rate signals, and their rate often needs to be reduced before they are sent. For example, before loading a flexible Ethernet client signal (FlexE Client signal) into a flexible Ethernet group signal (FlexE Group signal), the rate of the flexible Ethernet client signal needs to be reduced before the reduced-rate flexible Ethernet client signal can be loaded into the time slot of the flexible Ethernet group signal; in addition, before loading a 64b/66b coded signal into an optical data unit signal (ODU signal) of an optical transport network, the rate of the 64b/66b coded signal can be reduced before loading it into the optical data unit signal, so that the signal rate of the optical data unit can be lower.
  • FlexE Client signal Flexible Ethernet client signal
  • FlexE Group signal flexible Ethernet group signal
  • OFD signal optical data unit signal
  • the 64b/66b coded signal there are two main ways to reduce the 64b/66b coded signal: the first is to delete the 64b/66b control coded block containing 8 idle control characters; the second is to delete one of two consecutive 64b/66b coded blocks containing ordered set control information and whose contents are exactly the same. Both methods are only applicable to the case where the rate of the media access control frame is not too high. If the rate of the media access control frame is too high and close to its physical rate limit, there will be no deletable 64b/66b coded blocks that meet the above two conditions for a long time, and the 64b/66b coded blocks deleted by the above methods cannot be restored to the original position. Therefore, there is an urgent need for a method that can reduce the rate by deleting specific 64b/66b coded blocks when the rate of the media access control frame is very high, and the deleted 64b/66b coded blocks can be correctly restored to the original position.
  • the embodiments of the present application provide a 64b/66b coded signal processing method, communication device, computer-readable storage medium and computer program product, which can still reduce the rate by deleting specific 64b/66b coded blocks when the rate of the media access control frame is very high, and facilitate the recovery of the original 64b/66b coded signal.
  • an embodiment of the present application provides a method for processing a 64b/66b coded signal, the method comprising:
  • the 64b/66b coded signal includes a plurality of 64b/66b coded blocks, wherein the plurality of 64b/66b coded blocks include at least one of the following: an S coded block, a T coded block, a C coded block, a D coded block, or an E coded block;
  • an embodiment of the present application provides a communication device, including a sending module and a receiving module; wherein:
  • the sending module is used to: obtain a 64b/66b coded signal, wherein the 64b/66b coded signal includes a plurality of 64b/66b coded blocks, wherein the plurality of 64b/66b coded blocks include at least one of the following: an S coded block, a T coded block, a C coded block, a D coded block or an E coded block; traverse each of the 64b/66b coded blocks in the 64b/66b coded signal, and when the currently traversed 64b/66b coded block is an S coded block and a deletion condition is satisfied, delete the S coded block to obtain a 64b/66b coded signal with a reduced rate; and send the 64b/66b coded signal with a reduced rate;
  • the receiving module is used to: receive the reduced rate 64b/66b coded signal; traverse each 64b/66b coded block in the reduced rate 64b/66b coded signal; and when the currently traversed 64b/66b coded block is the D coded block and the condition allowing addition is met, add the S coded block before the currently traversed 64b/66b coded block to obtain the 64b/66b coded signal at the restored rate.
  • an embodiment of the present application provides a communication device, including:
  • At least one memory for storing at least one program
  • an embodiment of the present application provides a computer-readable storage medium, which stores a program executable by a processor, and when the program executable by the processor is executed by the processor, it is used to implement the processing method of the 64b/66b encoded signal as described in the first aspect.
  • an embodiment of the present application provides a computer program product, comprising a computer program or computer instructions, wherein the computer program or the computer instructions are stored in a computer-readable storage medium, a processor of a computer device reads the computer program or the computer instructions from the computer-readable storage medium, and the processor executes the computer program or the computer instructions, so that the computer device performs the 64b/66b encoded signal processing method as described in the first aspect.
  • the S coding blocks that meet the preset deletion permission conditions in the 64b/66b coded signal are deleted, thereby obtaining a 64b/66b coded signal with a reduced rate.
  • This method is convenient for adding S coding blocks to the 64b/66b coded signal with a reduced rate according to the position rule of the 64b/66b coding blocks when there is a need to restore the rate, thereby obtaining the original 64b/66b coded signal with a restored rate.
  • FIG1 is a schematic diagram of the formats of various types of 64b/66b coding blocks described in an embodiment of the present application
  • FIG2 is a flow chart of a method for processing a 64b/66b coded signal provided by an embodiment of the present application
  • FIG3 is a schematic diagram of a portion of coding blocks included in a 64b/66b coded signal
  • FIG4 is a schematic diagram of the structure of a media access control frame
  • FIG5 is a schematic diagram of a portion of coding blocks included in another 64b/66b coded signal
  • FIG6 is a flow chart of a method for processing a 64b/66b coded signal provided in another embodiment of the present application.
  • FIG7 is a schematic diagram of a portion of coding blocks included in a reduced rate 64b/66b coded signal
  • FIG8 is a schematic diagram of a portion of coding blocks included in another reduced rate 64b/66b coded signal
  • FIG. 9 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application.
  • 64b/66b coding is a physical coding sublayer (PCS) coding established by the IEEE802.3 standard. It is used to convert media access control frames into fixed-rate signals and can identify media access control frames and control information. The content of the media access control frame corresponds to data information. In addition to the content of the media access control frame, 64b/66b coding also needs to transmit some control information, including the frame header and frame trailer of the media access control frame, idle control information for rate filling, Local Fault control information or Remote Fault control information for indicating special signal states, etc.
  • PCS physical coding sublayer
  • 64b/66b coding is implemented by a bit block with a length of 66 bits
  • a bit block with a length of 66 bits based on 64b/66b coding is called a 64b/66b coding block, where b represents a bit
  • a 64b/66b coded signal is a signal composed of 64b/66b coding blocks.
  • 64b/66b encoding actually has different encoding rules. At least in IEEE802.3, the encoding rules of 64b/66b encoding based on 10GE (10GBASE-R) and 40GE/100GE (40GBASE-R/100GBASE-R) are different, but this difference is different in some implementation details.
  • the specific difference is mainly reflected in whether the position of the frame header must be aligned with 8 bytes or 4 bytes.
  • the position of the frame header of 40GE/100GE must be aligned with 8 bytes, that is, the frame header control character must be located in the first byte of the 64b/66b encoding block.
  • the 64b/66b encoding block is divided into 64b/66b data encoding block and 64b/66b control encoding block according to whether it contains control information.
  • 64b/66b coded signals are generally fixed rate signals, and their rate often needs to be reduced.
  • there are two main ways to reduce the rate of 64b/66b coded signals the first is to delete the 64b/66b control coding block containing 8 idle control characters; the second is to delete one of two consecutive 64b/66b coding blocks containing ordered set control information and whose contents are exactly the same.
  • the rate of the 64b/66b coded signal is reduced by deleting a 64b/66b control coding block containing 8 idle control characters.
  • a 64b/66b control coding block containing 8 idle control characters is deleted, the position information of the deleted 64b/66b control coding block will not be recorded. Therefore, the deleted 64b/66b control coding block cannot be restored at the original position later, and can only be added at a position between the frame tail and the frame header according to the rate requirement. In this way, bit transparent transmission of the 64b/66b coded signal cannot be achieved.
  • Another disadvantage is that if the rate of the media access control frame in the 64b/66b encoded signal is very high, that is, the rate of the media access control frame is very close to the rate of the 64b/66b encoded signal, then the 64b/66b encoded block containing the frame tail may be followed by a 64b/66b encoded block containing the frame header. In this way, there is no 64b/66b encoded block containing 8 idle control characters that can be deleted, and the rate of the 64b/66b encoded signal cannot be reduced in this way.
  • the second method can also only be used when the rate of the media access control frame is low.
  • the rate of the media access control frame is often very high, and the probability of having two consecutive 64b/66b control coding blocks with exactly the same code type is very low, which makes the application scope of the second method very limited.
  • the above two methods are only applicable to the case where the rate of the media access control frame is not too high. If the rate of the media access control frame is too high and close to its physical rate upper limit, there will be no deletable 64b/66b coding blocks that meet the above two conditions for a long time, and the 64b/66b coding blocks deleted by the above method cannot be restored to the original position.
  • the purpose of an embodiment of the present application is to provide a method that can reduce the rate by deleting specific 64b/66b coding blocks when the rate of the media access control frame is very high, and the deleted 64b/66b coding blocks can be correctly restored to the original position.
  • 64b/66b coding block refers to encoding 64 bits of "data or control information" into 66 bits of coding block for transmission, where data information represents the content of the media access control frame, and control information represents information used to represent the signal status in addition to the content of the media access control frame.
  • the first 2 bits can be called the synchronization header (2bit Sync Header), which is mainly used for data alignment at the receiving end and identifying the specific definition of the last 64 bits of the 66 bits; the last 64 bits can be called the block payload, which is used to store pure data information, pure control information, or mixed data information and control information.
  • the block payload contains pure control information, or mixed data information and control information
  • the first 8 bits are the type field
  • the last 56 bits are the information field.
  • the control information may include a frame header flag, a frame tail flag, error information, idle information, low-power idle information, ordered set (Ordered Sets) control information, etc.
  • There are two specific ways to implement the control information including 7-bit control characters or 28-bit ordered set control information, wherein the 28-bit ordered set control information includes a 4-bit ordered set type and a 24-bit ordered set content, and the ordered set control information occupies a 64b/66b coding block alone.
  • the 7-bit control characters other than the frame header and the frame tail cannot exist together with the data characters or the ordered set control information in a 64b/66b coding block. It is required that 8 consecutive 7-bit control characters other than the frame header and the frame tail must occupy a 64b/66b coding block together. Note that this application is only applicable to 64b/66b coding blocks defined based on 40GE/100GE, that is, the frame header can only be located at the first character position of the 64b/66b coding block, and the ordered set control information must occupy a 64b/66b coding block alone.
  • FIG. 1 shows various types of 64b/66b coded blocks. According to the values corresponding to the synchronization header and the block payload, the 64b/66b coded blocks can be divided into the following types:
  • (1) D-coded block whose synchronization header is "01" and whose block payload contains pure data information. Specifically, the block payload contains 8 data characters, and the size of each data character is 8 bits;
  • the C coding block whose synchronization header is "10" and the block payload contains pure control information.
  • the C coding block is divided into C-I coding block and C-O coding block;
  • the 7 data characters are fixed as a 7-byte preamble (the content is fixed as "0xaa").
  • the 7 data characters after the frame header flag correspond to other information, that is, it is not a fixed 7-byte preamble.
  • This application has different processing methods according to whether the 7 data characters after the frame header flag in the S coding block are fixed as a 7-byte preamble.
  • this S coding block will not be deleted, because after the S coding block is deleted, the information corresponding to the 7 data characters after the frame header flag cannot be correctly restored.
  • the embodiment of the present application also defines coding blocks other than D coding blocks, C coding blocks, S coding blocks and T coding blocks as E coding blocks (not shown in Figure 1), and the E coding blocks represent coding blocks with error information.
  • the embodiment of the present application believes that when it is necessary to reduce the rate of 64b/66b coding, the existing method of reducing the rate by deleting C-I or C-O coding blocks can continue to be used, but if the existing method does not work, the specific S coding block can be deleted when the preset deletion condition is met, thereby further reducing the rate of the 64b/66b coded signal.
  • This method is convenient for adding an S coding block before a specific D coding block when there is a need to restore the rate, so as to obtain the original 64b/66b coded signal of the restored rate.
  • the rate of the 64b/66b coded signal can be reduced by only using the above method of deleting the S coding block, or if it is slightly modified on the basis of the existing method of deleting C-I or C-O, so that the content and position information of the deleted C-I or C-O coding block is marked by a specific 64b/66b coding block, it can be achieved that after reducing the rate and restoring the rate, the content of the 64b/66b coding block remains unchanged.
  • a method for processing a 64b/66b coded signal provided by the present application is described below through a specific embodiment.
  • FIG. 2 is a flowchart of a method for processing a 64b/66b coded signal provided by an embodiment of the present application.
  • the method for processing a 64b/66b coded signal provided by the present embodiment includes the following steps S101-S103. The following describes each step in sequence:
  • Step S101 Acquire a 64b/66b coded signal, where the 64b/66b coded signal includes multiple 64b/66b coded blocks, where the multiple 64b/66b coded blocks include at least one of the following: an S coded block, a T coded block, a C coded block, a D coded block or an E coded block.
  • the 64b/66b encoded signal described in the embodiment of the present application includes multiple 64b/66b encoded blocks, and the 64b/66b encoded block includes a 2-bit synchronization header and a 64-bit block payload, wherein the block payload can be used to store pure data information, pure control information, or mixed data information and control information.
  • the block payload containing control information it can be further divided into an 8-bit type field and a 56-bit information field.
  • the multiple types of 64b/66b coding blocks include:
  • the synchronization header in the S coding block is 10
  • the type field includes the frame header flag, and the frame header flag is 0x78;
  • the synchronization header in the T coding block is 10
  • the type field includes the frame end flag
  • the frame end flag is one of the following: 0x87, 0x99, 0xaa, 0xb4, 0xcc, 0xd2, 0xe1 or 0xff;
  • the C coding block includes the C-I coding block and the C-O coding block, wherein the synchronization header in the C-I coding block is 10, the type field is 0x1E, and the information field includes 8 idle control characters, and the content of the idle control characters is 7 bits of 0; the synchronization header in the C-O coding block is 10, the type field is 0x4B, the first 28 bits of the information field contain the content and type of the ordered set control information, and the last 28 bits are fixed to "0x000_0000";
  • the synchronization header in the D coding block is 01;
  • E coding block refers to coding blocks other than S coding block, T coding block, C coding block and D coding block.
  • the 64b/66b coded signal of the embodiment of the present application includes any combination of S coding blocks, T coding blocks, C coding blocks, D coding blocks or E coding blocks.
  • the embodiment of the present application does not impose excessive restrictions on the type of 64b/66b coding blocks specifically included in the 64b/66b coded signal and the number of 64b/66b coding blocks of each type.
  • Step S102 traverse each 64b/66b coded block in the 64b/66b coded signal, and if the currently traversed 64b/66b coded block is an S coded block and the deletion condition is met, delete the S coded block to obtain a 64b/66b coded signal with a reduced rate.
  • an S coding block may only include zero or more C coding blocks in front of it, and if the rate of the media access control frame is very high, there are only a limited number of C coding blocks before the S coding block, and these limited number of C coding blocks are preceded by a T coding block.
  • These C codes can only be C-I or C-O. If C-I exists, the rate can be reduced by deleting the C-I coding block. If there are only C-O coding blocks and there are no two consecutive identical C-O coding blocks, all C-O coding blocks cannot be deleted.
  • the conditions for deleting the S coding are initially met. If other conditions are also met, the S coding block can be deleted, thereby reducing the rate of the 64b/66b coded signal.
  • a first preset value can be set, and it is stipulated that if there are N C-O coding blocks between the S coding block and the closest T coding block in front, and any C-O coding block cannot be deleted, and N is an integer greater than or equal to 0 and less than the first preset value, then the condition for deleting the S coding is preliminarily met.
  • the S coding block preliminarily meets the deletion condition.
  • N will not be too large. If N is very large or there are other types of 64b/66b coding blocks other than C-O between T and S, it means that the situation is special and the S coding block cannot be deleted at this time. It is worth noting that if S is preceded by T, there are 0 C-O coding blocks at this time, which must meet the condition that there are less than the first preset value of C-O coding blocks between T and S.
  • each 64b/66b coded block that is being prepared for transmission in the 64b/66b coded signal can be traversed in sequence according to the transmission order, and the following processing is performed for the currently traversed 64b/66b coded block:
  • 64b/66b code blocks If the type of the currently traversed 64b/66b code block is an S code block, search sequentially before the current S code block, either find T, or stop searching after searching forward for the first preset value. If T can be found, continue the subsequent processing, otherwise it is considered that the deletion condition is not met; then search backward for the second preset value of 64b/66b code blocks;
  • deletion allowing conditions described in the embodiments of the present application specifically include a first deletion allowing condition, a second deletion allowing condition, a third deletion allowing condition and a fourth deletion allowing condition.
  • first deletion allowing condition, the second deletion allowing condition, the third deletion allowing condition and the fourth deletion allowing condition are all met, the deletion allowing condition is met.
  • the first deletion condition includes: there are N CO coding blocks before the currently traversed S coding block, there is 1 T coding block before the N CO coding blocks, and there are M consecutive D coding blocks after the currently traversed S coding block, where N is an integer greater than or equal to 0 and less than a first preset value, and M is an integer equal to a second preset value.
  • Figure 3 shows a portion of the coding blocks contained in a 64b/66b coded signal.
  • a certain section of the 64b/66b coded signal sequentially contains 1 T coding block, N C-O coding blocks, 1 S coding block, and M consecutive D coding blocks. Then the S coding block in Figure 3 can be deleted to achieve the purpose of reducing the rate of the 64b/66b coded signal.
  • the rate can be reduced by deleting the C-I coding block without deleting the S coding block.
  • the first deletion condition allowed in the embodiment of the present application stipulates that the N C coding blocks before the S coding block must all be C-O coding blocks, that is, the S coding block is deleted only when all the blocks between the T coding block and the S coding block are C-O coding blocks.
  • the T coding block is followed by N C-O coding blocks. If there are at least two consecutive C-O coding blocks among the N C-O coding blocks that are repeated (i.e., the information domains are consistent), then the rate can be reduced by deleting the C-O coding blocks.
  • the first deletion permission condition of the embodiment of the present application may also include: the information domains of any two adjacent C-O coding blocks among the N C-O coding blocks are not completely consistent.
  • the first deletion permission condition of the embodiment of the present application may also include: under certain circumstances, the media access control frame to which the T coding block before the N C-O coding blocks belongs can normally pass the frame detection sequence (Frame Check Sequence)-32 detection, and the frame detection sequence-32 is located in the 4 bytes before the end of the media access control frame.
  • the media access control frame to which the T coding block before the N C-O coding blocks belongs can normally pass the frame detection sequence (Frame Check Sequence)-32 detection, and the frame detection sequence-32 is located in the 4 bytes before the end of the media access control frame.
  • the main function of the 64b/66b coding block is to transmit the media access control frame.
  • One media access control frame corresponds to multiple 64b/66b coding blocks, starting with the S coding block and ending with the T coding block.
  • the media access control frame is actually a byte structure, consisting of multiple bytes.
  • the media access control frame actually corresponds to all D coding blocks between S and T, and all data bytes in the T coding block.
  • the structure of the media access control frame is shown in Figure 4.
  • All bytes of the media access control frame can actually be divided into two parts, namely the media access control frame content and a 4-byte frame detection sequence, where the media access control frame content is K bytes, K is an integer greater than or equal to 60 and less than 3000, and the frame detection sequence is used to detect the K bytes of media.
  • the error detection algorithm is a 4-byte cyclic redundancy check-32 (CRC-32, -32 means 32 bits), that is, when sending a media access control frame, a 4-byte check information is generated according to the CRC-32 algorithm for the K-byte media access control frame content, and written into the 4-byte frame detection sequence of the media access control frame.
  • a 4-byte check information is first generated according to the CRC-32 algorithm for the K-byte media access control frame content, and then compared with the 4-byte frame detection sequence. If they are exactly the same, it means there is no error, otherwise it means there is an error.
  • the above method can also be called frame detection sequence-32 detection. If the frame detection sequence-32 detection can be passed, it means that the media access control frame has no error. If the frame detection sequence-32 detection cannot be passed, it means that the media access control frame has an error. Adding the above conditions in the first allowed deletion condition can ensure that the S coding block will not be deleted when there is an error, so as to prevent the S coding block from being added incorrectly due to the error in the recovery rate processing stage. However, due to the complexity of implementation, it is an optional option and is only used in scenarios with severe bit errors.
  • the S coding block currently traversed is followed by M D coding blocks, which means that the S coding block currently traversed is the beginning of a media access control frame, and the T coding block before the S coding block currently traversed is the end of another media access control frame.
  • M D coding blocks M D coding blocks
  • T coding block before the S coding block currently traversed the end of another media access control frame.
  • the second deletion permission condition includes: the last 56 bits of the information field of the S coding block are a 7-byte preamble code, and the preamble code is "0xaa".
  • the value of the block type field in the 64b/66b control coding block whose first control character is the frame header flag is 0x78 (0x represents hexadecimal, for example, 0x10 represents hexadecimal 10, that is, decimal 16), and the first character of the 8 characters corresponding to 64 bits is the frame header control character (that is, The frame header flag, also called the S control character, S stands for start), the following 7 bytes of data characters, the content is 0xaa, corresponding to the 7-byte preamble, that is, the first character is the frame header control character of the 64b/66b encoding block content is a fixed value.
  • the 64b/66b encoding block that is followed by 7 preambles 0xaa at the beginning of the packet header control character that conforms to the IEEE802.3 standard can be named S-DEL encoding block
  • the 64b/66b encoding block that is not followed by 7 preambles 0xaa at the beginning of the frame header control character that does not conform to the IEEE802.3 standard is named S-NO-DEL encoding block.
  • the deleted S encoding blocks should all be S-DEL encoding blocks.
  • the third deletion permission condition includes: receiving a request to reduce the signal rate.
  • the sender of the 64b/66b encoded signal generally executes the method provided in the embodiment of the present application only when it receives a request to reduce the signal rate, reduces the rate of the 64b/66b encoded signal, obtains a 64b/66b encoded signal with a reduced rate, and then sends the 64b/66b encoded signal with a reduced rate to the other device.
  • the fourth deletion permission condition includes: the number of 64b/66b coding blocks between the currently traversed S coding block and the last deleted S coding block is greater than a third preset value.
  • an additional deletion condition is required, that is, the number of 64b/66b coded blocks between two consecutive deletion operations of the S coded blocks is recorded as R, and R must be greater than the third preset value, wherein the third preset value and R are both integers, and the third preset value can be modified as needed.
  • This condition is added to take into account that when the rate is restored, the presence of bit errors is more likely to cause the D coded blocks that originally did not meet the addition conditions to meet the addition conditions, which will result in the addition of more S coded blocks.
  • this deletion condition is added, so that even if there is an erroneous addition of the S coded blocks, at most one error can occur in the R 64b/66b coded blocks, thereby ultimately limiting the number of errors. It is understandable that since there are at least 8 64b/66b coded blocks between the S coded blocks, if the third preset value is very small, this condition is equivalent to non-existence at this time.
  • FIG5 shows a partial coding block included in a 64b/66b coded signal.
  • the transmitter of the 64b/66b coded signal receives a request to reduce the signal rate, and needs to reduce the rate of the 64b/66b coded signal shown in FIG5, so it starts to traverse the 64b/66b coded blocks in the 64b/66b coded signal.
  • the 64b/66b coded signal portion shown in FIG5 includes 2 S coding blocks, and it is assumed that the first S coding block meets the deletion condition, and the first S coding block is deleted; then continue to traverse the blocks after the first S coding block 64b/66b coding blocks, when traversing to the second S coding block, it is assumed here that deleting the first S coding block is the most recent S coding block deletion operation before deleting the second S coding block.
  • R is greater than the third preset value, so the second S coding block also meets the deletion permission condition, and the second S coding block can be deleted.
  • the traversed 64b/66b coding blocks can be counted by a counter. Whenever a certain S coding block is deleted, the counter is cleared to count again. When the next S coding block is traversed, it is determined according to the count of the counter whether the number of 64b/66b coding blocks between the current S coding block and the last deleted S coding block is greater than the third preset number. If the value is greater than the third preset value, the current S coding block is deleted and the counter is cleared to perform the next round of counting.
  • the embodiment of the present application sets the above four deletion conditions and performs the deletion operation on the S coding block when all four deletion conditions are met, thereby ensuring the correctness of the S coding block added when the rate of the 64b/66b coded signal is subsequently restored.
  • Step S103 Send a 64b/66b encoded signal with a reduced rate.
  • the embodiment of the present application deletes the S coding block when the deletion condition is met, thereby reducing the speed of the 64b/66b coded signal, and then sending the reduced-rate 64b/66b coded signal to the peer device.
  • the solution for reducing the 64b/66b coding signal rate provided by the embodiment of the present application is applicable to the situation when the rate of the media access control frame is very high. Even when the rate of the media access control frame is very high, the coding signal rate can still be reduced by deleting specific 64b/66b coding blocks, and the deleted 64b/66b coding blocks can be correctly restored to the original position.
  • the existing method cannot be used for the situation when the rate of the media access rate frame is very high.
  • the embodiment of the present application is combined with the existing method to reduce the rate of the 64b/66b coding signal when the media access control frame is at any rate.
  • the 64b/66b coded signal with a reduced rate is sent.
  • the sending of the 64b/66b coded signal with a reduced rate can be specifically implemented in the following ways:
  • the first method is to send a 64b/66b encoded signal with a reduced rate through a physical medium, wherein the physical medium may be a physical transmission medium such as a metal wire or an optical fiber, and the specific type of the physical medium is not limited too much here.
  • the physical medium may be a physical transmission medium such as a metal wire or an optical fiber, and the specific type of the physical medium is not limited too much here.
  • the second method is to encapsulate the reduced rate 64b/66b encoded signal into a service signal and send the service signal, wherein the service signal may be an optical data unit signal, and the specific type of the service signal is not limited too much herein.
  • the third method is to convert the 64b/66b coded signal with a reduced rate into a coded signal of another format and send the coded signal of another format.
  • the coded signal of another format here can be any coded format other than the 64b/66b coded format, such as a 256b/257b coded signal, and the specific format of the coded signal of another format is not limited too much.
  • the method of the embodiment of the present application further includes: receiving a 64b/66b encoded signal with a reduced rate, wherein the 64b/66b encoded signal with a reduced rate can be received in the following ways:
  • the first method is to receive the reduced rate 64b/66b encoded signal through a physical medium, wherein the physical medium may be a physical transmission medium such as a metal wire or an optical fiber, and the specific type of the physical medium is not limited here;
  • the second method is to receive a service signal and extract a 64b/66b coded signal with a reduced rate from the service signal, wherein the service signal may be an optical data unit signal, and the specific type of the service signal is not limited here;
  • the third method is to receive coded signals in other formats and convert the coded signals in other formats into 64b/66b coded signals with reduced rate.
  • the coded signals in other formats here can be any coded formats except 64b/66b coded formats, such as 256b/257b coded signals.
  • the specific formats of the coded signals in other formats are not excessively limited here.
  • the device receives a 64b/66b coded signal with a reduced rate obtained by processing in the above step S102, it can also add an S coding block to the 64b/66b coded signal with a reduced rate based on the position rule of the 64b/66b coding block to restore the 64b/66b coded signal to the original rate.
  • FIG. 6 shows a flow chart of a method for processing a 64b/66b coded signal provided by another embodiment of the present application.
  • the method for processing a 64b/66b coded signal provided by this embodiment includes the following steps S201-S202. The following describes each step in sequence:
  • Step S201 Receive a reduced rate 64b/66b encoded signal.
  • the reduced rate 64b/66b coded signal here is obtained by deleting the S coded blocks that meet the deletion allowed conditions in the original 64b/66b coded signal as described above.
  • Step S202 traverse each 64b/66b coded block in the reduced rate 64b/66b coded signal, and when the currently traversed 64b/66b coded block is a D coded block and the condition allowing addition is met, add an S coded block before the currently traversed 64b/66b coded block to obtain a 64b/66b coded signal at a restored rate.
  • the reduced rate 64b/66b coded signal needs to be restored to obtain the original 64b/66b coded signal.
  • the first D coding block is preceded by N C-O coding blocks
  • the N C-O coding blocks are preceded by 1 T coding block, where N is an integer greater than or equal to 0 and less than a first preset value, then it is preliminarily met to add an S coding block in front of the first D coding block, so as to obtain a 64b/66b coded signal with a restored rate.
  • the S coding block added to the 64b/66b coded signal in the embodiment of the present application is an S coding block that meets specific rules.
  • the synchronization header in the S coding block is "10”
  • the type field of the block payload includes the frame header flag "0x78”
  • the last 56 bits of the information field of the block payload are a 7-byte preamble code (generally 7 0xaa).
  • the conditions for allowing addition described in the embodiment of the present application include a first condition for allowing addition and a second condition for allowing addition, and the condition for allowing addition is met when both the first condition for allowing addition and the second condition for allowing addition are met.
  • the first condition for allowing addition includes: there are N C-O coding blocks before the currently traversed D coding block, there is 1 T coding block before the N C-O coding blocks, there are J consecutive D coding blocks after the currently traversed D coding block, N is an integer greater than or equal to 0 and less than the first preset value, J is an integer equal to a fourth preset value, and the fourth preset value is equal to the second preset value M minus 1.
  • the conditions for allowing the deletion of S coding blocks may include: there are N C-O coding blocks before the S coding block, there is 1 T coding block before the N C-O coding blocks, and there are M (M equals J plus 1) consecutive D coding blocks after the S coding block, where N is an integer greater than or equal to 0 and less than a first preset value, and M is an integer equal to a second preset value; the S coding block can be deleted if the above conditions are met.
  • an S coding block when it is necessary to add an S coding block, it can be detected whether there is a T coding block, N C-O coding blocks, and M D coding blocks arranged in sequence in the 64b/66b coded signal. If this situation exists, it can be considered to insert and add an S coding block before the first D coding block among the M D coding blocks, and the inserted S coding block is located between the C-O coding block and the D coding block.
  • FIG. 7 shows a portion of coding blocks included in a reduced-rate 64b/66b coded signal.
  • the receiving end receives a reduced-rate 64b/66b coded signal as shown in FIG. 7, and needs to process it to recover the rate, so it starts to traverse the 64b/66b coding blocks in the reduced-rate 64b/66b coded signal in sequence from front to back.
  • FIG. 7 shows a portion of the reduced-rate 64b/66b coded signal, in which 1 T coding block, N C-O coding blocks, and M consecutive D coding blocks appear in sequence. Then, a standard S-DEL coding block can be inserted before the first D coding block to achieve the purpose of recovering the rate of the 64b/66b coded signal.
  • the first deletion-permitting condition may further include: the information domains of any two adjacent C-O coding blocks among the N C-O coding blocks are not completely consistent.
  • the first addition-permitting condition of the embodiment of the present application may further include: the information domains of any two adjacent C-O coding blocks among the N C-O coding blocks are not completely consistent.
  • the above-mentioned first condition for allowing addition may also include: under specific circumstances, the media access control frame to which the T coding block before the N CO coding blocks belongs can normally pass the frame detection sequence (Frame Check Sequence)-32 detection, and the frame detection sequence-32 is located in the 4 bytes before the end of the media access control frame.
  • the frame detection sequence Fra Check Sequence
  • the T coding block is the end of the media access control frame, and there are 4 bytes of frame detection information in front of it.
  • the cyclic redundancy check-32 algorithm can be used to determine whether the media access control frame has bit errors. If there are no bit errors, it means that the media access control frame can pass the frame detection sequence normally. If there are bit errors, it means that the media access control frame cannot pass the frame detection sequence normally. Adding the above conditions to the first allowed addition condition can avoid the incorrect addition of S coding blocks due to bit errors. However, due to the complexity of the implementation, it is an optional option and is only used in scenarios with more serious bit errors.
  • the second condition for allowing addition includes: the number of 64b/66b coding blocks between the currently traversed D coding block and the last added S coding block is greater than a third preset value.
  • the conditions for allowing deletion of the S coding block include: the number of 64b/66b coding blocks between the currently traversed S coding block and the last deleted S coding block is greater than a third preset value.
  • the conditions for allowing addition may also include that the number of 64b/66b coding blocks between the currently traversed D coding block and the last added S coding block is greater than a third preset value. This condition is also set to take fault tolerance into consideration.
  • a D coding block in the middle of a media access control frame becomes a T coding block due to a bit error, all addition conditions are met, resulting in an S coding block being added by mistake. If this phenomenon cannot be avoided, it must be reduced. This restriction is added to the deletion and addition conditions to prevent deletion and addition actions from being too frequent, and to prevent sudden bit errors from causing multiple consecutive erroneous addition actions.
  • the third preset value is small enough, for example 4, since the frame length of the media access control frame is greater than the third preset value of 64b/66b coding blocks, this condition is equivalent to not existing; a suitable third preset value can be selected according to the maximum frame length of the media access control frame, for example, the maximum frame length is selected as the third preset value. In this way, although the effect of reducing the 64b/66b coding signal rate will be weakened, excessive S coding blocks will not be added when burst errors occur.
  • Figure 8 shows a partial coding block included in a 64b/66b coded signal.
  • the S coding block in Figure 8 is the S coding block added last time;
  • the first D coding block shown in Figure 8 is the currently traversed 64b/66b coding block, which is preceded by N C-O coding blocks and T coding blocks, and the first condition for allowing addition is met.
  • the number of 64b/66b coding blocks between the currently traversed D coding block and the last added S coding block is R. At this time, it is necessary to determine whether the value of R is greater than the third preset value. If so, it is determined that the currently traversed D coding block meets the second condition for allowing addition, so 1 S coding block can be added before it.
  • the traversed 64b/66b coding blocks can be counted through a counter. Whenever an S coding block is added, the counter is cleared to count again. When traversing to the next D coding block, it is determined based on the count of the counter whether the number of 64b/66b coding blocks between the current D coding block and the last added S coding block is greater than a third preset value. If it is greater than the third preset value, an S coding block is added before the currently traversed D coding block, and the counter is cleared for the next round of counting.
  • the embodiment of the present application provides a communication device, including a sending module and a receiving module; wherein:
  • the sending module is used to: obtain a 64b/66b coded signal, the 64b/66b coded signal includes a plurality of 64b/66b coded blocks, the plurality of 64b/66b coded blocks include at least one of the following: an S coded block, a T coded block, a C coded block, a D coded block or an E coded block; traverse each 64b/66b coded block in the 64b/66b coded signal, and when the currently traversed 64b/66b coded block is an S coded block and a deletion condition is satisfied, delete the S coded block to obtain a 64b/66b coded signal with a reduced rate; and send the 64b/66b coded signal with a reduced rate;
  • the receiving module is used for: receiving a 64b/66b coded signal with a reduced rate; traversing each 64b/66b coded block in the 64b/66b coded signal with a reduced rate; and adding an S coded block before the 64b/66b coded block currently traversed when the 64b/66b coded block currently traversed is a D coded block and a condition allowing addition is satisfied, so as to obtain a 64b/66b coded signal with a restored rate.
  • the specific implementation of the communication device is basically the same as the specific implementation of the above-mentioned 64b/66b encoded signal processing method, and will not be repeated here.
  • the present application also provides a communication device, as shown in FIG9 , the communication device 900 includes but is not limited to:
  • At least one processor 910 At least one processor 910;
  • At least one memory 920 used to store at least one program
  • the at least one program is executed by the at least one processor 910 , the method for processing the 64b/66b encoded signal as described in any of the above embodiments is performed.
  • processor 910 and the memory 920 may be connected via a bus or other means.
  • the processor 910 can adopt a central processing unit (CPU).
  • the processor can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FPGA field programmable gate arrays
  • a general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.
  • the processor 910 adopts one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.
  • the memory 920 can be used to store non-transitory software programs and non-transitory computer executable programs, such as the 64b/66b coded signal processing method executed by the communication device side described in any embodiment of the present application.
  • the processor 910 implements the above-mentioned 64b/66b coded signal processing method by running the non-transitory software program and instructions stored in the memory 920.
  • the memory 920 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store a processing method for executing the above-mentioned 64b/66b encoded signal.
  • the memory 920 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device.
  • the memory 920 may optionally include a memory remotely arranged relative to the processor 910, and these remote memories may be connected to the processor 910 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • the non-transitory software programs and instructions required to implement the above-mentioned 64b/66b encoded signal processing method are stored in the memory 920.
  • the 64b/66b encoded signal processing method provided by any embodiment of the present application is executed.
  • An embodiment of the present application also provides a computer-readable storage medium, which stores a program executable by a processor.
  • the program executable by the processor is executed by the processor, it is used to implement the processing method of the 64b/66b encoded signal described in any of the above embodiments.
  • Computer-readable media can be computer-readable signal media or computer-readable storage media.
  • Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive lists) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.
  • computer-readable storage media can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.
  • Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.
  • the program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
  • Computer program code for performing the operations of the present application may be written in one or more programming languages or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages.
  • the program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server.
  • the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).
  • LAN local area network
  • WAN wide area network
  • Internet service provider e.g., via the Internet using an Internet service provider
  • An embodiment of the present application provides a computer program product, which stores program instructions.
  • the program instructions When the program instructions are executed on a computer, the computer implements the method for processing a 64b/66b encoded signal as described in any of the above embodiments.

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Abstract

本申请公开了一种64b/66b编码信号的处理方法、通信设备和存储介质，方法包括获取64b/66b编码信号，所述64b/66b编码信号包括多个64b/66b编码块，所述多个64b/66b编码块包括以下至少之一：S编码块、T编码块、C编码块、D编码块或者E编码块；遍历所述64b/66b编码信号中的每个所述64b/66b编码块，在当前遍历的64b/66b编码块为S编码块且允许删除条件成立的情况下，将所述S编码块删除，得到降低速率的64b/66b编码信号；发送降低速率的64b/66b编码信号。

Description

64b/66b编码信号的处理方法、通信设备和存储介质
相关申请的交叉引用
本申请基于申请号为202211383267.4、申请日为2022年11月07日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及通信技术领域，尤其涉及一种64b/66b编码信号的处理方法、通信设备和存储介质。
背景技术
64b/66b编码信号一般为固定速率的信号，在发送64b/66b编码信号以前经常需要先降低其速率。例如，在将灵活以太网客户信号(FlexE Client信号)装入灵活以太网群信号(FlexE Group信号)前，需要先降低灵活以太网客户信号的速率，然后才能将降低速率后的灵活以太网客户信号装入灵活以太网群信号的时隙中；另外在将64b/66b编码信号装入光传送网的光数据单元信号(ODU信号)前，可以先降低64b/66b编码信号的速率，然后再装入光数据单元信号中，这样光数据单元的信号速率可以更低。
相关技术中，降低64b/66b编码信号的方式主要有两种：第一种，删除包含8个空闲(idle)控制字符的64b/66b控制编码块；第二种，删除连续2个包含有序集(Ordered sets)控制信息且其内容完全一样的64b/66b编码块中的1个。这两种方式都只适用于媒体访问控制帧(Media Access Control Frame)的速率不太高的情况，如果媒体访问控制帧的速率太高且接近于其物理速率上限，此时会在较长时间内不出现符合以上两个条件的可删除的64b/66b编码块，而且通过以上方式删除的64b/66b编码块无法在原来的位置恢复。所以亟需一种能在媒体访问控制帧的速率很高时仍旧能通过删除特定64b/66b编码块降低速率的方法，且被删除的64b/66b编码块能在原来的位置正确恢复。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请实施例提供一种64b/66b编码信号的处理方法、通信设备、计算机可读存储介质和计算机程序产品，在媒体访问控制帧的速率很高时仍旧能通过删除特定64b/66b编码块降低速率，同时便于恢复原始的64b/66b编码信号。
第一方面，本申请实施例提供一种64b/66b编码信号的处理方法，所述方法包括：
获取64b/66b编码信号，所述64b/66b编码信号包括多个64b/66b编码块，所述多个64b/66b编码块包括以下至少之一：S编码块、T编码块、C编码块、D编码块或者E编码块；
遍历所述64b/66b编码信号中的每个所述64b/66b编码块，在当前遍历的64b/66b编码块为S编码块且允许删除条件成立的情况下，将所述S编码块删除，得到降低速率的64b/66b编码信号；
发送降低速率的64b/66b编码信号。
第二方面，本申请实施例提供一种通信设备，包括发送模块和接收模块；其中，
所述发送模块用于：获取64b/66b编码信号，所述64b/66b编码信号包括多个64b/66b编码块，所述多个64b/66b编码块包括以下至少之一：S编码块、T编码块、C编码块、D编码块或者E编码块；遍历所述64b/66b编码信号中的每个所述64b/66b编码块，在当前遍历的64b/66b编码块为S编码块且允许删除条件成立的情况下，将所述S编码块删除，得到降低速率的64b/66b编码信号；发送降低速率的64b/66b编码信号；
所述接收模块用于：接收所述降低速率的64b/66b编码信号；遍历所述降低速率的64b/66b编码信号中的每个64b/66b编码块；在当前遍历的64b/66b编码块为所述D编码块且允许添加条件成立的情况下，在当前遍历的64b/66b编码块之前添加所述S编码块，以获得恢复速率的64b/66b编码信号。
第三方面，本申请实施例提供一种通信设备，包括：
至少一个处理器；
至少一个存储器，用于存储至少一个程序；
当至少一个所述程序被至少一个所述处理器执行时实现如第一方面所述的64b/66b编码信号的处理方法。
第四方面，本申请实施例提供一种计算机可读存储介质，其中存储有处理器可执行的程序，所述处理器可执行的程序被处理器执行时用于实现如第一方面所述的64b/66b编码信号的处理方法。
第五方面，本申请实施例提供一种计算机程序产品，包括计算机程序或计算机指令，所述计算机程序或所述计算机指令存储在计算机可读存储介质中，计算机设备的处理器从所述计算机可读存储介质读取所述计算机程序或所述计算机指令，所述处理器执行所述计算机程序或所述计算机指令，使得所述计算机设备执行如第一方面所述的64b/66b编码信号的处理方法。
本申请实施例，通过将64b/66b编码信号中满足预设的允许删除条件的S编码块删除，进而获得降低速率的64b/66b编码信号。这种方式便于在有恢复速率需求时，根据64b/66b编码块的位置规则在降低速率的64b/66b编码信号之中添加S编码块，从而获得恢复速率的原始64b/66b编码信号。
附图说明
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1是本申请实施例描述的多种类型的64b/66b编码块的格式示意图；
图2是是本申请的一个实施例提供的64b/66b编码信号的处理方法的流程示意图；
图3是一个64b/66b编码信号包含的部分编码块的示意图；
图4是一个媒体访问控制帧的结构示意图；
图5是另一个64b/66b编码信号包含的部分编码块的示意图；
图6是本申请另一实施例提供的64b/66b编码信号的处理方法的流程示意图；
图7是一个降低速率的64b/66b编码信号包含的部分编码块的示意图；
图8是另一个降低速率的64b/66b编码信号包含的部分编码块的示意图；
图9是本申请实施例提供的一种通信设备的结构示意图。
具体实施方式
下面结合说明书附图和具体的实施例对本申请进行进一步的说明。所描述的实施例不应视为对本申请的限制，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本申请实施例的目的，不是旨在限制本申请。
64b/66b编码是由IEEE802.3标准制定的物理编码子层(physical coding sublayer，PCS)编码，用于将媒体访问控制帧转换为固定速率的信号，同时能识别出媒体访问控制帧和控制信息，其中媒体访问控制帧的内容对应数据信息，除了媒体访问控制帧的内容以外，64b/66b编码还需要传递一些控制信息，其中控制信息包括媒体访问控制帧的帧头和帧尾，用于实现速率填充的idle控制信息，用于表示信号特殊状态的Local Fault控制信息或者Remote Fault控制信息等。由于64b/66b编码是通过长度为66比特的比特块实现的，所以基于64b/66b编码的66比特长度的比特块被称为64b/66b编码块，这里b表示比特，而64b/66b编码信号是由64b/66b编码块组成的信号。64b/66b编码实际有不同的编码规则，至少在IEEE802.3中，基于10GE(10GBASE-R)的64b/66b编码和基于40GE/100GE(40GBASE-R/100GBASE-R)的编码规则是不一样的，但这种不一样是某些实现细节上的不一样，具体区别主要体现在帧头的位置是否必须和8字节对齐还是和4字节对齐。40GE/100GE为了实现简单要求，帧头位置必须和8字节对齐，即帧头控制字符必须位于64b/66b编码块中的第1个字节。64b/66b编码块按照是否包含控制信息分为64b/66b数据编码块和64b/66b控制编码块。
64b/66b编码信号一般为固定速率的信号，且经常需要降低其速率。相关技术中，降低64b/66b编码信号速率的方式主要有两种：第一种，删除包含8个空闲(idle)控制字符的64b/66b控制编码块；第二种，删除连续2个包含有序集(Ordered sets)控制信息且其内容完全一样的64b/66b编码块中的1个。
对于第一种方式，通过删除包含8个空闲(idle)控制字符的64b/66b控制编码块的方式来降低64b/66b编码信号的速率，然而该方式一旦删除某个包含8个空闲(idle)控制字符的64b/66b控制编码块后，由于不会记录所删除的64b/66b控制编码块的位置信息，所以后续无法在原来的位置恢复出被删除的64b/66b控制编码块，只能根据速率需求在帧尾和帧头之间找个位置加上，这样无法做到64b/66b编码信号的比特透传。另外一个缺点是如果64b/66b编码信号中媒体访问控制帧的速率很高，即媒体访问控制帧的速率非常接近64b/66b编码信号的速率，此时包含帧尾的64b/66b编码块后面可能紧跟着包含帧头的64b/66b编码块，这样不存在可以删除的包含8个空闲控制字符的64b/66b编码块，也就无法通过此方式降低64b/66b编码信号的速率。
对于第二种方式，同样只有在媒体访问控制帧的速率较低时才可能使用，但实际应用中往往媒体访问控制帧的速率都很高，存在连续2个码型完全一样的64b/66b控制编码块的概率很低，使得第二种方式的应用范围十分受限。
可见上述两种方式都只适用于媒体访问控制帧的速率不太高的情况，如果媒体访问控制帧的速率太高且接近于其物理速率上限，此时会在较长时间内不出现符合以上两个条件的可删除的64b/66b编码块，而且通过以上方式删除的64b/66b编码块无法在原来的位置恢复。
有鉴于此，本申请实施例的目的在于提供一种能在媒体访问控制帧的速率很高时仍旧能通过删除特定64b/66b编码块降低速率的方法，且被删除的64b/66b编码块能在原来的位置正确恢复。
下面对本申请实施例涉及的概念进行介绍。
64b/66b编码块指将64比特“数据或控制信息”编码成66比特的编码块来进行传输，其中数据信息表示媒体访问控制帧的内容，控制信息表示除了媒体访问控制帧内容以外用于表示信号状态的信息。在66比特的编码块中，前2个比特可称作同步头(2bit Sync Header)，主要用于接收端的数据对齐和识别66比特中后64比特的具体定义；后64比特可称作块负荷，用于存放纯数据信息、纯控制信息、或者混合的数据信息和控制信息。更具体地，对于块负荷包含纯控制信息、或者混合的数据信息和控制信息的情况，64比特的块负荷中，前8比特为类型域，后56比特为信息域。其中，控制信息可以包括帧头标志、帧尾标志、错误信息、空闲信息、低功耗空闲信息、有序集(Ordered Sets)控制信息等，控制信息的具体实现有两种方式，包括7比特的控制字符或28比特的有序集控制信息，其中28比特的有序集控制信息包括4比特的有序集类型和24比特的有序集内容，有序集控制信息单独占用一个64b/66b编码块，除了帧头和帧尾以外的7比特的控制字符不能和数据字符或者有序集控制信息一起存在于一个64b/66b编码块块中，要求必须连续8个除了帧头和帧尾以外的7比特的控制字符在起占用一个64b/66b编码块。注意，本申请仅适用于基于40GE/100GE定义的64b/66b编码块，即帧头只能位于64b/66b编码块第一个字符的位置，且有序集控制信息必须单独占用一个64b/66b编码块。
请参见图1，图1示出了多种类型的64b/66b编码块，根据同步头、块负荷对应包含的值，64b/66b编码块可以划分为以下几种类型：
(1)D编码块，其同步头为“01”，块负荷包含纯数据信息，具体的，块负荷包含8个数据字符，每个数据字符的大小为8比特；
(2)C编码块，其同步头为“10”，块负荷包含纯控制信息，根据块负荷不同的类型域值和信息域值，C编码块又分为C-I编码块和C-O编码块；
(2.1)C-I编码块，其同步头为“10”，块负荷的类型域为“0x1E”，信息域包含8个空闲控制字符，每个空闲控制字符为7比特的0；
(2.2)C-O编码块，其同步头为“10”，块负荷的类型域为“0x4B”，信息域的前28比特包含有序集控制信息的内容和类型，后28比特固定为“0x000_0000”；
(3)S编码块，其同步头为“10”，块负荷包含混合的数据信息和控制信息，其中类型域包含帧头标志(表示帧开始传送)，帧头标志的值为“0x78”，信息域包含7个数据字符，每个数据字符的大小为8比特；
需了解的是，本申请实施例描述的S编码块中，根据IEEE802.3标准，帧头标志后面7 个数据字符固定为7字节的前导码(内容是固定的“0xaa”)。但是在一些情况下，帧头标志后面7个数据字符对应其他信息，即不是固定的7字节的前导码，本申请根据S编码块中帧头标志后面7个数据字符是否固定为7字节的前导码有不同的处理方式。如果S编码块中帧头标志后面7个数据字符不是固定为7字节的前导码，则此S编码块不会被删除，因为这种S编码块删除后无法正确恢复出帧头标志后面的7个数据字符对应的信息。
(4)T编码块，其同步头为“10”，块负荷包含混合的数据信息和控制信息，其中类型域包含帧尾标志(表示帧结束传送)，帧尾标志的值可以为“0x87”、“0x99”、“0xaa”、“0xb4、“0xcc”、“0xd2”、“0xe1”或者“0xff”。
另外，本申请实施例还将除D编码块、C编码块、S编码块和T编码块以外的编码块定义为E编码块(图1未示出)，E编码块表示存在错误信息的编码块。
本申请实施例认为，当需要降低64b/66b编码的速率时，现有的通过删除C-I或C-O编码块降低速率的方式可以继续使用，但如果现有方式无法工作时，可在预设的允许删除条件成立的情况下将特定的S编码块删除，从而进一步降低64b/66b编码信号的速率。这种方式便于在有恢复速率需求时，可在预设的允许添加条件成立的情况下在特定的D编码块前添加一个S编码块，从而获得恢复速率的原始64b/66b编码信号。进一步的，如果能只使用以上的删除S编码块的方式降低64b/66b编码信号的速率，或者在现有的的删除C-I或C-O的方式基础上稍加改造，使得通过特定的64b/66b编码块标记被删除的C-I或C-O编码块的内容和位置信息，就可以实现降低速率再恢复速率后，64b/66b编码块的内容保持不变。
下面通过具体的实施例对本申请提供的一种64b/66b编码信号的处理方法进行说明。
请参见图2，图2是本申请的一个实施例提供的64b/66b编码信号的处理方法的流程示意图，本实施例提供的64b/66b编码信号的处理方法包括以下步骤S101—S103，下面依次介绍各个步骤：
步骤S101：获取64b/66b编码信号，64b/66b编码信号包括多个64b/66b编码块，多个64b/66b编码块包括以下至少之一：S编码块、T编码块、C编码块、D编码块或者E编码块。
可以理解的是，本申请实施例描述的64b/66b编码信号包括多个64b/66b编码块，64b/66b编码块包括2比特同步头和64比特块负荷，其中块负荷可用于存放纯数据信息、纯控制信息、或者混合的数据信息和控制信息，对于含有控制信息的块负荷，又进一步可以划分为8比特类型域和56比特信息域。
可以理解的是，本申请实施例需要预定义多个类型的64b/66b编码块。多个类型的64b/66b编码块包括：
S编码块，S编码块中的同步头为10，类型域包括帧头标志，帧头标志为0x78；
T编码块，T编码块中的同步头为10，类型域包括帧尾标志，帧尾标志为以下之一：0x87、0x99、0xaa、0xb4、0xcc、0xd2、0xe1或者0xff；
C编码块，C编码块包括C-I编码块和C-O编码块，其中，C-I编码块中的同步头为10，类型域为0x1E，信息域包括8个空闲控制字符，空闲控制字符的内容为7比特的0；C-O编码块中的同步头为10，类型域为0x4B，信息域的前28比特包含有序集控制信息的内容和类型，后28比特固定为“0x000_0000”；
D编码块，D编码块中的同步头为01；
E编码块，表示除S编码块、T编码块、C编码块、D编码块以外的编码块。
关于以上各类型64b/66b编码块的具体格式可参见图1以及上文对图1的相关描述，此处不再赘述。
可以理解的是，本申请实施例的64b/66b编码信号包括S编码块、T编码块、C编码块、D编码块或者E编码块的任意组合，本申请实施例在此不对64b/66b编码信号具体包含的64b/66b编码块类型、以及每个类型的64b/66b编码块的数量作过多的限定。
步骤S102：遍历64b/66b编码信号中的每个64b/66b编码块，在当前遍历的64b/66b编码块为S编码块且允许删除条件成立的情况下，将S编码块删除，得到降低速率的64b/66b编码信号。
可以理解的是，根据各类型的64b/66b编码块的定义，在媒体控制访问帧中，在没有错误发生的情况下，一个S编码块前面只可能包括零个或多个C编码块，而且如果媒体访问控制帧的速率很高，此时S编码块之前只有有限个数量的C编码块，且这些有限个数量的C编码块前面是一个T编码块。这些C编码只可能是C-I或C-O，如果有C-I存在，则可以通过删除C-I编码块的方式降低速率，如果只有C-O编码块，且不存在连续2个完全一样的C-O编码快，此时所有C-O编码块不可删除，此时初步符合删除S编码的条件，如果其他条件也满足则可删除S编码块，从而降低64b/66b编码信号的速率。需要注意的是，可以设置一个第一预设数值，并规定如果S编码块和前面最接近的T编码块之间存在N个C-O编码块，且任何一个C-O编码块都无法删除，且N为大于等于0且小于第一预设数值的整数，则初步符合删除S编码的条件。例如设置第一预设数值为3，即T和S之间存在小于3个C-O编码块时，可认为S编码块初步符合删除条件。一般来说，N不会太大，如果N很大或者T和S之间存在C-O以外的其他类型的64b/66b编码块，说明情况特殊，此时不能删除S编码块。值得特别注意的是，如果S前面是T，此时有0个C-O编码块，一定符合T和S之间存在小于第一预设数值个C-O编码块的条件。
可以理解的是，64b/66b编码信号中的多个64b/66b编码块是有前后顺序的，对于一个当前正在准备发送的64b/66b编码块，向前指已发送的64b/66b编码块，向后指后续等待发送且还没有来得及发送的64b/66b编码块，在具体实现步骤S102时，可以按照发送顺序依次遍历64b/66b编码信号中的每个正在准备发送的64b/66b编码块，且针对当前遍历到的64b/66b编码块执行以下处理：
a)确定当前遍历到的64b/66b编码块的类型；
b)若当前遍历到的64b/66b编码块的类型为S编码块，则在当前S编码块之前依次寻找，要么找到T，要么向前寻找第一预设数值次后停止寻找，如果能找到T，则继续后续处理，否则认为允许删除条件不成立；然后向后寻找第二预设数值个64b/66b编码块；
c)判断预设的允许删除条件是否成立，若成立，则将当前遍历到的64b/66b编码块(即S编码块)删除。
可以理解的是，本申请实施例描述的允许删除条件具体包括第一允许删除条件、第二允许删除条件、第三允许删除条件和第四允许删除条件，当第一允许删除条件、第二允许删除条件、第三允许删除条件、第四允许删除条件全部成立时允许删除条件成立。
示例性的，第一允许删除条件包括：当前遍历的S编码块之前存在N个C-O编码块，N个C-O编码块之前为1个T编码块，当前遍历的S编码块之后存在M个连续的D编码块，其中，N为大于等于0且小于第一预设数值的整数，M为等于第二预设数值的整数。
请参见图3，图3示出了一个64b/66b编码信号包含的部分编码块。在图3示例中，64b/66b编码信号的某一段依次出现了1个T编码块、N个C-O编码块、1个S编码块、M个连续的D编码块，那么可以将图3中的S编码块删除，达到降低64b/66b编码信号速率的目的。
可以理解的是，如果T编码块的后面存在C-I编码块，那么也可以通过删除C-I编码块来达到降低速率目的，而不必删除S编码块。考虑到上述情况的存在，本申请实施例的第一允许删除条件限定S编码块之前的N个C编码块需全部为C-O编码块，也就是说，T编码块和S编码块之间全部为C-O编码块时，才对S编码块进行删除处理。
可以理解的是，T编码块后面为N个C-O编码块，若这N个C-O编码块之中存在至少两个连续的C-O编码块是重复的(即信息域一致)，那么可通过删除C-O编码块来达到降低速率目的。考虑到上述情况的存在，本申请实施例的第一允许删除条件还可以包括：N个C-O编码块中的任意两个相邻C-O编码块的信息域不完全一致。
可以理解的是，本申请实施例的第一允许删除条件还可以包括：在特定情况下，N个C-O编码块之前的T编码块所属的媒体访问控制帧能正常通过帧检测序列(Frame Check Sequence)-32检测，该帧检测序列-32位于媒体访问控制帧帧尾前的4字节。
64b/66b编码块的主要功能是用于传送媒体访问控制帧，一个媒体访问控制帧对应多个64b/66b编码块，以S编码块开始，以T编码块结束，媒体访问控制帧实际是字节结构，由多个字节组成，媒体访问可控制帧实际对应S和T之间的所有D编码块，以及T编码块中的所有数据字节，媒体访问控制帧的结构如图4所示，媒体访问控制帧的所有字节实际可以分成两部分，即媒体访问控制帧内容和4字节的帧检测序列，其中媒体访问控制帧内容为K字节，K为大于等于60且小于3000的整数，帧检测序列用于对K字节的媒体访问控制帧内容做误码检测，误码检测算法为4字节长度的循环冗余校验-32(CRC-32，Cyclic Redundancy Check，-32表示32比特)，即在发送媒体访问控制帧时，针对K字节的媒体访问控制帧内容，按照CRC-32算法产生4字节的校验信息，并写入媒体访问控制帧的4字节的帧检测序列中，如果接收到媒体访问控制帧，则先针对K字节的媒体访问控制帧内容，按照CRC-32算法产生4字节的校验信息，然后和4字节的帧检测序列比较，如果完全一样说明无误码，否则说明有误码。以上方法也可称为帧检测序列-32检测，如果能通过帧检测序列-32检测则意味着媒体访问控制帧无误码，如果不能通过帧检测序列-32检测则意味着媒体访问控制帧有误码。在第一允许删除条件中额外增加以上条件，可以保证有误码时不会删除S编码块，防止以后在恢复速率处理阶段，不会因为误码导致错误地添加S编码块。但由于实现较为复杂，所以作为可选项，只在误码较为严重的场景下使用。
可以理解的是，当前遍历的S编码块的后面紧接着是M个D编码块，说明当前遍历的S编码块是一个媒体访问控制帧的开头，而当前遍历的S编码块前面的T编码块是另一个媒体访问控制帧的结尾。这里，在确定当前遍历的S编码块是一个媒体访问控制帧的开头的情况下，才会确定当前遍历的S编码块可以删除。
示例性的，第二允许删除条件包括：S编码块的信息域的后56比特为7字节的前导码，前导码为“0xaa”。
可以理解的是，根据IEEE 802.3标准中对64b/66b编码块的定义，第一个控制字符为帧头标志的64b/66b控制编码块中的块类型字段的取值为0x78(0x表示16进制，例如0x10表示16进制的10，即十进制的16)，64比特对应的8个字符中，第1个字符是帧头控制字符(即 帧头标志，也叫S控制字符，S表示start)，后面的7字节的数据字符，内容为0xaa，对应7字节的前导码，即第1个字符为帧头控制字符的64b/66b编码块内容为固定数值。但以上只是标准的规定，实际使用中可能会出现帧头控制字符后面的7个数据字符不是7字节的前导码的情况，所以可以将符合IEEE802.3标准的包头控制字符开头后面是7个前导码0xaa的64b/66b编码块命名为S-DEL编码块，将不符合IEEE802.3标准的帧头控制字符开头后面不是7个前导码0xaa的64b/66b编码块命名为S-NO-DEL编码块。需说明的是，在实施本申请实施例提供的64b/66b编码信号的处理方法时，所删除的S编码块均应当是S-DEL编码块。
可以理解的是，在遍历64b/66b编码信号中的每个64b/66b编码块的过程中，如果检测到当前遍历的64b/66b编码块的同步头为“10”、且类型域为“0x78”，那么还应当判断当前遍历的64b/66b编码块的信息域的最后56比特是否为7字节的前导码(固定值)，若是，则认为当前遍历的64b/66b编码块是S-DEL编码块，可删除；若否，则认为当前遍历的64b/66b编码块是S-NO-DEL编码块，不可删除。
示例性的，第三允许删除条件包括：接收到降低信号速率请求。
可以理解的是，64b/66b编码信号的发送端一般是在接收到降低信号速率请求的情况下，才执行本申请实施例提供的方法，将64b/66b编码信号的速率降低，得到降低速率的64b/66b编码信号，然后向对端设备发送该降低速率的64b/66b编码信号。
示例性的，第四允许删除条件包括：当前遍历的S编码块与上一次删除的S编码块之间的64b/66b编码块个数大于第三预设数值。
可以理解的是，为了防止64b/66b编码信号传输过程中引入的误码导致增加过多的S编码块，还需要额外增加一个删除条件，即连续两次删除S编码块的操作之间间隔的64b/66b编码块个数记为R，R必须大于第三预设数值，其中第三预设数值和R都是整数，且第三预设数值可根据需要修改。增加此条件是考虑到在恢复速率时，误码的存在较为容易导致原来不符合添加条件的D编码块符合添加条件，从而会导致多添加了S编码块，为了减小这种情况发生的概率，增加此删除条件，这样即使存在错误添加S编码块的情况，在R个64b/66b编码块中最多只能发生一次错误，从而最终限制错误发生的数量。可以理解的是，由于S编码块之间至少间隔8个64b/66b编码块，如果第三预设数值很小，此时此条件相当于不存在。
请参见图5，图5示出了一个64b/66b编码信号包含的部分编码块。在一种可能的实施方式中，64b/66b编码信号的发送端接收到降低信号速率请求，需要对如图5所示的64b/66b编码信号进行降低速率的处理，故开始遍历64b/66b编码信号中的64b/66b编码块，图5示出的64b/66b编码信号部分，包含了2个S编码块，且假定第1个S编码块满足允许删除条件，并对第1个S编码块进行删除操作；然后继续遍历第1个S编码块后面的64b/66b编码块，当遍历到第2个S编码块时，这里假定删除第1个S编码块是删除第2个S编码块之前的最近一次S编码块删除操作，由于第2个S编码块之前存在N个C-O编码块和1个T编码块，而且第2个S编码块与最近删除的第1个S编码块之间存在R个64b/66b编码块，R大于第三预设数值，所以第2个S编码块也符合允许删除条件，可以对第2个S编码块进行删除操作。
具体实现时，可以通过计数器对遍历的64b/66b编码块进行计数，每当对某个S编码块删除时，即对计数器进行清零以重新计数，当遍历到下一个S编码块，则根据计数器的计数确定当前S编码块与上一次删除的S编码块之间的64b/66b编码块个数是否大于第三预设数 值，如果大于第三预设数值，则删除当前S编码块，并对计数器进行清零以进行下一轮的计数。
可以理解的是，本申请实施例通过设置以上4个允许删除条件，在4个允许删除条件全部成立的情况下执行对S编码块的删除操作，可以保证后续对64b/66b编码信号恢复速率时所添加的S编码块的正确性。
步骤S103：发送降低速率的64b/66b编码信号。
可以理解的是，本申请实施例在允许删除条件成立的情况下，将S编码块删除，从而将64b/66b编码信号的速度降低，进而将降低速率的64b/66b编码信号发送给对端设备。
本申请实施例提供的降低64b/66b编码信号速率的方案，适用于媒体访问控制帧的速率很高时的情况，即使在媒体访问控制帧的速率很高时仍旧能通过删除特定64b/66b编码块来降低编码信号速率，且被删除的64b/66b编码块能在原来的位置正确恢复，现有方式无法用于媒体访问速率帧的速率很高时的情况，本申请实施例和现有方式结合，可在媒体访问控制帧为任何速率时都能降低64b/66b编码信号的速率。
本申请实施例在得到降低速率的64b/66b编码信号之后，执行发送降低速率的64b/66b编码信号，其中，发送降低速率的64b/66b编码信号具体可通过以下几种方式实现：
第一种，通过物理介质发送降低速率的64b/66b编码信号，其中物理介质可以是金属线或者光纤等物理传输介质，在此不对物理介质的具体类型作过多限定。
第二种，将降低速率的64b/66b编码信号封装至服务信号中，发送服务信号，其中服务信号可以是光数据单元信号，在此不对服务信号的具体类型作过多限定。
第三种，将降低速率的64b/66b编码信号转换为其他格式的编码信号，发送其他格式的编码信号。这里的其他格式的编码信号可以是除64b/66b编码格式以外的任意编码格式，例如256b/257b编码信号，在此不对其他格式的编码信号的具体格式作过多限定。
对应的，本申请实施例的方法还包括：接收降低速率的64b/66b编码信号，其中，降低速率的64b/66b编码信号具体可通过以下几种方式接收：
第一种，通过物理介质接收降低速率的64b/66b编码信号，其中物理介质可以是金属线或者光纤等物理传输介质，在此不对物理介质的具体类型作过多限定；
第二种，接收服务信号，从服务信号中提取出降低速率的64b/66b编码信号，其中服务信号可以是光数据单元信号，在此不对服务信号的具体类型作过多限定；
第三种，接收其他格式的编码信号，将其他格式的编码信号转换为降低速率的64b/66b编码信号，这里的其他格式的编码信号可以是除64b/66b编码格式以外的任意编码格式，例如256b/257b编码信号，在此不对其他格式的编码信号的具体格式作过多限定。
可以理解的是，设备如果接收到经上述步骤S102处理得到的降低速率的64b/66b编码信号，也可以基于64b/66b编码块的位置规则，向降低速率的64b/66b编码信号添加S编码块，以将64b/66b编码信号恢复至原来的速率。
请参见图6，图6示出了本申请另一实施例提供的64b/66b编码信号的处理方法的流程示意图，本实施例提供的64b/66b编码信号的处理方法包括以下步骤S201—S202，下面依次介绍各个步骤：
步骤S201：接收降低速率的64b/66b编码信号。
可以理解的是，这里的降低速率的64b/66b编码信号是采用如上文记载的通过对原始64b/66b编码信号中符合允许删除条件的S编码块进行删除操作所得到的。
步骤S202：遍历降低速率的64b/66b编码信号中的每个64b/66b编码块，在当前遍历的64b/66b编码块为D编码块且允许添加条件成立的情况下，在当前遍历的64b/66b编码块之前添加S编码块，以获得恢复速率的64b/66b编码信号。
可以理解的是，在接收到降低速率的64b/66b编码信号之后，需要对降低速率的64b/66b编码信号进行恢复，以获得原始的64b/66b编码信号。示例性的，如果出现连续多个D编码块，且第一个D编码块前面有N个C-O编码块，且N个C-O编码块前面还有1个T编码块，其中N为大于等于0且小于第一预设数值的整数，则初步符合在第一个D编码块前面添加一个S编码块的条件，从而获得恢复速率的64b/66b编码信号。
可以理解的是，本申请实施例向64b/66b编码信号添加的S编码块为满足特定规则的S编码块，具体地，S编码块中的同步头为“10”，块负荷的类型域包括帧头标志“0x78”，且块负荷的信息域的最后56比特为7字节的前导码(一般为7个0xaa)。
可以理解的是，本申请实施例描述的允许添加条件包括第一允许添加条件和第二允许添加条件，当第一允许添加条件和第二允许添加条件全部成立时允许添加条件成立。
示例性的，第一允许添加条件包括：当前遍历的D编码块之前存在N个C-O编码块，N个C-O编码块之前为1个T编码块，当前遍历的D编码块之后存在J个连续的D编码块，N为大于等于0且小于第一预设数值的整数，J为等于第四预设数值的整数，第四预设数值等于第二预设数值M减1。
基于上文描述的降低64b/66b编码信号速率的方案可知，允许删除S编码块的条件可以包括：S编码块之前存在N个C-O编码块，N个C-O编码块之前为1个T编码块，S编码块之后存在M(M等于J加1)个连续的D编码块，其中，N为大于等于0且小于第一预设数值的整数，M为等于第二预设数值的整数；满足以上条件即可将S编码块删除。对应的，在需要添加S编码块时，即可以检测64b/66b编码信号中是否存在1个T编码块、N个C-O编码块、M个D编码块依次排列的情况，若存在这种情况，则可以考虑在M个D编码块之中的第1个D编码块之前插入添加1个S编码块，所插入添加的S编码块位于C-O编码块和D编码块之间。
请参见图7，图7示出了一个降低速率的64b/66b编码信号包含的部分编码块。在一种可能的实施方式中，接收端接收到一个如图7所示的降低速率的64b/66b编码信号，并需要对其进行恢复速率的处理，故开始按照从前到后的顺序依次遍历该降低速率的64b/66b编码信号中的64b/66b编码块，图7示出的该降低速率的64b/66b编码信号的部分，依次出现了1个T编码块、N个C-O编码块、M个连续的D编码块，那么可以在第1个出现的D编码之前插入1个标准的S-DEL编码块，达到恢复64b/66b编码信号速率的目的。
可以理解的是，第一允许删除条件可以进一步包括：N个C-O编码块中的任意两个相邻C-O编码块的信息域不完全一致。对应的，本申请实施例的第一允许添加条件也可以进一步包括：N个C-O编码块中的任意两个相邻C-O编码块的信息域不完全一致。
可以理解的是，上述第一允许添加条件还可以包括：在特定情况下，N个C-O编码块之前的T编码块所属的媒体访问控制帧能正常通过帧检测序列(Frame Check Sequence)-32检测，该帧检测序列-32位于媒体访问控制帧帧尾前的4字节。
基于上文描述的降低64b/66b编码信号速率的方案可知，T编码块作为媒体访问控制帧的结尾，其前面存在4字节的帧检测信息，可以根据循环冗余校验-32算法判断媒体访问控制帧是否存在误码，如果不存在误码则意味着媒体访问控制帧能正常通过帧检测序列，如果存在误码则意味着媒体访问控制帧不能正常通过帧检测序列。在第一允许添加条件中额外增加以上条件，可以避免因为误码导致错误的添加S编码块。但由于实现较为复杂，所以作为可选项，只在误码较为严重的场景下使用。
示例性的，第二允许添加条件包括：当前遍历的D编码块与上一次添加的S编码块之间的64b/66b编码块个数大于第三预设数值。
基于上文描述的降低64b/66b编码信号速率的方案可知，S编码块的允许删除条件包括：当前遍历的S编码块与上一次删除的S编码块之间的64b/66b编码块个数大于第三预设数值。对应的，允许添加条件中也可以包括当前遍历的D编码块与上一次添加的S编码块之间的64b/66b编码块个数大于第三预设数值。设置此条件也是考虑到容错，如果因为误码导致媒体访问控制帧中间的一个D编码块变成了T编码块，则满足所有添加条件，从而导致误增加了一个S编码块，这种现象如果无法避免则必须设法减少。在删除和添加条件中加此限制就是为了让删除和添加动作不能太频繁，防止突发误码导致连续多个错误的添加动作发生。如果第三预设数值足够小，例如为4，由于媒体访问控制帧的帧长大于第三预设数值个64b/66b编码块，则此条件相当于不存在；可以根据媒体访问控制帧的最大帧长选择一个合适的第三预设数值，例如选择最大帧长作为第三预设数值，这样虽然降低64b/66b编码信号速率的效果会减弱，但存在突发误码时不会额外添加过多的S编码块。
请参见图8，图8示出了一个64b/66b编码信号包含的部分编码块。已知图8中的S编码块是上一次添加的S编码块；图8所示的第1个D编码块为当前遍历的64b/66b编码块，其前面为N个C-O编码块和T编码块，已满足第一允许添加条件，当前遍历的D编码块与上一次添加的S编码块之间相隔的64b/66b编码块数量为R，这时需要判断R的数值是否大于第三预设数值，若是，则确定当前遍历的D编码块满足第二允许添加条件，所以可以在其之前添加1个S编码块。
具体实现时，可以通过计数器对遍历的64b/66b编码块进行计数，每当对添加1个S编码块，即对计数器进行清零以重新计数，当遍历到下一个D编码块，则根据计数器的计数确定当前D编码块与上一次添加的S编码块之间的64b/66b编码块个数是否大于第三预设数值，如果大于第三预设数值，则在当前遍历的D编码块之前添加1个S编码块，并对计数器进行清零以进行下一轮的计数。
本申请实施例提供一种通信设备，包括发送模块和接收模块；其中，
发送模块用于：获取64b/66b编码信号，64b/66b编码信号包括多个64b/66b编码块，多个64b/66b编码块包括以下至少之一：S编码块、T编码块、C编码块、D编码块或者E编码块；遍历64b/66b编码信号中的每个64b/66b编码块，在当前遍历的64b/66b编码块为S编码块且允许删除条件成立的情况下，将S编码块删除，得到降低速率的64b/66b编码信号；发送降低速率的64b/66b编码信号；
接收模块用于：接收降低速率的64b/66b编码信号；遍历降低速率的64b/66b编码信号中的每个64b/66b编码块；在当前遍历的64b/66b编码块为D编码块且允许添加条件成立的情况下，在当前遍历的64b/66b编码块之前添加S编码块，以获得恢复速率的64b/66b编码信号。
该通信设备的具体实施方式与上述64b/66b编码信号的处理方法的具体实施例基本相同，在此不再赘述。
本申请实施例还提供了一种通信设备，如图9所示，该通信设备900包括但不限于：
至少一个处理器910；
至少一个存储器920，用于存储至少一个程序；
当至少一个程序被至少一个处理器910执行时执行如上任意实施例描述的64b/66b编码信号的处理方法。
应能理解的是，上述处理器910和存储器920可以通过总线或者其他方式连接。
应能理解的是，该处理器910可以采用中央处理单元(Central Processing Unit，CPU)。该处理器还可以是其它通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门矩阵(Field Programmable Gate Array，FPGA)或者其它可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。或者该处理器910采用一个或多个集成电路，用于执行相关程序，以实现本申请实施例所提供的技术方案。
存储器920作为一种非暂态计算机可读存储介质，可用于存储非暂态软件程序以及非暂态性计算机可执行程序，如本申请任意实施例描述的通信设备侧执行的64b/66b编码信号的处理方法。处理器910通过运行存储在存储器920中的非暂态软件程序以及指令，从而实现上述的64b/66b编码信号的处理方法。
存储器920可以包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需要的应用程序；存储数据区可存储执行上述的64b/66b编码信号的处理方法。此外，存储器920可以包括高速随机存取存储器，还可以包括非暂态存储器，比如至少一个磁盘存储器件、闪存器件、或其他非暂态固态存储器件。在一些实施方式中，存储器920可选包括相对于处理器910远程设置的存储器，这些远程存储器可以通过网络连接至该处理器910。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
实现上述的64b/66b编码信号的处理方法所需的非暂态软件程序以及指令存储在存储器920中，当被一个或者多个处理器910执行时，执行本申请任意实施例提供的64b/66b编码信号的处理方法。
本申请实施例还提供了一种计算机可读存储介质，计算机可读存储介质存储有处理器可执行的程序，处理器可执行的程序被处理器执行时用于实现如上任意实施例描述的64b/66b编码信号的处理方法。
本申请实施例的计算机存储介质，可以采用一个或多个计算机可读的介质的任意组合。计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质。计算机可读存储介质比如可以是，但不限于，电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本文件中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括、但不限于无线、电线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言或其组合来编写用于执行本申请操作的计算机程序代码，程序设计语言包括面向对象的程序设计语言—诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算机，或者，可以连接到外部计算机(比如利用因特网服务提供商来通过因特网连接)。
本申请实施例提供一种计算机程序产品，计算机程序产品存储有程序指令，程序指令在计算机上运行时，使得计算机实施如上任意实施例描述的64b/66b编码信号的处理方法。
以上是对本申请的若干实施方式进行的具体说明，但本申请并不局限于上述实施方式，熟悉本领域的技术人员在不违背本申请范围的共享条件下还可作出种种等同的变形或替换，这些等同的变形或替换均包括在本申请所限定的范围内。

Claims (21)

  1. 一种64b/66b编码信号的处理方法，所述方法包括：
    获取64b/66b编码信号，所述64b/66b编码信号包括多个64b/66b编码块，所述多个64b/66b编码块包括以下至少之一：S编码块、T编码块、C编码块、D编码块或者E编码块；
    遍历所述64b/66b编码信号中的每个所述64b/66b编码块，在当前遍历的64b/66b编码块为S编码块且允许删除条件成立的情况下，将所述S编码块删除，得到降低速率的64b/66b编码信号；
    发送降低速率的64b/66b编码信号。
  2. 根据权利要求1所述的方法，其中，所述64b/66b编码块包括2比特同步头和64比特块负荷，所述块负荷包括8比特类型域和56比特信息域；
    所述方法还包括：预定义多个类型的64b/66b编码块，所述多个类型的64b/66b编码块包括：
    所述S编码块，所述S编码块中的所述同步头为10，所述类型域包括帧头标志，所述帧头标志为0x78；
    所述T编码块，所述T编码块中的所述同步头为10，所述类型域包括帧尾标志，所述帧尾标志为以下之一：0x87、0x99、0xaa、0xb4、0xcc、0xd2、0xe1或者0xff；
    所述C编码块，所述C编码块包括C-I编码块和C-O编码块，其中，所述C-I编码块中的所述同步头为10，所述类型域为0x1E，所述信息域包括8个空闲控制字符，所述空闲控制字符为7比特的0；所述C-O编码块中的所述同步头为10，所述类型域为0x4B，所述信息域的前28比特包含有序集控制信息的内容和类型，所述信息域的后28比特固定为0x000_0000；
    所述D编码块，所述D编码块中的所述同步头为01；
    所述E编码块，表示除所述S编码块、所述T编码块、所述C编码块、所述D编码块以外的编码块。
  3. 根据权利要求2所述的方法，其中，所述允许删除条件包括第一允许删除条件、第二允许删除条件、第三允许删除条件和第四允许删除条件，当所述第一允许删除条件、第二允许删除条件、第三允许删除条件、第四允许删除条件全部成立时所述允许删除条件成立。
  4. 根据权利要求3所述的方法，其中，所述第一允许删除条件包括：当前遍历的S编码块之前存在N个C-O编码块，所述N个C-O编码块之前为1个T编码块，当前遍历的S编码块之后存在M个连续的D编码块，所述N为大于等于0且小于第一预设数值的整数，所述M为等于第二预设数值的整数。
  5. 根据权利要求4所述的方法，其中，所述N个C-O编码块中的任意两个相邻C-O编码块的信息域不完全一致。
  6. 根据权利要求4所述的方法，其中，在特定情况下，所述N个C-O编码块之前的所述T编码块所属的媒体访问控制帧能正常通过帧检测序列-32检测，所述帧检测序列-32位于媒体访问控制帧帧尾前的4字节。
  7. 根据权利要求3所述的方法，其中，所述第二允许删除条件包括：所述S编码块的所述信息域为7字节的前导码，所述前导码为0xaa。
  8. 根据权利要求3所述的方法，其中，所述第三允许删除条件包括：接收到降低信号速 率请求。
  9. 根据权利要求3所述的方法，其中，所述第四允许删除条件包括：当前遍历的所述S编码块与上一次删除的S编码块之间的64b/66b编码块个数大于第三预设数值。
  10. 根据权利要求1所述的方法，其中，所述发送降低速率的64b/66b编码信号，包括：
    通过物理介质发送所述降低速率的64b/66b编码信号；或者，
    将所述降低速率的64b/66b编码信号封装至服务信号中，发送所述服务信号；或者，
    将所述降低速率的64b/66b编码信号转换为其他格式的编码信号，发送所述其他格式的编码信号。
  11. 根据权利要求1所述的方法，其中，所述方法还包括：
    接收所述降低速率的64b/66b编码信号；
    遍历所述降低速率的64b/66b编码信号中的每个64b/66b编码块；
    在当前遍历的64b/66b编码块为所述D编码块且允许添加条件成立的情况下，在当前遍历的64b/66b编码块之前添加所述S编码块，添加的所述S编码块的信息域包括7字节的前导码，所述前导码为0xaa，以获得恢复速率的64b/66b编码信号。
  12. 根据权利要求11所述的方法，其中，所述允许添加条件包括第一允许添加条件和第二允许添加条件，当所述第一允许添加条件和所述第二允许添加条件全部成立时所述允许添加条件成立。
  13. 根据权利要求12所述的方法，其中，所述第一允许添加条件包括：当前遍历的D编码块之前存在N个C-O编码块，所述N个C-O编码块之前为1个T编码块，当前遍历的D编码块之后存在J个连续的D编码块，所述N为大于等于0且小于第一预设数值的整数，所述J为等于第四预设数值的整数，所述第四预设数值等于第二预设数值减1。
  14. 根据权利要求13所述的方法，其中，所述N个C-O编码块中的任意两个相邻C-O编码块的信息域不完全一致。
  15. 根据权利要求12所述的方法，其中，所述第二允许添加条件包括：当前遍历的D编码块与上一次添加的S编码块之间的64b/66b编码块个数大于第三预设数值。
  16. 根据权利要求13所述的方法，其中，在特定情况下，所述N个C-O编码块之前的所述T编码块所属的媒体访问控制帧能正常通过帧检测序列-32检测，所述帧检测序列-32位于媒体访问控制帧帧尾前的4字节。
  17. 根据权利要求11所述的方法，其中，所述接收所述降低速率的64b/66b编码信号，包括：
    通过物理介质接收所述降低速率的64b/66b编码信号；或者，
    接收服务信号，从所述服务信号中提取出所述降低速率的64b/66b编码信号；或者，
    接收其他格式的编码信号，将所述其他格式的编码信号转换为所述降低速率的64b/66b编码信号。
  18. 一种通信设备，包括发送模块和接收模块；其中，
    所述发送模块用于执行如权利要求1至10任意一项所述的64b/66b编码信号的处理方法；
    所述接收模块用于执行如权利要求11至17任意一项所述的64b/66b编码信号的处理方法。
  19. 一种通信设备，包括：
    至少一个处理器；
    至少一个存储器，用于存储至少一个程序；
    当至少一个所述程序被至少一个所述处理器执行时实现如权利要求1至17任意一项所述的64b/66b编码信号的处理方法。
  20. 一种计算机可读存储介质，其中存储有处理器可执行的程序，所述处理器可执行的程序被处理器执行时用于实现如权利要求1至17任意一项所述的64b/66b编码信号的处理方法。
  21. 一种计算机程序产品，包括计算机程序或计算机指令，所述计算机程序或所述计算机指令存储在计算机可读存储介质中，计算机设备的处理器从所述计算机可读存储介质读取所述计算机程序或所述计算机指令，所述处理器执行所述计算机程序或所述计算机指令，使得所述计算机设备执行如权利要求1至17任意一项所述的64b/66b编码信号的处理方法。
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