WO2021169184A1 - 一种线路编码方法及装置 - Google Patents

一种线路编码方法及装置 Download PDF

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Publication number
WO2021169184A1
WO2021169184A1 PCT/CN2020/108299 CN2020108299W WO2021169184A1 WO 2021169184 A1 WO2021169184 A1 WO 2021169184A1 CN 2020108299 W CN2020108299 W CN 2020108299W WO 2021169184 A1 WO2021169184 A1 WO 2021169184A1
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Prior art keywords
bit
block
blocks
header field
btf
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PCT/CN2020/108299
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English (en)
French (fr)
Inventor
王金山
柳剑飞
孙艳宾
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华为技术有限公司
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Publication of WO2021169184A1 publication Critical patent/WO2021169184A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H04L1/0058—Block-coded modulation

Definitions

  • This application relates to the field of communication technology, and in particular to a line coding method and device.
  • the line coding technology allows the sending end device to convert the information to be sent (such as data or control information, etc.) into a data format that the receiving end device can receive, while ensuring that there is enough clock information in the data stream to provide the clock recovery of the receiving end device Circuit.
  • the line coding technology provides a method for aligning data to bytes/words, which can maintain a good DC balance, increase the transmission distance of data, and provide a more effective error detection mechanism.
  • line coding technology can also be used to implement clock correction, block synchronization, and so on.
  • the sender device usually supports the IEEE802.3ch standard.
  • the IEEE802.3ch standard is generally used in scenarios where the transmission rate is 2.5G, 5G, or 10G, which can also be referred to as the 2.5/5/10GBASE-T1 standard, and uses 64B/65B line coding technology.
  • the 64B/65B line encoding technology refers to encoding an 8-byte (ie, 64-bit) character into a 65-bit (block).
  • the requirements for transmission rate continue to increase.
  • the embodiments of the present application provide a line coding method and device, so that a sending end can integrate multiple first blocks into a second block, thereby helping to reduce the overhead of line coding and thereby increasing the transmission rate.
  • an embodiment of the present application provides a line coding method, which is applied to a sending end device, which specifically includes: encoding every P bits of information to be sent into a first block; then, integrating the N first blocks into For the second block, after obtaining the M second blocks, perform RS-FEC encoding on the M second blocks to obtain an RS-FEC frame.
  • N and M are both greater than 1, and P, N and M are positive integers.
  • the transmitting end device can integrate N first blocks into a second block, and the number of bits of a second block is less than the number of bits of the N first blocks, it helps to reduce the line overhead and thereby Increase the transmission rate.
  • the information to be sent is less than P bits
  • the information to be sent is zero-filled to obtain P-bit information; then the P-bit information obtained after filling is encoded to obtain the first block. This helps to avoid the inability to encode the first block of the information to be sent when the information to be sent is less than P bits.
  • each 64 bits of the information to be sent is encoded into a 65-bit first block.
  • the data block includes a 1-bit first header field and a 64-bit first payload, and the first header field is used to indicate the value of the first payload.
  • the second block includes a 1-bit header field and N 64-bit first payloads, and the header field is used to indicate that the N first blocks are all data blocks. This helps simplify the implementation of integrating the N first blocks into one second block when the N first blocks are all data blocks.
  • the N 64-bit first loads are arranged in the order of encoding. This facilitates decoding by the receiving end device.
  • K first blocks of N 65-bit first blocks are data blocks
  • NK first blocks are control blocks
  • the data block includes a 1-bit first header field and 64 Bit first load
  • the first header field is used to indicate that the type of the first load is data
  • the control block includes a 1-bit second header field, 8-bit BTF and 56-bit second load
  • the second header field is used to Indicate that the type of the second payload is control information
  • the second block includes a 1-bit header field, L-bit BIF, 8-L-bit BTF, K 64-bit first payloads, and NK-1 8-bit BTF , And NK 56-bit second loads;
  • NK-1 8-bit BTF and an 8-L-bit BTF are respectively used to indicate the control type of one second load in NK 56-bit second loads, and the header field is used to indicate the existence of control in the N first blocks Block, 2 ⁇ L ⁇ 4, K is less than N, and K is a positive integer. This helps simplify the implementation of integrating the N first blocks into one second block when there are data blocks and control blocks in the N first blocks.
  • the 8-L bit BTF is used to indicate the control type of the second load of the first block that is encoded first among the N-K control blocks. This facilitates decoding by the receiving end device.
  • the control block includes a 1-bit second header field, an 8-bit BTF, and a 56-bit second payload.
  • the second header The field is used to indicate that the type of the second load is control information, and the second block includes a 1-bit header field, L-bit BIF, 8-L-bit BTF, N-1 8-bit BTF, and N 56-bits The second load;
  • N-1 8-bit BTFs and an 8-L-bit BTF are used to indicate the control type of one second load in the N 56-bit second loads, and the header field is used to indicate the N first blocks There are control blocks, 2 ⁇ L ⁇ 4, K is less than N, and K is a positive integer. This helps simplify the implementation of integrating the N first blocks into one second block when the N first blocks are all control blocks.
  • the 8-L bit BTF is used to indicate the control type of the second load of the first block obtained by encoding first among the N first blocks. This facilitates decoding by the receiving end device.
  • the block integration function is selected in the link synchronization phase or the auto-negotiation phase. This helps to facilitate decoding at the receiving end and improve the reliability of decoding.
  • an apparatus for sending specifically includes: a first encoding module, an integration module, and a second encoding module;
  • the first encoding module is used to encode every P bits of the information to be sent into a first block; P is a positive integer;
  • the integration module is used to integrate N first blocks into a second block; N is a positive integer greater than 1;
  • the second encoding module is used to perform RS-FEC encoding on M second blocks to obtain an RS-FEC frame; M is a positive integer greater than 1.
  • the first encoding module is specifically configured to perform zero padding on the information to be transmitted to obtain P-bit information if the information to be sent is less than P bits; and to encode the P-bit information obtained after padding to obtain The first piece.
  • the first encoding module is used to encode every 64 bits of the information to be sent into a 65-bit first block based on the 64B/65B line encoding technology.
  • the data block includes a 1-bit first header field and a 64-bit first payload, and the first header field is used to indicate the value of the first payload.
  • the second block includes a 1-bit header field and N 64-bit first payloads, and the header field is used to indicate that the N first blocks are all data blocks.
  • the N 64-bit first loads are arranged in the order of encoding.
  • K first blocks of N 65-bit first blocks are data blocks
  • NK first blocks are control blocks
  • the data block includes a 1-bit first header field and 64 Bit first load
  • the first header field is used to indicate that the type of the first load is data
  • the control block includes a 1-bit second header field, 8-bit BTF and 56-bit second load
  • the second header field is used to Indicate that the type of the second payload is control information
  • the second block includes a 1-bit header field, L-bit BIF, 8-L-bit BTF, K 64-bit first payloads, and NK-1 8-bit BTF , And NK 56-bit second loads;
  • NK-1 8-bit BTF and an 8-L-bit BTF are respectively used to indicate the control type of one second load in NK 56-bit second loads, and the header field is used to indicate the existence of control in the N first blocks Block, 2 ⁇ L ⁇ 4, K is less than N, and K is a positive integer.
  • the 8-L bit BTF is used to indicate the control type of the second load of the first block that is encoded first among the N-K control blocks.
  • the control block includes a 1-bit second header field, an 8-bit block type field BTF, and a 56-bit second payload.
  • the second header field is used to indicate that the type of the second load is control information, and the second block includes a 1-bit header field, an L-bit block indicator field BIF, an 8-L-bit BTF, and N-1 8-bit BTF, and N 56-bit second loads;
  • N-1 8-bit BTF and an 8-L-bit BTF are used to indicate the control type of one second load in the N 56-bit second loads, and the header field is used to indicate that there is control in the N first blocks.
  • Block, 2 ⁇ L ⁇ 4, K is less than N, and K is a positive integer.
  • the device also includes a function selection module
  • the function selection module is used to select the block integration function in the link synchronization phase or the auto-negotiation phase.
  • a device for sending provided in an embodiment of this application includes a processor and a memory, where the memory stores program instructions, and when the processor executes the program instructions, it executes the above-mentioned aspects and Any possible design method involved in all aspects.
  • a device for sending provided in an embodiment of the present application includes a device that executes the foregoing aspects of the embodiments of the present application and any possible design method involved in each aspect.
  • a chip provided by an embodiment of the present application includes a processor and an interface, configured to call and run the program instructions stored in the memory from the memory, and execute the above-mentioned aspects and the various aspects related to the embodiments of the present application. Any possible design method.
  • a computer storage medium stores program instructions.
  • the program instructions When the program instructions are executed on an electronic device, the electronic device executes the above-mentioned aspects and aspects of the embodiments of the present application. Any possible design method involved.
  • a computer program product of an embodiment of the present application when the computer program product runs on an electronic device, causes the electronic device to execute and implement the above-mentioned aspects of the embodiments of the present application and any possibility involved in each aspect The method of design.
  • FIG. 1 is a schematic diagram of a format of a data block according to an embodiment of the application
  • FIG. 2 is a schematic diagram of a format of a control block according to an embodiment of the application
  • FIG. 3 is a schematic flowchart of a multi-threaded encoding method according to an embodiment of the application.
  • FIG. 4 is a schematic diagram of a coding principle according to an embodiment of the application.
  • FIG. 5A is a schematic diagram of integrating the second block according to an embodiment of the application.
  • FIG. 5B is another schematic diagram of integrating the second block according to an embodiment of the application.
  • 6A is another schematic diagram of integrating the second block according to an embodiment of the application.
  • FIG. 6B is another schematic diagram of integrating the second block according to an embodiment of the application.
  • FIG. 7A is another schematic diagram of integrating the second block according to an embodiment of the application.
  • FIG. 7B is another schematic diagram of integrating the second block according to an embodiment of the application.
  • FIG. 7C is another schematic diagram of integrating the second block according to an embodiment of the application.
  • FIG. 8A is another schematic diagram of integrating the second block according to an embodiment of the application.
  • FIG. 8B is another schematic diagram of integrating the second block according to an embodiment of the application.
  • FIG. 9A is another schematic diagram of integrating the second block according to an embodiment of the application.
  • FIG. 9B is another schematic diagram of integrating the second block according to an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of an apparatus for sending according to an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of another device for sending according to an embodiment of the application.
  • At least one in the embodiments of the present application refers to one or more.
  • “Multiple” means two or more.
  • “And/or” describes the association relationship of the associated objects, indicating that there can be three types of relationships.
  • a and/or B can mean that: A alone exists, A and B exist at the same time, and B exists alone. Among them, A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects before and after are in an “or” relationship.
  • the following at least one (item) or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • At least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c.
  • each of a, b, and c can be an element itself, or a collection containing one or more elements.
  • the IEEE802.3bw standard is used in scenarios with a transmission rate of 100M, which can also be called the 100BASE-T1 standard, and uses 4B/5B line coding technology.
  • the IEEE802.3bp standard is used in scenarios with a transmission rate of 1000M, which can also be called the 1000BASE-T1 standard, and uses 80/81B line coding technology.
  • the IEEE802.3ch standard is used in scenarios where the transmission rate is 2.5G, 5G or 10G, using 64B/65B line coding technology.
  • the sender device usually supports the IEEE802.3ch standard. That is to say, the sending end equipment is encoded based on the 64B/65B line encoding technology.
  • the requirements for transmission rate continue to increase.
  • the future evolution of the vehicle Ethernet network supports a transmission rate of 25G.
  • 128B/129B line coding technology can be used.
  • the line coding can be reduced. Overhead, but by adding line coding technology to the sending end device, the improvement of the device is greater, and the loadability of the implementation is also increased.
  • the block format of the data block as shown in FIG. 1 includes a first header field and a first payload (payload).
  • the first header field includes T bits, which are used to indicate that the type of the first load is data.
  • the first load includes P bits.
  • T and P are positive integers.
  • the number of bits in the first header field can be the same or different.
  • the number of bits of the first load may be the same or different.
  • the data block when the data block is obtained based on the 64B/65B line coding technology, that is, when the data block is obtained by encoding 64-bit characters, the data block is 65 bits, the first header field is 1 bit, and the first The payload is 64 bits.
  • the first header field is 0, which is used to indicate that the type of the first load is data.
  • the data block is obtained based on 64B/66B line coding technology, that is, when the data block is obtained by encoding 64-bit characters, the data block is 66 bits, the first header field is 2 bits, and the first header field is 2 bits.
  • One payload is 64 bits.
  • control block Specifically, the block format of the control block may be as shown in FIG. 2, including a second header field, a block type field (BTF), and a second payload.
  • the second header field is a T bit, which is used to indicate that the type of the second load is control information.
  • BTF is the R bit, which is used to indicate the control type of the second load.
  • the block format of the control block may also include other fields, which are not limited.
  • the number of bits in the second header field, the number of bits in the BTF, and the number of bits in the second load are related to the line coding technology.
  • the number of bits in the second header field can be the same or different.
  • the number of BTF bits can be the same or different.
  • the number of bits of the second load may be the same or different.
  • control block is 65 bits.
  • the second header field is 1 bit
  • the BTF is 8 bits
  • the second payload is 56 bits.
  • the control type of the second load usually includes 15 types, and different BTFs are used to indicate the second load of different control types. As shown in Table 1.
  • BTF is 0x1E, which is used to indicate that the control type of the second load is control type 1.
  • a line coding method which is applied to a transmitting end device, specifically includes the following steps.
  • Step 301 Encode every P bits of the information to be sent into a first block.
  • P is a positive integer.
  • the value of P is related to the line coding technology adopted by the transmitting end device. For example, when the transmitting end device adopts the 64B/65B line coding technology, the value of P is 64. For another example, when the transmitting end device adopts the 80B/81B line coding technology, the value of P is 80.
  • the media access control (MAC) layer of the sender device sends the information to be sent to the physical layer through the XGMII interface, and the physical layer encodes every P bits of the information to be sent as a first Piece. Specifically, the physical layer adds a T-bit header field before the P-bit information to be sent to obtain a first block.
  • the value of T is related to the line coding technology adopted by the transmitting end device. For example, when the transmitting end device adopts the 64B/65B line coding technology, the value of T is 1. For another example, when the transmitting end device adopts the 64B/66B line coding technology, the value of T is 2.
  • the physical layer is based on the 64B/65B line coding technology, which encodes every 64 bits of the information to be sent into a 65-bit first block. Specifically, the physical layer adds a 1-bit header field before the 64-bit information to be sent to obtain a 65-bit first block.
  • the header field added before the information to be sent is related to whether the information to be sent contains control information. For example, when the 64-bit information to be sent contains control information, a second header field is added before the 64-bit information to be sent. For another example, when the 64-bit information to be sent does not contain control information, the first header field is added before the 64-bit information to be sent.
  • the information to be sent when the information to be sent does not satisfy the P bits, the information to be sent is zero-filled to obtain P-bit information; the P-bit information obtained after filling is encoded to obtain the first block.
  • the sending end device encodes multiple first blocks, when the remaining part of the information to be sent does not satisfy the P bit, 0 is added after the remaining part of the information to be sent, until the value of the information to be sent after 0 is added. The remaining part reaches P bits, and then the remaining part of the information to be sent after adding 0 is coded to obtain the first block.
  • the zero padding of the information to be sent may be performed by the MAC layer or the physical layer, which is not limited.
  • 64B/65B line coding technology Take 64B/65B line coding technology as an example. For example, if the information to be sent is 60 bits, add 4 0s after the 60 bits of information to be sent to obtain 64-bit information, and then add 1 bit before the 64-bit information obtained by adding 4 0s Header field to get the first block.
  • Step 302 Integrate the N first blocks into a second block. Wherein, N>1, and N is a positive integer.
  • the N first blocks are integrated into one second block.
  • the sending end device can perform parallel encoding on the information to be sent.
  • the sending end device may encode multiple first blocks each time for the information to be sent.
  • the transmitting end device may integrate the N first blocks obtained this time into one second block.
  • the sending end device can also encode N blocks at a time.
  • the first block is integrated to obtain a second block, or the first block can be integrated in parallel to obtain multiple second blocks each time.
  • the sending end device may encode 2N first blocks each time for the information to be sent, and may integrate the first block in parallel to obtain two second blocks each time.
  • the sending end device may also encode a first block each time for the information to be sent. After the sending end device obtains the N first blocks, the N first blocks are integrated to obtain a second block.
  • Step 303 Perform Reed-Solomon forward error correction coding (RS-REC) coding on the M second blocks to obtain an RS-REC frame, M>1, and M is a positive integer.
  • RS-REC Reed-Solomon forward error correction coding
  • the sending end device may perform RS-REC encoding according to M second blocks and R X-bit operation management maintenance (OAM) symbols to obtain RS-REC encoding.
  • the OAM symbol may include information used to indicate the communication quality of the device.
  • the OAM symbol is used to indicate the level of the signal-to-noise ratio (signal noise ratio, SNR).
  • the OAM symbol can also be used to indicate additional information, such as user-defined information.
  • the value of R is greater than 1, the information indicated by different OAM symbols may be different. For example, take the value of R as 2 as an example.
  • One OAM symbol is used to indicate information about the communication quality of the device, and the other OAM symbol is used to indicate additional information.
  • one OAM symbol is used to indicate the information of the communication quality of the device and part of the additional information, and the other OAM symbol is used to indicate another part of the additional information.
  • the physical layer when it obtains M second blocks, it uses M second blocks and R X-bit operation management maintenance (OAM) symbols as the input of the RS-REC encoder.
  • the REC encoder performs encoding to obtain an RS-FEC frame.
  • the sending end device may also perform according to M second blocks.
  • Blocks, R X-bit OAM symbols and padding are RS-REC encoded to obtain an RS-REC frame.
  • the padding bit (padding) may be at least one zero.
  • the values of M, R, X, and padding can be set according to actual needs. Take 64B/65B line coding technology as an example.
  • the value of N can be 2
  • the value of M can be set to 25
  • the value of R can be set to 2
  • the value of X can be 10.
  • the value of the number of bits of M, R, X, and padding can be pre-defined through the protocol, or determined by the sending end device according to a certain algorithm or rule.
  • the method of determining the value of the number is not limited, as long as the value of the number of bits of M, R, X, and padding is such that the sum of the number of M second blocks, R and X bits of OAM and padding meets the RS-REC encoder The number of input bits is sufficient.
  • M second blocks, R X-bit OAM symbols and padding are used as the input of the RS-REC encoder. Then, it is encoded by the RS-REC encoder to obtain the RS-FEC frame.
  • the number of bits in the second block is 129.
  • two 65-bit first blocks are integrated into a 129-bit second block.
  • 25 second blocks After 25 second blocks are obtained, 25 second blocks, 2 10-bit OAM symbols,
  • padding is used as the input of the RS-REC encoder to perform RS-FEC encoding to form a 3600-bit RS-FEC frame.
  • the 25 second blocks are arranged in the order obtained by encoding, the two 10-bit OAM symbols are located after the 25 second blocks, and the padding is located after the OAM symbols.
  • the sending-end device may interact with the capabilities supported by each in the process of link synchronization or auto-negotiation between the sending-end device and the receiving-end device.
  • the block integration capability can be selected to execute the line coding method of the embodiment of the present application. To improve the success rate of transmission.
  • the block integration capability is used to indicate that the device can execute the line coding method as shown in FIG. 3.
  • the sending end device may interact with the receiving end device via one or more reserved bits in a link code word (LCW) with the capabilities supported by each.
  • LCW link code word
  • the LCW includes 27 bits, which are A0 to A26, where A0 and A2-A5 are already occupied, and A1 and A6-A26 are reserved bits.
  • the capabilities indicated by bits A0 and A2-A5 can be as shown in Table 2.
  • the A6 sender device and receiver device in Link Codeword can interact with each other's supported block integration capabilities.
  • A6 in the Link Codeword indicates that the sender device supports the 25GBASE-T1 capability, and the sender device supports the block integration capability.
  • A6 in the Link Codeword indicates that the receiving end device supports 25GBASE-T1 capability, and the receiving end device supports the block integration capability.
  • the sender device may choose to enable the block integration capability when it detects that the current network supports a transmission rate not less than a certain threshold (for example, 25G) when both the sender device and the receiver device support the block integration capability.
  • a certain threshold for example, 25G
  • Example 1 The first blocks of N 65 bits are all data blocks.
  • the second block Integrating the 1-bit header field and the first loads of the N first blocks into the first second block, the second block includes a 1-bit header field and N 64-bit first loads.
  • the 1-bit header field is used to indicate that the N first blocks are all data blocks.
  • the first loads of the N first blocks are arranged in the second block according to the sequence obtained by encoding. In order to facilitate the receiving end equipment to read.
  • the value of N is 2, and the first blocks of N 65 bits are data block 1 and data block 2.
  • data block 1 includes a first header field 1 and a first payload 1, and data block 2 It includes the first header field 2 and the first payload 2.
  • the transmitting end device first obtains the data block 1 and then the data block 2 based on the 64B/65B line coding technology.
  • the second block obtained by integrating data block 1 and data block 2 includes a 1-bit header field, a first load 1 and a first load 2, the header field is located before the first load 1, and the first load 1 is located at the first load 2.
  • the first load 1 is located at the first load 2.
  • the value of N is 4, and the first blocks of N 65 bits are data block 1, data block 2, data block 3, and data block 4.
  • data block 1 includes a first header field 1.
  • the first payload 1 the data block 2 includes the first header field 2 and the first payload 2
  • the data block 3 includes the first header field 3 and the first payload 3
  • the data block 4 includes the first header field 4 and the first payload 4.
  • the transmitting end device sequentially obtains data block 1, data block 2, data block 3, and data block 4 based on the 64B/65B line coding technology.
  • the second block obtained by integrating data block 1, data block 2, data block 3, and data block 4 includes a 1-bit header field, a first load 1, a first load 2, a first load 3, and a first load 4.
  • the header field is located before the first load 1, the first load 1 is located before the first load 2, the first load 2 is located before the first load 3, and the first load 3 is located before the first load 4.
  • the first loads of the N first blocks in the second block may also be arranged in another order, which is not limited. For example, they are arranged in the order of transmission from the MAC layer to the physical layer.
  • Example 2 Among N 65-bit first blocks, K first blocks are data blocks, and N-K first blocks are control blocks.
  • the 1-bit header field, K first blocks of the first payload, L-bit BIF, 8-L-bit BTF, NK-1 8-bit BTF, and NK first block’s second payload are integrated into the first A second block
  • the second block includes a 1-bit header field, an L-bit block indicator field BIF, 8-L-bit BTF, K 64-bit first payloads, NK-1 8-bit BTF, And the second load of the NK first block.
  • the 1-bit header field is used to indicate that there are control blocks in the N first blocks.
  • 64B/65B line coding technology since there are 15 control types in the 64B/65B line coding technology, which are indicated by 8-bit information, a BTF has 4-bit redundancy. Therefore, the BTF bit The minimum number can be 4.
  • the value of N is 2, the value of L can be 2, 3, or 4, and the value of L is 2 as an example.
  • the first block of N 65 bits is data block 1 and control block 1. As shown in FIG. 6A, data block 1 includes a first header field 1 and a first payload 1, and control block 1 includes a second header field 1 and 8 bits.
  • the BTF and the second load 1, the first load 1, the 8-bit BTF and the second load 1 are integrated into a second load.
  • the second load includes a 1-bit header field, a 4-bit BIF, a first load 1, 4-bit BTF and second load 1. Among them, the 4-bit BIF is used to indicate the positional relationship between the first load 1 and the second load 1.
  • the 4-bit BTF used to indicate the control type of the second load 1 is obtained according to the 8-bit BTF in the control block 1.
  • the value of N is 2, the value of L is 4, and there are two redundant bits in a 4-bit BIF, and the two redundant bits can be defined in advance.
  • define the first Bits 3 and 4 are redundant bits.
  • the first and second bits in the BIF are 0 and 1, respectively, it indicates that the first load 1 is before the second load 1.
  • the first and second bits in the BIF are 1, 0, it indicates the first load.
  • the second load 1 is before the first load.
  • the data block 1 is coded before the control block 1 based on the 64B/65B line coding technology
  • the second block may be as shown in FIG. 6A.
  • the control block 1 is coded before the data block 1 based on the 64B/65B line coding technology
  • the second block may be as shown in FIG. 6B.
  • the value of N is 4, and the value of L can be 4.
  • the first block of N 65 bits is data block 1, data block 2, data block 3, and control block 1.
  • data block 1 includes a first header field 1 and a first payload 1
  • data block 2 includes The first header field 2 and the first load 2
  • data block 3 includes the first header field 3 and the first load 3
  • control block 1 includes the second header field 1, the 8-bit BTF and the second load 1, and the first load 1.
  • the first load 2, the first load 3, the 8-bit BTF and the second load 1 are integrated into a second load.
  • the second load includes a 1-bit header field, a 4-bit BIF, the first load 1, the first load Load 2, first load 3, 4-bit BTF, and second load 1.
  • the 4-bit BIF is used to indicate the positional relationship between the first load 1, the first load 2, the first load 3, and the second load 1.
  • the BIF can be 0001
  • the second block can be as shown in Figure 7A, with a 1-bit header field
  • the BIF is before the first load 1
  • the first load 1 is before the first load 2
  • the first load 2 is before the first load 3
  • the first load 3 is before the 4-bit BTF.
  • the BTF is located before the second load 1.
  • the BIF can be 0010
  • the second block can be as shown in Figure 7B, with a 1-bit header
  • the field is located before the 4-bit BIF
  • the 4-bit BIF is located before the first load 1
  • the first load 1 is located before the first load 2
  • the first load 2 is located before the 4-bit BTF
  • the 4-bit BTF is located at the second load 1.
  • the second load 1 was located before the first load 3.
  • the BIF can be 1000
  • the second block can be as shown in Figure 7C, with a 1-bit header
  • the field is located before the 4-bit BIF
  • the 4-bit BIF is located before the first load 1
  • the first load 1 is located before the first load 2
  • the first load 2 is located before the 4-bit BTF
  • the 4-bit BTF is located at the second load 1.
  • the second load 1 was located before the first load 3.
  • the value of N is 4, and the value of L can be 4.
  • the first block of N 65 bits is data block 1, data block 2, control block 1, and control block 2.
  • data block 1 includes a first header field 1 and a first payload 1
  • data block 2 includes The first header field 2 and the first payload 2
  • the control block 1 includes the second header field 1, the 8-bit BTF1, and the second payload 1
  • the control block 2 includes the second header field 2, the 8-bit BTF2, and the second payload 1.
  • the first load 1, the first load 2, the 8-bit BTF1, the second load 1, the 8-bit BTF2, and the second load 2 are integrated into a second load.
  • the second load includes a 1-bit header field and a 4-bit The first load 1, the first load 2, the 4-bit BTF, the second load 1, the 8-bit BTF2, and the second load 2.
  • the 4-bit BIF is used to indicate the positional relationship between the first load 1, the first load 2, the second load 1, and the second load 2.
  • control block 1 may be coded before the control block 2, or the control block 2 may be coded before the control block 1.
  • the BIF can be 1001
  • the second block can be as shown in Figure 8A, with a 1-bit header field It is located before the 4-bit BIF, the BIF is located before the 4-bit BTF, the 4-bit BTF is located before the second load 1, the second load 1 is located before the first load 1, and the first load 1 is located before the first load 2.
  • Payload 2 is located before the 8-bit BTF2, and the 8-bit BTF2 is located before the second payload 2.
  • the BIF can be 1001
  • the second block can be shown in Figure 8B, with a 1-bit header field
  • the BIF is before the 8-bit BTF1
  • the 8-bit BTF1 is before the second load 1
  • the second load 1 is before the first load 1
  • the first load 1 is before the first load 2.
  • Payload 2 is located before the 4-bit BTF
  • the 4-bit BTF is located before the second payload 2.
  • the 1-bit header field, K first payloads of the first block, L-bit BIF, NK The bit BTF and the second load of the NK first block are integrated into the first second block.
  • the second block includes a 1-bit header field, an L-bit block indicator field BIF, K 64-bit first loads, NK Bit BTF, and NK second load of the first block.
  • the 1-bit header field is used to indicate that there are control blocks in the N first blocks.
  • NK The bit BTF is respectively used to indicate the control type of a second load. NK ⁇ L ⁇ 4*(NK).
  • Example 3 The first blocks of N 65 bits are all control blocks.
  • the second The block includes a 1-bit header field, an L-bit BIF, an 8-L-bit BTF, and N first blocks of the first payload.
  • the 1-bit header field is used to indicate that there are control blocks in the N first blocks. 2 ⁇ L ⁇ 4.
  • the 8-L bit BTF is used to indicate the control type of the second load of the first block that is encoded first among the N first blocks, and it can also be used to indicate the control type of the first block of the N first blocks.
  • the control type of the second load is not limited.
  • control block 1 includes a second header field 1, an 8-bit BTF1 and a second load 1, and control block 2 includes a second header.
  • the 8-bit BTF1, second payload 1, BTF2, and second payload 2 are integrated into a second payload.
  • the second payload includes a 1-bit header field and a 4-bit payload.
  • the 4-bit BIF is used to indicate the positional relationship between the second load 1 and the second load 2.
  • the 4-bit BTF used to indicate the control type of the second load 1 is obtained according to the 8-bit BTF1 in the control block 1.
  • the two redundant bits can be defined in advance.
  • define the first Bits 3 and 4 are redundant bits.
  • the first and second bits in the BIF are 0 and 1, respectively, it indicates that the first load 1 is before the second load 1.
  • the first and second bits in the BIF are 1, 0, it indicates the first load.
  • the second load 1 is before the first load.
  • the control block 1 is coded before the control block 1 based on the 64B/65B line coding technology
  • the second block may be as shown in FIG. 9A.
  • the control block 1 is coded before the control block 2 based on the 64B/65B line coding technology
  • the second block can also be as shown in FIG. 9B.
  • the 1-bit header field, the L-bit BIF, and N The bit BTF and the second load of the N first block are integrated into the first second block, then the second block includes a 1-bit header field, an L-bit block indicator field BIF, and N Bit BTF, and N second load of the first block.
  • the 1-bit header field is used to indicate that there are control blocks in the N first blocks.
  • N The bit BTF is respectively used to indicate the control type of a second load. NK ⁇ L ⁇ 4*(NK).
  • the receiving end device After receiving the information from the sending end device, the receiving end device demodulates the information from the sending end device to obtain an RS-FEC frame.
  • the receiving device decomposes the RS-FEC frame into M second blocks, and decomposes each second block into N 65-bit first blocks, and then divides the RS-FEC frame into N 65-bit first blocks. The first block is processed.
  • the line coding method in the embodiment of the present application can also be applied to other line coding technologies besides the 64B/65B line coding technology, such as the 64B/66B line coding technology.
  • the 64B/65B line coding technology such as the 64B/66B line coding technology.
  • the above is only an example for illustration. It does not constitute a limitation to the embodiments of the present application.
  • the communication method provided in the embodiments of the present application is introduced from the perspective of a terminal device as an execution subject.
  • the terminal device may include a hardware structure and/or a software module, and realize the above functions in the form of a hardware structure, a software module, or a hardware structure plus a software module. Whether a certain function among the above-mentioned functions is executed by a hardware structure, a software module, or a hardware structure plus a software module depends on the specific application and design constraint conditions of the technical solution.
  • an embodiment of the present application further provides a device for sending.
  • the device includes a first encoding module 1001, an integration module 1002, and a second encoding module 1003.
  • the first encoding module 1001 is configured to encode every P bits of the information to be sent into a first block; P is a positive integer;
  • the integration module 1002 is used to integrate N first blocks into a second block; N is a positive integer greater than 1;
  • the second encoding module 1003 is configured to perform RS-FEC encoding on M second blocks to obtain an RS-FEC frame; M is a positive integer greater than 1.
  • the device further includes a function selection module 1004.
  • the function selection module 1004 is used to select the block integration function in the link synchronization phase or the auto-negotiation phase.
  • the device includes a processor 1101 and a memory 1102.
  • the device may be a device for sending, or a device in a device for sending.
  • the device may be a chip system.
  • the chip system may be composed of chips, or may include chips and other discrete devices.
  • the processor 1101 calls the program instructions stored in the memory 1102 to execute the multi-line encoding method shown in FIG. 3.
  • the division of modules in the embodiments of this application is illustrative, and it is only a logical function division. In actual implementation, there may be other division methods.
  • the functional modules in the various embodiments of this application can be integrated into one process. In the device, it can also exist alone physically, or two or more modules can be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or software functional modules.
  • the processor may be a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, which may implement or Perform the methods, steps, and logic block diagrams disclosed in the embodiments of the present application.
  • the general-purpose processor may be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed and completed by a hardware processor, or executed and completed by a combination of hardware and software modules in the processor.
  • the memory may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., or a volatile memory (volatile memory), for example Random-access memory (random-access memory, RAM).
  • the memory is any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and that can be accessed by a computer, but is not limited to this.
  • the memory in the embodiments of the present application may also be a circuit or any other device capable of realizing a storage function for storing program instructions and/or data.
  • the methods provided in the embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software When implemented by software, it can be implemented in the form of a computer program product in whole or in part.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, network equipment, user equipment, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital video disc (digital video disc, DVD for short)), or a semiconductor medium (for example, SSD).

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Abstract

一种线路编码方法及装置，涉及通信技术领域。其中，该方法应用于发送端设备，包括：将待发送的信息每P比特编码为一个第一块；然后将N个第一块整合为第二块，并对M个第二块进行RS-FEC编码，得到RS-FEC帧。其中，N、M均大于1，且P、N和M为正整数。这种技术方案有助于降低线路开销，进而提高传输速率。

Description

一种线路编码方法及装置
相关申请的交叉引用
本申请要求在2020年02月25日提交中国专利局、申请号为202010115425.2、申请名称为“一种线路编码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，特别涉及一种线路编码方法及装置。
背景技术
线路编码技术使得发送端设备可以将待发送的信息(例如数据或控制信息等)转变为接收端设备可接收的数据格式，同时保证数据流中有足够的时钟信息提供给接收端设备的时钟恢复电路。具体的，线路编码技术提供了一种将数据对齐到字节/字的方法，可以保持良好的直流平衡，增加数据的传输距离，提供更为有效的错误检测机制。此外，线路编码技术还可以用来实现时钟修正、块同步等。
目前，发送端设备通常支持IEEE802.3ch标准。具体的，IEEE802.3ch标准一般应用于传输速率为2.5G、5G或10G的场景中，又可以称之为2.5/5/10GBASE-T1标准，采用64B/65B线路编码技术。其中，64B/65B线路编码技术指的是将8字节(即64比特)的字符编码为一个65比特(bit)的块(Block)。然而，随着通信技术的进步，对传输速率的要求不断提高，对于传输速率更高的场景来说，例如传输速率为25G的场景来说，如果发送端设备继续采用64B/65B线路技术，容易导致线路编码开销较大，进而对信道的带宽要求增加，波特率也会随之增加。
发明内容
本申请实施例提供了一种线路编码方法及装置，使得发送端能够将多个第一块整合为第二块，从而有助于降低线路编码的开销，进而提高传输速率。
第一方面，本申请实施例提供了一种线路编码方法，应用于发送端设备，具体包括：将待发送的信息每P比特编码为一个第一块；然后，将N个第一块整合为第二块，在得到M个第二块之后，对M个第二块进行RS-FEC编码，得到RS-FEC帧。其中，N、M均大于1，且P、N和M为正整数。
本申请实施中由于发送端设备能够将N个第一块整合为一个第二块，而一个第二块的比特数小于N个第一块的比特数，因此，有助于降低线路开销，进而提高传输速率。
在一种可能的设计中，若待发送的信息不足P比特时，对待发送的信息进行零填充，得到P比特信息；然后对填充后得到的P比特信息进行编码，得到第一块。从而有助于避免当待发送信息不足P比特时，无法实现将待发送的信息编码第一块。
在一种可能的设计中，基于64B/65B线路编码技术，将待发送的信息每64比特编码为一个65比特的第一块。
在一种可能的设计中，若N个第一块均为数据块，其中，数据块包括1比特的第一头字段和64比特的第一负载，第一头字段用于指示第一负载的类型为数据，则第二块包括1比特的头字段和N个64比特的第一负载，头字段用于指示N个第一块均为数据块。从而有助于在N个第一块均为数据块的情况下，简化将N个第一块整合为一个第二块的实现方式。
在一种可能的设计中，N个64比特的第一负载是按照编码得到的先后顺序排列的。从而便于接收端设备解码。
在一种可能的设计中，若N个65比特的第一块中K个第一块为数据块，N-K个第一块为控制块，其中，数据块包括1比特的第一头字段和64比特的第一负载，第一头字段用于指示第一负载的类型为数据，控制块包括1比特的第二头字段、8比特的BTF和56比特的第二负载，第二头字段用于指示第二负载的类型为控制信息，则第二块包括1比特的头字段、L比特的BIF、8-L比特的BTF、K个64比特的第一负载、N-K-1个8比特的BTF、以及N-K个56比特的第二负载；
N-K-1个8比特的BTF和一个8-L比特的BTF分别用于指示N-K个56比特的第二负载中一个第二负载的控制类型，头字段用于指示N个第一块中存在控制块，2≤L≤4，K小于N，且K为正整数。从而有助于在N个第一块中有数据块和控制块的情况下，简化将N个第一块整合为一个第二块的实现方式。
在一种可能的设计中，8-L比特的BTF用于指示N-K个为控制块的第一块中最先编码得到的第一块的第二负载的控制类型。从而便于接收端设备解码。
在一种可能的设计中，若N个65比特的第一块均为控制块，其中，控制块包括1比特的第二头字段、8比特的BTF和56比特的第二负载，第二头字段用于指示第二负载的类型为控制信息，则第二块包括1比特的头字段、L比特的BIF、8-L比特的BTF、N-1个8比特的BTF、以及N个56比特的第二负载；
N-1个8比特的BTF和一个8-L比特的BTF分别用于指示N个56比特的第二负载中一个第二负载的控制类型，所述头字段用于指示N个第一块中存在控制块，2≤L≤4，K小于N，且K为正整数。从而有助于在N个第一块均为控制块的情况下，简化将N个第一块整合为一个第二块的实现方式。
在一种可能的设计中，8-L比特的BTF用于指示N个第一块中最先编码得到的第一块的第二负载的控制类型。从而便于接收端设备解码。
在一种可能的设计中，在链路同步阶段或自协商阶段，选择块整合功能。从而有助于提接收端便于解码，提高解码的可靠性。
第二方面，为本申请实施例提供的一种用于发送的装置，具体包括：第一编码模块、整合模块和第二编码模块；
其中，第一编码模块用于将待发送的信息每P比特编码为一个第一块；P为正整数；
整合模块用于将N个第一块整合为一个第二块；N为大于1的正整数；
第二编码模块用于对M个第二块进行RS-FEC编码，得到RS-FEC帧；M为大于1的正整数。
在一种可能的设计中，第一编码模块具体用于若待发送的信息不足P比特，对待发送的信息进行零填充，得到P比特信息；并对填充后得到的P比特信息进行编码，得到第一块。
在一种可能的设计中，第一编码模块用于基于64B/65B线路编码技术，将待发送的信息每64比特编码为一个65比特的第一块。
在一种可能的设计中，若N个第一块均为数据块，其中，数据块包括1比特的第一头字段和64比特的第一负载，第一头字段用于指示第一负载的类型为数据，则第二块包括1比特的头字段和N个64比特的第一负载，头字段用于指示N个第一块均为数据块。
在一种可能的设计中，N个64比特的第一负载是按照编码得到的先后顺序排列的。
在一种可能的设计中，若N个65比特的第一块中K个第一块为数据块，N-K个第一块为控制块，其中，数据块包括1比特的第一头字段和64比特的第一负载，第一头字段用于指示第一负载的类型为数据，控制块包括1比特的第二头字段、8比特的BTF和56比特的第二负载，第二头字段用于指示第二负载的类型为控制信息，则第二块包括1比特的头字段、L比特的BIF、8-L比特的BTF、K个64比特的第一负载、N-K-1个8比特的BTF、以及N-K个56比特的第二负载；
N-K-1个8比特的BTF和一个8-L比特的BTF分别用于指示N-K个56比特的第二负载中一个第二负载的控制类型，头字段用于指示N个第一块中存在控制块，2≤L≤4，K小于N，且K为正整数。
在一种可能的设计中，8-L比特的BTF用于指示N-K个为控制块的第一块中最先编码得到的第一块的第二负载的控制类型。
在一种可能设计中，若N个65比特的第一块均为控制块，其中，控制块包括1比特的第二头字段、8比特的块类型字段BTF和56比特的第二负载，第二头字段用于指示所述第二负载的类型为控制信息，则第二块包括1比特的头字段、L比特的块指示字段BIF、8-L比特的BTF、N-1个8比特的BTF、以及N个56比特的第二负载；
N-1个8比特的BTF和一个8-L比特的BTF分别用于指示N个56比特的第二负载中一个第二负载的控制类型，头字段用于指示N个第一块中存在控制块，2≤L≤4，K小于N，且K为正整数。
在一种可能的设计中，该装置还包括功能选择模块；
该功能选择模块，用于在链路同步阶段或自协商阶段，选择块整合功能。
第三方面，为本申请实施例提供的一种用于发送的设备，包括处理器和存储器，其中存储器存储有程序指令，处理器执行所述程序指令时，执行本申请实施例上述各个方面以及各个方面涉及的任一可能设计的方法。
第四方面，本申请实施例提供的一种用于发送的设备，包括执行本申请实施例上述各个方面以及各个方面涉及的任一可能设计的方法的装置。
第五方面，本申请实施例提供的一种芯片，包括：处理器和接口，用于从存储器中调用并运行所述存储器中存储的程序指令，执行本申请实施例上述各个方面以及各个方面涉及的任一可能设计的方法。
第六方面，本申请实施例的一种计算机存储介质，该计算机存储介质存储有程序指令，当所述程序指令在电子设备上运行时，使得电子设备执行本申请实施例上述各个方面以及各个方面涉及的任一可能设计的方法。
第七方面，本申请实施例的一种计算机程序产品，当所述计算机程序产品在电子设备上运行时，使得所述电子设备执行实现本申请实施例上述各个方面以及各个方面涉及的任一可能设计的方法。
另外，第二方面至第七方面中任一种可能设计方式所带来的技术效果可参见方法部分相关中不同设计方式所带来的技术效果，此处不再赘述。
附图说明
图1为本申请实施例的一种数据块的格式示意图；
图2为本申请实施例的一种控制块的格式示意图；
图3为本申请实施例的一种多线程编码方法的流程示意图；
图4为本申请实施例的一种编码原理的示意图；
图5A为本申请实施例的一种整合第二块的示意图；
图5B为本申请实施例的另一整合第二块的示意图；
图6A为本申请实施例的另一种整合第二块的示意图；
图6B为本申请实施例的另一种整合第二块的示意图；
图7A为本申请实施例的另一种整合第二块的示意图；
图7B为本申请实施例的另一种整合第二块的示意图；
图7C为本申请实施例的另一种整合第二块的示意图；
图8A为本申请实施例的另一种整合第二块的示意图；
图8B为本申请实施例的另一种整合第二块的示意图；
图9A为本申请实施例的另一种整合第二块的示意图；
图9B为本申请实施例的另一种整合第二块的示意图；
图10为本申请实施例的一种用于发送的装置的结构示意图；
图11为本申请实施例的另一用于发送的装置的结构示意图。
具体实施方式
应理解，本申请实施例中“至少一个”是指一个或者多个。“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系。例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的三种情况。其中A、B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一(项)个”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a、b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c，或a、b和c七种情况。其中a、b、c中的每一个本身可以是元素，也可以是包含一个或多个元素的集合。
在本申请中，“示例的”、“在一些实施例中”、“在另一些实施例中”等用于表示作例子、例证或说明。本申请中被描述为“示例”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用示例的一词旨在以具体方式呈现概念。
需要指出的是，本申请实施例中涉及的“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
IEEE802.3bw标准应用于传输速率为100M的场景，又可以称之为100BASE-T1标准，采用4B/5B线路编码技术。IEEE802.3bp标准应用于传输速率为1000M的场景，又可以称之为1000BASE-T1标准，采用80/81B线路编码技术。IEEE802.3ch标准应用于传输速率为2.5G、5G或10G的场景，采用64B/65B线路编码技术。目前，发送端设备通常支持IEEE802.3ch标准。即发送端设备基于64B/65B线路编码技术进行编码。然而，随着通信技术的进步，对传输速率的要求不断提高，对于传输速率更高的场景来说，例如传输速率为25G的场景，如果发送端设备继续采用64B/65B线路技术，容易导致线路编码开销较大， 进而对信道的带宽要求增加，波特率也会随之增加。
示例的，未来演进的车载以太网络支持传输速率为25G的场景，为了适应传输速率为25G的场景，可以采用128B/129B线路编码技术，与采用64B/65B线路编码技术相比，可以降低线路编码开销，但是通过在发送端设备中增加线路编码技术的方案，对于设备的改进较大，同时也增加了实现的负载性。
有鉴于此，本申请实施例提供了一种线路编码方法，使得发送端设备可以对基于64B/65B线路编码技术编码得到的多个块(block)进行整合，来适应更高传输速率的应用场景，不但有助于降低线路编码的开销，也有助于降低线路编码实现的复杂性。
首先，对本申请实施例涉及的部分名词进行解释，以便于本领域技术人员的理解。
1、数据块(data block)。具体的，数据块的块格式(block format)如图1所示包括第一头(header)字段和第一负载(payload)。其中，第一头字段包括T比特，用于指示第一负载的类型为数据。第一负载包括P比特。需要说明的是，第一头字段的比特数T、和第一负载的比特数P与线路编码技术相关。T和P均为正整数。不同的线路编码技术，第一头字段的比特数可以相同，也可以不同。此外，不同的线路编码技术，第一负载的比特数可以相同，也可以不同。
例如，在数据块是基于64B/65B线路编码技术得到的情况下，即数据块是对64比特的字符进行编码后得到的时，数据块为65比特，第一头字段为1比特，第一负载为64比特。比如，第一头字段为0，用于指示第一负载的类型为数据。又例如，在数据块是基于64B/66B线路编码技术得到的情况下，即数据块是对64比特的字符进行编码后得到的时，数据块为66比特，第一头字段为2比特，第一负载为64比特。
2、控制块(control block)。具体的，控制块的块格式可以如图2所示，包括第二头字段、块类型字段(block type field，BTF)和第二负载。其中，第二头字段为T比特，用于指示第二负载的类型为控制信息。BTF为R比特，用于指示第二负载的控制类型。需要说明的是，控制块的块格式还可以包括其它字段，对此不作限定。
此外，还需要说明的是，与数据块类似，第二头字段的比特数、BTF的比特数和第二负载的比特数与线路编码技术相关。不同的线路编码技术，第二头字段的比特数的可以相同，也可以不同。不同的线路编码技术，BTF的比特数的可以相同，也可以不同。另外，不同的线路编码技术，第二负载的比特数的可以相同，也可以不同。
以64B/65B线路编码技术为例。在控制块是基于64B/65B线路编码技术进行编码后得到的情况下，控制块为65比特。第二头字段为1比特，BTF为8比特，第二负载为56比特。具体的，在IEEE802.3ch标准中，第二负载的控制类型通常包括15种，不同的BTF用于指示不同控制类型的第二负载。如表1所示。
表1
控制类型 BTF
1 0x1E
2 0x2D
3 0x33
4 0x66
5 0x55
6 0x78
7 0x4B
8 0x87
9 0x99
10 0xAA
11 0xB4
12 0xCC
13 0xD2
14 0xE1
15 0xFF
例如，如表1所示，BTF为0x1E，用于指示第二负载的控制类型为控制类型1。
以下结合附图对本申请实施例的线路编码方法进行详细介绍。
示例的，如图3所示，为本申请实施例的一种线路编码方法，应用于发送端设备，具体包括以下步骤。
步骤301，将待发送的信息每P比特编码为一个第一块。其中，P为正整数。具体的，P的取值与发送端设备所采用的线路编码技术有关。例如，发送端设备采用64B/65B线路编码技术时，P的取值为64。再例如，发送端设备采用80B/81B线路编码技术时，P的取值为80。
在一些实施例中，发送端设备的媒体接入控制(media access control，MAC)层通过XGMII接口将待发送的信息发送给物理层，物理层将待发送的信息每P比特编码为一个第一块。具体的，物理层在P比特的待发送的信息前添加T比特的头字段，得到一个第一块。其中，T的取值与发送端设备所采用的线路编码技术有关。例如，发送端设备采用64B/65B线路编码技术时，T的取值为1。再例如，发送端设备采用64B/66B线路编码技术时，T的取值为2。
以64B/65B线路编码技术为例。物理层基于64B/65B线路编码技术，将待发送的信息的每64比特编码为一个65比特的第一块。具体的，物理层在64比特的待发送的信息前添加1比特的头字段，得到一个65比特的第一块。
其中，在待发送的信息前添加的头字段与待发送的信息中是否包含控制信息有关。比如，当64比特的待发送的信息中包含控制信息时，在该64比特的待发送的信息前添加第二头字段。再比如，当64比特的待发送的信息中不包含控制信息时，在该64比特的待发送的信息前添加第一头字段。
在另一些实施例中，当待发送的信息不满足P比特时，对待发送的信息进行零填充，得到P比特信息；对填充后得到的所述P比特信息进行编码，得到第一块。例如，发送端设备编码得到多个第一块后，待发送的信息的剩余部分不满足P比特时，在该待发送的信息的剩余部分之后添加0，直至添加0后的待发送的信息的剩余部分达到P比特为止，然后为添加0之后的待发送的信息的剩余部分进行编码，得到第一块。需要说明的是，对待发送的信息进行零填充可以是由MAC层执行的，也可以是由物理层执行的，对此不作限定。
以64B/65B线路编码技术为例。例如，待发送的信息为60比特，则在60比特的待发送的信息后添加4个0，得到64比特的信息，然后，在添加4个0后得到的64比特的信息的前添加1比特的头字段，得到第一块。
步骤302，将该N个第一块整合为一个第二块。其中，N＞1，且N为正整数。
示例的，发送端设备每得到N个第一块，则将N个第一块整合为一个第二块。
其中，发送端设备可以对待发送的信息进行并行编码。例如，发送端设备针对待发送的信息可以每次编码得到多个第一块。当发送端设备每次编码得到N个第一块时，发送端设备可以将该次得到的N个第一块整合为一个第二块。此外，在发送端设备针对待发送的信息可以每次编码得到多个第一块的情况下，如果发送端设备每次编码得到超过N个第一块，发送端设备还可以每次对N个第一块整合得到一个第二块，也可以每次并行整合第一块得到多个第二块。例如，发送端设备针对待发送的信息可以每次编码得到2N个第一块时，可以每次并行对第一块整合得到两个第二块。
发送端设备针对待发送的信息也可以每次编码得到一个第一块。当发送端设备得到N个第一块后，将N个第一块整合得到一个第二块。
步骤303，对M个第二块进行理德所罗门前向纠错编码(Reed-Solomon error forward correction coding，RS-REC)编码，得到RS-REC帧，M＞1，且M为正整数。
其中，发送端设备可以根据M个第二块、R个X比特的操作管理维护(operation adminstration maintenance，OAM)符号进行RS-REC编码，得到RS-REC编码。其中，OAM符号可以包括用于指示设备通信质量的信息。例如，OAM符号用于指示信噪比(signal noise ratio，SNR)的高低。或者，OAM符号还可以用于指示附加信息，例如用户自定义的信息。在R的取值大于1的情况下，不同的OAM符号指示的信息可以是不同的。例如，以R取值为2为例。一个OAM符号用于指示设备通信质量的信息，另一个OAM符号用于指示附加信息。或者，一个OAM符号用于指示设备通信质量的信息和部分附加信息，另一个OAM符号用于指示另一部分附加信息。
示例的，物理层当得到M个第二块后，将M个第二块、R个X比特的操作管理维护(operation adminstration maintenance，OAM)符号，作为RS-REC编码器的输入，由RS-REC编码器进行编码，得到RS-FEC帧。
进一步的，在一些实施例中，在M个第二块、R个X个比特的OAM的总比特数不满足RS-REC编码器输入的比特数时，发送端设备还可以根据M个第二块、R个X比特的OAM符号和填充比特(padding)，进行RS-REC编码，得到RS-REC帧。其中，填充比特(padding)可以为至少一个0。
需要说明的是，M、R、X和padding的取值可以根据实际需要进行设置。以64B/65B线路编码技术为例。例如，N的取值为2，M的取值可以设置为25，R的取值可以设置为2，X取值可以为10。具体的，M、R、X以及padding的比特数的取值可以是通过协议预定义的，也可以是通过发送端设备根据某一算法或规则确定的，对M、R、X、padding的比特数取值的确定方式不作限定，只要M、R、X以及padding的比特数的取值使得M个第二块、R个X个比特的OAM以及padding的比特数之和满足RS-REC编码器的输入比特数即可。
示例的，将M个第二块、R个X比特的OAM符号和填充比特(padding)作为RS-REC编码器的输入。然后，由RS-REC编码器进行编码，得到RS-FEC帧。
以64B/65B线路编码技术为例。在N的取值为2，M的取值为25的情况下，第二块的比特数为129。示例的，如图4所示，将两个65比特第一块整合一个129比特的第二块，在得到25个第二块后，将25个第二块、2个10比特的OAM符号、以及padding作为RS-REC编码器的输入，进行RS-FEC编码，形成一个3600比特的RS-FEC帧。例如，在RS-FEC帧 中，25个第二块是按照编码得到的先后顺序排列的，2个10比特的OAM符号位于25个第二块之后，padding位于OAM符号之后。
在一些实施例中，发送端设备可以在与接收端设备之间进行链路同步或自动协商的过程中，交互各自所支持的能力。发送端设备当与接收端设备均支持块整合能力时，可以选择块整合能力，执行本申请实施例的线路编码方法。以提高传输的成功率。其中，块整合能力用于指示设备能够执行如图3所示的线路编码方法。
示例的，发送端设备可以通过链路编码字(link code word，LCW)中一个或多个预留比特位与接收端设备交互各自所支持的能力。示例的，LCW包括27个比特，分别为A0至A26，其中，A0、A2-A5已被占用，A1、A6-A26为预留比特位。其中，A0、A2-A5比特所指示的能力可以如表2所示。
表2
比特 描述
A0 100BASE-T1 ability
A1 预留位(Reserved)
A2 100BASE-T1 ability
A3 2.5GBASE-T1 ability
A4 5GBASE-T1 ability
A5 10GBASE-T1 ability
A6～A26 预留位(Reserved)
例如，通过Link Codeword中的A6发送端设备与接收端设备交互各自所支持的块整合能力。比如，对于发送端设备来说，Link Codeword中的A6指示发送端设备支持25GBASE-T1能力，则发送端设备支持块整合能力。对于接收端设备来说，Link Codeword中的A6指示接收端设备支持25GBASE-T1能力，则接收端设备支持块整合能力。进一步的，发送端设备可以在当与接收端设备均支持块整合能力时，检测到当前网络支持的传输速率不小于某一阈值(比如，25G)时，选择开启块整合能力。
以基于64B/65B线路编码技术为例，对将N个第一块整合为一个第二块进行具体介绍。其中，在基于64B/65B线路编码的情况下，第一块的比特数为65比特。
示例一：N个65比特的第一块均为数据块。
将1比特的头字段和N个第一块的第一负载整合为第一个第二块，则第二块包括1比特的头字段和N个64比特的第一负载。在这种情况下，1比特的头字段用于指示N个第一块均为数据块。进一步的，N个第一块的第一负载在第二块中是按照编码得到的先后顺序排列的。以便于接收端设备读取。
例如，N的取值为2，N个65比特的第一块为数据块1和数据块2，如图5A所示，数据块1包括第一头字段1和第一负载1，数据块2包括第一头字段2和第一负载2，其中，发送端设备基于64B/65B线路编码技术先得到数据块1，再得到数据块2。则对数据块1和数据块2整合得到的第二块包括1比特的头字段、第一负载1和第一负载2，头字段位于第一负载1之前，第一负载1位于第一负载2之前。
再例如，N的取值为4，N个65比特的第一块为数据块1、数据块2、数据块3和数据块4，如图5B所示，数据块1包括第一头字段1和第一负载1，数据块2包括第一头字 段2和第一负载2，数据块3包括第一头字段3和第一负载3，数据块4包括第一头字段4和第一负载4，其中，发送端设备基于64B/65B线路编码技术依次得到数据块1、数据块2、数据块3和数据块4。则对数据块1、数据块2、数据块3和数据块4整合得到的第二块包括1比特的头字段、第一负载1、第一负载2、第一负载3和第一负载4，头字段位于第一负载1之前，第一负载1位于第一负载2之前，第一负载2位于第一负载3之前，第一负载3位于第一负载4之前。
需要说明的是，本申请实施例中，第二块中N个第一块的第一负载还可以是按照其他顺序排列的，对此不做限定。例如，按照MAC层传输到物理层的顺序排列的。
示例二：N个65比特的第一块中K个第一块为数据块，N-K个第一块为控制块。
将1比特的头字段、K个第一块的第一负载、L比特的BIF、8-L比特的BTF、N-K-1个8比特的BTF和N-K个第一块的第二负载整合为第一个第二块，则第二块包括1比特的头字段、L比特的块指示字段BIF、8-L比特的BTF、K个64比特的第一负载、N-K-1个8比特的BTF、以及N-K个第一块的第二负载。在这种情况下，1比特的头字段用于指示N个第一块中存在控制块。在采用64B/65B线路编码技术的情况下，由于64B/65B线路编码技术中控制类型包括15种，是通过8比特的信息指示的，因此一个BTF存在4比特的冗余，因此，BTF的比特数最小可以为4。
例如，N的取值为2，L取值可以为2、3或4，以L的取值为2为例。N个65比特的第一块为数据块1和控制块1，如图6A所示，数据块1包括第一头字段1和第一负载1，控制块1包括第二头字段1、8比特的BTF和第二负载1，将第一负载1、8比特的BTF和第二负载1整合为一个第二负载，第二负载包括1比特的头字段、4比特的BIF、第一负载1、4比特的BTF和第二负载1。其中，4比特的BIF用于指示第一负载1和第二负载1的位置关系。4比特的BTF的用于指示第二负载1的控制类型，是根据控制块1中的8比特的BTF得到的。需要说明的是，当N的取值为2时，L取值为4，4比特的BIF中存在两个冗余的比特，该两个冗余的比特可以预先定义好，例如定义BIF中第3、4个比特为冗余比特，BIF中第1、2比特分别为0、1时指示第一负载1在第二负载1之前，BIF中第1、2比特分别为1、0时指示第二负载1在第一负载之前。示例的，当基于64B/65B线路编码技术，数据块1先于控制块1编码得到时，第二块可以如图6A所示。进一步的，当基于64B/65B线路编码技术，控制块1先于数据块1编码得到时，第二块可以如图6B所示。
例如，N的取值为4，L取值可以为4。N个65比特的第一块为数据块1、数据块2、数据块3和控制块1，如图7A所示，数据块1包括第一头字段1和第一负载1，数据块2包括第一头字段2和第一负载2，数据块3包括第一头字段3和第一负载3，控制块1包括第二头字段1、8比特的BTF和第二负载1，将第一负载1、第一负载2、第一负载3、8比特的BTF和第二负载1整合为一个第二负载，第二负载包括1比特的头字段、4比特的BIF、第一负载1、第一负载2、第一负载3、4比特的BTF和第二负载1。其中，4比特的BIF用于指示第一负载1、第一负载2、第一负载3和第二负载1的位置关系。
比如，当基于64B/65B线路编码技术，依次得到数据块1、数据块2、数据块3和控制块1时，BIF可以为0001，第二块可以如图7A所示，1比特的头字段位于4比特的BIF之前，BIF位于第一负载1之前，第一负载1位于第一负载2之前，第一负载2位于第一负载3之前，第一负载3位于4比特的BTF之前，4比特的BTF位于第二负载1之前。
再比如，当基于64B/65B线路编码技术，依次得到数据块1、数据块2、控制块1和数据块3时，BIF可以为0010，第二块可以如图7B所示，1比特的头字段位于4比特的BIF之前，4比特的BIF位于第一负载1之前，第一负载1位于第一负载2之前，第一负载2位于4比特的BTF之前，4比特的BTF位于第二负载1之前，第二负载1位于第一负载3之前。
再比如，当基于64B/65B线路编码技术，依次得到控制块1、数据块1、数据块2和数据块3时，BIF可以为1000，第二块可以如图7C所示，1比特的头字段位于4比特的BIF之前，4比特的BIF位于第一负载1之前，第一负载1位于第一负载2之前，第一负载2位于4比特的BTF之前，4比特的BTF位于第二负载1之前，第二负载1位于第一负载3之前。
例如，N的取值为4，L取值可以为4。N个65比特的第一块为数据块1、数据块2、控制块1和控制块2，如图8A所示，数据块1包括第一头字段1和第一负载1，数据块2包括第一头字段2和第一负载2，控制块1包括第二头字段1、8比特的BTF1和第二负载1，控制块2包括第二头字段2、8比特的BTF2和第二负载1，将第一负载1、第一负载2、8比特的BTF1、第二负载1、8比特的BTF2和第二负载2整合为一个第二负载，第二负载包括1比特的头字段、4比特的BIF、第一负载1、第一负载2、4比特的BTF、第二负载1、8比特的BTF2和第二负载2。其中，4比特的BIF用于指示第一负载1、第一负载2、第二负载1和第二负载2的位置关系。
其中，控制块1可以是先于控制块2编码得到的，也可以是控制块2先于控制块1编码得到的。
比如，当基于64B/65B线路编码技术，依次得到控制块1、数据块1、数据块2和控制块2时，BIF可以为1001，第二块可以如图8A所示，1比特的头字段位于4比特的BIF之前，BIF位于4比特的BTF之前，4比特的BTF位于第二负载1之前，第二负载1位于第一负载1之前，第一负载1位于第一负载2之前，第一负载2位于8比特的BTF2之前，8比特的BTF2位于第二负载2之前。
再比如，当基于64B/65B线路编码技术，依次得到控制块1、数据块1、数据块2和控制块2时，BIF可以为1001，第二块可以如图8B示，1比特的头字段位于4比特的BIF之前，BIF位于8比特的BTF1之前，8比特的BTF1位于第二负载1之前，第二负载1位于第一负载1之前，第一负载1位于第一负载2之前，第一负载2位于4比特的BTF之前，4比特的BTF位于第二负载2之前。
在另一些实施例中，将1比特的头字段、K个第一块的第一负载、L比特的BIF、N-K个
Figure PCTCN2020108299-appb-000001
比特的BTF和N-K个第一块的第二负载整合为第一个第二块，则第二块包括1比特的头字段、L比特的块指示字段BIF、K个64比特的第一负载、N-K个
Figure PCTCN2020108299-appb-000002
比特的BTF、以及N-K个第一块的第二负载。在这种情况下，1比特的头字段用于指示N个第一块中存在控制块。其中，N-K个
Figure PCTCN2020108299-appb-000003
比特的BTF分别用于指示一个第二负载的控制类型。N-K≤L≤4*(N-K)。
示例三：N个65比特的第一块均为控制块。
将1比特的头字段、N个第一块的第二负载、L比特的BIF、8-L比特的BTF、和N-1个8比特的BTF整合为第一个第二块，则第二块包括1比特的头字段、L比特的BIF、8-L比特的BTF和N个第一块的第一负载。在这种情况下，1比特的头字段用于指示N个第一块中存 在控制块。2≤L≤4。其中，8-L比特的BTF用于指示N个第一块中最先编码得到的第一块的第二负载的控制类型，也可以用于指示N个第一块中其中一个第一块的第二负载的控制类型，对此不作限定。
例如，N的取值为2，L取值可以为2、3或4，以L的取值为2为例。N个65比特的第一块为控制块1和控制块2，如图9A所示，控制块1包括第二头字段1、8比特的BTF1和第二负载1，控制块2包括第二头字段2、8比特的BTF2和第二负载2，将8比特的BTF1、第二负载1、BTF2和第二负载2整合为一个第二负载，第二负载包括1比特的头字段、4比特的BIF、4比特的BTF、第二负载1、BTF2和第二负载2。其中，4比特的BIF用于指示第二负载1和第二负载2的位置关系。4比特的BTF的用于指示第二负载1的控制类型，是根据控制块1中的8比特的BTF1得到的。需要说明的是，当N的取值为2时，L取值为4，4比特的BIF中存在两个冗余的比特，该两个冗余的比特可以预先定义好，例如定义BIF中第3、4个比特为冗余比特，BIF中第1、2比特分别为0、1时指示第一负载1在第二负载1之前，BIF中第1、2比特分别为1、0时指示第二负载1在第一负载之前。示例的，当基于64B/65B线路编码技术，控制块1先于控制块1编码得到时，第二块可以如图9A所示。此外，当基于64B/65B线路编码技术，控制块1先于控制块2编码得到时，第二块也可以如图9B所示。
当N取值为4时，L的取值为4，具体的将4个65比特第一块整合为一个第二块的方式，与将2个65比特的第一块整合为一个第二块的方式类似，在此不再赘述。
此外，在另一些实施例中，将1比特的头字段、L比特的BIF、N个
Figure PCTCN2020108299-appb-000004
比特的BTF和N个第一块的第二负载整合为第一个第二块，则第二块包括1比特的头字段、L比特的块指示字段BIF、N个
Figure PCTCN2020108299-appb-000005
比特的BTF、以及N个第一块的第二负载。在这种情况下，1比特的头字段用于指示N个第一块中存在控制块。其中，N个
Figure PCTCN2020108299-appb-000006
比特的BTF分别用于指示一个第二负载的控制类型。N-K≤L≤4*(N-K)。
需要说明的是，当发送端设备采用图3所示的线路编码方法进行编码后，还可以进行脉冲幅度调制(pulse amplitude modulation，PAM)，然后向接收端设备发送PAM调制后的信息。
接收端设备接收到来自发送端设备的信息后，对来自发送端设备的信息进行解调，得到RS-FEC帧。接收端设备在块整合功能已开启的情况下，将RS-FEC帧分解为M个第二块，并将每个第二块分解为N个65比特的第一块，然后对每个65比特的第一块进行处理。
另外，还需要说明的是，本申请实施例中的线路编码方法还可以应用于除64B/65B线路编码技术以外的其它线路编码技术，例如64B/66B线路编码技术，上述仅为举例说明，并不构成对本申请实施例限定。
以上各实施例可以单独使用，也可以相互结合使用，以实现不同的技术效果。
上述本申请提供的实施例中，从终端设备作为执行主体的角度对本申请实施例提供的通信方法进行了介绍。为了实现上述本申请实施例提供的通信方法中的各功能，终端设备可以包括硬件结构和/或软件模块，以硬件结构、软件模块、或硬件结构加软件模块的形式来实现上述各功能。上述各功能中的某个功能以硬件结构、软件模块、还是硬件结构加软件模块的方式来执行，取决于技术方案的特定应用和设计约束条件。
与上述构思相同，如图10所示，本申请实施例还提供一种用于发送的装置，该装置包括第一编码模块1001、整合模块1002、和第二编码模块1003。
其中，第一编码模块1001用于将待发送的信息每P比特编码为一个第一块；P为正整数；
整合模块1002用于将N个第一块整合为一个第二块；N为大于1的正整数；
第二编码模块1003用于对M个第二块进行RS-FEC编码，得到RS-FEC帧；M为大于1的正整数。
进一步的，在一些实施例中，该装置还包括功能选择模块1004。其中，功能选择模块1004用于在链路同步阶段或自协商阶段，选择块整合功能。
示例的，如图11所示，为本申请实施例的另一装置，该装置包括处理器1101和存储器1102。
该装置可以是用于发送的设备，也可以是用于发送的设备中的装置。其中，该装置可以为芯片系统。本申请实施例中，芯片系统可以由芯片构成，也可以包含芯片和其他分立器件。
其中，处理器1101调用存储器1102中存储的程序指令，执行图3所示的多线路编码方法。
本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，另外，在本申请各个实施例中的各功能模块可以集成在一个处理器中，也可以是单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
关于图10和图11所示的装置的具体执行过程，可参见上方法实施例中的记载，在此不再赘述。
在本申请实施例中，处理器可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
在本申请实施例中，存储器可以是非易失性存储器，比如硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)等，还可以是易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)。存储器是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。本申请实施例中的存储器还可以是电路或者其它任意能够实现存储功能的装置，用于存储程序指令和/或数据。
本申请实施例提供的方法中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、网络设备、用户设备或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通 过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，简称DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机可以存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，数字视频光盘(digital video disc，简称DVD))、或者半导体介质(例如,SSD)等。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (20)

  1. 一种线路编码方法，其特征在于，应用于发送端设备，所述方法包括：
    将待发送的信息每P比特编码为一个第一块；所述P为正整数；
    将N个第一块整合为一个第二块；所述N为大于1的正整数；
    对所述M个第二块进行RS-FEC编码，得到RS-FEC帧；所述M为大于1的正整数。
  2. 如权利要求1所述的方法，其特征在于，所述将待发送的信息每P比特编码为一个第一块，包括：
    若所述待发送的信息不足P比特时，对所述待发送的信息进行零填充，得到P比特信息；
    对填充后得到的所述P比特信息进行编码，得到第一块。
  3. 如权利要求1或2所述的方法，其特征在于，所述将待发送的信息每P比特编码为一个第一块，包括：
    基于64B/65B线路编码技术，将所述待发送的信息每64比特编码为一个65比特的第一块。
  4. 如权利要求3所述的方法，其特征在于，若所述N个第一块均为数据块，其中，所述数据块包括1比特的第一头字段和64比特的第一负载，所述第一头字段用于指示所述第一负载的类型为数据，则所述第二块包括1比特的头字段和N个64比特的第一负载，所述头字段用于指示N个第一块均为数据块。
  5. 如权利要求4所述的方法，其特征在于，所述N个64比特的第一负载是按照编码得到的先后顺序排列的。
  6. 如权利要求3所述的方法，其特征在于，若所述N个65比特的第一块中K个第一块为数据块，N-K个第一块为控制块，其中，所述数据块包括1比特的第一头字段和64比特的第一负载，所述第一头字段用于指示所述第一负载的类型为数据，所述控制块包括1比特的第二头字段、8比特的块类型字段BTF和56比特的第二负载，所述第二头字段用于指示所述第二负载的类型为控制信息，则所述第二块包括1比特的头字段、L比特的块指示字段BIF、8-L比特的BTF、K个64比特的第一负载、N-K-1个8比特的BTF、以及N-K个56比特的第二负载；
    所述N-K-1个8比特的BTF和一个8-L比特的BTF分别用于指示N-K个56比特的第二负载中一个第二负载的控制类型，所述头字段用于指示N个第一块中存在控制块，2≤L≤4，K小于N，且K为正整数。
  7. 如权利要求6所述的方法，其特征在于，8-L比特的BTF用于指示N-K个56比特的第二负载中一个第二负载的控制类型，包括：
    8-L比特的BTF用于指示N-K个为控制块的第一块中最先编码得到的第一块的第二负载的控制类型。
  8. 如权利要求3所述的方法，其特征在于，若所述N个65比特的第一块均为控制块，其中，所述控制块包括1比特的第二头字段、8比特的块类型字段BTF和56比特的第二负载，所述第二头字段用于指示所述第二负载的类型为控制信息，则所述第二块包括1比特的头字段、L比特的块指示字段BIF、8-L比特的BTF、N-1个8比特的BTF、以及N个56比特的第二负载；
    所述N-1个8比特的BTF和一个8-L比特的BTF分别用于指示N个56比特的第二负载中 一个第二负载的控制类型，所述头字段用于指示N个第一块中存在控制块，2≤L≤4，K小于N，且K为正整数。
  9. 如权利要求1至8任一所述的方法，其特征在于，所述方法还包括：
    在链路同步阶段或自协商阶段，选择块整合功能。
  10. 一种用于发送的装置，其特征在于，所述装置包括：第一编码模块、整合模块和第二编码模块；
    所述第一编码模块，用于将待发送的信息每P比特编码为一个第一块；所述P为正整数；
    所述整合模块，用于将N个第一块整合为一个第二块；所述N为大于1的正整数；
    所述第二编码模块，用于对所述M个第二块进行RS-FEC编码，得到RS-FEC帧；所述M为大于1的正整数。
  11. 如权利要求10所述的装置，其特征在于，所述第一编码模块，用于将待发送的信息每P比特编码为一个第一块，具体包括：
    所述第一编码模块，用于若所述待发送的信息不足P比特，对所述待发送的信息进行零填充，得到P比特信息；并对填充后得到的所述P比特信息进行编码，得到第一块。
  12. 如权利要求10或11所述的装置，其特征在于，所述第一编码模块，用于将待发送的信息每P比特编码为一个第一块，具体包括：
    所述第一编码模块，用于基于64B/65B线路编码技术，将所述待发送的信息每64比特编码为一个65比特的第一块。
  13. 如权利要求12所述的装置，其特征在于，若所述N个第一块均为数据块，其中，所述数据块包括1比特的第一头字段和64比特的第一负载，所述第一头字段用于指示所述第一负载的类型为数据，则所述第二块包括1比特的头字段和N个64比特的第一负载，所述头字段用于指示N个第一块均为数据块。
  14. 如权利要求13所述的装置，其特征在于，所述N个64比特的第一负载是按照编码得到的先后顺序排列的。
  15. 如权利要求12所述的装置，其特征在于，若所述N个65比特的第一块中K个第一块为数据块，N-K个第一块为控制块，其中，所述数据块包括1比特的第一头字段和64比特的第一负载，所述第一头字段用于指示所述第一负载的类型为数据，所述控制块包括1比特的第二头字段、8比特的块类型字段BTF和56比特的第二负载，所述第二头字段用于指示所述第二负载的类型为控制信息，则所述第二块包括1比特的头字段、L比特的块指示字段BIF、8-L比特的BTF、K个64比特的第一负载、N-K-1个8比特的BTF、以及N-K个56比特的第二负载；
    所述N-K-1个8比特的BTF和一个8-L比特的BTF分别用于指示N-K个56比特的第二负载中一个第二负载的控制类型，所述头字段用于指示N个第一块中存在控制块，2≤L≤4，K小于N，且K为正整数。
  16. 如权利要求15所述的装置，其特征在于，8-L比特的BTF用于指示N-K个56比特的第二负载中一个第二负载的控制类型，包括：
    8-L比特的BTF用于指示N-K个为控制块的第一块中最先编码得到的第一块的第二负载的控制类型。
  17. 如权利要求12所述的装置，其特征在于，若所述N个65比特的第一块均为控制块，其中，所述控制块包括1比特的第二头字段、8比特的块类型字段BTF和56比特的第 二负载，所述第二头字段用于指示所述第二负载的类型为控制信息，则所述第二块包括1比特的头字段、L比特的块指示字段BIF、8-L比特的BTF、N-1个8比特的BTF、以及N个56比特的第二负载；
    所述N-1个8比特的BTF和一个8-L比特的BTF分别用于指示N个56比特的第二负载中一个第二负载的控制类型，所述头字段用于指示N个第一块中存在控制块，2≤L≤4，K小于N，且K为正整数。
  18. 如权利要求10至17任一所述的装置，其特征在于，所述装置还包括功能选择模块；
    所述功能选择模块，用于在链路同步阶段或自协商阶段，选择块整合功能。
  19. 一种用于发送的装置，其特征在于，包括处理器和存储器，所述存储器中存储有程序指令，所述处理器执行所述程序指令时，使得所述装置执行权利要求1至9任一所述的方法。
  20. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有程序指令，当所述程序指令在计算机上运行时，使得计算机执行如权利要求1至9任一所述的方法。
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