WO2024098564A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2024098564A1
WO2024098564A1 PCT/CN2023/075207 CN2023075207W WO2024098564A1 WO 2024098564 A1 WO2024098564 A1 WO 2024098564A1 CN 2023075207 W CN2023075207 W CN 2023075207W WO 2024098564 A1 WO2024098564 A1 WO 2024098564A1
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WO
WIPO (PCT)
Prior art keywords
sub
transistor
line
active pattern
variable signal
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Application number
PCT/CN2023/075207
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English (en)
French (fr)
Inventor
刘大超
曾勉
孙亮
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2024098564A1 publication Critical patent/WO2024098564A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel.
  • LTPO Low Temperature Polycrystalline Oxide
  • LTPS Low Temperature Poly-silicon
  • the embodiment of the present application provides a display panel, which can realize a solution to improve the flicker problem of low-frequency driving of the display panel.
  • the embodiment of the present application provides a display panel, comprising an active layer, a first scan line and a variable signal line.
  • the active layer comprises a first channel portion and a second channel portion arranged opposite to each other, and a first electrical connection portion connected between the first channel portion and the second channel portion;
  • the first scan line extends along a first direction and overlaps with the first channel portion and the second channel portion;
  • the variable signal line comprises a routing portion and an overlapping portion connected to each other, the overlapping portion is located on a side of the routing portion close to the first electrical connection portion, and the overlapping portion at least partially overlaps with the first electrical connection portion.
  • the display panel further includes a plurality of sub-pixels, each sub-pixel includes a light-emitting device and a pixel driving circuit
  • the pixel driving circuit includes: a driving transistor, connected in series with the light-emitting device between a first power line and a second power line; and a compensation transistor, including a first sub-transistor and a second sub-transistor connected in series, one of the source and the drain of the first sub-transistor is electrically connected to the gate of the driving transistor, the other of the source and the drain of the first sub-transistor is electrically connected to one of the source and the drain of the second sub-transistor, the other of the source and the drain of the second sub-transistor is electrically connected to one of the source and the drain of the driving transistor, and the gate of the first sub-transistor and the gate of the second sub-transistor are both electrically connected to the first scan line.
  • the active layer further includes a first sub-active pattern of the first sub-transistor and a second sub-active pattern of the second sub-transistor, the first sub-active pattern includes a first channel portion, and the second sub-active pattern includes a second channel portion.
  • the display panel includes a plurality of variable signal lines, and a plurality of sub-pixels located in the same row are electrically connected to the same variable signal line.
  • the display panel further includes a first gate drive circuit electrically connected to the plurality of variable signal lines and configured to output variable signals to the plurality of variable signal lines.
  • the variable signal has at least one level jump.
  • the display panel further comprises a plurality of cascaded first gating drive circuits, each of which is electrically connected to the two variable signal lines and configured to output a variable signal to the two variable signal lines.
  • each variable signal has at least one level jump, and the level jumps of the plurality of variable signals are at different times.
  • the pixel driving circuit further includes a reset transistor
  • the reset transistor includes a third sub-transistor and a fourth sub-transistor connected in series, one of the source and the drain of the third sub-transistor is electrically connected to the first reset line, one of the source and the drain of the fourth sub-transistor is electrically connected to the other of the source and the drain of the second sub-transistor, the other of the source and the drain of the fourth sub-transistor is electrically connected to the other of the source and the drain of the third sub-transistor, and the gate of the third sub-transistor and the gate of the fourth sub-transistor are both electrically connected to the second scan line.
  • the variable signal line is located between the first scan line and the second scan line, and the variable signal line is in a different layer from the first scan line and the second scan line.
  • the active layer further includes a third sub-active pattern of the third sub-transistor, a fourth sub-active pattern of the fourth sub-transistor, and a second electrical connection portion connected between the third sub-active pattern and the fourth sub-active pattern;
  • the third sub-active pattern includes a third channel portion, and the fourth sub-active pattern includes a fourth channel portion.
  • the second scan line overlaps with the third channel portion and the fourth channel portion, and the first reset line overlaps with the second electrical connection portion;
  • the third sub-active pattern and the fourth sub-active pattern are both located between the variable signal line and the first reset line, and the third sub-active pattern and the fourth sub-active pattern are both spaced apart from the variable signal line.
  • the second sub-active pattern and the fourth sub-active pattern are electrically connected via a bridge portion that is in a different layer from the variable signal line and the first scan line.
  • variable signal line and the first reset line are in the same layer and made of the same material.
  • the ion doping concentration of the first electrical connection portion is greater than the ion doping concentration of the first channel portion and the second channel portion.
  • the display panel also includes: a first conductive layer, located on the active layer, including a variable signal line; a second conductive layer, located between the first conductive layer and the active layer, including a first scanning line and a second scanning line; and a third conductive layer, located on the first conductive layer, including a bridging portion.
  • the pixel driving circuit also includes a data transistor, a source and a drain of the data transistor are electrically connected between the other of the source and the drain of the driving transistor and the data line, and a gate of the data transistor is electrically connected to a third scan line; the data transistor is used to transmit a data signal to the gate of the driving transistor so that the gate of the driving transistor has a first potential.
  • the variable signal transmitted by the variable signal line has at least one jump from the second potential to the third potential, wherein the first potential is between the second potential and the third potential.
  • the overlapping portion at least partially overlaps with the first electrical connection portion to form a coupling capacitor, wherein the capacitance value of the coupling capacitor is greater than 0 femtofarad and less than or equal to 10 femtofarad.
  • the display panel further includes a fourth conductive layer, which is located on the first conductive layer and includes data lines.
  • the present application provides a display panel, including an active layer, a first scan line and a variable signal line.
  • the first scan line extends along a first direction, and the first scan line overlaps with a first channel portion and a second channel portion that are arranged opposite to each other in the active layer.
  • the variable signal line includes a routing portion and an overlapping portion that are connected to each other, the overlapping portion is located on a side of the routing portion close to the first electrical connection portion, and the overlapping portion at least partially overlaps with a first electrical connection portion in the active layer that is connected between the first channel portion and the second channel portion to form a coupling capacitor, so that when the display panel adopts low-frequency driving, a solution to improve the low-frequency flicker problem is realized by using a variable signal transmitted by the variable signal line and a coupling capacitor.
  • FIG1A is a schematic diagram of a structure in which a variable signal line overlaps an active layer
  • FIG1B is a cross-sectional view taken along the line p-p' in FIG1A
  • FIG1C is a cross-sectional view taken along the line z-z' in FIG1A
  • 2A and 2B are schematic diagrams showing connections between a first gate driving circuit and a sub-pixel provided in an embodiment of the present application
  • FIG3 is a schematic diagram of the structure of a sub-pixel provided in an embodiment of the present application
  • FIG4 is a timing diagram provided in an embodiment of the present application
  • FIG5 is a schematic diagram of display brightness change provided by an embodiment of the present application
  • FIG6 is a schematic diagram of a film layer structure of a sub-pixel provided in an embodiment of the present application
  • FIG7 is a schematic diagram of the structure of an active layer provided in an embodiment of the present application
  • FIG8 is a schematic structural diagram of a first conductive layer provided in an embodiment of the present application
  • Fig. 1A is a schematic diagram of a structure in which a variable signal line overlaps an active layer
  • Fig. 1B is a cross-sectional view taken along p-p' in Fig. 1A
  • Fig. 1C is a cross-sectional view taken along z-z' in Fig. 1A.
  • the present application provides a display panel, including a substrate 100, an active layer 101, a first scan line SL1, and a variable signal line EML1.
  • the substrate 100 includes a rigid substrate and a flexible substrate.
  • the substrate 100 includes glass, polyimide, quartz, etc.
  • a buffer layer 100 a is further disposed on the substrate 100 .
  • the active layer 101 is located on the substrate 100.
  • the active layer 101 includes a silicon semiconductor material or an oxide semiconductor material.
  • the silicon semiconductor material includes single crystal silicon, polycrystalline silicon, etc.; the oxide semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO) or indium gallium zinc tin oxide (IGZTO), etc.
  • the active layer 101 is made using a low temperature polysilicon process.
  • the active layer 101 includes a first channel portion CP1 and a second channel portion CP2 disposed opposite to each other, and a first electrical connection portion Cn1 connected between the first channel portion CP1 and the second channel portion CP2.
  • the first scan line SL1 extends along the first direction x and overlaps the first channel portion CP1 and the second channel portion CP2 .
  • the variable signal line EML1 includes a routing portion EML11 and an overlapping portion EML12 that are interconnected.
  • the overlapping portion EML12 is located on a side of the routing portion EML11 close to the first electrical connection portion Cn1, and the overlapping portion EML12 at least partially overlaps with the first electrical connection portion Cn1, so that the overlapping portion EML12 and the first electrical connection portion Cn1 form two electrodes of a coupling capacitor Co, so as to improve the low-frequency flicker problem by utilizing the coupling capacitor Co and the variable signal EM1 transmitted by the variable signal line EML1.
  • the overlapping area between the variable signal line EML1 and the first electrical connection portion Cn1 may be greater than 0 micrometer*micrometer and less than or equal to 100 micrometer*micrometer.
  • the routing portion EML11 includes a first sub-portion EML11a, a second sub-portion EML11b and a third sub-portion EML11c, the first sub-portion EML11a and the first electrical connection portion Cn1 are arranged at intervals, the second sub-portion EML11b and the third sub-portion EML11c are respectively connected to the two ends of the first sub-portion EML11a, and the extension line between the second sub-portion EML11b and the third sub-portion EML11c overlaps with the first electrical connection portion Cn1.
  • the distance between the second sub-portion EML11b and the second end of the first electrical connection portion Cn1 is smaller than the distance between the third sub-portion EML11c and the second end of the first electrical connection portion Cn1, and the overlapping portion EML12 is connected to the portion of the first sub-portion EML11a close to the second sub-portion EML11b, so that when the capacitance value of the required coupling capacitor Co is small, only the overlapping portion EML12 overlaps with the first electrical connection portion Cn1.
  • the overlapping portion EML12 protrudes toward the first scan line SL1 relative to the second sub-portion EML11 b , and the first scan line SL1 has a recess corresponding to the overlapping portion EML12 , so that there is no overlap between the first scan line SL1 and the overlapping portion EML12 .
  • variable signal line EML1 is located on the active layer 101 or under the active layer 101.
  • the display panel further includes a first conductive layer 102 located on the active layer 101, and the first conductive layer 102 includes the variable signal line EML1.
  • the first conductive layer 102 includes at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), etc.
  • the first conductive layer 102 can be a single-layer film structure, or a stacked structure such as Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Cu/Mo, Cu/Ti, Cu/MoTi or Cu/MoNb.
  • the display panel further includes an insulating layer between the first conductive layer 102 and the active layer 101.
  • the insulating layer includes a first insulating layer 1001 and a second insulating layer 1002.
  • the first insulating layer 1001 and the second insulating layer 1002 may respectively include a silicon compound, a metal oxide, etc.
  • the first insulating layer 1001 and the second insulating layer 1002 may respectively include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.
  • 100b in FIG. 1B to FIG. 1C is a multi-layer composite insulating layer (ie, including an interlayer dielectric layer, a first planarization layer, a second planarization layer, and a pixel definition layer, etc.).
  • FIGS. 2A and 2B are schematic diagrams showing the connection between the first gate drive circuit and the sub-pixel provided in the embodiment of the present application.
  • the display panel further includes a plurality of signal lines and a plurality of sub-pixels.
  • the plurality of signal lines include a plurality of scan lines, a plurality of data lines DL, a plurality of emission control lines EML, a plurality of reset lines and a plurality of variable signal lines EML1.
  • the plurality of scan lines are used to transmit a plurality of scan signals, and the plurality of scan lines include a plurality of first scan lines SL1, a plurality of second scan lines SL22, a plurality of third scan lines SL21, and a plurality of fourth scan lines SL23.
  • the first scan line SL1 is used to transmit the first scan signal S1
  • the second scan line SL22, the third scan line SL21, and the fourth scan line SL23 are all used to transmit the second scan signal S2.
  • the second scan signal transmitted by the second scan line SL22 is valid before the second scan signal transmitted by the third scan line SL21
  • the second scan signal transmitted by the fourth scan line SL23 is the same as the second scan signal transmitted by the second scan line SL22 or the second scan signal transmitted by the third scan line SL21.
  • the data line DL is used to transmit data signals; the light control line EML is used to transmit the light control signal EM; the reset line includes a first reset line VL1 and a second reset line VL2, the first reset line VL1 is used to transmit a first reset signal, the second reset line VL2 is used to transmit a second reset signal, the first reset signal and the second reset signal may be equal or unequal.
  • the variable signal line EML1 is used to transmit a variable signal EM1.
  • the frequency of the first scanning signal S1 is less than the frequency of the second scanning signal S2.
  • the effective pulse of the first scanning signal S1 is located in a writing frame WF of a display cycle
  • the effective pulse of the second scanning signal S2 is located in a writing frame WF and a holding frame HF of a display cycle.
  • a display cycle includes a holding frame HF
  • the display panel adopts a low refresh frequency driving mode.
  • a plurality of sub-pixels in the same row are electrically connected to the same variable signal line EML1 , so that the sub-pixels in the same row are all acted upon by the same variable signal EM1 , thereby improving the flicker problem.
  • the display panel further includes a plurality of gate drive circuits, the plurality of gate drive circuits including at least a first gate drive circuit EMG1, a plurality of cascaded second gate drive circuits, a plurality of cascaded third gate drive circuits and a plurality of cascaded fourth gate drive circuits EMG2.
  • the plurality of gate drive circuits including at least a first gate drive circuit EMG1, a plurality of cascaded second gate drive circuits, a plurality of cascaded third gate drive circuits and a plurality of cascaded fourth gate drive circuits EMG2.
  • the display panel includes a first enabling driving circuit EMG1, a plurality of variable signal lines EML1 are electrically connected to the first enabling driving circuit EMG1, and a first enabling driving circuit EMG1 is configured to output the variable signal EM1 to the plurality of variable signal lines EM1, as shown in FIG. 2A, so that the plurality of sub-pixels arranged in the array are all under the action of the same variable signal EM1, thereby improving the flicker problem.
  • the display panel includes a plurality of cascaded first selection drive circuits EMG1, each first selection drive circuit EMG1 is electrically connected to two variable signal lines EML1, and each first selection drive circuit EMG1 is configured to output the variable signal EM1 to the two variable signal lines EM1, as shown in FIG. 2B, so that the plurality of sub-pixels located in two rows are affected by the same variable signal EM1, thereby improving the flicker problem.
  • the design of a first selection drive circuit EMG1 as shown in Figure 2A outputting the variable signal EM1 to multiple variable signal lines EM1 is conducive to realizing the narrow frame design of the display panel; the design of a first selection drive circuit EMG1 as shown in Figure 2B outputting the variable signal EM1 to two variable signal lines EM1 does not have high requirements on the design of the driver chip and is easy to control.
  • variable signal line EML1 may also be electrically connected to a driving chip to provide a variable signal through the driving chip.
  • a plurality of cascaded second selection drive circuits are electrically connected to a plurality of first scan lines SL1 to provide a plurality of first scan signals S1 to the plurality of first scan lines SL1; a plurality of cascaded third selection drive circuits are electrically connected to a plurality of second scan lines SL22, a plurality of third scan lines SL21 and a plurality of fourth scan lines SL23 to provide a plurality of second scan signals S2 to the plurality of second scan lines SL22, a plurality of third scan lines SL21 and a plurality of fourth scan lines SL23; a plurality of cascaded fourth selection drive circuits EMG2 are electrically connected to a plurality of light-emitting control lines EML to provide a plurality of light-emitting control signals to the plurality of light-emitting control lines EML.
  • the topology structure of the fourth gate driving circuit EMG2 is the same as the topology structure of the first gate driving circuit EMG1, so that the existing design can be used to save design costs.
  • the arrangement positions of the plurality of cascaded fourth gate driving circuits EMG2 and the plurality of cascaded first gate driving circuits EMG1 are symmetrical about the central axis of the display area of the display panel to facilitate wiring and reduce the frame of the display panel.
  • FIG. 3 is a schematic diagram of the structure of a sub-pixel provided in an embodiment of the present application
  • FIG. 4 is a timing diagram provided in an embodiment of the present application.
  • Each of the sub-pixels includes a light-emitting device D and a pixel driving circuit.
  • Each sub-pixel is electrically connected to a corresponding scan line, a corresponding data line DL, and a corresponding light-emitting control line EML, so that the pixel driving circuit controls the corresponding light-emitting device D to emit light according to the corresponding scan signal, data signal, and light-emitting control signal EM.
  • the light-emitting device D includes an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, etc.
  • At least one pixel driving circuit includes a driving transistor T1 , a compensation transistor and a coupling capacitor Co.
  • the source and drain of the driving transistor T1 and the corresponding light emitting device D are connected in series between the first power line VDD and the second power line VSS.
  • the driving transistor T1 is used to generate a driving current for driving the light emitting device D to emit light according to the data signal transmitted to the gate of the driving transistor T1.
  • the compensation transistor includes a first sub-transistor TL1 and a second sub-transistor TL2 connected in series, and the first sub-transistor TL1 and the second sub-transistor TL2 have a connection node A.
  • One of the source and the drain of the first sub-transistor TL1 is electrically connected to the gate of the driving transistor T1
  • the other of the source and the drain of the first sub-transistor TL1 is electrically connected to one of the source and the drain of the second sub-transistor TL2 through the connection node A
  • the other of the source and the drain of the second sub-transistor TL2 is electrically connected to one of the source and the drain of the driving transistor T1
  • the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 are both electrically connected to the first scan line SL1.
  • the coupling capacitor Co is connected in series between the variable signal line EML1 and the connection node A, and is used to couple the potential of the connection node A according to the variable signal EM1 transmitted by the variable signal line EML1 to change the difference between the connection node A and the gate potential of the driving transistor T1.
  • At least one of the pixel driving circuits further includes a data transistor T2, a source and a drain of the data transistor T2 being electrically connected between the other of the source and the drain of the driving transistor T1 and the data line DL, and a gate of the data transistor T2 being electrically connected to the third scan line SL21.
  • the data transistor T2 is used to transmit a data signal to the gate of the driving transistor T1 according to a second scan signal S2 transmitted by the corresponding third scan line SL21, so that the gate of the driving transistor T1 has a first potential.
  • variable signal EM1 has at least one level jump, so that the potential of the connection node A changes accordingly due to coupling during the light emitting phase, thereby changing the gate potential of the driving transistor T1 accordingly to improve the flicker problem.
  • the display panel includes a plurality of cascaded first gate drive circuits EMG1, and each first gate drive circuit EMG1 is configured to output the variable signal EM1 to two variable signal lines EM1, the level jump times of the plurality of variable signals EM1 are different, as shown by EM1(n) and EM1(n+1) in FIG4 , so that the plurality of sub-pixels can adjust the gate potential of their respective drive transistors T1 at different times, so that the average value of the gate potential of the drive transistors T1 of the plurality of sub-pixels is substantially stable at the first potential during the light-emitting phase.
  • the display panel includes a first gate drive circuit EMG1, and a first gate drive circuit EMG1 is configured to output the variable signal EM1 to a plurality of variable signal lines EM1, the timing of the variable signal EM1 can be as shown by EM1 in FIG4 .
  • variable signal EM1 has at least one jump from the second potential V2 to the third potential V3, and the first potential is between the second potential V2 and the third potential V3, so that the average value of the gate potential of the driving transistor T1 is basically stable at the first potential during the light-emitting stage.
  • the capacitance value of the coupling capacitor Co may be greater than 0 femtofarad and less than or equal to 10 femtofarad.
  • At least one pixel driving circuit further includes a compensation transistor T3 , a first switch transistor T4 , a second switch transistor T5 , an initial transistor T6 , a reset transistor and a storage capacitor Cst.
  • the source and drain of the compensation transistor T3 are electrically connected between one of the source and drain of the driving transistor T1 and the other of the source and drain of the second sub-transistor TL2, and the gate of the compensation transistor T3 is electrically connected to the third scan line SL21.
  • the compensation transistor T3 is used to transmit the data signal to the gate of the driving transistor T1 in cooperation with the compensation transistor and the data transistor T2 according to the second scan signal S2 transmitted by the third scan line SL21.
  • the source and drain of the first switch transistor T4 are electrically connected between the other of the source and drain of the driving transistor T1 and the first power line
  • the source and drain of the second switch transistor T5 are electrically connected between one of the source and drain of the driving transistor T1 and the first node B
  • the gate of the first switch transistor T4 and the gate of the second switch transistor T5 are both electrically connected to the light emitting control line EML.
  • the first switch transistor T4 and the second switch transistor T5 are used to enable the driving transistor T1 to drive the light emitting device D to emit light according to the light emitting control signal EM transmitted by the light emitting control line EML.
  • the source and drain of the initial transistor T6 are electrically connected between the second reset line VL2 and the first node B, the gate of the initial transistor T6 is electrically connected to the fourth scan line SL23, and the initial transistor T6 is used to transmit the second reset signal transmitted by the second reset line VL2 to the first node B according to the second scan signal transmitted by the fourth scan line SL23.
  • the light emitting device D is electrically connected between the first node B and the second power line VSS.
  • the source and drain of the reset transistor are electrically connected between the first reset line VL1 and the other of the source and drain of the second sub-transistor TL2, and the gate of the reset transistor is electrically connected to the second scan line SL22.
  • the reset transistor includes a third sub-transistor TL3 and a fourth sub-transistor TL4 connected in series, one of the source and drain of the third sub-transistor TL3 is electrically connected to the first reset line VL1, one of the source and drain of the fourth sub-transistor TL4 is electrically connected to the other of the source and drain of the second sub-transistor TL2, the other of the source and drain of the fourth sub-transistor TL4 is electrically connected to the other of the source and drain of the third sub-transistor TL3, and the gate of the third sub-transistor TL3 and the gate of the fourth sub-transistor TL4 are both electrically connected to the second scan line SL22.
  • the storage capacitor Cst is connected in series between the first power line and the gate of the driving transistor T1 , and is used to maintain the gate potential of the driving transistor T1 .
  • each transistor included in the pixel driving circuit includes a silicon semiconductor material or an oxide semiconductor, wherein the silicon semiconductor material includes polycrystalline silicon, single crystal silicon, etc., and the oxide semiconductor material includes indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO), etc.
  • the silicon semiconductor material includes polycrystalline silicon, single crystal silicon, etc.
  • the oxide semiconductor material includes indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO), etc.
  • each transistor included in the pixel driving circuit is a P-type transistor
  • the first scanning line SL1 electrically connected to the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2 transmits the first scanning signal S1(n) of the nth level
  • the second scanning line SL22 electrically connected to the gate of the third sub-transistor TL3 and the gate of the fourth sub-transistor TL4 transmits the second scanning signal S2(n-1) of the n-1th level
  • the light emitting control line EML electrically connected to the gate of the first switch transistor T4 and the gate of the second switch transistor T5 transmits the light emitting control signal EM(n) of the nth level
  • the third scanning line SL21 electrically connected to the gate of the data transistor T2 and the gate of the compensation transistor T3 and the fourth scanning line SL23 electrically connected to the gate of the initial transistor T6 both transmit the second scanning signal S2(
  • the first scan signal S1(n) transmitted by the first scan line SL1 and the second scan signal S2(n-1) transmitted by the second scan line SL22 are valid, the first sub-transistor TL1, the second sub-transistor TL2, the third sub-transistor TL3 and the fourth sub-transistor TL4 are turned on, and the first reset signal transmitted by the first reset line VL1 is transmitted to the gate of the driving transistor T1 via the third sub-transistor TL3, the fourth sub-transistor TL4, the second sub-transistor TL2 and the first sub-transistor TL1 to reset the gate potential of the driving transistor T1.
  • the first scanning signal S1(n) transmitted by the first scanning line SL1 and the second scanning signal S2(n) transmitted by the third scanning line SL21 and the fourth scanning line SL23 are valid
  • the first sub-transistor TL1, the second sub-transistor TL2, the data transistor T2, the compensation transistor T3 and the initial transistor T6 are turned on in response to the second scanning signal S2(n)
  • the data signal transmitted by the data line DL is transmitted to the gate of the driving transistor T1 via the data transistor T2, the compensation transistor T3, the second sub-transistor TL2 and the first sub-transistor TL1, so that the gate of the driving transistor T1 has a first potential.
  • the second reset signal transmitted by the second reset line VL2 is transmitted to the first node B via the initial transistor T6 to reset the anode potential of the light emitting device D.
  • the light-emitting control signal EM(n) transmitted by the light-emitting control line EML is effective
  • the first switch transistor T4 and the second switch transistor T5 are turned on in response to the light-emitting control signal EM(n)
  • the driving transistor T1 generates a driving current for driving the light-emitting device D to emit light.
  • the frequency of the light-emitting control signal EM(n) is greater than the frequency of the first scanning signal S1(n), and the low-frequency flicker problem can be improved by continuously switching the light-emitting device D between bright and dark states.
  • the writing frame WF includes the stage in which the data signal is transmitted to the gate of the driving transistor T1, while the holding frame HF does not include the stage in which the data signal is transmitted to the gate of the driving transistor T1.
  • a display cycle includes at least one holding frame HF, and the data displayed by the holding frame HF is consistent with the data displayed in the writing frame WF. Therefore, it can be understood that the light-emitting stage t3 continues from the writing frame WF to the holding frame HF.
  • the second scanning signal S2 still has a valid pulse in the holding frame, which can correct the gate potential of the driving transistor T1 and compensate for the brightness change of the light-emitting device D.
  • the change time of the variable signal EM1(n) is after the data signal is transmitted to the gate of the driving transistor T1.
  • the variable signal EM1(n) can change in the light-emitting phase t3 of the write frame, or can change in the hold frame HF.
  • the change time of the variable signal EM1(n) is within the invalid pulse action time of the light-emitting control signal EM(n), or the change time of the variable signal EM1(n) is the same as the change time of the light-emitting control signal EM(n).
  • the moment when the variable signal EM1(n) changes from the second potential V2 to the third potential V3 is the same as the moment when the light-emitting control signal EM(n) changes from a high level to a low level; or, the moment when the variable signal EM1(n) changes from the third potential V3 to the second potential V2 is the same as the moment when the light-emitting control signal EM(n) changes from a high level to a low level.
  • the first potential is greater than the third potential V3 and less than the second potential V2.
  • variable signal EM1(n) maintains the second potential V2 for a first time period t11
  • variable signal EM1(n) maintains the third potential V3 for a second time period t12.
  • the gate of the driving transistor T1 is mainly affected by the first reset signal and the data signal
  • the variable signal EM1(n) is the third potential V3 or the second potential V2 and does not affect the gate potential of the driving transistor T1.
  • the variable signal EM1(n) has a jump in the light-emitting stage t3
  • the potential of the connection node A changes accordingly due to the coupling effect, so that the gate potential of the driving transistor T1 also changes accordingly.
  • the transistors of the pixel driving circuit are still P-type transistors.
  • the variable signal EM1(n) jumps from the third potential V3 to the second potential V2, and the potential of the connection node A is coupled to be higher than the gate potential of the driving transistor T1 through the coupling capacitor Co.
  • the connection node A leaks to the gate of the driving transistor T1, so that the gate potential of the driving transistor T1 becomes higher accordingly, thereby reducing the driving current, causing the light-emitting brightness of the light-emitting device D to decrease.
  • the jump of the variable signal EM1(n) can cause the brightness of the light emitting device D to change, and by continuously jumping the variable signal EM1(n) between the second potential V2 and the third potential V3, the average value of the gate potential of the driving transistor T1 can be basically stabilized at the first potential.
  • the duration of the first time period t11 may be equal to or unequal to the duration of the second time period t12. It is understandable that the duration of the first time period t11 and the duration of the second time period t12 may be set according to actual needs, and the duration of each time the variable signal EM1(n) maintains the second potential V2 may be equal or unequal, and the duration of each time the variable signal EM1(n) maintains the third potential V3 may be equal or unequal. The shorter the duration of the first time period t11 and the duration of the second time period t12, the more times the variable signal EM1(n) jumps, and the higher the frequency of the variable signal EM1(n).
  • the potential of the connection node A and the gate potential of the driving transistor T1 are always equal, and the brightness of the light-emitting device D changes minimally.
  • the gate potential of the driving transistor T1 is different under different grayscales, and the potential of the connection node A is not much different, therefore, without changing the potential of the connection node A, only individual grayscales can have a better display effect, and most of the remaining grayscales are not well displayed due to the difference between the potential of the connection node A and the gate potential of the driving transistor T1.
  • the present application utilizes the light-emitting stage t3, which is a relatively long period of time that must exist during low-frequency driving, so that the potential of the connection node A can be changed during the light-emitting stage t3 through the action of the coupling capacitor Co, so as to comprehensively combine the influence of the second potential V2 and the third potential V3 on the gate potential of the driving transistor T1, so that the average value of the gate potential of the driving transistor T1 is basically stable at the first potential, so that the light-emitting brightness of the light-emitting device D is basically maintained at the initial light-emitting brightness, which can improve the flicker problem existing in low-frequency driving, thereby improving the display quality.
  • each first enable driving circuit EMG1 when the display panel includes multiple cascaded first enable driving circuits EMG1, and each first enable driving circuit EMG1 is configured to output the variable signal EM1 to two variable signal lines EM1, the second potentials V2 of the multiple variable signals EM1 may be the same or different, the third potentials V3 of the multiple variable signals EM1 may also be the same or different, the time length for which the multiple variable signals EM1 maintain the second potential V2 each time may also be the same or different, and the time length for which the multiple variable signals EM1 maintain the third potential V3 each time may also be the same or different.
  • FIG5 is a schematic diagram of display brightness change provided by an embodiment of the present application; wherein L1 represents the display brightness change curve obtained by driving the light-emitting device using the pixel driving circuit of the present application with the gate potential of the driving transistor T1, and L2 represents the display brightness change curve obtained by driving the light-emitting device using the pixel driving circuit in the prior art (the pixel driving circuit in the prior art has no coupling capacitor Co) with the gate potential of the driving transistor.
  • the luminous brightness of the light-emitting device D driven by the pixel driving circuit of the present application will change multiple times, but the change amplitude of the luminous brightness of the light-emitting device D is significantly smaller than the brightness change amplitude of the light-emitting device driven by the pixel driving circuit in the prior art.
  • a display cycle (1 Display) is greater than the duration of each change in luminous brightness, even if the number of times the second potential V2 is greater than the gate potential of the driving transistor T1 is not equal to the number of times the third potential V3 is less than the gate potential of the driving transistor T1, it only manifests as a difference in the number of brightness change switches in L1. From the perspective of the duration of a display cycle (1 Display), the difference in the number of brightness change switches has little effect on the overall brightness change. It can be understood that a display cycle (1 Display) can include only one write frame WF, or it can include a write frame WF and at least one hold frame HF.
  • FIG6 is a schematic diagram of the film layer structure of the sub-pixel provided in an embodiment of the present application
  • FIG7 is a schematic diagram of the structure of the active layer provided in an embodiment of the present application.
  • the active layer 101 includes a first sub-active pattern of the first sub-transistor TL1, a second sub-active pattern of the second sub-transistor TL2, a first active pattern of the driving transistor T1, a second active pattern of the data transistor T2, a third active pattern of the compensation transistor T3, a fourth active pattern of the first switch transistor T4, a fifth active pattern of the second switch transistor T5, a sixth active pattern of the initial transistor T6 and a first electrical connection portion Cn1.
  • the first sub-active pattern includes a first channel portion CP1, the second sub-active pattern includes a second channel portion CP2, and the first electrical connection portion Cn1 is connected between the first sub-active pattern and the second sub-active pattern to serve as a connection node A.
  • the first electrical connection portion Cn1 extends along a first direction x
  • the first sub-active pattern and the second sub-active pattern extend along a second direction y
  • the first direction x and the second direction y intersect.
  • the first sub-active pattern and the second sub-active pattern are located on the same side of the first electrical connection portion Cn1.
  • the first end of the first electrical connection portion Cn1 is connected to the first end STL1 of the first sub-active pattern
  • the second end of the first electrical connection portion Cn1 is connected to the second end DTL2 of the second sub-active pattern.
  • the overlapping portion EML12 overlaps with the second end of the first electrical connection portion Cn1 and the second end DTL2 of the second sub-active pattern, so that the overlapping portion EML12 and the second end of the first electrical connection portion Cn1 and the second end DTL2 of the second sub-active pattern form two electrodes of the coupling capacitor Co.
  • the ion doping concentration of the first electrical connection portion Cn1 is greater than the ion doping concentration of the first channel portion CP1 and the second channel portion CP2, so that the conductivity of the first electrical connection portion Cn1 is higher than the conductivity of the first channel portion CP1 and the second channel portion CP2, thereby utilizing the first electrical connection portion Cn1 to electrically connect the first sub-active pattern and the second sub-active pattern.
  • the first end ST1 of the first active pattern is connected to the second end DT2 of the second active pattern and the second end DT4 of the fourth active pattern; the second end DT1 of the first active pattern is connected to the first end ST3 of the third active pattern and the first end ST5 of the fifth active pattern, and the second end DT5 of the fifth active pattern is connected to the first end ST6 of the sixth active pattern.
  • the second active pattern, the third active pattern, the fourth active pattern and the fifth active pattern all extend along the second direction y, and the second active pattern and the third active pattern are arranged at intervals, the fourth active pattern and the fifth active pattern are arranged at intervals, and the second end DT3 of the third active pattern is connected to the first end STL2 of the second sub-active pattern.
  • the active layer 101 also includes a third sub-active pattern of the third sub-transistor TL3, a fourth sub-active pattern of the fourth sub-transistor TL4, and a second electrical connection portion Cn2 connected between the third sub-active pattern and the fourth sub-active pattern
  • the third sub-active pattern includes a third channel portion CP3
  • the fourth sub-active pattern includes a fourth channel portion CP4
  • the second scan line SL22 overlaps with the third channel portion CP3 and the fourth channel portion CP4, so that the display panel can still be prepared using the existing preparation process, thereby achieving a lower manufacturing cost than the LTPO backplane.
  • the first end STL3 of the third sub-active pattern and the second end DTL4 of the fourth sub-active pattern are connected through the second electrical connection portion Cn2, and the second electrical connection portion Cn2 extends along the first direction x and overlaps with the first reset line VL1, so that the overlapping portion of the second electrical connection portion Cn2 and the first reset line VL1 forms two electrodes of another coupling capacitor, thereby maintaining the potential of the middle node (i.e., point C in Figure 3) of the third sub-transistor TL3 and the fourth sub-transistor TL4, and reducing the influence of the potential of the middle node of the third sub-transistor TL3 and the fourth sub-transistor TL4 on the gate potential of the driving transistor T1.
  • the middle node i.e., point C in Figure 3
  • the third sub-active pattern and the fourth sub-active pattern are both located between the variable signal line EML1 and the first reset line VL1, and the third sub-active pattern and the fourth sub-active pattern are both spaced apart from the variable signal line EML1 to avoid the variable signal line EML1 and the first scan line SL1 from forming unnecessary transistors when realizing the connection between the second sub-active pattern and the fourth sub-active pattern, thereby affecting the normal display of the sub-pixel.
  • the second sub-active pattern and the fourth sub-active pattern are electrically connected via a bridge portion F3 that is in a different layer from the variable signal line EML1 and the first scan line SL1 .
  • variable signal line EML1 and the first reset line VL1 are in the same layer and made of the same material.
  • FIG8 is a schematic diagram of the structure of the first conductive layer provided in an embodiment of the present application, and the first conductive layer 102 further includes a first reset line VL1, a second reset line VL2, and a first electrode portion E1.
  • the first reset line VL1 is located on a side of the variable signal line EML1 away from the second reset line VL2; the first electrode portion E1 is located between the second reset line VL2 and the variable signal line EML1, and the first electrode portion E1 overlaps with the first active pattern.
  • the first power line VDD includes a first sub-power line VDD1 and a second sub-power line VDD2 that are electrically connected, the first sub-power line VDD1 extends along the second direction y; the second sub-power line VDD2 extends along the first direction x, and the first sub-power line VDD1 and the second sub-power line VDD2 are in different layers.
  • the first conductive layer 102 also includes a second sub-power line VDD2, the second sub-power line VDD2 is located between the first electrode portion E1 and the variable signal line EML1, and the second sub-power line VDD2 is connected to the first electrode portion E1.
  • variable signal line EML1 is in a different layer from the first scan line SL1 and the second scan line SL22.
  • FIG9 is a schematic diagram of the structure of the second conductive layer provided in an embodiment of the present application; the display panel further includes a second conductive layer, and the second conductive layer is located between the first conductive layer 102 and the active layer 101. Further, the second conductive layer is located between the first insulating layer 1001 and the second insulating layer 1002.
  • the second conductive layer includes the first scan line SL1, the third scan line SL21, the second scan line SL22, the fourth scan line SL23, the light emitting control line EML, and the second electrode portion E2.
  • variable signal line EML1 is located between the first scan line SL1 and the second scan line SL22
  • first reset line VL1 is located on the side of the second scan line SL22 away from the variable signal line EML1
  • the third scan line SL21 is located between the first scan line SL1 and the second sub-power line VDD2
  • the light-emitting control line EML is located between the second sub-power line VDD2 and the second reset line VL2
  • fourth scan line SL23 is located on the side of the second reset line VL2 away from the light-emitting control line EML.
  • the portion where the first scan line SL1 overlaps with the first channel portion CP1 is used as the gate of the first sub-transistor TL1, and the portion where the first scan line SL1 overlaps with the second channel portion CP2 is used as the gate of the second sub-transistor TL2.
  • the portion where the second scan line SL22 overlaps with the third channel portion CP3 is used as the gate of the third sub-transistor TL3, and the portion where the second scan line SL22 overlaps with the fourth channel portion CP4 is used as the gate of the fourth sub-transistor TL4.
  • the third scan line SL21 partially overlaps with the second active pattern and the third active pattern, and the portion where the third scan line SL21 overlaps with the second active pattern is used as the gate of the data transistor T2, and the portion where the third scan line SL21 overlaps with the third active pattern is used as the gate of the compensation transistor T3.
  • the light emission control line EML partially overlaps with the fourth active pattern and the fifth active pattern, and the portion where the light emission control line EML overlaps with the fourth active pattern is used as the gate of the first switch transistor T4, and the portion where the light emission control line EML overlaps with the fifth active pattern is used as the gate of the second switch transistor T5.
  • the fourth scan line SL23 partially overlaps with the sixth active pattern, and the portion where the fourth scan line SL23 overlaps with the sixth active pattern is used as the gate of the initial transistor T6.
  • the second electrode portion E2 overlaps with the first active pattern to serve as a gate of the driving transistor T1 ; the first electrode portion E1 and the second electrode portion E2 overlap to form two electrodes of the storage capacitor Cst.
  • the first end ST2 of the second active pattern, the second end DTL1 of the first sub-active pattern, the first end STL2 of the second sub-active pattern, and the second end DT3 of the third active pattern are all located between the third scan line SL21 and the first scan line SL1.
  • the second end DTL3 of the third sub-active pattern and the first end STL4 of the fourth sub-active pattern are located between the variable signal line EML1 and the second scan line SL22.
  • the first end ST4 of the fourth active pattern and the second end DT5 of the fifth active pattern are both located between the light emitting control line EML and the second reset line VL2, and the second end DT6 of the sixth active pattern is located on the side of the fourth scan line SL23 away from the second reset line VL2.
  • the first active pattern is u-shaped.
  • FIG10 is a schematic diagram of the structure of the third conductive layer provided in an embodiment of the present application, wherein the display panel further includes an interlayer dielectric layer and a third conductive layer located on the first conductive layer.
  • the third conductive layer includes a first conductive portion F1, a second conductive portion F2, a bridge portion F3, a fourth conductive portion F4, a fifth conductive portion F5, a sixth conductive portion F6, and a seventh conductive portion F7.
  • the first conductive portion F1 extends along the second direction y, and is electrically connected between the second electrode portion E2 and the second end DTL1 of the first sub-active pattern, so as to realize the electrical connection between the gate of the driving transistor T1 and the first sub-transistor TL1.
  • the first electrode portion E1 includes a first opening exposing the second electrode portion E2, and the first conductive portion F1 is electrically connected to the second electrode portion E2 through the first opening and a via hole penetrating the interlayer dielectric layer and the second insulating layer 1002 (such as CNT1 in FIG.
  • the second conductive portion F2 overlaps with the first end ST2 of the second active pattern and is electrically connected to the first end ST2 of the second active pattern to serve as the source of the data transistor T2. Specifically, the second conductive portion F2 is electrically connected to the first end ST2 of the second active pattern (such as CNT3 in FIG. 10 ) through a via hole penetrating the interlayer dielectric layer, the second insulating layer 1002 and the first insulating layer 1001 to serve as the source of the data transistor T2.
  • the bridge portion F3 extends along the second direction y and is electrically connected between the first end STL2 of the second sub-active pattern and the first end STL4 of the fourth sub-active pattern to achieve electrical connection between the second sub-transistor TL2 and the fourth sub-transistor TL4. Specifically, the bridge portion F3 is electrically connected to the first end STL2 of the second sub-active pattern through a via hole penetrating the interlayer dielectric layer, the second insulating layer 1002 and the first insulating layer 1001 (such as CNT4 in FIG.
  • the fourth conductive portion F4 extends along the second direction y, and is electrically connected between the first electrode portion E1 and the first end ST4 of the fourth active pattern, so as to realize the electrical connection between the first switch transistor T4 and the second sub-power line VDD2. Specifically, the fourth conductive portion F4 is electrically connected to the first electrode portion E1 through a via hole penetrating the interlayer dielectric layer (such as CNT6 in FIG. 10), and is electrically connected to the first end ST4 of the fourth active pattern through a via hole penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (such as CNT7 in FIG. 10).
  • a via hole penetrating the interlayer dielectric layer such as CNT6 in FIG. 10
  • the first insulating layer 1001 such as CNT7 in FIG. 10
  • the fifth conductive portion F5 is electrically connected between the second end DTL3 of the third sub-active pattern and the first reset line VL1 to realize the electrical connection between the third sub-transistor TL3 and the first reset line VL1.
  • the fifth conductive portion F5 is electrically connected to the second end DTL3 of the third sub-active pattern through a via hole penetrating the interlayer dielectric layer, the second insulating layer 1002 and the first insulating layer 1001 (such as CNT8 in FIG. 10), and is electrically connected to the first reset line VL1 through a via hole penetrating the interlayer dielectric layer (such as CNT9 in FIG. 10).
  • the sixth conductive portion F6 extends along the second direction y, overlaps the second electrode portion E2, the light emitting control line EML, and the fifth active pattern portion, and is electrically connected to the second end DT5 of the fifth active pattern to serve as the first node B. Specifically, the sixth conductive portion F6 is electrically connected to the second end DT5 of the fifth active pattern through a via hole penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (such as CNT10 in FIG. 10 ).
  • the seventh conductive portion F7 is electrically connected between the second end DT6 of the sixth active pattern and the second reset line VL2 to achieve electrical connection between the initial transistor T6 and the second reset line VL2. Specifically, the seventh conductive portion F7 is electrically connected to the second end DT6 of the sixth active pattern through a via hole penetrating the interlayer dielectric layer, the second insulating layer 1002 and the first insulating layer 1001 (such as CNT11 in FIG. 10), and is electrically connected to the second reset line VL2 through a via hole penetrating the interlayer dielectric layer (such as CNT12 in FIG. 10).
  • FIG. 11 is a schematic structural diagram of a fourth conductive layer provided in an embodiment of the present application; the display panel further includes a first planar layer and a fourth conductive layer located on the third conductive layer, and the fourth conductive layer includes a data line DL and a first sub-power line VDD1.
  • the data line DL includes a first main portion DL1 and an extension portion DL2.
  • the first main portion DL1 extends along the second direction y
  • the extension portion DL2 is located on a side of the first main portion DL1 close to the first sub-active pattern
  • the extension portion DL2 overlaps with the first end ST2 and the second conductive portion F2 of the second active pattern
  • the extension portion DL2 is electrically connected to the second conductive portion F2
  • the extension portion DL2 is electrically connected to the first end ST2 of the second active pattern through the second conductive portion F2.
  • the extension portion DL2 is electrically connected to the second conductive portion F2 through a via hole penetrating the first planar layer (such as PLN1 in FIG. 11).
  • the first sub-power line VDD1 is spaced apart from the data line DL, and the first sub-power line VDD1 includes a second main body VD1, a third main body VD2, and a avoidance portion VD3 located between the second main body VD1 and the third main body VD2 and corresponding to the extension portion DL2.
  • the second main body VD1 and the third main body VD2 both extend along the second direction y.
  • the avoidance portion VD3 overlaps with the junction of the first sub-portion EML11a and the third sub-portion EML11c, and is spaced apart from the overlapping portion EML12, so that there is no overlap between the avoidance portion VD3 and the overlapping portion EML12, and then there is no parasitic capacitance between the avoidance portion VD3 and the overlapping portion EML12.
  • the second sub-power line VDD2 is electrically connected to the first sub-power line VDD1 through the fourth conductive part F4.
  • part of the third main body VD2 overlaps with the fourth conductive part F4 and is electrically connected to the fourth conductive part F4, and the fourth conductive part F4 is electrically connected between the first electrode part E1 and the first end ST4 of the fourth active pattern, and the first electrode part E1 is electrically connected to the second sub-power line VDD2.
  • the fourth conductive part F4 can realize the electrical connection between the second sub-power line VDD2 and the first sub-power line VDD1, and can make one of the source and drain of the first switch transistor T4 electrically connected to the second sub-power line VDD2 and the first sub-power line VDD1.
  • the third main body VD2 is electrically connected to the fourth conductive part F4 through a via that penetrates the first planar layer (such as PLN2 in Figure 11).
  • the fourth conductive layer further includes a node connection portion B1, which is located on a side of the first sub-power line VDD1 away from the data line DL, overlaps with the sixth conductive portion F6 and is electrically connected to the sixth conductive portion F6.
  • the node connection portion B1 is electrically connected to the sixth conductive portion F6 through a via hole penetrating the first planar layer (such as PLN3 in FIG. 11).
  • the size of the portion corresponding to the via hole in each conductive layer and the active layer may be larger than the size of the portion not corresponding to the via hole in each conductive layer and the active layer.
  • the plurality of light emitting devices are electrically connected to the first nodes B of the plurality of pixel driving circuits.
  • the light emitting device and the source and drain of the driving transistor T1 in the corresponding pixel driving circuit are electrically connected between the first voltage terminal and the second voltage terminal.
  • the first power line is electrically connected between the first voltage terminal and one of the source and drain of the driving transistor T1
  • the second power line is electrically connected between the cathode of the light emitting device and the second voltage terminal.
  • the present application also provides a display device, the display device comprising any of the above-mentioned drive circuits or any of the above-mentioned display panels.
  • the display device includes a movable display device (such as a laptop computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a thermometer, etc.), etc.

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Abstract

本申请公开一种显示面板，包括有源层、第一扫描线及可变信号线。第一扫描线沿第一方向延伸，且与有源层中相对设置的第一沟道部和第二沟道部重叠。可变信号线包括相互连接的走线部和重叠部，重叠部位于走线部靠近第一电连接部的一侧，且重叠部与有源层中的连接于第一沟道部和第二沟道部之间的第一电连接部至少部分重叠。

Description

显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种显示面板。
 背景技术
在现有的显示面板中，常采用LTPO（Low Temperature Polycrystalline Oxide，低温多晶氧化物）背板和LTPS（Low Temperature Poly-silicon低温多晶硅）背板，但LTPS背板中晶体管的漏电流较大，会引起流经发光器件的驱动电流的变化，导致显示面板在低频驱动时出现闪烁问题；而LTPO背板的结构和制备工艺又较复杂，制备成本也较高。
 技术问题
本申请实施例提供一种显示面板，可以实现改善显示面板低频驱动闪烁问题的方案。
 技术解决方案
本申请实施例提供一种显示面板，包括有源层、第一扫描线及可变信号线。有源层包括相对设置的第一沟道部和第二沟道部，以及连接于第一沟道部和第二沟道部之间的第一电连接部；第一扫描线沿第一方向延伸，且与第一沟道部和第二沟道部重叠；可变信号线包括相互连接的走线部和重叠部，重叠部位于走线部靠近第一电连接部的一侧，且重叠部与第一电连接部至少部分重叠。
可选地，在本申请的一些实施例中，显示面板还包括多个子像素，每一子像素包括发光器件及像素驱动电路，像素驱动电路包括：驱动晶体管，与发光器件串联于第一电源线和第二电源线之间；以及补偿晶体管，包括串联的第一子晶体管和第二子晶体管，第一子晶体管的源极和漏极中的一个与驱动晶体管的栅极电性连接，第一子晶体管的源极和漏极中的另一个电性连接于第二子晶体管的源极和漏极中的一个，第二子晶体管的源极和漏极中的另一个电性连接于驱动晶体管的源极和漏极中的一个，第一子晶体管的栅极和第二子晶体管的栅极均电性连接于第一扫描线。其中，有源层还包括第一子晶体管的第一子有源图案及第二子晶体管的第二子有源图案，第一子有源图案包括第一沟道部，第二子有源图案包括第二沟道部。
可选地，在本申请的一些实施例中，显示面板包括多条可变信号线，位于同一行的多个子像素与同一可变信号线电性连接。
可选地，在本申请的一些实施例中，显示面板还包括一第一选通驱动电路，与多条可变信号线电性连接，被配置为将可变信号输出至多条可变信号线。其中，在驱动晶体管驱动发光器件发光的发光阶段内，可变信号至少具有一次电平跳变。
可选地，在本申请的一些实施例中，显示面板还包括多个级联的第一选通驱动电路，每一第一选通驱动电路与两可变信号线电性连接，并被配置为将可变信号输出至两可变信号线。其中，在驱动晶体管驱动发光器件发光的发光阶段内，每一可变信号至少具有一次电平跳变，且多个可变信号的电平跳变的时刻不同。
可选地，在本申请一些实施例中，像素驱动电路还包括复位晶体管，复位晶体管包括串联的第三子晶体管和第四子晶体管，第三子晶体管的源极和漏极中的一个与第一复位线电性连接，第四子晶体管的源极和漏极中的一个与第二子晶体管的源极和漏极中的另一个电性连接，第四子晶体管的源极和漏极中的另一个与第三子晶体管的源极和漏极中的另一个电性连接，第三子晶体管的栅极和第四子晶体管的栅极均与第二扫描线电性连接。其中，可变信号线位于第一扫描线和第二扫描线之间，且可变信号线与第一扫描线和第二扫描线异层。
可选地，在本申请的一些实施例中，有源层还包括第三子晶体管的第三子有源图案、第四子晶体管的第四子有源图案及连接于第三子有源图案和第四子有源图案之间的第二电连接部；第三子有源图案包括第三沟道部，第四子有源图案包括第四沟道部。其中，第二扫描线与第三沟道部和第四沟道部重叠，第一复位线与第二电连接部重叠；第三子有源图案与第四子有源图案均位于可变信号线与第一复位线之间，且第三子有源图案和第四子有源图案均与可变信号线间隔设置。
可选地，在本申请的一些实施例中，第二子有源图案和第四子有源图案通过与可变信号线、第一扫描线异层的桥接部电性连接。
可选地，在本申请的一些实施例中，可变信号线与第一复位线同层且材料相同。
可选地，在本申请的一些实施例中，第一电连接部的离子掺杂浓度大于第一沟道部、第二沟道部的离子掺杂浓度。
可选地，在本申请一些实施例中，显示面板还包括：第一导电层，位于有源层上，包括可变信号线；第二导电层，位于第一导电层和有源层之间，包括第一扫描线及第二扫描线；以及第三导电层，位于第一导电层上，包括桥接部。
可选地，在本申请的一些实施例中，像素驱动电路还包括数据晶体管，数据晶体管的源极和漏极电性连接于驱动晶体管的源极和漏极中的另一个和数据线之间，数据晶体管的栅极电性连接于第三扫描线；数据晶体管用于向驱动晶体管的栅极传输数据信号，以使驱动晶体管的栅极具有第一电位。
可选地，在本申请的一些实施例中，在驱动晶体管驱动发光器件发光的发光阶段内，可变信号线传输的可变信号至少具有一次由第二电位至第三电位的跳变。其中，第一电位介于第二电位和第三电位之间。
可选地，在本申请的一些实施例中，重叠部与第一电连接部至少部分重叠以形成耦合电容。其中，耦合电容的电容值大于0飞法且小于或等于10飞法。
可选地，在本申请的一些实施例中，显示面板还包括第四导电层，位于第一导电层上，包括数据线。
 有益效果
相较于现有技术，本申请提供一种显示面板，包括有源层、第一扫描线及可变信号线。第一扫描线沿第一方向延伸，且第一扫描线与有源层中相对设置的第一沟道部和第二沟道部重叠。可变信号线包括相互连接的走线部和重叠部，重叠部位于走线部靠近第一电连接部的一侧，且重叠部与有源层中的连接于第一沟道部和第二沟道部之间的第一电连接部至少部分重叠，以形成耦合电容，从而在显示面板采用低频驱动时，利用可变信号线传输的可变信号及耦合电容实现改善低频闪烁问题的方案。
 附图说明
图1A是可变信号线与有源层重叠的结构示意图；
图1B是图1A中沿p-p’剖切的剖视图；
图1C是图1A中沿z-z’剖切的剖视图；
图2A~图2B是本申请实施例提供的第一选通驱动电路与子像素的连接示意图；
图3是本申请实施例提供的子像素的结构示意图；
图4是本申请实施例提供的时序图；
图5是本申请实施例提供的显示亮度变化示意图；
图6是本申请实施例提供的子像素的膜层结构示意图；
图7是本申请实施例提供的有源层的结构示意图；
图8是本申请实施例提供的第一导电层的结构示意图；
图9是本申请实施例提供的第二导电层的结构示意图；
图10是本申请实施例提供的第三导电层的结构示意图；
图11是本申请实施例提供的第四导电层的结构示意图。
本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
具体地，图1A是可变信号线与有源层重叠的结构示意图，图1B是图1A中沿p-p’剖切的剖视图，图1C是图1A中沿z-z’剖切的剖视图。本申请提供一种显示面板，包括衬底100、有源层101、第一扫描线SL1及可变信号线EML1。
衬底100包括刚性衬底和柔性衬底。可选地，衬底100包括玻璃、聚酰亚胺、石英等。可选地，衬底100上还设有缓冲层100a。
有源层101位于衬底100上。可选地，有源层101包括硅半导体材料或氧化物半导体材料。可选地，硅半导体材料包括单晶硅、多晶硅等；氧化物半导体材料可以包括铟镓锌氧化物(IGZO)、铟镓锡氧化物(IGTO)或者铟镓锌锡氧化物(IGZTO)等。可选地，有源层101采用低温多晶硅工艺制得。
有源层101包括相对设置的第一沟道部CP1和第二沟道部CP2，以及连接于第一沟道部CP1和第二沟道部CP2之间的第一电连接部Cn1。
第一扫描线SL1沿第一方向x延伸，且与第一沟道部CP1和第二沟道部CP2重叠。
可变信号线EML1包括相互连接的走线部EML11和重叠部EML12，重叠部EML12位于走线部EML11靠近第一电连接部Cn1的一侧，且重叠部EML12与第一电连接部Cn1至少部分重叠，以使重叠部EML12与第一电连接部Cn1形成耦合电容Co的两电极，以利用耦容电容Co及可变信号线EML1传输的可变信号EM1改善低频闪烁问题。
可选地，在显示面板采用高分辨率设计时，受设计空间的限制，可变信号线EML1与第一电连接部Cn1的重叠面积可以大于0微米*微米且小于或等于100微米*微米。
可选地，请继续参阅图1A，走线部EML11包括第一子部EML11a、第二子部EML11b和第三子部EML11c，第一子部EML11a和第一电连接部Cn1间隔设置，第二子部EML11b和所述第三子部EML11c分别与第一子部EML11a的两端相接，第二子部EML11b和第三子部EML11c之间的延长线与第一电连接部Cn1重叠。其中，第二子部EML11b距第一电连接部Cn1的第二端的距离，小于第三子部EML11c距第一电连接部Cn1的第二端的距离，重叠部EML12与第一子部EML11a的靠近第二子部EML11b的部分相接，以在所需的耦合电容Co的电容值较小时，仅重叠部EML12和第一电连接部Cn1重叠。
可选地，重叠部EML12相对于第二子部EML11b朝向第一扫描线SL1突出，第一扫描线SL1对应重叠部EML12具有凹陷，以使第一扫描线SL1与重叠部EML12之间无交叠。
可选地，请继续参阅图1B~图1C，可变信号线EML1位于有源层101上或位于有源层101下。可选地，显示面板还包括位于有源层101上的第一导电层102，第一导电层102包括可变信号线EML1。可选地，第一导电层102包括钼(Mo)、铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、钙(Ca)、钛(Ti)、钽(Ta)、钨(W)、铜(Cu)等中的至少一种。可选地，第一导电层102可为单层膜层结构，也可为Ti/Al/Ti、Mo/Al/Mo、Mo/AlGe/Mo、Cu/Mo、Cu/Ti、Cu/MoTi或Cu/MoNb等叠层结构。
可选地，显示面板还包括位于第一导电层102和有源层101之间的绝缘层。可选地，绝缘层包括第一绝缘层1001和第二绝缘层1002。可选地，第一绝缘层1001和第二绝缘层1002可分别包括硅化合物、金属氧化物等。进一步地，第一绝缘层1001和第二绝缘层1002可分别包括硅氧化物、硅氮化物、硅氮氧化物、铝氧化物、钽氧化物、铪氧化物、锆氧化物、钛氧化物等。
图1B~图1C中的100b为多层复合绝缘层（即包括层间介电层、第一平坦层、第二平坦层和像素定义层等）。
如图2A~图2B是本申请实施例提供的第一选通驱动电路与子像素的连接示意图。显示面板还包括多条信号线和多个子像素。
可选地，多条信号线包括多条扫描线，多条数据线DL、多条发光控制线EML、多条复位线和多条可变信号线EML1。
多条扫描线用于传输多个扫描信号，多条扫描线包括多条第一扫描线SL1、多条第二扫描线SL22、多条第三扫描线SL21和多条第四扫描线SL23。第一扫描线SL1用于传输第一扫描信号S1，第二扫描线SL22、第三扫描线SL21及第四扫描线SL23均用于传输第二扫描信号S2。其中，与同一像素驱动电路电性连接的第三扫描线SL21、第二扫描线SL22及第四扫描线SL23中，第二扫描线SL22传输的第二扫描信号先于第三扫描线SL21传输的第二扫描信号有效，第四扫描线SL23传输的第二扫描信号与第二扫描线SL22传输的第二扫描信号或第三扫描线SL21传输的第二扫描信号相同。
数据线DL用于传输数据信号；发光控制线EML用于传输发光控制信号EM；复位线包括第一复位线VL1和第二复位线VL2，第一复位线VL1用于传输第一复位信号，第二复位线VL2用于传输第二复位信号，第一复位信号和第二复位信号可以相等或不相等。可变信号线EML1用于传输可变信号EM1。
可选地，第一扫描信号S1的频率小于第二扫描信号S2的频率。可选地，第一扫描信号S1的有效脉冲位于一显示周期的写入帧WF内，第二扫描信号S2的有效脉冲位于一显示周期的写入帧WF和保持帧HF内。其中，在一显示周期包括保持帧HF时，即为显示面板采用了低刷新频率的驱动方式。
可选地，位于同一行的多个子像素与同一可变信号线EML1电性连接，以使位于同一行的子像素均在同一可变信号EM1的作用下，实现改善闪烁的问题。
可选地，显示面板还包括多个选通驱动电路，多个选通驱动电路包括至少一第一选通驱动电路EMG1、多个级联的第二选通驱动电路、多个级联的第三选通驱动电路及多个级联的第四选通驱动电路EMG2。
可选地，显示面板包括一第一选通驱动电路EMG1，多条可变信号线EML1与第一选通驱动电路EMG1电性连接，一第一选通驱动电路EMG1被配置为将可变信号EM1输出至多条可变信号线EM1，如图2A所示，以使阵列排布的多个子像素均在同一可变信号EM1的作用下，实现改善闪烁的问题。
可选地，显示面板包括多个级联的第一选通驱动电路EMG1，每一第一选通驱动电路EMG1与两条可变信号线EML1电性连接，每一第一选通驱动电路EMG1被配置为将可变信号EM1输出至两条可变信号线EM1，如图2B所示，以使位于两行的多个子像素在同一可变信号EM1的作用下，实现改善闪烁的问题。
其中，如图2A所示的一第一选通驱动电路EMG1将可变信号EM1输出至多条可变信号线EM1的设计，有利于实现显示面板的窄边框设计；如图2B所示的一第一选通驱动电路EMG1将可变信号EM1输出至两条可变信号线EM1的设计对驱动芯片的设计要求不高，易于实现控制。
可选地，可变信号线EML1也可与驱动芯片电性连接，以通过驱动芯片提供可变信号。
多个级联的第二选通驱动电路与多条第一扫描线SL1电性连接，以向多条第一扫描线SL1提供多个第一扫描信号S1；多个级联的第三选通驱动电路与多条第二扫描线SL22、多条第三扫描线SL21和多条第四扫描线SL23电性连接，以向多条第二扫描线SL22、多条第三扫描线SL21和多条第四扫描线SL23提供多个第二扫描信号S2；多个级联的第四选通驱动电路EMG2与多条发光控制线EML电性连接，以向多条发光控制线EML提供多个发光控制信号。
可选地，第四选通驱动电路EMG2的拓扑结构和第一选通驱动电路EMG1的拓扑结构相同，以沿用现有的设计，从而节省设计成本。
可选地，多个级联的第四选通驱动电路EMG2和多个级联的第一选通驱动电路EMG1的设置位置关于显示面板显示区的中心轴线对称，以便于布线及缩减显示面板的边框。
如图3是本申请实施例提供的子像素的结构示意图，图4是本申请实施例提供的时序图。每一所述子像素包括发光器件D及像素驱动电路。每一子像素与对应的扫描线、对应的数据线DL及对应的发光控制线EML电性连接，以使像素驱动电路根据对应的扫描信号、数据信号及发光控制信号EM控制对应的发光器件D发光。可选地，所述发光器件D包括有机发光二极管、次毫米发光二极管、微型发光二极管等。
至少一像素驱动电路包括驱动晶体管T1、补偿晶体管及耦合电容Co。
驱动晶体管T1的源极和漏极与对应的发光器件D串联在第一电源线VDD和第二电源线VSS之间，驱动晶体管T1用于根据传输至驱动晶体管T1的栅极的数据信号，生成驱动发光器件D发光的驱动电流。
补偿晶体管包括串联的第一子晶体管TL1和第二子晶体管TL2，第一子晶体管TL1和第二子晶体管TL2具有连接节点A。第一子晶体管TL1的源极和漏极中的一个与驱动晶体管T1的栅极电性连接，第一子晶体管TL1的源极和漏极中的另一个通过连接节点A电性连接于第二子晶体管TL2的源极和漏极中的一个，所述第二子晶体管TL2的源极和漏极中的另一个电性连接于所述驱动晶体管T1的源极和漏极中的一个，第一子晶体管TL1的栅极和所述第二子晶体管TL2的栅极均电性连接于第一扫描线SL1。
耦合电容Co串联于可变信号线EML1和连接节点A之间，用于根据可变信号线EML1传输的可变信号EM1耦合连接节点A的电位，以改变连接节点A和驱动晶体管T1的栅极电位之差。
请继续参阅图3，至少一所述像素驱动电路还包括数据晶体管T2，数据晶体管T2的源极和漏极电性连接于驱动晶体管T1的源极和漏极中的另一个和数据线DL之间，数据晶体管T2的栅极电性连接于第三扫描线SL21。数据晶体管T2用于根据对应的第三扫描线SL21传输的第二扫描信号S2而向驱动晶体管T1的栅极传输数据信号，以使驱动晶体管T1的栅极具有第一电位。
在驱动晶体管T1驱动发光器件D发光的发光阶段内，可变信号EM1至少具有一次电平跳变，以使连接节点A的电位在发光阶段内受耦合作用而相应变化，从而使驱动晶体管T1的栅极电位也相应变化，以改善闪烁问题。
可选地，在显示面板包括多个级联的第一选通驱动电路EMG1，且每一第一选通驱动电路EMG1被配置为将可变信号EM1输出至两条可变信号线EM1时，多个可变信号EM1的电平跳变的时刻不同，如图4中的EM1(n)和EM1(n+1)所示，以使多个子像素可在不同的时刻对各自的驱动晶体管T1的栅极电位进行调节，从而使多个子像素的驱动晶体管T1的栅极电位的均值在发光阶段内基本稳定在第一电位。在显示面板包括一第一选通驱动电路EMG1，且一第一选通驱动电路EMG1被配置为将可变信号EM1输出至多条可变信号线EM1时，可变信号EM1的时序可如图4中的EM1所示。
可选地，在驱动晶体管T1驱动发光器件D发光的发光阶段内，可变信号EM1至少具有一次由第二电位V2至第三电位V3的跳变，第一电位介于第二电位V2和第三电位V3之间，以使驱动晶体管T1的栅极电位的均值在发光阶段内基本稳定在第一电位。
可选地，为使所述第一电位介于所述第二电位V2和所述第三电位V3之间，耦合电容Co的电容值可大于0飞法且小于或等于10飞法。
请继续参阅图3，至少一像素驱动电路还包括补偿晶体管T3、第一开关晶体管T4、第二开关晶体管T5、初始晶体管T6、复位晶体管及存储电容Cst。
补偿晶体管T3的源极和漏极电性连接于驱动晶体管T1的源极和漏极中的一个与第二子晶体管TL2的源极和漏极中的另一个之间，补偿晶体管T3的栅极电性连接于第三扫描线SL21。补偿晶体管T3用于根据第三扫描线SL21传输的第二扫描信号S2，配合补偿晶体管和数据晶体管T2将数据信号传输至驱动晶体管T1的栅极。
第一开关晶体管T4的源极和漏极电性连接于驱动晶体管T1的源极和漏极中的另一个和第一电源线之间，第二开关晶体管T5的源极和漏极电性连接于驱动晶体管T1的源极和漏极中的一个和第一节点B之间，第一开关晶体管T4的栅极和第二开关晶体管T5的栅极均电性连接于发光控制线EML。第一开关晶体管T4和第二开关晶体管T5用于根据发光控制线EML传输的发光控制信号EM使驱动晶体管T1驱动发光器件D发光。
初始晶体管T6的源极和漏极电性连接于第二复位线VL2和第一节点B之间，初始晶体管T6的栅极电性连接于第四扫描线SL23，初始晶体管T6用于根据第四扫描线SL23传输的第二扫描信号将第二复位线VL2传输的第二复位信号传输至第一节点B。发光器件D电性连接于所述第一节点B和第二电源线VSS之间。
复位晶体管的源极和漏极电性连接于第一复位线VL1和第二子晶体管TL2的源极和漏极中的另一个之间，复位晶体管的栅极电性连接于第二扫描线SL22。可选地，复位晶体管包括串联的第三子晶体管TL3和第四子晶体管TL4，第三子晶体管TL3的源极和漏极中的一个与第一复位线VL1电性连接，第四子晶体管TL4的源极和漏极中的一个与第二子晶体管TL2的源极和漏极中的另一个电性连接，第四子晶体管TL4的源极和漏极中的另一个与第三子晶体管TL3的源极和漏极中的另一个电性连接，第三子晶体管TL3的栅极和第四子晶体管TL4的栅极均与第二扫描线SL22电性连接。
存储电容Cst串联于第一电源线和驱动晶体管T1的栅极之间，用于维持驱动晶体管T1的栅极电位。
可选地，像素驱动电路包括的各晶体管包括硅半导体材料或氧化物半导体。其中，硅半导体材料包括多晶硅、单晶硅等；氧化物半导体材料包括铟镓锌氧化物(IGZO)、铟镓锡氧化物(IGTO)或者铟镓锌锡氧化物(IGZTO)等。
请继续参阅图3~图4，以像素驱动电路包括的各晶体管为P型晶体管，第一子晶体管TL1的栅极和第二子晶体管TL2的栅极电性连接的第一扫描线SL1传输第n级的第一扫描信号S1(n)；第三子晶体管TL3的栅极和第四子晶体管TL4的栅极电性连接的第二扫描线SL22传输第n-1级的第二扫描信号S2(n-1)；第一开关晶体管T4的栅极和第二开关晶体管T5的栅极电性连接的发光控制线EML传输第n级的发光控制信号EM(n)；数据晶体管T2的栅极和补偿晶体管T3的栅极电性连接的第三扫描线SL21以及初始晶体管T6的栅极电性连接的第四扫描线SL23均传输第n级的第二扫描信号S2(n)为例，对像素驱动电路的工作原理进行说明。其中，n≥1。
在复位阶段t1，第一扫描线SL1传输的第一扫描信号S1(n)及第二扫描线SL22传输的第二扫描信号S2(n-1)有效，第一子晶体管TL1、第二子晶体管TL2、第三子晶体管TL3和第四子晶体管TL4导通，第一复位线VL1传输的第一复位信号经第三子晶体管TL3、第四子晶体管TL4、第二子晶体管TL2和第一子晶体管TL1传输至驱动晶体管T1的栅极，以对驱动晶体管T1的栅极电位进行复位。
在数据写入阶段t2，第一扫描线SL1传输的第一扫描信号S1(n)及第三扫描线SL21和第四扫描线SL23传输的第二扫描信号S2(n)有效，第一子晶体管TL1、第二子晶体管TL2、数据晶体管T2、补偿晶体管T3及初始晶体管T6响应第二扫描信号S2(n)导通，数据线DL传输的数据信号经数据晶体管T2、补偿晶体管T3、第二子晶体管TL2和第一子晶体管TL1传输至驱动晶体管T1的栅极，以使驱动晶体管T1的栅极具有第一电位。第二复位线VL2传输的第二复位信号经初始晶体管T6传输至第一节点B，以对发光器件D的阳极电位进行复位。
在发光阶段t3，发光控制线EML传输的发光控制信号EM(n)有效，第一开关晶体管T4和第二开关晶体管T5响应发光控制信号EM(n)导通，驱动晶体管T1生成驱动发光器件D发光的驱动电流。可选地，发光控制信号EM(n)的频率大于第一扫描信号S1(n)的频率，可通过发光器件D不断的亮暗状态改善低频闪烁问题。
写入帧WF包括数据信号被传输至驱动晶体管T1的栅极的阶段，保持帧HF则不包括数据信号被传输至驱动晶体管T1的栅极的阶段。在采用低频进行驱动显示时，一显示周期至少包括一保持帧HF，保持帧HF所显示的数据与写入帧WF内所显示的数据保持一致。因此，可以理解的，发光阶段t3自写入帧WF延续至保持帧HF。第二扫描信号S2在保持帧内仍具有有效脉冲，可对驱动晶体管T1的栅极电位进行修正，补偿发光器件D的亮度变化。
可变信号EM1(n)的跳变时刻位于数据信号被传输至驱动晶体管T1的栅极之后。如可变信号EM1(n)可在写入帧的发光阶段t3内进行跳变，也可在保持帧HF内进行跳变。其中，为避免可变信号EM1(n)的跳变导致发光器件D的亮度变化被人眼所察觉，可变信号EM1(n)的跳变时刻位于发光控制信号EM(n)的无效脉冲作用时间内，或可变信号EM1(n)的跳变时刻与发光控制信号EM(n)的跳变时刻相同。如在写入帧WF的发光阶段t3内，可变信号EM1(n)由第二电位V2跳变至第三电位V3的时刻与发光控制信号EM(n)由高电平跳变至低电平的时刻相同；或，可变信号EM1(n)由第三电位V3跳变至第二电位V2的时刻与发光控制信号EM(n)由高电平跳变至低电平的时刻相同。可选地，第一电位大于第三电位V3，且小于第二电位V2。
可变信号EM1(n)保持第二电位V2的时长为第一时间段t11，可变信号EM1(n)保持第三电位V3的时长为第二时间段t12。在写入帧WF的第一时间段t11内，驱动晶体管T1的栅极主要受第一复位信号和数据信号的影响，可变信号EM1(n)为第三电位V3或第二电位V2并不影响驱动晶体管T1的栅极电位。在可变信号EM1(n)在发光阶段t3内具有跳变后，连接节点A的电位受耦合作用而相应变化，从而使驱动晶体管T1的栅极电位也相应变化。如以像素驱动电路的各晶体管仍为P型晶体管为例进行说明，可变信号EM1(n)由第三电位V3跳变至第二电位V2，则连接节点A的电位经耦合电容Co作用被耦合升高至大于驱动晶体管T1的栅极电位，连接节点A向驱动晶体管T1的栅极漏电，使得驱动晶体管T1的栅极电位相应变高，从而使驱动电流降低，引起发光器件D的发光亮度降低。可变信号EM1(n)由第二电位V2跳变至第三电位V3时，连接节点A的电位经耦合电容Co作用被耦合降低至小于驱动晶体管T1的栅极电位，驱动晶体管T1的栅极向连接节点A漏电，使得驱动晶体管T1的栅极电位相应降低，从而使驱动电流升高，引起发光器件D的发光亮度升高。因此，可变信号EM1(n)的跳变可引起发光器件D的亮度变化，通过不断的使可变信号EM1(n)在第二电位V2和第三电位V3之间进行跳变，可以使驱动晶体管T1的栅极电位的均值基本稳定在第一电位。
可选地，第一时间段t11的时长可与第二时间段t12的时长相等，也可不相等。可以理解的，第一时间段t11的时长与第二时间段t12的时长可根据实际需求进行设定，可变信号EM1(n)每次维持第二电位V2的时长可均相等或均不相等，可变信号EM1(n)每次维持第三电位V3的时长也可均相等或均不相等。第一时间段t11的时长与第二时间段t12的时长越短，可变信号EM1(n)的跳变次数越多，可变信号EM1(n)的频率也就越高。
理论上连接节点A的电位和驱动晶体管T1的栅极电位一直相等，发光器件D的亮度变化最小。但由于不同灰阶下，驱动晶体管T1的栅极电位不同，而连接节点A的电位相差不大，因此，在不改变连接节点A的电位的情况下，只能使个别灰阶具有较好的显示效果，其余大部分灰阶由于连接节点A的电位和驱动晶体管T1的栅极电位之间的差异，显示的改善效果并不好。因此，本申请利用低频驱动时必然存在的较长时间段的发光阶段t3，使连接节点A的电位经耦合电容Co作用在发光阶段t3内实现可变，以综合第二电位V2和第三电位V3对驱动晶体管T1的栅极电位的影响，使驱动晶体管T1的栅极电位的均值基本稳定在第一电位，从而使发光器件D的发光亮度基本维持在最初发光亮度，可以改善低频驱动存在的闪烁问题，从而改善显示品质。
可以理解的，在显示面板包括多个级联的第一选通驱动电路EMG1，且每一第一选通驱动电路EMG1被配置为将可变信号EM1输出至两条可变信号线EM1时，多个可变信号EM1的第二电位V2可以相同或不同，多个可变信号EM1的第三电位V3也可相同或不同，多个可变信号EM1每次维持第二电位V2的时长也可相同或不同，多个可变信号EM1每次维持第三电位V3的时长也可相同或不同。
如图5是本申请实施例提供的显示亮度变化示意图；其中，L1表示利用本申请的像素驱动电路驱动发光器件得到的随驱动晶体管T1的栅极电位变化的显示亮度变化曲线，L2表示利用现有技术中的像素驱动电路（现有技术中的像素驱动电路无耦合电容Co）驱动发光器件得到的随驱动晶体管的栅极电位变化的显示亮度变化曲线。经对比可知，在一显示周期(1 Display)的时长内，采用本申请的像素驱动电路驱动的发光器件D的发光亮度会变化多次，但发光器件D的发光亮度的变化幅度明显小于现有技术中的像素驱动电路所驱动的发光器件的亮度变化幅度。
此外，由于一显示周期(1 Display)的时长要大于每一发光亮度的变化时长。因此，即使第二电位V2大于驱动晶体管T1的栅极电位的次数，与第三电位V3小于驱动晶体管T1的栅极电位的次数不相等，也仅表现为L1中亮度变化切换次数的差异，从一显示周期(1 Display)的时长内来看，亮度变化切换次数的差异对整体的亮度变化影响不大。可以理解的，一显示周期(1 Display)可以只包括写入帧WF一帧，也可包括一写入帧WF和至少一保持帧HF。
如图6是本申请实施例提供的子像素的膜层结构示意图，如图7是本申请实施例提供的有源层的结构示意图。请继续参阅图6~图7，有源层101包括第一子晶体管TL1的第一子有源图案、第二子晶体管TL2的第二子有源图案、驱动晶体管T1的第一有源图案、数据晶体管T2的第二有源图案、补偿晶体管T3的第三有源图案、第一开关晶体管T4的第四有源图案、第二开关晶体管T5的第五有源图案、初始晶体管T6的第六有源图案及第一电连接部Cn1。
可选地，第一子有源图案包括第一沟道部CP1，第二子有源图案包括第二沟道部CP2，第一电连接部Cn1连接于第一子有源图案和第二子有源图案之间，以用作连接节点A。可选地，第一电连接部Cn1沿第一方向x延伸，第一子有源图案和第二子有源图案沿第二方向y延伸，第一方向x和第二方向y交叉。第一子有源图案和第二子有源图案位于第一电连接部Cn1的同侧。第一电连接部Cn1的第一端与第一子有源图案的第一端STL1相接，第一电连接部Cn1的第二端和第二子有源图案的第二端DTL2相接。
可选地，重叠部EML12与第一电连接部Cn1的第二端和第二子有源图案的第二端DTL2的相接处重叠，以使重叠部EML12与第一电连接部Cn1的第二端和第二子有源图案的第二端DTL2的相接处形成耦合电容Co的两电极。
可选地，第一电连接部Cn1的离子掺杂浓度大于第一沟道部CP1、第二沟道部CP2的离子掺杂浓度，以使第一电连接部Cn1的导电性能高于第一沟道部CP1和第二沟道部CP2的导电性能，从而利用第一电连接部Cn1电性连接第一子有源图案和第二子有源图案。
第一有源图案的第一端ST1连接于第二有源图案的第二端DT2、第四有源图案的第二端DT4；第一有源图案的第二端DT1连接于第三有源图案的第一端ST3、第五有源图案的第一端ST5，第五有源图案的第二端DT5连接于第六有源图案的第一端ST6。第二有源图案、第三有源图案、第四有源图案及第五有源图案均沿第二方向y延伸，且第二有源图案和第三有源图案间隔设置，第四有源图案和第五有源图案间隔设置，第三有源图案的第二端DT3连接于第二子有源图案的第一端STL2。
可选地，有源层101还包括第三子晶体管TL3的第三子有源图案、第四子晶体管TL4的第四子有源图案及连接于第三子有源图案和第四子有源图案之间的第二电连接部Cn2，第三子有源图案包括第三沟道部CP3，第四子有源图案包括第四沟道部CP4，第二扫描线SL22与第三沟道部CP3和第四沟道部CP4重叠，以使显示面板仍可沿用现有制备工艺实现制备，从而可以实现较LTPO背板更低的制造成本。
可选地，第三子有源图案的第一端STL3和第四子有源图案的第二端DTL4通过第二电连接部Cn2相接，第二电连接部Cn2沿第一方向x延伸且与第一复位线VL1重叠，以使第二电连接部Cn2和第一复位线VL1重叠的部分形成另一耦合电容的两电极，从而维持第三子晶体管TL3和第四子晶体管TL4的中间节点(即图3中的C点)的电位，降低第三子晶体管TL3和第四子晶体管TL4的中间节点电位对驱动晶体管T1的栅极电位的影响。
可选地，第三子有源图案与第四子有源图案均位于可变信号线EML1与第一复位线VL1之间，且第三子有源图案和第四子有源图案均与可变信号线EML1间隔设置，以避免可变信号线EML1、第一扫描线SL1在实现第二子有源图案和第四子有源图案的连接时形成非必要的晶体管，从而影响子像素的正常显示。
可选地，第二子有源图案和第四子有源图案通过与可变信号线EML1、第一扫描线SL1异层的桥接部F3电性连接。
可选地，可变信号线EML1与第一复位线VL1同层且材料相同。如图8是本申请实施例提供的第一导电层的结构示意图，第一导电层102还包括第一复位线VL1、第二复位线VL2及第一电极部E1。第一复位线VL1位于可变信号线EML1远离第二复位线VL2的一侧；第一电极部E1位于第二复位线VL2和可变信号线EML1之间，且第一电极部E1与第一有源图案重叠。
可选地，第一电源线VDD包括电性连接的第一子电源线VDD1和第二子电源线VDD2，第一子电源线VDD1沿第二方向y延伸；第二子电源线VDD2沿第一方向x延伸，第一子电源线VDD1和第二子电源线VDD2异层。可选地，第一导电层102还包括第二子电源线VDD2，第二子电源线VDD2位于第一电极部E1和可变信号线EML1之间，且第二子电源线VDD2与第一电极部E1相接。
可选地，可变信号线EML1与第一扫描线SL1和第二扫描线SL22异层，如图9是本申请实施例提供的第二导电层的结构示意图；显示面板还包括第二导电层，第二导电层位于第一导电层102和有源层101之间。进一步地，第二导电层位于第一绝缘层1001和第二绝缘层1002之间。可选地，第二导电层包括第一扫描线SL1、第三扫描线SL21、第二扫描线SL22、第四扫描线SL23、发光控制线EML以及第二电极部E2。
其中，可变信号线EML1位于第一扫描线SL1和第二扫描线SL22之间，第一复位线VL1位于第二扫描线SL22远离可变信号线EML1的一侧，第三扫描线SL21位于第一扫描线SL1和第二子电源线VDD2之间，发光控制线EML位于第二子电源线VDD2和第二复位线VL2之间，第四扫描线SL23位于第二复位线VL2远离发光控制线EML的一侧。
第一扫描线SL1与第一沟道部CP1重叠的部分用作第一子晶体管TL1的栅极，第一扫描线SL1与第二沟道部CP2重叠的部分用作第二子晶体管TL2的栅极。第二扫描线SL22与第三沟道部CP3重叠的部分用作第三子晶体管TL3的栅极，第二扫描线SL22与第四沟道部CP4重叠的部分用作第四子晶体管TL4的栅极。第三扫描线SL21和第二有源图案、第三有源图案部分重叠，第三扫描线SL21与第二有源图案重叠的部分用作数据晶体管T2的栅极，第三扫描线SL21与第三有源图案重叠的部分用作补偿晶体管T3的栅极。发光控制线EML与第四有源图案、第五有源图案部分重叠，发光控制线EML与第四有源图案重叠的部分用作第一开关晶体管T4的栅极，发光控制线EML与第五有源图案重叠的部分用作第二开关晶体管T5的栅极。第四扫描线SL23与第六有源图案部分重叠，第四扫描线SL23与第六有源图案重叠的部分用作初始晶体管T6的栅极。第二电极部E2与第一有源图案重叠，以用作驱动晶体管T1的栅极；第一电极部E1和第二电极部E2重叠形成存储电容Cst的两电极。
可选地，第二有源图案的第一端ST2、第一子有源图案的第二端DTL1及第二子有源图案的第一端STL2及第三有源图案的第二端DT3均位于第三扫描线SL21和第一扫描线SL1之间。第三子有源图案的第二端DTL3、第四子有源图案的第一端STL4位于可变信号线EML1和第二扫描线SL22之间。第四有源图案的第一端ST4和第五有源图案的第二端DT5均位于发光控制线EML和第二复位线VL2之间，第六有源图案的第二端DT6位于第四扫描线SL23远离第二复位线VL2的一侧。可选地，第一有源图案为u形。
如图10是本申请实施例提供的第三导电层的结构示意图，显示面板还包括位于第一导电层上的层间介电层和第三导电层。第三导电层包括第一导电部F1、第二导电部F2、桥接部F3、第四导电部F4、第五导电部F5、第六导电部F6、第七导电部F7。
第一导电部F1沿第二方向y延伸，电性连接于第二电极部E2和第一子有源图案的第二端DTL1之间，以实现驱动晶体管T1的栅极和第一子晶体管TL1的电性连接。具体的，第一电极部E1包括暴露出第二电极部E2的第一开孔，第一导电部F1通过第一开孔及贯穿层间介电层和第二绝缘层1002的过孔与第二电极部E2电性连接(如图10中的CNT1处)，通过贯穿层间介电层、第二绝缘层1002和第一绝缘层1001的过孔与第一子有源图案的第二端DTL1电性连接(如图10中的CNT2处)。
第二导电部F2与第二有源图案的第一端ST2重叠，且电性连接于第二有源图案的第一端ST2，以用作数据晶体管T2的源极。具体的，第二导电部F2通过贯穿层间介电层、第二绝缘层1002和第一绝缘层1001的过孔与第二有源图案的第一端ST2电性连接(如图10中的CNT3处)，以用作数据晶体管T2的源极。
桥接部F3沿第二方向y延伸，电性连接于第二子有源图案的第一端STL2和第四子有源图案的第一端STL4之间，以实现第二子晶体管TL2和第四子晶体管TL4的电性连接。具体的，桥接部F3 通过贯穿层间介电层、第二绝缘层1002和第一绝缘层1001的过孔与第二子有源图案的第一端STL2电性连接(如图10的CNT4处)，通过贯穿层间介电层、第二绝缘层1002和第一绝缘层1001的过孔与第四子有源图案的第一端STL4 电性连接(如图10中的CNT5处)。
第四导电部F4沿第二方向y延伸，电性连接于第一电极部E1和第四有源图案的第一端ST4之间，实现第一开关晶体管T4与第二子电源线VDD2的电性连接。具体的，第四导电部F4通过贯穿层间介电层的过孔与第一电极部E1电性连接(如图10中的CNT6处)，通过贯穿层间介电层、第二绝缘层1002和第一绝缘层1001的过孔与第四有源图案的第一端ST4电性连接(如图10中的CNT7处)。
第五导电部F5电性连接于第三子有源图案的第二端DTL3和第一复位线VL1之间，以实现第三子晶体管TL3与第一复位线VL1的电性连接。具体的，第五导电部F5通过贯穿层间介电层、第二绝缘层1002和第一绝缘层1001的过孔与第三子有源图案的第二端DTL3电性连接(如图10中的CNT8处)，通过贯穿层间介电层的过孔与第一复位线VL1电性连接(如图10中的CNT9处)。
第六导电部F6沿第二方向y延伸，且与第二电极部E2和发光控制线EML、第五有源图案部分重叠，电性连接于第五有源图案的第二端DT5，以用作第一节点B。具体的，第六导电部F6通过贯穿层间介电层、第二绝缘层1002和第一绝缘层1001的过孔与第五有源图案的第二端DT5电性连接(如图10中的CNT10处)。
第七导电部F7电性连接于第六有源图案的第二端DT6和第二复位线VL2之间，以实现初始晶体管T6与第二复位线VL2的电性连接。具体的，第七导电部F7通过贯穿层间介电层、第二绝缘层1002和第一绝缘层1001的过孔与第六有源图案的第二端DT6电性连接(如图10中的CNT11处)，通过贯穿层间介电层的过孔第二复位线VL2电性连接(如图10中的CNT12处)。
图11是本申请实施例提供的第四导电层的结构示意图；显示面板还包括位于第三导电层上的第一平坦层和第四导电层，第四导电层包括数据线DL和第一子电源线VDD1。
数据线DL包括第一主体部DL1和延伸部DL2。第一主体部DL1沿第二方向y延伸，延伸部DL2位于第一主体部DL1靠近第一子有源图案的一侧，延伸部DL2与第二有源图案的第一端ST2及第二导电部F2重叠，延伸部DL2电性连接于第二导电部F2，延伸部DL2通过第二导电部F2电性连接于第二有源图案的第一端ST2。具体的，延伸部DL2通过贯穿第一平坦层的过孔与第二导电部F2电性连接(如图11中的PLN1处)。
第一子电源线VDD1与数据线DL间隔设置，第一子电源线VDD1包括第二主体部VD1、第三主体部VD2和位于第二主体部VD1和第三主体部VD2之间且对应延伸部DL2设置的避让部VD3。第二主体部VD1和第三主体部VD2均沿第二方向y延伸。避让部VD3与第一子部EML11a和第三子部EML11c的相接处重叠，且与重叠部EML12间隔设置，从而使避让部VD3和重叠部EML12之间无重叠，继而使避让部VD3和重叠部EML12之间无寄生电容。
可选地，第二子电源线VDD2通过第四导电部F4电性连接于第一子电源线VDD1。具体的，第三主体部VD2的部分与第四导电部F4重叠并与第四导电部F4电性连接，加之第四导电部F4又电性连接于第一电极部E1和第四有源图案的第一端ST4之间，第一电极部E1又与第二子电源线VDD2电性连接，因此，第四导电部F4可实现第二子电源线VDD2和第一子电源线VDD1的电性连接，以及可以使第一开关晶体管T4的源极和漏极中的一个与第二子电源线VDD2和第一子电源线VDD1电性连接。其中，第三主体部VD2通过贯穿第一平坦层的过孔与第四导电部F4电性连接(如图11中的PLN2处)。
可选地，第四导电层还包括节点连接部B1，节点连接部B1位于第一子电源线VDD1远离数据线DL的一侧，且与第六导电部F6重叠并电性连接于第六导电部F6。具体地，节点连接部B1通过贯穿第一平坦层的过孔与第六导电部F6电性连接(如图11中的PLN3处)。
可以理解的，各导电层及有源层中与过孔对应处的尺寸，可以大于各导电层及有源层中与过孔非对应处的尺寸。
可选地，多个发光器件对应电性连接至多个像素驱动电路的第一节点B处。发光器件与对应的像素驱动电路中的驱动晶体管T1的源极和漏极电性连接于第一电压端和第二电压端之间。可选地，第一电源线电性连接于第一电压端和驱动晶体管T1的源极和漏极中的一个之间，第二电源线电性连接于发光器件的阴极和第二电压端之间。
本申请还提供一种显示装置，所述显示装置包括任一上述的驱动电路或任一上述的显示面板。可以理解地，所述显示装置包括可移动显示装置（如笔记本电脑、手机等）、固定终端（如台式电脑、电视等）、测量装置（如运动手环、测温仪等）等。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想，本说明书内容不应理解为对本申请的限制。

Claims (14)

  1. 一种显示面板，其中，包括：
    有源层，包括相对设置的第一沟道部和第二沟道部，以及连接于所述第一沟道部和所述第二沟道部之间的第一电连接部；
    第一扫描线，沿第一方向延伸，且与所述第一沟道部和所述第二沟道部重叠；以及
    可变信号线，包括相互连接的走线部和重叠部，所述重叠部位于所述走线部靠近所述第一电连接部的一侧，且所述重叠部与所述第一电连接部至少部分重叠。
  2. 根据权利要求1所述的显示面板，其中，还包括多个子像素，每一所述子像素包括发光器件及像素驱动电路，所述像素驱动电路包括：
    驱动晶体管，与所述发光器件串联于第一电源线和第二电源线之间；以及
    补偿晶体管，包括串联的第一子晶体管和第二子晶体管，所述第一子晶体管的源极和漏极中的一个与所述驱动晶体管的栅极电性连接，所述第一子晶体管的源极和漏极中的另一个电性连接于所述第二子晶体管的源极和漏极中的一个，所述第二子晶体管的源极和漏极中的另一个电性连接于所述驱动晶体管的源极和漏极中的一个，所述第一子晶体管的栅极和所述第二子晶体管的栅极均电性连接于所述第一扫描线；
    其中，所述有源层还包括所述第一子晶体管的第一子有源图案及所述第二子晶体管的第二子有源图案，所述第一子有源图案包括所述第一沟道部，所述第二子有源图案包括所述第二沟道部。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板包括多条所述可变信号线，位于同一行的多个所述子像素与同一所述可变信号线电性连接。
  4. 根据权利要求3所述的显示面板，其中，还包括：
    一第一选通驱动电路，与多条所述可变信号线电性连接，被配置为将可变信号输出至多条所述可变信号线；
    其中，在所述驱动晶体管驱动所述发光器件发光的发光阶段内，所述可变信号至少具有一次电平跳变。
  5. 根据权利要求3所述的显示面板，其中，还包括：
    多个级联的第一选通驱动电路，每一所述第一选通驱动电路与两所述可变信号线电性连接，并被配置为将可变信号输出至两所述可变信号线；
    其中，在所述驱动晶体管驱动所述发光器件发光的发光阶段内，每一所述可变信号至少具有一次电平跳变，且多个所述可变信号的所述电平跳变的时刻不同。
  6. 根据权利要求2所述的显示面板，其中，所述像素驱动电路还包括复位晶体管，所述复位晶体管包括串联的第三子晶体管和第四子晶体管，所述第三子晶体管的源极和漏极中的一个与第一复位线电性连接，所述第四子晶体管的源极和漏极中的一个与所述第二子晶体管的源极和漏极中的另一个电性连接，所述第四子晶体管的源极和漏极中的另一个与所述第三子晶体管的源极和漏极中的另一个电性连接，所述第三子晶体管的栅极和所述第四子晶体管的栅极均与第二扫描线电性连接；
    其中，所述可变信号线位于所述第一扫描线和所述第二扫描线之间，且所述可变信号线与所述第一扫描线和所述第二扫描线异层。
  7. 根据权利要求6所述的显示面板，其中，所述有源层还包括所述第三子晶体管的第三子有源图案、所述第四子晶体管的第四子有源图案及连接于所述第三子有源图案和所述第四子有源图案之间的第二电连接部；所述第三子有源图案包括第三沟道部，所述第四子有源图案包括第四沟道部；
    其中，所述第二扫描线与所述第三沟道部和所述第四沟道部重叠，所述第一复位线与所述第二电连接部重叠；所述第三子有源图案与所述第四子有源图案均位于所述可变信号线与所述第一复位线之间，且所述第三子有源图案和所述第四子有源图案均与所述可变信号线间隔设置。
  8. 根据权利要求7所述的显示面板，其中，所述第二子有源图案和所述第四子有源图案通过与所述可变信号线、所述第一扫描线异层的桥接部电性连接。
  9. 根据权利要求6所述的显示面板，其中，所述可变信号线与所述第一复位线同层且材料相同。
  10. 根据权利要求1所述的显示面板，其中，所述第一电连接部的离子掺杂浓度大于所述第一沟道部、所述第二沟道部的离子掺杂浓度。
  11. 根据权利要求8所述的显示面板，其中，还包括：
    第一导电层，位于所述有源层上，包括所述可变信号线；
    第二导电层，位于所述第一导电层和所述有源层之间，包括所述第一扫描线及所述第二扫描线；以及
    第三导电层，位于所述第一导电层上，包括所述桥接部。
  12. 根据权利要求2所述的显示面板，其中，所述像素驱动电路还包括数据晶体管，所述数据晶体管的源极和漏极电性连接于所述驱动晶体管的源极和漏极中的另一个和数据线之间，所述数据晶体管的栅极电性连接于第三扫描线；所述数据晶体管用于向所述驱动晶体管的栅极传输数据信号，以使所述驱动晶体管的栅极具有第一电位。
  13. 根据权利要求12所述的显示面板，其中，在所述驱动晶体管驱动所述发光器件发光的发光阶段内，所述可变信号线传输的可变信号至少具有一次由第二电位至第三电位的跳变；
    其中，所述第一电位介于所述第二电位和所述第三电位之间。
  14. 根据权利要求13所述的显示面板，其中，所述重叠部与所述第一电连接部至少部分重叠以形成耦合电容；
    其中，所述耦合电容的电容值大于0飞法且小于或等于10飞法。
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CN115696988A (zh) * 2022-11-11 2023-02-03 武汉华星光电半导体显示技术有限公司 显示面板

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