WO2024093842A1 - 一种减少超声换能器声串扰的深槽隔离方法及超声换能器 - Google Patents

一种减少超声换能器声串扰的深槽隔离方法及超声换能器 Download PDF

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WO2024093842A1
WO2024093842A1 PCT/CN2023/127260 CN2023127260W WO2024093842A1 WO 2024093842 A1 WO2024093842 A1 WO 2024093842A1 CN 2023127260 W CN2023127260 W CN 2023127260W WO 2024093842 A1 WO2024093842 A1 WO 2024093842A1
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layer
pmut
cavity
substrate
deep
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PCT/CN2023/127260
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English (en)
French (fr)
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李晖
尹峰
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浙江仙声科技有限公司
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Publication of WO2024093842A1 publication Critical patent/WO2024093842A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
    • B06B1/0644—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction using a single piezoelectric element
    • B06B1/0662—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction using a single piezoelectric element with an electrode on the sensitive surface
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B2201/00—Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
    • B06B2201/70—Specific application
    • B06B2201/76—Medical, dental

Definitions

  • the present disclosure relates to the field of interference blocking technology, and in particular to a deep trench isolation method for reducing acoustic crosstalk of an ultrasonic transducer and an ultrasonic transducer.
  • Ultrasonic transducer arrays have many piezoelectric micromachined ultrasonic transducer (PMUT) units arranged in rows and columns to form an array, that is, a PMUT unit will have multiple adjacent units. When the adjacent units have excitation signals, the PMUT film deforms up and down in the Z direction and generates vibrations.
  • PMUT piezoelectric micromachined ultrasonic transducer
  • the vibration in the Z direction will also propagate along the X and Y directions on the horizontal plane perpendicular to the Z direction. That is, when a PMUT unit vibrates, the adjacent units will be disturbed by the vibration and will also vibrate at a lower amplitude, affecting normal use and causing mutual interference.
  • CMOS complementary metal oxide semiconductor
  • image sensor processes are all aimed at better electrical or optical isolation.
  • the requirements for acoustic isolation are very different.
  • the process of deep trenches to reduce acoustic crosstalk is mainly to cut off the channel for mechanical wave propagation, reduce coupling and increase damping.
  • CMUT capacitive micromechanical ultrasonic transducer
  • CMOS complementary metal-oxide-semiconductor
  • the back of the second wafer is a silicon substrate and a thin layer of silicon oxide, and the process steps related to the deep groove can be directly performed.
  • CMP Chemical Mechanical Polishing
  • the complexity of making deep grooves is relatively high.
  • the main reason is that there are piezoelectric materials and their upper and lower metal materials above the silicon mechanical layer.
  • the thickness of the piezoelectric material plus its upper/lower metal layers generally reaches 1.5-3.5 microns ( ⁇ m). It is relatively difficult to form a deep groove with a high aspect ratio through this layer of material.
  • the present disclosure provides a deep trench isolation method and an ultrasonic transducer for reducing acoustic crosstalk of an ultrasonic transducer, wherein the deep trench isolation method solves the problem that the current process of deep trench isolation for thinner materials is relatively difficult.
  • a deep trench isolation method for reducing acoustic crosstalk of an ultrasonic transducer comprising a CMOS unit, at least one PMUT unit being arranged on the CMOS unit, all PMUT units sharing a PMUT substrate, at least one cavity being arranged in the PMUT substrate, and a mechanical layer and a piezoelectric stack being arranged in sequence on the PMUT substrate covering the cavity, the deep trench isolation method comprising the following steps:
  • the piezoelectric stack is formed on the mechanical layer in the area isolated by the deep groove by deposition
  • a contact hole is formed by etching from the surface of the piezoelectric stack to the surface of the mechanical layer around the cavity, and Etching is performed from the surface of the mechanical layer in the contact hole into the PMUT substrate to form at least one deep groove.
  • the piezoelectric stack includes a lower metal layer, a piezoelectric layer and an upper metal layer; in step S2, the deep groove pre-setting process specifically includes the following steps:
  • step S3 the deep trench post-process specifically includes the following steps:
  • the preset thickness is 2-5 ⁇ m.
  • step S207 and the step S307 both include the following steps:
  • the damping material is porous oxide or porous plastic.
  • a damping material is deposited by plasma chemical vapor deposition, so that the deep groove is filled with the damping material, and a closed vacuum hole is formed in the deep groove.
  • the process of melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate specifically includes: melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate, and the back side of the mechanical layer is oxidized at the same time to form an oxide layer between the mechanical layer and the PMUT substrate.
  • the cross section of the deep groove is a circular ring or a polygonal ring.
  • the present disclosure also proposes an ultrasonic transducer, comprising a CMOS unit, wherein at least one PMUT unit is arranged on the CMOS unit, and all PMUT units share a PMUT substrate, wherein at least one cavity is arranged on the surface of the PMUT substrate toward the inside of the PMUT substrate, and a mechanical layer and a piezoelectric stack are arranged in sequence on the PMUT substrate to cover the cavity.
  • the size of the PMUT unit is smaller than the preset size
  • the area of the PMUT unit is smaller than the first preset area
  • the area of the cavity is larger than the second preset area
  • a deep groove is provided around the cavity from the surface of the mechanical layer to the inside of the PMUT substrate, and the deep groove is filled with damping material;
  • the size of the PMUT unit is greater than or equal to a preset size
  • the area of the PMUT unit is greater than or equal to a first preset area
  • the area of the cavity is less than or equal to a second preset area
  • one or more deep grooves are formed around the cavity from the surface of the mechanical layer to the PMUT substrate, and a damping layer is formed on the bottom and side walls of the deep grooves.
  • the present disclosure provides a deep trench isolation method and an ultrasonic transducer for reducing acoustic crosstalk of an ultrasonic transducer; compared with the prior art, the deep trench isolation method has the following beneficial effects:
  • the present invention uses different methods to make deep groove processes according to different PMUT unit sizes, which solves the problem that it is difficult to make deep grooves on thinner materials under different conditions.
  • the method is simple and effective.
  • deep grooves are set between PMUT units on the CMOS unit in the ultrasonic transducer for isolation, which effectively reduces the acoustic crosstalk of the ultrasonic transducer. Disturbance.
  • chemical mechanical polishing is used after re-deposition to remove the filling medium on the silicon surface, so that the lower metal electrode material of the piezoelectric material can be deposited.
  • the damping material is filled.
  • the outside of the wider deep groove is air. This Si/damping material/air interface can significantly attenuate mechanical waves.
  • Chemical mechanical polishing is used after re-deposition to remove the filling medium on the silicon surface, so that the lower metal electrode material of the piezoelectric material can be deposited.
  • the damping material is deposited by plasma chemical vapor deposition at low temperature.
  • This deposition method has a fast deposition speed at the top of the deep groove and can quickly seal the groove, leaving a vacuum hole in the middle or bottom of the deep groove.
  • This technology cleverly forms a Si/damping material/air/damping material/Si interface structure, which can significantly reduce the propagation of ultrasonic waves in the deep groove.
  • FIG1 is a schematic diagram of a deep trench pre-setting process structure of a deep trench isolation method for reducing acoustic crosstalk of an ultrasonic transducer provided by the present disclosure
  • FIG2 is a schematic diagram of a deep trench post-process structure of a deep trench isolation method for reducing acoustic crosstalk of an ultrasonic transducer provided by the present disclosure
  • FIG3 is a schematic diagram of a PMUT unit structure of an ultrasonic transducer provided by the present disclosure that introduces deep trench isolation;
  • FIG4 is a schematic diagram of the structure of three PMUT units of an ultrasonic transducer provided by the present disclosure that introduces deep trench isolation;
  • FIG5 is a schematic diagram of a top view of a 3 ⁇ 3 PMUT unit array with deep trench isolation when the unit size is small for an ultrasonic transducer provided by the present disclosure
  • FIG6 is a schematic diagram of a top view of a 3 ⁇ 3 PMUT unit array with deep trench isolation when the unit size of an ultrasonic transducer provided by the present disclosure is large;
  • FIG7 is a schematic diagram of a top view of a 3 ⁇ 3 PMUT unit array with deep trench isolation of different shapes when the unit size of an ultrasonic transducer provided by the present disclosure is large;
  • FIG8 is a schematic diagram of a top view of a double deep groove isolation structure of an ultrasonic transducer provided by the present disclosure
  • FIG9 is a schematic diagram of the longitudinal cross-sectional structure of a deep groove after plasma chemical vapor deposition of a damping material provided by the present disclosure.
  • a deep trench isolation method for reducing acoustic crosstalk of an ultrasonic transducer includes a CMOS unit, a PMUT unit is provided on the CMOS unit, and the PMUT unit includes a PMUT substrate 1.
  • a cavity 2 is provided in the PMUT substrate 1, and a mechanical layer 4 and a piezoelectric stack 5 are sequentially provided on the PMUT substrate 1 to cover the cavity 2.
  • the deep trench isolation method includes the following steps:
  • the piezoelectric stack is then formed on the mechanical layer in the area isolated by the deep trenches through deposition.
  • the piezoelectric stack includes a lower metal layer, a piezoelectric layer, and an upper metal layer;
  • step S2 the deep groove pre-setting process specifically includes the following steps:
  • the material of the piezoelectric layer may be PZT or aluminum nitride (AlN).
  • the preset thickness may be 4 ⁇ m.
  • the step S207 includes the following steps:
  • a passivation layer is formed to cover the piezoelectric stack, the mechanical layer and the bottom and sidewall of the contact hole, i.e. the "passivation layer” step shown in Figure 1.
  • Different methods are used to make deep groove processes according to different situations, which solves the problem that it is difficult to make deep grooves for thinner materials under different situations, and the method is simple and has good effect.
  • the damping material 31 is a porous plastic.
  • the edge of the deep groove is porous plastic, and a vacuum hole is provided in the middle of the groove.
  • the deposition method is to deposit porous plastic by plasma chemical vapor deposition at a low temperature. This deposition method has a fast deposition speed at the top of the deep groove, can quickly seal, and leaves a vacuum hole in the middle or bottom of the deep groove. This technology cleverly forms a Si/porous plastic/air/porous plastic/Si interface structure, which can significantly reduce the propagation of ultrasonic waves in the deep groove.
  • step S204 the damping material 31 is deposited by plasma chemical vapor deposition, so that after the deep groove 3 is filled with the damping material 31, a closed vacuum hole 32 is formed in the deep groove 3.
  • the temperature of the plasma chemical vapor deposition damping material 31 is 250-350°C.
  • the damping material 31 is a porous oxide (such as SiO 2 ), and during deposition, the edge of the deep groove is the porous oxide, and a vacuum hole 32 is provided in the middle of the groove.
  • the deposition method in step S204 is to deposit SiO 2 by plasma chemical vapor deposition at low temperature. This deposition method has a fast deposition speed at the top of the deep groove, which can quickly seal the groove, leaving a vacuum hole in the middle or bottom of the deep groove. This technology cleverly forms a Si/SiO 2 /air/SiO 2 /Si interface structure, which can significantly reduce the propagation of ultrasonic waves in the deep groove.
  • step S204 plasma chemical vapor deposition is used to deposit the damping material 31, so that after the deep groove is filled with the damping material, a closed vacuum hole is formed in the deep groove; illustratively, SiO 2 is deposited by plasma chemical vapor deposition at a low temperature.
  • This deposition method has a fast deposition speed at the top of the deep groove and can quickly seal it, leaving a vacuum hole in the middle or bottom of the deep groove.
  • This technology cleverly forms a Si/SiO 2 /air/SiO 2 /Si interface structure, which can significantly reduce the propagation of ultrasonic waves in the deep groove.
  • the present disclosure also provides an ultrasonic transducer, comprising a CMOS unit, wherein the CMOS unit is provided with a A PMUT unit, the PMUT unit comprises a PMUT substrate 1, a cavity 2 is provided on the surface of the PMUT substrate 1 and is recessed into the PMUT substrate 1, a mechanical layer 4 and a piezoelectric stack 5 are sequentially provided on the PMUT substrate 1 to cover the cavity 2, when the size of the PMUT unit is smaller than a preset size, the area of the PMUT unit is smaller than a first preset area, and the area of the cavity is larger than a second preset area, a deep groove 3 is provided around the cavity and is recessed from the surface of the mechanical layer into the PMUT substrate 1, and the deep groove 3 is filled with damping material.
  • the ultrasonic transducer includes a CMOS unit, a PMUT unit is provided on the CMOS unit, and the PMUT unit includes a PMUT substrate 1.
  • a cavity 2 is provided in the PMUT substrate 1 (i.e., a cavity 2 is provided in one PMUT unit).
  • a mechanical layer 4 and a piezoelectric stack 5 are sequentially provided on the PMUT substrate 1 covering the cavity 2.
  • the deep trench isolation method includes the following steps:
  • etching is performed around the cavity from the surface of the piezoelectric stack to the surface of the mechanical layer to form a contact hole, and etching is performed from the surface of the mechanical layer in the contact hole to the PMUT substrate to form at least one deep groove.
  • the piezoelectric stack includes a lower metal layer, a piezoelectric layer, and an upper metal layer;
  • step S3 the deep trench post-process specifically includes the following steps:
  • Photolithography and etching are performed in sequence in the PMUT substrate to form a deep trench, namely the “deep trench photolithography, deep trench etching” steps shown in FIG. 2 .
  • the preset thickness may be 3 ⁇ m.
  • the step S307 includes the following steps:
  • a passivation layer is formed to cover the piezoelectric stack, the mechanical layer and the bottom and sidewall of the contact hole, i.e. the "passivation layer” step shown in Figure 2.
  • Different methods are used to make deep groove processes according to different situations, which solves the problem that it is difficult to make deep grooves for thinner materials under different situations, and the method is simple and has good effect.
  • step S306 after the damping material is coated or deposited, only the deep trench filling medium/coating medium is retained in the deep trench area by photolithography. Through reasonable design, the acoustic crosstalk can be further reduced.
  • the process of melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate specifically includes: melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate, and the back side of the mechanical layer is oxidized at the same time to form an oxide layer between the mechanical layer and the PMUT substrate.
  • the cross section of the deep groove is a circular ring.
  • the cross section of the deep groove is a polygonal ring; illustratively, the polygonal ring may be a square ring, a hexagonal ring, an octagonal ring, etc.
  • the present disclosure also proposes an ultrasonic transducer, including a CMOS unit, on which a PMUT unit is provided, wherein the PMUT unit includes a PMUT substrate 1, a surface of the PMUT substrate 1 facing the PMUT A cavity 2 is formed in the substrate 1, and a mechanical layer 4 and a piezoelectric stack 5 are sequentially formed on the PMUT substrate 1 to cover the cavity.
  • a deep groove 3 is provided around the cavity 2 and is recessed from the surface of the mechanical layer 4 to the PMUT substrate 1, and a damping layer is formed on the bottom and side walls of the deep groove 3.
  • the ultrasonic transducer includes a CMOS unit, and three PMUT units are provided on the CMOS unit.
  • the three PMUT units are connected, and the three PMUT units share a PMUT substrate 1.
  • Three cavities 2 are provided in the PMUT substrate 1 (i.e., one PMUT unit has one cavity 2 corresponding to it), and a mechanical layer 4 and a piezoelectric stack 5 are sequentially provided on the PMUT substrate 1 covering the cavity 2.
  • the deep trench isolation method includes the following steps:
  • the piezoelectric stack is then formed on the mechanical layer in the area isolated by the deep trenches through deposition.
  • the piezoelectric stack includes a lower metal layer, a piezoelectric layer, and an upper metal layer;
  • step S2 the deep groove pre-setting process specifically includes the following steps:
  • etching is performed from the surface of the upper metal layer to the surface of the mechanical layer to form a contact hole on the deep groove, which is the “piezoelectric lithography” step shown in FIG1 .
  • the preset thickness is 4 ⁇ m.
  • the step S207 includes the following steps:
  • a passivation layer is formed to cover the piezoelectric stack, the mechanical layer and the bottom and sidewall of the contact hole, i.e. the "passivation layer” step shown in Figure 1.
  • Different methods are used to make deep groove processes according to different situations, which solves the problem that it is difficult to make deep grooves for thinner materials under different situations, and the method is simple and has good effect.
  • the damping material 31 is a porous plastic
  • the edge of the deep groove is porous plastic
  • a vacuum hole 32 is provided in the middle of the groove.
  • the deposition method in step S204 is plasma chemical vapor deposition of porous plastic. This deposition method has a fast deposition speed at the top of the deep groove, can quickly seal, and leaves a vacuum hole in the middle or bottom of the deep groove. This technology cleverly forms a Si/porous plastic/air/porous plastic/Si interface structure, which can significantly reduce the propagation of ultrasonic waves in the deep groove.
  • step S204 the damping material is deposited by plasma chemical vapor deposition, so that after the damping material is filled in the deep groove, a closed vacuum hole is formed in the deep groove.
  • the temperature of the plasma chemical vapor deposition damping material is 250-350°C.
  • the damping material 31 is a porous oxide (such as SiO 2 ), and during deposition, the edge of the deep groove is a porous oxide, and a vacuum hole is provided in the middle of the groove.
  • the deposition method in step S204 is plasma chemical vapor deposition of SiO 2 , which has a fast deposition speed at the top of the deep groove, can quickly seal, and leaves a vacuum hole in the middle or bottom of the deep groove. This technology cleverly forms a Si/SiO 2 /air/SiO 2 /Si interface structure, which can significantly reduce the propagation of ultrasonic waves in the deep groove.
  • a damping material is deposited by plasma chemical vapor deposition, so that after the deep groove is filled with the damping material, a closed vacuum hole is formed in the deep groove; illustratively, SiO 2 is deposited by plasma chemical vapor deposition.
  • This deposition method has a fast deposition speed at the top of the deep groove and can quickly seal it, leaving a vacuum hole in the middle or bottom of the deep groove.
  • This technology cleverly forms a Si/SiO 2 /air/SiO 2 /Si interface structure, which can significantly reduce the propagation of ultrasonic waves in the deep groove.
  • the present disclosure also proposes an ultrasonic transducer, including a CMOS unit, on which three PMUT units are arranged, and the three PMUT units share a PMUT substrate 1, and three cavities 2 are recessed from the surface of the PMUT substrate 1 into the PMUT substrate 1 (that is, one cavity 2 is correspondingly arranged in one PMUT unit), and a mechanical layer 4 and a piezoelectric stack 5 are sequentially arranged on the PMUT substrate 1 to cover the cavity 2.
  • the size of the PMUT unit is smaller than a preset size
  • the area of the PMUT unit is smaller than a first preset area
  • the area of the cavity 2 is larger than a second preset area
  • three deep grooves 3 are recessed around the cavity 2 from the surface of the mechanical layer 4 into the PMUT substrate 1, and the deep grooves 3 are filled with damping material, and the three PMUT units are adjacent, and one deep groove 3 is shared between adjacent PMUT units.
  • the ultrasonic transducer includes a CMOS unit, three PMUT units are provided on the CMOS unit, and the three PMUT units are connected.
  • the three PMUT units share a PMUT substrate 1, and three cavities 2 are provided in the PMUT substrate 1 (i.e., one PMUT unit has one cavity 2 corresponding to it), and a mechanical layer 4 and a piezoelectric stack 5 are sequentially provided on the PMUT substrate 1 covering the cavity 2.
  • the deep trench isolation method includes the following steps:
  • etching is performed around the cavity from the surface of the piezoelectric stack to the surface of the mechanical layer to form a contact hole, and etching is performed from the surface of the mechanical layer in the contact hole to the PMUT substrate to form at least one deep groove.
  • the piezoelectric stack includes a lower metal layer, a piezoelectric layer, and an upper metal layer;
  • step S3 the deep trench post-process specifically includes the following steps:
  • the preset thickness is 3 ⁇ m.
  • the step S307 includes the following steps:
  • a passivation layer is formed to cover the piezoelectric stack, the mechanical layer and the bottom and sidewall of the contact hole, i.e. the "passivation layer” step shown in Figure 2.
  • Different methods are used to make deep groove processes according to different situations, which solves the problem that it is difficult to make deep grooves for thinner materials under different situations, and the method is simple and has good effect.
  • step S306 after the damping material is coated or deposited, photolithography is performed to retain only the deep trench filling medium/coating medium in the deep trench area. Through reasonable design, the acoustic crosstalk can be further reduced.
  • the process of melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate specifically includes: melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate, and the back side of the mechanical layer is oxidized at the same time to form an oxide layer between the mechanical layer and the PMUT substrate.
  • the cross section of the deep groove is a circular ring.
  • the cross section of the deep groove is a polygonal ring; illustratively, the polygonal ring It can be a square ring, a hexagonal ring, an octagonal ring, etc.
  • the present disclosure also proposes an ultrasonic transducer, including a CMOS unit, wherein at least one (e.g., nine) PMUT units are arranged on the CMOS unit, and all PMUT units share a PMUT substrate 1, wherein at least one cavity 2 is recessed into the PMUT substrate 1 on the surface of the PMUT substrate 1 (i.e., one cavity 2 is correspondingly arranged in one PMUT unit), and a mechanical layer 4 and a piezoelectric stack 5 are sequentially arranged on the PMUT substrate 1 to cover the cavity 2.
  • CMOS unit wherein at least one (e.g., nine) PMUT units are arranged on the CMOS unit, and all PMUT units share a PMUT substrate 1, wherein at least one cavity 2 is recessed into the PMUT substrate 1 on the surface of the PMUT substrate 1 (i.e., one cavity 2 is correspondingly arranged in one PMUT unit), and a mechanical layer 4 and a piezoelectric stack 5 are sequentially arranged on the PMUT substrate 1 to
  • a deep groove 3 is provided around the cavity 2, from the surface of the mechanical layer 4 to the inside of the PMUT substrate 1, a damping layer is formed on the bottom and side walls of the deep groove 3, three PMUT units are adjacent, and one deep groove 3 is shared between adjacent PMUT units.
  • the ultrasonic transducer includes a CMOS unit, and nine PMUT units are arranged on the CMOS unit, and the nine PMUT units are distributed in a 3 ⁇ 3 array. All PMUT units share a PMUT substrate 1, and the grid-like pattern is a deep groove 3 structure.
  • the black circle is a cavity 2
  • the white circle is a top layer 51 (such as an upper metal layer) of the piezoelectric stack of the PMUT unit.
  • the deep groove 3 grid completely surrounds the cavity 2 and the PMUT unit, and is completely isolated from adjacent PMUT units.
  • the deep groove isolation method includes the following steps:
  • the piezoelectric stack is then formed on the mechanical layer in the area isolated by the deep trenches through deposition.
  • the piezoelectric stack includes a lower metal layer, a piezoelectric layer, and an upper metal layer;
  • step S2 the deep groove pre-setting process specifically includes the following steps:
  • etching is performed from the surface of the upper metal layer to the surface of the mechanical layer to form a contact hole on the deep groove, which is the “piezoelectric lithography” step shown in FIG1 .
  • the preset thickness is 4 ⁇ m.
  • the step S207 includes the following steps:
  • a passivation layer is formed to cover the piezoelectric stack, the mechanical layer and the bottom and sidewall of the contact hole, i.e. the "passivation layer” step shown in Figure 1.
  • Different methods are used to make deep groove processes according to different situations, which solves the problem that it is difficult to make deep grooves for thinner materials under different situations, and the method is simple and has good effect.
  • the damping material 31 is a porous plastic.
  • the edge of the deep groove is porous plastic, and a vacuum hole is provided in the middle of the groove.
  • the deposition method is plasma chemical vapor deposition of porous plastic. This deposition method has a fast deposition speed at the top of the deep groove, can quickly seal, and leaves a vacuum hole in the middle or bottom of the deep groove.
  • This technology cleverly forms a Si/porous plastic/air/porous plastic/Si interface structure, which can significantly reduce the propagation of ultrasonic waves in the deep groove.
  • step S204 the damping material 31 is deposited by plasma chemical vapor deposition, so that after the deep groove 3 is filled with the damping material 31, a closed vacuum hole 32 is formed in the deep groove 3.
  • the temperature of the plasma chemical vapor deposition damping material is 250-300°C.
  • the damping material 31 is a porous oxide (such as SiO 2 ), and during deposition, the edge of the deep groove is a porous oxide, and a vacuum hole 32 is provided in the middle of the groove.
  • the deposition method in step S204 is to deposit SiO 2 by plasma chemical vapor deposition at low temperature.
  • This deposition method has a fast deposition speed at the top of the deep groove, which can quickly seal the groove, leaving a vacuum hole in the middle or bottom of the deep groove.
  • This technology cleverly forms a Si/SiO 2 /air/SiO 2 /Si interface structure, which can significantly reduce the propagation of ultrasonic waves in the deep groove.
  • the damping material is deposited by plasma chemical vapor deposition.
  • the present disclosure also proposes an ultrasonic transducer, including a CMOS unit, on which nine PMUT units are arranged, and the nine PMUT units are distributed in a 3 ⁇ 3 array, all PMUT units share a PMUT substrate 1, the grid-like pattern is a deep groove 3 structure, the black circle is a cavity 2, and the white circle is a top layer 51 (such as an upper metal layer) of the piezoelectric stack 5 of the PMUT unit.
  • the deep groove 3 grid completely surrounds the cavity 2 and the PMUT unit, and is completely isolated from the adjacent PMUT unit.
  • a deep trench isolation method for reducing acoustic crosstalk of an ultrasonic transducer includes a CMOS unit, nine PMUT units are arranged on the CMOS unit, and the nine PMUT units are distributed in a 3 ⁇ 3 array. All PMUT units share a PMUT substrate 1.
  • a piezoelectric stack 5 is provided on the top of the PMUT unit. From a top-down perspective, a cavity 2 is provided around a top layer 51 (such as an upper metal layer) of the piezoelectric stack.
  • the deep trench isolation method includes the following steps:
  • etching is performed around the cavity from the surface of the piezoelectric stack to the surface of the mechanical layer to form a contact hole, and etching is performed from the surface of the mechanical layer in the contact hole to the PMUT substrate to form at least one deep groove.
  • the piezoelectric stack includes a lower metal layer, a piezoelectric layer, and an upper metal layer;
  • step S3 the deep trench post-process specifically includes the following steps:
  • the preset thickness is 3 ⁇ m.
  • the step S307 includes the following steps:
  • a passivation layer is formed to cover the piezoelectric stack, the mechanical layer and the bottom and sidewall of the contact hole, i.e. the "passivation layer” step shown in Figure 2.
  • Different methods are used to make deep groove processes according to different situations, which solves the problem that it is difficult to make deep grooves for thinner materials under different situations, and the method is simple and has good effect.
  • step S306 after the damping material is coated or deposited, photolithography is performed to retain only the deep trench filling medium/coating medium in the deep trench area. Through reasonable design, the acoustic crosstalk can be further reduced.
  • the process of melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate specifically includes: melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate, and the back side of the mechanical layer is oxidized at the same time to form an oxide layer between the mechanical layer and the PMUT substrate.
  • the cross section of the deep groove is a circular ring.
  • the cross section of the deep groove is a polygonal ring; illustratively, the polygonal ring It can be a square ring, a hexagonal ring, an octagonal ring, etc.
  • the present disclosure also proposes an ultrasonic transducer, including a CMOS unit, on which nine PMUT units are arranged, all of which share a PMUT substrate 1, a piezoelectric stack 5 is arranged on the top of the PMUT unit, and a cavity 2 is arranged around a top layer 51 (such as an upper metal layer) of the piezoelectric stack when viewed from a top view.
  • CMOS unit on which nine PMUT units are arranged, all of which share a PMUT substrate 1
  • a piezoelectric stack 5 is arranged on the top of the PMUT unit
  • a cavity 2 is arranged around a top layer 51 (such as an upper metal layer) of the piezoelectric stack when viewed from a top view.
  • a deep groove 3 is provided around the cavity 2 and from the surface of the piezoelectric stack 5, and an independent closed deep groove 3 is formed near the cavity 2, and the deep groove 3 only isolates the cavity 2 and the vibrating device structure above it.
  • a deep trench isolation method for reducing acoustic crosstalk of an ultrasonic transducer includes a CMOS unit, nine PMUT units are arranged on the CMOS unit, and the nine PMUT units are distributed in a 3 ⁇ 3 array. All PMUT units share a PMUT substrate 1.
  • a piezoelectric stack 5 is provided on the top of the PMUT substrate 1. From a top view angle, a cavity 2 is provided around a top layer 51 (such as an upper metal layer) of the piezoelectric stack.
  • the deep trench isolation method includes the following steps:
  • etching is performed around the cavity from the surface of the piezoelectric stack to the surface of the mechanical layer to form a contact hole, and etching is performed from the surface of the mechanical layer in the contact hole to the PMUT substrate to form at least one deep groove.
  • the piezoelectric stack includes a lower metal layer, a piezoelectric layer, and an upper metal layer;
  • step S3 the deep trench post-process specifically includes the following steps:
  • the preset thickness is 3 ⁇ m.
  • the step S307 includes the following steps:
  • a passivation layer is formed to cover the piezoelectric stack, the mechanical layer and the bottom and sidewall of the contact hole, i.e. the "passivation layer” step shown in Figure 2.
  • Different methods are used to make deep groove processes according to different situations, which solves the problem that it is difficult to make deep grooves for thinner materials under different situations, and the method is simple and has good effect.
  • step S306 after the damping material is coated or deposited, photolithography is performed to retain only the deep trench filling medium/coating medium in the deep trench area. Through reasonable design, the acoustic crosstalk can be further reduced.
  • the process of melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate specifically includes: melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate, and the back side of the mechanical layer is oxidized at the same time to form an oxide layer between the mechanical layer and the PMUT substrate.
  • the cross section of the deep groove is a circular ring.
  • the cross section of the deep groove is a polygonal ring; illustratively, the polygonal ring It can be a square ring, a hexagonal ring, an octagonal ring, etc.
  • the present disclosure also proposes an ultrasonic transducer, including a CMOS unit, on which nine PMUT units are arranged, all of which share a PMUT substrate 1, a piezoelectric stack 5 is arranged on the top of the PMUT unit, and a cavity 2 is arranged around a top layer 51 (such as an upper metal layer) of the piezoelectric stack when viewed from a top view.
  • CMOS unit on which nine PMUT units are arranged, all of which share a PMUT substrate 1
  • a piezoelectric stack 5 is arranged on the top of the PMUT unit
  • a cavity 2 is arranged around a top layer 51 (such as an upper metal layer) of the piezoelectric stack when viewed from a top view.
  • a deep groove 3 is surrounded by the cavity 2 and from the surface of the piezoelectric stack 5.
  • An independent closed deep groove 3 is formed near the cavity 2.
  • the deep groove 3 only isolates the cavity 2 and the vibrating device structure above it.
  • the shape of the deep groove 3 can be a quadrilateral ring, a hexagonal ring or an octagonal ring, etc.
  • a deep trench isolation method for reducing acoustic crosstalk of an ultrasonic transducer includes a CMOS unit, and nine PMUT units are arranged on the CMOS unit, and the nine PMUT units are distributed in a 3 ⁇ 3 array. All PMUT units share a PMUT substrate 1.
  • a piezoelectric stack 5 is provided on the top of the PMUT unit. When viewed from a top view, a cavity 2 is provided around a top layer 51 (such as an upper metal layer) of the piezoelectric stack.
  • the deep trench isolation method includes the following steps:
  • etching is performed around the cavity from the surface of the piezoelectric stack to the surface of the mechanical layer to form a contact hole, and etching is performed from the surface of the mechanical layer in the contact hole to the PMUT substrate to form at least one deep groove.
  • the piezoelectric stack includes a lower metal layer, a piezoelectric layer, and an upper metal layer;
  • step S3 the deep trench post-process specifically includes the following steps:
  • the preset thickness is 3 ⁇ m.
  • the step S307 includes the following steps:
  • a passivation layer is formed to cover the piezoelectric stack, the mechanical layer and the bottom and sidewall of the contact hole, i.e. the "passivation layer” step shown in Figure 2.
  • Different methods are used to make deep groove processes according to different situations, which solves the problem that it is difficult to make deep grooves for thinner materials under different situations, and the method is simple and has good effect.
  • step S306 after the damping material is coated or deposited, photolithography is performed to retain only the deep trench filling medium/coating medium in the deep trench area. Through reasonable design, the acoustic crosstalk can be further reduced.
  • the process of melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate specifically includes: melt bonding to cover the cavity and form a mechanical layer on the PMUT substrate, and the back side of the mechanical layer is oxidized at the same time to form an oxide layer between the mechanical layer and the PMUT substrate.
  • the cross section of the deep groove is a circular ring.
  • the cross section of the deep groove is a polygonal ring; illustratively, the polygonal ring may be a square ring, a hexagonal ring, an octagonal ring, etc.
  • the present disclosure also proposes an ultrasonic transducer, including a CMOS unit, on which nine PMUT units are arranged, all of which share a PMUT substrate 1, a piezoelectric stack 5 is arranged on the top of the PMUT unit, and a cavity 2 is arranged around a top layer 51 (such as an upper metal layer) of the piezoelectric stack 5 when viewed from a top view.
  • CMOS unit on which nine PMUT units are arranged, all of which share a PMUT substrate 1
  • a piezoelectric stack 5 is arranged on the top of the PMUT unit
  • a cavity 2 is arranged around a top layer 51 (such as an upper metal layer) of the piezoelectric stack 5 when viewed from a top view.
  • a deep groove 3 is formed around the cavity 2 and from the surface of the piezoelectric stack 5, and an independent closed deep groove 3 is formed near the cavity 2.
  • the deep groove 3 only isolates the cavity 2 and the vibrating device structure above it.
  • the shape of the deep groove 3 can be a quadrilateral ring, a hexagonal ring or an octagonal ring, etc.;
  • the anti-interference design is not limited to a single deep groove. If the unit area allows, a double groove or even a multi-groove design can also be made.
  • the discontinuous double groove isolation schematic diagram shown in Figure 8 in the unit layout, areas A, B, C, and D already have related unit structures, such as vertical connections of three-dimensional structures, or metal wiring, etc. Double groove isolation can stagger these areas with a single groove, and the other deep groove can be staggered and complementary to ensure that at least one deep groove is on the lateral path of the mechanical wave, which plays a role in reducing interference.
  • the preset size refers to the minimum lateral size of the PMUT unit when the double deep groove isolation process can be adopted; the first preset area refers to the minimum area of the PMUT unit when the double deep groove isolation process can be adopted; the second preset area refers to the maximum area of the cavity in the PMUT unit when the double deep groove isolation process can be adopted.

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  • Mechanical Engineering (AREA)
  • Transducers For Ultrasonic Waves (AREA)

Abstract

本公开涉及阻断干扰领域，公开了一种减少超声换能器声串扰的深槽隔离方法及超声换能器，超声换能器包括CMOS单元，其上设有至少一个PMUT单元，所有PMUT单元共用PMUT衬底，PMUT单元设有空腔，深槽隔离方法包括步骤：当PMUT单元的尺寸和面积均小于其相应的预设值、及空腔的面积大于其预设值时，先围绕空腔、自机械层向PMUT衬底内刻蚀深槽；再在深槽隔离出的区域内的机械层上淀积压电叠层；反之，先在机械层上淀积压电叠层；再围绕空腔、自压电叠层表面向机械层表面刻蚀接触孔，并自接触孔内的机械层表面向PMUT衬底内刻蚀至少一个深槽。本公开通过在PMUT单元之间设置深槽阻碍超声波横向传播，可有效减少超声换能器的声串扰。

Description

一种减少超声换能器声串扰的深槽隔离方法及超声换能器
优先权
本PCT专利申请要求申请日为2022年10月31日、申请号为202211342448.2的中国专利的优先权，本PCT专利申请结合了上述专利的技术方案。
技术领域
本公开涉及阻断干扰技术领域，具体为一种减少超声换能器声串扰的深槽隔离方法及超声换能器。
背景技术
医学超声扫描的发展需要越来越高的图像分辨率，体内超声检查则要求超声探头不断小型化，超声探头小型化，高密度化会遇到很多挑战，换能器单元彼此的声串扰就是其中之一，声串扰定义为由于相邻元件的声学振动而在受测元件(本身没有激励)上产生的电压，或声学振幅，超声换能器阵列，有许多压电微机械超声换能器(Piezoelectric Micromachined Ultrasonic Transducer，PMUT)单元排成行与列，组成阵列，即PMUT单元会有多个邻近单元，当相邻的单元有激励信号时，PMUT薄膜在Z方向上下形变，产生振动，在固体弹性材料中，Z方向的振动，也会沿着垂直于Z方向的水平面上的X，Y方向传播，也即，一个PMUT单元振动，相邻的单元受振动的干挠，也会出现较低幅度的振动，影响正常的使用,其会产生相互干扰。
普通互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)高压或图像传感器工艺中所用的深槽(Deep Trench)都以较好的电学，或光学隔离为目的，声学隔离的要求则很不一样，降低声串扰的深槽的工艺制程主要是截断机械波传播的通道，降低耦合，增加阻尼。
在由电容式微机械超声换能器(Capacitive micromechanical ultrasonic transducer，CMUT)和CMOS构成的三维架构(具体可通过把CMUT做在CMOS芯片上方形成)上制造降低声串扰的深槽，其工艺相对简单，直接，一般是在减合，减薄后，第二晶圆背面就是硅衬底及氧化硅薄层，可直接执行深槽相关的工艺步骤，同时，不管空腔与单元面积的相对大小，均较容易做深槽的布局(layout)，以及光刻，腐蚀，深槽填充，化 学机械抛光(Chemical Mechanical Polishing，CMP)等后续工艺，如果能够满足特定声串扰的规格要求，甚至只要在硅衬底上进行较浅的深槽腐蚀即可，不需要腐蚀穿透整个硅机械层，上述由CMUT和CMOS构成的三维架构也更容易采用双深槽隔离，进一步提升隔离效果。
对于由PMUT和CMOS构成的三维架构(具体可通过把PMUT做在CMOS芯片上方形成)，制作深槽的复杂性相对较高，其主要原因是硅机械层上方有压电材料及其上层及底层金属等材料，压电材料加上其上/下层金属的厚度一般会达到1.5-3.5微米(μm)，透过这层材料，要形成高深宽比(Aspect Ratio)的深槽，工艺相对比较难，在此同时，PZT(锆钛酸铅，Pb(ZrTi)O3)压电材料，光刻腐蚀形成很小尺寸的图形也不容易，这就进一步增加了深槽工艺的难度，因此提出一种减少超声换能器声串扰的深槽隔离方法及超声换能器。
发明内容
针对现有技术的不足，本公开提供了一种减少超声换能器声串扰的深槽隔离方法及超声换能器，其中该深槽隔离方法解决了目前对于较薄材料做深槽隔离方法工艺相对较难的问题。
为实现上述目的，本公开提供如下技术方案：
一种减少超声换能器声串扰的深槽隔离方法，所述超声换能器包括CMOS单元，所述CMOS单元上设有至少一个PMUT单元，所有PMUT单元共用包括PMUT衬底，所述PMUT衬底内设有至少一个空腔，覆盖所述空腔、所述PMUT衬底上依次设有机械层和压电叠层，所述深槽隔离方法包括以下步骤：
S1、获取所述PMUT单元的尺寸和面积、以及所述空腔的面积；
S2、当所述PMUT单元的尺寸小于预设尺寸、所述PMUT单元的面积小于第一预设面积、以及所述空腔的面积大于第二预设面积时，进行深槽先设流程：
先围绕所述空腔、自所述机械层向所述PMUT衬底内刻蚀，形成深槽；
然后经淀积，在所述深槽隔离出的区域内的所述机械层上形成所述压电叠层；
S3、当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔的面积小于或等于第二预设面积时，进行深槽后设流程：
先在所述机械层上淀积，形成所述压电叠层；
然后围绕所述空腔，自所述压电叠层表面向所述机械层表面刻蚀，形成接触孔，并 自所述接触孔内的所述机械层表面向所述PMUT衬底内刻蚀，形成至少一个深槽。
作为本公开再进一步的方案，所述压电叠层包括下金属层、压电层和上金属层；所述步骤S2中，所述深槽先设流程具体包括以下步骤：
S201、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；
S202、经淀积，在所述机械层上形成掩膜氧化层；
S203、掩膜下，围绕所述空腔、自所述掩膜氧化层向所述PMUT衬底内依次进行光刻和腐蚀，形成所述深槽；
S204、去除所述掩膜氧化层后、淀积阻尼材料，使所述深槽内充满阻尼材料、并在所述PMUT衬底的一表面上形成阻尼层；
S205、经抛光处理，去除所述阻尼层；
S206、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；
S207、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，在所述深槽上形成接触孔；
所述步骤S3中，所述深槽后设流程具体包括以下步骤：
S301、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；
S302、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；
S303、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，形成接触孔；
S304、经淀积，覆盖所述机械层和所述压电叠层，形成一掩膜氧化层；
S305、掩膜下，围绕所述空腔、自所述接触孔内的所述掩膜氧化层表面向所述PMUT衬底内依次进行光刻和腐蚀，形成所述至少一个深槽；
S306、去除所述掩膜氧化层后、涂敷或淀积阻尼材料，覆盖所述深槽的底部和侧壁、所述机械层以及所述压电叠层，形成阻尼层；
S307、经抛光处理、去除多余的阻尼层，保留所述深槽内的阻尼层。
进一步的，所述预设厚度为2-5μm。
在前述方案的基础上，所述步骤S207和所述步骤S307之后均包括步骤：
S408、在所述PMUT衬底背面形成一金属互连层；
S409、在所述PMUT衬底内沿第一方向形成金属布线层，并自所述金属布线层垂直所述第一方向形成金属引线孔，使所述金属布线层与所述金属互连层连接，所述第一方向为所述PMUT衬底的长度方向；
S410、贯穿所述压电层、所述下金属层和所述机械层并延伸至所述金属布线层表面，形成上金属层连接孔和下金属层连接孔；
S411、经淀积，覆盖所述压电叠层、所述机械层和所述接触孔的底部和侧壁，形成一钝化层。
进一步的，所述阻尼材料为多孔氧化物或多孔塑胶。
在前述方案的基础上，所述步骤S204中，采用等离子化学气相淀积阻尼材料，使所述深槽内被填充阻尼材料后,在所述深槽内形成有密闭的真空孔洞。
进一步的，所述经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，具体包括：经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，且所述机械层背面同时被氧化，在所述机械层和所述PMUT衬底之间形成一氧化层。
在前述方案的基础上，所述深槽的横截面呈圆形环或多边形环。
本公开还提出了一种超声换能器，包括CMOS单元，所述CMOS单元上设有至少一个PMUT单元，所有PMUT单元共用PMUT衬底，所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个空腔，覆盖所述空腔、在所述PMUT衬底上依次设有机械层和压电叠层，
当所述PMUT单元的尺寸小于预设尺寸、所述PMUT单元的面积小于第一预设面积、以及所述空腔的面积大于第二预设面积时，围绕所述空腔、自所述机械层表面向所述PMUT衬底内凹设有一个深槽，所述深槽内充满有阻尼材料；
当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔的面积小于或等于第二预设面积时，围绕所述空腔、自所述机械层表面向所述PMUT衬底内凹设有一个或多个深槽，所述深槽的底部和侧壁形成有阻尼层。
本公开提供了一种减少超声换能器声串扰的深槽隔离方法及超声换能器；与现有技术相比，该深槽隔离方法具备以下有益效果：
1、本公开，针对PMUT单元尺寸不同的情况来使用不用的方法做深槽工艺，解决了不同情况下对较薄材料做深槽较难的问题，而且方法简单，效果好，而且在超声换能器中CMOS单元上的PMUT单元之间设置深槽进行隔离，有效减少超声换能器的声串 扰。
2、本公开中，在进行再次淀积后采用化学机械抛光处理，去除硅表面的填充介质，从而可以淀积压电材料的下层金属电极材料，在形成深槽后，填充阻尼材料，较宽的深槽外面就是空气，这一Si/阻尼材料/空气界面能显著衰减机械波，在进行再次淀积后采用化学机械抛光处理，去除硅表面的填充介质，从而可以淀积压电材料的下层金属电极材料。
3、本公开中，通过于低温下等离子化学气相淀积阻尼材料，这一淀积方法在深槽顶端淀积速度较快，能够快速封口，在深槽中部或底部留下真空孔洞，这一技术巧妙地形成了Si/阻尼材料/空气/阻尼材料/Si界面结构，能显著减少超声波在深槽的传播。
4、本公开中，在填充高阻尼介质后再涂敷另一层介质，通过光刻，仅保留深槽填充介质与涂敷介质在深槽区域，设计合理，可以进一步降低声串扰。
附图说明
图1为本公开提供的一种减少超声换能器声串扰的深槽隔离方法的深槽先设流程结构示意图；
图2为本公开提供的一种减少超声换能器声串扰的深槽隔离方法的深槽后设流程结构示意图；
图3为本公开提供的一种超声换能器的引入深槽隔离的PMUT单元结构示意图；
图4为本公开提供的一种超声换能器的引入深槽隔离的三个PMUT单元结构示意图；
图5为本公开提供的一种超声换能器的小单元尺寸时，深槽隔离的3×3PMUT单元阵列俯视结构示意图；
图6为本公开提供的一种超声换能器的大单元尺寸时，深槽隔离的3×3PMUT单元阵列俯视结构示意图；
图7为本公开提供的一种超声换能器的大单元尺寸时，不同形状深槽隔离的3×3PMUT单元阵列俯视结构示意图；
图8为本公开提供的一种超声换能器的双深槽隔离俯视结构示意图；
图9为本公开提供的一种经等离子化学气相淀积阻尼材料后的深槽的纵截面结构示意图。
附图标记说明：
1、PMUT衬底；2、空腔；3、深槽；31、阻尼材料；32、真空孔洞；4、机械层；
5、压电叠层；51、压电叠层的顶层。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
实施例1
参照图1、图3，一种减少超声换能器声串扰的深槽隔离方法，所述超声换能器包括CMOS单元，所述CMOS单元上设有一个PMUT单元，所述PMUT单元包括PMUT衬底1，所述PMUT衬底1内设有一个空腔2，覆盖所述空腔2、所述PMUT衬底1上依次设有机械层4和压电叠层5，所述深槽隔离方法包括以下步骤：
S1、获取所述PMUT单元的尺寸和面积、以及所述空腔的面积；
S2、当所述PMUT单元的尺寸小于预设尺寸、所述PMUT单元的面积小于第一预设面积、以及所述空腔的面积大于第二预设面积时，进行深槽先设流程：
先围绕所述空腔、自所述机械层向所述PMUT衬底内刻蚀，形成深槽；
然后经淀积，在所述深槽隔离出的区域内的所述机械层上形成所述压电叠层。
在一些实施方式中，所述压电叠层包括下金属层、压电层和上金属层；
所述步骤S2中，所述深槽先设流程具体包括以下步骤：
S201、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；即图1中所示的“键合减薄”步骤。
S202、经淀积，在所述机械层上形成掩膜氧化层；即图1中所示的“淀积”步骤。
S203、掩膜下，围绕所述空腔、自所述掩膜氧化层向所述PMUT衬底内依次进行光刻和腐蚀，形成所述深槽；即图1中所示的“深槽光刻”步骤。
S204、去除所述掩膜氧化层后、淀积阻尼材料，使所述深槽内充满阻尼材料、并在所述PMUT衬底的一表面上形成阻尼层；即图1中所示的“再次淀积”步骤。
S205、经抛光处理，去除所述阻尼层；即图1中所示的“抛光”步骤。
S206、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；即图1中所示的“敷设材料”步骤。示例性的，压电层的材料可为PZT或氮化铝(AlN)。
S207、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，在所述深槽上形成 接触孔。即图1中的所示“压电光刻”步骤。
示例性的，所述预设厚度可为4μm。
在一些实施方式中，所述步骤S207之后包括步骤：
S408、在所述PMUT衬底背面形成一金属互连层；即图1中所示的“金属互连”步骤。
S409、在所述PMUT衬底内沿第一方向形成金属布线层，并自所述金属布线层垂直所述第一方向形成金属引线孔，使所述金属布线层与所述金属互连层连接，所述第一方向为所述PMUT衬底的长度方向；
S410、贯穿所述压电层、所述下金属层和所述机械层并延伸至所述金属布线层表面，形成上金属层连接孔和下金属层连接孔；
S411、经淀积，覆盖所述压电叠层、所述机械层和所述接触孔的底部和侧壁，形成一钝化层；即图1中所示的“钝化层”步骤。针对不同的情况来使用不用的方法做深槽工艺，解决了不同情况下对较薄材料做深槽较难的问题，而且方法简单，效果好。
请参阅图9，在一些实施方式中，阻尼材料31为多孔塑胶，在淀积时深槽最边缘是多孔塑胶，槽中间设有真空孔洞。步骤S204中淀积方法为于低温下等离子化学气相淀积多孔塑胶，这一淀积方法在深槽顶端淀积速度较快，能够快速封口，在深槽中部或底部留下真空孔洞，这一技术巧妙地形成了Si/多孔塑胶/空气/多孔塑胶/Si界面结构，能显著减少超声波在深槽的传播。步骤S204中，采用等离子化学气相淀积阻尼材料31，使所述深槽3内被填充阻尼材料31后，在所述深槽3内形成有密闭的真空孔洞32。较佳的，等离子化学气相淀积阻尼材料31的温度为250-350℃。
在另一些实施方式中，阻尼材料31为多孔氧化物(如SiO2)，且在淀积时深槽最边缘是多孔氧化物，槽中间设有真空孔洞32。示例性的，步骤S204中淀积方法为于低温下等离子化学气相淀积SiO2，这一淀积方法在深槽顶端淀积速度较快，能够快速封口，在深槽中部或底部留下真空孔洞，这一技术巧妙地形成了Si/SiO2/空气/SiO2/Si界面结构，能显著减少超声波在深槽的传播。步骤S204中，采用等离子化学气相淀积阻尼材料31，使所述深槽内被填充阻尼材料后,在所述深槽内形成有密闭的真空孔洞；示例性的，通过于低温下等离子化学气相淀积SiO2，这一淀积方法在深槽顶端淀积速度较快，能够快速封口，在深槽中部或底部留下真空孔洞，这一技术巧妙地形成了Si/SiO2/空气/SiO2/Si界面结构，能显著减少超声波在深槽的传播。
本公开还提出了一种超声换能器，包括CMOS单元，所述CMOS单元上设有一个 PMUT单元，所述PMUT单元包括PMUT衬底1，所述PMUT衬底1表面向所述PMUT衬底1内凹设有一个空腔2，覆盖所述空腔2、在所述PMUT衬底1上依次设有机械层4和压电叠层5，当所述PMUT单元的尺寸小于预设尺寸、所述PMUT单元的面积小于第一预设面积、以及所述空腔的面积大于第二预设面积时，围绕所述空腔、自所述机械层表面向所述PMUT衬底1内凹设有一个深槽3，所述深槽3内充满有阻尼材料。
实施例2
参照图2-图3，一种减少超声换能器声串扰的深槽隔离方法，所述超声换能器包括CMOS单元，所述CMOS单元上设有一个PMUT单元，所述PMUT单元包括PMUT衬底1，所述PMUT衬底1内设有一个空腔2(即一个PMUT单元内对应设有一个空腔2)，覆盖所述空腔2、所述PMUT衬底1上依次设有机械层4和压电叠层5，所述深槽隔离方法包括以下步骤：
S1、获取所述PMUT单元的尺寸和面积、以及所述空腔的面积；
S3、当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔的面积小于或等于第二预设面积时，进行深槽后设流程：
先在所述机械层上淀积，形成所述压电叠层；
然后围绕所述空腔，自所述压电叠层表面向所述机械层表面刻蚀，形成接触孔，并自所述接触孔内的所述机械层表面向所述PMUT衬底内刻蚀，形成至少一个深槽。
在一些实施方式中，所述压电叠层包括下金属层、压电层和上金属层；
所述步骤S3中，所述深槽后设流程具体包括以下步骤：
S301、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；即图2中所示的“键合减薄”步骤。
S302、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；即图2中所示的“压电层淀积”步骤。
S303、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，形成接触孔；即图2中所示的“压电层光刻”步骤。
S304、经淀积，覆盖所述机械层和所述压电叠层，形成一掩膜氧化层；即图2中所示的“深槽淀积”步骤。
S305、掩膜下，围绕所述空腔、自所述接触孔内的所述掩膜氧化层表面向所述 PMUT衬底内依次进行光刻和腐蚀，形成一个深槽；即图2中所示的“深槽光刻、深槽腐蚀”步骤。
S306、去除所述掩膜氧化层后、涂敷或淀积阻尼材料，覆盖所述深槽的底部和侧壁、所述机械层以及所述压电叠层，形成阻尼层；即图2中所示的“深槽介质沉积”步骤。
S307、经抛光处理、去除多余的阻尼层，保留所述深槽内的阻尼层。即图2中所示的“抛光”步骤。
示例性的，所述预设厚度可为3μm。
在一些实施方式中，所述步骤S307之后包括步骤：
S408、在所述PMUT衬底背面形成一金属互连层；即图2中所示的“金属互连”步骤。
S409、在所述PMUT衬底内沿第一方向形成金属布线层，并自所述金属布线层垂直所述第一方向形成金属引线孔，使所述金属布线层与所述金属互连层连接，所述第一方向为所述PMUT衬底的长度方向；
S410、贯穿所述压电层、所述下金属层和所述机械层并延伸至所述金属布线层表面，形成上金属层连接孔和下金属层连接孔；
S411、经淀积，覆盖所述压电叠层、所述机械层和所述接触孔的底部和侧壁，形成一钝化层；即图2中所示的“钝化层”步骤。针对不同的情况来使用不用的方法做深槽工艺，解决了不同情况下对较薄材料做深槽较难的问题，而且方法简单，效果好。
在一些实施方式中，步骤S306中，在涂敷或淀积阻尼材料之后，通过光刻，仅保留深槽填充介质/涂敷介质在深槽区域，通过合理设计，可以进一步降低声串扰。
进一步地，在一种实施方式中，所述经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，具体包括：经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，且所述机械层背面同时被氧化，在所述机械层和所述PMUT衬底之间形成一氧化层。
进一步地，在一种实施方式中，深槽的横截面呈圆形环。
进一步地，在一种实施方式中，深槽的横截面呈多边形环；示例性的，多边形环可为方形环、六边形环、八边形环等。
本公开还提出了一种超声换能器，包括CMOS单元，所述CMOS单元上设有一个PMUT单元，所述PMUT单元包括PMUT衬底1，所述PMUT衬底1表面向所述PMUT 衬底1内凹设有一个空腔2，覆盖所述空腔、在所述PMUT衬底1上依次设有机械层4和压电叠层5，
当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔2的面积小于或等于第二预设面积时，围绕所述空腔2、自所述机械层4表面向所述PMUT衬底1内凹设有一个深槽3，所述深槽3的底部和侧壁形成有阻尼层。
实施例3
参照图1、图4，一种减少超声换能器声串扰的深槽隔离方法，所述超声换能器包括CMOS单元，所述CMOS单元上设有三个PMUT单元，且三个PMUT单元相连接，三个PMUT单元共用PMUT衬底1，所述PMUT衬底1内设有三个空腔2(即一个PMUT单元内对应设有一个空腔2)，覆盖所述空腔2、所述PMUT衬底1上依次设有机械层4和压电叠层5，所述深槽隔离方法包括以下步骤：
S1、获取所述PMUT单元的尺寸和面积、以及所述空腔的面积；
S2、当所述PMUT单元的尺寸小于预设尺寸、所述PMUT单元的面积小于第一预设面积、以及所述空腔的面积大于第二预设面积时，进行深槽先设流程：
先围绕所述空腔、自所述机械层向所述PMUT衬底内刻蚀，形成深槽；
然后经淀积，在所述深槽隔离出的区域内的所述机械层上形成所述压电叠层。
在一些实施方式中，所述压电叠层包括下金属层、压电层和上金属层；
所述步骤S2中，所述深槽先设流程具体包括以下步骤：
S201、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；即图1中所示的“键合减薄”步骤。
S202、经淀积，在所述机械层上形成掩膜氧化层；即图1中所示的“淀积”步骤。
S203、掩膜下，围绕所述空腔、自所述掩膜氧化层向所述PMUT衬底内依次进行光刻和腐蚀，形成所述深槽；即图1中所示的“深槽光刻”步骤。
S204、去除所述掩膜氧化层后、淀积阻尼材料，使所述深槽内充满阻尼材料、并在所述PMUT衬底的一表面上形成阻尼层；即图1中所示的“再次淀积”步骤。
S205、经抛光处理，去除所述阻尼层；即图1中所示的“抛光”步骤。
S206、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；即图1中所示的“敷设材料”步骤。
S207、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，在所述深槽上形成接触孔。即图1中的所示“压电光刻”步骤。
示例性的，所述预设厚度为4μm。
在一些实施方式中，所述步骤S207之后包括步骤：
S408、在所述PMUT衬底背面形成一金属互连层；即图1中所示的“金属互连”步骤。
S409、在所述PMUT衬底内沿第一方向形成金属布线层，并自所述金属布线层垂直所述第一方向形成金属引线孔，使所述金属布线层与所述金属互连层连接，所述第一方向为所述PMUT衬底的长度方向；
S410、贯穿所述压电层、所述下金属层和所述机械层并延伸至所述金属布线层表面，形成上金属层连接孔和下金属层连接孔；
S411、经淀积，覆盖所述压电叠层、所述机械层和所述接触孔的底部和侧壁，形成一钝化层；即图1中所示的“钝化层”步骤。针对不同的情况来使用不用的方法做深槽工艺，解决了不同情况下对较薄材料做深槽较难的问题，而且方法简单，效果好。
参阅图9，在一些实施方式中，阻尼材料31为多孔塑胶，在淀积时深槽最边缘是多孔塑胶，槽中间设有真空孔洞32。示例性的，步骤S204中淀积方法为等离子化学气相淀积多孔塑胶，这一淀积方法在深槽顶端淀积速度较快，能够快速封口，在深槽中部或底部留下真空孔洞，这一技术巧妙地形成了Si/多孔塑胶/空气/多孔塑胶/Si界面结构，能显著减少超声波在深槽的传播。步骤S204中，采用等离子化学气相淀积阻尼材料，使所述深槽内被填充阻尼材料后,在所述深槽内形成有密闭的真空孔洞。较佳的，等离子化学气相淀积阻尼材料的温度为250-350℃。
在另一些实施方式中，阻尼材料31为多孔氧化物(如SiO2)，且在淀积时深槽最边缘是多孔氧化物，槽中间设有真空孔洞。示例性的，步骤S204中淀积方法为等离子化学气相淀积SiO2，这一淀积方法在深槽顶端淀积速度较快，能够快速封口，在深槽中部或底部留下真空孔洞，这一技术巧妙地形成了Si/SiO2/空气/SiO2/Si界面结构，能显著减少超声波在深槽的传播。步骤S204中，采用等离子化学气相淀积阻尼材料，使所述深槽内被填充阻尼材料后,在所述深槽内形成有密闭的真空孔洞；示例性的，通过等离子化学气相淀积SiO2，这一淀积方法在深槽顶端淀积速度较快，能够快速封口，在深槽中部或底部留下真空孔洞，这一技术巧妙地形成了Si/SiO2/空气/SiO2/Si界面结构，能显著减少超声波在深槽的传播。
本公开还提出了一种超声换能器，包括CMOS单元，所述CMOS单元上设有三个PMUT单元，三个PMUT单元共用PMUT衬底1，所述PMUT衬底1表面向所述PMUT衬底1内凹设有三个空腔2(即一个PMUT单元内对应设有一个空腔2)，覆盖所述空腔2、在所述PMUT衬底1上依次设有机械层4和压电叠层5，当所述PMUT单元的尺寸小于预设尺寸、所述PMUT单元的面积小于第一预设面积、以及所述空腔2的面积大于第二预设面积时，围绕所述空腔2、自所述机械层4表面向所述PMUT衬底1内凹设有三个深槽3，所述深槽3内充满有阻尼材料，三个PMUT单元相邻，且相邻的PMUT单元之间共用一个深槽3。
实施例4
参照图2、图4，一种减少超声换能器声串扰的深槽隔离方法，所述超声换能器包括CMOS单元，所述CMOS单元上设有三个PMUT单元，且三个PMUT单元相连接，三个PMUT单元共用PMUT衬底1，所述PMUT衬底1内设有三个空腔2(即一个PMUT单元内对应设有一个空腔2)，覆盖所述空腔2、所述PMUT衬底1上依次设有机械层4和压电叠层5，所述深槽隔离方法包括以下步骤：
S1、获取所述PMUT单元的尺寸和面积、以及所述空腔的面积；
S3、当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔的面积小于或等于第二预设面积时，进行深槽后设流程：
先在所述机械层上淀积，形成所述压电叠层；
然后围绕所述空腔，自所述压电叠层表面向所述机械层表面刻蚀，形成接触孔，并自所述接触孔内的所述机械层表面向所述PMUT衬底内刻蚀，形成至少一个深槽。
在一些实施方式中，所述压电叠层包括下金属层、压电层和上金属层；
所述步骤S3中，所述深槽后设流程具体包括以下步骤：
S301、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；即图2中所示的“键合减薄”步骤。
S302、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；即图2中所示的“压电层淀积”步骤。
S303、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，形成接触孔；即图2中所示的“压电层光刻”步骤。
S304、经淀积，覆盖所述机械层和所述压电叠层，形成一掩膜氧化层；即图2中所示的“深槽淀积”步骤。
S305、掩膜下，围绕所述空腔、自所述接触孔内的所述掩膜氧化层表面向所述PMUT衬底内依次进行光刻和腐蚀，形成三个深槽；即图2中所示的“深槽光刻、深槽腐蚀”步骤。
S306、去除所述掩膜氧化层后、涂敷或淀积阻尼材料，覆盖所述深槽的底部和侧壁、所述机械层以及所述压电叠层，形成阻尼层；即图2中所示的“深槽介质沉积”步骤。
S307、经抛光处理、去除多余的阻尼层，保留所述深槽内的阻尼层。即图2中所示的“抛光”步骤。
示例性的，所述预设厚度为3μm。
在一些实施方式中，所述步骤S307之后包括步骤：
S408、在所述PMUT衬底背面形成一金属互连层；即图2中所示的“金属互连”步骤。
S409、在所述PMUT衬底内沿第一方向形成金属布线层，并自所述金属布线层垂直所述第一方向形成金属引线孔，使所述金属布线层与所述金属互连层连接，所述第一方向为所述PMUT衬底的长度方向；
S410、贯穿所述压电层、所述下金属层和所述机械层并延伸至所述金属布线层表面，形成上金属层连接孔和下金属层连接孔；
S411、经淀积，覆盖所述压电叠层、所述机械层和所述接触孔的底部和侧壁，形成一钝化层；即图2中所示的“钝化层”步骤。针对不同的情况来使用不用的方法做深槽工艺，解决了不同情况下对较薄材料做深槽较难的问题，而且方法简单，效果好。
在一些实施方式中，步骤S306中，在涂敷或淀积阻尼材料之后，通过光刻，仅保留深槽填充介质/涂敷介质在深槽区域，通过合理设计，可以进一步降低声串扰。
进一步地，在一种实施方式中，所述经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，具体包括：经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，且所述机械层背面同时被氧化，在所述机械层和所述PMUT衬底之间形成一氧化层。
进一步地，在一种实施方式中，深槽的横截面呈圆形环。
进一步地，在一种实施方式中，深槽的横截面呈多边形环；示例性的，多边形环 可为方形环、六边形环、八边形环等。
本公开还提出了一种超声换能器，包括CMOS单元，所述CMOS单元上设有至少一个(如九个)PMUT单元，所有PMUT单元共用PMUT衬底1，所述PMUT衬底1表面向所述PMUT衬底1内凹设有至少一个空腔2(即一个PMUT单元内对应设有一个空腔2)，覆盖所述空腔2、在所述PMUT衬底1上依次设有机械层4和压电叠层5，
当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔2的面积小于或等于第二预设面积时，围绕所述空腔2、自所述机械层4表面向所述PMUT衬底1内凹设有一个深槽3，所述深槽3的底部和侧壁形成有阻尼层，三个PMUT单元相邻，且相邻的PMUT单元之间共用一个深槽3。
实施例5
参照图1、图5，一种减少超声换能器声串扰的深槽隔离方法，所述超声换能器包括CMOS单元，所述CMOS单元上设有九个PMUT单元，且九个PMUT单元呈3×3阵列分布，所有PMUT单元共用PMUT衬底1，网格状图形是深槽3结构，黑色圆形是空腔2，白色圆形是PMUT单元的压电叠层的顶层51(如上层金属层)，这一设计中，深槽3网格将空腔2，及PMUT单元完全包围，并与邻近PMUT单元实现彻底隔离，所述深槽隔离方法包括以下步骤：
S1、获取所述PMUT单元的尺寸和面积、以及所述空腔的面积；
S2、当所述PMUT单元的尺寸小于预设尺寸、所述PMUT单元的面积小于第一预设面积、以及所述空腔的面积大于第二预设面积时，进行深槽先设流程：
先围绕所述空腔、自所述机械层向所述PMUT衬底内刻蚀，形成深槽；
然后经淀积，在所述深槽隔离出的区域内的所述机械层上形成所述压电叠层。
在一些实施方式中，所述压电叠层包括下金属层、压电层和上金属层；
所述步骤S2中，所述深槽先设流程具体包括以下步骤：
S201、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；即图1中所示的“键合减薄”步骤。
S202、经淀积，在所述机械层上形成掩膜氧化层；即图1中所示的“淀积”步骤。
S203、掩膜下，围绕所述空腔、自所述掩膜氧化层向所述PMUT衬底内依次进行光刻和腐蚀，形成所述深槽；即图1中所示的“深槽光刻”步骤。
S204、去除所述掩膜氧化层后、淀积阻尼材料，使所述深槽内充满阻尼材料、并 在所述PMUT衬底的一表面上形成阻尼层；即图1中所示的“再次淀积”步骤。
S205、经抛光处理，去除所述阻尼层；即图1中所示的“抛光”步骤。
S206、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；即图1中所示的“敷设材料”步骤。
S207、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，在所述深槽上形成接触孔。即图1中的所示“压电光刻”步骤。
示例性的，所述预设厚度为4μm。
在一些实施方式中，所述步骤S207之后包括步骤：
S408、在所述PMUT衬底背面形成一金属互连层；即图1中所示的“金属互连”步骤。
S409、在所述PMUT衬底内沿第一方向形成金属布线层，并自所述金属布线层垂直所述第一方向形成金属引线孔，使所述金属布线层与所述金属互连层连接，所述第一方向为所述PMUT衬底的长度方向；
S410、贯穿所述压电层、所述下金属层和所述机械层并延伸至所述金属布线层表面，形成上金属层连接孔和下金属层连接孔；
S411、经淀积，覆盖所述压电叠层、所述机械层和所述接触孔的底部和侧壁，形成一钝化层；即图1中所示的“钝化层”步骤。针对不同的情况来使用不用的方法做深槽工艺，解决了不同情况下对较薄材料做深槽较难的问题，而且方法简单，效果好。
请参阅图9，在一些实施方式中，阻尼材料31为多孔塑胶，在淀积时深槽最边缘是多孔塑胶，槽中间设有真空孔洞。步骤S204中淀积方法为等离子化学气相淀积多孔塑胶，这一淀积方法在深槽顶端淀积速度较快，能够快速封口，在深槽中部或底部留下真空孔洞，这一技术巧妙地形成了Si/多孔塑胶/空气/多孔塑胶/Si界面结构，能显著减少超声波在深槽的传播。步骤S204中，采用等离子化学气相淀积阻尼材料31，使所述深槽3内被填充阻尼材料31后,在所述深槽3内形成有密闭的真空孔洞32。较佳的，等离子化学气相淀积阻尼材料的温度为250-300℃。
在另一些实施方式中，阻尼材料31为多孔氧化物(如SiO2)，且在淀积时深槽最边缘是多孔氧化物，槽中间设有真空孔洞32。示例性的，步骤S204中淀积方法为于低温下等离子化学气相淀积SiO2，这一淀积方法在深槽顶端淀积速度较快，能够快速封口，在深槽中部或底部留下真空孔洞，这一技术巧妙地形成了Si/SiO2/空气/SiO2/Si界面结构，能显著减少超声波在深槽的传播。步骤S204中，采用等离子化学气相淀积阻尼材 料，使所述深槽内被填充阻尼材料后,在所述深槽内形成有密闭的真空孔洞；示例性的，通过于低温下等离子化学气相淀积SiO2，这一淀积方法在深槽顶端淀积速度较快，能够快速封口，在深槽中部或底部留下真空孔洞，这一技术巧妙地形成了Si/SiO2/空气/SiO2/Si界面结构，能显著减少超声波在深槽的传播。本公开还提出了一种超声换能器，包括CMOS单元，所述CMOS单元上设有九个PMUT单元，且九个PMUT单元呈3×3阵列分布，所有PMUT单元共用PMUT衬底1，网格状图形是深槽3结构，黑色圆形是空腔2，白色圆形是PMUT单元的压电叠层5的顶层51(如上层金属层)。这一设计中，深槽3网格将空腔2，及PMUT单元完全包围，并与邻近PMUT单元实现彻底隔离。
实施例6
参照图2、图6，一种减少超声换能器声串扰的深槽隔离方法，所述超声换能器包括CMOS单元，所述CMOS单元上设有九个PMUT单元，且九个PMUT单元呈3×3阵列分布，所有PMUT单元共用PMUT衬底1，所述PMUT单元的顶部设有压电叠层5，以俯视角度看、压电叠层的顶层51(如上金属层)的周围设有空腔2，所述深槽隔离方法包括以下步骤：
S1、获取所述PMUT单元的尺寸和面积、以及所述空腔的面积；
S3、当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔的面积小于或等于第二预设面积时，进行深槽后设流程：
先在所述机械层上淀积，形成所述压电叠层；
然后围绕所述空腔，自所述压电叠层表面向所述机械层表面刻蚀，形成接触孔，并自所述接触孔内的所述机械层表面向所述PMUT衬底内刻蚀，形成至少一个深槽。
在一些实施方式中，所述压电叠层包括下金属层、压电层和上金属层；
所述步骤S3中，所述深槽后设流程具体包括以下步骤：
S301、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；即图2中所示的“键合减薄”步骤。
S302、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；即图2中所示的“压电层淀积”步骤。
S303、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，形成接触孔；即图2中所示的“压电层光刻”步骤。
S304、经淀积，覆盖所述机械层和所述压电叠层，形成一掩膜氧化层；即图2中所示的“深槽淀积”步骤。
S305、掩膜下，围绕所述空腔、自所述接触孔内的所述掩膜氧化层表面向所述PMUT衬底内依次进行光刻和腐蚀，形成三个深槽；即图2中所示的“深槽光刻、深槽腐蚀”步骤。
S306、去除所述掩膜氧化层后、涂敷或淀积阻尼材料，覆盖所述深槽的底部和侧壁、所述机械层以及所述压电叠层，形成阻尼层；即图2中所示的“深槽介质沉积”步骤。
S307、经抛光处理、去除多余的阻尼层，保留所述深槽内的阻尼层。即图2中所示的“抛光”步骤。
示例性的，所述预设厚度为3μm。
在一些实施方式中，所述步骤S307之后包括步骤：
S408、在所述PMUT衬底背面形成一金属互连层；即图2中所示的“金属互连”步骤。
S409、在所述PMUT衬底内沿第一方向形成金属布线层，并自所述金属布线层垂直所述第一方向形成金属引线孔，使所述金属布线层与所述金属互连层连接，所述第一方向为所述PMUT衬底的长度方向；
S410、贯穿所述压电层、所述下金属层和所述机械层并延伸至所述金属布线层表面，形成上金属层连接孔和下金属层连接孔；
S411、经淀积，覆盖所述压电叠层、所述机械层和所述接触孔的底部和侧壁，形成一钝化层；即图2中所示的“钝化层”步骤。针对不同的情况来使用不用的方法做深槽工艺，解决了不同情况下对较薄材料做深槽较难的问题，而且方法简单，效果好。
在一些实施方式中，步骤S306中，在涂敷或淀积阻尼材料之后，通过光刻，仅保留深槽填充介质/涂敷介质在深槽区域，通过合理设计，可以进一步降低声串扰。
进一步地，在一种实施方式中，所述经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，具体包括：经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，且所述机械层背面同时被氧化，在所述机械层和所述PMUT衬底之间形成一氧化层。
进一步地，在一种实施方式中，深槽的横截面呈圆形环。
进一步地，在一种实施方式中，深槽的横截面呈多边形环；示例性的，多边形环 可为方形环、六边形环、八边形环等。
本公开还提出了一种超声换能器，包括CMOS单元，所述CMOS单元上设有九个PMUT单元，所有PMUT单元共用PMUT衬底1，所述PMUT单元的顶部设有压电叠层5，以俯视角度看、压电叠层的顶层51(如上金属层)的周围设有空腔2，
当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔2的面积小于或等于第二预设面积时，围绕所述空腔2、自所述压电叠层5表面设有一个深槽3，在空腔2的近邻处，形成独立的封闭深槽3，深槽3仅仅隔离空腔2及其上方可振动器件结构。
实施例6
参照图2、图7，一种减少超声换能器声串扰的深槽隔离方法，所述超声换能器包括CMOS单元，所述CMOS单元上设有九个PMUT单元，且九个PMUT单元呈3×3阵列分布，所有PMUT单元共用PMUT衬底1，所述PMUT衬底1的顶部设有压电叠层5，以俯视角度看、压电叠层的顶层51(如上金属层)周围设有空腔2，所述深槽隔离方法包括以下步骤：
S1、获取所述PMUT单元的尺寸和面积、以及所述空腔的面积；
S3、当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔的面积小于或等于第二预设面积时，进行深槽后设流程：
先在所述机械层上淀积，形成所述压电叠层；
然后围绕所述空腔，自所述压电叠层表面向所述机械层表面刻蚀，形成接触孔，并自所述接触孔内的所述机械层表面向所述PMUT衬底内刻蚀，形成至少一个深槽。
在一些实施方式中，所述压电叠层包括下金属层、压电层和上金属层；
所述步骤S3中，所述深槽后设流程具体包括以下步骤：
S301、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；即图2中所示的“键合减薄”步骤。
S302、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；即图2中所示的“压电层淀积”步骤。
S303、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，形成接触孔；即图2中所示的“压电层光刻”步骤。
S304、经淀积，覆盖所述机械层和所述压电叠层，形成一掩膜氧化层；即图2中所示的“深槽淀积”步骤。
S305、掩膜下，围绕所述空腔、自所述接触孔内的所述掩膜氧化层表面向所述PMUT衬底内依次进行光刻和腐蚀，形成三个深槽；即图2中所示的“深槽光刻、深槽腐蚀”步骤。
S306、去除所述掩膜氧化层后、涂敷或淀积阻尼材料，覆盖所述深槽的底部和侧壁、所述机械层以及所述压电叠层，形成阻尼层；即图2中所示的“深槽介质沉积”步骤。
S307、经抛光处理、去除多余的阻尼层，保留所述深槽内的阻尼层。即图2中所示的“抛光”步骤。
示例性的，所述预设厚度为3μm。
在一些实施方式中，所述步骤S307之后包括步骤：
S408、在所述PMUT衬底背面形成一金属互连层；即图2中所示的“金属互连”步骤。
S409、在所述PMUT衬底内沿第一方向形成金属布线层，并自所述金属布线层垂直所述第一方向形成金属引线孔，使所述金属布线层与所述金属互连层连接，所述第一方向为所述PMUT衬底的长度方向；
S410、贯穿所述压电层、所述下金属层和所述机械层并延伸至所述金属布线层表面，形成上金属层连接孔和下金属层连接孔；
S411、经淀积，覆盖所述压电叠层、所述机械层和所述接触孔的底部和侧壁，形成一钝化层；即图2中所示的“钝化层”步骤。针对不同的情况来使用不用的方法做深槽工艺，解决了不同情况下对较薄材料做深槽较难的问题，而且方法简单，效果好。
在一些实施方式中，步骤S306中，在涂敷或淀积阻尼材料之后，通过光刻，仅保留深槽填充介质/涂敷介质在深槽区域，通过合理设计，可以进一步降低声串扰。
进一步地，在一种实施方式中，所述经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，具体包括：经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，且所述机械层背面同时被氧化，在所述机械层和所述PMUT衬底之间形成一氧化层。
进一步地，在一种实施方式中，深槽的横截面呈圆形环。
进一步地，在一种实施方式中，深槽的横截面呈多边形环；示例性的，多边形环 可为方形环、六边形环、八边形环等。
本公开还提出了一种超声换能器，包括CMOS单元，所述CMOS单元上设有九个PMUT单元，所有PMUT单元共用PMUT衬底1，所述PMUT单元的顶部设有压电叠层5，以俯视角度看、压电叠层的顶层51(如上金属层)的周围设有空腔2，
当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔2的面积小于或等于第二预设面积时，围绕所述空腔2、自所述压电叠层5表面包围有一个深槽3，在空腔2的近邻处，形成独立的封闭深槽3，深槽3仅仅隔离空腔2及其上方可振动器件结构，深槽3的形状可为四边形环、六边形环或者八边形环等。
实施例7
参照图2、图7、图8，一种减少超声换能器声串扰的深槽隔离方法，所述超声换能器包括CMOS单元，所述CMOS单元上设有九个PMUT单元，且九个PMUT单元呈3×3阵列分布，所有PMUT单元共用PMUT衬底1，所述PMUT单元的顶部设有压电叠层5，以俯视角度看、压电叠层的顶层51(如上金属层)的周围设有空腔2，所述深槽隔离方法包括以下步骤：
S1、获取所述PMUT单元的尺寸和面积、以及所述空腔的面积；
S3、当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔的面积小于或等于第二预设面积时，进行深槽后设流程：
先在所述机械层上淀积，形成所述压电叠层；
然后围绕所述空腔，自所述压电叠层表面向所述机械层表面刻蚀，形成接触孔，并自所述接触孔内的所述机械层表面向所述PMUT衬底内刻蚀，形成至少一个深槽。
在一些实施方式中，所述压电叠层包括下金属层、压电层和上金属层；
所述步骤S3中，所述深槽后设流程具体包括以下步骤：
S301、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；即图2中所示的“键合减薄”步骤。
S302、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；即图2中所示的“压电层淀积”步骤。
S303、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，形成接触孔；即图 2中所示的“压电层光刻”步骤。
S304、经淀积，覆盖所述机械层和所述压电叠层，形成一掩膜氧化层；即图2中所示的“深槽淀积”步骤。
S305、掩膜下，围绕所述空腔、自所述接触孔内的所述掩膜氧化层表面向所述PMUT衬底内依次进行光刻和腐蚀，形成三个深槽；即图2中所示的“深槽光刻、深槽腐蚀”步骤。
S306、去除所述掩膜氧化层后、涂敷或淀积阻尼材料，覆盖所述深槽的底部和侧壁、所述机械层以及所述压电叠层，形成阻尼层；即图2中所示的“深槽介质沉积”步骤。
S307、经抛光处理、去除多余的阻尼层，保留所述深槽内的阻尼层。图2中所示的“抛光”步骤。
示例性的，所述预设厚度为3μm。
在一些实施方式中，所述步骤S307之后包括步骤：
S408、在所述PMUT衬底背面形成一金属互连层；即图2中所示的“金属互连”步骤。
S409、在所述PMUT衬底内沿第一方向形成金属布线层，并自所述金属布线层垂直所述第一方向形成金属引线孔，使所述金属布线层与所述金属互连层连接，所述第一方向为所述PMUT衬底的长度方向；
S410、贯穿所述压电层、所述下金属层和所述机械层并延伸至所述金属布线层表面，形成上金属层连接孔和下金属层连接孔；
S411、经淀积，覆盖所述压电叠层、所述机械层和所述接触孔的底部和侧壁，形成一钝化层；即图2中所示的“钝化层”步骤。针对不同的情况来使用不用的方法做深槽工艺，解决了不同情况下对较薄材料做深槽较难的问题，而且方法简单，效果好。
在一些实施方式中，步骤S306中，在涂敷或淀积阻尼材料之后，通过光刻，仅保留深槽填充介质/涂敷介质在深槽区域，通过合理设计，可以进一步降低声串扰。
进一步地，在一种实施方式中，所述经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，具体包括：经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，且所述机械层背面同时被氧化，在所述机械层和所述PMUT衬底之间形成一氧化层。
进一步地，在一种实施方式中，深槽的横截面呈圆形环。
进一步地，在一种实施方式中，深槽的横截面呈多边形环；示例性的，多边形环可为方形环、六边形环、八边形环等。
本公开还提出了一种超声换能器，包括CMOS单元，所述CMOS单元上设有九个PMUT单元，所有PMUT单元共用PMUT衬底1，所述PMUT单元的顶部设有压电叠层5，以俯视角度看、压电叠层5的顶层51(如上金属层)的周围设有空腔2，
当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔2的面积小于或等于第二预设面积时，围绕所述空腔2、自所述压电叠层5表面包围有一个深槽3，在空腔2的近邻处，形成独立的封闭深槽3，深槽3仅仅隔离空腔2及其上方可振动器件结构，深槽3的形状可为四边形环、六边形环或者八边形环等；
抗干扰的设计不局限于单一深槽，如果单元面积允许，也可以做双槽，甚至多槽设计，如图8为例的不连续双槽隔离示意图，在单元布局(layout)中，区域A，B，C，D已经有相关单元结构存在，如三维架构的垂直连接，或金属布线等，双槽隔离可以单槽错开这些区域，另一深槽则可交错互补，保证至少有一个深槽在机械波横向路径上，起到减低干挠的作用。应当理解的是，所述预设尺寸是指能采用双深槽隔离工艺时，所述PMUT单元具有的最小横向尺寸；所述第一预设面积是指能采用双深槽隔离工艺时，所述PMUT单元具有的最小面积；所述第二预设面积是指能采用双深槽隔离工艺时，所述PMUT单元内的空腔具有的最大面积。
在该文中的描述中，需要说明的是，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。
尽管已经示出和描述了本公开的实施例，本领域的普通技术人员而言，可以理解在不脱离本公开的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本公开的范围由所附权利要求及其等同物限定。

Claims (10)

  1. 一种减少超声换能器声串扰的深槽隔离方法，所述超声换能器包括CMOS单元，所述CMOS单元上设有至少一个PMUT单元，所有PMUT单元共用PMUT衬底，所述PMUT衬底内设有至少一个空腔，覆盖所述空腔、所述PMUT衬底上依次设有机械层和压电叠层，其中，所述深槽隔离方法包括以下步骤：
    S1、获取所述PMUT单元的尺寸和面积、以及所述空腔的面积；
    S2、当所述PMUT单元的尺寸小于预设尺寸、所述PMUT单元的面积小于第一预设面积、以及所述空腔的面积大于第二预设面积时，进行深槽先设流程：
    先围绕所述空腔、自所述机械层向所述PMUT衬底内刻蚀，形成深槽；
    然后经淀积，在所述深槽隔离出的区域内的所述机械层上形成所述压电叠层；
    S3、当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔的面积小于或等于第二预设面积时，进行深槽后设流程：
    先在所述机械层上淀积，形成所述压电叠层；
    然后围绕所述空腔，自所述压电叠层表面向所述机械层表面刻蚀，形成接触孔，并自所述接触孔内的所述机械层表面向所述PMUT衬底内刻蚀，形成至少一个深槽。
  2. 如权利要求1所述的一种减少超声换能器声串扰的深槽隔离方法，其中，所述压电叠层包括下金属层、压电层和上金属层；
    所述步骤S2中，所述深槽先设流程具体包括以下步骤：
    S201、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；
    S202、经淀积，在所述机械层上形成掩膜氧化层；
    S203、掩膜下，围绕所述空腔、自所述掩膜氧化层向所述PMUT衬底内依次进行光刻和腐蚀，形成所述深槽；
    S204、去除所述掩膜氧化层后、淀积阻尼材料，使所述深槽内充满阻尼材料、并在所述PMUT衬底的一表面上形成阻尼层；
    S205、经抛光处理，去除所述阻尼层；
    S206、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；
    S207、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，在所述深槽上形成接触孔；
    所述步骤S3中，所述深槽后设流程具体包括以下步骤：
    S301、提供PMUT衬底，自所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个所述空腔，经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，经减薄、使所述机械层达到预设厚度；
    S302、经淀积，在所述机械层上依次形成下金属层、压电层和上金属层；
    S303、掩膜下，自所述上金属层表面向所述机械层表面刻蚀，形成接触孔；
    S304、经淀积，覆盖所述机械层和所述压电叠层，形成一掩膜氧化层；
    S305、掩膜下，围绕所述空腔、自所述接触孔内的所述掩膜氧化层表面向所述PMUT衬底内依次进行光刻和腐蚀，形成所述至少一个深槽；
    S306、去除所述掩膜氧化层后、涂敷或淀积阻尼材料，覆盖所述深槽的底部和侧壁、所述机械层以及所述压电叠层，形成阻尼层；
    S307、经抛光处理、去除多余的阻尼层，保留所述深槽内的阻尼层。
  3. 如权利要求2所述的一种减少超声换能器声串扰的深槽隔离方法，其中，所述预设厚度为2-5μm。
  4. 如权利要求2所述的一种减少超声换能器声串扰的深槽隔离方法，其中，所述步骤S207和所述步骤S307之后均包括步骤：
    S408、在所述PMUT衬底背面形成一金属互连层；
    S409、在所述PMUT衬底内沿第一方向形成金属布线层，并自所述金属布线层垂直所述第一方向形成金属引线孔，使所述金属布线层与所述金属互连层连接，所述第一方向为所述PMUT衬底的长度方向；
    S410、贯穿所述压电层、所述下金属层和所述机械层并延伸至所述金属布线层表面，形成上金属层连接孔和下金属层连接孔；
    S411、经淀积，覆盖所述压电叠层、所述机械层和所述接触孔的底部和侧壁，形成一钝化层。
  5. 如权利要求2所述的一种减少超声换能器声串扰的深槽隔离方法，其中，所述阻尼材料为多孔氧化物或多孔塑胶。
  6. 如权利要求2所述的一种减少超声换能器声串扰的深槽隔离方法，其中，所述步骤S204中，采用等离子化学气相淀积阻尼材料，使所述深槽内被填充阻尼材料后,在所 述深槽内形成有密闭的真空孔洞。
  7. 如权利要求2所述的一种减少超声换能器声串扰的深槽隔离方法，其中，所述经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，具体包括：经熔融键合，覆盖所述空腔、在所述PMUT衬底上形成一机械层，且所述机械层背面同时被氧化，在所述机械层和所述PMUT衬底之间形成一氧化层。
  8. 如权利要求1-7中任一项所述的一种减少超声换能器声串扰的深槽隔离方法，其中，所述深槽的横截面呈圆形环或多边形环。
  9. 如权利要求8所述的一种减少超声换能器声串扰的深槽隔离方法，其中，所述多边形环为四形环、六边形环或八边形环。
  10. 一种超声换能器，其中，包括CMOS单元，所述CMOS单元上设有至少一个PMUT单元，所有PMUT单元共用PMUT衬底(1)，所述PMUT衬底表面向所述PMUT衬底内凹设有至少一个空腔(2)，覆盖所述空腔(2)、在所述PMUT衬底(1)上依次设有机械层(4)和压电叠层(5)；
    当所述PMUT单元的尺寸小于预设尺寸、所述PMUT单元的面积小于第一预设面积、以及所述空腔的面积大于第二预设面积时，围绕所述空腔、自所述机械层(4)表面向所述PMUT衬底内凹设有一个深槽(3)，所述深槽(3)内充满有阻尼材料；
    当所述PMUT单元的尺寸大于或等于预设尺寸、所述PMUT单元的面积大于或等于第一预设面积、以及所述空腔的面积小于或等于第二预设面积时，围绕所述空腔(2)、自所述机械层(4)表面向所述PMUT衬底内凹设有一个或多个深槽(3)，所述深槽(3)的底部和侧壁形成有阻尼层。
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