WO2024093559A1 - 光电探测器、光接收模块及电子设备 - Google Patents

光电探测器、光接收模块及电子设备 Download PDF

Info

Publication number
WO2024093559A1
WO2024093559A1 PCT/CN2023/120098 CN2023120098W WO2024093559A1 WO 2024093559 A1 WO2024093559 A1 WO 2024093559A1 CN 2023120098 W CN2023120098 W CN 2023120098W WO 2024093559 A1 WO2024093559 A1 WO 2024093559A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
layer
region
well region
photodiode
Prior art date
Application number
PCT/CN2023/120098
Other languages
English (en)
French (fr)
Inventor
万景
张伟
冯波
黄东
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2024093559A1 publication Critical patent/WO2024093559A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/66—Non-coherent receivers, e.g. using direct detection
    • H04B10/69—Electrical arrangements in the receiver

Definitions

  • the present application relates to the field of photoelectric conversion technology, and in particular to a photodetector that integrates a photodiode and a transistor monolithically, and a light receiving module comprising the photodetector, as well as a method for preparing the photodetector, and an electronic device comprising the light receiving module.
  • Photodetectors have the ability to convert optical signals directly into electrical signals. Therefore, they are widely used in optical communications, image sensing, and spectral analysis.
  • Silicon-based PN junction photodiode is one of the most basic and widely used photodetectors. Its structure is to form a PN junction on a bulk silicon substrate. By applying a reverse bias voltage to the PN junction, a large number of electron-hole pairs are generated when light is incident. The carriers are separated under the action of the external electric field in the depletion region to form a photocurrent, thereby realizing the conversion of optical signals and electrical signals.
  • photodiodes have been required to have low power consumption, high speed, and fast response, making it difficult for PN junction photodiodes built on bulk silicon substrates to meet the requirements.
  • Silicon-On-Insulator (SOI) substrate shows a structure diagram of a PN junction photodiode formed on an SOI substrate.
  • SOI substrate structure due to the introduction of an oxide buried layer between the bottom silicon and the top silicon, it has the advantages of reducing power consumption, reducing parasitic resistance, and fast photoelectric response, and is widely used.
  • the photodiode in this structure is integrated into the top silicon layer, which uses the top silicon layer as a light absorption layer.
  • the thickness of the top silicon layer (the dimension along the Z direction shown in FIG1 ) is usually thin (for example, less than 22 nm).
  • most of the incident light directly penetrates the photosensitive area formed by the top silicon layer and cannot be effectively absorbed by the photosensitive area, resulting in lower quantum efficiency and poorer sensitivity of the photodetector built on the SOI substrate.
  • the avalanche multiplication mechanism can be used to directly improve the quantum efficiency and detection sensitivity of the photodiode integrated in the top silicon of the SOI substrate.
  • This method requires a large reverse drive voltage (for example, greater than 8.2V), which is not conducive to reducing the power consumption of the photodetector, that is, this technology cannot meet the low power consumption characteristics while having high quantum efficiency, high sensitivity, and high responsiveness.
  • the thicker bottom silicon below the oxide buried layer can be used to capture and absorb the incident light, so as to overcome the defect that most of the incident light directly passes through the photosensitive area formed by the top silicon of the SOI substrate due to the thin thickness of the top silicon of the SOI substrate, and cannot be efficiently absorbed.
  • a large reverse driving voltage for example, greater than 5V
  • the present application provides a photodetector, a light receiving module including the photodetector, and a method for preparing the photodetector, and also provides an electronic device including the light receiving module.
  • the main purpose is to provide a photodetector that not only has high quantum efficiency and sensitivity, and high responsiveness, but also can achieve low power consumption.
  • the present application provides a photodetector, which includes: a semiconductor substrate, a transistor, a first photodiode and a second photodiode; a first well region is disposed on a first region of the semiconductor substrate, and a first well region is disposed in the first well region and away from the semiconductor substrate; A first electrode doping region and a second electrode doping region are formed on the surface layer of the bulk substrate, one of the first electrode doping region and the second electrode doping region is an anode doping region, and the other is a cathode doping region; on the second region of the semiconductor substrate, and in a direction away from the semiconductor substrate, an oxide buried layer and a semiconductor layer are stacked in sequence, a first pole and a second pole of a transistor are formed in the semiconductor layer, a portion of the semiconductor layer located between the first pole and the second pole forms a channel layer of the transistor, and a gate of the transistor is arranged on a side of the channel layer away from the oxide buried layer;
  • the first well region can be regarded as a bulk silicon substrate.
  • the thick silicon of the bulk silicon i.e., the first well region with a larger thickness
  • the absorption of incident light is enhanced to obtain higher quantum efficiency and sensitivity.
  • the structure including the semiconductor substrate, the buried oxide layer and the semiconductor layer can be considered as a silicon-on-insulator SOI substrate structure, the semiconductor substrate can be considered as the bottom silicon, and the semiconductor layer can be considered as the top silicon. That is, the present application forms a transistor on a silicon-on-insulator SOI substrate. Since the semiconductor substrate and the semiconductor layer of the silicon-on-insulator SOI are isolated by the buried oxide layer, the leakage current and the parasitic capacitance can be reduced.
  • the gate serves as a gate of the transistor
  • the semiconductor substrate can be considered as another gate of the transistor, that is, the transistor has a dual-gate structure
  • the first electrode doping region of the first photodiode is electrically connected to the gate of the transistor (which can be called a top gate)
  • the first well region is electrically connected to the semiconductor substrate (which can be called a bottom gate)
  • the first electrode doping region and the first well region can form a PN junction of the first photodiode.
  • the depletion region widens, achieving effective absorption of the incident light and generating photogenerated electron-hole pairs.
  • the photogenerated carriers will gather toward the top gate and bottom gate established on the SOI substrate under the action of the built-in electric field in the depletion region.
  • the photogenerated carriers gathered at the top gate and the bottom gate will directly lead to a decrease in the transistor threshold voltage and an increase in the conductance of the channel layer, thereby resulting in a significant increase in the transistor drain current, thereby realizing internal amplification of the photocurrent; and, under the same lighting conditions, the photocurrent obtained in the present application is much higher than the photocurrent of the photodetector on the silicon SOI substrate on the insulating layer, that is, the photoelectric responsivity and quantum efficiency can be greatly improved.
  • the transistor, the first photodiode, and the second photodiode are co-integrated on a single substrate to achieve photosensitivity and amplification at the same time, and it can not only meet the requirements of high quantum efficiency, high sensitivity, and high photoelectric responsiveness, but also has the characteristics of low leakage current, low power consumption, high gain, radiation resistance, and high reliability.
  • the second photodiode also includes a second well region; the second well region is arranged on the second area and is located between the semiconductor substrate and the buried oxide layer; the doping type of the second well region is the same as the doping type of the semiconductor substrate, and the doping concentration of the second well region is greater than the doping concentration of the semiconductor substrate.
  • the first well region and the second well region form a PN junction of the second photodiode; the second well region, the semiconductor substrate and the first well region form a PIN junction of the second photodiode.
  • the second photodiode By setting a second well region between the semiconductor substrate and the buried oxide layer, the second photodiode includes not only a PN junction but also a PIN junction, so that the photodetector has a wider effective detection area.
  • the photogenerated carriers will gather toward the semiconductor substrate and the gate under the action of the electric field, resulting in a significant decrease in the transistor threshold voltage and a significant increase in the conductance of the channel layer.
  • the photodetector further includes a shallow trench isolation layer; the semiconductor layer and the first well region, as well as the buried oxide layer and the first well region are electrically isolated by the shallow trench isolation layer, and the first well region is in contact with the second well region.
  • the semiconductor layer and the second well region, as well as the buried oxide layer and the second well region are physically and electrically isolated by a shallow trench isolation layer, except that the shallow trench isolation layer does not penetrate between the first well region and the second well region, that is, the first well region and the second well region are in contact, and the photogenerated carriers will gather toward the second well region and work together with the photogenerated carriers gathered in the gate (top gate) to achieve photocurrent amplification.
  • the depth of the shallow trench isolation layer is h, and 200 nm ⁇ h ⁇ 1000 nm; the width of the shallow trench isolation layer is s, and 100 nm ⁇ s ⁇ 10000 nm.
  • the width s of the shallow trench isolation layer here can be understood as: the dimension of the shallow trench isolation layer in a direction parallel to the arrangement direction of the first region and the second region.
  • the depth h of the shallow trench isolation layer can be understood as: the dimension of the shallow trench isolation layer in a direction perpendicular to the semiconductor substrate.
  • one of the first well region and the second well region is a P-well region, and the other is an N-well region;
  • the doping type of the first electrode doping region is opposite to the doping type of the first well region, and the doping type of the second electrode doping region is the same as the doping type of the first well region.
  • the first well region is an N-well region
  • the second well region is a P-well region
  • the first electrode doping region is P-type doped
  • the second electrode doping region is N-type doped
  • the first electrode and the second electrode of the transistor are both N-type doped.
  • the first well region is a P-well region
  • the second well region is an N-well region
  • the first electrode doping region is N-type doped
  • the second electrode doping region is P-type doped
  • the first electrode and the second electrode of the transistor are both P-type doped.
  • the doping concentration of the first well region is 10 17 cm ⁇ 3 ⁇ 1 ⁇ 10 19 cm ⁇ 3 ; and/or the doping concentration of the second well region is 10 17 cm ⁇ 3 ⁇ 2 ⁇ 10 19 cm ⁇ 3 .
  • the doping concentration of at least one of the first electrode and the second electrode is 10 19 cm -3 ⁇ 3 ⁇ 10 21 cm -3 ; and/or the doping concentration of at least one of the first electrode doping region and the second electrode doping region is 10 19 cm -3 ⁇ 4 ⁇ 10 21 cm -3 .
  • the first electrode doping region and the second electrode doping region are heavily doped regions relative to the second well region, and the first pole and the second pole are heavily doped regions relative to the second well region.
  • the doping concentration of the semiconductor substrate is 10 15 cm -3 ⁇ 5 ⁇ 10 17 cm -3 .
  • a width of a depletion region of the first photodiode is 100 nm ⁇ 1 ⁇ 10 ⁇ m.
  • the photoelectric responsivity of the photodetector is greater than or equal to 10 5 A/W.
  • the present application can greatly improve the photoelectric responsivity of 160A/W to 10 5 A/W.
  • the present application can not only obtain a higher photoelectric responsivity but also reduce power consumption.
  • a first electrode metal contact layer is formed on a side of the first electrode doping region facing away from the semiconductor substrate; a metal interconnection layer is formed on a side of the gate facing away from the channel layer and on a side of the first electrode metal contact layer facing away from the semiconductor substrate, and the gate is electrically connected to the first electrode metal contact layer through the metal interconnection layer.
  • the gate of the transistor is electrically connected to the first electrode metal contact layer of the photodiode by using a metal interconnection layer.
  • a back-end process may be used to fabricate a metal interconnection layer.
  • the present application also provides a method for preparing a photoelectric detector, the preparation method comprising the following steps:
  • a first electrode doping region and a second electrode doping region are formed in the first well region on the surface away from the bottom silicon, and a first electrode and a second electrode of a transistor are formed in the top silicon, and a portion of the top silicon between the first electrode and the second electrode forms a channel layer of the transistor, a gate of the transistor is arranged on a side of the channel layer away from the oxide buried layer, one of the first electrode doping region and the second electrode doping region is an anode doping region, and the other is a cathode doping region, so as to obtain a transistor, a first photodiode and a second photodiode;
  • the first photodiode includes a first electrode doping region and a first well region; the second photodiode includes the first well region and bottom silicon.
  • a hybrid substrate including a first well region (which is the present silicon structure) and silicon on an insulating layer is formed by processing a silicon on an insulating layer substrate, and a transistor is integrated into the silicon on an insulating layer structure, and a photodiode is integrated into the present silicon.
  • the thick silicon of the bulk silicon i.e., the first well region with a larger thickness
  • the use of silicon on an insulating layer can reduce leakage current and parasitic capacitance.
  • the first electrode doping region of the first photodiode is electrically connected to the gate of the transistor (which can be called the top gate), the first well region and the semiconductor substrate (which can be called the bottom gate) are electrically connected, and the PN junction of the second photodiode is formed, so that the threshold voltage of the transistor can be reduced, resulting in an increase in the drain current of the transistor, thereby realizing internal amplification of the photocurrent, and under the same lighting conditions, the photocurrent obtained in the present application is much higher than the photocurrent of the photodetector on the SOI substrate, that is, the photoelectric responsivity and quantum efficiency are greatly improved.
  • the preparation method before removing a portion of the buried oxide layer and a portion of the top silicon on the bottom silicon of the silicon substrate on the insulating layer, the preparation method further includes: implanting ions into a portion of the bottom silicon near the buried oxide layer to form a well layer, wherein the doping type of the well layer is The doping type is the same as that of the underlying silicon, and the doping concentration of the well layer is greater than the doping concentration of the underlying silicon; a portion of the buried oxide layer and a portion of the top silicon on the underlying silicon of the silicon substrate on the insulating layer are removed, including: a portion of the buried oxide layer, a portion of the top silicon, and a portion of the well layer stacked on the underlying silicon of the silicon substrate on the insulating layer are removed, and a first well region is formed at the position after the removal, and the remaining well layer forms a second well region.
  • the effective detection area is further widened, thereby causing a further decrease in the transistor threshold voltage and a further increase in the conductance of the channel layer, thereby achieving a significant amplification of the photocurrent.
  • the preparation method after forming the second well region, also includes: setting a shallow trench isolation layer, the shallow trench isolation layer penetrates the top silicon and the oxidized buried layer, so that the top silicon and the first well region, as well as the oxidized buried layer and the first well region are electrically isolated by the shallow trench isolation layer, and the first well region is in contact with the second well region.
  • the top silicon layer is electrically isolated from the first well region, and the buried oxide layer is electrically isolated from the first well region by providing a shallow trench isolation layer, but the first well region is not electrically isolated from the second well region.
  • one of the first well region and the second well region is a P-well region, and the other is an N-well region; the doping type of the first electrode doping region is opposite to the doping type of the second well region, and the doping type of the second electrode doping region is the same as the doping type of the second well region.
  • the well regions and doping regions may be doped using an ion implantation process to form different well regions.
  • the preparation method further includes: forming a first electrode metal contact layer on the first electrode doping region; and using a back-end process to manufacture a metal interconnection layer so that the gate is electrically connected to the first electrode metal contact layer through the metal interconnection layer.
  • This type of electrical connection structure is simple and easy to implement from a process perspective.
  • the present application also provides a light receiving module, which includes a processor and any one of the above-mentioned photodetectors, and the processor is electrically connected to the photodetector.
  • the optical receiving module provided in the present application includes the above-mentioned photodetector, in this photodetector, on the basis of realizing photosensitivity and amplification, it can not only meet the requirements of high quantum efficiency, high sensitivity, and high photoelectric responsiveness, but also has the characteristics of low leakage current, low power consumption, high gain, radiation resistance, and high reliability.
  • the optical receiving module is one of an image sensor, a spectrum analyzer, and an optical switch.
  • the present application also provides an electronic device, for example, the electronic device may be a mobile phone, a wearable device, etc.
  • the electronic device includes a housing and the above-mentioned optical receiving module, the optical receiving module is arranged in the housing, and the optical receiving module is used to receive an optical signal.
  • the electronic device provided in the present application includes the above-mentioned optical receiving module, so the electronic device provided in the present application and the optical receiving module of the above-mentioned technical solution can solve the same technical problems and achieve the same expected effects.
  • the present application provides a photodetector, which includes a transistor, a first photodiode and a second photodiode; any one of the first photodiode and the second photodiode includes a first electrode and a second electrode, one of the first electrode and the second electrode is an anode, and the other is a cathode;
  • the transistor includes a source, a drain, a first gate and a second gate;
  • the second electrode of the first photodiode is electrically connected to the second electrode of the second photodiode, and is used to be electrically connected to a power supply;
  • the first electrode of the first photodiode is electrically connected to the first gate of the transistor;
  • the first electrode of the second photodiode is electrically connected to the second gate of the transistor.
  • the photodetector provided in the present application includes not only a transistor with an amplifying function, but also a first photodiode and a second photodiode connected in parallel, and the first electrode of the first photodiode is electrically connected to the first gate of the transistor, and the first electrode of the second photodiode is electrically connected to the second gate of the transistor.
  • the two PN junctions are in a reverse biased state, the depletion region of the photodiode is widened, achieving effective absorption of the incident light, and generating photogenerated electron-hole pairs, and the photogenerated carriers will gather toward the first gate and the second gate established on the SOI substrate under the action of the built-in electric field in the depletion region.
  • the photogenerated carriers gathered on the first gate and the second gate will directly lead to a decrease in the threshold voltage of the transistor and an increase in the conductance of the channel layer, thereby causing a significant increase in the drain current of the transistor, achieving internal amplification of the photocurrent; and, under the same illumination conditions, the photocurrent obtained in the present application is much higher than the photocurrent of the photodetector on the silicon SOI substrate on the insulating layer, that is, the photoelectric responsivity and quantum efficiency are greatly improved.
  • FIG1 is a structural diagram of a photoelectric detector in the related art
  • FIG2 is a structural diagram of an electronic device provided in an embodiment of the present application.
  • FIG3 is an exploded view of an electronic device provided in an embodiment of the present application.
  • FIG4 is an exploded view of an optical communication device provided in an embodiment of the present application.
  • FIG5 is an exploded view of an optical module in an optical communication device provided in an embodiment of the present application.
  • FIG6 is a top view of a photoelectric detector provided in an embodiment of the present application.
  • Fig. 7 is a cross-sectional view taken along the line A-A of Fig. 6;
  • FIG8 is a circuit diagram of a photodetector provided in an embodiment of the present application.
  • FIG9 is a cross-sectional view of another photodetector provided in an embodiment of the present application.
  • FIG10 is a circuit diagram of a photodetector provided in an embodiment of the present application.
  • FIG11 is a cross-sectional view of another photodetector provided in an embodiment of the present application.
  • FIG12 shows a PN junction and a PIN junction formed by the second photodiode in FIG11;
  • FIG13A is a structural diagram showing the effective detection area of a photodetector provided in an embodiment of the present application.
  • FIG13B is a structural diagram showing the effective detection area of a photoelectric detector provided in an embodiment of the present application.
  • FIG14 is a top view of FIG11
  • FIG15 is a curve diagram showing the change of the voltage Vc applied to the second electrode doping region and the photoelectric responsivity R when the photodetector provided by the embodiment of the present application is used;
  • FIG16 is a curve diagram showing the relationship between the drain current ID and V C when the photodetector provided in the embodiment of the present application is used;
  • FIG17 is a flowchart of a method for manufacturing a photodetector provided in an embodiment of the present application.
  • 18A1 to 18H are cross-sectional views of corresponding process structures after each step in a method for manufacturing a photodetector provided in an embodiment of the present application is completed;
  • 19A to 19F are cross-sectional views of corresponding process structures after each step in a photodetector manufacturing method provided in an embodiment of the present application is completed.
  • Avalanche multiplication effect Under a strong electric field, carriers in semiconductors will be heated by the electric field (hot carriers in semiconductors), and some carriers can obtain high enough energy. These carriers may transfer energy to electrons in the valence band through collision, causing them to ionize, thereby generating electron-hole pairs. This process is called impact ionization. The generated electron-hole pairs move in opposite directions in the electric field, are heated by the electric field again, and generate new electron-hole pairs. In this way, carriers can be multiplied in large numbers, and this phenomenon is called the avalanche multiplication effect.
  • Quantum efficiency also known as monochromatic incident photon-to-electron conversion efficiency (IPCE) refers to the ratio of the number of electron-hole pairs generated to the number of photons incident on the surface of the light absorption layer. That is, the higher the quantum efficiency, the higher the photoelectric conversion efficiency.
  • Photodetectors are a type of photoelectric conversion device that has the ability to directly convert light signals into electrical signals. For example, they can be used in image sensors, spectrum analyzers, optical switches, and automatic control equipment.
  • the electronic device may be a mobile phone, a tablet computer (tablet personal computer), a laptop computer, a personal digital assistant (PDA), a camera, a personal computer, a notebook computer, a vehicle-mounted device, a wearable device, an augmented reality (AR) glasses, an AR helmet, a virtual reality (VR) glasses or a VR helmet, etc., which have a camera module.
  • the electronic device of the embodiment shown in FIG2 is described by taking a mobile phone as an example.
  • FIG2 shows a schematic diagram of the appearance structure of a mobile phone 1000 provided in an embodiment of the present application
  • FIG3 is a schematic diagram of the exploded structure of a mobile phone 1000 provided in an embodiment of the present application.
  • the mobile phone 1000 includes a housing 100, the housing 100 includes a first housing 101 and a second housing 102 which are interlocked and have a space formed therein, the second housing 102 is provided with a window 1021, the window 1021 is covered with a camera cover 200, a camera module 400 is arranged in the housing 100, and the camera module 400 can be arranged on a carrier plate 500 located in the housing 100; and the camera cover 200 has a light-transmitting window 300, and light through the light-transmitting window 300 can be projected to the camera module 400 to be received by the camera module 400.
  • the camera module 400 may include an image sensor, which may also be called a photosensitive element or a photosensitive chip.
  • the main component of the image sensor is a photodetector, which may be used to receive light transmitted from the light-transmitting window and convert the image information carried by the light into an electrical signal.
  • the housing 100 also includes a processor electrically connected to the image sensor, and the processor is used to process the electrical signal converted by the image sensor.
  • FIG4 shows a schematic diagram of the connection relationship between various structures in an optical communication equipment 2000.
  • the optical communication equipment 2000 includes an optical network terminal device (such as a switch) 1, an optical module 2, an optical fiber 3, and a network cable 4.
  • the optical module 2 includes an electrical interface and an optical interface.
  • the optical interface of the optical module 2 is connected to the optical fiber 3 to establish a bidirectional optical signal connection with the optical fiber 3.
  • the electrical interface of the optical module 2 is connected to the optical network terminal device 1 through the optical module interface 5 to establish a bidirectional electrical signal connection with the optical network terminal device 1.
  • the optical signal from the optical fiber 3 is converted into an electrical signal by the optical module 2 and then input into the optical network terminal device 1, or the electrical signal from the optical network terminal device 1 is converted into an optical signal by the optical module 2 and input into the optical fiber 3.
  • the optical network terminal device 1 has a network cable interface 6 for accessing the network cable 4 and establishing a bidirectional electrical signal connection with the network cable 4. Specifically, the optical network terminal device 1 transmits the signal from the optical module 2 to the network cable 4, or the optical network terminal device 1 transmits the signal from the network cable 4 to the optical module 2.
  • FIG5 shows an exploded schematic diagram of an optical module 2.
  • the optical module 2 includes a housing 21 having a receiving cavity, a circuit board 22 disposed in the receiving cavity of the housing 21, an optical receiving module (receiver optical subassembly, ROSA) 23, an optical transmitting module (transmitter optical subassembly, TOSA) 24 and other electronic components.
  • ROSA optical receiving module
  • TOSA optical transmitting module
  • the housing 21 is provided with a first opening 2a and a second opening 2b, one of which is for electrical connection.
  • the plug-in end of the circuit board 22 extends from the electrical interface to the outside of the shell 21 to be inserted into the optical module interface 6 of the optical network terminal device 1; the other opening is an optical interface, and the optical fiber 3 can pass through the optical interface to be connected to the optical receiving module 23 in the shell 21.
  • the optical fiber 3 can be directly connected to the optical receiving module 23, or an adapter can be provided, that is, the optical fiber 3 and the optical receiving module 23 are connected through the adapter.
  • the optical receiving module 23 may include: a circuit board, a photodetector disposed on the circuit board, and a processor.
  • the photodetector directly converts the optical signal into an electrical signal, and the processor is used to process the converted electrical signal.
  • the specific application scenarios of the photodetector involved in the present application are not particularly limited and may include a light receiving module with the photodetector.
  • the working mechanism of the photodetector is basically as follows: light of a certain wavelength acts on the semiconductor PN junction (PN junction), and the energy of the incident photon is greater than or equal to the bandgap width of the semiconductor material, which excites electron-hole pairs (i.e., photogenerated carriers), generates an electromotive force effect on both sides of the depletion region (potential barrier region), and is converted into a current signal when connected to an external circuit, thereby realizing the conversion of electrical signals into optical signals.
  • PN junction semiconductor PN junction
  • the energy of the incident photon is greater than or equal to the bandgap width of the semiconductor material, which excites electron-hole pairs (i.e., photogenerated carriers), generates an electromotive force effect on both sides of the depletion region (potential barrier region), and is converted into a current signal when connected to an external circuit, thereby realizing the conversion of electrical signals into optical signals.
  • photodetectors With the development of optoelectronic technology, the performance requirements for photodetectors are becoming increasingly higher. For example, they not only need to have high quantum efficiency and sensitivity, as well as high responsiveness, but also need to achieve low power consumption so that photodetectors can be used in different scenarios.
  • the embodiments of the present application provide some photoelectric detectors that can achieve the above technical effects.
  • the structure, working principle, and corresponding preparation method of the photoelectric detectors provided in the embodiments of the present application are introduced below in conjunction with the accompanying drawings.
  • FIG6 is a top view of a photoelectric detector provided in an embodiment of the present application
  • FIG7 is a cross-sectional view taken along the line A-A of FIG6 .
  • the photodetector 7 provided in the embodiment of the present application includes a semiconductor substrate 701, and the semiconductor substrate 701 can be divided into a first region Q1 and a second region Q2.
  • the first region Q1 and the second region Q2 can be adjacent to each other, and semiconductor devices, such as photodiodes and some electronic devices electrically connected to the photodiodes, can be formed on the first region Q1 and the second region Q2, respectively.
  • semiconductor devices such as photodiodes and some electronic devices electrically connected to the photodiodes, can be formed on the first region Q1 and the second region Q2, respectively.
  • the semiconductor substrate 701 does not have a boundary between the first region Q1 and the second region Q2.
  • the embodiment of the present application is to vividly describe the location of some electronic devices, and the custom semiconductor substrate 701 may include the first region Q1 and the second region Q2.
  • the semiconductor substrate 701 involved in the embodiment of the present application may be at least one of a germanium substrate, a silicon germanium substrate, a gallium nitride substrate or an indium gallium arsenide substrate.
  • a first well region 702 is provided on the first region Q1 of the semiconductor substrate 701, and a first electrode doping region 703 and a second electrode doping region 704 are formed on the surface of the first well region 702 away from the semiconductor substrate 701.
  • One of the first electrode doping region 703 and the second electrode doping region 704 is an anode doping region, and the other is a cathode doping region.
  • the semiconductor substrate 701 may be a P-type doped substrate
  • the first well region 702 may be an N-type well region
  • the first electrode doping region 703 may be a P-type doping region
  • the second electrode doping region 704 may be an N-type doping region.
  • the first well region 702 and the first electrode doping region 703 form a photodiode (PD1 as shown in Figure 7), and the first well region 702 and the semiconductor substrate 701 form another photodiode (PD2 as shown in Figure 7). That is, this photodetector includes the first photodiode PD1 and the second photodiode PD2.
  • an oxide buried layer 706 and a semiconductor layer 707 are sequentially stacked, a first electrode 708 and a second electrode 709 of the transistor Tr are formed in the semiconductor layer 707, a portion of the semiconductor layer 707 between the first electrode 708 and the second electrode 709 forms a channel layer 710 of the transistor Tr, a gate 712 of the transistor Tr is disposed on one side of the channel layer 710 away from the oxide buried layer 706, and the gate 712 and the channel layer 707 are electrically isolated by a gate dielectric layer 711. Furthermore, the first electrode doping region 703 is electrically connected to the gate 712.
  • One of the first electrode 708 and the second electrode 709 of the transistor Tr involved in the embodiment of the present application is a source, and the other is a drain.
  • the source and the drain can be distinguished according to the current method. For example, if the current flows from the first electrode 708 to the second electrode 709, the first electrode 708 is the drain, and the second electrode 709 is the source.
  • the transistor Tr given in the embodiment of the present application is a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the transistor Tr shown in FIG. 7 above can select an NMOS (N-channel metal oxide semiconductor, N-channel metal oxide semiconductor) tube, or can select a PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) tube. Oxide semiconductor) tube.
  • the transistor Tr integrated on the semiconductor substrate 701 is a dual-gate transistor, in which the gate 712 serves as the first gate (also called the top gate) of the transistor Tr, and the semiconductor substrate 701 serves as the second gate (also called the bottom gate) of the transistor Tr.
  • the photodetector includes a first photodiode PD1, a second photodiode PD2 and a transistor Tr, wherein the cathode of the first photodiode PD1 is electrically connected to the cathode of the second photodiode PD2 and is electrically connected to a power supply, the anode of the first photodiode PD1 is electrically connected to the first gate VG of the transistor Tr, and the anode of the second photodiode PD2 is electrically connected to the second gate VBG of the transistor Tr.
  • the source of the transistor Tr may be grounded.
  • the second electrode doping region 704 is used to connect to a power supply voltage Vc, one of the first electrode 708 and the second electrode 709 is connected to VD, and the other is grounded.
  • the transistor Tr, the first photodiode PD1, and the second photodiode PD2 are monolithically integrated to improve the integration of the photodetection system.
  • the semiconductor substrate 701, the buried oxide layer 706, and the semiconductor layer 707 form a silicon-on-insulator SOI substrate, that is, the transistor Tr is integrated on the silicon-on-insulator SOI substrate;
  • the first well region 702 can be understood as a bulk silicon substrate, that is, the PN junction of the photodiode is formed on the bulk silicon substrate, and the transistor Tr and the photodiode are integrated on a hybrid substrate.
  • the semiconductor substrate 701 and the semiconductor layer 707 are physically and electrically isolated by the oxide buried layer 706 in the silicon-on-insulator SOI substrate, the power consumption of the transistor Tr can be reduced, the parasitic capacitance can be reduced, and the radiation resistance can be increased.
  • the first well region 702 is used as a light absorption layer of the photodiode. Compared with using a thinner silicon layer in a silicon SOI substrate on an insulating layer as a light absorption layer, it can increase the light absorption amount, thereby improving the light quantum efficiency and the photoelectric conversion efficiency.
  • the semiconductor substrate 701 serving as the bottom gate of the transistor also forms a PN junction with the first well region 702, when a bias voltage is applied to the second electrode doping region 704, PD1 and PD2 simultaneously operate in a reverse biased state. At this time, the depletion region of the photodiode widens, and light can be absorbed through the first well region 702 to generate photogenerated electron-hole pairs.
  • the aggregation of photogenerated carriers in the first electrode doping region 703 triggers an increase in the potential of the gate 712 of the transistor Tr on the silicon SOI substrate on the insulating layer, and the aggregation of photogenerated carriers toward the interface between the semiconductor substrate 701 and the first well region 702 triggers an increase in the potential of the semiconductor substrate 701 serving as the bottom gate of the transistor Tr.
  • This will cause the threshold voltage of the transistor Tr to decrease and the conductivity of the channel layer 710 to increase, thereby significantly increasing the drain current of the transistor Tr.
  • This process realizes the conversion of photons absorbed by the photodiode into conductive electrons and holes, and adjusts the threshold voltage of the transistor Tr through carrier aggregation, further amplifying the photocurrent, so that under the same lighting conditions, the photocurrent obtained by the photodetector provided in the embodiment of the present application is much higher than the photocurrent of the photodiode in the prior art, that is, the photoelectric responsivity and quantum efficiency are greatly improved.
  • the photodetector provided in the embodiment of the present application adopts the threshold voltage adjustment mechanism of the transistor Tr to improve the photoelectric response.
  • the threshold voltage of the transistor Tr can be adjusted by adjusting the doping concentration of the first well region 702, the semiconductor substrate 701, the first electrode doping region 703 and the second electrode doping region 704, as well as the voltage applied to the second electrode doping region 704 and the voltage applied to the source and drain of the transistor Tr.
  • the photoelectric detectors shown in Figures 6 to 8 provided in the embodiments of the present application, while achieving photosensitivity and amplification, can not only meet the requirements of high quantum efficiency and high sensitivity, but can also achieve the characteristics of low leakage current, low power consumption, high gain, radiation resistance, and high reliability in extreme environments.
  • the first well region 702 serves as an absorption layer for the incident light, and the incident light basically does not pass through the semiconductor layer 707 and the buried oxide layer 706 to enter the photodetector.
  • the incident light is almost only absorbed by the two reverse-biased PN junctions at the body silicon position and converted into electrical signals, thereby improving the absorption efficiency of the photodetector for the incident light, reducing losses, and improving the photoelectric response.
  • the semiconductor substrate 701 is a P-type substrate
  • the first well region 702 is an N-type well region
  • the first electrode doping region 703 is P-type doped
  • the second electrode doping region 704 is N-type doped
  • the first pole 708 and the second pole 709 of the transistor Tr are respectively N-type doped.
  • FIG9 shows a cross-sectional view of another photodetector 7 provided in an embodiment of the present application.
  • the semiconductor substrate 701 is an N-type substrate
  • the first well region 702 is a P-type well region
  • the first electrode doping region 703 is N-type doped
  • the second electrode doping region 704 is P-type doped
  • the first pole 708 and the second pole 709 of the transistor Tr are respectively P-type doped.
  • the photodetector includes a first photodiode PD1, a second photodiode PD2 and a transistor Tr, wherein the anode of the first photodiode PD1 is electrically connected to the anode of the second photodiode PD2 and is electrically connected to a power supply, the cathode of the first photodiode PD1 is electrically connected to the first gate VG of the transistor Tr, and the cathode of the second photodiode PD2 is electrically connected to the second gate VBG of the transistor Tr.
  • a shallow trench isolation layer (STI) 719 is also provided on the semiconductor substrate 701, and the stacked semiconductor layer 707 and the buried oxide layer 706 are physically and electrically isolated from the first well region 702 by the shallow trench isolation layer 719.
  • STI shallow trench isolation layer
  • the photodetector also includes a first electrode metal contact layer 714 , a second electrode metal contact layer 715 , a first pole metal contact layer 716 and a second pole metal contact layer 717 .
  • the first electrode metal contact layer 714 is arranged on the first electrode doping region 703 (that is, arranged on the side of the first electrode doping region 703 away from the semiconductor substrate 701); the second electrode metal contact layer 715 is arranged on the second electrode doping region 704 (that is, arranged on the side of the second electrode doping region 704 away from the semiconductor substrate 701); the first pole metal contact layer 716 is arranged on the first pole 708 (that is, arranged on the side of the first pole 708 away from the buried oxide layer 706), and the second pole metal contact layer 717 is arranged on the second pole 709 (that is, arranged on the side of the second pole 709 away from the buried oxide layer 706).
  • the first well region 702, the first electrode doping region 703, the second electrode doping region 704, the first pole 708, the second pole 709, the first electrode metal contact layer 714, the second electrode metal contact layer 715, the first pole metal contact layer 716 and the second pole metal contact layer 717 can all be integrated on the semiconductor substrate 701 by using a front end of line (FEOL) process.
  • FEOL front end of line
  • a metal interconnection layer 713 can be set on the side of the gate 712 facing away from the semiconductor substrate 701, and on the side of the first electrode metal contact layer 714 facing away from the semiconductor substrate 701, and the gate 712 is electrically connected to the first electrode metal contact layer 714 through the metal interconnection layer 713.
  • the metal interconnect layer 713 can be manufactured using a back end of line (BEOL) process.
  • BEOL back end of line
  • the photodetector may further include a gate sidewall 718 disposed on the side of the gate 712.
  • the gate sidewall 718 may cover the side of the gate 712, or may cover the side of the gate dielectric layer 711 as shown in FIG7 .
  • FIG11 is a cross-sectional view of another photodetector provided in an embodiment of the present application.
  • the photodetector 7 in this embodiment further includes a second well region 705 , which is disposed on the second region Q2 of the semiconductor substrate 701 and between the semiconductor substrate 701 and the buried oxide layer 706 .
  • the doping type of the second well region 705 is the same as the doping type of the semiconductor substrate 701.
  • both are P-type doping
  • the doping concentration of the second well region 705 is greater than the doping concentration of the semiconductor substrate 701.
  • the second well region 705 is a heavily doped region
  • the semiconductor substrate 701 is a lightly doped region.
  • the second photodiode includes not only a PN junction formed by the first well region 702 and the second well region 705 , but also a PIN junction formed by the first well region 702 , the semiconductor substrate 701 and the second well region 705 .
  • FIG. 13A simply shows that when the photodetector 7 does not include the second well region 705 , the effective detection region of the second photodiode is the region T1 shown in FIG. 13A .
  • FIG13B simply shows that when the photodetector 7 includes the second well region 705, that is, the second photodiode includes not only a PN junction but also a PIN junction, the effective detection region of the second photodiode includes the T2 region and the T3 region as shown in FIG13B.
  • the approximate position of the effective detection area is only exemplarily drawn, and does not constitute an absolute limitation on the effective detection area.
  • the effective detection area can also be extended to the periphery of the T1 area.
  • the effective detection area can also be extended to the periphery of the T2 area and the T3 area.
  • the larger number of photogenerated carriers generated will be transmitted to the top gate (such as the gate 712 in Figure 11) and to the bottom gate (such as the second well region 705 and the semiconductor substrate 701 in Figure 11), causing the transistor threshold voltage to further decrease and the channel layer conductivity to further increase, so that the drain current of the transistor is further increased, thereby achieving a significant amplification of the photocurrent.
  • the semiconductor layer 707 and the first well region 702 are electrically isolated by the shallow trench isolation layer 719 .
  • the adjacent first well region 702 and second well region 705 are in contact with each other.
  • the width d1 of the shallow trench isolation layer 719 is between 0.1 ⁇ m and 10 ⁇ m.
  • the depth h1 of the shallow trench isolation layer 719 is between 200 nm and 1 ⁇ m.
  • the present application does not limit the width and depth of the shallow trench isolation layer 719, and any range is within the protection scope of the present application.
  • FIG14 is a top view of FIG11, wherein the length S of the channel layer 710 is between 10 nm and 1 ⁇ m, the width d2 of the channel layer 710 is between 7 nm and 400 nm, and the depth h2 of the channel layer 710 is between 7 nm and 200 nm.
  • the distance d3 between the first electrode doping region 703 and the second electrode doping region 704 may be between 100 nm and 10000 nm.
  • the doping element may be at least one of Group III elements such as boron, aluminum, gallium, and indium.
  • the doping element may be at least one of the elements of the Vth main group, such as phosphorus and arsenic.
  • the first electrode doping region 703 and the second electrode doping region 704 are heavily doped regions compared to the first well region 702.
  • the doping concentration of the first well region 702 is ⁇ 1, and 10 17 cm -3 ⁇ ⁇ 1 ⁇ 10 19 cm -3
  • the doping concentration of the first electrode doping region 703 and the second electrode doping region 704 is ⁇ 4, and 10 19 cm -3 ⁇ ⁇ 4 ⁇ 10 21 cm -3 .
  • the first electrode 708 and the second electrode 709 are heavily doped regions compared to the second well region 705.
  • the doping concentration of the second well region 705 is ⁇ 2, and 10 17 cm -3 ⁇ ⁇ 2 ⁇ 10 19 cm -3 ; the doping concentration of the first electrode 708 and the second electrode 709 is ⁇ 3, and 10 19 cm -3 ⁇ ⁇ 3 ⁇ 10 21 cm -3 .
  • the semiconductor substrate 701 may be a lightly doped region.
  • the doping concentration of the semiconductor substrate 701 is ⁇ 5, and 10 15 cm ⁇ 3 ⁇ 5 ⁇ 10 17 cm ⁇ 3 .
  • the above is an exemplary description of the doping concentrations of the first well region 702 , the second well region 705 , the first electrode doping region 703 , the second electrode doping region 704 , the first pole 708 , and the second pole 709 .
  • other ranges may also be selected.
  • Table 1 below provides a comparison of some performance indicators of the photoelectric detector using the embodiment of FIG11 and the photoelectric detector involved in the related art. For details, see Table 1 below.
  • the substrate when the substrate adopts bulk silicon, it involves silicon-based PN junction photodiodes and avalanche photodiodes APD formed by utilizing the avalanche multiplication effect; when the substrate adopts silicon-on-insulator SOI, it involves photodetectors including metal oxide semiconductor field effect transistors MOSFET, avalanche photodiodes APD formed by utilizing the avalanche multiplication effect and ICPD formed by utilizing the interface coupling effect, as well as photodetectors formed using Si nanowires and Si microwires; the substrate type provided in the embodiments of the present application can be referred to as a hybrid substrate comprising bulk silicon and silicon-on-insulator SOI.
  • 650 nm, 400-1000 nm, and 520 nm indicate the wavelength of light irradiated onto the photodetector.
  • the wavelength of incident light of the APD formed by the avalanche multiplication effect is 400 nm
  • the wavelength of incident light used in the embodiment of the present application is 520 nm.
  • 5V, 0.2V, and 8.2V in Table 1 indicate the operating voltages applied to the photodetector.
  • the operating voltage using the PN structure can be 5V
  • the operating voltage of the embodiment of the present application can be 0.5V.
  • the operating voltage here is the voltage Vc applied to the second electrode doping region 704 of the photodiode shown in FIG. 11.
  • the photodetector provided in the embodiment of the present application When the photodetector provided in the embodiment of the present application is used, and the light wavelength is 520nm, and the working voltage Vc is only 0.5V, the photoelectric responsivity reaches about 10 5 A/W. Compared with the ICPD formed by the interface coupling effect with the same light wavelength, although the photoelectric responsivity of the ICPD also reaches about 10 5 A/W, the working voltage Vc is as high as 5V or even 20V. Compared with the photodetector provided in the present application, the photodetector of the present application can significantly reduce the working voltage Vc, reduce power consumption, and achieve low power consumption and high photoelectric responsivity.
  • the photodetector provided in the embodiment of the present application When the photodetector provided in the embodiment of the present application is used, the light wavelength is 520nm, and the working voltage Vc is only 0.5V, the photoelectric responsivity reaches about 10 5 A/W. Compared with the photodetector using Si nanowires and Si microwires, when the working voltage Vc of Si nanowires and Si microwires is 1V, the photoelectric responsivity is only about 10A/W. Obviously, the photodetector involved in the embodiment of the present application can achieve a higher photoelectric responsivity at a lower working voltage.
  • the photodetector made of a hybrid substrate provided in the present application can obtain a higher photoelectric response at a smaller operating voltage Vc, thereby improving the working performance of the photodetector.
  • FIG15 shows a curve of the change of the working voltage Vc applied to the second electrode doping region and the photoelectric responsivity R when the photodetector provided in the embodiment of the present application is used.
  • the horizontal axis of the curve indicates the working voltage Vc applied to the second electrode doping region, and the vertical axis indicates the photoelectric responsivity R.
  • the photoelectric responsivity R increases with the increase of the operating voltage Vc and can reach the order of 10 5 A/W. Moreover, when the operating voltage Vc is 0.5V, the photoelectric responsivity R can reach 1 ⁇ 10 5 A/W. When the operating voltage Vc is 1V, the photoelectric responsivity R is even close to 2 ⁇ 10 5 A/W.
  • the photoelectric detector provided in the embodiment of the present application can achieve a higher photoelectric response when a relatively small operating voltage is applied.
  • the horizontal axis indicates the operating voltage Vc applied to the second electrode doping region, and the vertical axis indicates the drain current ID .
  • Curve (1) shows the relationship between the drain current ID and VC when the wavelength of the incident light is 520nm and the light intensity is 1mW/ cm2 ;
  • Curve (2) shows the relationship between the drain current ID and VC in the dark state.
  • FIG17 exemplarily shows a flowchart of the process of preparing a photodetector.
  • Step S1 removing part of the buried oxide layer and part of the top silicon on the bottom silicon of the silicon substrate on the insulating layer, and forming a first well region at the position after the buried oxide layer and the top silicon are removed.
  • Silicon on insulation layer SOI is used as raw material for processing and manufacturing.
  • Step S2 forming a first electrode doping region and a second electrode doping region in the first well region away from the surface layer of the bottom silicon, and forming a first pole and a second pole of a transistor in the top silicon, and making the portion of the top silicon located between the first pole and the second pole form a channel layer of the transistor, and arranging a gate of the transistor on a side of the channel layer away from the buried oxide layer, one of the first electrode doping region and the second electrode doping region is an anode doping region, and the other is a cathode doping region, so as to obtain a transistor, a first photodiode and a second photodiode.
  • a photodiode is formed on the bulk silicon, and a transistor is formed on the silicon substrate on the insulating layer.
  • Step S3 electrically connecting the first electrode doping region and the gate; wherein the first photodiode includes the first electrode doping region and the first well region, and the second photodiode includes the first well region and underlying silicon.
  • step S1 and step S3 are introduced below in conjunction with the accompanying drawings.
  • 18A1 to 18H show the process structure after each step is completed in the process of manufacturing a photoelectric detector according to an embodiment of the present application.
  • Fig. 18A2 is a cross-sectional view taken along the line B-B of Fig. 18A1.
  • a silicon-on-insulator SOI substrate is prepared.
  • the silicon-on-insulator SOI substrate includes a stacked bottom silicon layer and a top silicon layer, and an oxide buried layer disposed between the bottom silicon layer and the top silicon layer.
  • the thickness of the oxide buried layer may be 10 nm to 1000 nm.
  • the bottom silicon may be a lightly doped P-type substrate, or may be a lightly doped N-type substrate.
  • the doping concentration of the bottom silicon may be 10 15 cm -3 ⁇ 10 17 cm -3 .
  • Figure 18B2 is a cross-sectional view taken along the C-C direction of Figure 18B1.
  • the top silicon and the buried oxide layer on the first region Q1 of the bottom silicon are removed to form a vacancy on the first region Q1 of the bottom silicon, and the buried oxide layer and the top silicon are retained in the second region Q2 of the bottom silicon adjacent to the first region Q1.
  • the etching process may be dry etching or wet etching. Dry etching may use fluorine-based or halogen element gases, such as SF6, CHF3, HBr or Cl2, etc., while wet etching may use solutions such as TMAH and KOH.
  • the silicon on insulating layer SOI may be cleaned.
  • Figure 18C2 is a cross-sectional view taken along the D-D direction of Figure 18C1.
  • a first well region 702 is formed at the vacant position formed in Figure 18B2, and a shallow trench isolation layer 719 is formed.
  • epitaxial growth technology may be used to grow an epitaxial layer.
  • the epitaxial growth technology may be implemented by physical vapor deposition, chemical vapor deposition, or molecular beam epitaxy.
  • the first well region 702 can be formed by performing an ion implantation process on the epitaxial layer.
  • the doping type of the first well region 702 is opposite to the doping type of the underlying silicon. For example, if the first well region 702 is a P-type well region, the underlying silicon is N-type doped.
  • the ion implantation concentration of the first well region 702 is 10 17 cm ⁇ 3 to 10 19 cm ⁇ 3 .
  • a hybrid substrate including bulk silicon (first well region 702) and silicon-on-insulator SOI is formed as shown in FIGS. 18C1 and 18C2.
  • a shallow trench isolation layer 719 may be formed.
  • a photolithography and etching process may be first used to open a groove at the interface between the top silicon layer and the buried oxide layer and the first well region 702 , and then fill the groove with an oxide layer to form the shallow trench isolation layer 719 .
  • the shallow trench isolation layer 719 may be in a ring structure and disposed on the second region Q2 of the underlying silicon. In this way, the electronic device formed on the second region Q2 may be electrically isolated from the adjacent electronic devices.
  • Figure 18D2 is a cross-sectional view of Figure 18D1 along the EE direction.
  • a polysilicon gate 720 of a metal oxide semiconductor transistor MOSFET can be manufactured on the top silicon by using the front-end process.
  • a gate oxide dielectric layer may be formed first, and then a polysilicon gate may be formed on the gate oxide dielectric layer.
  • the gate oxide dielectric layer may be made of a high-K value material such as hafnium oxide or silicon oxide.
  • the thickness of the gate oxide dielectric layer may be selected to be 1 nm to 100 nm.
  • Figure 18E2 is a cross-sectional view taken along the F-F direction of Figure 18E1.
  • a first electrode 708 and a second electrode 709 of the transistor Tr are formed, as well as a first electrode doping region 703 and a second electrode doping region 704 are formed.
  • the first pole 708 and the second pole 709 can be formed by epitaxial process or ion implantation process, and the first electrode doping region 703 and the second electrode doping region 704 can be formed. Then, a high temperature annealing process is used to activate the impurities and repair the process defects introduced by the ion implantation.
  • the doping element may be arsenic or phosphorus ions, and the doping concentration is 10 20 cm -3 to 10 21 cm -3 .
  • the ion activation annealing temperature is generally between 900 degrees and 1200 degrees, and the time is between 1 second and 10 seconds.
  • Figure 18F2 is a cross-sectional view taken along the G-G direction of Figure 18F1.
  • a replacement metal gate process is adopted, that is, the polysilicon gate 720 manufactured in Figures 18E1 and 18E2 is replaced by a metal gate to form a metal gate 712.
  • the gate 712 can be made of at least one of metal materials such as gold, platinum, and aluminum.
  • a gate spacer 718 may be manufactured on the side of the gate 712 .
  • Figure 18G2 is a cross-sectional view of Figure 18G1 along the H-H direction.
  • a first pole metal contact layer 715, a second pole metal contact layer 717, a first electrode metal contact layer 714 and a second electrode metal contact layer 715 are manufactured.
  • these metal contact layers can be formed by evaporation or sputtering processes.
  • metal deposition can use physical vapor deposition or evaporation methods, and the metals that can be selected are aluminum, nickel, titanium, gold, etc.
  • annealing is performed at an annealing temperature between 300 degrees and 900 degrees for 10-120 seconds.
  • a metal interconnection layer 13 is formed so that the gate 712 is electrically connected to the first electrode metal contact layer 714 through the metal interconnection layer 13 .
  • the metal interconnection layer 13 may be made of copper or aluminum.
  • a silicon-on-insulator SOI substrate can be used as a raw material to obtain a hybrid substrate containing bulk silicon and silicon-on-insulator, and the bulk silicon is used as the light absorption layer of the photodiode to improve the light absorption efficiency, and the transistor is made in the silicon-on-insulator to obtain low power consumption.
  • 19A to 19F show the process structure after each step is completed in the process of manufacturing another photoelectric detector according to an embodiment of the present application.
  • a well layer is formed at a position of the bottom silicon of the silicon on the insulating layer close to the buried oxide layer.
  • the well layer can be formed by ion implantation.
  • Boron or BF 3 can be selected as the source of ion implantation, the energy is between 10keV and 100keV, the implantation dose can be between 10 10 cm -2 and 10 13 cm -2 , and the doping concentration of the well layer finally formed is between 10 17 cm -2 and 10 19 cm -2 .
  • the top silicon, the buried oxide layer and the well layer above the first region Q1 of the bottom silicon are removed, and a first well region 702 is formed at the vacant position after the removal, and a second well region 705 is formed in the well layer located on the second region Q2 of the bottom silicon.
  • a shallow trench isolation layer 719 is formed.
  • the first electrode 708 , the second electrode 709 , the first electrode doping region 703 and the second electrode doping region 704 may be formed first.
  • an epitaxial process or an ion implantation process can be used to form the first electrode 708 and the second electrode 709, as well as the first electrode doping region 703 and the second electrode doping region 704. Then, a high temperature annealing process is used to activate the impurities and repair the process defects introduced by the ion implantation.
  • a polysilicon gate 720 of a metal oxide semiconductor transistor MOSFET is fabricated on the channel layer of the top silicon layer between the first electrode 708 and the second electrode 709 .
  • a gate oxide dielectric layer may be formed first, and then a polysilicon gate may be formed on the gate oxide dielectric layer.
  • a replacement metal gate process is used, that is, the polysilicon gate 720 made in FIG. 19D is replaced by a metal gate to form a metal gate 712 .
  • the above preparation method adopts the gate-first process, that is, after the polysilicon gate 720 is prepared, ion implantation is performed to form the first electrode 708 and the second electrode 709, as well as the first electrode doping region 703 and the second electrode doping region 704.
  • This preparation method adopts the gate-last process, that is, the first electrode 708 and the second electrode 709 are formed first, and The first electrode doping region 703 and the second electrode doping region 704 are formed, and then a polysilicon gate 720 is formed.
  • a first pole metal contact layer 716, a second pole metal contact layer 717, a first electrode metal contact layer 714, a second electrode metal contact layer 715, and a metal interconnection layer 713 are prepared.
  • a photodetector structure including a first well region 702 and a second well region 705 is prepared.
  • Table 2 below shows the performance comparison of some related photoelectric detectors and the photoelectric detector provided in the embodiment of the present application, as shown in Table 2 below:

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Manufacturing & Machinery (AREA)
  • Light Receiving Elements (AREA)

Abstract

一种光电探测器（7）、光接收模块（23）及电子设备，该光电探测器（7）包括体硅和绝缘层上硅的混合衬底，并将晶体管形成在绝缘层上硅衬底上，将第一光电二极管和第二光电二极管形成在体硅衬底上，第一光电二极管包括第一电极掺杂区（703）和第一阱区（702），栅极（712）作为晶体管的第一栅极，半导体衬底（701）作为晶体管的第二栅极，第一光电二极管的第一电极掺杂区（703）与晶体管的栅极（712）电连接，半导体衬底（701）和第一阱区（702）形成PN结，即构成第二光电二极管。这样不仅增强对入射光的吸收，获得较高的量子效率和灵敏度，还可以提高光电响应度，降低漏电流、减小寄生电容，降低功耗。

Description

光电探测器、光接收模块及电子设备
本申请要求于2022年10月31日提交国家知识产权局、申请号为202211351084.4、发明名称为“光电探测器、光接收模块及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及光电转换技术领域，尤其涉及一种光电二极管和晶体管单片集成的光电探测器，和包含该光电探测器的光接收模块，以及光电探测器的制备方法，还有包含光接收模块的电子设备。
背景技术
光电探测器具备将光信号直接转换为电信号的能力，因此，被广泛应用在光通讯、图像传感和光谱分析等领域。
硅基PN结光电二极管(photoelectric detector，PD)是最基本、应用最广泛的光电探测器之一。其结构是将PN结形成在体硅衬底上，通过对PN结施加反偏电压，使得光照入射产生大量电子空穴对，载流子在耗尽区的外加电场作用下分离，形成光电流，从而实现光信号和电信号的转换。然而，随着集成光路和光电集成系统(例如：硅光网络、光开关、可见光通讯等)的发展，对光电二极管提出了低功耗、高速度、响应快的性能要求，使得建立于体硅衬底上的PN结光电二极管难以满足要求。
绝缘层上硅(Silicon-On-Insulator，SOI)衬底，如图1，图1示出的是将PN结光电二极管形成在SOI衬底上的结构图。在SOI衬底结构中，由于在底层硅和顶层硅之间引入氧化埋层，从而具备降低功耗、减少寄生电阻、光电响应快的优势，被广泛应用。
但是，见图1，该种结构中的光电二极管被集成在顶层硅中，是利用顶层硅作为光吸收层，为了降低短沟道效应，通常顶层硅厚度(沿图1所示Z方向尺寸)较薄(比如，22nm以下)，这样，会使得大部分入射光直接穿透顶层硅所形成的感光区，而不能被感光区有效吸收，从而导致建立在SOI衬底上的光电探测器的量子效率较低、灵敏度较差。
为了提升量子效率和灵敏度，在一些相关技术中，可以利用雪崩倍增机制直接提升集成于SOI衬底的顶层硅内的光电二极管的量子效率和探测灵敏度。该种方式需要较大的反向驱动电压(比如，大于8.2V)，这样的话，不利于降低光电探测器的功耗，即就是此技术不能在拥有高量子效率和高灵敏度，以及高响应度的同时满足低功耗特性。
在另外一些相关技术中，基于SOI技术的深耗尽效应和界面耦合效应，可以利用位于氧化埋层下方的厚度较大的底层硅进行入射光的捕获吸收，以克服SOI衬底顶层硅厚度太薄所导致的大部分入射光直接穿过顶层硅所构成的感光区，而不能被高效吸收的缺陷。启动SOI衬底的深耗尽效应，需要较大的反向驱动电压(比如，大于5V)，如此的话，同样的，不利于降低光电探测器的功耗，也就是不能在拥有高量子效率和高灵敏度，以及高响应度的同时满足低功耗特性。
发明内容
本申请提供一种光电探测器，和包含有光电探测器的光接收模块，以及光电探测器的制备方法，还提供包含光接收模块的电子设备。主要目的提供一种不仅可以拥有较高的量子效率和灵敏度，以及较高的响应度，还可以实现低功耗的光电探测器。
为达到上述目的，本申请的实施例采用如下技术方案：
一方面，本申请提供了一种光电探测器，该光电探测器包括：半导体衬底、晶体管、第一光电二极管和第二光电二极管；半导体衬底的第一区域上设置有第一阱区，第一阱区中且背离半导 体衬底的表层形成有第一电极掺杂区和第二电极掺杂区，第一电极掺杂区和第二电极掺杂区中的一个为阳极掺杂区，另一个为阴极掺杂区；半导体衬底的第二区域上，且沿着背离半导体衬底的方向，依次堆叠有氧化埋层和半导体层，半导体层中形成有晶体管的第一极和第二极，半导体层中的位于第一极和第二极之间的部分形成晶体管的沟道层，沟道层的背离氧化埋层的一侧设置有晶体管的栅极；第一电极掺杂区与栅极电连接；第一光电二极管包括第一电极掺杂区和第一阱区，第二光电二极管包括第一阱区和半导体衬底。
在本申请给出的光电探测器中，由于阳极掺杂区和阴极掺杂区形成在半导体衬底上的第一阱区中，该第一阱区可以被认为体硅衬底，通过利用体硅的厚硅(即厚度较大的第一阱区)作为光电二极管的光吸收层，从而增强对入射光吸收，以获得较高的量子效率和灵敏度。
另外，包含半导体衬底、氧化埋层和半导体层的结构，可以被认为绝缘层上硅SOI衬底结构，该半导体衬底可以被认为是底层硅，半导体层可以被认为是顶层硅，也就是，本申请是将晶体管形成在绝缘层上硅SOI衬底上，由于在绝缘层上硅SOI的半导体衬底和半导体层之间被氧化埋层隔离开，如此的话，可以降低漏电流、减小寄生电容。
还有，在本申请中，栅极作为晶体管的一个栅极，半导体衬底可以被认为是晶体管的又一个栅极，即该晶体管为一种双栅结构，第一光电二极管的第一电极掺杂区与晶体管的栅极(可以被称为顶栅)电连接，第一阱区和半导体衬底(可以被称为底栅)电连接，并可以形成第二光电二极管的PN结，以及，第一电极掺杂区和第一阱区可以形成第一光电二极管的PN结，那么，当第一光电二极管和第二光电二极管的PN结均处于反偏状态时，耗尽区发生展宽，实现对入射光的有效吸收，并产生光生电子空穴对，光生载流子会在耗尽区内建电场的作用下，向着建立在SOI衬底的顶栅和底栅聚集。与此同时，聚集在顶栅和底栅的光生载流子，会直接导致晶体管阈值电压的下降和沟道层电导的增加，从而导致晶体管漏极电流的显著增加，实现光电流的内部放大；并且，使得同样光照条件下，本申请得到的光电流远高于绝缘层上硅SOI衬底上的光电探测器的光电流，即光电响应度和量子效率可以得到大幅提升。
所以，本申请给出的光电探测器中，将晶体管和第一光电二极管，以及第二光电二极管在单片衬底上共集成，同时实现感光和放大，并且，不仅可以满足高量子效率、高灵敏度，高光电响应度，还具有低漏电流、低功耗、高增益、抗辐射，以及高可靠性的特性。
在一种可能的实现方式中，第二光电二极管还包括第二阱区；第二阱区设置在第二区域上，且位于半导体衬底和氧化埋层之间；第二阱区的掺杂类型与半导体衬底的掺杂类型相同，第二阱区的掺杂浓度大于半导体衬底的掺杂浓度。
在一种可能的实现方式中，第一阱区和第二阱区形成第二光电二极管的PN结；第二阱区、半导体衬底和第一阱区形成第二光电二极管的PIN结。
通过在在半导体衬底和氧化埋层之间设置第二阱区，以使得第二光电二极管不仅包括PN结，还包括了PIN结，使得该光电探测器具有更宽的有效探测区域。这样的话，当外加电压使得PIN结和PN结反偏时，光生载流子会在电场作用下向半导体衬底和栅极聚集，导致晶体管阈值电压的明显下降和沟道层电导的明显增加。
在一种可能的实现方式中，光电探测器还包括浅槽隔离层；半导体层与第一阱区之间，以及氧化埋层和第一阱区之间均被浅槽隔离层电隔离开，且第一阱区和第二阱区接触。
通过浅槽隔离层将半导体层与第二阱区，以及将氧化埋层与第二阱区进行物理和电隔离，除外，浅槽隔离层并未贯通至第一阱区和第二阱区之间，也就是，第一阱区和第二阱区接触，光生载流子会朝着第二阱区聚集，并与聚集在栅极(顶栅)的光生载流子共同作用，实现光电流的放大。
在一种可能的实现方式中，浅槽隔离层的深度为h，且200nm≤h≤1000nm；浅槽隔离层的宽度为s，且100nm≤s≤10000nm。
这里的浅槽隔离层的宽度s可以被理解为：浅槽隔离层的与第一区域和第二区域排布方向相平行的方向上的尺寸。浅槽隔离层的深度h可以被理解为：浅槽隔离层的沿与半导体衬底相垂直方向上的尺寸。
在一种可能的实现方式中，第一阱区和第二阱区的其中一个为P阱区，另一个为N阱区；第 一电极掺杂区的掺杂类型与第一阱区的掺杂类型相反，第二电极掺杂区的掺杂类型与第一阱区的掺杂类型相同。
比如，第一阱区为N阱区，第二阱区为P阱区，第一电极掺杂区为P型掺杂，第二电极掺杂区为N型掺杂；晶体管的第一极和第二极均为N型掺杂。
再比如，第一阱区为P阱区，第二阱区为N阱区，第一电极掺杂区为N型掺杂，第二电极掺杂区为P型掺杂；晶体管的第一极和第二极均为P型掺杂。
在一种可能的实现方式中，第一阱区的掺杂浓度1017cm-3≤ρ1≤1019cm-3；和/或，第二阱区的掺杂浓度1017cm-3≤ρ2≤1019cm-3。
在一种可能的实现方式中，第一极和第二极中的至少一个电极的掺杂浓度1019cm-3≤ρ3≤1021cm-3；和/或，第一电极掺杂区和第二电极掺杂区中的至少一个掺杂区的掺杂浓度1019cm-3≤ρ4≤1021cm-3。
第一电极掺杂区和第二电极掺杂区相对第二阱区为重掺杂区，第一极和第二极相对第二阱区为重掺杂区。
在一种可能的实现方式中，半导体衬底的掺杂浓度1015cm-3≤ρ5≤1017cm-3。
在一种可能的实现方式中，第一光电二极管的耗尽区宽度为100nm≤l≤10μm。
在一种可能的实现方式中，光电探测器的光电响应度大于或等于105A/W。
相比相关技术中的一种利用雪崩倍增机制，来提升量子效率和灵敏度的技术，本申请可以将160A/W的光电响应度，大大提升至105A/W，或者，相比相关技术中利用SOI衬底的深耗尽效应，本申请可以将不仅可以获得较高的光电响应度，还可以降低功耗。
在一种可能的实现方式中，第一电极掺杂区背离半导体衬底的一侧形成有第一电极金属接触层；栅极的背离沟道层的一侧，和第一电极金属接触层的背离半导体衬底的一侧形成有金属互连层，栅极通过金属互连层与第一电极金属接触层电连接。
在此实施例中，通过利用金属互连层将晶体管的栅极与光电二极管的第一电极金属接触层电连接。
在一些工艺结构中，可以采用后道工艺制作金属互连层。
另一方面，本申请还提供一种光电探测器的制备方法，该制备方法包括如下：
将绝缘层上硅衬底的底层硅上的部分氧化埋层和部分顶层硅去除，并在去除氧化埋层和顶层硅后的位置处形成第一阱区；
在第一阱区中背离底层硅的表层形成第一电极掺杂区和第二电极掺杂区，以及在顶层硅中形成晶体管的第一极和第二极，并使得顶层硅的位于第一极和第二极之间部分形成晶体管的沟道层，在沟道层的背离氧化埋层的一侧设置晶体管的栅极，第一电极掺杂区和第二电极掺杂区中的一个为阳极掺杂区，另一个为阴极掺杂区，以制得晶体管、第一光电二极管和第二光电二极管；
电连接第一电极掺杂区与栅极；
其中，第一光电二极管包括第一电极掺杂区和第一阱区；第二光电二极管包括第一阱区和底层硅。
本申请给出的光电探测器的制备方法中，通过对绝缘层上硅衬底进行处理，以形成包括第一阱区(为本硅结构)，和绝缘层上硅的混合衬底，并且，将晶体管集成在绝缘层上硅结构中，以及，将光电二极管集成在本硅中。这样的话，通过利用体硅的厚硅(即厚度较大的第一阱区)作为光电二极管的光吸收层，从而增强对入射光吸收，以获得较高的量子效率和灵敏度。除外，利用绝缘层上硅可以降低漏电流、减小寄生电容。
除此之外，本申请制备方法中，不仅将第一光电二极管的第一电极掺杂区与晶体管的栅极(可以被称为顶栅)电连接，第一阱区和半导体衬底(可以被称为底栅)电连接，并形成第二光电二极管的PN结，从而，可以使得晶体管的阈值电压下降，导致晶体管的漏极电流增加，实现光电流的内部放大，并且，使得同样光照条件下，本申请得到的光电流远高于SOI衬底上的光电探测器的光电流，即光电响应度和量子效率得到大幅提升。
在一种可能的实现方式中，将绝缘层上硅衬底的底层硅上的部分氧化埋层和部分顶层硅去除之前，制备方法还包括：对底层硅的靠近氧化埋层的部分离子注入，以形成阱层，阱层的掺杂类 型与底层硅的掺杂类型相同，阱层的掺杂浓度大于底层硅的掺杂浓度；将绝缘层上硅衬底的底层硅上的部分氧化埋层和部分顶层硅去除，包括：绝缘层上硅衬底的底层硅上的堆叠的部分氧化埋层、部分顶层硅，以及部分阱层去除，并在去除后的位置处形成第一阱区，剩余的阱层形成第二阱区。
通过引入能够与第二阱区，以使得第一阱区、底层硅和第二阱区形成PIN结，进一步的扩宽有效探测区域，从而，导致晶体管阈值电压的进一步下降和沟道层电导的进一步增加，实现光电流的明显放大。
在一种可能的实现方式中，形成第二阱区之后，制备方法还包括：设置浅槽隔离层，浅槽隔离层贯穿顶层硅和所氧化埋层，使得顶层硅与第一阱区之间，以及氧化埋层和第一阱区之间均被浅槽隔离层电隔离开，且第一阱区和第二阱区接触。
通过设置浅槽隔离层将顶层硅与第一阱区，以及将氧化埋层和第一阱区进行电隔离，而并未将第一阱区和第二阱区电隔离开。
在一种可能的实现方式中，第一阱区和第二阱区的其中一个为P阱区，另一个为N阱区；第一电极掺杂区的掺杂类型与第二阱区的掺杂类型相反，第二电极掺杂区的掺杂类型与第二阱区的掺杂类型相同。
比如，可以采用离子注入工艺对这些阱区、掺杂区进行掺杂，以形成不同的阱区。
在一种可能的实现方式中，形成第一电极掺杂区和第二电极掺杂区之后，制备方法还包括：在第一电极掺杂区上形成第一电极金属接触层；采用后道工艺制作金属互连层，以使得栅极通过金属互连层与第一电极金属接触层电连接。
该种电连接结构简单，从工艺角度易于实现。
再一方面，本申请还提供一种光接收模块，该光接收模块包括处理器，以及上述任意一种光电探测器，处理器与光电探测器电连接。
由于本申请给出的光接收模块中，包含了上述涉及的光电探测器，在此光电探测器中，实现感光和放大的基础上，不仅可以满足高量子效率、高灵敏度，高光电响应度，还具有低漏电流、低功耗、高增益、抗辐射，以及高可靠性的特性。
在一种可能的实现方式中，光接收模块是图像传感器、光谱分析仪、光开关中的一种。
又一方面，本申请还提供一种电子设备，比如，该电子设备可以是手机、可穿戴设备等。该电子设备包括壳体、上述涉及的光接收模块，光接收模块设置在壳体内，光接收模块用于接收光信号。
本申请提供的电子设备包括上述的光接收模块，因此本申请提供的电子设备与上述技术方案的光接收模块能够解决相同的技术问题，并达到相同的预期效果。
再一方面，本申请又提供一种光电探测器，该光电探测器包括晶体管、第一光电二极管和第二光电二极管；第一光电二极管和第二光电二极管中的任意一个包括第一电极和第二电极，第一电极和第二电极中的一个为阳极，另一个为阴极；晶体管包括源极、漏极、第一栅极和第二栅极；第一光电二极管的第二电极与第二光电二极管的第二电极电连接，并用于与电源电连接；第一光电二极管的第一电极与晶体管的第一栅极电连接；第二光电二极管的第一电极与晶体管的第二栅极电连接。
本申请给出的光电探测器中，不仅包括具有放大作用的晶体管，还包括相并联的第一光电二极管和第二光电二极管，且第一光电二极管的第一电极与晶体管的第一栅极电连接，以及，第二光电二极管的第一电极与晶体管的第二栅极电连接。这样，当两个PN结处于反偏状态时，光电二极管的耗尽区发生展宽，实现对入射光的有效吸收，并产生光生电子空穴对，光生载流子会在耗尽区内建电场的作用下，向着建立在SOI衬底的第一栅极和第二栅极聚集。与此同时，聚集在第一栅极和第二栅极的光生载流子，会直接导致晶体管阈值电压的下降和沟道层电导的增加，从而导致晶体管漏极电流的显著增加，实现光电流的内部放大；并且，使得同样光照条件下，本申请得到的光电流远高于绝缘层上硅SOI衬底上的光电探测器的光电流，即光电响应度和量子效率得到大幅提升。
附图说明
图1为相关技术中的一种光电探测器的结构图；
图2为本申请实施例提供的一种电子设备的外形结构图；
图3为本申请实施例提供的一种电子设备的分解图；
图4为本申请实施例提供的一种光通信设备的分解图；
图5为本申请实施例提供的一种光通信设备中光模块的分解图；
图6为本申请实施例提供的一种光电探测器的俯视图；
图7为图6的A-A方向的剖面图；
图8为本申请实施例提供的一种光电探测器的电路原理图；
图9为本申请实施例提供的另一种光电探测器的剖面图；
图10为本申请实施例提供的一种光电探测器的电路原理图；
图11为本申请实施例提供的又一种光电探测器的剖面图；
图12为图11中第二光电二极管所形成的PN结和PIN结；
图13A为本申请实施例提供的体现光电探测器有效探测区域的结构图；
图13B为本申请实施例提供的体现光电探测器有效探测区域的结构图；
图14为图11的俯视图；
图15为采用本申请实施例提供的光电探测器时，施加给第二电极掺杂区的电压Vc与光电响应度R的变化曲线图；
图16为采用本申请实施例提供的光电探测器时，漏极电流ID与VC变化关系曲线图；
图17为本申请实施例提供的一种光电探测器制作方法的流程框图；
图18A1至图18H为本申请实施例提供的一种光电探测器制作方法中各步骤完成后对应的工艺结构剖面图；
图19A至图19F为本申请实施例提供的一种光电探测器制作方法中各步骤完成后对应的工艺结构剖面图。
附图标记：
1000-手机；
100-壳体；101-第一壳体；102-第二壳体；1021-窗口；
200-摄像头盖板；
300-透光窗口；
400-摄像头模组；
500-承载板；
2000-承载板；
1-光网络终端设备；
2-光模块；2a-第一开口；2b-第二开口；21-壳体；22-电路板；23-光接收模块；24-光发射
模块；
3-光纤；
4-网线；
5-光模块接口；
6-网线接口；
7-光电探测器；
701-半导体衬底；702-第一阱区；703-第一电极掺杂区；704-第二电极掺杂区；705-第二阱
区；
706-氧化埋层；707-半导体层；708-第一极；709-第二极；710-沟道层；711-栅介质层；712-
栅极；713-金属互连层；714-第一电极金属接触层；715-第二电极金属接触层；716-第一极金属接触层；717-第二极金属接触层；718-栅侧墙；719-浅槽隔离层；720-多晶硅栅极。
具体实施方式
在介绍本申请实施例之前，先介绍与本申请实施例相关的一些技术术语，具体见下述：
雪崩倍增效应：在强电场下，半导体中的载流子会被电场加热(半导体中的热载流子)，部分载流子可以获得足够高的能量，这些载流子有可能通过碰撞把能量传递给价带上的电子，使之发生电离，从而产生电子空穴对,这种过程称为碰撞电离。所产生的电子空穴对，在电场中向相反方向运动，又被电场加热并产生新的电子空穴对。依此方式可以使载流子大量增殖,此现象被称为雪崩倍增效应。
量子效率(quantum efficiency，QE)：或称光电转化效率(monochromatic incident photon-to-electron conversion efficiency，IPCE)，是指产生的电子空穴对数目与入射到光吸收层表面的光子数目之比。即量子效率越高，光电转化效率越高。
光电响应度(Responsivity)：其大小为光电探测器的平均输出电流Ip与平均输入功率Po的比值，即输出电信号电流大小与输入光信号功率大小之比。用公式表示为:R＝Ip/Po，单位为A/W。可以理解为，响应度越大，光电探测器的性能越优。
下面结合附图介绍本申请涉及的实施例。
光电探测器属于一种光电转换器件，具备将光信号直接转换为电信号的能力。例如，可以被应用在图像传感器、光谱分析仪、光开关、自动控制设备中。
比如，在电子设备中，该电子设备可以为手机、平板电脑(tablet personal computer)、膝上型电脑(laptop computer)、个人数码助理(personal digital assistant，PDA)、照相机、个人计算机、笔记本电脑、车载设备、可穿戴设备、增强现实(augmented reality，AR)眼镜、AR头盔、虚拟现实(virtual reality，VR)眼镜或者VR头盔等具有摄像模组的设备。图2所示实施例的电子设备以手机为例进行阐述。
图2示出了本申请实施例提供的一种手机1000的外形结构示意图，图3是本申请实施例提供的一种手机1000的分解结构示意图。一并结合图2和图3，该手机1000包括壳体100，壳体100包括相扣合、内部形成有空间的第一壳体101和第二壳体102，第二壳体102上开设有窗口1021，窗口1021上覆盖有摄像头盖板200，壳体100内设置有摄像头模组400，摄像头模组400可以被设置在位于壳体100内的承载板500上；并且，摄像头盖板200上具有透光窗口300，经透光窗口300的光线可以投射至摄像头模组400，以被摄像头模组400接收。
在摄像头模组400中，可以包括图像传感器，图像传感器也可以称为感光元件、或者感光芯片。图像传感器的主要部件是光电探测器，光电探测器可以用于接收自透光窗口透射的光线，并将光线所携带的图像信息转化为电信号。
以及，壳体100内还具有与图像传感器电连接的处理器，该处理器用于对图像传感器转化的电信号进行处理。
在另外一些场景中，比如，在光通信设备中，图4示出了一种光通信设备2000中各个结构之间的连接关系示意图。该光通信设备2000包括光网络终端设备(比如交换机)1、光模块2、光纤3以及网线4。
其中，光模块2包括电接口和光接口，光模块2的光接口与光纤3连接，与光纤3建立双向的光信号连接，光模块2的电接口通过光模块接口5与光网路终端设备1连接，与光网路终端设备1建立双向的电信号连接。示例的，来自光纤3的光信号由光模块2转换为电信号后输入至光网络终端设备1中，或者，来自光网络终端设备1的电信号由光模块2转换为光信号输入至光纤3中。
继续如图4，光网络终端设备1具有网线接口6，用于接入网线4，与网线4建立双向的电信号连接。具体地，光网络终端设备1将来自光模块2的信号传递给网线4，或者，光网络终端设备1将来自网线4的信号传递给光模块2。
图5给出了一种光模块2的分解示意图。其中，光模块2包括形成有容纳腔的壳体21、设置在壳体21的容纳腔内的电路板22、光接收模块(receiver optical subassembly，ROSA)23、光发射模块(transmitter optical subassembly，TOSA)24等电子元器件。
壳体21上开设有第一开口2a和第二开口2b，第一开口2a和第二开口2b中的一个开口为电 接口，电路板22的插接端从电接口伸出至壳体21外部，以插入光网络终端设备1的光模块接口6内；另一个开口为光接口，光纤3可以穿过光接口，以与壳体21内的光接收模块23连接，在一些实施方式中，光纤3可以直接与光接收模块23连接，或者，还可以设置适配器，即通过适配器连接光纤3和光接收模块23。
光接收模块23可以包括：电路板、设置在电路板上的光电探测器和处理器。光电探测器将光信号直接转换为电信号，处理器用于对转换的电信号进行处理。
上述仅是给出了具有光电探测器的一些示例性的应用场景，本申请涉及的光电探测器的具体应用场景不做特殊限定，可以包括具有光电探器的光接收模块。
无论是图2示出的手机1000的摄像头模组400中的光电探测器，还是图4示出的光通信设备2000的光模块2中的光电探测器，还是包含光电探测器的其他器件中，光电探测器的工作机理基本如下：一定波长的光作用于半导体PN结(PN junction)，入射光子的能量大于或等于半导体材料的禁带宽度，激发出电子空穴对(即光生载流子)，在耗尽区(势垒区)两边产生电动势的效应，连上外接电路即转变为电流信号，进而，实现电信号转换为光信号。
随着光电技术的发展，对光电探测器的性能要求愈来愈高，比如，不仅需要拥有较高的量子效率和灵敏度，以及较高的响应度，还需要实现低功耗，以使得光电探测器可以被应用在不同的场景中。
基于此，本申请实施例给出了一些可以实现上述技术效果的光电探测器。下面结合附图介绍本申请实施例给出的光电探测器的结构、工作原理，以及相对应的制备方法。
图6是本申请实施例给出的一种光电探测器的俯视图，图7是图6的A-A方向的剖面图。
一并结合图6和图7，本申请实施例提供的光电探测器7包括半导体衬底701，半导体衬底701可以被划分为第一区域Q1和第二区域Q2，第一区域Q1和第二区域Q2可以相毗邻，可以在第一区域Q1和第二区域Q2上分别形成半导体器件，比如，光电二极管，和与光电二极管电连接的一些电子器件。当然，在实体结构中，半导体衬底701没有第一区域Q1和第二区域Q2的分界，本申请实施例是为了形象描述一些电子器件所处的位置，自定义半导体衬底701可以包括第一区域Q1和第二区域Q2。
本申请实施例涉及的半导体衬底701可以是锗衬底、锗硅衬底、氮化镓衬底或者铟镓砷衬底中的至少一种。
继续见图7，半导体衬底701的第一区域Q1上设置有第一阱区702，并且，第一阱区702的背离半导体衬底701的表层形成有第一电极掺杂区703和第二电极掺杂区704。第一电极掺杂区703和第二电极掺杂区704中的一个掺杂区为阳极掺杂区，另一个掺杂区为阴极掺杂区。
在一种实施例中，如图7，半导体衬底701可以是P型掺杂衬底，第一阱区702可以是N型阱区，以及，第一电极掺杂区703可以是P型掺杂区，第二电极掺杂区704可以是N型掺杂区。
这样，第一阱区702和第一电极掺杂区703形成一个光电二极管(如图7示出的PD1)，第一阱区702和半导体衬底701形成又一个光电二极管(如图7示出的PD2)，即就是，此光电探测器中包含了第一光电二极管PD1和第二光电二极管PD2。
继续见图7，在半导体衬底701的第二区域Q2上，且沿着背离半导体衬底701的方向，依次堆叠有氧化埋层706和半导体层707，半导体层707中形成有晶体管Tr的第一极708和第二极709，半导体层707中的位于第一极708和第二极709之间的部分形成晶体管Tr的沟道层710，沟道层710的背离氧化埋层706的一侧设置有晶体管Tr的栅极712，且栅极712和沟道层707之间被栅介质层711电隔离开。以及，第一电极掺杂区703与栅极712电连接。
本申请实施例涉及的晶体管Tr的第一极708和第二极709中的一个是源极(source)，另一个为漏极(drain)。其中，可以根据电流方法判别源极(source)和漏极(drain)，比如，电流由第一极708流向第二极709，则第一极708为漏极，第二极709为源极。
本申请实施例给出的晶体管Tr是一种金属氧化物半导体场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)。在本申请所涉及的实施例中，例如上述图7所示的晶体管Tr可以选择NMOS(N-channel metal oxide semiconductor，N沟道金属氧化物半导体)管，或者可以选择PMOS(P-channel metal oxide semiconductor，P沟道金 属氧化物半导体)管。
基于上述结构，集成在半导体衬底701上的晶体管Tr是一种双栅晶体管，其中栅极712作为晶体管Tr的第一栅极(也可以被称为顶栅)，半导体衬底701作为晶体管Tr的第二栅极(也可以被称为底栅)。
本申请实施例给出的图7的光电探测器的工作机理可以见图8所示的等效电路原理图。即是：光电探测器包括第一光电二极管PD1、第二光电二极管PD2和晶体管Tr，其中，第一光电二极管PD1的阴极与第二光电二极管PD2的阴极电连接，并与电源电连接，第一光电二极管PD1的阳极与晶体管Tr的第一栅极VG电连接，第二光电二极管PD2的阳极与晶体管Tr的第二栅极VBG电连接。
在一些可以实现的实施例中，如图9，晶体管Tr的源极可以接地。
结合图8和图7，第二电极掺杂区704用于接电源电压Vc，第一极708和第二极709中的一个接VD，另一个接地。
结合图8所示电路原理图，和图6、图7所示的工艺结构图，本申请提供的实施例中，将晶体管Tr、第一光电二极管PD1、第二光电二极管PD2进行单片集成，提高光电探测系统集成度。并且，半导体衬底701、氧化埋层706和半导体层707形成绝缘层上硅SOI衬底，也就是，晶体管Tr被集成在绝缘层上硅SOI衬底上；另外，第一阱区702可以被理解为体硅衬底，即就是将光电二极管的PN结形成在体硅衬底上，晶体管Tr和光电二极管被集成在混合(hybrid)衬底上。
由于在绝缘层上硅SOI衬底中，通过氧化埋层706将半导体衬底701和半导体层707物理、电隔离开，这样的话，可以降低该晶体管Tr的功耗、减小寄生电容、增加抗辐射能力。
另外，第一阱区702作为光电二极管的光吸收层，相比利用绝缘层上硅SOI衬底中厚度较薄的硅层作为光吸收层，可以增加光吸收量，从而，可以提升光量子效率，光电转换效率。
还有，由于第一电极掺杂区703与晶体管Tr的栅极712电连接，以及，作为晶体管的底栅的半导体衬底701还和第一阱区702形成PN结，这样，当给第二电极掺杂区704施加偏置电压时，PD1和PD2同时工作于反偏状态，此时，光电二极管的耗尽区发生展宽，通过第一阱区702可以实现对光的吸收，并产生光生电子空穴对。其中，光生载流子在第一电极掺杂区703的聚集，引发了绝缘层上硅SOI衬底上的晶体管Tr的栅极712电位增加，光生载流子朝半导体衬底701和第一阱区702的界面处的聚集，引发作为晶体管Tr底栅的半导体衬底701的电位增加，如此一来，就会导致晶体管Tr的阈值电压的下降，沟道层710电导增加，从而，使得晶体管Tr漏极电流的显著增加，此过程实现了将光电二极管吸收的光子转化为导电的电子和空穴，并通过载流子聚集调节晶体管Tr的阈值电压，进一步放大光电流，使得同样光照条件下，本申请实施例给出的光电探测器得到的光电流远高于现有技术中光电二极管的光电流，即光电响应度和量子效率得到了大幅度提升。
也就是，本申请实施例提供的光电探测器，采用晶体管Tr的阈值电压调节机理，可以提升光电响应度，在工艺中，可以通过调节第一阱区702、半导体衬底701、第一电极掺杂区703和第二电极掺杂区704的掺杂浓度，以及，施加给第二电极掺杂区704的电压和施加给晶体管Tr的源漏极的电压，调节确定晶体管Tr的阈值电压。
总之，本申请实施例给出的如图6至图8所示的光电探测器，在实现感光和放大的基础上，不仅可以满足高量子效率、高灵敏度，还可以实现低漏电流、低功耗、高增益、抗辐射、以及极端环境下高可靠性的特性。
在图6、图7所示的工艺结构中，第一阱区702作为入射光的吸收层，入射光基本不会穿过半导体层707和氧化埋层706而进入该光电探测器内，这样，入射光几乎只被体硅位置两个反偏PN结吸收并转化为电信号，提升该光电探测器对入射光的吸收效率，降低损耗，提升光电响应度。
在一些可以实现的结构中，如图7，半导体衬底701为P型衬底，第一阱区702为N型阱区，第一电极掺杂区703为P型掺杂，第二电极掺杂区704为N型掺杂，以及，晶体管Tr的第一极708和第二极709分别为N型掺杂。
这样，该光电探测器在工作时，可以通过给电源VC施加正向偏置电压时，PD1和PD2会工作于反偏状态，产生光生电子空穴对。
在另外一些可以实现的结构中，如图9，图9示出的是本申请实施例给出的另外一种光电探测器7的剖面图。和上述图7所示光电探测器7相比，区别在于：在图9中，半导体衬底701为N型衬底，第一阱区702为P型阱区，第一电极掺杂区703为N型掺杂，第二电极掺杂区704为P型掺杂，以及，晶体管Tr的第一极708和第二极709分别为P型掺杂。
本申请实施例给出的图9的光电探测器的工作机理可以见图10所示的等效电路原理图。即是：光电探测器包括第一光电二极管PD1、第二光电二极管PD2和晶体管Tr，其中，第一光电二极管PD1的阳极与第二光电二极管PD2的阳极电连接，并与电源电连接，第一光电二极管PD1的阴极与晶体管Tr的第一栅极VG电连接，第二光电二极管PD2的阴极与晶体管Tr的第二栅极VBG电连接。
图9和图10所示的光电探测器在工作为，可以通过给电源VC施加负向偏置电压时，PD1和PD2会工作于反偏状态，产生光生电子空穴对。
在可以实现的工艺结构中，为了避免晶体管Tr的源漏极与光电二极管的阴第一电极发生短路，见图9，在半导体衬底701上还设置有浅槽隔离层(STI)719，并且，堆叠的半导体层707和氧化埋层706，与第一阱区702之间均需要被浅槽隔离层719物理和电隔离。
为了实现晶体管Tr和光电二极管PD与外围电路的电连接，参阅图7和图9，在可以实现的工艺结构中，该光电探测器还包括第一电极金属接触层714、第二电极金属接触层715、第一极金属接触层716和第二极金属接触层717。
其中，第一电极金属接触层714设置在第一电极掺杂区703上(即设置在第一电极掺杂区703的背离半导体衬底701的一侧)；第二电极金属接触层715设置在第二电极掺杂区704上(即设置在第二电极掺杂区704的背离半导体衬底701的一侧)；第一极金属接触层716设置在第一极708上(即设置在第一极708的背离氧化埋层706的一侧)，第二极金属接触层717设置在第二极709上(即设置在第二极709的背离氧化埋层706的一侧)。
在可以实现的工艺流程中，第一阱区702、第一电极掺杂区703、第二电极掺杂区704、第一极708、第二极709、第一电极金属接触层714、第二电极金属接触层715、第一极金属接触层716和第二极金属接触层717，均可以采用前道(front end of line，FEOL)制程被集成在半导体衬底701上。
为了实现栅极712与第一电极掺杂区703的电连接，如图9，可以在栅极712的背离半导体衬底701的一侧，以及第一电极金属接触层714的背离半导体衬底701的一侧，设置金属互连层713，栅极712通过金属互连层713与第一电极金属接触层714电连接。
在可以实现的工艺流程中，金属互连层713可以采用后道(back end of line，BEOL)制程制作。
在一些工艺结构中，为了保护栅极712，如图9，该光电探测器还可以包括设置在栅极712侧面的栅极侧墙718。栅极侧墙718可以覆盖栅极712侧面，也可以如图7所示的覆盖栅介质层711的侧面。
图11是本申请实施例给出的另外一种光电探测器的剖面图。图11与上述图7和图9相比，该实施例的光电探测器7还包括第二阱区705，第二阱区705设置在半导体衬底701的第二区域Q2上，且位于半导体衬底701和氧化埋层706之间。
其中，第二阱区705的掺杂类型与半导体衬底701的掺杂类型相同，比如，图11所示的，均为P型掺杂，并且，第二阱区705的掺杂浓度，大于半导体衬底701的掺杂浓度。比如，第二阱区705为重掺杂区，半导体衬底701为轻掺杂区。
进而，如图12所示，第二光电二极管不仅包括了第一阱区702和第二阱区705形成的PN结，还包括了第一阱区702、半导体衬底701和第二阱区705形成的PIN结。
在图13A中，简易示出了光电探测器7不包括第二阱区705时，第二光电二极管的有效探测区域如图13A所示的T1区域。
在图13B中，简易示出了光电探测器7包括第二阱区705时，即第二光电二极管不仅包括PN结，还包括PIN结时，第二光电二极管的有效探测区域包括如图13B所示的T2区域和T3区域。
在图13A和图13B中，仅是示例性的画出有效探测区域的大概位置，并不构成对有效探测区域的绝对限定。比如，在图13A中，有效探测区域也可以扩展至T1区域的外围，类似的，在图 13B中，有效探测区域也可以扩展至T2区域和T3区域的外围。
由图13B所示的T2区域和T3区域，可以看出：当本申请实施例给出的光电探测器7增加第二阱区705后，明显的增大了有效探测区域，实现对入射光的有效吸收，可以产生更多的空穴电子对，从而提升光电转换效率。
当产生更多的空穴电子对后，产生的较多的光生载流子会传输至顶栅(如图11中的栅极712)，和传输至底栅(如图11中的第二阱区705和半导体衬底701)，引起晶体管阈值电压的进一步下降，和沟道层电导的进一步增加，使得晶体管的漏极电流进一步增加，实现光电流的明显放大。
光生载流子继续参阅图11，本申请实施例包括用于电隔离的浅槽隔离层719时，半导体层707和第一阱区702之间，以及氧化埋层706和第一阱区702之间，均被浅槽隔离层719电隔离开，但是，相毗邻的第一阱区702和第二阱区705相接触。
在一些可以实现的工艺结构中，如图11，浅槽隔离层719的宽度d1在0.1μm至10μm之间。浅槽隔离层719的深度h1在200nm至1μm之间。当然，本申请对浅槽隔离层719的宽度和深度不做限定，任何范围均在本申请的保护范围之内。
本申请对沟道层710的长度、宽度和深度均不做限定。比如，见图11和图14，图14是图11的俯视图，其中，沟道层710的长度S为10nm至1μm之间，沟道层710的宽度d2为7nm至400nm之间，沟道层710的深度h2为7nm至200nm之间。
另外，第一电极掺杂区703与第二电极掺杂区704之间的间距d3可以为100nm至10000nm之间。
在一些实施例中，当半导体衬底701为P型衬底，第二阱区705为P型阱区时，掺杂元素可以为硼、铝、镓、铟等第III主族元素中的至少一种。
第一阱区702为N型阱区时，掺杂元素可以为磷、砷等第V主族元素中的至少一种。
继续见图11，第一电极掺杂区703和第二电极掺杂区704相比第一阱区702，为重掺杂区。示例的，第一阱区702的掺杂浓度ρ1，且1017cm-3≤ρ1≤1019cm-3；第一电极掺杂区703和第二电极掺杂区704的掺杂浓度ρ4，且1019cm-3≤ρ4≤1021cm-3。
第一极708和第二极709相比第二阱区705，为重掺杂区。示例的，第二阱区705的掺杂浓度ρ2，且1017cm-3≤ρ2≤1019cm-3；第一极708和第二极709的掺杂浓度ρ3，且1019cm-3≤ρ3≤1021cm-3。
另外，半导体衬底701可以是轻掺杂区，比如，半导体衬底701的掺杂浓度ρ5，且1015cm-3≤ρ5≤1017cm-3。
上述是对第一阱区702、第二阱区705、第一电极掺杂区703、第二电极掺杂区704、第一极708和第二极709掺杂浓度的示例性说明，当然也可以选择其他范围。
下述列表1给出了采用图11实施例的光电探测器，与相关技术涉及的光电探测器的一些性能指标对比，具体见下表1。

表1
上述表1中，当衬底采用体硅时，涉及硅基PN结光电二极管，和利用雪崩倍增效应形成的雪崩光电二极管APD；当衬底采用绝缘层上硅SOI时，涉及包含金属氧化物半导体场效应晶体管MOSFET的光电探测器、利用雪崩倍增效应形成的雪崩光电二极管APD和利用界面耦合效应形成的ICPD，以及采用Si纳米线和Si微米线形成的光电探测器；本申请实施例提供的衬底类型可以被称为包含体硅和绝缘层上硅SOI的混合衬底。
表1中的诸如650nm、400-1000nm、520nm示意的是照射至光电探测器上的光波长。例如，采用雪崩倍增效应形成的APD的入射光波长为400nm，本申请实施例采用的入射光波长为520nm。
表1中的5V、0.2V、8.2V示意的是施加给该光电探测器的工作电压。例如，利用PN结构的工作电压可以选择5V，本申请实施例工作电压可以选择0.5V。此处的工作电压为图11所示的施加给光电二极管的第二电极掺杂区704上的电压Vc。
基于表1，可以得知：
当采用本申请实施例给出的光电探测器，且光波长为520nm，工作电压Vc仅为0.5V时，光电响应度达到105A/W左右。相比光波长相同，采用界面耦合效应形成的ICPD，尽管ICPD的光电响应度也达到了105A/W左右，但是，工作电压Vc高达5V以上，甚至达到20V左右，与本申请提供的光电探测器相比，本申请的光电探测器可以明显的降低工作电压Vc，降低功耗，实现低功耗、高光电响应度。
当采用本申请实施例给出的光电探测器，光波长为520nm，工作电压Vc仅为0.5V时，光电响应度达到105A/W左右。相比采用Si纳米线和Si微米线的光电探测器，Si纳米线和Si微米线工作电压Vc为1V时，光电响应度仅为10A/W左右。明显的，本申请实施例涉及的光电探测器，在较小工作电压时，就可以达到较高的光电响应度。
所以，基本上述对表1相关信息的描述，可以确定：本申请提供的利用混合衬底制得的光电探测器，在较小的工作电压Vc时，就能够获得较高的光电响应度，从而，可以提升该光电探测器的工作性能。
例如，图15示出的是采用本申请实施例提供的光电探测器时，施加给第二电极掺杂区的工作电压Vc与光电响应度R的变化曲线。其中，该曲线的横坐标示意的是施加给第二电极掺杂区的工作电压Vc，纵坐标示意的是光电响应度R。
由图15所示的变化曲线得知：光电响应度R随着工作电压Vc的增加而增加，可以达到了105A/W数量级，并且，当工作电压Vc为0.5V时，光电响应度R就可以达到1×105A/W，当工作电压Vc为1V时，光电响应度R甚至接近2×105A/W。
进而，结合上述表1和图15所示变化曲线，本申请实施例提供的光电探测器，施加比较小的工作电压时，就可以达到较高的光电响应度。
图16示出的是采用本申请实施例给出的光电探测器，沟道层710的长度为136nm，半导体衬底701的掺杂浓度为1015cm-3，栅极的偏置电压为1.8V，晶体管Tr的漏极电压VD＝0.1V，晶体管Tr的源极接地Vs＝0V，漏极电流ID与VC变化关系曲线。其中，横坐标示意的是施加给第二电极掺杂区的工作电压Vc，纵坐标示意的是漏极电流ID。
曲线(1)示意的是入射光的波长为520nm，光照强度为1mW/cm2时的漏极电流ID与VC变化关系曲线；曲线(2)示意的是黑暗状态下的漏极电流ID与VC变化关系曲线。
对比曲线(1)和曲线(2)，表明当采用本申请实施例给出的光电探测器时，光照强度仅为 1mW/cm2时，漏极电流ID明显的被放大。也可以被理解为，本申请实施例的光电探测器能够有效的吸收光，可以获得较高的光电转换效率。
上述结合附图介绍了本申请实施给出的光电探测器的工艺结构图，下面结合附图详细介绍本申请实施例给出的制备方法，以制得承载在混合衬底上的光电探测器，具体见下述。
图17示例性的给出了制备光电探测器的流程框图。
步骤S1：将绝缘层上硅衬底的底层硅上的部分氧化埋层和部分顶层硅去除，并在去除氧化埋层和顶层硅后的位置处形成第一阱区。
利用绝缘层上硅SOI作为原材料，进行加工制造。
步骤S2：在第一阱区中背离底层硅的表层形成第一电极掺杂区和第二电极掺杂区，以及在顶层硅中形成晶体管的第一极和第二极，并使得顶层硅的位于第一极和第二极之间部分形成晶体管的沟道层，在沟道层的背离氧化埋层的一侧设置晶体管的栅极，第一电极掺杂区和第二电极掺杂区中的一个为阳极掺杂区，另一个为阴极掺杂区，以制得晶体管、第一光电二极管和第二光电二极管。
即就是在体硅上形成光电二极管，在绝缘层上硅衬底形成晶体管。
步骤S3：电连接第一电极掺杂区与栅极；其中，第一光电二极管包括第一电极掺杂区和第一阱区，第二光电二极管包括第一阱区和底层硅。
下面结合附图对上述步骤S1和步骤S3所涉及的具体工艺流程进行介绍。
图18A1至图18H给出了制得本申请实施例一种光电探测器的工艺过程中每一步骤完成后的工艺结构。
如图18A1和图18A2，图18A2是图18A1的B-B方向的剖面图。准备绝缘层上硅SOI衬底。
其中，绝缘层上硅SOI衬底包括堆叠的底层硅和顶层硅，以及设置在底层硅和顶层硅之间的氧化埋层。示例的，氧化埋层的厚度可以为10nm至1000nm。
在一些结构中，底层硅可以是轻掺杂的P型衬底，或者，可以是轻掺杂的N型掺杂。比如，底层硅的掺杂浓度可以为1015cm-3≤ρ≤1017cm-3。
如图18B1和图18B2，图18B2是图18B1的C-C方向的剖面图。去除位于底层硅的第一区域Q1上的顶层硅和氧化埋层，以在底层硅的第一区域Q1上形成空缺，底层硅的与第一区域Q1相邻的第二区域Q2保留氧化埋层和顶层硅。
在去除位于底层硅的第一区域Q1上的顶层硅和氧化埋层时，可以采用光刻和刻蚀工艺，例如，刻蚀工艺可以采用干法刻蚀或者湿法刻蚀。干法刻蚀可以采用氟基或者卤族元素气体，如SF6，CHF3，HBr或者Cl2等，而湿法刻蚀可以使用TMAH，KOH等溶液。
在去除位于底层硅的第一区域Q1上的顶层硅和氧化埋层之前，可以将绝缘层上硅SOI清洗干净。
如图18C1和图18C2，图18C2是图18C1的D-D方向的剖面图。在上述图18B2形成的空缺位置形成第一阱区702，以及，形成浅槽隔离层719。
在一些可以选择的工艺中，可以采用外延生长技术，生长外延层，外延生长技术可为物理气相沉积，化学气相沉积，或者分子束外延等方式实现。
并且，可以通过对外延层进行离子注入工艺，形成第一阱区702。第一阱区702的掺杂类型与底层硅的掺杂类型相反，比如，第一阱区702为P型阱区，则底层硅为N型掺杂。
在一些工艺中，示例的，第一阱区702的离子注入浓度为1017cm-3至1019cm-3。
这样，就形成了如图18C1和图18C2所示的，包含体硅(第一阱区702)和绝缘层上硅SOI的混合衬底。
之后，可以形成浅槽隔离层719，比如，首先可以采用光刻和刻蚀工艺，在顶层硅和氧化埋层，与第一阱区702的界面处开设凹槽，并在凹槽内填充氧化层，以形成浅槽隔离层719。
如图18C1，浅槽隔离层719可以呈环形结构，设置在底层硅的第二区域Q2上，这样的话，可以实现形成在第二区域Q2上的电子器件，与旁侧的电子器件的电隔离。
如图18D1和图18D2，图18D2是图18D1的E-E方向的剖面图。本申请实施例中，可以利用前道工艺，在顶层硅上制作金属氧化物半导体晶体管MOSFET的多晶硅栅极720。
在形成多晶硅栅极720之前，可以先形成栅氧介质层，再在栅氧介质层上形成多晶硅栅极。
栅氧介质层可以选择氧化铪、氧化硅等高K值材料。栅氧介质层的厚度可以选择1nm至100nm。
如图18E1和图18E2，图18E2是图18E1的F-F方向的剖面图。形成晶体管Tr的第一极708和第二极709，以及形成第一电极掺杂区703和第二电极掺杂区704。
在可以选择的工艺方式中，可以采用外延工艺或者离子注入工艺形成第一极708和第二极709，以及形成第一电极掺杂区703和第二电极掺杂区704。然后，采用高温退火工艺，激活杂质并修复离子注入引入的工艺缺陷。
第二电极掺杂区和第一电极掺杂区中，掺杂元素可以为砷或磷离子，掺杂浓度为1020cm-3至1021cm-3。离子激活退火温度一般为900度至1200度之间，时间为1秒至10秒之间。
如图18F1和图18F2，图18F2是图18F1的G-G方向的剖面图。采用替换金属栅极工艺，即就是将图18E1和图18E2制得的多晶硅栅720被金属栅极替换掉，以形成金属的栅极712。
其中，栅极712可以选择金，铂，铝等金属材料中的至少一种。
制得栅极712之后，还可以在栅极712的侧面制得栅极侧墙718。
如图18G1和图18G2，图18G2是图18G1的H-H方向的剖面图。制得第一极金属接触层715、第二极金属接触层717、第一电极金属接触层714和第二电极金属接触层715。
比如，可以采用蒸发、溅射工艺形成这些金属接触层。其中，金属淀积可以使用物理气相淀积或蒸发等方法，可以选择的金属为铝、镍、钛、金等。之后在退火温度为300度至900度之间，进行10-120秒的退火。
如图18H，在后道制程中，制得金属互连层13，以使得栅极712通过金属互连层13与第一电极金属接触层714电连接。
金属互连层13可以选择铜或者铝等。
根据图18A1至图18H所示的工艺步骤，可以看出：本申请实施例示出的制备方法中，可以采用绝缘层上硅SOI衬底作为原材料，制得包含体硅和绝缘层上硅的混合衬底，并且，利用体硅作为光电二极管的光吸收层，以提升光吸收效率，以及，将晶体管制作在绝缘层上硅中，获得低功耗。
图19A至图19F给出了制得本申请实施例另一种光电探测器的工艺过程中每一步骤完成后的工艺结构。
如图19A，在绝缘层上硅的底层硅的靠近氧化埋层的位置处形成阱层。
在一些工艺方式中，可以采用离子注入方式形成阱层。离子注入可以选择硼或者BF3作为源，能量为10keV至100keV之间，注入剂量可以为1010cm-2至1013cm-2之间，最终形成的阱层掺杂浓度为1017cm-2至1019cm-2之间。
如图19B，去除底层硅的第一区域Q1上方的顶层硅、氧化埋层和阱层，并在去除后空缺位置形成第一阱区702，位于底层硅的第二区域Q2上的阱层形成第二阱区705。
以及，形成浅槽隔离层719。
如图19C，采用后栅工艺，可以先形成第一极708、第二极709、第一电极掺杂区703和第二电极掺杂区704。
和上述的制备方法类似，可以采用外延工艺或者离子注入工艺形成第一极708和第二极709，以及形成第一电极掺杂区703和第二电极掺杂区704。然后，采用高温退火工艺，激活杂质并修复离子注入引入的工艺缺陷。
如图19D，在顶层硅的位于第一极708和第二极709之间的沟道层上制作金属氧化物半导体晶体管MOSFET的多晶硅栅极720。
在形成多晶硅栅极720之前，可以先形成栅氧介质层，再在栅氧介质层上形成多晶硅栅极。
如图19E，采用替换金属栅极工艺，即就是将图19D制得的多晶硅栅被720被金属栅极替换掉，以形成金属的栅极712。
在该制备方法中，和上述的制备方法相比，上述制备方法采用的是前栅工艺，即先制得多晶硅栅极720之后，再进行离子注入掺杂，形成第一极708和第二极709，以及第一电极掺杂区703和第二电极掺杂区704。此制备方法采用的是后栅工艺，即先形成第一极708和第二极709，以及 第一电极掺杂区703和第二电极掺杂区704，再制得多晶硅栅极720。
如图19F，和上述方法类似，制得第一极金属接触层716、第二极金属接触层717、第一电极金属接触层714和第二电极金属接触层715，以及金属互连层713。从而，制得包含第一阱区702和第二阱区705的光电探测器结构。
下面表2给出了一些相关技术的光电探测器，与本申请实施例提供的光电探测器的性能对比，具体见下表2：
表2
基于上述表2，显然的，由于本申请实施例给出光电探测器的性能更优，被应用的场景会更广。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示 例中以合适的方式结合。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (19)

  1. 一种光电探测器，其特征在于，包括：
    半导体衬底；
    晶体管、第一光电二极管和第二光电二极管；
    所述半导体衬底的第一区域上设置有第一阱区，所述第一阱区中且背离所述半导体衬底的表层形成有第一电极掺杂区和第二电极掺杂区，所述第一电极掺杂区和所述第二电极掺杂区中的一个为阳极掺杂区，另一个为阴极掺杂区；
    所述半导体衬底的第二区域上，且沿着背离所述半导体衬底的方向，依次堆叠有氧化埋层和半导体层，所述半导体层中形成有所述晶体管的第一极和第二极，所述半导体层中的位于所述第一极和所述第二极之间的部分形成所述晶体管的沟道层，所述沟道层的背离所述氧化埋层的一侧设置有所述晶体管的栅极；
    所述第一电极掺杂区与所述栅极电连接；
    所述第一光电二极管包括所述第一电极掺杂区和所述第一阱区；
    所述第二光电二极管包括所述第一阱区和所述半导体衬底。
  2. 根据权利要求1所述的光电探测器，其特征在于，所述第二光电二极管还包括第二阱区；
    所述第二阱区设置在所述第二区域上，且位于所述半导体衬底和所述氧化埋层之间；
    所述第二阱区的掺杂类型与所述半导体衬底的掺杂类型相同，所述第二阱区的掺杂浓度大于所述半导体衬底的掺杂浓度。
  3. 根据权利要求2所述的光电探测器，其特征在于，
    所述第一阱区和所述第二阱区形成所述第二光电二极管的PN结；
    所述第二阱区、所述半导体衬底和所述第一阱区形成所述第二光电二极管的PIN结。
  4. 根据权利要求2或3所述的光电探测器，其特征在于，所述光电探测器还包括浅槽隔离层；
    所述半导体层与第一阱区之间，以及所述氧化埋层和所述第一阱区之间均被所述浅槽隔离层电隔离开，所述第一阱区和所述第二阱区接触。
  5. 根据权利要求2-4中任一项所述的光电探测器，其特征在于，
    所述第一阱区和所述第二阱区的其中一个为P阱区，另一个为N阱区；
    所述第一电极掺杂区的掺杂类型与所述第一阱区的掺杂类型相反，所述第二电极掺杂区的掺杂类型与所述第一阱区的掺杂类型相同。
  6. 根据权利要求2-5中任一项所述的光电探测器，其特征在于，
    所述第一阱区的掺杂浓度为ρ1，1017cm-3≤ρ1≤1019cm-3；和/或，
    所述第二阱区的掺杂浓度为ρ2，1017cm-3≤ρ2≤1019cm-3。
  7. 根据权利要求1-6中任一项所述的光电探测器，其特征在于，所述第一电极掺杂区背离所述半导体衬底的一侧形成有第一电极金属接触层；
    所述栅极的背离所述沟道层的一侧，和所述第一电极金属接触层的背离所述半导体衬底的一侧形成有金属互连层，所述栅极通过所述金属互连层与所述第一电极金属接触层电连接。
  8. 根据权利要求1-7中任一项所述的光电探测器，其特征在于，
    所述第一极和所述第二极中的至少一个电极的掺杂浓度为ρ3，1019cm-3≤ρ3≤1021cm-3；和/或，
    所述第一电极掺杂区和所述第二电极掺杂区中的至少一个掺杂区的掺杂浓度为ρ4，1019cm-3≤ρ4≤1021cm-3。
  9. 根据权利要求1-8中任一项所述的光电探测器，其特征在于，所述半导体衬底的掺杂浓度为ρ5，1015cm-3≤ρ5≤1017cm-3。
  10. 根据权利要求1-9中任一项所述的光电探测器，其特征在于，所述第一光电二极管的耗尽区宽度为100nm≤l≤10μm。
  11. 根据权利要求1-10中任一项所述的光电探测器，其特征在于，所述光电探测器的光电响应度大于或等于105A/W。
  12. 一种光电探测器的制备方法，其特征在于，所述制备方法包括：
    将绝缘层上硅衬底的底层硅上的部分氧化埋层和部分顶层硅去除，并在去除所述氧化埋层和所述顶层硅后的位置处形成第一阱区；
    在所述第一阱区中背离所述底层硅的表层形成第一电极掺杂区和第二电极掺杂区，以及在所述顶层硅中形成晶体管的第一极和第二极，并使得所述顶层硅的位于所述第一极和所述第二极之间部分形成所述晶体管的沟道层，在所述沟道层的背离所述氧化埋层的一侧设置所述晶体管的栅极，所述第一电极掺杂区和所述第二电极掺杂区中的一个为阳极掺杂区，另一个为阴极掺杂区，以制得所述晶体管、第一光电二极管和第二光电二极管；
    电连接所述第一电极掺杂区与所述栅极；
    其中，所述第一光电二极管包括所述第一电极掺杂区和所述第一阱区；
    所述第二光电二极管包括所述第一阱区和所述底层硅。
  13. 根据权利要求12所述的光电探测器的制备方法，其特征在于，将所述绝缘层上硅衬底的底层硅上的部分氧化埋层和部分顶层硅去除之前，所述制备方法还包括：
    对所述底层硅的靠近所述氧化埋层的部分离子注入，以形成阱层，所述阱层的掺杂类型与所述底层硅的掺杂类型相同，所述阱层的掺杂浓度大于所述底层硅的掺杂浓度；
    将所述绝缘层上硅衬底的底层硅上的部分氧化埋层和部分顶层硅去除，包括：
    所述绝缘层上硅衬底的底层硅上的堆叠的部分氧化埋层、部分顶层硅，以及部分所述阱层去除，并在去除后的位置处形成所述第一阱区，剩余的所述阱层形成第二阱区。
  14. 根据权利要求13所述的光电探测器的制备方法，其特征在于，形成所述第二阱区之后，所述制备方法还包括：
    设置浅槽隔离层，所述浅槽隔离层贯穿所述顶层硅和所述氧化埋层，使得所述顶层硅与第一阱区之间，以及所述氧化埋层和所述第一阱区之间均被所述浅槽隔离层电隔离开，且所述第一阱区和所述第二阱区接触。
  15. 根据权利要求12-14中任一项所述的光电探测器的制备方法，其特征在于，形成所述第一电极掺杂区和所述第二电极掺杂区之后，所述制备方法还包括：
    在所述第一电极掺杂区上形成第一电极金属接触层；
    采用后道工艺制作金属互连层，以使得所述栅极通过所述金属互连层与所述第一电极金属接触层电连接。
  16. 一种光接收模块，其特征在于，包括：
    处理器；
    如权利要求1-11中任一项所述的光电探测器，或者，如权利要求12-15中任一项所述的光电探测器的制备方法制得的光电探测器；
    所述处理器与所述光电探测器电连接。
  17. 根据权利要求16所述的光接收模块，其特征在于，所述光接收模块是图像传感器、光谱分析仪、光开关中的一种。
  18. 一种电子设备，其特征在于，包括：
    壳体；
    如权利要求16或17所述的光接收模块；
    所述光接收模块设置在所述壳体内，所述光接收模块用于接收光信号。
  19. 一种光电探测器，其特征在于，包括：
    晶体管，所述晶体管包括源极、漏极、第一栅极和第二栅极；
    第一光电二极管和第二光电二极管，所述第一光电二极管和所述第二光电二极管中的任意一个包括第一电极和第二电极，所述第一电极和所述第二电极中的一个为阳极，另一个为阴极；
    所述第一光电二极管的所述第二电极与所述第二光电二极管的所述第二电极电连接，并用于与电源电连接；
    所述第一光电二极管的所述第一电极与所述晶体管的所述第一栅极电连接；
    所述第二光电二极管的所述第一电极与所述晶体管的所述第二栅极电连接。
PCT/CN2023/120098 2022-10-31 2023-09-20 光电探测器、光接收模块及电子设备 WO2024093559A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211351084.4 2022-10-31
CN202211351084.4A CN117995836A (zh) 2022-10-31 2022-10-31 光电探测器、光接收模块及电子设备

Publications (1)

Publication Number Publication Date
WO2024093559A1 true WO2024093559A1 (zh) 2024-05-10

Family

ID=90901609

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/120098 WO2024093559A1 (zh) 2022-10-31 2023-09-20 光电探测器、光接收模块及电子设备

Country Status (2)

Country Link
CN (1) CN117995836A (zh)
WO (1) WO2024093559A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103460688A (zh) * 2011-04-11 2013-12-18 索尼公司 固态图像捕获元件与照相机系统
US20140284610A1 (en) * 2013-03-22 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor device
CN109728019A (zh) * 2019-01-04 2019-05-07 复旦大学 基于绝缘层上硅的单晶体管主动像素传感器及制备方法
CN112382639A (zh) * 2020-10-16 2021-02-19 复旦大学 基于绝缘层上硅衬底的可调性能光电传感器及其制备方法
CN112397532A (zh) * 2019-08-15 2021-02-23 天津大学青岛海洋技术研究院 一种高量子效率图像传感器像素结构及其制作方法
CN112510058A (zh) * 2020-12-16 2021-03-16 中山大学 一种集成光电传感器及其制备方法
CN116598322A (zh) * 2023-05-18 2023-08-15 复旦大学 基于绝缘衬底上硅-二维材料异质集成光电探测器及其制备方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103460688A (zh) * 2011-04-11 2013-12-18 索尼公司 固态图像捕获元件与照相机系统
US20140284610A1 (en) * 2013-03-22 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor device
CN109728019A (zh) * 2019-01-04 2019-05-07 复旦大学 基于绝缘层上硅的单晶体管主动像素传感器及制备方法
CN112397532A (zh) * 2019-08-15 2021-02-23 天津大学青岛海洋技术研究院 一种高量子效率图像传感器像素结构及其制作方法
CN112382639A (zh) * 2020-10-16 2021-02-19 复旦大学 基于绝缘层上硅衬底的可调性能光电传感器及其制备方法
CN112510058A (zh) * 2020-12-16 2021-03-16 中山大学 一种集成光电传感器及其制备方法
CN116598322A (zh) * 2023-05-18 2023-08-15 复旦大学 基于绝缘衬底上硅-二维材料异质集成光电探测器及其制备方法

Also Published As

Publication number Publication date
CN117995836A (zh) 2024-05-07

Similar Documents

Publication Publication Date Title
CN110663114B (zh) 锗-硅光感测设备ii
TWI720821B (zh) 光學感測器
US7893468B2 (en) Optical sensor including stacked photodiodes
US7453131B2 (en) Photodiode detector and associated readout circuitry
US7883916B2 (en) Optical sensor including stacked photosensitive diodes
US9437632B2 (en) Image sensor and manufacturing method thereof
US9613998B2 (en) Backside illumination image sensor and method for reducing dark current of backside illumination image sensor
JPH11317512A (ja) Ｃｍｏｓイメ―ジセンサ―及びその製造方法
JPH11214665A (ja) Ｃｍｏｓイメージセンサ
KR101905978B1 (ko) 이미지 센서와 솔라 셀로서 동작 가능한 단위 픽셀 엘리먼트
TW201535697A (zh) 固態攝影元件及其製造方法
Liu et al. A review on the recent progress of silicon‐on‐insulator‐based photodetectors
WO2021253971A1 (zh) 感光像素模块、图像传感器及电子设备
US7732886B2 (en) Pin photodiode structure
US20130001729A1 (en) High Fill-Factor Laser-Treated Semiconductor Device on Bulk Material with Single Side Contact Scheme
US11973093B2 (en) Visible-to-longwave infrared single photon avalanche photodetector on silicon
US6096573A (en) Method of manufacturing a CMOS sensor
WO2024093559A1 (zh) 光电探测器、光接收模块及电子设备
WO2023116035A1 (zh) 感光电路结构和光学器件
US11316063B2 (en) Diode devices and methods of forming a diode device
CN109065660B (zh) 一种波导型光伏场效应晶体管结构的光敏器件及制作方法
Afzal et al. A Proposed Silicon Optical Electronic Integrated Circuit with Monolithic Integration of LED, OPFET and Receiver Circuit
US20230369378A1 (en) Photodiode and manufacturing method thereof
CN118039724A (zh) 光电探测器、光接收模块及电子设备
Mamdy et al. Back-side-illuminated 1.4 um pixel with a vertically pinned photodiode based on hole collection, PMOS readout chain and active side-wall passivation

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23884491

Country of ref document: EP

Kind code of ref document: A1