WO2023116035A1 - 感光电路结构和光学器件 - Google Patents

感光电路结构和光学器件 Download PDF

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Publication number
WO2023116035A1
WO2023116035A1 PCT/CN2022/115968 CN2022115968W WO2023116035A1 WO 2023116035 A1 WO2023116035 A1 WO 2023116035A1 CN 2022115968 W CN2022115968 W CN 2022115968W WO 2023116035 A1 WO2023116035 A1 WO 2023116035A1
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Prior art keywords
transistor
electrically connected
control
circuit structure
layer
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PCT/CN2022/115968
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English (en)
French (fr)
Inventor
任庆荣
邢汝博
李俊峰
王刚
崔霜
张豪峰
郭瑞
孙丹丹
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合肥维信诺科技有限公司
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Publication of WO2023116035A1 publication Critical patent/WO2023116035A1/zh
Priority to US18/362,124 priority Critical patent/US20230400353A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
    • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
    • G01T1/16—Measuring radiation intensity
    • G01T1/20—Measuring radiation intensity with scintillation detectors
    • G01T1/2018—Scintillation-photodiode combinations
    • G01T1/20184—Detector read-out circuitry, e.g. for clearing of traps, compensating for traps or compensating for direct hits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J2001/4446—Type of detector
    • G01J2001/446—Photodiode

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a photosensitive circuit structure and an optical device.
  • X-ray (X-Ray) flat panel detectors have been widely used in medical testing, safety inspection, and industrial production.
  • the X-Ray flat panel detector uses transistor array technology to form a pixel array on the substrate, and a layer of coating that can convert X-rays into visible light, such as a fluorescent film or a flash film, is placed above the pixel array.
  • each pixel of the X-Ray flat panel detector includes a photoelectric conversion unit and a transistor switch.
  • X-rays are received by the X-Ray flat panel detector after passing through the irradiated object and converted into image output.
  • the embodiments of the present application provide a photosensitive circuit structure and an optical device, which can reduce the noise of the photosensitive circuit structure, improve the signal-to-noise ratio, and thus improve the performance of the optical device.
  • an embodiment of the present application provides a photosensitive circuit structure, including a photosensitive unit, a signal amplifying unit, and a control unit;
  • the photosensitive unit includes a photodiode and a reset transistor
  • the signal amplifying unit includes an amplifying transistor
  • the control unit It includes a control transistor;
  • the input end of the reset transistor is electrically connected to the power supply end, the output end of the reset transistor is electrically connected to the control end of the amplification transistor, and the control end of the reset transistor is electrically connected to the reset signal end;
  • the input end of the amplifying transistor is electrically connected to the power supply end, the output end of the amplifying transistor is electrically connected to the input end of the control transistor, and the control end of the control transistor is electrically connected to the control signal end;
  • the reset transistor The leakage current of the amplifying transistor is less than the leakage current of the amplifying transistor, and the leakage current of the control transistor is less than the leakage current of the amplifying transistor; the carrier
  • the photosensitive circuit structure provided in the embodiment of the present application includes a photosensitive unit, a signal amplifying unit, and a control unit.
  • the photosensitive unit includes a photodiode and a reset transistor
  • the signal amplifying unit includes an amplifying transistor
  • the control unit includes a control transistor.
  • the input end of the reset transistor is electrically connected to the power supply end, the output end of the reset transistor is electrically connected to the control end of the amplifying transistor, and the control end of the reset transistor is electrically connected to the reset signal end;
  • the input end of the amplifying transistor is electrically connected to the power supply end , the output terminal of the amplifying transistor is electrically connected to the input terminal of the control transistor, and the control terminal of the control transistor is electrically connected to the control signal terminal, so that the photosensitive unit can convert the light signal into an electrical signal, and the electrical signal can control the signal amplification unit to convert the power supply terminal
  • the electric signal is transmitted to the output end of the control unit, and then the function of controlling the photosensitive circuit structure can be realized.
  • the leakage current of the reset transistor By setting the leakage current of the reset transistor to be smaller than the leakage current of the amplification transistor, and setting the leakage current of the control transistor to be smaller than the leakage current of the amplification transistor, the problem of leakage current in the photosensitive circuit structure is effectively reduced, and the signal-to-noise of the photosensitive circuit structure is improved. Compare. By setting the carrier mobility of the reset transistor to be smaller than the carrier mobility of the amplifying transistor, and setting the carrier mobility of the reset transistor to be smaller than the carrier mobility of the control transistor, the signal response speed of the photosensitive circuit structure can be improved, Therefore, the working performance of the photosensitive circuit structure is improved.
  • the anode of the photodiode is electrically connected to the reverse bias voltage terminal
  • the cathode of the photodiode is electrically connected to the output terminal of the reset transistor and the amplifier between the control terminals of the transistor.
  • Such an arrangement can use the photodiode to convert the optical signal into an electrical signal, and at the same time reverse bias the signal to the photodiode through the reverse bias voltage terminal, so as to adjust different working processes of the photodiode and ensure its working performance.
  • the photosensitive unit includes a storage capacitor, the first electrode of the storage capacitor is electrically connected to the anode of the photodiode, and the second electrode of the storage capacitor is connected to the anode of the photodiode.
  • the cathode of the photodiode is electrically connected.
  • Such an arrangement can use the storage capacitor to store the electrical signal generated by the photodiode or provide a buffered electrical signal to the photodiode, thereby helping to ensure the stability of the electrical signal sent to the control terminal of the signal amplifying unit.
  • the photosensitive circuit structure further includes an operational amplifier unit, and an output terminal of the control unit is electrically connected to an input terminal of the operational amplifier unit.
  • the operational amplification unit is used to process the electrical signal output from the output terminal of the control unit for subsequent application in other components of the optical device.
  • the photosensitive circuit structure further includes a voltage dividing unit, and the input end of the voltage dividing unit is electrically connected to the output end of the control unit and the operational amplifier unit. Between the input terminals, the output terminal of the voltage dividing unit is electrically connected to the ground wire.
  • the voltage dividing unit can regulate the current in the circuit to protect the safety of the photosensitive circuit structure and the circuit of the operational amplifier unit.
  • the reset transistor is a metal oxide transistor or an amorphous silicon transistor
  • the amplifier transistor is a low-temperature polysilicon transistor, a high-speed metal oxide transistor, a silicon carbide transistor, a carbon Any one of nanotube transistors
  • the control transistor is any one of N-type high-speed metal oxide transistors, P-type low-temperature polysilicon transistors, and P-type carbon nanotube transistors.
  • Such setting is beneficial to reduce the leakage current of the reset transistor, ensure that the leakage current of the reset transistor is smaller than the leakage current of the amplifying transistor, reduce the signal energy loss in the process of converting the optical signal into an electrical signal, and improve the signal-to-noise ratio of the photosensitive circuit structure.
  • the active layer of the reset transistor includes indium gallium zinc oxide and/or indium tin zinc oxide; the active layer of the amplifying transistor and/or the control transistor
  • the source layer includes at least one of ITZO, IGXO, and polycrystalline IGZO, wherein X is copper-aluminum alloy.
  • Such setting is further beneficial to reduce the leakage current of the reset transistor, ensure that the leakage current of the reset transistor is smaller than the leakage current of the amplification transistor and the control transistor, reduce the signal energy loss in the process of converting the optical signal into an electrical signal, and improve the signal-to-noise ratio of the photosensitive circuit structure .
  • the photosensitive circuit structure includes at least two buffer layers; at least two of the reset transistor, the amplifying transistor and the control transistor use different active layers and respectively located on two different buffer layers.
  • Such an arrangement is not only beneficial to better use of the space in the extending direction of the buffer layer, but also beneficial to avoiding mutual interference between the transistors.
  • At least two buffer layers include a first buffer layer and a second buffer layer, and the reset transistor is disposed on the first buffer layer; the second buffer layer Located on the side of the first buffer layer away from the reset transistor, the control transistor and/or the amplifier transistor are disposed on the second buffer layer; both the reset transistor and the amplifier transistor are located on the There is a distance between the orthographic projections on the second buffer layer; or, there is a distance between the orthographic projections of the reset transistor and the control transistor on the second buffer layer.
  • Such an arrangement can ensure that the reset transistor and the amplifying transistor are structurally separated from each other, avoiding mutual interference between the two structures, and improving the stability of the two structures. It can ensure that the reset transistor and the control transistor are structurally separated from each other, avoiding mutual interference in the structure of the two, and improving the stability of the structures of the two.
  • the reset transistor includes a first source, a first drain, a first gate, and a first active layer disposed on the first buffer layer, the Both the first source and the first drain are electrically connected to the first active layer, and one of the first source and the first drain is an input terminal of the reset transistor, so The other of the first source and the first drain is an output terminal of the reset transistor.
  • the cathode of the photodiode is electrically connected to the other of the first source and the first drain, and a first gate is arranged between the first gate and the first active layer
  • the insulating layer, the first gate can control the turn-on or turn-off of the first source and the first drain.
  • the side of the first active layer and the first gate far away from the first buffer layer is provided with an interlayer dielectric layer
  • the interlayer dielectric layer is provided with a first trench and a second trenches, the first trenches and the second trenches are arranged at intervals along the extending direction of the first buffer layer, the first trenches and the second trenches respectively expose the source regions of the first active layer and a drain region; at least part of one of the first source and the first drain is located in the first trench and is electrically connected to the source region of the first active layer; at least Part of the other of the first source and the first drain is located in the second trench and is electrically connected to the drain region of the first active layer.
  • Such an arrangement can ensure the structural integrity of the reset transistor and improve the working stability of the reset transistor.
  • the control transistor and/or the amplification transistor includes a second source, a second drain, a second gate and a
  • the second active layer, the second source and the second drain are electrically connected to the second active layer, one of the second source and the second drain is The control transistor and/or the input terminal of the amplification transistor, the other of the second source and the second drain is the output terminal of the control transistor and/or the amplification transistor, so A second gate insulating layer is disposed between the second gate and the second active layer.
  • the second gate insulating layer covers a side of the second active layer away from the second buffer layer
  • the first buffer layer covers the second gate insulating layer away from the second
  • the interlayer dielectric layer covers the side of the first buffer layer away from the second buffer layer
  • the side of the interlayer dielectric layer away from the second buffer layer is also provided with a second A passivation layer
  • the first passivation layer covers the side of the first source and the first drain away from the first buffer layer.
  • the first passivation layer can improve the protection effect on the first source and the first drain.
  • the side of the second active layer away from the second buffer layer is provided with a third groove and a fourth groove at intervals, and the third groove and the fourth groove both penetrate through the first groove at the same time.
  • Such an arrangement can ensure the structural integrity of the control transistor and/or the amplifying transistor, and improve the working stability of the reset transistor.
  • the photodiode is arranged on a side of the interlayer dielectric layer away from the first buffer layer, and the photodiode is far away from the side of the first buffer layer.
  • One side is provided with a light guide layer. Such a setting can increase the light receiving amount of the photodiode.
  • a planarization layer and a second passivation layer are arranged in sequence on the side of the first passivation layer away from the first buffer layer, and the planarization layer Covering the second source and the second drain, the second passivation layer covers a side of the light guiding layer away from the first buffer layer.
  • an embodiment of the present application provides an optical device, including a substrate and a plurality of photosensitive circuit structures as described above, and the plurality of photosensitive circuit structures are arranged in an array on the substrate.
  • the optical device provided by the embodiment of the present application includes a substrate and multiple photosensitive circuit structures, and the multiple photosensitive circuit structures are arranged in an array on the substrate, which is beneficial to improve the performance of the optical device.
  • the photosensitive circuit structure includes a photosensitive unit, a signal amplifying unit and a control unit.
  • the output end of the photosensitive unit is electrically connected to the control end of the signal amplifying unit; the input end of the signal amplifying unit is electrically connected to the power supply end, and the output end of the signal amplifying unit is connected to the control unit
  • the input terminal is electrically connected, so that the photosensitive unit can convert the optical signal into an electrical signal, and the electrical signal can control the signal amplifying unit to output the electrical signal of the power supply terminal to the control unit, and finally output under the control of the control unit, and then control the photosensitive circuit.
  • the leakage current of the reset transistor of the photosensitive unit and the leakage current of the control transistor of the control unit are smaller than the leakage current of the amplifying transistor of the signal amplifying unit, the problem of leakage current in the photosensitive circuit structure is effectively reduced, and the The signal-to-noise ratio of photosensitive circuit structures.
  • the carrier mobility of the reset transistor is lower than the carrier mobility of the amplifying transistor and the control transistor simultaneously, the signal response speed of the photosensitive circuit structure can be improved, thereby improving the working performance of the photosensitive circuit structure.
  • Fig. 1 is the equivalent circuit diagram of the photosensitive circuit structure provided in the related art
  • Fig. 2 is the working sequence diagram of the equivalent circuit diagram of photosensitive circuit structure in Fig. 1;
  • FIG. 3 is an equivalent circuit diagram 1 of a photosensitive circuit structure provided in the embodiment of the present application.
  • Fig. 4 is an equivalent circuit diagram 2 of a photosensitive circuit structure provided by the embodiment of the present application.
  • FIG. 5 is an equivalent circuit diagram 3 of a photosensitive circuit structure provided in the embodiment of the present application.
  • Fig. 6 is a schematic structural diagram of a reset transistor and a control transistor of a photosensitive circuit structure provided by an embodiment of the present application.
  • the photosensitive circuit structure of the pixel of the image detector usually includes a plurality of transistors.
  • the following describes in detail in conjunction with the equivalent circuit diagram of the photosensitive circuit structure with three transistors and its working timing diagram.
  • FIG. 1 is an equivalent circuit diagram of the photosensitive circuit structure provided in the related art
  • FIG. 2 is a working timing diagram of the equivalent circuit diagram of the photosensitive circuit structure in FIG. 1 .
  • the equivalent circuit of the photosensitive circuit structure in the related art includes a reset switch transistor Trst, a source follower transistor Tsf, a selection switch transistor Tsel and a photodiode PD.
  • the input terminal of the reset switch transistor Trst is electrically connected to the reset voltage Vrst
  • the output terminal of the reset switch transistor Trst is electrically connected to the negative terminal of the photodiode PD
  • the control terminal of the reset switch transistor Trst is electrically connected to the reset signal terminal.
  • the input end of the source follower transistor Tsf is electrically connected to the power supply voltage Vdd
  • the output end of the source follower transistor Tsf is electrically connected to the input end of the selection switch transistor Tsel
  • the control end of the source follower transistor Tsf is connected to the photodiode PD
  • the negative terminal is electrically connected.
  • the control terminal of the selection switch transistor Tsel is electrically connected to the selection signal terminal, and the output terminal of the selection switch transistor Tsel outputs a voltage Vout.
  • the reset switch transistor Trst is turned on by the reset signal Reset, and the photodiode PD is reverse-biased to the reset voltage Vrst, and the reset voltage Vrst has an effect on the PN junction of the photodiode PD.
  • the capacitor is charged, and the charged charge Qrst satisfies the following relationship:
  • CPD in Formula 1 is the capacitance of the PN junction capacitance.
  • the photon excitation generates electron-hole pairs on the PN junction, causing the charge on the PN junction capacitance to recombine, and the charge on the PN junction capacitance QPD begins Falling from the value of Qrst, the voltage VPD of the photodiode PD starts to fall from the value of Vrst.
  • the charge quantity QPD of the PN junction capacitance decreases at different rates, and the rate at which the voltage VPD of the photodiode PD decreases is also different.
  • the voltage VPD of the photodiode PD is converted into an output voltage Vout after passing through the source follower transistor Tsf.
  • the photodiode PD When the photodiode PD is irradiated with different light intensities Iph, after the same exposure time Texp, a greater number of photogenerated carriers will be generated on the PN junction under higher light intensity, so that the charge on the PN junction capacitance will be recombined and the charge QPD will be larger. Low, the voltage VPD of the photodiode PD is also lower.
  • the light intensity Iph1 ⁇ Iph2 ⁇ Iph3 correspondingly, the amount of charge on the PN junction capacitance QPD1>QPD2>QPD3, the voltage of the photodiode PD VPD1>VPD2>VPD3, the voltage of the photodiode PD passes through the source follower transistor
  • the voltage Vo1>Vo2>Vo3 output by Tsf, here the voltage gain of the source follower transistor Tsf is slightly less than 1.
  • the time between the end of the reset signal (Reset) and the start of the selection signal (Select) is the actual exposure time Texp of the photodiode PD.
  • the reset switch transistor Trst, the source follower transistor Tsf, and the selection switch transistor Tsel generally use polysilicon transistors. Due to the relatively large leakage current of the polysilicon transistor switch, the shot noise of the polysilicon transistor in the photosensitive circuit structure is relatively large, and the shot noise satisfies the following relationship:
  • ⁇ TFT-shot in Equation 2 is the shot noise
  • I TFT-off is the leakage current of the transistor
  • ⁇ FT is the integration time. It can be seen that the larger the leakage current is, the larger the shot noise is.
  • Leakage current can be understood as the current flowing between the source and drain of a transistor in the off state.
  • the reset switch transistor Trst it controls the reverse bias process of the photodiode PD, so if the leakage current at the reset switch transistor Trst is large, it will seriously affect the output of the electrical signal after the photoelectric conversion of the photodiode PD, The energy of the output electrical signal is low, which in turn leads to a decrease in the signal-to-noise ratio of the photosensitive circuit structure. Therefore, when the photosensitive circuit structure is applied in an image detector, the image signal output by the image detector is affected by the noise signal in the photosensitive circuit structure, which will also lead to a decrease in the quality of the output image.
  • an embodiment of the present application provides a photosensitive circuit structure and an optical device.
  • the photosensitive circuit structure includes a photosensitive unit, a signal amplifying unit, and a control unit.
  • the photosensitive unit includes a photodiode and a reset transistor, and the signal amplifying unit includes an amplifying transistor.
  • the control unit includes a control transistor.
  • the input end of the reset transistor is electrically connected to the power supply end, the output end of the reset transistor is electrically connected to the control end of the amplifying transistor, the control end of the reset transistor is electrically connected to the reset signal end; the input end of the amplifying transistor is electrically connected to the power supply end, and the amplifying transistor
  • the output end of the control transistor is electrically connected to the input end of the control transistor, and the control end of the control transistor is electrically connected to the control signal end, so that the photosensitive unit can convert the light signal into an electrical signal, and the electrical signal can control the signal amplification unit to transmit the electrical signal of the power supply end To the control output terminal of the control unit, and then realize the function of controlling the photosensitive circuit structure.
  • the leakage current of the reset transistor By setting the leakage current of the reset transistor to be smaller than the leakage current of the amplification transistor, and setting the leakage current of the control transistor to be smaller than the leakage current of the amplification transistor, the problem of leakage current in the photosensitive circuit structure is effectively reduced, and the signal-to-noise ratio of the photosensitive circuit structure is improved.
  • the carrier mobility of the reset transistor By setting the carrier mobility of the reset transistor to be smaller than that of the amplifying transistor, and setting the carrier mobility of the reset transistor to be smaller than that of the control transistor, the signal response of the photosensitive circuit structure can be improved. speed, thereby improving the working performance of the photosensitive circuit structure.
  • FIG. 3 is an equivalent circuit diagram 1 of a photosensitive circuit structure provided by the embodiment of the present application
  • Fig. 4 is an equivalent circuit diagram 2 of a photosensitive circuit structure provided by the embodiment of the present application
  • Fig. 5 is an equivalent circuit diagram provided by the embodiment of the present application Figure 3 of an equivalent circuit of a photosensitive circuit structure
  • FIG. 6 is a structural schematic diagram of a reset transistor and a control transistor of a photosensitive circuit structure provided by an embodiment of the present application.
  • the embodiment of the present application provides a photosensitive circuit structure, including: a photosensitive unit 10 , a signal amplifying unit 20 and a control unit 30 .
  • the input terminal of the photosensitive unit 10 is electrically connected to the power supply terminal VDD, and the output terminal of the photosensitive unit 10 is electrically connected to the control terminal of the signal amplifying unit 20 .
  • the input terminal of the signal amplifying unit 20 is electrically connected to the power supply terminal VDD, and the output terminal of the signal amplifying unit 20 is electrically connected to the input terminal of the control unit 30 .
  • the photosensitive circuit structure can be arranged on the substrate 100, and the material of the substrate 100 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound or silicon-on-insulator (silicon-on-insulator, referred to as SOI) etc.; It is an organic or inorganic film layer, such as polyimide (Polyimide, referred to as PI) etc.; it can also be other materials known to those skilled in the art, and the substrate 100 can provide the rest of the structural layers arranged on the substrate 100. support base.
  • the electrical connection between the photosensitive unit 10 , the signal amplifying unit 20 , the control unit 30 and the power supply terminal VDD can be implemented by embedding metal wires.
  • the photosensitive unit 10 is provided with a reset transistor T1
  • the signal amplifying unit 20 is provided with an amplifying transistor T2
  • the control unit 30 is provided with a control transistor T3.
  • the input terminal of the reset transistor T1 is electrically connected to the power supply terminal VDD
  • the output terminal of the reset transistor T1 is electrically connected to the control terminal of the amplifying transistor T2
  • the control terminal of the reset transistor T1 is electrically connected to the reset signal terminal Rst.
  • the input terminal of the amplifying transistor T2 is electrically connected to the power supply terminal VDD
  • the output terminal of the amplifying transistor T2 is electrically connected to the input terminal of the control transistor T3
  • the control terminal of the control transistor T3 is electrically connected to the control signal terminal Gate.
  • the input terminal of the reset transistor T1 and the input terminal of the amplifying transistor T2 may also be connected to different voltage terminals as in the above-mentioned related art.
  • connecting both of them to the power supply terminal VDD can effectively simplify the structure of the photosensitive circuit.
  • the reset transistor T1 in the photosensitive unit 10 is turned on to control the power supply terminal VDD to input an electrical signal to the photosensitive unit 10 , and is turned off when the photosensitive unit 10 has an initial electrical signal.
  • the photosensitive unit 10 can convert the received light signal into an electrical signal, and after the electrical signal is recombined with the initial electrical signal of the photosensitive unit 10, it is transmitted to the control terminal of the amplifier transistor T2 of the signal amplifying unit 20 , so that the output terminal of the amplifying transistor T2 can follow the electrical signal, and output a corresponding following electrical signal.
  • the following electrical signal can be transmitted to the input terminal of the control transistor T3, and the purpose of controlling the on-off of the control transistor T3 can be achieved by controlling the control signal input to the control terminal of the control transistor T3.
  • the control transistor T3 is turned on, the following electrical signal can be transmitted to the output terminal of the control transistor T3.
  • the leakage current of the reset transistor T1 is smaller than the leakage current of the amplifying transistor T2; the leakage current of the control transistor T3 is also smaller than the leakage current of the amplifying transistor T2.
  • the leakage current of the reset transistor T1 is smaller than the leakage current of the control transistor T3.
  • the photosensitive unit 10 combines the electrical signal converted from the optical signal with the original electrical signal to obtain a composite electrical signal.
  • the noise in the photosensitive unit 10 it is necessary to reduce the noise in the photosensitive unit 10, and the noise and Transistor leakage current is positively correlated. Therefore, the authenticity of the composite electrical signal can be ensured by reducing the leakage current of the reset transistor T1 in the photosensitive unit 10, thereby helping to ensure that the composite electrical signal can be finally output after passing through the subsequent signal amplifying unit 20 and the control unit 30 Output electrical signal with high signal-to-noise ratio.
  • control transistor T3 needs to transmit the signal amplifying unit 20 to the input terminal of the control transistor T3 to follow the electrical signal output, and the leakage current of the control transistor T3 is smaller, and the electrical signal output through the control transistor T3 is doped Therefore, the signal-to-noise ratio of the output electrical signal can be further improved by reducing the leakage current of the control transistor T3.
  • the carrier mobility of the reset transistor T1 can be set to be smaller than the carrier mobility of the amplifying transistor T2; at the same time, the carrier mobility of the reset transistor T1 can be set The rate is less than the carrier mobility of the control transistor T3.
  • the amplifying transistor T2 can follow the composite electrical signal to generate a following electrical signal, and transmit the following electrical signal to the control transistor T3, and the control transistor T3 can control the output process of the following electrical signal, so the carrier mobility of the two can be improved, which can The electrical signal output efficiency of the photosensitive circuit structure is effectively improved, thereby improving the working performance of the photosensitive circuit structure.
  • the carrier mobility of the amplifying transistor T2 may be greater than that of the control transistor T3; or, the carrier mobility of the amplifying transistor T2 may be smaller than that of the control transistor T3.
  • the photosensitive unit 10 may include a photodiode D1, the anode of the photodiode D1 is electrically connected to the reverse bias voltage terminal Vbias, and the photodiode D1 The negative electrode is electrically connected between the output terminal of the reset transistor T1 and the control terminal of the amplifying transistor T2.
  • Such a setting can provide a reset signal to the photosensitive unit 10 through the reset transistor T1 during the reset process to turn on the power supply terminal VDD and the photodiode D1 to realize the initial power-on state of the photodiode D1.
  • the reverse bias signal is provided to the photodiode D1 through the reverse bias voltage terminal Vbias to realize the reverse bias process of the photodiode D1, thereby adjusting the different working states of the photodiode D1 to ensure The working performance of the photosensitive unit 10.
  • the reset signal sent by the reset signal terminal Rst controls the control terminal of the reset transistor T1 to turn on the reset transistor T1, so that the electrical signal of the power supply terminal VDD is transmitted to the control terminal of the amplifying transistor T2.
  • the cathode of the photodiode D1 may directly contact one of the source and drain of the reset transistor T1 to realize the electrical connection between the two.
  • the reset transistor T1, the photodiode D1, the reset signal terminal Rst, and the reverse bias voltage terminal Vbias may not have a mutual abutting relationship in structure, and the electrical connection relationship between the above structures may also be It may be implemented by embedding metal wires, which is not limited in this embodiment.
  • the first is the initial power-on stage.
  • the reset transistor T1 is turned on under the control of the reset signal terminal Rst, and the power supply terminal VDD is electrically connected to the negative side of the photodiode D1.
  • the reset signal terminal Rst controls the reset transistor T1 to turn off.
  • the node of the photodiode D1 connected to the output terminal of the reset transistor T1 obtains an initial voltage and then enters an operating state.
  • the photodiode D1 Under the light environment, the photodiode D1 generates a photocurrent and injects electrons into the negative side of the photodiode D1, so that the voltage on the negative side of the photodiode D1 continues to decrease.
  • the voltage drop on the cathode side of the photodiode D1 is ⁇ . Since the negative side of the photodiode D1 is electrically connected to the control terminal of the amplifying transistor T2 at the same time, when the voltage on the negative side of the photodiode D1 continues to decrease, the output voltage of the amplifying transistor T2 also decreases accordingly.
  • control transistor T3 is turned on under the control of the control signal terminal Gate, and the input end of the control transistor T3 is turned on with the output end of the amplifying transistor T2.
  • the change of the photocurrent is positively correlated with the voltage change of the negative side of the photodiode D1
  • the voltage change ⁇ of the negative side of the photodiode D1 is positively correlated with the light intensity, so the greater the light intensity, the negative side of the photodiode D1
  • the larger the voltage change ⁇ the smaller the voltage value on the negative side of the photodiode D1, the smaller the output voltage value of the amplifying transistor T2, and the smaller the output voltage signal of the control transistor T3, so that the control transistor T3 can be controlled by detecting
  • the magnitude of the output voltage signal is used to determine the light intensity irradiated on the photodiode D1.
  • a reverse bias stage which can be set between multiple photoelectric conversion stages according to the needs of users, so as to ensure the working performance of the photodiode D1. Stablize. Since electrons are injected into the cathode side of the photodiode D1 for a long time, it is in a biased state, which affects the photoelectric conversion process of the photodiode D1. Therefore, it needs to be adjusted for reverse bias.
  • the specific process may be to provide a reverse bias voltage to the anode side of the photodiode D1 through the reverse bias voltage terminal Vbias, eliminate the bias voltage in the photodiode D1, and maintain the high-efficiency photoelectric conversion performance of the photodiode D1.
  • the anode of D1 is electrically connected, and the second electrode C1b of the storage capacitor C1 is electrically connected to the cathode of the photodiode D1.
  • the storage capacitor C1 can be used to store the electrical signal generated by the photodiode D1 when it is illuminated or to provide a buffered electrical signal to the photodiode D1, which is beneficial to ensure that the electrical signal on the negative side of the photodiode D1 can be output stably to improve the signal amplification unit. 20 control effects.
  • the photosensitive circuit structure further includes an operational amplifier unit 40 , and the output terminal of the control unit 30 is electrically connected to the input terminal of the operational amplifier unit 40 .
  • Operational amplification unit 40 comprises operational amplifier L, capacitor Cs, adjustable capacitor Cf and relevant double sampling circuit CDS1 and CDS2, the output end of control unit 30 is connected with the inverting input end of operational amplifier L, the forward input end of operational amplifier L
  • the reference input terminal REF_TFT is connected, and the output terminal of the operational amplifier L is connected with correlated double sampling circuits CDS1 and CDS2.
  • the two electrodes of the adjustable capacitor Cf are respectively connected to the inverting input terminal of the operational amplifier L and the output terminal of the operational amplifier L.
  • the operational amplification unit 40 can perform operational processing on the electrical signal output from the output terminal of the control unit 30, so as to subsequently generate a high-quality image.
  • the photosensitive circuit structure further includes a voltage dividing unit 50.
  • the voltage dividing unit 50 may include a transistor T4, a resistor, and the like. This embodiment is described by taking the voltage dividing unit 50 as the transistor T4 as an example.
  • the input terminal of the voltage dividing unit 50 is electrically connected between the output terminal of the control unit 30 and the input terminal of the operational amplifier unit 40, and the output terminal of the voltage dividing unit 50 is electrically connected to the ground line GND, so that the current in the circuit can be adjusted.
  • the photosensitive circuit structure has three transistors as an example for illustration. In other embodiments, the photosensitive circuit structure may also include four transistors, five transistors, and seven transistors. The method and principle are similar to the photosensitive circuit structure of this embodiment, and will not be repeated here.
  • the photosensitive circuit structure may include at least two buffer layers, and at least two of the reset transistor T1 , the amplifying transistor T2 and the control transistor T3 adopt different active layers and are respectively located on two different buffer layers.
  • the photosensitive circuit structure may include two buffer layers, the reset transistor T1 may be located on one of the buffer layers, and the amplifying transistor T2 and the control transistor T3 may be located on the other buffer layer; or, the photosensitive circuit structure may include three buffer layers. layer, the reset transistor T1, the amplifying transistor T2 and the control transistor T3 are respectively located on the three buffer layers.
  • the reset transistor T1 can be a metal oxide transistor or an amorphous silicon transistor.
  • the amplifying transistor T2 can be any one of low-temperature polysilicon transistor, high-speed metal oxide transistor, silicon carbide transistor, and carbon nanotube transistor.
  • the control transistor T3 may be any one of an N-type high-speed metal oxide transistor, a P-type low-temperature polysilicon transistor, and a P-type carbon nanotube transistor.
  • both the amplifying transistor T2 and the control transistor T3 may be polysilicon transistors, since polysilicon transistors have higher mobility, faster response speed and stronger ability to resist light interference, it is not only beneficial to ensure that the control transistor T3 and The performance and reliability of the amplifying transistor T2; and it is beneficial to ensure that the carrier mobility of the reset transistor T1 is lower than that of the amplifying transistor T2 and the carrier mobility of the control transistor T3.
  • the at least two buffer layers include a first buffer layer 210, the reset transistor T1 is disposed on the first buffer layer 210, and the first buffer layer 210 is located above the substrate 100; the first Other structural layers may be disposed between the buffer layer 210 and the substrate 100 , and the material of the first buffer layer 210 may be silicon oxide, silicon nitride or other materials known to those skilled in the art.
  • the reset transistor T1 includes one 11 of the first source and the first drain, the other 12 of the first source and the first drain, a first gate 13 and a The first active layer 14, one 11 of the first source and the first drain is the input terminal of the reset transistor T1, and the other 12 of the first source and the first drain is the output of the reset transistor T1 end.
  • One 11 of the first source and the first drain and the other 12 of the first source and the first drain are electrically connected to the first active layer 14, and the first gate 13 can be connected to the first
  • the active layer 14 is stacked, and the first gate insulating layer 310 is arranged between the first gate 13 and the first active layer 14, and the electrical signal applied to the first gate 13 can be controlled to make the first source
  • the first active layer 14 between the one 11 of the first drain and the other 12 of the first source and the first drain is turned on or off.
  • the material of the first gate insulating layer 310 may be silicon oxide or other materials known to those skilled in the art.
  • the reset transistor T1 is an N-type transistor, one of the first source and the first drain 11 is the first drain, and the other 12 of the first source and the first drain is first source. In some embodiments, the reset transistor T1 is a P-type transistor, one of the first source and the first drain 11 is the first source, and the other 12 of the first source and the first drain is first drain.
  • the first gate 13 and the first active layer 14 are stacked, including the realization that the first active layer 14 is disposed between the first buffer layer 210 and the first gate 13, and the first gate 13 An implementation manner of being disposed between the first buffer layer 210 and the first active layer 14 .
  • the material of one 11 of the first source and the first drain, and the other 12 of the first source and the first drain may include aluminum, titanium or other materials known to those skilled in the art; the first The material of the gate 13 can be molybdenum or other materials known to those skilled in the art.
  • the side of the first active layer 14 and the first gate 13 away from the first buffer layer 210 may both be provided with an interlayer dielectric layer 400, and the interlayer dielectric layer 400 is provided with a first trench and a second trench at intervals, The first trench and the second trench respectively expose the source region and the drain region of the first active layer 14 . At least part of one 11 of the first source and the first drain is located in the first trench, and is electrically connected to one of the source region and the drain region of the first active layer 14; the first source At least part of the other 12 of the electrode and the first drain is located in the second trench and is electrically connected to the other of the source region and the drain region of the first active layer 14 . In this way, the structural integrity of the reset transistor T1 can be guaranteed, and its working stability can be improved.
  • the material of the interlayer dielectric layer 400 may be silicon oxide, silicon nitride or other materials known to those skilled in the art.
  • the first trench and the second trench are arranged at intervals along the extending direction of the first buffer layer 210, which can effectively avoid the mutual interference between the two in structure, and at the same time avoid the first source in the first trench
  • One 11 of the first drain and the other 12 of the first source and the first drain in the second trench are in operation, and the problem of electrical signal interference occurs, so as to ensure the stable operation of the reset transistor T1 sex.
  • the active layer of the reset transistor T1 may include indium gallium zinc oxide and/or indium tin zinc oxide. That is, the first active layer 14 may be indium gallium zinc oxide, indium tin zinc oxide, or a combination of indium gallium zinc oxide and indium tin zinc oxide.
  • the use of indium gallium zinc oxide and indium tin zinc oxide can reduce the leakage current of the reset transistor T1 and reduce the signal energy loss in the process of converting the optical signal into an electrical signal, which is conducive to improving the signal-to-noise ratio of the reset transistor T1, which in turn is beneficial to Improve the performance of photosensitive circuit structures.
  • the manufacturing cost of indium gallium zinc oxide and indium tin zinc oxide is low, which is beneficial to saving the cost of the photosensitive circuit structure.
  • At least two buffer layers further include a second buffer layer 220, and the second buffer layer 220 is located on the side of the first buffer layer 210 away from the reset transistor T1.
  • the control transistor T3 and/or the amplifying transistor T2 are disposed on the second buffer layer 220, and there is a distance between the orthographic projections of the reset transistor T1 and the amplifying transistor T2 on the second buffer layer 220; or, the reset transistor T1 and the control transistor There is a distance between the two orthographic projections of T3 on the second buffer layer 220 .
  • the control transistor T3 and the reset transistor T1 are separated from each other in structure, on the one hand, it can effectively avoid two
  • the mutual interference in the structure reduces the difficulty of preparing the photosensitive circuit structure.
  • it can also avoid the electrical signal interference between the two during use, thereby improving the stability of the structure and working performance of the two.
  • the amplifying transistor T2 and the reset transistor T1 are separated from each other structurally, on the one hand, the mutual interference in the structure of the two can be effectively avoided, and the difficulty of preparing the photosensitive circuit structure is reduced; Electrical signal interference occurs during use, thereby improving the stability of both structures and working performance.
  • the distance between the control transistor T3 and the reset transistor T1, or the distance between the amplifying transistor T2 and the reset transistor T1 is not limited.
  • control transistor T3 and the amplifying transistor T2 in the photosensitive circuit structure can be the same.
  • the transistor disposed on the second buffer layer 220 in FIG. 6 is the control transistor T3 , and the amplifying transistor T2 is not shown in FIG. 6 .
  • This embodiment is described by taking the structure of the control transistor T3 as an example with reference to FIG.
  • the control transistor T3 (amplification transistor T2) includes one 31 of the second source and the second drain, the other 32 of the second source and the second drain, a second gate 33, and a second The second active layer 34 on the buffer layer 220, one 31 of the second source and the second drain is the input terminal of the control transistor T3 (amplifying transistor T2), and one of the second source and the second drain is The other 32 is the output terminal of the control transistor T3 (amplifier transistor T2 ), and the second gate 33 is the control terminal of the control transistor T3 (amplifier transistor T2 ).
  • the control transistor T3 (amplifying transistor T2) is an N-type transistor, one of the second source and the second drain 31 is the second drain, and one of the second source and the second drain is The other 32 is the second source.
  • the control transistor T3 (amplifying transistor T2) is a P-type transistor, one of the second source and the second drain 31 is the second source, and one of the second source and the second drain is The other 32 is the second drain.
  • the second gate 33 and the second active layer 34 are stacked, including an implementation in which the second active layer 34 is disposed between the second buffer layer 220 and the second gate 33, and the second gate 33 An implementation manner of being disposed between the second buffer layer 220 and the second active layer 34 .
  • the material of one 31 of the second source and the second drain, and the other 32 of the second source and the second drain may include molybdenum, neodymium and copper, or aluminum and titanium, or the technology in the art other materials known to those skilled in the art; the material of the second grid 33 may be molybdenum or other materials known to those skilled in the art.
  • the material of the second gate insulating layer 320 may be silicon oxide or other materials known to those skilled in the art.
  • the second gate insulating layer 320 may cover the side of the second active layer 34 away from the second buffer layer 220 .
  • the first buffer layer 210 covers the side of the second gate insulating layer 320 away from the second buffer layer 220
  • the interlayer dielectric layer 400 covers the side of the first buffer layer 210 away from the second buffer layer 220
  • the interlayer dielectric layer 400 is away from
  • One side of the second buffer layer 220 is further provided with a first passivation layer 510 .
  • the control transistor T3 (amplifying transistor T2) further includes a third trench and a fourth trench, and in the extending direction along the second buffer layer 220, the third trench and the fourth trench are arranged at intervals in the second active layer. 34 away from the second buffer layer 220, the third trench and the fourth trench both penetrate the first passivation layer 510, the interlayer dielectric layer 400, the first buffer layer 210 and the second gate insulating layer 320 , and expose the source region and the drain region of the second active layer 34 respectively.
  • the material of the interlayer dielectric layer 400 may be silicon oxide, silicon nitride or other materials known to those skilled in the art.
  • the third groove and the fourth groove are arranged at intervals along the extending direction of the second buffer layer 220, which can effectively avoid mutual interference in the structure between the two. , while avoiding that one of the second source and the second drain 31 in the third trench and the other 32 of the second source and the second drain in the fourth trench are in operation, occur The problem of electrical signal interference is guaranteed to ensure the stability of the polysilicon transistor. This embodiment also does not limit the distance between the third groove and the fourth groove.
  • control transistor T3 when the control transistor T3 is working, referring to FIGS.
  • the other 32 of the second gate outputs an electrical signal, and the second gate 33 makes one of the second source and the second drain 31 and the second source and the second drain under the control of the control signal terminal Gate.
  • the other 32 is turned on, so that the electrical signal output by the amplifying transistor T2 can be output from the output terminal of the control transistor T3.
  • the control transistor T3 is a high-speed metal oxide transistor
  • the active layer of the control transistor T3 may include at least one of ITZO, IGXO, and polycrystalline IGZO, wherein X is copper-aluminum alloy.
  • the control transistor T3 may be an NMOS field effect transistor with a relatively small leakage current, so as to meet the requirements of high mobility and low leakage of the control transistor T3, thereby improving the performance of the photosensitive circuit structure.
  • the amplifying transistor T2 works (the amplifying transistor T2 is not shown in FIG. 6 ), one of the source and the drain of the amplifying transistor T2 is connected to the power supply terminal VDD, and the source and the drain of the amplifying transistor T2 The other is connected to the input terminal of the control transistor T3, the gate of the amplifying transistor T2 is connected to the negative side of the photodiode D1, and the electrical signal on the negative side of the photodiode D1 can control the gate of the amplifying transistor T2, so that the amplifying transistor T2 The source and the drain of T2 are turned on, and the electrical signal of the power supply terminal VDD can be transmitted to the other of the source and the drain of the amplifying transistor T2.
  • the active layer of the amplifying transistor T2 may include at least one of ITZO, IGXO, and polycrystalline IGZO, wherein X is copper-aluminum alloy.
  • the photodiode D1 is arranged on the side of the interlayer dielectric layer 400 away from the first buffer layer 210 , and the cathode of the photodiode D1 is connected to the first source and the first source.
  • the other 12 of the first drains is electrically connected.
  • the photodiode D1 is located on the side of the interlayer dielectric layer 400 that is close to the other 12 of the first source and the first drain, so as to be connected to the other of the first source and the first drain. 12 abut to form an electrical connection relationship between the two.
  • the first electrode C1a of the storage capacitor C1 in the photosensitive circuit structure is located on the side of the second buffer layer 220 away from the substrate 100, and the second gate insulating layer 320 covers the side of the first electrode C1a away from the substrate 100.
  • the second electrode C1b of the storage capacitor C1 is provided on the side of the second gate insulating layer 320 away from the substrate 100 , and the first electrode C1a and the second electrode C1b are separated by the second gate insulating layer 320 .
  • the side of the second electrode C1b away from the substrate 100 is covered with the first buffer layer 210 and the interlayer dielectric layer 400 in sequence.
  • the other 12 of the first source electrode and the first drain electrode is electrically connected to the second electrode C1b through the via hole provided in the first buffer layer 210 and the interlayer dielectric layer 400, of course, the second electrode C1b may It is indirectly electrically connected to the cathode of the photodiode D1 through the other 12 of the first source and the first drain.
  • a light guide layer 700 is provided on the side of the photodiode D1 away from the first buffer layer 210, and the light guide layer 700 can increase the amount of light received into the anode side of the photodiode D1, thereby improving the photoelectric conversion of the photodiode D1 performance.
  • the light guiding layer 700 can be made of indium tin oxide, indium zinc oxide or other materials known to those skilled in the art.
  • the first passivation layer 510 covers one side of the first source and the first drain 11 and the other 12 of the first source and the first drain away from the first buffer layer 210, the first The passivation layer 510 can effectively protect various structural layers located between the first passivation layer 510 and the substrate 100 and improve the structural stability of the photosensitive circuit structure.
  • the side of the first passivation layer 510 away from the first buffer layer 210 is provided with a planarization layer 600, and the planarization layer 600 covers one 31 of the second source and the second drain and the second source and the second The other 32 of the drains, the setting of the planarization layer 600 can reduce the setting of one 31 of the second source and the second drain and the setting of the other 32 of the second source and the second drain difficulty.
  • the second passivation layer 520 is provided on the side of the planarization layer 600 away from the first buffer layer 210 , and the second passivation layer 520 covers the side of the light guide layer 700 away from the first buffer layer 210 .
  • the second passivation layer 520 may protect various structural layers between the second passivation layer 520 and the substrate 100 . Based on the fact that one 31 of the second source and the second drain and the other 32 of the second source and the second drain are located on the side of the first passivation layer 510 away from the substrate 100, therefore, the second The second passivation layer 520 can also further protect the one 31 of the second source and the second drain and the other 32 of the second source and the second drain.
  • the first passivation layer 510 and the second passivation layer 520 can be selected from any one of silicon oxide, silicon oxynitride, and silicon nitride, and multiple composite materials.
  • the material of the planarization layer may be resin or other materials known to those skilled in the art.
  • a third buffer layer 230 and a fourth buffer layer 240 may be provided on the substrate 100, the third buffer layer 230 is located on the side of the fourth buffer layer 240 away from the substrate 100, the third buffer layer 230 and the fourth buffer layer
  • the ground wire GND can be set between 240.
  • the second buffer layer 220 is located on a side of the third buffer layer 230 away from the substrate 100 .
  • the other 32 of the second source and the second drain passes through the first passivation layer 510, the interlayer dielectric layer 400, the first buffer layer 210, the second gate insulating layer 320, the second buffer layer 220 and the via holes of the third buffer layer 230 are electrically connected to the ground line GND.
  • the material of the second buffer layer 220 , the third buffer layer 230 and the fourth buffer layer 240 may be the same as that of the first buffer layer 210 , which will not be repeated here.
  • an embodiment of the present application further provides an optical device, including a substrate and a plurality of photosensitive circuit structures, and the plurality of photosensitive circuit structures are arranged in an array on the substrate.
  • the structure of the light-sensing circuit is the same as that of the above-mentioned light-sensing circuit, and can bring about the same or similar technical effects. For details, please refer to the above description, and details will not be repeated here.
  • the optical device provided in the embodiment of the present application may be a medical flat panel detector or the like.
  • the optical device may include a substrate and a plurality of photosensitive circuit structures, and the plurality of photosensitive circuit structures are arranged in an array on the substrate to form a photosensitive flat panel, and power supply lines and control signal lines corresponding to the photosensitive circuit structures are arranged around the photosensitive flat panel. , reset signal line, reverse bias voltage line, etc., the surface of the photosensitive plate is provided with a coating that can convert radiation into visible light, such as a fluorescent film or a flash film, so that the photosensitive plate can realize its own function.
  • the optics can also include a radiation emitter, which can be an X-ray emitter, for example.
  • the ray emitter can be arranged opposite to the photosensitive plate, and the object to be detected is located between the ray emitter and the photosensitive plate, and the rays emitted by the ray emitter pass through the object to be detected and are received by the photosensitive plate.
  • the coating can convert the received rays into visible light, which can be processed by the photosensitive circuit structure that makes up the photosensitive plate, and finally form an image.
  • the high signal-to-noise ratio of the photosensitive circuit structure is conducive to improving the quality of the image generated by the optical device.
  • the optical device provided in the embodiment of the present application may also be an optical fingerprint sensor, and may also be other optical devices that require the application of a photosensitive circuit structure.

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Abstract

本申请提供一种感光电路结构和光学器件，该感光电路结构包括感光单元、信号放大单元和控制单元；感光单元包括光电二极管与复位晶体管，信号放大单元包括放大晶体管，控制单元包括控制晶体管；复位晶体管的输入端与供电端电连接，输出端与放大晶体管的控制端电连接，控制端与复位信号端电连接；放大晶体管的输入端与供电端电连接，输出端与控制晶体管的输入端电连接，控制端与控制信号端电连接；复位晶体管和控制晶体管的漏电流均小于放大晶体管的漏电流；复位晶体管的载流子迁移率小于放大晶体管的载流子迁移率和控制晶体管的载流子迁移率。有利于降低感光电路结构的漏电流，提高感光电路结构中信号传输的信噪比，从而提升光学器件的性能。

Description

感光电路结构和光学器件
本申请要求于2021年12月24日提交中国专利局、申请号为202111603737.9、申请名称为“感光电路结构和光学器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，特别涉及一种感光电路结构和光学器件。
背景技术
随着半导体技术的发展，X射线(X-Ray)平板探测器在医疗检测、安全检查、工业生产得到了广泛应用。X-Ray平板探测器是利用晶体管阵列技术在衬底上形成像素阵列，并在像素阵列上方设置一层能够将X射线转换成可见光的涂层，如，荧光膜或闪光膜。相关技术中，X-Ray平板探测器的每个像素都包括一个光电变换单元和晶体管开关。具体应用时，X射线穿过被照射的物体后被X-Ray平板探测器接收并转换成图像输出。
然而，X-Ray平板探测器的图像品质仍需进一步提高，这也是业界持续研究的重要课题。
发明内容
本申请实施例提供一种感光电路结构和光学器件，可以降低感光电路结构的噪声，提高信噪比，从而提升光学器件的性能。
第一方面，本申请实施例提供一种感光电路结构，包括感光单元、信号放大单元和控制单元；所述感光单元包括光电二极管与复位晶体管，所述信号放大单元包括放大晶体管，所述控制单元包括控制晶体管；所述复位晶体管的输入端与供电端电连接，所述复位晶体管的输出端与所述放大晶体管的控制端电连接，所述复位晶体管的控制端与复位信号端电连接；所述放大晶体管的输入端与所述供电端电连接，所述放大晶体管的输出端与所述控制晶体管的输入端电连接，所述控制晶体管的控制端与控制信号端电连接；所 述复位晶体管的漏电流小于所述放大晶体管的漏电流，且所述控制晶体管的漏电流小于所述放大晶体管的漏电流；所述复位晶体管的载流子迁移率小于所述放大晶体管的载流子迁移率，且所述复位晶体管的载流子迁移率小于所述控制晶体管的载流子迁移率。
本申请实施例提供的感光电路结构包括感光单元、信号放大单元和控制单元，感光单元包括光电二极管与复位晶体管，信号放大单元包括放大晶体管，控制单元包括控制晶体管。通过设置复位晶体管的输入端与供电端电连接，复位晶体管的输出端与放大晶体管的控制端电连接，复位晶体管的控制端与复位信号端电连接；设置放大晶体管的输入端与供电端电连接，放大晶体管的输出端与控制晶体管的输入端电连接，控制晶体管的控制端与控制信号端电连接，从而使感光单元可以将光信号转换成电信号，电信号可以控制信号放大单元将供电端的电信号传递至控制单元的输出端，进而可以实现控制感光电路结构的功能。
通过设置复位晶体管的漏电流设置小于放大晶体管的漏电流，并设置控制晶体管的漏电流小于放大晶体管的漏电流，有效减小感光电路结构中的漏电流的问题，提高该感光电路结构的信噪比。通过设置复位晶体管的载流子迁移率小于放大晶体管的载流子迁移率，并设置复位晶体管的载流子迁移率小于控制晶体管的载流子迁移率，可以提高感光电路结构的信号响应速度，从而提升该感光电路结构的工作性能。
在上述感光电路结构的一种可能的实现方式中，所述光电二极管的正极与反向偏置电压端电连接，所述光电二极管的负极电连接在所述复位晶体管的输出端和所述放大晶体管的控制端之间。
这样的设置可以利用光电二极管将光信号转变为电信号，同时通过反向偏置电压端向光电二极管反向偏置信号，从而调整光电二极管的不同工作过程，保证其的工作性能。
在上述感光电路结构的一种可能的实现方式中，所述感光单元包括存储电容，所述存储电容的第一电极与所述光电二极管的正极电连接，所述存储电容的第二电极与所述光电二极管的负极电连接。
这样的设置可以利用存储电容存储光电二极管产生的电信号或向光电二极管提供缓冲电信号，从而有利于保证输送至信号放大单元的控制端的电信 号的稳定性。
在上述感光电路结构的一种可能的实现方式中，所述感光电路结构还包括运算放大单元，所述控制单元的输出端与所述运算放大单元的输入端电连接。
运算放大单元用于对控制单元的输出端输出的电信号进行处理，以便后续应用在光学器件的其他元器件中。
在上述感光电路结构的一种可能的实现方式中，所述感光电路结构还包括分压单元，所述分压单元的输入端电连接在所述控制单元的输出端和所述运算放大单元的输入端之间，所述分压单元的输出端与地线电连接。
分压单元可以调控电路中的电流，以保护该感光电路结构以及上述运算放大单元的电路的安全性。
在上述感光电路结构的一种可能的实现方式中，所述复位晶体管为金属氧化物晶体管或非晶硅晶体管；所述放大晶体管为低温多晶硅晶体管、高迁金属氧化物晶体管、碳化硅晶体管、碳纳米管晶体管中的任一种；所述控制晶体管为N型高迁金属氧化物晶体管、P型低温多晶硅晶体管、P型碳纳米管晶体管中的任一种。
这样的设置有利于降低复位晶体管的漏电流，保证复位晶体管的漏电流小于放大晶体管的漏电流，降低光信号转换为电信号过程中信号能量损失，提高感光电路结构的信噪比。
在上述感光电路结构的一种可能的实现方式中，所述复位晶体管的有源层包括铟镓锌氧化物和/或铟锡锌氧化物；所述放大晶体管和/或所述控制晶体管的有源层包括ITZO、IGXO、多晶IGZO中的至少一种，其中，X为铜铝合金。
这样的设置进一步有利于降低复位晶体管的漏电流，保证复位晶体管的漏电流小于放大晶体管和控制晶体管的漏电流，降低光信号转换为电信号过程中信号能量损失，提高感光电路结构的信噪比。
在上述感光电路结构的一种可能的实现方式中，所述感光电路结构包括至少两个缓冲层；所述复位晶体管、放大晶体管与控制晶体管三者中的至少两个采用不同的有源层并分别位于两个不同的所述缓冲层上。
这样的设置不仅有利于更好的利用缓冲层延伸方向上的空间，而且有利 于避免各晶体管之间相互干涉。
在上述感光电路结构的一种可能的实现方式中，至少两个所述缓冲层包括第一缓冲层与第二缓冲层，所述复位晶体管设置于第一缓冲层上；所述第二缓冲层位于所述第一缓冲层背离所述复位晶体管的一侧，所述控制晶体管和/或所述放大晶体管设置于所述第二缓冲层上；所述复位晶体管、所述放大晶体管两者在所述第二缓冲层上的正投影之间具有间距；或，所述复位晶体管、所述控制晶体管两者在所述第二缓冲层上的正投影之间具有间距。
这样的设置可以保证复位晶体管和放大晶体管在结构上相互分离，避免两者结构上的相互干扰，以提高两者结构的稳定性。可以保证复位晶体管和控制晶体管在结构上相互分离，避免两者结构上的相互干扰，以提高两者结构的稳定性。
在上述感光电路结构的一种可能的实现方式中，复位晶体管包括第一源极、第一漏极、第一栅极和设置在所述第一缓冲层上的第一有源层，所述第一源极和所述第一漏极均与所述第一有源层电连接，所述第一源极和所述第一漏极中的一者为所述复位晶体管的输入端，所述第一源极和所述第一漏极中的另一者为所述复位晶体管的输出端。所述光电二极管的负极与所述第一源极和所述第一漏极中的另一者电连接，所述第一栅极和所述第一有源层之间设置有第一栅极绝缘层，第一栅极可以控制第一源极和第一漏极的导通或截止。
其中，所述第一有源层和所述第一栅极远离所述第一缓冲层的一侧均设置有层间介质层，所述层间介质层上设置有第一沟槽和第二沟槽，第一沟槽和第二沟槽在沿第一缓冲层的延伸方向间隔设置，所述第一沟槽和所述第二沟槽分别暴露所述第一有源层的源极区和漏极区；至少部分所述第一源极和所述第一漏极中的一者位于所述第一沟槽中，并与所述第一有源层的源极区电连接；至少部分所述第一源极和所述第一漏极中的另一者位于所述第二沟槽中，并与所述第一有源层的漏极区电连接。
这样的设置可以保证复位晶体管的结构完整性，提高复位晶体管的工作稳定性。
在上述感光电路结构的一种可能的实现方式中，所述控制晶体管和/或所述放大晶体管包括第二源极、第二漏极、第二栅极和设置在所述第二缓冲层 上的第二有源层，所述第二源极和所述第二漏极均与所述第二有源层电连接，所述第二源极和所述第二漏极中的一者为所述控制晶体管和/或所述放大晶体管的输入端，所述第二源极和所述第二漏极中的另一者为所述控制晶体管和/或所述放大晶体管的输出端，所述第二栅极和所述第二有源层之间设置有第二栅极绝缘层。
其中，所述第二栅极绝缘层覆盖所述第二有源层的远离所述第二缓冲层的一侧，所述第一缓冲层覆盖所述第二栅极绝缘层远离所述第二缓冲层的一侧，所述层间介质层覆盖所述第一缓冲层远离所述第二缓冲层的一侧，所述层间介质层远离所述第二缓冲层的一侧还设置有第一钝化层，所述第一钝化层覆盖所述第一源极和所述第一漏极的远离所述第一缓冲层的一侧。第一钝化层可以提高对第一源极和第一漏极的保护效果。
所述第二有源层的背离所述第二缓冲层的一侧间隔设置有第三沟槽和第四沟槽，所述第三沟槽和所述第四沟槽均同时贯穿所述第一钝化层、所述层间介质层、所述第一缓冲层和所述第二栅极绝缘层，并分别暴露所述第二有源层的源极区和漏极区；至少部分所述第二源极和所述第二漏极中的一者位于所述第三沟槽中，并与所述第二有源层的源极区电连接，至少部分所述第二源极和所述第二漏极中的另一者位于所述第四沟槽中，并与所述第二有源层的漏极区电连接。
这样的设置可以保证控制晶体管和/或放大晶体管的结构完整性，提高复位晶体管的工作稳定性。
在上述感光电路结构的一种可能的实现方式中，所述光电二极管设置在所述层间介质层的远离所述第一缓冲层的一侧，所述光电二极管远离所述第一缓冲层的一侧设置有导光层。这样的设置可以提高光电二极管的光接收量。
在上述感光电路结构的一种可能的实现方式中，所述第一钝化层的远离所述第一缓冲层的一侧依次设置有平坦化层与第二钝化层，所述平坦化层覆盖所述第二源极和所述第二漏极，所述第二钝化层覆盖所述导光层的远离所述第一缓冲层的一侧。这样的设置可以提高对该感光电路结构的保护效果。
第二方面，本申请实施例提供一种光学器件，包括衬底和多个如上述的感光电路结构，多个所述感光电路结构呈阵列排布在衬底上。
本申请实施例提供的光学器件包括衬底和多个感光电路结构，通过使多 个感光电路结构呈阵列排布在衬底上，从而有利于提升光学器件性能。其中，感光电路结构包括感光单元、信号放大单元和控制单元。通过设置感光单元的输入端与供电端电连接，感光单元的输出端与信号放大单元的控制端电连接；设置信号放大单元的输入端与供电端电连接，信号放大单元的输出端与控制单元的输入端电连接，从而感光单元可以将光信号转换成电信号，电信号可以控制信号放大单元将供电端的电信号输出至控制单元，最终在控制单元的控制下输出，进而可以实现控制感光电路结构的功能。
具体的，通过将感光单元的复位晶体管的漏电流和控制单元的控制晶体管的漏电流均设置为小于信号放大单元的放大晶体管的漏电流，有效减小感光电路结构中的漏电流的问题，提升感光电路结构的信噪比。通过设置复位晶体管的载流子迁移率同时小于放大晶体管的载流子迁移率和控制晶体管的载流子迁移率，可以提高感光电路结构的信号响应速度，从而提升该感光电路结构的工作性能。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的感光电路结构和光学器件所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作以简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中提供的感光电路结构的等效电路图；
图2为图1中感光电路结构的等效电路图的工作时序图；
图3为本申请实施例提供的一种感光电路结构的等效电路图一；
图4为本申请实施例提供的一种感光电路结构的等效电路图二；
图5为本申请实施例提供的一种感光电路结构的等效电路图三；
图6为本申请实施例提供的一种感光电路结构的复位晶体管和控制晶体 管的结构示意图。
具体实施方式
相关技术中，图像探测器的像素的感光电路结构中通常包括多个晶体管。下面结合具有三个晶体管的感光电路结构的等效电路图以及其工作时序图进行详细说明。图1为相关技术中提供的感光电路结构的等效电路图，图2为图1中感光电路结构的等效电路图的工作时序图。参照图1所示，相关技术中的感光电路结构的等效电路中包括重置开关晶体管Trst、源极跟随器晶体管Tsf、选择开关晶体管Tsel和光电二极管PD。
重置开关晶体管Trst的输入端和重置电压Vrst电连接，重置开关晶体管Trst的输出端和光电二极管PD的负极端电连接，重置开关晶体管Trst的控制端和重置信号端电连接。源极跟随器晶体管Tsf的输入端和电源电压Vdd电连接，源极跟随器晶体管Tsf的输出端和选择开关晶体管Tsel的输入端电连接，源极跟随器晶体管Tsf的控制端和光电二极管PD的负极端电连接。选择开关晶体管Tsel的控制端与选择信号端电连接，选择开关晶体管Tsel的输出端输出电压Vout。
结合图2所示，在曝光开始之前，通过重置信号Reset开启重置开关晶体管Trst，把光电二极管PD反向偏置到重置电压Vrst上，该重置电压Vrst对光电二极管PD的PN结电容充电，充电的电荷量Qrst满足下述关系：
Qrst＝CPD·Vrst         式一
其中，式一中CPD为PN结电容的电容量。重置开关晶体管Trst完成充电后，在重置信号Reset的作用下关闭，使光电二极管PD结点(即光电二极管PD的负极端)成为悬浮状态，此时，当入射光照强度Iph＝0时，光电二极管PD的重置电压Vrst和电荷量Qrst都保持在PN结电容上。
在曝光开始时，当光电二极管的PN结上有入射光照射时，光量子激发在PN结上产生电子-空穴对，使PN结电容上的电荷发生复合，PN结电容上的电荷量QPD开始从Qrst值下降，光电二极管PD的电压VPD开始从Vrst值下降。在受不同光照强度Iph照射的光电二极管PD上，PN结电容的电荷量QPD下降的速率不同，光电二极管PD的电压VPD下降的速率也不同。 光电二极管PD的电压VPD经过源极跟随器晶体管Tsf后转换成输出电压Vout。
光电二极管PD在不同光照强度Iph照射下，经过相同曝光时间Texp后，更高光照强度下在PN结上产生更多数量的光生载流子，使PN结电容上的电荷复合后电荷量QPD更低，光电二极管PD的电压VPD也更低。因此，当光照强度Iph1＜Iph2＜Iph3时，对应的，PN结电容上的电荷量QPD1＞QPD2＞QPD3，光电二极管PD的电压VPD1＞VPD2＞VPD3，光电二极管PD的电压经过源极跟随器晶体管Tsf输出的电压Vo1＞Vo2＞Vo3，这里源极跟随器晶体管Tsf的电压增益略小于1。其中，从重置信号(Reset)结束，到选择信号(Select)开始之间的时间为光电二极管PD的实际曝光时间Texp。
在上述的感光电路结构中，重置开关晶体管Trst、源极跟随器晶体管Tsf、选择开关晶体管Tsel一般均选用多晶硅晶体管。由于多晶硅晶体管开关的漏电流比较大，从而导致感光电路结构中多晶硅晶体管的散粒噪声比较大，散粒噪声满足下述关系：
σ TFT-shot＝sqrt(I TFT-off*τ FT)       式二
其中，式二中σ TFT-shot为散粒噪声，I TFT-off为晶体管的漏电流，τ FT为积分时间，由此可见，漏电流越大，散粒噪声越大。
漏电流可以理解为晶体管关闭状态下源极和漏极之间流过的电流。对于重置开关晶体管Trst而言，其控制了光电二极管PD反向偏置过程，因此如果重置开关晶体管Trst处的漏电流较大，会严重影响光电二极管PD的光电转换后电信号的输出，造成输出的电信号能量较低，进而导致该感光电路结构的信噪比降低。因此，当该感光电路结构应用在图像探测器中，图像探测器输出的图像信号，受到感光电路结构中的噪声信号的影响，也会导致输出图像的品质降低。
为了解决上述技术问题，本申请实施例提供一种感光电路结构和光学器件，该感光电路结构包括感光单元、信号放大单元和控制单元，感光单元包括光电二极管与复位晶体管，信号放大单元包括放大晶体管，控制单元包括控制晶体管。复位晶体管的输入端与供电端电连接，复位晶体管的输出端与放大晶体管的控制端电连接，复位晶体管的控制端与复位信号端电连接；放大晶体管的输入端与供电端电连接，放大晶体管的输出端与控制晶体管的输 入端电连接，控制晶体管的控制端与控制信号端电连接，从而使感光单元可以将光信号转换成电信号，电信号可以控制信号放大单元将供电端的电信号传递至控制单元的控制输出端，进而可以实现控制感光电路结构的功能。
通过设置复位晶体管的漏电流小于放大晶体管的漏电流，并设置控制晶体管的漏电流小于放大晶体管的漏电流，有效减小感光电路结构中的漏电流的问题，提高该感光电路结构的信噪比。同时，通过设置复位晶体管的载流子迁移率小于放大晶体管的载流子迁移率，并设置复位晶体管的载流子迁移率小于控制晶体管的载流子迁移率，可以提高感光电路结构的信号响应速度，从而提升该感光电路结构的工作性能。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图3为本申请实施例提供的一种感光电路结构的等效电路图一；图4为本申请实施例提供的一种感光电路结构的等效电路图二；图5为本申请实施例提供的一种感光电路结构的等效电路图三；图6为本申请实施例提供的一种感光电路结构的复位晶体管和控制晶体管的结构示意图。
参照图3至图6所示，本申请实施例提供一种感光电路结构，包括：感光单元10、信号放大单元20和控制单元30。
感光单元10的输入端与供电端VDD电连接，感光单元10的输出端与信号放大单元20的控制端电连接。信号放大单元20的输入端与供电端VDD电连接，信号放大单元20的输出端与控制单元30的输入端电连接。
感光电路结构可以设置在衬底100上，衬底100的材料可以是单晶硅、多晶硅、无定形硅、硅锗化合物或绝缘体上硅(silicon-on-insulator，简称为SOI)等；也可以是有机或无机膜层，例如聚酰亚胺(Polyimide，简称为PI)等；还可以是本领域技术人员已知的其他材料，衬底100可以为设置在衬底100上的其余结构层提供支撑基础。感光单元10、信号放大单元20、控制单元30以及供电端VDD之间的电连接可以通过埋入金属线的方式实现。
结合图3所示，该感光单元10中设置有复位晶体管T1，信号放大单元 20中设置有放大晶体管T2，控制单元30中设置有控制晶体管T3。在该感光电路结构中，复位晶体管T1的输入端与供电端VDD电连接，复位晶体管T1的输出端与放大晶体管T2的控制端电连接，复位晶体管T1的控制端与复位信号端Rst电连接。放大晶体管T2的输入端与供电端VDD电连接，放大晶体管T2的输出端与控制晶体管T3的输入端电连接，控制晶体管T3的控制端与控制信号端Gate电连接。
示例性的，复位晶体管T1的输入端和放大晶体管T2的输入端也可以如同上述的相关技术中一样，分别连接不同的电压端。本实施例中将两者同时连接至供电端VDD可以有效简化该感光电路结构。
本实施例提供的感光电路结构的工作过程可以是：
在感光单元10受到光线照射之前，感光单元10中的复位晶体管T1导通以控制供电端VDD向感光单元10输入电信号，并在感光单元10具有初始电信号时关断。在感光单元10受到光线照射时，感光单元10可以将接收的光信号转变为电信号，该电信号与感光单元10的初始电信号复合后，传递至信号放大单元20的放大晶体管T2的控制端，以使放大晶体管T2的输出端可以跟随该电信号，并输出与之对应的跟随电信号。该跟随电信号可以传输至控制晶体管T3的输入端，通过控制输入控制晶体管T3的控制端的控制信号，可以实现控制控制晶体管T3的通断的目的。当控制晶体管T3导通时，该跟随电信号可以传递至控制晶体管T3的输出端。
需要强调的是，在本实施例中，复位晶体管T1的漏电流小于放大晶体管T2的漏电流；控制晶体管T3的漏电流也小于放大晶体管T2的漏电流。示例性的，复位晶体管T1的漏电流小于控制晶体管T3的漏电流。
就复位晶体管T1而言，感光单元10是将由光信号转变的电信号与初始电信号复合以获得复合电信号，为了保证复合电信号的真实性，需要降低感光单元10中的噪声，而噪声和晶体管的漏电流正相关。因此，可以通过降低感光单元10中复位晶体管T1的漏电流的方式，以保证复合电信号的真实性，从而有利于保证复合电信号经过后续的信号放大单元20及控制单元30后，最终可以输出高信噪比的输出电信号。
就控制晶体管T3而言，控制晶体管T3需要将信号放大单元20传输至控制晶体管T3的输入端的跟随电信号输出，而控制晶体管T3的漏电流越小， 经由控制晶体管T3输出的电信号中掺杂的噪声就越少，因此，可以通过降低控制晶体管T3的漏电流的方式，以进一步提高输出电信号的信噪比。
作为一种实施方式，为提高该感光电路结构的响应速度，可以设置复位晶体管T1的载流子迁移率小于放大晶体管T2的载流子迁移率；同时，可以设置复位晶体管T1的载流子迁移率小于控制晶体管T3的载流子迁移率。基于放大晶体管T2可以跟随复合电信号产生跟随电信号，并将跟随电信号传递至控制晶体管T3，而控制晶体管T3可以控制跟随电信号的输出过程，因此提高两者的载流子迁移率，可以有效提高感光电路结构的电信号输出效率，从而提升感光电路结构的工作性能。放大晶体管T2的载流子迁移率可以大于控制晶体管T3的载流子迁移率；或者，放大晶体管T2的载流子迁移率可以小于控制晶体管T3的载流子迁移率。
参照图3至图5所示，本申请实施例提供的一种实现方式中，感光单元10可以包括光电二极管D1，光电二极管D1的正极与反向偏置电压端Vbias电连接，光电二极管D1的负极电连接在复位晶体管T1的输出端和放大晶体管的T2的控制端之间。
这样的设置可以在复位过程中通过复位晶体管T1向感光单元10提供复位信号，以导通供电端VDD和光电二极管D1，实现光电二极管D1的初始上电的状态。在反向偏置过程中，通过反向偏置电压端Vbias向光电二极管D1提供反向偏置信号，以实现光电二极管D1的反向偏置过程，从而调整光电二极管D1的不同工作状态，保证感光单元10的工作性能。
其中，复位信号端Rst发出的复位信号通过控制复位晶体管T1的控制端，可以使复位晶体管T1导通，从而使供电端VDD的电信号输送至放大晶体管T2的控制端。
参照图6所示，光电二极管D1的负极可以直接与复位晶体管T1的源极和漏极中的一个电极抵接，以实现两者的电连接。当然，在一些实施例中，复位晶体管T1、光电二极管D1、复位信号端Rst以及反向偏置电压端Vbias之间在结构上可不存在相互抵接的关系，上述结构之间的电连接关系也可以通过埋入金属线的方式实现，本实施例对此并不加以限制。
下面结合光电二极管D1详细说明本实施例的感光单元10的具体工作过程：
首先是初始上电阶段，复位晶体管T1在复位信号端Rst的控制下导通，供电端VDD与光电二极管D1的负极侧电连接，预设时间之后，复位信号端Rst控制复位晶体管T1关断。在这个过程中，光电二极管D1的与复位晶体管T1的输出端连接的节点处获取初始电压后进入工作状态。
接着是光电转换阶段，在光照环境下，光电二极管D1产生光电流并向光电二极管D1的负极侧注入电子，以使光电二极管D1的负极侧的电压持续降低。在光电转换阶段，光电二极管D1的负极侧的电压降低量为δ。由于光电二极管D1的负极侧同时与放大晶体管T2控制端电连接，因此，在光电二极管D1的负极侧的电压持续降低的过程中，放大晶体管T2的输出电压也跟随降低。
继而是电信号读取阶段，感光单元10曝光一段时间后，控制晶体管T3在控制信号端Gate的控制下导通，控制晶体管T3的输入端与放大晶体管T2的输出端导通，获取来自放大晶体管T2的输出端的电压信号，并通过控制晶体管T3的输出端输出该电压信号。
其中，由于光电流的变化与光电二极管D1的负极侧的电压变化正相关，而光电二极管D1的负极侧的电压变化量δ与光照强度正相关，所以光照强度越大，光电二极管D1的负极侧的电压变化量δ越大，光电二极管D1的负极侧的电压值越小，放大晶体管T2的输出电压值也越小，控制晶体管T3输出的电压信号也就越小，从而可以通过检测控制晶体管T3输出的电压信号大小来确定照射在光电二极管D1上的光照强度。
在上述的光电二极管D1的工作过程中，还会存在反向偏置阶段，该反向偏置阶段可以根据用户的需求设置在多个光电转换阶段之间，以保证光电二极管D1的工作性能的稳定。由于光电二极管D1长时间的负极侧注入电子，导致其处于偏置状态，影响光电二极管D1的光电转换过程。因此，需要对其进行反向偏置调整。具体的过程可以是，通过反向偏置电压端Vbias向光电二极管D1的正极侧提供反向偏置电压，消除光电二极管D1中的偏置电压，维持光电二极管D1的高效的光电转换性能。
为进一步维持感光单元10的电信号的稳定输出，参照图4所示，本申请实施例提供的一种实现方式中，感光单元10包括存储电容C1，存储电容C1的第一电极C1a与光电二极管D1的正极电连接，存储电容C1的第二电极 C1b与光电二极管D1的负极电连接。存储电容C1可以用于存储光电二极管D1在光照时产生的电信号或向光电二极管D1提供缓冲电信号，从而有利于保证光电二极管D1的负极侧的电信号可以稳定输出，以提高对信号放大单元20的控制效果。
如图5所示，本申请实施例提供的一种实现方式中，感光电路结构还包括运算放大单元40，控制单元30的输出端与运算放大单元40的输入端电连接。运算放大单元40包括运算放大器L、电容器Cs、可调电容器Cf以及相关双取样电路CDS1和CDS2，控制单元30的输出端与运算放大器L的反相输入端连接，运算放大器L的正向输入端连接参考输入端REF_TFT，运算放大器L的输出端连接相关双取样电路CDS1和CDS2。可调电容器Cf的两个电极分别连接运算放大器L的反相输入端和运算放大器L的输出端。该运算放大单元40可以对控制单元30的输出端输出的电信号进行运算处理，以便后续生成高品质的图像。
本申请实施例提供的一种实现方式中，感光电路结构还包括分压单元50，示例性的，分压单元50可以包括晶体管T4、电阻等。本实施例以分压单元50为晶体管T4为例进行说明。分压单元50的输入端电连接在控制单元30的输出端和运算放大单元40的输入端之间，分压单元50的输出端与地线GND电连接，从而可以调控电路中的电流。
需要指出的是，本实施例中以感光电路结构具有三个晶体管为例进行说明，在其他实施例中，该感光电路结构同样可以包括四个晶体管、五个晶体管以及七个晶体管，其设置的方式及原理与本实施例的感光电路结构类似，此处不再赘述。
下面结合图6详细说明该感光电路结构的具体结构。感光电路结构可以包括至少两个缓冲层，复位晶体管T1、放大晶体管T2与控制晶体管T3三者中的至少两个采用不同的有源层并分别位于两个不同的缓冲层上。示例性的，感光电路结构可以包括两个缓冲层，复位晶体管T1可以位于其中一个缓冲层上，放大晶体管T2和控制晶体管T3可以位于另一个缓冲层上；或者，感光电路结构可以包括三个缓冲层，复位晶体管T1、放大晶体管T2和控制晶体管T3分别位于三个缓冲层上。
复位晶体管T1可以为金属氧化物晶体管或非晶硅晶体管。放大晶体管 T2可以为低温多晶硅晶体管、高迁金属氧化物晶体管、碳化硅晶体管、碳纳米管晶体管中的任一种。控制晶体管T3可以为N型高迁金属氧化物晶体管、P型低温多晶硅晶体管、P型碳纳米管晶体管中的任一种。
示例性的，放大晶体管T2和控制晶体管T3可以均为多晶硅晶体管，由于多晶硅晶体管具有较高的迁移率、较快的响应速度以及较强的抗光干扰能力，从而不仅有利于保证控制晶体管T3和放大晶体管T2的性能和可靠性；而且有利于保证复位晶体管T1的载流子迁移率小于放大晶体管T2的载流子迁移率和控制晶体管T3的载流子迁移率。
本申请实施例提供的一种实现方式中，至少两个缓冲层包括第一缓冲层210，复位晶体管T1设置于第一缓冲层210上，第一缓冲层210位于衬底100的上方；第一缓冲层210与衬底100之间可以设置其他结构层，第一缓冲层210的材料可以是氧化硅、氮化硅或者本领域技术人员已知的其他材料。
复位晶体管T1包括第一源极和第一漏极中的一者11、第一源极和第一漏极中的另一者12、第一栅极13和设置在第一缓冲层210上的第一有源层14，第一源极和第一漏极中的一者11为复位晶体管T1的输入端，第一源极和第一漏极中的另一者12为复位晶体管T1的输出端。第一源极和第一漏极中的一者11和第一源极和第一漏极中的另一者12均与第一有源层14电连接，第一栅极13可以和第一有源层14层叠设置，且第一栅极13和第一有源层14之间设置有第一栅极绝缘层310，控制第一栅极13上施加的电信号，可以使第一源极和第一漏极中的一者11和第一源极和第一漏极中的另一者12之间的第一有源层14导通或者截止。其中，第一栅极绝缘层310的材料可以是氧化硅或者本领域技术人员已知的其他材料。在一些实施例中，复位晶体管T1为N型晶体管，第一源极和第一漏极中的一者11为第一漏极，第一源极和第一漏极中的另一者12为第一源极。在一些实施例中，复位晶体管T1为P型晶体管，第一源极和第一漏极中的一者11为第一源极，第一源极和第一漏极中的另一者12为第一漏极。
其中，第一栅极13和第一有源层14层叠设置，包括第一有源层14设置在第一缓冲层210和第一栅极13之间的实现方式，和，第一栅极13设置在第一缓冲层210和第一有源层14之间的实现方式。第一源极和第一漏极中的一者11、第一源极和第一漏极中的另一者12的材料可以包括铝、钛或者本 领域技术人员已知的其他材料；第一栅极13的材料可以是钼或者本领域技术人员已知的其他材料。
第一有源层14和第一栅极13远离第一缓冲层210的一侧可以均设置有层间介质层400，层间介质层400上间隔设置有第一沟槽和第二沟槽，第一沟槽和第二沟槽分别暴露第一有源层14的源极区和漏极区。第一源极和第一漏极中的一者11的至少部分位于第一沟槽中，并与第一有源层14的源极区和漏极区中的一个区电连接；第一源极和第一漏极中的另一者12的至少部分位于第二沟槽中，并与第一有源层14的源极区和漏极区中的另一个区电连接。这样，可以保证复位晶体管T1的结构完整性，提高其工作稳定性。其中，层间介质层400的材料可以是氧化硅、氮化硅或者本领域技术人员已知的其他材料。
具体的，第一沟槽和第二沟槽在沿第一缓冲层210的延伸方向间隔设置，可以有效避免两者之间在结构上相互干扰，同时避免第一沟槽中的第一源极和第一漏极中的一者11和第二沟槽中的第一源极和第一漏极中的另一者12在工作中，发生电信号干扰的问题，保证复位晶体管T1的工作稳定性。本实施例对第一沟槽和第二沟槽的间隔距离并不加以限制。
当复位晶体管T1为金属氧化物晶体管时，复位晶体管T1的有源层可以包括铟镓锌氧化物和/或铟锡锌氧化物。即，第一有源层14可以是铟镓锌氧化物、铟锡锌氧化物或铟镓锌氧化物和铟锡锌氧化物的组合。
由于复位晶体管T1的散粒噪声和漏电流直接相关，而铟镓锌氧化物和铟锡锌氧化物具有关态漏电流低、均匀性好的优点，因此，用铟镓锌氧化物和铟锡锌氧化物作为复位晶体管T1的有源层，可以减小复位晶体管T1的漏电流，降低光信号转换为电信号过程中信号能量损失，从而有利于提高复位晶体管T1的信噪比，进而有利于提高感光电路结构的性能。而且，铟镓锌氧化物和铟锡锌氧化物的制造成本低，从而有利于节约感光电路结构的成本。
继续参照图6所示，本申请实施例提供的一种实现方式中，至少两个缓冲层还包括第二缓冲层220，第二缓冲层220位于第一缓冲层210背离复位晶体管T1的一侧。控制晶体管T3和/或放大晶体管T2设置于第二缓冲层220上，复位晶体管T1和放大晶体管T2两者在第二缓冲层220上的正投影之间具有间距；或，复位晶体管T1和控制晶体管T3两者在第二缓冲层220上的 正投影之间具有间距。
基于控制晶体管T3、放大晶体管T2与复位晶体管T1分别控制感光电路结构中不同部位的电信号的导通，因此将控制晶体管T3与复位晶体管T1两者从结构上相互分离，一方面可以有效避免两者结构上的相互干扰，减小该感光电路结构的制备难度，另一方面也可以避免两者在使用过程中发生电信号干扰，从而提高两者结构和工作性能的稳定性。或，将放大晶体管T2与复位晶体管T1两者从结构上相互分离，一方面可以有效避免两者结构上的相互干扰，减小该感光电路结构的制备难度，另一方面也可以避免两者在使用过程中发生电信号干扰，从而提高两者结构和工作性能的稳定性。本实施例对控制晶体管T3与复位晶体管T1的间距，或，对放大晶体管T2与复位晶体管T1的间距并不加以限制。
控制晶体管T3和放大晶体管T2在感光电路结构中的具体结构可以相同。图6中设置在第二缓冲层220上的晶体管为控制晶体管T3，图6中未示出放大晶体管T2。本实施例以参照图6以控制晶体管T3的结构为例进行描述，本领域技术人员可以理解的是，本实施例中描述的控制晶体管T3的结构同样可以是放大晶体管T2的结构。
控制晶体管T3(放大晶体管T2)包括第二源极和第二漏极中的一者31、第二源极和第二漏极中的另一者32、第二栅极33和设置在第二缓冲层220上的第二有源层34，第二源极和第二漏极中的一者31为控制晶体管T3(放大晶体管T2)的输入端，第二源极和第二漏极中的另一者32为控制晶体管T3(放大晶体管T2)的输出端，第二栅极33为控制晶体管T3(放大晶体管T2)的控制端。第二源极和第二漏极中的一者31和第二源极和第二漏极中的另一者32均与第二有源层34电连接，第二栅极33和第二有源层34可以层叠设置，且第二栅极33和第二有源层34之间设置有第二栅极绝缘层320。在一些实施例中，控制晶体管T3(放大晶体管T2)为N型晶体管，第二源极和第二漏极中的一者31为第二漏极，第二源极和第二漏极中的另一者32为第二源极。在一些实施例中，控制晶体管T3(放大晶体管T2)为P型晶体管，第二源极和第二漏极中的一者31为第二源极，第二源极和第二漏极中的另一者32为第二漏极。
其中，第二栅极33和第二有源层34层叠设置，包括第二有源层34设置 在第二缓冲层220和第二栅极33之间的实现方式，和，第二栅极33设置在第二缓冲层220和第二有源层34之间的实现方式。第二源极和第二漏极中的一者31、第二源极和第二漏极中的另一者32的材料可以包括钼、钕和铜，或，铝和钛，或者本领域技术人员已知的其他材料；第二栅极33的材料可以是钼或者本领域技术人员已知的其他材料。第二栅极绝缘层320的材料可以是氧化硅或者本领域技术人员已知的其他材料。
示例性的，第二栅极绝缘层320可以覆盖在第二有源层34的远离第二缓冲层220的一侧。第一缓冲层210覆盖第二栅极绝缘层320远离第二缓冲层220的一侧，层间介质层400覆盖第一缓冲层210远离第二缓冲层220的一侧，层间介质层400远离第二缓冲层220的一侧还设置有第一钝化层510。
该控制晶体管T3(放大晶体管T2)还包括第三沟槽和第四沟槽，在沿第二缓冲层220的延伸方向上，第三沟槽和第四沟槽间隔设置在第二有源层34的背离第二缓冲层220的一侧，第三沟槽和第四沟槽均同时贯穿第一钝化层510、层间介质层400、第一缓冲层210和第二栅极绝缘层320，并分别暴露第二有源层34的源极区和漏极区。第二源极和第二漏极中的一者31的至少部分位于第三沟槽中，并与第二有源层34的源极区和漏极区中的一个区电连接，至少部分第二源极和第二漏极中的另一者32位于第四沟槽中，并与第二有源层34的源极区和漏极区中的另一个区电连接。其中，层间介质层400的材料可以是氧化硅、氮化硅或者本领域技术人员已知的其他材料。
其中，与第一沟槽和第二沟槽类似的是，第三沟槽和第四沟槽在沿第二缓冲层220的延伸方向间隔设置，可以有效避免两者之间在结构上相互干扰，同时避免第三沟槽中的第二源极和第二漏极中的一者31和第四沟槽中的第二源极和第二漏极中的另一者32在工作中，发生电信号干扰的问题，保证多晶硅晶体管的工作稳定性。本实施例同样对第三沟槽和第四沟槽的间隔距离不加以限制。
示例性的，控制晶体管T3工作时，参照图5和图6，第二源极和第二漏极中的一者31和放大晶体管T2的输出端连接，第二源极和第二漏极中的另一者32向外输出电信号，第二栅极33在控制信号端Gate的控制下，使第二源极和第二漏极中的一者31和第二源极和第二漏极中的另一者32导通，以使放大晶体管T2输出的电信号可以从控制晶体管T3的输出端输出。当控制 晶体管T3为高迁金属氧化物晶体管时，控制晶体管T3的有源层可以包括ITZO、IGXO、多晶IGZO中的至少一种，其中，X为铜铝合金。示例性的，控制晶体管T3可以为漏电流比较小的N型金属氧化物半导体场效应晶体管，以满足控制晶体管T3的高迁移率、低漏电的要求，从而有利于提升感光电路结构的性能。
示例性的，放大晶体管T2工作时(图6中未示出放大晶体管T2)，放大晶体管T2的源极和漏极中的一者和供电端VDD连接，放大晶体管T2的源极和漏极中的另一者和控制晶体管T3的输入端连接，放大晶体管T2的栅极和光电二极管D1的负极侧连接，光电二极管D1的负极侧的电信号可以控制放大晶体管T2的栅极，以使放大晶体管T2的源极和漏极导通，供电端VDD的电信号可以传输至放大晶体管T2的源极和漏极中的另一者。当放大晶体管T2为高迁金属氧化物晶体管时，放大晶体管T2的有源层可以包括ITZO、IGXO、多晶IGZO中的至少一种，其中，X为铜铝合金。
参照图6所示，本申请实施例提供的一种实现方式中，光电二极管D1设置在层间介质层400的远离第一缓冲层210的一侧，光电二极管D1的负极与第一源极和第一漏极中的另一者12电连接。
需要说明的是，光电二极管D1位于层间介质层400上靠近第一源极和第一漏极中的另一者12的一侧，便于与第一源极和第一漏极中的另一者12抵接形成两者的电连接关系。同时，该感光电路结构中的存储电容C1的第一电极C1a位于第二缓冲层220的远离衬底100的一侧，第二栅极绝缘层320覆盖在第一电极C1a的远离衬底100的一侧，同时第二栅极绝缘层320远离衬底100的一侧设置有存储电容C1的第二电极C1b，第一电极C1a和第二电极C1b通过第二栅极绝缘层320分隔。第二电极C1b远离衬底100的一侧依次覆盖有第一缓冲层210和层间介质层400。
其中，第一源极和第一漏极中的另一者12通过设置在第一缓冲层210和层间介质层400中的过孔与第二电极C1b电连接，当然，第二电极C1b可以通过第一源极和第一漏极中的另一者12间接与光电二极管D1的负极电连接。
并且，在光电二极管D1远离第一缓冲层210的一侧设置有导光层700，该导光层700可以提高进入光电二极管D1的正极一侧的光接收量，从而提高光电二极管D1的光电转换性能。导光层700可以是氧化铟锡、氧化铟锌 或者本领域技术人员已知的其他材料。
第一钝化层510覆盖第一源极和第一漏极中的一者11和第一源极和第一漏极中的另一者12的远离第一缓冲层210的一侧，第一钝化层510可以有效保护位于第一钝化层510和衬底100之间的各个结构层，提高感光电路结构的结构稳定性。第一钝化层510的远离第一缓冲层210的一侧设置有平坦化层600，平坦化层600覆盖第二源极和第二漏极中的一者31和第二源极和第二漏极中的另一者32，平坦化层600的设置可以减小第二源极和第二漏极中的一者31和第二源极和第二漏极中的另一者32的设置难度。进一步地，平坦化层600远离第一缓冲层210的一侧设置有第二钝化层520，第二钝化层520覆盖导光层700的远离第一缓冲层210的一侧。第二钝化层520可以保护位于第二钝化层520和衬底100之间的各个结构层。基于第二源极和第二漏极中的一者31和第二源极和第二漏极中的另一者32位于第一钝化层510的远离衬底100的一侧，因此，第二钝化层520也可以对第二源极和第二漏极中的一者31和第二源极和第二漏极中的另一者32起到进一步地保护效果。其中，第一钝化层510和第二钝化层520可以选用氧化硅、氮氧化硅和氮化硅中的任意一种与多种的复合材料。平坦化层的材料可以是树脂或者本领域技术人员已知的其他材料。
在衬底100上可以设置有第三缓冲层230和第四缓冲层240，第三缓冲层230位于第四缓冲层240的远离衬底100的一侧，第三缓冲层230和第四缓冲层240之间可以设置地线GND。第二缓冲层220位于第三缓冲层230的远离衬底100的一侧。其中，第二源极和第二漏极中的另一者32通过贯穿第一钝化层510、层间介质层400、第一缓冲层210、第二栅极绝缘层320、第二缓冲层220和第三缓冲层230的过孔，与地线GND电连接。其中，第二缓冲层220、第三缓冲层230和第四缓冲层240可以与第一缓冲层210的材料相同，此处不再赘述。
在上述基础上，本申请实施例还提供一种光学器件，包括衬底和多个感光电路结构，多个感光电路结构呈阵列排布在衬底上。其中，感光电路结构与上文的感光电路结构相同，并能带来相同或者类似的技术效果，具体可参照上文的描述，此处不再一一赘述。
在一种实现方式中，本申请实施例提供的光学器件可以是医疗平板探测 器等。光学器件可以包括衬底和多个感光电路结构，多个感光电路结构呈阵列排布在衬底上以形成感光平板，感光平板周围设置有与感光电路结构对应电连接的供电线、控制信号线、复位信号线、反向偏置电压线等，感光平板的表面设置有可以将射线转换成可见光的涂层，如，荧光膜或闪光膜，从而使感光平板可以实现自身的功能。光学器件还可以包括射线发射器，射线发射器例如可以是X射线发射器。
具体应用时，射线发射器可以和感光平板相对设置，待探测的物体位于射线发射器可以和感光平板之间，射线发射器发射出的射线穿过待探测的物体被感光平板接收，感光平板表面的涂层可以将接收到的射线转换成可见光，可见光可以被组成感光平板的感光电路结构处理，并最终形成图像。感光电路结构的高信噪比有利于提升光学器件生成图像的品质。
在其他可能的实现方式中，本申请实施例提供的光学器件也可以是光学指纹传感器，还可以是其他需要应用感光电路结构的光学器件。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (20)

  1. 一种感光电路结构，包括：
    感光单元，所述感光单元包括光电二极管与复位晶体管；
    信号放大单元，所述信号放大单元包括放大晶体管；
    控制单元，所述控制单元包括控制晶体管；
    其中，所述复位晶体管的输入端与供电端电连接，所述复位晶体管的输出端与所述放大晶体管的控制端电连接，所述复位晶体管的控制端与复位信号端电连接；所述放大晶体管的输入端与所述供电端电连接，所述放大晶体管的输出端与所述控制晶体管的输入端电连接，所述控制晶体管的控制端与控制信号端电连接；
    所述复位晶体管的漏电流小于所述放大晶体管的漏电流，且所述控制晶体管的漏电流小于所述放大晶体管的漏电流；
    所述复位晶体管的载流子迁移率小于所述放大晶体管的载流子迁移率，且所述复位晶体管的载流子迁移率小于所述控制晶体管的载流子迁移率。
  2. 根据权利要求1所述的感光电路结构，其中，所述光电二极管的正极与反向偏置电压端电连接，所述光电二极管的负极电连接在所述复位晶体管的输出端和所述放大晶体管的控制端之间；
    所述感光单元还包括存储电容，所述存储电容的第一电极与所述光电二极管的正极电连接，所述存储电容的第二电极与所述光电二极管的负极电连接。
  3. 根据权利要求1所述的感光电路结构，还包括运算放大单元，所述控制单元的输出端与所述运算放大单元的输入端电连接。
  4. 根据权利要求3所述的感光电路结构，其中，所述感光电路结构还包括分压单元，所述分压单元的输入端电连接在所述控制单元的输出端和所述运算放大单元的输入端之间，所述分压单元的输出端与地线电连接。
  5. 根据权利要求1所述的感光电路结构，其中，所述复位晶体管为金属 氧化物晶体管或非晶硅晶体管；
    所述放大晶体管为低温多晶硅晶体管、高迁金属氧化物晶体管、碳化硅晶体管、碳纳米管晶体管中的任一种；
    所述控制晶体管为N型高迁金属氧化物晶体管、P型低温多晶硅晶体管、P型碳纳米管晶体管中的任一种。
  6. 根据权利要求1或5所述的感光电路结构，其中，所述复位晶体管的有源层包括铟镓锌氧化物和铟锡锌氧化物中的至少一者；
    所述放大晶体管的有源层和所述控制晶体管的有源层中的至少一者包括ITZO、IGXO、多晶IGZO中的至少一种，其中，X为铜铝合金。
  7. 根据权利要求1-5中任一项所述的感光电路结构，其中，所述感光电路结构包括至少两个缓冲层；所述复位晶体管、放大晶体管与控制晶体管三者中的至少两个包括不同的有源层，并且所述有源层分别位于两个不同的所述缓冲层上。
  8. 根据权利要求7所述的感光电路结构，其中，所述至少两个缓冲层包括第一缓冲层与第二缓冲层，所述复位晶体管设置于所述第一缓冲层上；
    所述第二缓冲层位于所述第一缓冲层背离所述复位晶体管的一侧，所述控制晶体管和所述放大晶体管中的至少一者设置于所述第二缓冲层上；
    所述复位晶体管和所述放大晶体管在所述第二缓冲层上的正投影之间具有间距；或，所述复位晶体管和所述控制晶体管在所述第二缓冲层上的正投影之间具有间距。
  9. 根据权利要求8所述的感光电路结构，其中，所述复位晶体管包括第一源极、第一漏极、第一栅极和设置在所述第一缓冲层上的第一有源层，所述第一源极和所述第一漏极均与所述第一有源层电连接，所述第一源极和所述第一漏极中的一者为所述复位晶体管的输入端，所述第一源极和所述第一漏极中的另一者为所述复位晶体管的输出端，所述光电二极管的负极与所述第一源极和所述第一漏极中的另一者电连接，所述第一栅极和所述第一有源 层之间设置有第一栅极绝缘层；
    所述放大晶体管和所述控制晶体管中的至少一者包括第二源极、第二漏极、第二栅极和设置在所述第二缓冲层上的第二有源层，所述第二源极和所述第二漏极均与所述第二有源层电连接，所述第二源极和所述第二漏极中的一者为所述放大晶体管和所述控制晶体管中至少一者的输入端，所述第二源极和所述第二漏极中的另一者为所述放大晶体管和所述控制晶体管中至少一者的输出端，所述第二栅极和所述第二有源层之间设置有第二栅极绝缘层；
    所述第一有源层和所述第一栅极远离所述第一缓冲层的一侧设置有层间介质层，所述层间介质层远离所述第二缓冲层的一侧还设置有第一钝化层。
  10. 根据权利要求9所述的感光电路结构，其中，所述光电二极管设置在所述层间介质层的远离所述第一缓冲层的一侧，所述光电二极管远离所述第一缓冲层的一侧设置有导光层；
    所述第一钝化层的远离所述第一缓冲层的一侧依次设置有平坦化层与第二钝化层，所述第二钝化层覆盖所述导光层的远离所述第一缓冲层的一侧。
  11. 根据权利要求9所述的感光电路结构，其中，所述光电二极管的负极直接与所述第一源极和所述第一漏极中的一个电极抵接。
  12. 根据权利要求1-5任一所述的感光电路结构，其中，所述复位晶体管的漏电流小于所述控制晶体管的漏电流。
  13. 根据权利要求1-5任一所述的感光电路结构，其中，所述放大晶体管的载流子迁移率大于所述控制晶体管的载流子迁移率；或者，所述放大晶体管的载流子迁移率小于所述控制晶体管的载流子迁移率。
  14. 根据权利要求3或4所述的感光电路结构，其中，所述运算放大单元包括运算放大器、电容器、可调电容器以及相关双取样电路，所述电容器电连接在所述控制单元的输出端与所述运算放大器的反相输入端之间，所述运算放大器的正向输入端与参考输入端电连接，所述运算放大器的输出端与 所述相关双取样电路电连接，所述可调电容器电连接在所述运算放大器的反相输入端和所述运算放大器的输出端之间。
  15. 根据权利要求7所述的感光电路结构，其中，所述至少两个缓冲层包括三个缓冲层，所述三个缓冲层沿所述缓冲层的厚度方向层叠设置，所述复位晶体管、所述控制晶体管和所述放大晶体管分别位于不同的所述缓冲层上。
  16. 根据权利要求9所述的感光电路结构，其中，所述层间介质层上设置有第一沟槽和第二沟槽，所述第一沟槽和所述第二沟槽均沿所述缓冲层的厚度方向贯穿所述层间介质层，所述第一源极和所述第一漏极中的一者通过所述第一沟槽与所述第一有源层电连接，所述第一源极和所述第一漏极中的另一者通过所述第二沟槽与所述第一有源层电连接。
  17. 根据权利要求16所述的感光电路结构，其中，所述第一沟槽和所述第二沟槽沿所述缓冲层的延伸方向间隔设置。
  18. 根据权利要求9所述的感光电路结构，其中，所述控制晶体管和所述放大晶体管中的至少一者中包括第三沟槽和第四沟槽，所述第三沟槽和所述第四沟槽均沿所述缓冲层的厚度方向贯穿所述第一钝化层、所述层间介质层、所述第一缓冲层和所述第二栅极绝缘层，所述第二源极和所述第二漏极中的一者通过所述第三沟槽与所述第二有源层电连接，所述第二源极和所述第二漏极中的另一者通过所述第四沟槽与所述第二有源层电连接。
  19. 根据权利要求18所述的感光电路结构，其中，所述第三沟槽和所述第四沟槽沿所述缓冲层的延伸方向间隔设置。
  20. 一种光学器件，包括衬底和多个如权利要求1-19中任一项所述的感光电路结构，所述多个感光电路结构呈阵列排布在所述衬底上。
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Publication number Priority date Publication date Assignee Title
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005238A (en) * 1998-04-28 1999-12-21 Xerox Corporation Hybrid sensor pixel architecture with linearization circuit
CN101459757A (zh) * 2008-12-31 2009-06-17 昆山锐芯微电子有限公司 Cmos图像传感器
CN207217538U (zh) * 2017-10-18 2018-04-10 展谱光电科技（上海）有限公司 图像探测器
US20200006412A1 (en) * 2018-06-28 2020-01-02 Applied Materials, Inc. Methods and apparatus for image sensor semiconductors
CN110690227A (zh) * 2019-09-05 2020-01-14 武汉华星光电技术有限公司 阵列基板及其制作方法、显示装置
CN113013189A (zh) * 2021-04-02 2021-06-22 京东方科技集团股份有限公司 一种有源像素图像传感器及显示装置
CN113014837A (zh) * 2021-02-20 2021-06-22 北京大学深圳研究生院 一种光电式的传感像素电路
CN114363542A (zh) * 2021-12-24 2022-04-15 合肥维信诺科技有限公司 感光电路结构和光学器件

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103680409B (zh) * 2013-12-23 2016-04-20 中国科学院上海高等研究院 有源有机发光二极管驱动系统及驱动方法
JP6171997B2 (ja) * 2014-03-14 2017-08-02 ソニー株式会社 固体撮像素子およびその駆動方法、並びに電子機器
CN105044955B (zh) * 2015-09-02 2018-09-11 京东方科技集团股份有限公司 光电传感器及其驱动方法、阵列基板和显示装置
CN109215569B (zh) * 2017-07-04 2020-12-25 京东方科技集团股份有限公司 一种像素电路、驱动方法及显示装置
CN108470742B (zh) * 2018-03-22 2020-10-02 思特威(上海)电子科技有限公司 Hdr图像传感器像素结构及成像系统
WO2020082390A1 (en) * 2018-10-27 2020-04-30 Huawei Technologies Co., Ltd. Sensor and display device
CN112071277A (zh) * 2020-09-03 2020-12-11 深圳市华星光电半导体显示技术有限公司 一种驱动电路及其驱动方法
CN113225499B (zh) * 2021-05-10 2022-08-30 北京京东方传感技术有限公司 有源像素传感器电路及驱动方法、显示装置和平板探测器

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005238A (en) * 1998-04-28 1999-12-21 Xerox Corporation Hybrid sensor pixel architecture with linearization circuit
CN101459757A (zh) * 2008-12-31 2009-06-17 昆山锐芯微电子有限公司 Cmos图像传感器
CN207217538U (zh) * 2017-10-18 2018-04-10 展谱光电科技（上海）有限公司 图像探测器
US20200006412A1 (en) * 2018-06-28 2020-01-02 Applied Materials, Inc. Methods and apparatus for image sensor semiconductors
CN110690227A (zh) * 2019-09-05 2020-01-14 武汉华星光电技术有限公司 阵列基板及其制作方法、显示装置
CN113014837A (zh) * 2021-02-20 2021-06-22 北京大学深圳研究生院 一种光电式的传感像素电路
CN113013189A (zh) * 2021-04-02 2021-06-22 京东方科技集团股份有限公司 一种有源像素图像传感器及显示装置
CN114363542A (zh) * 2021-12-24 2022-04-15 合肥维信诺科技有限公司 感光电路结构和光学器件

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