WO2024093221A1 - 多屏显示的低功耗控制方法、显示设备和电子价签系统 - Google Patents

多屏显示的低功耗控制方法、显示设备和电子价签系统 Download PDF

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Publication number
WO2024093221A1
WO2024093221A1 PCT/CN2023/097347 CN2023097347W WO2024093221A1 WO 2024093221 A1 WO2024093221 A1 WO 2024093221A1 CN 2023097347 W CN2023097347 W CN 2023097347W WO 2024093221 A1 WO2024093221 A1 WO 2024093221A1
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Prior art keywords
module
screen
image data
mipi
display
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PCT/CN2023/097347
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English (en)
French (fr)
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申明
侯世国
魏思兵
赵亚文
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汉朔科技股份有限公司
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Publication of WO2024093221A1 publication Critical patent/WO2024093221A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F3/00—Labels, tag tickets, or similar identification or indication means; Seals; Postage or like stamps
    • G09F3/08—Fastening or securing by means not forming part of the material of the label itself
    • G09F3/18—Casings, frames or enclosures for labels

Definitions

  • the present invention relates to the field of smart supermarket technology, and in particular to a low-power consumption control method for multi-screen display, a display device and an electronic price tag system.
  • Dynamic LCD (Liquid Crystal Display) price tags are an important part of traditional retailers' new retail digitalization. Each medium and large store usually needs to deploy hundreds of dynamic LCD price tags in the new retail digitalization. In order to maintain the normal display of dynamic LCD price tags, the control system of dynamic LCD price tags is always in working mode, which consumes a lot of electricity and increases the digital operation costs of retailers.
  • the low-power consumption control method, display device and electronic price tag system for multi-screen display provided by the present invention solve the problem of high power consumption in the control method of LCD price tags in the prior art.
  • the present invention provides a low-power control method for multi-screen display, which is applied to a display device, wherein the display device includes a main chip, an FPGA, a memory and at least two display screens, wherein the FPGA includes a MIPI receiving module, a data cutting module, a storage control module and a MIPI sending module, and the method includes: when the main chip obtains a sleep instruction, the main chip sends a sleep control command to the FPGA before sleep, so that the FPGA controls the MIPI receiving module and the data cutting module to enter a low-power state according to the sleep control command; the storage control module obtains multiple image data currently stored from the memory according to a synchronization signal, and sends the multiple image data to the corresponding display screens through the MIPI sending module for automatic screen refresh.
  • the method further includes: the main chip obtains matching screen parameters and screen drivers according to the screen IDs of the at least two display screens; when the serial port control module When receiving the initialization control command sent by the main chip, the serial port control module controls the MIPI receiving module and the data cutting module to enter low power consumption, so that the FPGA establishes transparent transmission channels between the main chip and the at least two display screens respectively; the main chip sends the screen parameters and the screen driver to the corresponding display screen through the corresponding transparent transmission channel, so that the display screen is initialized according to the screen parameters and the screen driver.
  • the method also includes: when the serial port control module receives a data transmission control command sent by the main chip, the serial port control module controls the waking up of the MIPI receiving module and the data cutting module, so that the MIPI receiving module switches to high-speed mode to receive the merged image data sent by the main chip; wherein the merged image data includes image data, video data, or combined data of image and video embedded in each other; the merged image data received by the data cutting module is segmented, and the segmented data is sent to the memory for storage through the storage control module to obtain multiple image data; the storage control module sends the multiple image data to the corresponding display screens through the MIPI sending module for display.
  • the FPGA also includes a first cache module and a pixel counting module
  • the merged image data received by the data cutting module is segmented, and the segmented data is sent to the memory for storage through the storage control module to obtain multiple image data, including: the MIPI receiving module stores each row of pixels of the merged image data in the first cache module in sequence; the data cutting module obtains the current row of pixels from the first cache module; the pixel counting module counts the current row of pixels, and when the pixel counting module obtains the data segmentation point, the data cutting module cuts the current row of pixels; after the data cutting module sends the cut row of pixels to the memory through the storage control module for storage, it obtains the next row of pixels from the first cache module for segmentation.
  • the method when the FPGA also includes a second cache module, while the data cutting module sends the cut row pixels to the memory through the storage control module for storage, the method also includes: the cut row pixels are sent to the second cache module through the storage control module, so that the MIPI sending module obtains the cut row pixels from the second cache module and sends them to the corresponding display screen for display.
  • the storage control module obtains multiple image data currently stored from the memory according to the synchronization signal, and sends the multiple image data to the corresponding display screens through the MIPI sending module for automatic screen refresh, including: when the clock synchronization module outputs a synchronization signal, the storage control module stores each image data obtained from the memory in the second cache module by staggering one pixel, so that the MIPI sending module obtains the staggered image data from the second cache module and sends it to the corresponding display screen for display.
  • the present invention provides a display device, the display device comprising: a main chip, an FPGA, a memory and at least two display screens, wherein the FPGA includes a MIPI receiving module, a data cutting module, a storage control module and a MIPI sending module; the main chip is used to send a sleep control command to the FPGA when obtaining a sleep instruction and before sleep, so that the FPGA controls the MIPI receiving module and the data cutting module to enter a low power consumption state according to the sleep control command; the storage control module is used to obtain multiple image data currently stored in the memory according to a synchronization signal, and send the multiple image data to the corresponding display screens through the MIPI sending module for automatic screen refresh.
  • the FPGA includes a MIPI receiving module, a data cutting module, a storage control module and a MIPI sending module
  • the main chip is used to send a sleep control command to the FPGA when obtaining a sleep instruction and before sleep, so that the FPGA controls the MIPI receiving module and the data cutting module to enter a low power
  • the main chip is also used to obtain matching screen parameters and screen drivers according to the screen IDs of the at least two display screens; when the serial port control module receives an initialization control command sent by the main chip, the serial port control module is used to control the MIPI receiving module and the data cutting module to enter low power consumption, so that the FPGA establishes transparent transmission channels between the main chip and the at least two display screens respectively; the main chip is also used to send the screen parameters and the screen driver to the corresponding display screen through the corresponding transparent transmission channel, so that the display screen is initialized according to the screen parameters and the screen driver.
  • the serial port control module when the serial port control module receives a data transmission control command sent by the main chip, the serial port control module is also used to control the awakening of the MIPI receiving module and the data cutting module, so that the MIPI receiving module switches to high-speed mode to receive the merged image data sent by the main chip; the data cutting module is used to segment the received merged image data, and send the segmented data to the memory for storage through the storage control module to obtain multiple image data; the storage control module is used to send the multiple image data to the corresponding display screens for display through the MIPI sending module.
  • the present invention provides an electronic price label system, which includes the display device.
  • the present invention has the following beneficial effects:
  • the present invention obtains multiple image data currently stored in the memory according to the synchronization signal through the storage control module, and sends each image data to the corresponding display screen through the MIPI sending module of the FPGA, so as to meet the timing refresh requirement of the display screen; therefore, without modifying the displayed image data, the main chip, the MIPI receiving module of the FPGA and the data cutting module can enter a low-power sleep state, which not only reduces the overall power consumption of the display device, but also does not affect the normal display of the display screen, thereby reducing the operating costs of the supermarket.
  • FIG1 is a schematic flow chart of a low power consumption control method for multi-screen display provided by an embodiment of the present invention
  • FIG2 is a schematic diagram showing the structure of a display device provided by an embodiment of the present invention.
  • FIG3 is a schematic diagram showing the structure of an FPGA provided by an embodiment of the present invention.
  • FIG4 is a schematic diagram showing a specific process of screen initialization and image data transmission provided by an embodiment of the present invention.
  • FIG5 is a schematic diagram showing a specific process of dual-screen different display and screen static display provided by an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of image partition storage provided by an embodiment of the present invention.
  • the present invention provides a low power consumption control method for multi-screen display, which specifically includes the following embodiments:
  • FIG1 is a flow chart of a low power consumption control method for multi-screen display provided by an embodiment of the present invention. As shown in FIG1 , the method specifically includes the following steps:
  • Step S101 when the main chip obtains the sleep instruction, the main chip sends a sleep control command to the FPGA before sleep, so that the FPGA controls the MIPI receiving module and the data cutting module to enter a low power consumption state according to the sleep control command.
  • the low-power control method for multi-screen display is applied to a display device.
  • the display device includes a main chip, an FPGA, a memory and at least two display screens, wherein the FPGA includes a MIPI receiving module, a data cutting module, a storage control module and a MIPI sending module; the display screen in this embodiment uses an LCD MIPI interface screen, and the resolution of each screen is 800x1280.
  • the FPGA realizes one MIPI input and two MIPI outputs.
  • the main chip in this embodiment can be a SOC (System on Chip), in which only one LCD controller and one MIPI interface are provided, by adding an FPGA module, one interface input and two interface outputs can be realized, and the FPGA cuts the input data into two copies, thereby realizing the dual-screen different display function, that is, when playing two different videos, each screen displays a video, and when displaying two different pictures, each screen displays a picture, and the picture can also be superimposed with the video and displayed on the screen; therefore, this embodiment realizes the control of multiple display screens through one main chip, which not only reduces the cost of LCD price tags, but also reduces power consumption compared with the prior art in which one main chip controls one display screen.
  • SOC System on Chip
  • the main chip and FPGA need to provide corresponding image data according to the refresh frequency of the LCD screen.
  • the main chip, FPGA and LCD screen will always work, increasing the power consumption of the entire display device.
  • the display content of the LCD screen is updated only when the product name and price are modified. Therefore, the picture content displayed on the LCD screen remains basically unchanged or changes infrequently.
  • the main chip of the present invention enters a sleep mode when the picture content of the LCD screen is not modified, thereby reducing the power consumption of the main chip.
  • the main chip can obtain the sleep instruction in a manner that the sleep instruction is sent by a control chip other than the main chip, or the main chip can automatically generate a sleep instruction when it determines that there is no picture data, configuration parameters or control instructions to be sent. Therefore, when the sleep instruction is obtained, the LCD price tag does not modify the displayed image data.
  • the main chip when the main chip obtains the sleep instruction, the main chip sends a sleep control instruction to the FPGA, causing the MIPI receiving module and data cutting module of the FPGA to enter a low power consumption state; at this time, the main chip, the MIPI receiving module and the data cutting module of the FPGA all enter a low power consumption state, thereby reducing the power consumption of the display device.
  • Step S102 the storage control module obtains the currently stored multiple image data from the memory according to the synchronization signal, and sends the multiple image data to the corresponding display screens through the MIPI sending module for automatic screen refresh.
  • this embodiment obtains the currently stored multiple image data from the memory through the storage control module, and sends each image data to the corresponding LCD through the FPGA's MIPI sending module for screen refresh.
  • this embodiment has the following beneficial effects:
  • the storage control module obtains the multiple image data currently stored from the memory according to the synchronization signal, and sends each image data to the corresponding display screen through the MIPI sending module of the FPGA to meet the timed refresh requirement of the display screen; therefore, without modifying the displayed image data, the main chip, the MIPI receiving module of the FPGA and the data cutting module can enter a low-power sleep state, which not only reduces the overall power consumption of the display device, but also does not affect the normal display of the display screen, thereby reducing the operating costs of the supermarket.
  • the FPGA in this embodiment also includes a serial port control module for receiving control commands sent by the main chip, a first cache module, a second cache module, a pixel counting module for pixel counting, a clock synchronization module for sending synchronization signals, and a configuration module for configuring parameters.
  • the method further includes: the main chip obtains matching screen parameters and screen drivers according to the screen IDs of at least two display screens; when the serial port control module receives an initialization control command sent by the main chip, the serial port control module controls the MIPI receiving module and the data cutting module to enter low power consumption, so that the FPGA establishes transparent transmission channels between the main chip and at least two display screens respectively; the main chip sends the screen parameters and screen drivers to the corresponding display screen through the corresponding transparent transmission channels, so that the display screen can be configured to receive the screen parameters and screen drivers according to the screen parameters and screen drivers. Initialize the screen driver.
  • the method also includes: when the serial port control module receives a data transmission control command sent by the main chip, the serial port control module controls the awakening of the MIPI receiving module and the data cutting module, so that the MIPI receiving module switches to high-speed mode to receive the merged image data sent by the main chip; wherein the merged image data includes image data, video data, or combined data of image and video embedded in each other; the merged image data received by the data cutting module is segmented, and the segmented data is sent to the memory for storage through the storage control module to obtain multiple image data; the storage control module sends the multiple image data to the corresponding display screens through the MIPI sending module for display.
  • the main chip reads the screen IDs of at least two display screens from the secure partition of the flash memory, selects a set of LCD screen parameters that match the screens based on the IDs, and loads the corresponding LCD screen drivers, so that the main chip can adaptively configure the screen parameters and achieve seamless switching of screens from different manufacturers.
  • the GPIO_Config port of the main chip outputs a low level to the serial port control module, so that the MIPI receiving module and the data cutting module enter the low power consumption mode;
  • the GPIO_Rotate port of the main chip outputs a low level to the serial port control module, and the serial port control module connects the MIPI line of the main chip and the MIPI line of screen A together, thereby establishing a transparent transmission channel between the main chip and screen A.
  • the main chip sends the configuration parameter information of screen A to screen A to perform the initialization setting of screen A; (3)
  • the GPIO_Config port of the main chip outputs a low level to the serial port control module, and the serial port control module connects the MIPI line of the main chip and the MIPI line of screen A together, thereby establishing a transparent transmission channel between the main chip and screen A.
  • the main chip sends the configuration parameter information of screen A to screen A to perform the initialization setting of screen A; (4)
  • the GPIO_Config port of the main chip outputs a low level to the serial port control module, and the MIPI_Rotate port of the main chip outputs a low level to the serial port control module, and the serial port control module connects the MIPI line of the main chip and the MIPI line of screen A together to establish the transparent transmission channel between the main chip and screen A.
  • the main chip sends the configuration parameter information of screen A to screen A to perform the initialization setting of screen A; (5)
  • the PIO_Rotate port outputs a high level to the serial port control module, and the serial port control module connects the MIPI line of the main chip and the MIPI line of the B screen together, thereby establishing a transparent transmission channel between the main chip and the B screen.
  • the main chip sends the configuration parameter information of the B screen to the B screen to perform the initialization settings of the B screen; (4)
  • the GPIO_Config port of the main chip outputs a high level to the serial port control module, wakes up the MIPI receiving module and the data cutting module, and switches the MIPI receiving module to the high-speed mode to receive the merged image data sent by the main chip, and performs image segmentation on the merged image data, and sends the segmented image to the A screen and the B screen for display.
  • the FPGA when the FPGA also includes a first cache module and a pixel counting module, the merged image data received by the data cutting module is segmented, and the segmented data is sent to the memory for storage through the storage control module to obtain multiple image data, including: the MIPI receiving module stores each row of pixels of the merged image data in the first cache module in sequence; the data cutting module obtains the current row of pixels from the first cache module; the pixel counting module counts the current row of pixels, and when the pixel counting module obtains the data segmentation point, the data cutting module cuts the current row of pixels; the data cutting module sends the cut row of pixels to the memory through the storage control module for storage, and then obtains the next row of pixels from the first cache module for segmentation.
  • the method when the FPGA also includes a second cache module, while the data cutting module sends the cut row pixels to the memory for storage through the storage control module, the method also includes: sending the cut row pixels to the second cache module through the storage control module, so that the MIPI sending module obtains the cut row pixels from the second cache module and sends them to the corresponding display screen for display.
  • the storage control module obtains multiple image data currently stored from the memory according to the synchronization signal, and sends the multiple image data to the corresponding display screens through the MIPI sending module for automatic screen refresh, including: when the clock synchronization module outputs a synchronization signal, the storage control module stores each image data obtained from the memory in the second cache module by staggering one pixel, so that the MIPI sending module obtains the staggered image data from the second cache module and sends it to the corresponding display screen for display.
  • FIG5 The specific process of performing dual-screen display and static screen display in this embodiment is shown in FIG5: (1) As shown in FIG6, in the main chip, FrameBuffer is used as an image of the display memory. After it is mapped to the process address space, the user process can directly perform read and write operations. The content of area A is sent to the A screen by cutting by the FPGA, and the content of area B is sent to the B screen by cutting by the FPGA. The application in the main chip maps FB to the process space and copies the content currently displayed by FB to the FB cache. If there is video or picture content to be input to the A screen, it is written to the FB cache A1 area in RGBA format.
  • the display driver refreshes the frame data (1600x1280) to the MIPI_DSI interface.
  • the FPGA converts it into RGB data, then cuts it line by line, and caches the cut data in the memory.
  • the FPGA memory control module reads the cached screen content data from the memory, refreshes the content of screen A to MIPI_ch0, displays it on screen A, and refreshes the content of screen B to MIPI_ch1, displays it on screen B. This completes the display of different contents on two screens on a single-chip SOC with only one LCDC.
  • the application receives the background sleep command, it sets the main chip SOC to a low-power deep sleep mode, controls the FPGA to enter low power through UART, stops the content cutting and pixel processing modules, and the FPGA works in the self-refresh state.
  • the SYNC signal After the SYNC signal arrives, it reads the cached screen content data, refreshes the content of screen A to MIPI_ch0, displays it on screen A, and refreshes the content of screen B to MIPI_ch1, displays it on screen B.
  • MIPI_ch0 This completes the static display of two screens when the main chip SOC is in low-power mode.
  • this embodiment has the following advantages:
  • the two LCD screens can statically display different picture contents.
  • FPGA is used to implement content segmentation on a single chip with only one LCDC, so that different video and image contents can be displayed on two screens.
  • the main chip can directly set the screen drive parameters through FPGA transparent transmission, realizing seamless switching of screens from different manufacturers.
  • the present invention provides a display device, comprising: a main chip, an FPGA, a memory and at least two display screens, wherein the FPGA comprises a MIPI receiving module, a data cutting module, a storage control module and a MIPI sending module; the main chip is used to send a sleep control command to the FPGA when a sleep instruction is obtained and before sleep, so that the FPGA controls the MIPI receiving module and the data cutting module to enter a low power consumption state according to the sleep control command; the storage control module is used to obtain multiple image data currently stored from the memory according to a synchronization signal, and send the multiple image data to the corresponding display screens through the MIPI sending module for automatic screen refresh.
  • the FPGA comprises a MIPI receiving module, a data cutting module, a storage control module and a MIPI sending module
  • the main chip is used to send a sleep control command to the FPGA when a sleep instruction is obtained and before sleep, so that the FPGA controls the MIPI receiving module and the data cutting module to enter a low power consumption state according
  • the main chip when the FPGA also includes a serial port control module, the main chip is also used to obtain matching screen parameters and screen drivers according to the screen IDs of at least two display screens; when the serial port control module receives an initialization control command sent by the main chip, the serial port control module is used to control the MIPI receiving module and the data cutting module to enter low power consumption, so that the FPGA establishes a transparent transmission channel between the main chip and at least two display screens respectively; the main chip is also used to send the screen parameters and screen drivers to the corresponding display screens through the corresponding transparent transmission channels, so that the display screens are initialized according to the screen parameters and the screen driver.
  • the serial port control module when the serial port control module receives a data transmission control command sent by the main chip, the serial port control module is also used to control the wake-up of the MIPI receiving module and the data cutting module, so that the MIPI receiving module switches to high-speed mode to receive the merged image data sent by the main chip; the data cutting module is used to split the received merged image data, and send the split data to the memory for storage through the storage control module to obtain multiple image data; the storage control module is used to send the multiple image data to the corresponding display screens for display through the MIPI sending module.
  • the present invention provides an electronic price tag system, which includes the display device in the above embodiment.
  • Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
  • SRAM static RAM
  • DRAM dynamic RAM
  • SDRAM synchronous DRAM
  • DDRSDRAM double data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM synchronous link (Synchlink) DRAM
  • SLDRAM synchronous link (Synchlink) DRAM
  • Rambus direct RAM
  • DRAM direct memory bus dynamic RAM
  • RDRAM memory bus dynamic RAM

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Abstract

一种多屏显示的低功耗控制方法、显示设备和电子价签系统，方法包括：当主芯片获取到休眠指令时，主芯片在休眠之前发送休眠控制命令到FPGA，使FPGA根据休眠控制命令控制MIPI接收模块和数据切割模块进入低功耗状态（S101）；存储控制模块根据同步信号从存储器中获取当前存储的多个图像数据，并通过MIPI发送模块将多个图像数据分别发送到相对应的显示屏中进行屏幕自动刷新（S102）。通过在不进行显示图像数据修改的情况下，主芯片、FPGA的MIPI接收模块和数据切割模块可以进入低功耗的休眠状态，不仅可以降低显示设备的整体功耗，还不影响显示屏的正常显示，从而降低了商超的运营成本。

Description

多屏显示的低功耗控制方法、显示设备和电子价签系统
本申请要求2022年11月4日递交的申请号为202211376429.1、发明名称为“多屏显示的低功耗控制方法、显示设备和电子价签系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及智能商超技术领域，具体涉及多屏显示的低功耗控制方法、显示设备和电子价签系统。
背景技术
动态的LCD(Liquid Crystal Display)价签是传统零售商进行新零售数字化重要的一环，每个中大型门店在新零售数字化中需要部署的动态LCD价签通常都是几百个；为了维护动态LCD价签的正常显示，动态LCD价签的控制系统始终处于工作模式，从而需要消耗很多电能，导致零售商的数字化运行成本的增加。
可见，现有技术中LCD价签的控制方法存在功耗高的问题，增加了商超的运营成本。
发明内容
针对现有技术中所存在的不足，本发明提供的多屏显示的低功耗控制方法、显示设备和电子价签系统，解决了现有技术中LCD价签的控制方法存在功耗高的问题。
第一方面，本发明提供一种多屏显示的低功耗控制方法，应用于显示设备，所述显示设备包括主芯片、FPGA、存储器和至少两个显示屏，其中所述FPGA包括MIPI接收模块、数据切割模块、存储控制模块和MIPI发送模块，所述方法包括：当所述主芯片获取到休眠指令时，所述主芯片在休眠之前发送休眠控制命令到所述FPGA，使所述FPGA根据所述休眠控制命令控制所述MIPI接收模块和所述数据切割模块进入低功耗状态；所述存储控制模块根据同步信号从所述存储器中获取当前存储的多个图像数据，并通过MIPI发送模块将所述多个图像数据分别发送到相对应的显示屏中进行屏幕自动刷新。
可选地，当所述FPGA还包括串口控制模块时，所述方法还包括：所述主芯片根据所述至少两个显示屏的屏幕ID，获取相匹配的屏幕参数和屏幕驱动；当所述串口控制模块 接收到所述主芯片发送初始化控制命令时，所述串口控制模块控制所述MIPI接收模块和数据切割模块进入低功耗，使所述FPGA建立主芯片分别与所述至少两个显示屏的透传通道；所述主芯片将所述屏幕参数和所述屏幕驱动通过相对应的透传通道发送到相对应的显示屏中，使所述显示屏根据所述屏幕参数和所述屏幕驱动进行初始化设置。
可选地，所述方法还包括：当所述串口控制模块接收到所述主芯片发送数据传输控制命令时，所述串口控制模块控制唤醒所述MIPI接收模块和所述数据切割模块，使所述MIPI接收模块切换至高速模式接收所述主芯片发送的合并图像数据；其中，所述合并图像数据包括图像数据、视频数据或图像与视频相互嵌入的组合数据；所述数据切割模块接收到的合并图像数据进行分割，并通过所述存储控制模块将分割后的数据发送到存储器进行存储，得到多个图像数据；所述存储控制模块通过MIPI发送模块将所述多个图像数据分别发送到相对应的显示屏进行显示。
可选地，当所述FPGA还包括第一缓存模块和像素计数模块，所述数据切割模块接收到的合并图像数据进行分割，并通过所述存储控制模块将分割后的数据发送到存储器进行存储，得到多个图像数据，包括：所述MIPI接收模块将合并图像数据的每行像素依次存储在所述第一缓存模块中；所述数据切割模块从所述第一缓存模块中获取当前行像素；所述像素计数模块对所述当前行像素进行计数，当所述像素计数模块获取到数据分割点时使所述数据切割模块进行当前行像素的切割；所述数据切割模块将切割后的行像素通过所述存储控制模块发送到所述存储器进行存储后，从所述第一缓存模块中获取下一行像素进行分割。
可选地，当所述FPGA还包括第二缓存模块时，在所述数据切割模块将切割后的行像素通过所述存储控制模块发送到所述存储器进行存储的同时，所述方法还包括：所述切割后的行像素通过所述存储控制模块发送到所述第二缓存模块，使所述MIPI发送模块从所述第二缓存模块中获取切割后的行像素，并发送到相对应的显示屏进行显示。
可选地，当所述FPGA还包括时钟同步模块时，所述存储控制模块根据同步信号从所述存储器中获取当前存储的多个图像数据，并通过MIPI发送模块将所述多个图像数据分别发送到相对应的显示屏中进行屏幕自动刷新，包括：当所述时钟同步模块输出同步信号时，所述存储控制模块通过错位一个像素的方法将从所述存储器中获取的每个图像数据存储在所述第二缓存模块中，使所述MIPI发送模块从所述第二缓存模块中获取错位后的图像数据发送到相对应的显示屏进行显示。
第二方面，本发明提供一种显示设备，所述显示设备包括：主芯片、FPGA、存储器 和至少两个显示屏，其中所述FPGA包括MIPI接收模块、数据切割模块、存储控制模块和MIPI发送模块；所述主芯片用于获取到休眠指令时且在休眠之前，发送休眠控制命令到所述FPGA，使所述FPGA根据所述休眠控制命令控制所述MIPI接收模块和所述数据切割模块进入低功耗状态；所述存储控制模块用于根据同步信号从所述存储器中获取当前存储的多个图像数据，并通过MIPI发送模块将所述多个图像数据分别发送到相对应的显示屏中进行屏幕自动刷新。
可选地，当所述FPGA还包括串口控制模块时，所述主芯片还用于根据所述至少两个显示屏的屏幕ID，获取相匹配的屏幕参数和屏幕驱动；当所述串口控制模块接收到所述主芯片发送初始化控制命令时，所述串口控制模块用于控制所述MIPI接收模块和数据切割模块进入低功耗，使所述FPGA建立主芯片分别与所述至少两个显示屏的透传通道；所述主芯片还用于将所述屏幕参数和所述屏幕驱动通过相对应的透传通道发送到相对应的显示屏中，使所述显示屏根据所述屏幕参数和所述屏幕驱动进行初始化设置。
可选地，当所述串口控制模块接收到所述主芯片发送数据传输控制命令时，所述串口控制模块还用于控制唤醒所述MIPI接收模块和所述数据切割模块，使所述MIPI接收模块切换至高速模式接收所述主芯片发送的合并图像数据；所述数据切割模块用于接收到的合并图像数据进行分割，并通过所述存储控制模块将分割后的数据发送到存储器进行存储，得到多个图像数据；所述存储控制模块用于通过MIPI发送模块将所述多个图像数据分别发送到相对应的显示屏进行显示。
第三方面，本发明提供一种电子价签系统，所述价签系统包括所述的显示设备。
相比于现有技术，本发明具有如下有益效果：
本发明通过存储控制模块根据同步信号从存储器中获取当前存储的多个图像数据，并将每个图像数据通过FPGA的MIPI发送模块分别发送到相对应的显示屏中，来满足显示屏的定时刷新需求；因此，在不进行显示图像数据修改的情况下，所述主芯片、所述FPGA的MIPI接收模块和所述数据切割模块可以进入低功耗的休眠状态，这样不仅可以降低显示设备的整体功耗，还不影响显示屏的正常显示，从而降低了商超的运营成本。
附图说明
图1所示为本发明实施例提供的一种多屏显示的低功耗控制方法的流程示意图；
图2所示为本发明实施例提供的一种显示设备的结构示意图；
图3所示为本发明实施例提供的一种FPGA的结构示意图；
图4所示为本发明实施例提供的一种屏幕初始化和图像数据发送的具体流程示意图；
图5所示为本发明实施例提供的一种双屏异显和屏幕静态显示的具体流程示意图；
图6所示为本发明实施例提供的一种图像分区存储的示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本申请保护的范围。
第一方面，本发明提供一种多屏显示的低功耗控制方法，具体包括以下实施例：
图1所示为本发明实施例提供的一种多屏显示的低功耗控制方法的流程示意图，如图1所示，具体包括以下步骤：
步骤S101，当主芯片获取到休眠指令时，主芯片在休眠之前发送休眠控制命令到FPGA，使FPGA根据休眠控制命令控制MIPI接收模块和数据切割模块进入低功耗状态。
需要说明的是，本实施例提供的多屏显示的低功耗控制方法应用于显示设备，如图2所示，显示设备包括主芯片、FPGA、存储器和至少两个显示屏，其中FPGA包括MIPI接收模块、数据切割模块、存储控制模块和MIPI发送模块；本实施例中的显示屏采用LCD MIPI接口的屏幕，每块屏幕的分辨率是800x1280，FPGA实现了一路MIPI进入，两路MIPI输出。
本实施例中的主芯片可以是SOC(System on Chip)，其中在仅提供一个LCD控制器和一个MIPI接口的情况下，通过增加一个FPGA模块，即可实现一路接口进入，两路接口输出，FPGA切割输入的数据为两份，从而实现双屏异显功能,也就是说，当播放两个不同的视频，每个屏幕显示一个视频，当显示不同的两个图片时，每个屏幕显示一幅图片，图片也可以叠加视频显示在屏幕上；因此，本实施通过一个主芯片实现多面显示屏的控制，与现有技术中一个主芯片控制一个显示屏相比，不仅降低了LCD价签的成本，还降低了功耗。
由于LCD屏幕具有固定刷新特性，需要主芯片和FPGA根据LCD屏幕的刷新频率提供相应图像数据，那么主芯片、FPGA和LCD屏就一直工作，增大了整个显示设备的耗电量； 但是在实际电子价签系统的应用过程中，在修改商品名称、价格时才会更新LCD屏幕的显示内容，因此LCD屏幕显示的图片内容基本不变或者变化频率低；本发明为了降低整个显示设备的功耗，在不进行LCD屏幕图片内容修改的情况下，主芯片进入休眠模式，从而降低了主芯片的功耗；其中，主芯片获取休眠指令的方式可以是除主芯片以外的控制芯片发送的休眠指令，也可以是主芯片判断出当前没有图片数据、配置参数或控制指令发送时自动生成休眠指令；因此获取到休眠指令时，也就是LCD价签不进行显示图像数据修改时。
在本实施例中，当主芯片获取到休眠指令时，主芯片发送休眠控制指令到FPGA中，使FPGA的MIPI接收模块和数据切割模块进入低功耗状态；在此时，主芯片、FPGA的MIPI接收模块和数据切割模块都进入低功耗状态，从而降低了显示设备的功耗。
步骤S102，存储控制模块根据同步信号从存储器中获取当前存储的多个图像数据，并通过MIPI发送模块将多个图像数据分别发送到相对应的显示屏中进行屏幕自动刷新。
需要说明的是，由于主芯片、FPGA的MIPI接收模块和数据切割模块都进入低功耗状态，为了满足LCD屏幕的定时刷新特征，本实施例通过存储控制模块从存储器中获取当前存储的多个图像数据，并将每个图像数据通过FPGA的MIPI发送模块分别发送到相对应的LCD中进行屏幕刷新。
相比于现有技术，本实施例具有如下有益效果：
本实施例通过存储控制模块根据同步信号从存储器中获取当前存储的多个图像数据，并将每个图像数据通过FPGA的MIPI发送模块分别发送到相对应的显示屏中，来满足显示屏的定时刷新需求；因此，在不进行显示图像数据修改的情况下，主芯片、FPGA的MIPI接收模块和数据切割模块可以进入低功耗的休眠状态，这样不仅可以降低显示设备的整体功耗，还不影响显示屏的正常显示，从而降低了商超的运营成本。
如图3所示，在本实施例中的FPGA还包括用于接收主芯片发送的控制命令的串口控制模块、第一缓存模块、第二缓存模块、用于像素计数的像素计数模块、发送同步信号的时钟同步模块以及用于配置参数的配置模块。
在本发明的另一个实施例中，当FPGA还包括串口控制模块时，方法还包括：主芯片根据至少两个显示屏的屏幕ID，获取相匹配的屏幕参数和屏幕驱动；当串口控制模块接收到主芯片发送初始化控制命令时，串口控制模块控制MIPI接收模块和数据切割模块进入低功耗，使FPGA建立主芯片分别与至少两个显示屏的透传通道；主芯片将屏幕参数和屏幕驱动通过相对应的透传通道发送到相对应的显示屏中，使显示屏根据屏幕参数和屏 幕驱动进行初始化设置。
在本发明的另一个实施例中，方法还包括：当串口控制模块接收到主芯片发送数据传输控制命令时，串口控制模块控制唤醒MIPI接收模块和数据切割模块，使MIPI接收模块切换至高速模式接收主芯片发送的合并图像数据；其中，合并图像数据包括图像数据、视频数据或图像与视频相互嵌入的组合数据；数据切割模块接收到的合并图像数据进行分割，并通过存储控制模块将分割后的数据发送到存储器进行存储，得到多个图像数据；存储控制模块通过MIPI发送模块将多个图像数据分别发送到相对应的显示屏进行显示。
需要说明的是，主芯片从闪存的安全分区中读取至少两个显示屏的屏幕ID，依据ID选取一组与屏幕相匹配的LCD屏幕参数和加载相应的LCD屏幕驱动，从而使主芯片可以自适应配置屏幕参数，实现不同厂家屏幕的无缝切换。
以显示屏包括A屏和B屏为例，在本实施例中进行屏幕初始化和图像数据发送的具体流程如图4所示：(1)主芯片的GPIO_Config端口输出低电平到串口控制模块，使MIPI接收模块和数据切割模块进入低功耗模式；(2)主芯片的GPIO_Rotate端口输出低电平到串口控制模块,串口控制模块将主芯片的MIPI线和A屏幕的MIPI线连接在一起，从而建立主芯片和A屏幕的透传通道，主芯片发送A屏幕的配置参数信息到A屏幕中，进行A屏幕的初始化设置；(3)主芯片的GPIO_Rotate端口输出高电平到串口控制模块，串口控制模块将主芯片的MIPI线和B屏幕的MIPI线连接在一起，从而建立主芯片和B屏幕的透传通道，主芯片发送B屏幕的配置参数信息到B屏幕中，进行B屏幕的初始化设置；(4)主芯片的GPIO_Config端口输出高电平到串口控制模块，唤醒MIPI接收模块和数据切割模块，使MIPI接收模块切换至高速模式接收主芯片发送的合并图像数据，并对合并图像数据进行图像分割，将分割后的图像分别发送到A屏和B屏进行显示。
在本发明的另一个实施例中，当FPGA还包括第一缓存模块和像素计数模块，数据切割模块接收到的合并图像数据进行分割，并通过存储控制模块将分割后的数据发送到存储器进行存储，得到多个图像数据，包括：MIPI接收模块将合并图像数据的每行像素依次存储在第一缓存模块中；数据切割模块从第一缓存模块中获取当前行像素；像素计数模块对当前行像素进行计数，当像素计数模块获取到数据分割点时使数据切割模块进行当前行像素的切割；数据切割模块将切割后的行像素通过存储控制模块发送到存储器进行存储后，从第一缓存模块中获取下一行像素进行分割。
在本实施例中，当FPGA还包括第二缓存模块时，在数据切割模块将切割后的行像素通过存储控制模块发送到存储器进行存储的同时，方法还包括：切割后的行像素通过存储控制模块发送到第二缓存模块，使MIPI发送模块从第二缓存模块中获取切割后的行像素，并发送到相对应的显示屏进行显示。
在本实施例中，当FPGA还包括时钟同步模块时，存储控制模块根据同步信号从存储器中获取当前存储的多个图像数据，并通过MIPI发送模块将多个图像数据分别发送到相对应的显示屏中进行屏幕自动刷新，包括：当时钟同步模块输出同步信号时，存储控制模块通过错位一个像素的方法将从存储器中获取的每个图像数据存储在第二缓存模块中，使MIPI发送模块从第二缓存模块中获取错位后的图像数据发送到相对应的显示屏进行显示。
在本实施例中进行双屏异显和屏幕静态显示的具体流程如图5所示：(1)如图6所示，在主芯片中将FrameBuffer作为显示内存的一个映像，将其映射到进程地址空间之后，用户进程就可以直接进行读写操作。A区内容被FPGA通过切割送给A面屏幕，B区内容被FPGA通过切割送给B面屏幕主芯片中的应用程序将FB映射到进程空间，将FB当前显示的内容拷贝到FB缓存。如果有要输入到A屏幕的视频或图片内容按照RGBA格式写入到FB缓存A1区。如果有要输入到B屏幕的视频或图片内容按照RGBA格式写入到FB缓存B1区，更新FB当前指针指向FB缓存。(2)显示驱动在场同步VSYNC信号到来后，将帧数据(1600x1280)刷新到MIPI_DSI接口。(3)FPGA在MIPI_RX接收到数据后，转换成RGB数据,然后逐行进行切割，将切割后的数据缓存在内存。(4)在SYNC信号到来后，FPGA内存控制模块从内存中读取缓存的屏幕内容数据，将A屏幕内容刷新到MIPI_ch0，在A屏幕显示，将B屏幕内容刷新到MIPI_ch1，在B屏幕显示，这样就完成了在仅有一个LCDC的单芯片SOC显示不同的内容到两个屏幕上面。(5)应用收到后台休眠指令后，将主芯片SOC设置为低功耗深度睡眠模式，通过UART控制FPGA进入低功耗，使内容切割和像素处理模块停止工作，FPGA工作在自刷新状态，SYNC信号到来后，读取缓存的屏幕内容数据，将A屏幕内容刷新到MIPI_ch0，在A屏幕显示，将B屏幕内容刷新到MIPI_ch1，在B屏幕显示，这样就完成了在主芯片SOC处于低功耗模式下的两个屏幕静态显示。(6)FPGA工作在自刷新状态，SYNC信号到来时，自动将上一次SYNC时传输的每个屏幕的静态图片错位一个像素，保证这次刷新的图片内容是新的，避免LCD屏幕刷新相同的静态图片内容时出现残影。
因此，本实施例具有以下优点：
(1)在主芯片和FPGA工作在低功耗模式下，两个LCD屏幕可以静态显示不同的图片内容。
(2)FPGA工作在自刷新状态时，每次场同步信号到来时，通过错位相同静态图片的一个像素，动态显示静态图片内容到LCD屏幕，避免LCD屏幕刷新相同的静态图片内容时出现残影。
(3)通过软硬件的方式，在仅有一个LCDC的单芯片上利用FPGA实现内容切割，从而实现两个屏幕显示不同的视频和图片内容。
(4)主芯片可以通过FPGA透传直接设置屏幕驱动参数，实现不同厂家的屏幕无缝切换。
第二方面，本发明提供一种显示设备，显示设备包括：主芯片、FPGA、存储器和至少两个显示屏，其中FPGA包括MIPI接收模块、数据切割模块、存储控制模块和MIPI发送模块；主芯片用于获取到休眠指令时且在休眠之前，发送休眠控制命令到FPGA，使FPGA根据休眠控制命令控制MIPI接收模块和数据切割模块进入低功耗状态；存储控制模块用于根据同步信号从存储器中获取当前存储的多个图像数据，并通过MIPI发送模块将多个图像数据分别发送到相对应的显示屏中进行屏幕自动刷新。
在本实施例中，当FPGA还包括串口控制模块时，主芯片还用于根据至少两个显示屏的屏幕ID，获取相匹配的屏幕参数和屏幕驱动；当串口控制模块接收到主芯片发送初始化控制命令时，串口控制模块用于控制MIPI接收模块和数据切割模块进入低功耗，使FPGA建立主芯片分别与至少两个显示屏的透传通道；主芯片还用于将屏幕参数和屏幕驱动通过相对应的透传通道发送到相对应的显示屏中，使显示屏根据屏幕参数和屏幕驱动进行初始化设置。
在本实施例中，当串口控制模块接收到主芯片发送数据传输控制命令时，串口控制模块还用于控制唤醒MIPI接收模块和数据切割模块，使MIPI接收模块切换至高速模式接收主芯片发送的合并图像数据；数据切割模块用于接收到的合并图像数据进行分割，并通过存储控制模块将分割后的数据发送到存储器进行存储，得到多个图像数据；存储控制模块用于通过MIPI发送模块将多个图像数据分别发送到相对应的显示屏进行显示。
第三方面，本发明提供一种电子价签系统，价签系统包括上述实施例中的显示设备。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序的指令完成，计算机程序可存储于一非易失性计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，本申请所提供的各实施 例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDRSDRAM)、增强型SDRAM(ESDRAM)、同步链路(Synchlink)DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)等。
需要说明的是，在本文中，诸如“第一”和“第二”等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。

Claims (10)

  1. 一种多屏显示的低功耗控制方法，其特征在于，应用于显示设备，所述显示设备包括主芯片、FPGA、存储器和至少两个显示屏，其中所述FPGA包括MIPI接收模块、数据切割模块、存储控制模块和MIPI发送模块，所述方法包括：
    当所述主芯片获取到休眠指令时，所述主芯片在休眠之前发送休眠控制命令到所述FPGA，使所述FPGA根据所述休眠控制命令控制所述MIPI接收模块和所述数据切割模块进入低功耗状态；
    所述存储控制模块根据同步信号从所述存储器中获取当前存储的多个图像数据，并通过MIPI发送模块将所述多个图像数据分别发送到相对应的显示屏中进行屏幕自动刷新。
  2. 如权利要求1所述的多屏显示的低功耗控制方法，其特征在于，当所述FPGA还包括串口控制模块时，所述方法还包括：
    所述主芯片根据所述至少两个显示屏的屏幕ID，获取相匹配的屏幕参数和屏幕驱动；
    当所述串口控制模块接收到所述主芯片发送初始化控制命令时，所述串口控制模块控制所述MIPI接收模块和数据切割模块进入低功耗，使所述FPGA建立主芯片分别与所述至少两个显示屏的透传通道；
    所述主芯片将所述屏幕参数和所述屏幕驱动通过相对应的透传通道发送到相对应的显示屏中，使所述显示屏根据所述屏幕参数和所述屏幕驱动进行初始化设置。
  3. 如权利要求1所述的多屏显示的低功耗控制方法，其特征在于，所述方法还包括：
    当串口控制模块接收到所述主芯片发送数据传输控制命令时，所述串口控制模块控制唤醒所述MIPI接收模块和所述数据切割模块，使所述MIPI接收模块切换至高速模式接收所述主芯片发送的合并图像数据；其中，所述合并图像数据包括图像数据、视频数据或图像与视频相互嵌入的组合数据；
    所述数据切割模块接收到的合并图像数据进行分割，并通过所述存储控制模块将分割后的数据发送到存储器进行存储，得到多个图像数据；
    所述存储控制模块通过MIPI发送模块将所述多个图像数据分别发送到相对应的显示屏进行显示。
  4. 如权利要求3所述的多屏显示的低功耗控制方法，其特征在于，当所述FPGA还 包括第一缓存模块和像素计数模块，所述数据切割模块接收到的合并图像数据进行分割，并通过所述存储控制模块将分割后的数据发送到存储器进行存储，得到多个图像数据，包括：
    所述MIPI接收模块将合并图像数据的每行像素依次存储在所述第一缓存模块中；
    所述数据切割模块从所述第一缓存模块中获取当前行像素；
    所述像素计数模块对所述当前行像素进行计数，当所述像素计数模块获取到数据分割点时使所述数据切割模块进行当前行像素的切割；
    所述数据切割模块将切割后的行像素通过所述存储控制模块发送到所述存储器进行存储后，从所述第一缓存模块中获取下一行像素进行分割。
  5. 如权利要求4所述的多屏显示的低功耗控制方法，其特征在于，当所述FPGA还包括第二缓存模块时，在所述数据切割模块将切割后的行像素通过所述存储控制模块发送到所述存储器进行存储的同时，所述方法还包括：
    所述切割后的行像素通过所述存储控制模块发送到所述第二缓存模块，使所述MIPI发送模块从所述第二缓存模块中获取切割后的行像素，并发送到相对应的显示屏进行显示。
  6. 如权利要求5所述的多屏显示的低功耗控制方法，其特征在于，当所述FPGA还包括时钟同步模块时，所述存储控制模块根据同步信号从所述存储器中获取当前存储的多个图像数据，并通过MIPI发送模块将所述多个图像数据分别发送到相对应的显示屏中进行屏幕自动刷新，包括：
    当所述时钟同步模块输出同步信号时，所述存储控制模块通过错位一个像素的方法将从所述存储器中获取的每个图像数据存储在所述第二缓存模块中，使所述MIPI发送模块从所述第二缓存模块中获取错位后的图像数据发送到相对应的显示屏进行显示。
  7. 一种显示设备，其特征在于，所述显示设备包括：
    主芯片、FPGA、存储器和至少两个显示屏，其中所述FPGA包括MIPI接收模块、数据切割模块、存储控制模块和MIPI发送模块；
    所述主芯片用于获取到休眠指令时且在休眠之前，发送休眠控制命令到所述FPGA，使所述FPGA根据所述休眠控制命令控制所述MIPI接收模块和所述数据切割模块进入低功耗状态；
    所述存储控制模块用于根据同步信号从所述存储器中获取当前存储的多个图像数据，并通过MIPI发送模块将所述多个图像数据分别发送到相对应的显示屏中进行屏幕 自动刷新。
  8. 如权利要求7所述的显示设备，其特征在于，当所述FPGA还包括串口控制模块时，所述主芯片还用于根据所述至少两个显示屏的屏幕ID，获取相匹配的屏幕参数和屏幕驱动；
    当所述串口控制模块接收到所述主芯片发送初始化控制命令时，所述串口控制模块用于控制所述MIPI接收模块和数据切割模块进入低功耗，使所述FPGA建立主芯片分别与所述至少两个显示屏的透传通道；
    所述主芯片还用于将所述屏幕参数和所述屏幕驱动通过相对应的透传通道发送到相对应的显示屏中，使所述显示屏根据所述屏幕参数和所述屏幕驱动进行初始化设置。
  9. 如权利要求7或8所述的显示设备，其特征在于，当所述串口控制模块接收到所述主芯片发送数据传输控制命令时，所述串口控制模块还用于控制唤醒所述MIPI接收模块和所述数据切割模块，使所述MIPI接收模块切换至高速模式接收所述主芯片发送的合并图像数据；
    所述数据切割模块用于接收到的合并图像数据进行分割，并通过所述存储控制模块将分割后的数据发送到存储器进行存储，得到多个图像数据；
    所述存储控制模块用于通过MIPI发送模块将所述多个图像数据分别发送到相对应的显示屏进行显示。
  10. 一种电子价签系统，其特征在于，所述价签系统包括权利要求7-9任一项所述的显示设备。
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Publication number Priority date Publication date Assignee Title
CN115712334A (zh) * 2022-11-04 2023-02-24 汉朔科技股份有限公司 多屏显示的低功耗控制方法、显示设备和电子价签系统
CN116471216B (zh) * 2023-05-26 2024-02-27 南京国兆光电科技有限公司 一种用于mipi协议层验证的硬件平台及其验证方法
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Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005242081A (ja) * 2004-02-27 2005-09-08 Canon Inc 表示装置
CN101093646A (zh) * 2007-06-28 2007-12-26 上海交通大学 利用伪彩色显示技术的嵌入式液晶显示系统低功耗方法
US20140022234A1 (en) * 2011-09-06 2014-01-23 Sharp Kabushiki Kaisha Display device and method for driving same
CN103810971A (zh) * 2012-11-14 2014-05-21 中兴通讯股份有限公司 终端的节能显示方法及装置、lcd模组、终端
CN113031751A (zh) * 2019-12-09 2021-06-25 Oppo广东移动通信有限公司 电子设备
CN113312020A (zh) * 2021-06-16 2021-08-27 北京康斯特仪表科技股份有限公司 用于手持设备的屏幕刷新方法及该手持设备
CN114090500A (zh) * 2022-01-13 2022-02-25 南京初芯集成电路有限公司 一种全通式图像处理soc芯片及图像处理方法
CN114118323A (zh) * 2021-11-26 2022-03-01 努比亚技术有限公司 降低电子价签功耗的方法、电子价签及可读存储介质
CN114442788A (zh) * 2022-04-08 2022-05-06 北京智芯半导体科技有限公司 芯片的低功耗系统、低功耗管理方法、控制装置及存储介质
CN114666878A (zh) * 2022-05-23 2022-06-24 汉朔科技股份有限公司 高效低功耗的通信方法、系统、计算机设备及存储介质
CN114679545A (zh) * 2022-03-30 2022-06-28 汉朔科技股份有限公司 一种多屏显示方法、显示装置及显示设备
CN115712334A (zh) * 2022-11-04 2023-02-24 汉朔科技股份有限公司 多屏显示的低功耗控制方法、显示设备和电子价签系统

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005242081A (ja) * 2004-02-27 2005-09-08 Canon Inc 表示装置
CN101093646A (zh) * 2007-06-28 2007-12-26 上海交通大学 利用伪彩色显示技术的嵌入式液晶显示系统低功耗方法
US20140022234A1 (en) * 2011-09-06 2014-01-23 Sharp Kabushiki Kaisha Display device and method for driving same
CN103810971A (zh) * 2012-11-14 2014-05-21 中兴通讯股份有限公司 终端的节能显示方法及装置、lcd模组、终端
CN113031751A (zh) * 2019-12-09 2021-06-25 Oppo广东移动通信有限公司 电子设备
CN113312020A (zh) * 2021-06-16 2021-08-27 北京康斯特仪表科技股份有限公司 用于手持设备的屏幕刷新方法及该手持设备
CN114118323A (zh) * 2021-11-26 2022-03-01 努比亚技术有限公司 降低电子价签功耗的方法、电子价签及可读存储介质
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CN114679545A (zh) * 2022-03-30 2022-06-28 汉朔科技股份有限公司 一种多屏显示方法、显示装置及显示设备
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CN115712334A (zh) * 2022-11-04 2023-02-24 汉朔科技股份有限公司 多屏显示的低功耗控制方法、显示设备和电子价签系统

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