WO2024093044A1 - 存储器 - Google Patents

存储器 Download PDF

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Publication number
WO2024093044A1
WO2024093044A1 PCT/CN2023/076108 CN2023076108W WO2024093044A1 WO 2024093044 A1 WO2024093044 A1 WO 2024093044A1 CN 2023076108 W CN2023076108 W CN 2023076108W WO 2024093044 A1 WO2024093044 A1 WO 2024093044A1
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WIPO (PCT)
Prior art keywords
array
data
storage array
storage
selection circuit
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PCT/CN2023/076108
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English (en)
French (fr)
Inventor
鲁耀华
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长鑫存储技术有限公司
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Publication of WO2024093044A1 publication Critical patent/WO2024093044A1/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair

Definitions

  • the present disclosure relates to memory technology, and more particularly to a memory.
  • DRAM dynamic random access memory
  • the memory unit may fail, and the failed memory unit cannot work normally and needs to be replaced and repaired. Therefore, considering the possible replacement and repair, how to ensure that the memory can achieve accurate data processing becomes a problem that needs to be considered.
  • An embodiment of the present disclosure provides a memory.
  • the first aspect of the present disclosure provides a memory, comprising: N storage arrays arranged in sequence, the N storage arrays are respectively recorded as the 1st storage array, the 2nd storage array, ..., the i-th storage array, ..., the N-th storage array, wherein at least one of the storage arrays is a redundant array, and at least one of the storage arrays is a main storage array, the redundant array is used to replace the faulty storage unit in the main storage array, 1 ⁇ i ⁇ N, and i and N are positive integers; N-1 selection circuits, respectively recorded as the 1st selection circuit, the 2nd selection circuit, ..., the i-th selection circuit, ..., the N-1-th selection circuit; wherein the i-th selection circuit receives data read from the i-th storage array and the i+1-th storage array, and the i-th selection circuit is used to output the data read from the i-th storage array or the data read from the i+1-th storage array according to the i
  • the main storage array and the redundant array each include M columns, respectively recorded as the 1st column, the 2nd column, ..., the jth column, ..., the Mth column, the jth column of the redundant array is used to replace the jth column of any one of the main storage arrays, 1 ⁇ j ⁇ M, and j and M are positive integers.
  • the selection circuit includes: a plurality of sub-selection circuits, and each of the sub-selection circuits of the i-th selection circuit receives 1-bit data read out from the i-th storage array and the (i+1)-th storage array, respectively.
  • the sub-selection circuit includes a data selector, a first data input terminal of the data selector receives data read from the i-th storage array, a second data input terminal of the data selector receives data read from the i+1-th storage array, The selection end of the data selector receives the i-th selection signal.
  • the number of the redundant array is one.
  • the first storage array is the redundant array.
  • the i-th selection circuit when a faulty storage unit in the nth storage array is replaced by the redundant array, within the range of 1 ⁇ i ⁇ n, the i-th selection circuit outputs data read from the i-th storage array, and within the range of n ⁇ i ⁇ N-1, the i-th selection circuit outputs data read from the i+1-th storage array, where n is a positive integer; when a faulty storage unit in the N-th storage array is replaced by the redundant array, the i-th selection circuit outputs data read from the i-th storage array.
  • the Nth storage array is the redundant array.
  • the i-th selection circuit when a faulty storage unit in the nth storage array is replaced by the redundant array, within the range of 1 ⁇ i ⁇ n, the i-th selection circuit outputs data read from the i-th storage array, and within the range of n ⁇ i ⁇ N-1, the i-th selection circuit outputs data read from the i+1-th storage array, where n is a positive integer; when a faulty storage unit in the 1st storage array is replaced by the redundant array, the i-th selection circuit outputs data read from the i+1-th storage array.
  • the mth storage array is the redundant array, 1 ⁇ m ⁇ N and m is a positive integer.
  • the i-th selection circuit when a faulty storage unit in the nth storage array is replaced by the redundant array, within the range of 1 ⁇ i ⁇ n-1, the i-th selection circuit outputs data read from the i-th storage array, and within the range of n ⁇ i ⁇ N-1, the i-th selection circuit outputs data read from the i+1-th storage array, n ⁇ m and n is a positive integer; when a faulty storage unit in the k-th storage array is replaced by the redundant array, within the range of 1 ⁇ i ⁇ k, the i-th selection circuit outputs data read from the i-th storage array, and within the range of k ⁇ i ⁇ N-1, the i-th selection circuit outputs data read from the i+1-th storage array, m ⁇ k and k is a positive integer.
  • the number of the redundant arrays is plural and the redundant arrays are not adjacent.
  • At least one of the main storage arrays is a check code storage array, and the check code storage array stores check code data.
  • the memory further includes: a verification module; the verification module is connected to the N-1 selection circuits, the data output by the N-1 selection circuits includes data to be verified and verification code data, and the verification module is used to perform data verification on the data to be verified according to the verification code data.
  • the memory provided by the embodiment of the present disclosure includes N memory arrays arranged in sequence, including at least one main memory array and at least one redundant array, the redundant array is used to replace the faulty unit of the main memory array, and N-1 selection circuits, each selection circuit receives data read from the memory array corresponding to the bit sequence and the next memory array, and each selection circuit responds to its own selection signal and outputs corresponding data by selection to realize data reading after the faulty memory unit is replaced.
  • the memory of this scheme is provided with multiple selection circuits, and according to the replacement of the faulty unit of the memory, the selection circuit is controlled to output corresponding data, thereby realizing data reading after the faulty memory unit is replaced, and ensuring the accuracy and reliability of data processing.
  • FIG1 is a diagram showing an example of a memory architecture according to an embodiment
  • FIG2 is a structural diagram of a storage unit according to an embodiment
  • FIG3 and FIG4 are respectively diagrams of an exemplary replacement solution architecture
  • FIG5 is a diagram showing an example structure of a memory provided by an embodiment
  • FIGS 6 and 7 are example diagrams of states under different circumstances
  • FIG8 is a diagram showing an example of a storage array architecture
  • FIG9 is a structural diagram of an exemplary memory
  • Figures 10 to 12 are example diagrams of states under different situations
  • FIG13 is a structural diagram of an exemplary memory
  • Figures 14 to 16 are example diagrams of states under different situations
  • FIG17 is a diagram showing an exemplary structure of a memory device
  • FIG. 18 and FIG. 19 are diagrams showing examples of states in different situations.
  • FIG1 is an example diagram of the architecture of a memory device according to an embodiment.
  • a DRAM is used as an example, including a data input/output buffer, a row decoder, a column decoder, a sense amplifier, and a storage array.
  • the data input/output buffer belongs to the peripheral area circuit, and the sense amplifier, the row decoder, the column decoder, and the storage array belong to the array area circuit.
  • the storage array is mainly composed of word lines, bit lines, and storage cells.
  • the word lines in the memory array extend in the row direction
  • the bit lines in the memory array extend in the column direction
  • the intersection of the word lines and the bit lines is the memory cell of the memory array.
  • FIG2 is a structural example diagram of a storage unit shown in an embodiment, and the storage unit is mainly composed of a transistor switch M and a capacitor C.
  • the capacitor is used to store data, and the transistor switch is used to turn off or on according to the selected state.
  • a certain storage cell can be activated by controlling the word line and the bit line to access the storage cell.
  • the read scenario as an example: when the data in the storage cell needs to be read, the word line of the row where the storage cell is located can be selected through the row decoder. Correspondingly, the transistor M in the diagram is turned on, and the state of the capacitor C at this time can be sensed by sensing and amplifying the bit line signal. For example, if the bit data stored in the storage cell is 1, then after the transistor M is turned on, 1 will be read from the bit line of the storage cell, and vice versa.
  • the write scenario as an example: when bit data needs to be written to a certain storage cell, such as writing 1.
  • the word line of the row where the storage cell is located can be selected through the row decoder, and the corresponding transistor M in the diagram is turned on.
  • the logic level of the bit line By setting the logic level of the bit line to 1, the capacitor C is charged, that is, 1 is written to the storage cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the capacitor C is discharged, that is, 0 is written to the storage cell.
  • faulty storage cells may be generated in the storage array.
  • These faulty storage cells cannot work properly, so in order to prevent the faulty storage cells from affecting the normal operation of the memory, in addition to planning the main storage array containing regular storage cells, a redundant array is also planned during the design.
  • the storage cells in the redundant array are used as redundant parts to replace the faulty storage cells in the main storage array.
  • replacement in this article refers to the replacement of storage function, that is, ensuring the number of storage units that can be used to store data normally after replacement.
  • Specific replacement methods include but are not limited to using redundant storage units to store the bit data that the failed storage unit originally needed to store, or ensuring that after adding redundant storage units, the number of storage units that can work normally can ensure the storage of complete data, and there is no restriction on which storage unit stores which bit of data.
  • a storage column including regular storage cells and a redundant column including redundant storage cells are designed in the storage array.
  • the redundant column and the storage column share the data line of the storage array, and the data line is used to transmit read or write data.
  • CCR Central Column Repair
  • all redundant storage cells are set in an independent redundant array, and the redundant array and the regular storage array are set independently, each with an independent data line. Therefore, it is necessary to provide an effective solution to support data processing when a fault replacement occurs under this architecture, such as normal reading of data.
  • Figures 3 and 4 are respectively an example of an architecture diagram of a replacement scheme, taking a memory including N storage arrays as an example, namely the first storage array, the second storage array, ... the Nth storage array.
  • the fault replacement scheme adopted in Figure 3 is the LCR scheme, and the columns filled with shades in the figure are redundant columns, and the unfilled shaded parts are regular storage columns. It can be seen that in the LCR scheme, each redundant column is integrated into each storage array, and the storage columns and redundant columns under each storage array share data lines.
  • the fault replacement scheme adopted in Figure 4 The scheme is a CCR scheme.
  • the array filled with shades in the figure is a redundant array, and the unfilled shaded part is a conventional main storage array.
  • a redundant array is independently set up, and the storage units in the redundant array are used to replace the failed storage units in the main storage array.
  • Each array is configured with an independent data line. It should be noted that the figure is only an example, and the specific array architecture can be adjusted according to actual needs and is not limited to the example in the figure.
  • FIG5 is a structural example diagram of a memory provided by an embodiment. As shown in FIG5, the memory includes:
  • N storage arrays 11 are arranged in sequence, the N storage arrays are respectively recorded as the first storage array, the second storage array, ..., the i-th storage array, ..., the N-th storage array, wherein at least one storage array is a redundant array, and at least one storage array is a primary storage array, the redundant array is used to replace a faulty storage unit in the primary storage array, 1 ⁇ i ⁇ N, and i and N are positive integers;
  • the N-1 selection circuits 12 are respectively recorded as the 1st selection circuit, the 2nd selection circuit, ..., the i-th selection circuit, ..., the N-1-th selection circuit; wherein the i-th selection circuit receives the data read out from the i-th storage array and the i+1-th storage array, and the i-th selection circuit is used to output the data read out from the i-th storage array or the data read out from the i+1-th storage array according to the i-th selection signal.
  • the data read from the storage array 11 is recorded as Data, wherein the data read from the i-th storage array is recorded as Data_i, Data_i may be data read from the main storage array, or may be data Data_Red read from the redundant array, which may be determined specifically depending on the type of the i-th storage array.
  • the memory of this embodiment includes but is not limited to a double data rate synchronous dynamic random access memory (DDR for short), etc.
  • the main storage array in the storage array is used to store data when there is no faulty storage unit.
  • at least one main storage array is a check code storage array
  • the check code storage array stores check code data. That is, the data read from the storage array will contain the data to be verified Data_CP, and the check code data Data_ECC.
  • the check code storage array stores the check code data, which can be interpreted as the check code storage array normally stores the check code data when there is no faulty storage unit.
  • the faulty storage unit in the check code storage array can also be replaced by a redundant array.
  • the check code data corresponding to the faulty storage unit will be stored in a storage unit after the replacement.
  • the data verification method may include but is not limited to parity check, cyclic redundancy check, etc.
  • the verification scheme verification is required based on the verification code data. Therefore, when writing data to the storage array, the verification code data will be generated and written at the same time, so that when the data is read, the read storage data is verified according to the read verification code data.
  • the memory also includes: a verification module 13; the verification module 13 is connected to N-1 selection circuits 12, and the data output by the N-1 selection circuits 12 includes data to be verified and verification code data.
  • the verification module 13 is used to perform data verification on the data to be verified according to the verification code data.
  • Data_1 represents the data that should be stored in the first main storage array under normal circumstances among the complete 34 sets of data, and the first data represents the data actually read from the first storage array
  • Data_2 represents the data that should be stored in the second main storage array under normal circumstances among the complete 34 sets of data, and the second data represents the data actually read from the second storage array
  • Data_Red represents the data stored in the redundant array.
  • the i-th data is Data_Red data.
  • the data in the redundant array is specifically the data stored after replacing the faulty storage unit.
  • the data may be one of the 34 sets of data. Which set of data it is can be determined according to the actual situation, and an example will be given later.
  • FIG6 is a state example diagram under a situation where there is no faulty storage unit in the main storage array.
  • the complete 34 sets of data should be stored in the corresponding main storage array.
  • Data_1 (the first data) in the complete data is stored in the first storage array (the first main storage array)
  • Data_2 (the second data) is stored in the second storage array (the second main storage array)
  • Data_17 (the 17th data) is stored in the 17th storage array (the 17th main storage array)
  • the 18th storage array is a redundant array
  • the 18th storage array is used to replace the main storage array. Since the memory has no faulty storage units, the redundant array does not store data, and therefore the 18th data is not read out from the 18th storage array.
  • Data_18 (the 19th data) is stored in the 19th storage array (the 18th main storage array)
  • Data_19 (the 20th data) is stored in the 20th storage array (the 19th main storage array)
  • Data_34 (the 35th data) is stored in the 35th storage array (the 34th main storage array).
  • the i-th selection circuit receives data (i-th data) read out from the i-th storage array and data (i+1-th data) read out from the i+1-th storage array.
  • the 1st selection circuit receives the 1st data and the 2nd data.
  • the 1st data is Data_1 read out from the 1st storage array
  • the 2nd data is Data_2 read out from the 2nd storage array
  • the 17th selection circuit receives the 17th data and the 18th data
  • the 18th selection circuit receives the 18th data and the 19th data.
  • the 17th data is Data_17 read out from the 17th storage array
  • the 19th data is Data_18 read out from the 19th storage array. Since the memory has no faulty storage cells, the redundant array does not store data, and therefore the 18th data is not read out from the 18th storage array, ...
  • the 34th selection circuit receives the 34th data and the 35th data. At this time, the 34th data is Data_33 read out from the 34th storage array, and the 35th data is Data_34 read out from the 35th storage array.
  • the i-th selection circuit selects to output the i-th data
  • the i-th selection circuit selects to output the i+1-th data, thereby realizing that the data output by the N-1 selection circuits constitute the complete data Data_1 ⁇ Data_34.
  • FIG7 is a state example diagram under another situation, in which there is a faulty storage unit in the main storage array.
  • the redundant array (the 18th storage array) is used to replace the faulty storage unit in the first storage array.
  • Data_1 originally stored in the first storage array is transferred to the second storage array, and Data_2 originally stored in the second storage array is stored in the third storage array, until Data_17 originally stored in the 17th storage array is stored in the redundant array (the 18th storage array), thereby replacing the faulty storage unit in the first storage array.
  • the first storage array may not store data, or may store data but not read the data. Therefore, the first data read out from the first storage array is empty or there is no need to read data from the first storage array, the second data read out from the second storage array is Data_1, ... the 17th data read out from the 17th storage array is Data_16, the 18th data (Data_Red) read out from the 18th storage array (redundant array) is Data_17, and the states of the 19th data to the 35th data are similar to the state shown in FIG. 6 .
  • the first selection circuit receives the first data and the second data, that is, the empty data and Data_1, ... the second selection circuit receives the second data and the third data, that is, Data_1 and Data_2, ... the 17th selection circuit receives the 17th data and the 18th data, that is, Data_16 and Data_Red (Data_Red is Data_17 at this time), ... the 18th selection circuit receives the 18th data and the 19th data, that is, Data_Red (Data_17 at this time) and Data_18, ... the 34th selection circuit receives the 34th data and the 35th data, that is, Data_33 and Data_34.
  • each selection unit is controlled to select and output the data read out from the i-th storage array or from the i+1-th storage array according to its own selection signal to output the complete data.
  • the i-th selection circuit selects to output the i+1-th data
  • the i-th selection circuit also selects to output the i+1-th data, thereby realizing that the data output by the N-1 selection circuits constitute the complete data Data_1 ⁇ Data_34.
  • N-1 selection circuits are set for N storage arrays, and the selection circuits can be controlled to select and output corresponding data regardless of whether a failed storage unit is replaced, so as to achieve accurate output of complete data and ensure the accuracy and reliability of data processing.
  • the solution of this embodiment is convenient for circuit design and preparation, and can be applied to high-integration scenarios such as memory.
  • FIG8 is an example diagram of the architecture of a storage array.
  • the main storage array and the redundant array both include multiple columns, for example, M columns, which are respectively recorded as the first column, the second column, ..., the jth column, ..., the Mth column.
  • the jth column of the redundant array is used to replace the jth column of the main storage array, where 1 ⁇ j ⁇ M, and j and M are positive integers.
  • the single "column” here refers to the control object of a single column selection signal.
  • the storage array includes multiple physical rows (for example, understood as word lines) and multiple physical columns (for example, understood as bit lines) in physical structure.
  • multiple physical columns in a storage array are divided into multiple groups of columns, and all physical columns in each group of columns are controlled by the same column selection signal, and columns in different groups are controlled by different column selection signals.
  • a storage array includes 16 physical columns, it is divided according to every 4 physical columns, and 4 columns (column_1 to column_4) will be obtained.
  • Column_1 to column_4 correspond to column selection signals 1 to column selection signals 4 respectively, and the 4 physical columns in each column correspond to the same column selection signal.
  • Each column can be regarded as a "column" described in this example. It should be noted that, in the case of multiple storage arrays, the same column selection signal is used to select the same column in different storage arrays.
  • the same column here refers to the column with the same position in different storage arrays, for example, column selection signal 1 is used to select column_1 in all storage arrays.
  • a single “column” in this example is a single physical column.
  • a storage array includes 8 physical columns, which are respectively controlled by 8 column selection signals. Then, each physical column at this time can be regarded as a "column” described in this example. This embodiment does not limit this.
  • the selection circuit 12 includes: a plurality of sub-selection circuits 121, each sub-selection circuit of the i-th selection circuit receives 1-bit data read out from the i-th storage array and the i+1-th storage array respectively.
  • each storage array 11 includes a plurality of columns 21, and an enlarged view of one of the storage arrays is used as an example in the figure, and each column 21 is further composed of a plurality of physical columns (for example, 4 bits).
  • the column decoder will parse the column selection signal from the read instruction, for example, the column selection signal represents the address of the first column.
  • the first column of the plurality of storage arrays 11 is selected.
  • the i-th data includes 4-bit data read from the first column of the i-th storage array, that is, the first data includes 4-bit data read from the first column of the first storage array, and the second data includes 4-bit data read from the first column of the second storage array, and so on. Therefore, the i-th selection circuit includes 4 sub-selection circuits, each corresponding to 1 bit of the 4-bit data, and each sub-selection circuit in the i-th selection circuit receives 1 bit of the 4-bit data read from the column of the i-th storage array selected by the current column selection signal, and 1 bit of the 4-bit data read from the column of the i+1-th storage array selected by the column selection signal.
  • the column selection signal has the same position in the columns selected by different storage arrays, and the two bits received by the sub-selection circuit here come from the physical columns of the storage array, are distributed in the same columns of the two different storage arrays, and have the same position in each column.
  • the column selection signal is the address of the first column
  • the two bits of data received by the first sub-selection circuit of the first selection circuit come from the first bit of the 4 bits read out of the first column of the first storage array, and the first bit of the 4 bits read out of the first column of the second storage array.
  • the selection circuit may include one or more sub-selection circuits, and the sub-selection circuits in the same selection circuit have the same selection signal. Therefore, in one example, the sub-selection circuits in the same selection circuit may share a selection signal, and different selection circuits receive their own independent selection signals.
  • the sub-selection circuit is used to select a data output from the received data in response to a selection signal.
  • the implementation of the sub-selection circuit is not limited.
  • the sub-selection circuit includes a data selector, and the first data input terminal of the data selector receives the data read from the i-th storage array, the second data input terminal of the data selector receives the data read from the i+1-th storage array, and the selection terminal of the data selector receives the i-th selection signal.
  • the sub-selection circuit includes a data selector, so as to select and output corresponding data according to the selection signal, and the sub-selection circuit is implemented by conventional devices, which can simplify the circuit structure and reduce costs.
  • how the data selector outputs data according to the level of the selection signal can be set according to actual needs. For example, it can be set so that when the selection signal is at a high level, the output end of the data selector outputs the data received by the first input end, and when the selection signal is at a low level, the output end of the data selector outputs the data received by the second input end, thereby realizing the selection and output of corresponding data according to the selection signal, and realizing the sub-selection circuit through conventional devices, which can simplify the circuit structure and reduce costs.
  • the sub-selection circuit in the i-th selection circuit may include a first switch tube and a second switch tube, the first end of the first switch tube receives 1 bit of data read from the i-th storage array, the first end of the second switch tube receives 1 bit of data read from the i+1-th storage array, the second end of the first switch tube and the second end of the second switch tube serve as output ends of the sub-selection circuit, wherein one of the first switch tube or the second switch tube is closed according to the i-th selection signal, and the other is opened according to the i-th selection signal, thereby realizing the selection and output of corresponding data according to the selection signal, and realizing the sub-selection circuit by conventional devices, which can simplify the circuit structure and reduce costs.
  • the arrangement of each storage array can be designed as needed.
  • the number of redundant arrays can be one or more. Taking the number of redundant arrays as one as an example, there are also many arrangements of redundant arrays.
  • the redundant arrays can be located in the entire The edge of the storage array, for example, the first storage array or the Nth storage array is a redundant array.
  • the redundant array may be located between the storage arrays, for example, the mth storage array is a redundant array, 1 ⁇ m ⁇ N and m is a positive integer.
  • the number of redundant arrays is one.
  • each column in a single redundant array can be used to replace a column in the same position in any main storage array.
  • the first column in the redundant array can be used to replace the first column in any main storage array
  • the second column in the redundant array can be used to replace the second column in any main storage array.
  • when there are faulty storage units in both columns of a main storage array they can be replaced with two columns in the same position in the redundant array. The replacement of faulty storage units can be achieved by setting redundant arrays.
  • FIG. 9 is a structural example diagram of an example memory, as shown in FIG. 9, the first storage array is a redundant array. That is, the redundant array is set in the first storage array. As shown in FIG. 9, the storage array filled with shades in the figure is a redundant array, and the storage array not filled with shades is a main storage array.
  • FIG. 10 is a state example diagram under a situation where there is no faulty storage unit in the main storage array.
  • the first storage array is a redundant array, and the second to third storage arrays are all main storage arrays.
  • the first storage array is a redundant array, so the data read from the first storage array (the first data) is Data_Red, and Data_1 to Data_34 are stored in the second to third storage arrays (34 main storage arrays) in sequence.
  • FIG. 10 is a state example diagram under a situation where there is no faulty storage unit in the main storage array.
  • the first storage array is a redundant array, and the second to third storage arrays are all main storage arrays.
  • the first storage array is a redundant array, so the data read from the first storage array (the first data) is Data_Red, and Data_1 to Data_34 are stored in the second to third storage arrays (34 main storage arrays) in sequence.
  • FIG. 10 is a state example diagram under a situation where there is no faulty storage unit in
  • the first selection circuit receives the data read from the first storage array and the second storage array, namely Data_Red and Data_1
  • the second selection circuit receives the data read from the second storage array and the third storage array, namely Data_1 and Data_2, ... and so on, until the 34th selection circuit receives the data read from the 34th storage array and the 35th storage array, namely Data_33 and Data_34.
  • the i-th selection circuit outputs the data read from the i+1-th storage array, so that the data output by the N-1 selection circuits constitutes the complete data Data_1 to Data_34.
  • Fig. 11 is a state example diagram under another situation, in which there is a faulty storage unit in the main storage array. Specifically, when the faulty storage unit in the nth storage array is replaced by the redundant array, within the range of 1 ⁇ i ⁇ n, the i-th selection circuit outputs the data read from the i-th storage array, and within the range of n ⁇ i ⁇ N-1, the i-th selection circuit outputs the data read from the i+1th storage array, where n is a positive integer.
  • a main storage array has a faulty storage unit, and the main storage array is not the last storage array.
  • Data_1 originally stored in the 2nd storage array is stored in the 1st storage array (redundant array), thereby achieving the replacement of the faulty unit
  • Data_17 originally stored in the 18th storage array is still stored in the 18th storage array
  • Data_18 originally stored in the 19th storage array is still stored in the 19th storage array
  • Data_34 originally stored in the 35th storage array is still stored in the 35th storage array.
  • the i-th selection circuit outputs the data read from the i-th storage array, that is, the 1st to 16th selection circuits output the data read from the 1st to 16th storage arrays, that is, output Data_1 to Data_16; within the range of 17 ⁇ i ⁇ 34, the i-th selection circuit outputs the data read from the i+1th storage array, that is, the 17th to 34th selection circuits output the data read from the 18th to 35th storage arrays, that is, Data_17 to Data_34, so that the data output by N-1 selection circuits constitute complete data, and accurate data reading is achieved.
  • the i-th selection circuit when the faulty storage unit in the Nth storage array is replaced by the redundant array, the i-th selection circuit outputs the data read from the i-th storage array. That is, when the redundant array is the first storage array and the storage array that has a fault and is replaced is the last storage array, all selection circuits select to output the data read from the i-th storage array.
  • a main storage array has a faulty storage unit
  • the main storage array is the last storage array.
  • the 35th storage array has a faulty storage unit.
  • the 35th storage array does not store data
  • Data_34 originally stored in the 35th storage array is stored in the 34th storage array
  • Data_33 originally stored in the 34th storage array is stored in the 33rd storage array
  • Data_1 originally stored in the 2nd storage array is stored in the 1st storage array (redundant array), thereby achieving faulty unit replacement.
  • the i-th selection circuit outputs the data read from the i-th storage array, that is, the 1st to 34th selection circuits respectively output the data read from the 1st to 34th storage arrays, that is, output Data_1 to Data_34, so that the data output by N-1 selection circuits constitute complete data, thereby realizing accurate data reading.
  • FIG. 13 is a structural example diagram of an example memory, as shown in FIG. 13, the Nth storage array is a redundant array. That is, the redundant array is set at the last storage array.
  • the storage array filled with shades in the figure is a redundant array, and the storage array not filled with shades is a main storage array.
  • FIG. 14 is a state example diagram under a situation where there is no faulty storage unit in the main storage array.
  • the 35th storage array is a redundant array, and the 1st to 34th storage arrays are all main storage arrays.
  • the 35th storage array is a redundant array, so the data read from the 35th storage array (the 35th data) is Data_Red, and Data_1 to Data_34 are stored in the 1st to 34th storage arrays (34 main storage arrays) in sequence.
  • the 1st selection circuit receives the data read from the 1st storage array and the 2nd storage array, namely Data_1 and Data_2, the 2nd selection circuit receives the data read from the 2nd storage array and the 3rd storage array, namely Data_2 and Data_3, ... and so on, until the 34th selection circuit receives the data read from the 34th storage array and the 35th storage array, namely Data_34 and Data_Red.
  • the i-th selection circuit outputs the data read from the i-th storage array, so that the data output by the N-1 selection circuits constitutes the complete data Data_1 to Data_34.
  • Fig. 15 is a state example diagram under another situation, in which there is a faulty storage unit in the main storage array. Specifically, when the faulty storage unit in the nth storage array is replaced by the redundant array, within the range of 1 ⁇ i ⁇ n, the i-th selection circuit outputs the data read from the i-th storage array, and within the range of n ⁇ i ⁇ N-1, the i-th selection circuit outputs the data read from the i+1th storage array, where n is a positive integer.
  • a main storage array has a faulty storage unit, and the main storage array is not the first storage array.
  • the 17th storage array does not store data
  • Data_17 originally stored in the 17th storage array is stored in the 18th storage array
  • Data_18 originally stored in the 18th storage array is stored in the 19th storage array, ...
  • Data_34 originally stored in the 34th storage array is stored in the 35th storage array (redundant array), thereby achieving faulty unit replacement, and Data_1 originally stored in the 1st storage array is still stored in the 1st storage array, and Data_2 originally stored in the 2nd storage array is stored in the 2nd storage array.
  • Data_16 originally stored in the 16th storage array is still stored in the 16th storage array.
  • the i-th selection circuit outputs the data read from the i-th storage array, that is, the 1st to 16th selection circuits output the data read from the 1st to 16th storage arrays, that is, output Data_1 to Data_16; within the range of 17 ⁇ i ⁇ 34, the i-th selection circuit outputs the data read from the i+1th storage array, that is, the 17th to 34th selection circuits respectively output the data read from the 18th to 35th storage arrays, that is, Data_17 to Data_34, so that the data output by N-1 selection circuits constitutes complete data, and the data is accurately read.
  • the i-th selection circuit outputs the data read from the i+1 storage array. That is, when the redundant array is the last storage array and the storage array that has a fault and is replaced is the first storage array, all selection circuits select to output the data read from the i+1 storage array.
  • the first storage array does not store data
  • Data_1 originally stored in the first storage array is stored in the second storage array
  • Data_2 originally stored in the second storage array is stored in the third storage array
  • Data_34 originally stored in the 34th storage array is stored in the 35th storage array (redundant array), thereby achieving faulty unit replacement.
  • the i-th selection circuit outputs the data read from the i+1-th storage array, that is, the 1st to 34th selection circuits respectively output the data read from the 2nd to 35th storage arrays, that is, output Data_1 to Data_34, so that the data output by the N-1 selection circuits constitute complete data, thereby realizing accurate data reading.
  • FIG17 is a structural example diagram of an example memory, as shown in FIG17, the mth storage array is a redundant array, 1 ⁇ m ⁇ N and m is a positive integer. That is, the redundant array is set in a storage array that is not the first or the last.
  • the circuit operation principle when the redundant array is the mth storage array is exemplified below: still taking the complete data read once as 34 groups of data as an example, the example can be combined with the aforementioned FIG6.
  • the state when there is no faulty storage unit in the main storage array is shown in FIG6.
  • FIG. 18 and FIG. 19 are state example diagrams under two situations, respectively.
  • the situation shown in FIG. 18 is that the storage array where the fault occurs is located before the redundant array, that is, in one example, when the faulty storage unit in the nth storage array is replaced by the redundant array, within the range of 1 ⁇ i ⁇ n-1, the i-th selection circuit outputs the data read from the i-th storage array, and within the range of n ⁇ i ⁇ N-1, the i-th selection circuit outputs the data read from the i+1th storage array, n ⁇ m and n is a positive integer.
  • the 15th storage array no longer stores data
  • Data_15 originally stored in the 15th storage array is stored in the 16th storage array
  • Data_16 originally stored in the 16th storage array is stored in the 17th storage array
  • Data_17 originally stored in the 17th storage array is stored in the 18th storage array (redundant array), completing the fault replacement.
  • the i-th selection circuit outputs the data read from the i-th storage array, that is, the 1st to 14th selection circuits respectively output the data read from the 1st to 14th storage arrays, that is, Data_1 to Data_14; within the range of 15 ⁇ i ⁇ 34, the i-th selection circuit outputs the data read from the i+1th storage array, that is, the 15th to 34th selection circuits respectively output the data read from the 16th to 35th storage arrays, that is, Data_15 to Data_34, thereby realizing that the data output by N-1 selection circuits constitute a complete data To achieve accurate reading of data.
  • FIG19 shows a situation where the failed storage array is located after the redundant array, that is, in one example, when the failed storage unit in the kth storage array is replaced by the redundant array, within the range of 1 ⁇ i ⁇ k, the i-th selection circuit outputs the data read from the i-th storage array, and within the range of k ⁇ i ⁇ N-1, the i-th selection circuit outputs the data read from the i+1th storage array, m ⁇ k and k is a positive integer.
  • the 21st storage array no longer stores data
  • Data_20 originally stored in the 21st storage array is stored in the 20th storage array
  • Data_19 originally stored in the 20th storage array is stored in the 19th storage array
  • Data_18 originally stored in the 19th storage array is stored in the 18th storage array (redundant array), completing the failure replacement.
  • the i-th selection circuit outputs the data read from the i-th storage array, that is, the 1st to 20th selection circuits respectively output the data read from the 1st to 20th storage arrays, that is, Data_1 to Data_20; within the range of 21 ⁇ i ⁇ 34, the i-th selection circuit outputs the data read from the i+1-th storage array, that is, the 21st to 34th selection circuits respectively output the data read from the 22nd to 35th storage arrays, that is, Data_21 to Data_34, thereby achieving the data output by the N-1 selection circuits constituting complete data, and achieving accurate data reading.
  • the number of redundant arrays is multiple and the redundant arrays are not adjacent.
  • the redundant columns in the 7th storage array can be used to replace the faulty storage units in the 1st storage array to the 6th storage array
  • the redundant columns in the 15th storage array can be used to replace the faulty storage units in the 16th storage array to the 35th storage array.
  • the main storage array between two adjacent redundant arrays for example, the 8th storage array to the 14th storage array
  • they can be divided during design, for example, the 8th storage array to the 9th storage array are divided into the 7th storage array responsible for fault replacement, and the 10th storage array to the 14th storage array are divided into the 15th storage array responsible for fault replacement.
  • the control mechanism for executing fault replacement and selecting circuits is similar to the aforementioned scheme.
  • the memory provided in this embodiment includes N memory arrays arranged in sequence, including at least one main memory array and at least one redundant array, the redundant array is used to provide faulty unit replacement of the main memory array, and N-1 selection circuits, each selection circuit receives data read from the memory array corresponding to the bit sequence and the next memory array, and each selection circuit responds to its own selection signal and outputs a corresponding signal by selection to achieve data processing in a fault replacement scenario.
  • the memory of this solution sets multiple selection circuits, and controls the selection circuit to output corresponding data according to the faulty unit replacement situation of the memory, thereby achieving data processing under fault replacement and ensuring the accuracy and reliability of data processing.

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Abstract

本公开提供一种存储器，包括：依次排列的N个存储阵列，N个存储阵列分别记为第1存储阵列，第2存储阵列，…，第i存储阵列，…，第N存储阵列，其中至少一个存储阵列为冗余阵列，且至少一个存储阵列为主存储阵列，冗余阵列用于替换主存储阵列中的故障存储单元，1≤i<N，且i和N为正整数；N-1个选择电路，分别记为第1选择电路，第2选择电路，…，第i选择电路，…，第N-1选择电路；其中，第i选择电路接收从第i存储阵列和第i+1存储阵列读出的数据，且第i选择电路用于根据第i选择信号输出从第i存储阵列读出的数据或从第i+1存储阵列读出的数据。

Description

存储器
本公开要求于2022年11月02日提交中国专利局、申请号为202211361064.5、申请名称为“存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及存储器技术，尤其涉及一种存储器。
背景技术
伴随存储器技术的发展，存储器被广泛应用在多种领域，比如，动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)的使用非常广泛。
实际应用中，在存储器的生产和使用过程中，存储单元可能会产生故障，故障存储单元不能正常工作，需要进行替换修复。因此，结合考虑可能进行替换修复的情况，如何保证存储器实现准确的数据处理，成为需要考虑的问题。
发明内容
本公开的实施例提供一种存储器。
根据一些实施例，本公开第一方面提供一种存储器，包括：依次排列的N个存储阵列，所述N个存储阵列分别记为第1存储阵列，第2存储阵列，…，第i存储阵列，…，第N存储阵列，其中至少一个所述存储阵列为冗余阵列，且至少一个所述存储阵列为主存储阵列，所述冗余阵列用于替换所述主存储阵列中的故障存储单元，1≤i<N，且i和N为正整数；N-1个选择电路，分别记为第1选择电路，第2选择电路，…，第i选择电路，…，第N-1选择电路；其中，第i选择电路接收从所述第i存储阵列和第i+1存储阵列读出的数据，且所述第i选择电路用于根据第i选择信号输出从所述第i存储阵列读出的数据或从所述第i+1存储阵列读出的数据。
在一些实施例中，所述主存储阵列和所述冗余阵列均包括M个列，分别记为第1列，第2列，…，第j列，…，第M列，所述冗余阵列的第j列用于替换任意一个所述主存储阵列的第j列，1≤j≤M，且j和M为正整数。
在一些实施例中，所述选择电路包括：多个子选择电路，所述第i选择电路的每一所述子选择电路分别接收从所述第i存储阵列和第i+1存储阵列的读出的1bit数据。
在一些实施例中，所述子选择电路包括数据选择器，所述数据选择器的第一数据输入端接收从所述第i存储阵列读出的数据，所述数据选择器的第二数据输入端接收从所述第i+1存储阵列读出的数据，所 述数据选择器的选择端接收所述第i选择信号。
在一些实施例中，所述冗余阵列的数量为一个。
在一些实施例中，所述第1存储阵列为所述冗余阵列。
在一些实施例中，第n存储阵列中的故障存储单元被所述冗余阵列替换时，在1≤i<n的范围内，第i选择电路输出从第i存储阵列读取的数据，在n≤i≤N-1的范围内，第i选择电路输出从第i+1存储阵列读出的数据，n为正整数；当所述第N存储阵列中的故障存储单元被所述冗余阵列替换时，所述第i选择电路输出从所述第i存储阵列读取的数据。
在一些实施例中，所述第N存储阵列为所述冗余阵列。
在一些实施例中，第n存储阵列中的故障存储单元被所述冗余阵列替换时，在1≤i<n的范围内，第i选择电路输出从第i存储阵列读取的数据，在n≤i≤N-1的范围内，第i选择电路输出从第i+1存储阵列读出的数据，n为正整数；当所述第1存储阵列中的故障存储单元被所述冗余阵列替换时，所述第i选择电路输出从所述第i+1存储阵列读取的数据。
在一些实施例中，第m存储阵列为所述冗余阵列，1<m<N且m为正整数。
在一些实施例中，第n存储阵列中的故障存储单元被所述冗余阵列替换时，在1≤i≤n-1的范围内，所述第i选择电路输出从所述第i存储阵列读出的数据，在n≤i≤N-1的范围内，所述第i选择电路输出从所述第i+1存储阵列读出的数据，n<m且n为正整数；第k存储阵列中的故障存储单元被所述冗余阵列替换时，在1≤i<k的范围内，所述第i选择电路输出从所述第i存储阵列读出的数据，在k≤i≤N-1的范围内，所述第i选择电路输出从所述第i+1存储阵列读出的数据，m<k且k为正整数。
在一些实施例中，所述冗余阵列的数量为多个且所述冗余阵列不相邻。
在一些实施例中，至少一个所述主存储阵列为校验码存储阵列，所述校验码存储阵列存储有校验码数据。
在一些实施例中，所述存储器还包括：校验模块；所述校验模块与所述N-1个选择电路连接，所述N-1个选择电路输出的数据包括待校验数据和校验码数据，所述校验模块用于根据所述校验码数据对所述待校验数据进行数据校验。
本公开实施例提供的存储器，包括依次排列的N个存储阵列，其中包含至少一个主存储阵列和至少一个冗余阵列，冗余阵列用于替换主存储阵列的故障单元，以及N-1个选择电路，每个选择电路接收从位序对应的存储阵列以及下一存储阵列读出的数据，每个选择电路响应于自身的选择信号，通过选择输出相应的数据，实现故障存储单元替换后的数据读取。本方案的存储器通过设置多个选择电路，根据存储器的故障单元替换情况，控制选择电路输出相应的数据，从而实现故障存储单元替换后的数据读出，保证数据处理的准确性和可靠性。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开实施例的原理。
图1为一实施例示出的存储器的架构示例图；
图2为一实施例示出的存储单元的结构示例图；
图3和图4分别为一种示例的替换方案架构图；
图5为一实施例提供的存储器的结构示例图；
图6和图7为不同情形下的状态示例图；
图8为存储阵列的架构示例图；
图9为一示例的存储器的结构示例图；
图10-图12为不同情形下的状态示例图；
图13为一示例的存储器的结构示例图；
图14-图16为不同情形下的状态示例图；
图17为一示例的存储器的结构示例图；
图18和图19为不同情形下的状态示例图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
本公开中的用语“包括”和“具有”用以表示开放式的包括在内的意思，并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记或区分使用，不是对其对象的先后顺序或数量限制。此外，附图中的不同元件和区域只是示意性示出，因此不限于附图中示出的尺寸或距离。
下面以具体的实施例对技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本公开的实施例进行描述。
图1为一实施例示出的存储器的架构示例图，如图1所示，以DRAM作为示例，包括数据输入/输出缓冲、行解码器、列解码器、感测放大器以及存储阵列。其中，数据输入/输出缓冲属于外围区电路，感测放大器、行解码器、列解码器以及存储阵列属于阵列区电路。存储阵列主要由字线、位线和存储单元 组成。存储阵列中的字线沿行方向延伸，存储阵列中的位线沿列方向延伸，字线与位线的交叉处为存储阵列的存储单元。
其中，每个存储单元用于存储一个位(bit)的数据。如图2所示，图2为一实施例示出的存储单元的结构示例图，存储单元主要由晶体管开关M和电容C组成。其中，电容用于存储数据，晶体管开关用于根据选中状态，关断或导通。
可以通过控制字线和位线来激活某个存储单元，以实现对该存储单元的访问。结合读取场景作为示例：需要读取存储单元中的数据时，可以通过行解码器选中该存储单元所在行的字线，相应的，图示中的晶体管M导通，通过对位线信号的感测放大就可以感知到此时电容C上的状态。例如，如果存储单元中存储的bit数据为1，那么晶体管M导通后就会从存储单元的位线上读到1，反之也是同样的道理。另外，结合写入场景作为示例：需要向某存储单元中写入bit数据时，比如写入1。可以通过行解码器选中该存储单元所在行的字线，相应的图示中的晶体管M导通，通过将位线的逻辑电平设为1，使得电容C充电，即向存储单元写入1。反之，如果要写入0，那么位线的逻辑电平设为0，使得电容C放电，即向存储单元写入0。
实际应用中，DRAM在生产过程中有一定概率会产生故障的存储单元，或者，伴随着设备的老化损坏，尤其是运行环境存在挑战(高温环境)，并且需要频繁运行的存储器，在存储阵列中可能产生故障存储单元。这些故障存储单元不能正常工作，因此为了避免故障存储单元影响存储器的正常工作，在设计时除了规划包含常规存储单元的主存储阵列以外，还会规划冗余阵列，冗余阵列中的存储单元作为冗余部分，用于实现对主存储阵列中故障存储单元的替换。
本文中的“替换”指存储功能上的替换，即保证替换后能正常用于存储数据的存储单元的数量即可，具体的替换方式包括但不限于，用冗余存储单元存储故障存储单元原本需要存储的bit数据，或者，只需保证加入冗余存储单元后，能够正常工作的存储单元的数量可以保证完整数据的储存即可，至于哪个存储单元存储哪个bit数据则不做限制。
在一些替换方案中，比如LCR(Local Column Repair)方案，会在存储阵列中设计包含常规存储单元的存储列，以及包含冗余存储单元的冗余列，冗余列和存储列共享该存储阵列的数据线，数据线用于传输读取或写入的数据。为了进一步便于设计，在一些替换方案里，比如CCR(Central Column Repair)方案中，所有冗余存储单元设置在独立的冗余阵列中，冗余阵列和常规的存储阵列分别独立设置，各自具有独立的数据线，故需要提供一种有效方案支持该架构下，发生故障替换时的数据处理，比如，数据的正常读取。
为便于理解，如图3和图4所示，图3和图4分别为一种示例的替换方案架构图，以存储器包括N个存储阵列作为示例，分别为第1存储阵列、第2存储阵列，…第N存储阵列。图3采用的故障替换方案为LCR方案，图中填充阴影的列为冗余列，未填充阴影的部分为常规的存储列，可知LCR方案中，各冗余列集成于每个存储阵列中，每个存储阵列下的存储列和冗余列共享数据线。图4采用的故障替换方 案为CCR方案，图中填充阴影的阵列为冗余阵列，未填充阴影的部分为常规的主存储阵列，可知CCR方案中，独立设置冗余阵列，冗余阵列中的存储单元用于替换主存储阵列中故障的存储单元，每个阵列配置有独立的数据线。需要说明的是，图中只是一种示例，具体的阵列架构可以根据实际需要调整，而不限于图中的示例。
本公开实施例的一些方面涉及上述考虑。以下结合本公开的一些实施例对方案进行示例介绍。图5为一实施例提供的存储器的结构示例图，如图5所示，该存储器包括：
依次排列的N个存储阵列11，N个存储阵列分别记为第1存储阵列，第2存储阵列，…，第i存储阵列，…，第N存储阵列，其中至少一个存储阵列为冗余阵列，且至少一个存储阵列为主存储阵列，冗余阵列用于替换主存储阵列中的故障存储单元，1≤i<N，且i和N为正整数；
N-1个选择电路12，分别记为第1选择电路，第2选择电路，…，第i选择电路，…，第N-1选择电路；其中，第i选择电路接收从第i存储阵列和第i+1存储阵列读出的数据，且第i选择电路用于根据第i选择信号输出从第i存储阵列读出的数据或从第i+1存储阵列读出的数据。
如图5中，从存储阵列11读出的数据记为Data，其中从第i存储阵列读出的数据记为Data_i，Data_i可能是从主存储阵列读取的数据，也可能是从冗余阵列读取的数据Data_Red，具体可以视第i存储阵列的类型确定。实际应用中，本实施例的存储器包括但不限于双倍速率同步动态随机存储器(简称DDR)等。
其中，存储阵列中的主存储阵列用于在未存在故障存储单元的情况下存储数据。实际应用中，为了验证数据读取的准确性，可以对读取的数据进行数据校验。故在一个示例中，至少一个主存储阵列为校验码存储阵列，校验码存储阵列存储有校验码数据。即从存储阵列中读出的数据将包含待校验数据Data_CP，以及校验码数据Data_ECC。其中，校验码存储阵列存储有校验码数据可解释为，校验码存储阵列在不存在故障存储单元时，正常存储校验码数据，可以理解，如果校验码存储阵列中存在故障存储单元，也可用冗余阵列对校验码存储阵列中的故障存储单元进行替换，相应的，故障存储单元对应的校验码数据将被存储在进行替换之后的某个存储单元中。
实际应用中，在数据读取和传输的过程中可能产生错误，故为了避免和及时发现这种错误，可以采用数据校验方法对读取出的数据进行校验。作为示例，数据校验方法可以包括但不限于奇偶校验、循环冗余校验等，在校验方案中，需要基于校验码数据进行校验，故在向存储阵列中写入数据时，会一并生成并写入校验码数据，以便在数据读取时，根据读出的校验码数据对读出的存储数据进行数据校验。相应的，在一个示例中，存储器还包括：校验模块13；校验模块13与N-1个选择电路12连接，N-1个选择电路12输出的数据包括待校验数据和校验码数据，校验模块13用于根据校验码数据对待校验数据进行数据校验。本示例通过设置校验码模块，能够对读取的数据进行数据校验，从而进一步提高数据处理的准确性和可靠性。
下面结合附图，对本实施例的电路工作原理进行示例：以一次读取的完整数据为34组数据进行举例， 记为Data_1～Data_34。实际应用中，一次读取的数据长度和内容可以根据存储器的类型和工作参数确定。其中，Data_1表示完整的34组数据中，在正常情况下应存储在第1个主存储阵列中的数据，第1数据表示实际从第1存储阵列中读出的数据；Data_2表示完整的34组数据中，正常情况下应存储在第2个主存储阵列中的数据，第2数据表示实际从第2个存储阵列中读出的数据；以此类推。另外，记Data_Red表示存储在冗余阵列中的数据，可以理解，当第i存储阵列为冗余阵列时，第i数据即Data_Red数据。具体的，冗余阵列中的数据具体为替换故障存储单元后存储的数据，该数据可能是34组数据中的其中一组，具体为哪组数据可根据实际情况确定，后述会进行举例说明。
首先，图6为一种情形下的状态示例图，该情形为主存储阵列中未存在故障存储单元。当主存储阵列中没有故障存储单元时，完整的34组数据应存储在对应的主存储阵列中。结合图中的示例，假设存储器包含35个存储阵列，即N＝35，其中冗余阵列为第18存储阵列，其余的第1存储阵列至第17存储阵列以及第19存储阵列至第35存储阵列均为主存储阵列。具体的，完整数据中的Data_1(第1数据)存储于第1存储阵列(第1个主存储阵列)，Data_2(第2数据)存储于第2存储阵列(第2个主存储阵列)，以此类推，直至Data_17(第17数据)存储于第17存储阵列(第17个主存储阵列)，之后第18存储阵列为冗余阵列，第18存储阵列用于替换主存储阵列，由于存储器无故障存储单元，冗余阵列不存储数据，因此不从第18存储阵列读出第18数据，再之后与前17个存储阵列类似，Data_18(第19数据)存储于第19存储阵列(第18个主存储阵列)，Data_19(第20数据)存储于第20存储阵列(第19个主存储阵列)，以此类推，直至Data_34(第35数据)存储于第35存储阵列(第34个主存储阵列)。
相应的，第i选择电路接收从第i存储阵列读出的数据(第i数据)以及从第i+1存储阵列读出的数据(第i+1数据)。结合图6所示，第1选择电路接收第1数据和第2数据，此时，第1数据为从第1存储阵列读出的Data_1，第2数据为第2存储阵列读出的Data_2，…第17选择电路接收第17数据和第18数据，第18选择电路接收第18数据和第19数据，此时，第17数据为从第17存储阵列读出的Data_17，第19数据为从第19存储阵列读出的Data_18，由于存储器无故障存储单元，冗余阵列不存储数据，因此不从第18存储阵列读出第18数据，…第34选择电路接收第34数据和第35数据，此时，第34数据为从第34存储阵列读出的Data_33，第35数据为从第35存储阵列读出的Data_34。基于上述情形，N-1个选择电路中，在1≤i≤17的范围内，第i选择电路选择输出第i数据，在18≤i≤34的范围内，第i选择电路选择输出第i+1数据，从而实现N-1个选择电路输出的数据构成完整数据Data_1～Data_34。
以上为不存在故障存储单元的情形。作为示例，图7为另一种情形下的状态示例图，该情形为主存储阵列中存在故障存储单元。仍结合图6所示的架构，以第1存储阵列存在故障存储单元为例，在图7中，冗余阵列(第18存储阵列)用于替换第1存储阵列中的故障存储单元。在一个示例中，原本存储在第1存储阵列的Data_1被转移至第2存储阵列，原本存储在第2存储阵列的Data_2被存储至第3存储阵列，直至原本存储在第17存储阵列中Data_17被存储至冗余阵列(第18存储阵列中)，实现对第一存储阵列中故障存储单元的替换。此时，第1存储阵列中可以不存储储据，或者存储数据但不读出该数据， 故从第1存储阵列读出的第1数据为空或者为无需从第1存储阵列读出数据，从第2存储阵列读出的第2数据为Data_1，…第17存储阵列读出的第17数据为Data_16，第18存储阵列(冗余阵列)读出的第18数据(Data_Red)为Data_17，第19数据至第35数据的状态则与图6所示的状态类似。
结合图7所示，相应的，第1选择电路接收第1数据和第2数据，即空数据和Data_1，…第2选择电路接收第2数据和第3数，即Data_1和Data_2，…第17选择电路接收第17数据和第18数据，即Data_16和Data_Red(此时为Data_Red为Data_17)，…第18选择电路接收第18数据和第19数据，即Data_Red(此时为Data_17)和Data_18，…第34选择电路接收第34数据和第35数据，即Data_33和Data_34。基于上述情形，控制各选择单元根据各自的选择信号选择输出从第i存储阵列或者从第i+1存储阵列读出的数据，以输出完整数据。作为示例，N-1个选择电路中，在1≤i≤17的范围内，第i选择电路选择输出第i+1数据，在18≤i≤34的范围内，第i选择电路同样选择输出第i+1数据，从而实现N-1个选择电路输出的数据构成完整数据Data_1～Data_34。
本实施例中，针对N个存储阵列设置N-1个选择电路，能够在无论是否发生故障存储单元替换的情形下，通过控制选择电路选择输出相应的数据，来实现完整数据的准确输出，保证数据处理的准确性和可靠性。并且本实施例的方案，便于电路设计和制备，可以适用于存储器等集成度高的场景。
其中，选择电路12的具体实现电路可以根据实际情况设计。作为示例，图8为存储阵列的架构示例图，如图8所示，主存储阵列和所述冗余阵列均包括多个列，例如M个列，分别记为第1列，第2列，…，第j列，…，第M列。
具体的，冗余阵列的第j列用于替换所述主存储阵列的第j列，其中1≤j≤M，且j和M为正整数。需要说明的是，这里的单个“列”指单个列选择信号的控制对象。举例来说，存储阵列在物理结构上包括多个物理行(例如理解为字线wordline)和多个物理列(例如理解为位线bitline)。在一些存储器设计方案中，将一个存储阵列中的多个物理列划分为多组列，每组列中的所有物理列受控于同一个列选择信号，不同组的列受控的列选择信号不同。举例来说，假设某存储阵列包含16个物理列，按照每4个物理列进行划分，将得到4列(column_1～column_4)，column_1～column_4分别对应列选择信号1～列选择信号4，每个column中的4个物理列对应同一列选择信号，每个column可视为本示例所述的一个“列”。需要说明的是，在多个存储阵列的情形下，同一列选择信号用于选中不同存储阵列中的相同列，这里的相同列指在不同存储阵列中位置相同的列，比如列选择信号1用于选中所有存储阵列中的column_1。在另一些存储器设计方案中，本示例中的单个“列”即单个物理列，比如，某存储阵列包含8个物理列，分别受控于8个列选择信号，则此时的每一物理列可视为本示例所述的一个“列”。本实施例在此不对此进行限制。
以匹配前一种设计方案作为示例，在一个示例中，选择电路12包括：多个子选择电路121，第i选择电路的每一子选择电路分别接收从第i存储阵列和第i+1存储阵列的读出的1bit数据。
结合图8所示，结合第一种设计方案，存储器的数据读取过程示例如下：如图8所示，示出了多个 存储阵列11，每个存储阵列11包括多个列21，图中以其中一个存储阵列的放大图作为示例，每个列21进一步由多个物理列(比如4bit)构成。当进行数据读取时，列解码器会从读取指令中解析出列选择信号，比如，列选择信号表征第1列的地址。响应于该列选择信号，多个存储阵列11的第1列被选中，结合前述图6的示例，第i数据包括从第i存储阵列的第1列读出的4bit数据，即第1数据包括从第1存储阵列的第1列读出的4bit数据，第2数据包括从第2存储阵列的第1列读出的4bit数据，以此类推。故第i选择电路对应包括4个子选择电路，分别对应4bit数据中的1bit数据，第i选择电路中的每一子选择电路接收从第i存储阵列的被当前列选择信号选中的列读出的4bit数据中的1个bit，以及从第i+1存储阵列的该列选择信号选中的列读出的4bit数据中的1个bit。其中，该列选择信号在不同存储阵列选中的列的位置相同，这里子选择电路接收的两个bit来自存储阵列的物理列，分布在不同的两个存储阵列的位置相同的列，且在各自列中的位置相同。比如，假设列选择信号为第1列的地址，则第1选择电路的第1子选择电路接收的两个bit数据，分别来自第1存储阵列的第1列读出的4bit中的第1个bit，以及第2存储阵列的第1列读出的4bit中的第1个bit。
故可以理解，实际应用中，选择电路可以包括一个或多个子选择电路，同一选择电路中子选择电路选择信号相同。故在一个示例中，同一选择电路中的子选择电路可以共享一个选择信号，不同选择电路接收各自独立的选择信号。
结合前述，子选择电路用于响应于选择信号从接收的数据中选择一个数据输出。实际应用中，子选择电路的实现方式不限，在一个示例中，子选择电路包括数据选择器，所述数据选择器的第一数据输入端接收从所述第i存储阵列读出的数据，所述数据选择器的第二数据输入端接收从所述第i+1存储阵列读出的数据，所述数据选择器的选择端接收所述第i选择信号。本示例中，子选择电路包括数据选择器，从而实现根据选择信号选择输出相应的数据，并且通过常规器件实现子选择电路，能够简化电路结构，降低成本。
本示例中，数据选择器如何根据选择信号的电平高低来输出数据可以根据实际需求设置，例如可以设置为当选择信号为高电平的时候，数据选择器的输出端输出第一输入端接收的数据，选择信号为低电平的时候，数据选择器的输出端输出第二输入端接收的数据，从而实现根据选择信号选择输出相应的数据，并且通过常规器件实现子选择电路，能够简化电路结构，降低成本。
在一个示例中，第i选择电路中的子选择电路可以包括一个第一开关管和一个第二开关管，第一开关管的第一端接收从第i存储阵列读出的1bit数据，第二开关管的第一端接收从第i+1存储阵列读出的1bit数据，第一开关管的第二端和第二开关管的第二端作为子选择电路的输出端，其中第一开关管或第二开关管的其中一个根据第i选择信号闭合，另一个根据第i选择信号断开，从而实现根据选择信号选择输出相应的数据，并且通过常规器件实现子选择电路，能够简化电路结构，降低成本。
实际应用中，各存储阵列的排布可以根据需要设计。作为示例，冗余阵列的数量可以为一个或者多个。以冗余阵列的数量为一个作为示例，冗余阵列的排布情形也有多种。比如，冗余阵列可以位于整个 存储阵列的边缘，例如第1存储阵列或者第N存储阵列为冗余阵列。再比如，冗余阵列可以位于存储阵列之间，例如，第m存储阵列为冗余阵列，1<m<N且m为正整数。
在一个示例中，冗余阵列的数量为一个。具体的，单个冗余阵列中的每列可以用于替换任一主存储阵列中位置相同的列，比如，冗余阵列中的第1列可以用于替换任意一个主存储阵列的第1列，该冗余阵列中的第2列可以用于替换任意一个主存储阵列的第2列。或者，当某一主存储阵列的两个列都存在故障存储单元时，也可用冗余阵列中位置相同的两个列进行替换。通过设置冗余阵列能够实现故障存储单元的替换。
结合一个冗余阵列的不同位置，作为上述示例的一种可能的方式，图9为一示例的存储器的结构示例图，如图9所示，第1存储阵列为冗余阵列。也就是说，冗余阵列设置在首个存储阵列。如图9所示，图中填充阴影的存储阵列为冗余阵列，未填充阴影的存储阵列为主存储阵列。
下面结合附图，对冗余阵列为第1存储阵列时的电路工作原理进行示例：仍以一次读取的完整数据为34组数据进行举例。图10为一种情形下的状态示例图，该情形为主存储阵列中未存在故障存储单元。第1存储阵列为冗余阵列，第2～35存储阵列均为主存储阵列。第1存储阵列为冗余阵列，故从第1存储阵列读出的数据(第1数据)为Data_Red，Data_1～Data_34依次分别存储于第2～35存储阵列(34个主存储阵列)。相应的，结合图9所示，第1选择电路接收从第1存储阵列和第2存储阵列读出的数据，即Data_Red和Data_1，第2选择电路接收从第2存储阵列和第3存储阵列读出的数据，即Data_1和Data_2，...以此类推，直至第34选择电路接收从第34存储阵列和第35存储阵列读出的数据，即Data_33和Data_34。基于上述情形，N-1个选择电路中，第i选择电路输出从第i+1存储阵列读出的数据，从而实现N-1个选择电路输出的数据构成完整数据Data_1～Data_34。
图11为另一种情形下的状态示例图，该情形为主存储阵列中存在故障存储单元。具体的，第n存储阵列中的故障存储单元被冗余阵列替换时，在1≤i<n的范围内，第i选择电路输出从第i存储阵列读取的数据，在n≤i≤N-1的范围内，第i选择电路输出从第i+1存储阵列读出的数据，n为正整数。
结合图11举例来说，某个主存储阵列存在故障存储单元，且该主存储阵列并非最后一个存储阵列，比如，假设图11中第17存储阵列存在故障存储单元，即n＝17为例，结合图中的示例，采用预定方案执行故障存储单元替换后，第17存储阵列不存储数据，原本存储在第17存储阵列的Data_16被存储至第16存储阵列，原本存储在第16存储阵列的Data_15被存储至第15存储阵列，...以此类推，直至原本存储在第2存储阵列的Data_1被存储至第1存储阵列(冗余阵列)，从而实现故障单元替换，而原本存储在第18存储阵列的Data_17仍被存储至第18存储阵列，原本存储在第19存储阵列的Data_18仍被存储至第19存储阵列，...以此类推，原本存储在第35存储阵列的Data_34仍被存储至第35存储阵列。相应的，为了准确读出数据，在1≤i<17的范围内，第i选择电路输出从第i存储阵列读取的数据，即第1～16选择电路输出从第1～16存储阵列读出的数据，即输出Data_1～Data_16；在17≤i≤34的范围内，第i选择电路输出从第i+1存储阵列读出的数据，即第17～34选择电路输出从第18～35存储阵读出的数据，即 Data_17～Data_34，从而实现N-1个选择电路输出的数据构成完整数据，实现数据的准确读出。
再具体的，当第N存储阵列中的故障存储单元被冗余阵列替换时，第i选择电路输出从第i存储阵列读取的数据。即在冗余阵列为首个存储阵列，存在故障被替换的存储阵列为最后一个存储阵列时，所有选择电路均选择输出从第i存储阵列读取的数据。结合图12举例来说，某个主存储阵列存在故障存储单元，且该主存储阵列为最后一个存储阵列，比如，图12中第35存储阵列存在故障存储单元，结合图10的示例，采用预定方案执行故障存储单元替换后，第35存储阵列不存储数据，原本存储在第35存储阵列的Data_34被存储至第34存储阵列，原本存储在第34存储阵列的Data_33被存储至第33存储阵列，...以此类推，原本存储在第2存储阵列的Data_1被存储至第1存储阵列(冗余阵列)，从而实现故障单元替换。相应的，为了准确读出数据，在1≤i≤34的范围内，第i选择电路输出从第i存储阵列读取的数据，即第1～34选择电路分别输出从第1～34存储阵列读出的数据，即输出Data_1～Data_34，从而实现N-1个选择电路输出的数据构成完整数据，实现数据的准确读出。
仍结合一个冗余阵列的不同位置，作为上述示例的一种可能的方式，图13为一示例的存储器的结构示例图，如图13所示，第N存储阵列为冗余阵列。也就是说，冗余阵列设置在最后一个存储阵列。图中填充阴影的存储阵列为冗余阵列，未填充阴影的存储阵列为主存储阵列。
下面结合附图，对冗余阵列为第N存储阵列时的电路工作原理进行示例：仍以一次读取的完整数据为34组数据进行举例。图14为一种情形下的状态示例图，该情形为主存储阵列中未存在故障存储单元。第35存储阵列为冗余阵列，第1～34存储阵列均为主存储阵列。第35存储阵列为冗余阵列，故从第35存储阵列读出的数据(第35数据)为Data_Red，Data_1～Data_34依次分别存储于第1～34存储阵列(34个主存储阵列)。相应的，结合图所示，第1选择电路接收从第1存储阵列和第2存储阵列读出的数据，即Data_1和Data_2，第2选择电路接收从第2存储阵列和第3存储阵列读出的数据，即Data_2和Data_3，...以此类推，直至第34选择电路接收从第34存储阵列和第35存储阵列读出的数据，即Data_34和Data_Red。基于上述情形，N-1个选择电路中，第i选择电路输出从第i存储阵列读出的数据，从而实现N-1个选择电路输出的数据构成完整数据Data_1～Data_34。
图15为另一种情形下的状态示例图，该情形为主存储阵列中存在故障存储单元。具体的，第n存储阵列中的故障存储单元被所述冗余阵列替换时，在1≤i<n的范围内，第i选择电路输出从第i存储阵列读取的数据，在n≤i≤N-1的范围内，第i选择电路输出从第i+1存储阵列读出的数据，n为正整数。
结合图15举例来说，假设某个主存储阵列存在故障存储单元，且该主存储阵列并非首个存储阵列，比如，假设图15中第17存储阵列存在故障存储单元，即n＝17为例，结合图14的示例，采用预定方案执行故障存储单元替换后，第17存储阵列不存储数据，原本存储在第17存储阵列的Data_17被存储至第18存储阵列，原本存储在第18存储阵列的Data_18被存储至第19存储阵列，...以此类推，原本存储在第34存储阵列的Data_34被存储至第35存储阵列(冗余阵列)，从而实现故障单元替换，而原本存储在第1存储阵列的Data_1仍被存储至第1存储阵列，原本存储在第2存储阵列的Data_2被存储至第2存储阵 列，...以此类推，原本存储在第16存储阵列的Data_16仍被存储至第16存储阵列。相应的，为了准确读出数据，在1≤i<17的范围内，第i选择电路输出从第i存储阵列读取的数据，即第1～16选择电路输出从第1～16存储阵列读出的数据，即输出Data_1～Data_16；在17≤i≤34的范围内，第i选择电路输出从第i+1存储阵列读出的数据，即第17～34选择电路分别输出从第18～35存储阵读出的数据，即Data_17～Data_34，从而实现N-1个选择电路输出的数据构成完整数据，实现数据的准确读出。
再具体的，当第1存储阵列中的故障存储单元被冗余阵列替换时，第i选择电路输出从第i+1存储阵列读取的数据。即在冗余阵列为最后一个存储阵列，存在故障被替换的存储阵列为首个存储阵列时，所有选择电路均选择输出从第i+1存储阵列读取的数据。结合图16举例来说，首个存储阵列存在故障存储单元，比如，图16中第1存储阵列存在故障存储单元，结合图15的示例，采用预定方案执行故障存储单元替换后，第1存储阵列不存储数据，原本存储在第1存储阵列的Data_1被存储至第2存储阵列，原本存储在第2存储阵列的Data_2被存储至第3存储阵列，...以此类推，原本存储在第34存储阵列的Data_34被存储至第35存储阵列(冗余阵列)，从而实现故障单元替换。相应的，为了准确读出数据，在1≤i≤34的范围内，第i选择电路输出从第i+1存储阵列读取的数据，即第1～34选择电路分别输出从第2～35存储阵列读出的数据，即输出Data_1～Data_34，从而实现N-1个选择电路输出的数据构成完整数据，实现数据的准确读出。
继续结合一个冗余阵列的不同位置，作为上述示例的一种可能的方式，图17为一示例的存储器的结构示例图，如图17所示，第m存储阵列为冗余阵列，1<m<N且m为正整数。也就是说，冗余阵列设置在并非首个或最后一个的存储阵列。
下面结合附图，对冗余阵列为第m存储阵列时的电路工作原理进行示例：仍以一次读取的完整数据为34组数据进行举例，可结合前述的图6进行示例。图6中示例的冗余阵列为第18存储阵列，即m＝18。当主存储阵列没有故障存储单元时的状态，如图6所示。
当主存储阵列中存在故障存储单元时，图18和图19分别为两种情形下的状态示例图。图18所示的情形为发生故障的存储阵列位于冗余阵列之前，即在一个示例中，第n存储阵列中的故障存储单元被冗余阵列替换时，在1≤i≤n-1的范围内，第i选择电路输出从第i存储阵列读出的数据，在n≤i≤N-1的范围内，第i选择电路输出从第i+1存储阵列读出的数据，n＜m且n为正整数。结合图18所示，假设发生故障的存储阵列为第1～17存储阵列中的某个存储阵列，比如，为第15存储阵列，即n＝15。在一个示例中，第15存储阵列不再存储数据，原本存储在第15存储阵列的Data_15被存储至第16存储阵列，原本存储在第16存储阵列的Data_16被存储至第17存储阵列，原本存储在第17存储阵列的Data_17被存储至第18存储阵列(冗余阵列)，完成故障替换。相应的，1≤i≤14的范围内，第i选择电路输出从第i存储阵列读出的数据，即第1～14选择电路分别输出从第1～14存储阵列读出的数据，即Data_1～Data_14；在15≤i≤34的范围内，第i选择电路输出从第i+1存储阵列读出的数据，即第15～34选择电路分别输出从第16～35存储阵列读出的数据，即Data_15～Data_34，从而实现N-1个选择电路输出的数据构成完整数 据，实现数据的准确读出。
图19所示的情形为发生故障的存储阵列位于冗余阵列之后，即在一个示例中，第k存储阵列中的故障存储单元被冗余阵列替换时，在1≤i＜k的范围内，第i选择电路输出从第i存储阵列读出的数据，在k≤i≤N-1的范围内，第i选择电路输出从第i+1存储阵列读出的数据，m＜k且k为正整数。结合图19所示，假设发生故障的存储阵列为第19～35存储阵列中的某个存储阵列，比如，为第21存储阵列，即k＝21。在一个示例中，第21存储阵列不再存储数据，原本存储在第21存储阵列的Data_20被存储至第20存储阵列，原本存储在第20存储阵列的Data_19被存储至第19存储阵列，原本存储在第19存储阵列的Data_18被存储至第18存储阵列(冗余阵列)，完成故障替换。相应的，1≤i＜21的范围内，第i选择电路输出从第i存储阵列读出的数据，即第1～20选择电路分别输出从第1～20存储阵列读出的数据，即Data_1～Data_20；在21≤i≤34的范围内，第i选择电路输出从第i+1存储阵列读出的数据，即第21～34选择电路分别输出从第22～35存储阵列读出的数据，即Data_21～Data_34，从而实现N-1个选择电路输出的数据构成完整数据，实现数据的准确读出。
上述示例结合冗余阵列的数量为一个的情况，针对冗余阵列设置在不同位置下，未存在和存在故障存储单元的不同情形进行了示例说明，可以理解，通过控制选择电路选择输出相应的数据，能够在不同示例的情形下均可实现数据的准确读取。
此外，在另一个示例中，冗余阵列的数量为多个且所述冗余阵列不相邻。具体的，当设置有多个冗余阵列时，可以支持对多个主存储阵列中位置相同的列同时故障时的替换。举例来说，假设第7存储阵列和第15存储阵列为冗余阵列，则可使用第7存储阵列中的冗余列替换第1存储阵列至第6存储阵列中的故障存储单元，使用第15存储阵列中的冗余列替换第16存储阵列至第35存储阵列中的故障存储单元。针对相邻两个冗余阵列之间的主存储阵列，比如，第8存储阵列至第14存储阵列，可以在设计时进行划分，例如，将第8存储阵列至第9存储阵列划分至第7存储阵列负责故障替换，将第10存储阵列至第14存储阵列划分至第15存储阵列负责故障替换。执行故障替换和选择电路的控制机制与前述方案类似。通过设置多个冗余阵列，可以支持多个主存储阵列中位置相同的列同时故障的场景，提高故障修复的可靠性。
本实施例提供的存储器，包括依次排列的N个存储阵列，其中包含至少一个主存储阵列和至少一个冗余阵列，冗余阵列用于提供主存储阵列的故障单元替换，以及N-1个选择电路，每个选择电路接收从位序对应的存储阵列以及下一存储阵列读出的数据，每个选择电路响应于自身的选择信号，通过选择输出相应的信号，实现故障替换场景下的数据处理。本方案的存储器通过设置多个选择电路，根据存储器的故障单元替换情况，控制选择电路输出相应的数据，从而实现故障替换下的数据处理，保证数据处理的准确性和可靠性。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一 般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (14)

  1. 一种存储器，包括：
    依次排列的N个存储阵列，所述N个存储阵列分别记为第1存储阵列，第2存储阵列，…，第i存储阵列，…，第N存储阵列，其中至少一个所述存储阵列为冗余阵列，且至少一个所述存储阵列为主存储阵列，所述冗余阵列用于替换所述主存储阵列中的故障存储单元，1≤i<N，且i和N为正整数；
    N-1个选择电路，分别记为第1选择电路，第2选择电路，…，第i选择电路，…，第N-1选择电路；其中，第i选择电路接收从所述第i存储阵列和第i+1存储阵列读出的数据，且所述第i选择电路用于根据第i选择信号输出从所述第i存储阵列读出的数据或从所述第i+1存储阵列读出的数据。
  2. 根据权利要求1所述的存储器，其中，所述主存储阵列和所述冗余阵列均包括M个列，分别记为第1列，第2列，…，第j列，…，第M列，所述冗余阵列的第j列用于替换任意一个所述主存储阵列的第j列，1≤j≤M，且j和M为正整数。
  3. 根据权利要求2所述的存储器，其中，所述选择电路包括：
    多个子选择电路，所述第i选择电路的每一所述子选择电路分别接收从所述第i存储阵列和第i+1存储阵列的读出的1bit数据。
  4. 根据权利要求3所述的存储器，其中，所述子选择电路包括数据选择器，所述数据选择器的第一数据输入端接收从所述第i存储阵列读出的数据，所述数据选择器的第二数据输入端接收从所述第i+1存储阵列读出的数据，所述数据选择器的选择端接收所述第i选择信号。
  5. 根据权利要求1所述的存储器，其中，所述冗余阵列的数量为一个。
  6. 根据权利要求5所述的存储器，其中，所述第1存储阵列为所述冗余阵列。
  7. 根据权利要求6所述的存储器，其中，第n存储阵列中的故障存储单元被所述冗余阵列替换时，在1≤i<n的范围内，第i选择电路输出从第i存储阵列读取的数据，在n≤i≤N-1的范围内，第i选择电路输出从第i+1存储阵列读出的数据，n为正整数；当所述第N存储阵列中的故障存储单元被所述冗余阵列替换时，所述第i选择电路输出从所述第i存储阵列读取的数据。
  8. 根据权利要求5所述的存储器，其中，所述第N存储阵列为所述冗余阵列。
  9. 根据权利要求8所述的存储器，其中，第n存储阵列中的故障存储单元被所述冗余阵列替换时，在1≤i<n的范围内，第i选择电路输出从第i存储阵列读取的数据，在n≤i≤N-1的范围内，第i选择电路输出从第i+1存储阵列读出的数据，n为正整数；
    当所述第1存储阵列中的故障存储单元被所述冗余阵列替换时，所述第i选择电路输出从所述第i+1存储阵列读取的数据。
  10. 根据权利要求5所述的存储器，其中，第m存储阵列为所述冗余阵列，1<m<N且m为正整数。
  11. 根据权利要求10所述的存储器，其中，第n存储阵列中的故障存储单元被所述冗余阵列替换时，在1≤i≤n-1的范围内，所述第i选择电路输出从所述第i存储阵列读出的数据，在n≤i≤N-1的范围内， 所述第i选择电路输出从所述第i+1存储阵列读出的数据，n<m且n为正整数；
    第k存储阵列中的故障存储单元被所述冗余阵列替换时，在1≤i<k的范围内，所述第i选择电路输出从所述第i存储阵列读出的数据，在k≤i≤N-1的范围内，所述第i选择电路输出从所述第i+1存储阵列读出的数据，m<k且k为正整数。
  12. 根据权利要求1所述的存储器，其中，所述冗余阵列的数量为多个且所述冗余阵列不相邻。
  13. 根据权利要求1-12任一项所述的存储器，其中，至少一个所述主存储阵列为校验码存储阵列，所述校验码存储阵列存储有校验码数据。
  14. 根据权利要求13所述的存储器，其中，所述存储器还包括：校验模块；
    所述校验模块与所述N-1个选择电路连接，所述N-1个选择电路输出的数据包括待校验数据和校验码数据，所述校验模块用于根据所述校验码数据对所述待校验数据进行数据校验。
PCT/CN2023/076108 2022-11-02 2023-02-15 存储器 WO2024093044A1 (zh)

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CN1487527A (zh) * 2002-09-13 2004-04-07 富士通株式会社 能够实现冗余单元阵列正确替换的半导体存储器
CN1744230A (zh) * 2004-08-30 2006-03-08 三星电子株式会社 具有支持多存储块的列冗余电路的半导体存储设备
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CN1459860A (zh) * 2002-05-22 2003-12-03 富士通株式会社 半导体器件
CN1487527A (zh) * 2002-09-13 2004-04-07 富士通株式会社 能够实现冗余单元阵列正确替换的半导体存储器
CN1744230A (zh) * 2004-08-30 2006-03-08 三星电子株式会社 具有支持多存储块的列冗余电路的半导体存储设备
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