WO2024092989A1 - 半导体衬底及其处理方法、太阳能电池及其制备方法 - Google Patents

半导体衬底及其处理方法、太阳能电池及其制备方法 Download PDF

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WO2024092989A1
WO2024092989A1 PCT/CN2022/141509 CN2022141509W WO2024092989A1 WO 2024092989 A1 WO2024092989 A1 WO 2024092989A1 CN 2022141509 W CN2022141509 W CN 2022141509W WO 2024092989 A1 WO2024092989 A1 WO 2024092989A1
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Prior art keywords
semiconductor substrate
area
surface area
layer
protective layer
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PCT/CN2022/141509
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English (en)
French (fr)
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周锡伟
张良
张景
赵泽
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安徽华晟新能源科技有限公司
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Priority to EP22958961.9A priority Critical patent/EP4394894A1/en
Publication of WO2024092989A1 publication Critical patent/WO2024092989A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1864—Annealing

Definitions

  • the present application relates to the technical field of solar cells, and in particular to a semiconductor substrate and a processing method thereof, a solar cell and a preparation method thereof.
  • a solar cell is a device that absorbs sunlight and converts solar radiation energy directly or indirectly into electrical energy through the photoelectric effect or photochemical effect.
  • Solar cells are a type of clean energy battery that is widely used in life and production.
  • One of the commonly used semiconductor substrates in solar cells is the silicon substrate.
  • a texturing process is usually performed on the surface of the silicon substrate to form a velvet surface, thereby increasing the light trapping capacity of the silicon substrate and improving the photoelectric conversion efficiency of the solar cell.
  • densely arranged pyramid structures will be formed on the surface of the silicon substrate. The height of these pyramid structures can usually reach 1 ⁇ m to 2 ⁇ m, causing the uniformity of other material layers formed in subsequent processes to deteriorate, resulting in a decrease in the open circuit voltage of the solar cell; in addition, the contact between the material layers will also deteriorate, limiting the transmission of carriers and increasing the series resistance, thereby reducing the photoelectric conversion performance of solar energy.
  • the technical problem to be solved by the present application is to overcome the problem of low photoelectric conversion efficiency of solar cells in the prior art, thereby providing a semiconductor substrate and a processing method thereof, a solar cell and a preparation method thereof.
  • the first aspect of the present application provides a method for processing a semiconductor substrate, comprising: forming a smooth surface area and a velvet surface area adjacent to the smooth surface area on at least one side of the semiconductor substrate; the area of the smooth surface area is greater than or equal to the area of the velvet surface area.
  • the ratio of the area of the smooth surface area to the area of the velvet surface area is 1:1 to 1.2:1.
  • the steps of forming a smooth surface area and a velvet area adjacent to the smooth surface area on any side of the semiconductor substrate include: forming a protective layer on the surface of any side of the semiconductor substrate; setting a patterned cover layer on the surface of the protective layer facing away from the semiconductor substrate, the cover layer having a hollow area, the protective layer including a first area located at the bottom of the hollow area and a second area blocked by the cover layer; using the cover layer to thicken the first area of the protective layer; after the first area of the protective layer is thickened, removing the cover layer; using the first area of the protective layer after removing the cover layer as protection, etching to remove the second area of the protective layer; velveting the side of the semiconductor substrate exposed by the protective layer after removing the second area of the protective layer, so that the velvet area is formed on the side of the semiconductor substrate exposed by the protective layer; after the velvet area is formed, etching to remove the first area corresponding to the protective layer, so that a smooth surface area is formed on a portion of the surface of one side
  • the hollow area includes at least a plurality of strip-shaped openings that are spaced apart from each other, and the strip-shaped openings are parallel to each other.
  • the step of forming a protective layer on any side of the semiconductor substrate includes: coating the entire surface of a base film on any side of the semiconductor substrate; performing diffusion annealing on the base film so that the base film and one side surface of the semiconductor substrate react to form a protective layer with doped ions, so that impurities inside the semiconductor substrate migrate into the protective layer.
  • the step of thickening the first area of the protective layer includes: using the cover layer as a mask to coat a top film on the surface of the first area; performing diffusion annealing on the top film to make the top film become a part of the protective layer, thereby increasing the thickness of the first area.
  • the cover plate layer comprises quartz material.
  • the bottom film and the top film are liquid source films.
  • the bottom membrane and the top membrane are phosphorus-containing liquid source membranes, and the phosphorus concentration of the top membrane is greater than that of the bottom membrane.
  • the diffusion annealing time for the top film is greater than the diffusion annealing time for the bottom film.
  • the temperature at which the top film is subjected to the diffusion annealing treatment is greater than the temperature at which the bottom film is subjected to the diffusion annealing treatment.
  • the parameters include: the etching solution used is a mixture of hydrofluoric acid aqueous solution, hydrochloric acid aqueous solution and water solvent, the mass concentration of the hydrofluoric acid aqueous solution is 35% to 50%, the mass concentration of the hydrochloric acid aqueous solution is 30% to 50%, the volume proportion of the hydrofluoric acid aqueous solution is 1% to 4%, the volume proportion of the hydrochloric acid aqueous solution is 1% to 3%, and the etching time is 100s to 300s.
  • the etching solution used is a mixture of hydrofluoric acid aqueous solution, hydrochloric acid aqueous solution and water solvent
  • the mass concentration of the hydrofluoric acid aqueous solution is 35% to 50%
  • the mass concentration of the hydrochloric acid aqueous solution is 30% to 50%
  • the volume proportion of the hydrofluoric acid aqueous solution is 1% to 4%
  • a second aspect of the present application provides a semiconductor substrate, wherein at least one side of the semiconductor substrate has a smooth surface area and a velvet surface area adjacent to the smooth surface area, and an area of the smooth surface area is greater than or equal to an area of the velvet surface area.
  • the ratio of the area of the smooth surface area to the area of the velvet surface area is 1:1 to 1.2:1.
  • the third aspect of the present application provides a method for preparing a solar cell, comprising: providing a semiconductor substrate; processing the semiconductor substrate using the aforementioned semiconductor substrate processing method so that at least one side of the semiconductor substrate has a glossy area and a velvet area adjacent to the glossy area; forming a transparent conductive film on a side of the semiconductor substrate having the glossy area and the velvet area, the transparent conductive film being located in and only located in the glossy area; and forming a gate line in at least a portion of the area on a side of the transparent conductive film that is away from the semiconductor substrate.
  • the method for preparing a solar cell further includes: before forming the transparent conductive film, forming a doped semiconductor layer on a side of the semiconductor substrate having the smooth surface area and the velvet surface area; the doped semiconductor layer is located between the semiconductor substrate and the transparent conductive film.
  • an intrinsic semiconductor layer is formed on the side of the semiconductor substrate having the smooth surface area and the textured surface area; the intrinsic semiconductor layer is located between the semiconductor substrate and the doped semiconductor layer.
  • the fourth aspect of the present application provides a solar cell, comprising: a semiconductor substrate, at least one side of the semiconductor substrate having a smooth surface area and a velvet surface area adjacent to the smooth surface area, the area of the smooth surface area being greater than or equal to the area of the velvet surface area; a transparent conductive film, located on a side of the semiconductor substrate having the smooth surface area and the velvet surface area, and only located on the smooth surface area; a gate line, located on at least a portion of the area on a side of the transparent conductive film facing away from the semiconductor substrate.
  • the solar cell further includes: a doped semiconductor layer located between the semiconductor substrate and the transparent conductive film.
  • the solar cell further includes: an intrinsic semiconductor layer located between the semiconductor substrate and the doped semiconductor layer.
  • the present application processes a semiconductor substrate so that at least one side of the surface of the semiconductor substrate includes a glossy area and a velvet area adjacent to the glossy area, wherein the velvet area can provide excellent light trapping effect, and the surface of the glossy area is smooth, which is conducive to the uniform deposition of other material layers in this area, thereby obtaining better uniformity of the material film layer, which is conducive to improving the photoelectric conversion efficiency and enhancing the battery efficiency.
  • the present application forms a protective layer on the surface of the semiconductor substrate, and the impurity ions in the semiconductor substrate can be migrated into the protective layer through diffusion annealing, which helps to reduce the defects in the semiconductor substrate.
  • the first area of the protective layer is thickened by using a cover layer, and the impurity ions of the semiconductor substrate can continue to diffuse into the first area of the protective layer, which helps to further reduce the defects in the area corresponding to the semiconductor substrate and the first area of the protective layer.
  • the first area of the protective layer can protect the corresponding area of the semiconductor substrate from being etched, and then the first area of the protective layer is etched away, and the area corresponding to the semiconductor substrate and the first area of the protective layer forms a smooth area with a flat surface, and the impurity ion concentration in the smooth area of the semiconductor substrate is low, so the defect density of the semiconductor substrate is low.
  • the cover layer used in this application is made of high-temperature resistant quartz material, which is low-cost and can be reused after cleaning; in addition, the cover layer can protect the semiconductor substrate during the diffusion annealing process and reduce the risk of fragmentation.
  • the solar cell provided by the present application has transparent conductive film and grid lines located only in the light surface area. Since the surface of the light surface area is smooth, it is conducive to the uniform deposition of the transparent conductive film and grid lines in the light surface area. The flat light surface area is conducive to the full contact between the transparent conductive film and the grid lines, thereby reducing the series resistance. The velvet surface area can provide excellent light trapping effect.
  • the solar cell provided by the present application can take into account both light trapping effect and low series resistance, which is conducive to improving the photoelectric conversion efficiency of the solar cell.
  • FIG. 1 is an exemplary flow chart of forming a smooth surface area and a velvet surface area on one side of a semiconductor substrate according to an embodiment of the present application;
  • FIGS. 2 to 10 are schematic diagrams of structures during the processing of a semiconductor substrate in an embodiment of the present application.
  • FIG11 is a schematic structural diagram of a cover plate layer according to an embodiment of the present application.
  • One or more embodiments of the present application provide a method for processing a semiconductor substrate, comprising: forming a smooth surface area and a velvet surface area adjacent to the smooth surface area on at least one side of the semiconductor substrate; the area of the smooth surface area is greater than or equal to the area of the velvet surface area.
  • the present application processes a semiconductor substrate so that at least one side surface of the semiconductor substrate includes a glossy area and a velvet area adjacent to the glossy area, wherein the velvet area can provide excellent light trapping effect, and the surface of the glossy area is smooth, which is conducive to the uniform deposition of other material layers in this area, and is conducive to improving the photoelectric conversion efficiency and enhancing the battery efficiency.
  • the ratio of the area of the glossy area to the area of the suede area is 1:1 to 1.2:1.
  • the ratio of the area of the glossy area to the area of the suede area is 1:1, 1.12:1, 1.15:1, 1.17:1 or 1.2:1.
  • the step of forming a smooth surface area and a velvet surface area adjacent to the smooth surface area on any one side of the semiconductor substrate comprises:
  • Step S100 forming a protective layer on any side of the semiconductor substrate
  • Step S200 a patterned cover layer is disposed on a surface of the protective layer away from the semiconductor substrate, wherein the cover layer has a hollow area, and the protective layer includes a first area located at the bottom of the hollow area and a second area blocked by the cover layer;
  • Step S300 after providing the patterned cover layer, thickening the first area of the protective layer;
  • Step S400 After thickening the first area of the protective layer, the cover layer is removed;
  • Step S500 after removing the cover layer, using the first area of the protective layer as protection to etch and remove the second area of the protective layer;
  • Step S600 after etching away the second region of the protection layer, texturing is performed on the side of the semiconductor substrate exposed by the protection layer, so that a textured region is formed on the side of the semiconductor substrate exposed by the protection layer;
  • Step S700 After the textured area is formed, the first area of the protection layer is removed by etching, so that a portion of the surface of one side of the semiconductor substrate forms a smooth area.
  • the present application forms a protective layer on the surface of the semiconductor substrate, so that the impurity ions in the semiconductor substrate can migrate to the protective layer, which helps to reduce the defects in the semiconductor substrate.
  • the first area of the protective layer is thickened by using a cover layer, and the impurity ions of the semiconductor substrate can continue to diffuse into the first area of the protective layer, which helps to further reduce the defects in the area corresponding to the semiconductor substrate and the first area of the protective layer.
  • the second area is subsequently etched away, at least part of the thickness of the first area of the protective layer can be retained.
  • the area corresponding to the semiconductor substrate and the second area of the protective layer forms a velvet area; the first area of the protective layer can protect the corresponding area of the semiconductor substrate from being etched. Afterwards, the first area of the protective layer is etched away, and the area corresponding to the semiconductor substrate and the first area of the protective layer forms a smooth area, and the impurity ion concentration in the smooth area of the semiconductor substrate is low, so the defect density of the semiconductor substrate is small.
  • the hollow region at least includes a plurality of strip-shaped openings spaced apart from each other and parallel to each other.
  • the hollow region can be used to prepare a main gate to form an electrode structure without a secondary gate.
  • the step of forming a protective layer on any side of a semiconductor substrate includes: coating an entire surface of a base film on any side of the semiconductor substrate; performing diffusion annealing on the base film so that the base film and one surface of the semiconductor substrate react to form a protective layer with doped ions, and impurities inside the semiconductor substrate migrate into the protective layer.
  • performing diffusion annealing on the bottom film can accelerate the diffusion of impurity ions in the semiconductor substrate into the protective layer and make the reaction more complete.
  • the step of thickening the first area of the protective layer includes: using the cover layer as a mask to coat a top film on the surface of the first area; and performing diffusion annealing on the top film to increase the thickness of the first area.
  • cover layer can limit the coating position and area of the top film, and a cover layer with different shapes and structures is used according to specific application scenarios.
  • the embodiments of the present application do not specifically limit the shape and structure of the cover layer.
  • the cover layer includes quartz material.
  • the embodiments of the present application are not specifically limited to this, as long as the cover layer does not melt or deform under high temperature conditions.
  • the bottom film and the top film are liquid source films. In other embodiments, the bottom film and the top film can also be formed by vapor deposition.
  • the bottom film and the top film are phosphorus-containing liquid source films, and the phosphorus concentration of the top film is greater than that of the bottom film.
  • the protective layer has a loose structure, and the top film can penetrate into the protective layer formed by the bottom film, thereby contacting with the surface of the semiconductor substrate for reaction; in addition, the phosphorus concentration of the top film is greater than the phosphorus concentration of the bottom film, which is conducive to the diffusion of the phosphorus element in the top film into the protective layer formed by the bottom film, so that the protective layer formed by the bottom film can continue to react with the semiconductor substrate.
  • the diffusion annealing process is performed on the top film for a longer time than the diffusion annealing process is performed on the bottom film.
  • the top film is diffusion annealed at a temperature greater than the bottom film.
  • the parameters include: the etching solution used is a mixture of hydrofluoric acid aqueous solution, hydrochloric acid aqueous solution and water solvent, the mass concentration of the hydrofluoric acid aqueous solution is 35% to 50%, the mass concentration of the hydrochloric acid aqueous solution is 30% to 50%, the volume proportion of the hydrofluoric acid aqueous solution is 1% to 4%, the volume proportion of the hydrochloric acid aqueous solution is 1% to 3%, and the etching time is 100s to 300s.
  • the step of forming a polished area and a velvet area adjacent to the polished area on at least one side of a semiconductor substrate includes: forming a first polished area and a first velvet area adjacent to the first polished area on one side of the semiconductor substrate, the area of the first polished area being greater than or equal to the area of the first velvet area; and/or forming a second polished area and a second velvet area adjacent to the second polished area on the other side of the semiconductor substrate, the area of the second polished area being greater than or equal to the area of the second velvet area.
  • the semiconductor substrate processing method of the present application is described in detail by taking the formation of the first polished area and the first velvet area on one side of the semiconductor substrate and the formation of the second polished area and the second velvet area on the other side as an example.
  • FIG. 2 shows an unprocessed semiconductor substrate 100 according to an embodiment of the present application.
  • the material of the semiconductor substrate 100 includes single crystal silicon. In other embodiments, the material of the semiconductor substrate is other semiconductor materials, such as germanium or silicon germanium. The material of the semiconductor substrate can also be other semiconductor materials.
  • the conductivity type of the semiconductor substrate 100 is N-type, and the semiconductor substrate is used to prepare a solar cell.
  • a first protective layer is formed on one side of a semiconductor substrate 100 .
  • a first bottom layer film is coated on the entire surface of one side of the semiconductor substrate 100; a first diffusion annealing treatment is performed to react the first bottom layer film with one side of the semiconductor substrate to form a first protective layer with doped ions, so that impurities inside the semiconductor substrate migrate into the first protective layer.
  • the first bottom layer film is a liquid source film.
  • the first bottom layer film is a phosphorus-containing liquid source film.
  • the first diffusion annealing treatment is a high temperature annealing process.
  • the semiconductor substrate 100 coated with the first bottom film is placed in an oven or a hot plate for baking treatment, so that the phosphorus in the first bottom film is fully diffused into the semiconductor substrate 100 and reacts with the impurities in the semiconductor substrate 100 to form a first protective layer 210 with a loose structure.
  • the baking treatment temperature is 650°C to 900°C, and the temperature is 650°C, 700°C, 800°C, 850°C or 900°C, and the baking treatment time is 120s to 1200s, and the time is 120s, 150s, 200s, 250s, 300s, 350s, 400s, 450s, 500s, 600s, 700s, 800s, 900s, 950s, 1000s, 1050s, 1100s, 1150s or 1200s.
  • a second protection layer is formed on the other side of the semiconductor substrate 100 .
  • a second bottom layer film is coated on the entire surface of the other side of the semiconductor substrate 100; a third diffusion annealing treatment is performed to react the second bottom layer film with the other side of the semiconductor substrate to form a second protective layer with doped ions, so that impurities inside the semiconductor substrate migrate into the second protective layer.
  • the second bottom layer film is a liquid source film, which is the same as or different from the first bottom layer film. In one embodiment, the second bottom layer film is the same as the first bottom layer film.
  • the third diffusion annealing treatment is a high temperature annealing treatment process. It is understandable that the process method and effect of the third diffusion annealing treatment are substantially the same as those of the first diffusion annealing treatment, and will not be described in detail here.
  • a patterned first cover layer is set on the surface of the first protective layer 210 facing away from the semiconductor substrate 100, and the first cover layer has a first hollow area with a plurality of parallel strip openings.
  • the first protective layer 210 includes a first area 310 located at the bottom of the first hollow area and a second area blocked by the first cover layer. After the patterned first cover layer is set, the first area 310 of the first protective layer 210 is thickened.
  • the first cover plate layer includes a first cover plate body 810 and a first hollow area 820.
  • the first hollow area 820 is a hollow structure of several strip-shaped openings uniformly distributed on the first cover plate body 810.
  • the first hollow area 820 may also have other shapes, for example: the first hollow area is a hollow structure of a network shape regularly arranged on the first cover plate body 810, which is suitable for forming a grid line electrode structure including a main grid and a secondary grid, wherein a plurality of main grids are parallel to each other, the main grid is arranged in parallel with the main grid, and the main grid and the secondary grid are arranged vertically or at any angle, and the width and height of the secondary grid are respectively smaller than the width and height of the main grid; in addition, the first hollow area may also be a hollow structure irregularly arranged or having different shapes on the first cover plate body 810, which is suitable for forming a grid line with a special pattern.
  • the shape and layout of the first hollow area 820 are consistent with the shape and layout of the grid line of the solar cell finally formed, and the cover plate layer with what kind of hollow structure is used is not limited here.
  • a first top film is coated on the surface of the first region 310; a second diffusion annealing process is performed to make the first top film become a part of the first protective layer 210, thereby increasing the thickness of the first region 310.
  • the first top film has the same components as the first bottom film. It should be noted that the phosphorus concentration of the first top film is greater than the phosphorus concentration of the first bottom film, so that the phosphorus of the first top film can fully penetrate the first protective layer 210 to react with impurities in the semiconductor substrate 100.
  • the first top film can directly penetrate into the surface of the semiconductor substrate 100 through the first region 310 of the first protective layer 210, and diffuse into the semiconductor substrate 100 to react with the impurities in the semiconductor substrate 100; in addition, the phosphorus inside the first region 310 of the first protective layer 210 can still participate in the impurity gettering reaction, and the first top film with a higher concentration can be provided to supplement phosphorus for the first region 310 of the first protective layer 210, so that the first region 310 of the first protective layer 210 continues to react with the impurities in the semiconductor substrate 100; finally, the thickness of the first region 310 of the first protective layer 210 is increased. It can be understood that part of the first top film can penetrate into the second region of the first protective layer 210, but the amount of the first top film that penetrates into this region is very small and can be ignored compared with the first region 310 of the first protective layer 210.
  • the second diffusion annealing treatment is a high temperature annealing treatment process.
  • the second diffusion annealing treatment is the same as the first diffusion annealing treatment process, and the only difference is the temperature and time.
  • the temperature of the second diffusion annealing treatment is higher than the temperature of the first diffusion annealing treatment, and the time of the second diffusion annealing treatment is longer than the time of the first diffusion annealing treatment, so that the phosphorus in the first top film can fully pass through the first protective layer 210 to react with the impurities in the semiconductor substrate 100, and the reaction activity of the phosphorus in the first top film and the phosphorus in the first protective layer 210 with the impurities in the semiconductor substrate can be improved.
  • the first cover plate layer is made of quartz material.
  • the first cover plate layer of quartz material is low in cost and can be reused after cleaning. At the same time, it can play a buffering role in the second diffusion annealing process to protect the semiconductor substrate 100 and reduce the risk of fragmentation.
  • a first cover layer is disposed on the surface of the first protection layer away from the semiconductor substrate 100.
  • the semiconductor substrate 100 can be protected due to the presence of the first cover layer.
  • a patterned second cover layer is set on the surface of the second protective layer 220 facing away from the semiconductor substrate 100, and the second cover layer has a second hollow area.
  • the second protective layer 220 includes a third area 320 located at the bottom of the second hollow area and a fourth area blocked by the second cover layer; after the patterned second cover layer is set, the third area 320 of the second protective layer 220 is thickened.
  • the second cover plate layer is the same as or different from the first cover plate layer.
  • the shape and layout of the second hollowed-out area of the second cover plate layer are consistent with the shape and layout of the grid lines of the solar cell finally formed.
  • a second top film is coated on the surface of the third region 320; a fourth diffusion annealing treatment is performed to make the second top film become a part of the second protective layer, so that the thickness is increased to form the third region 320.
  • the second top film has the same component as the second bottom film. It should be noted that the phosphorus concentration of the second top film is greater than the phosphorus concentration of the second bottom film, so that the phosphorus of the second top film can fully penetrate the second protective layer 220 to react with impurities in the semiconductor substrate 100.
  • the second top film can directly penetrate into the surface of the semiconductor substrate 100 through the third region 320 of the second protective layer 220, and diffuse into the semiconductor substrate 100 to react with the impurities in the semiconductor substrate 100; in addition, the phosphorus inside the third region 320 of the second protective layer 220 can still participate in the impurity gettering reaction, and the second top film with a higher concentration can be provided to supplement phosphorus for the third region 320 of the second protective layer 220, so that the third region 320 of the second protective layer 220 continues to react with the impurities in the semiconductor substrate 100; finally, the thickness of the third region 320 of the second protective layer 220 is increased. It can be understood that part of the second top film can penetrate into the fourth region of the second protective layer 220, but the amount of the second top film that penetrates into this area is very small and can be ignored compared with the third region 320 of the second protective layer 220.
  • the fourth diffusion annealing treatment is a high temperature annealing treatment process.
  • the fourth diffusion annealing treatment has the same process method as the third diffusion annealing treatment, and only differs in temperature and time.
  • the temperature of the fourth diffusion annealing treatment is higher than the temperature of the third diffusion annealing treatment, and the time of the fourth diffusion annealing treatment is longer than the time of the third diffusion annealing treatment, so that the phosphorus in the second top film can fully pass through the second protective layer 220 to react with the impurities in the semiconductor substrate 100, and the reaction activity of the phosphorus in the second top film and the phosphorus in the second protective layer 220 with the impurities in the semiconductor substrate can be improved.
  • the second cover plate layer is made of quartz material.
  • the second cover plate layer of quartz material is low in cost and can be reused after cleaning. At the same time, it can play a buffering role in the fourth diffusion annealing process to protect the semiconductor substrate 100 and reduce the risk of fragmentation.
  • a second cover layer is set on the surface of the second protective layer.
  • the second cover layer is not removed and can continue to play a buffering role to protect the semiconductor layer substrate layer 100 and reduce the risk of fragmentation.
  • the first cover layer is removed.
  • the second area of the first protection layer 210 is removed by etching using the first area 310 of the first protection layer 210 as protection.
  • the second area of the first protective layer 210 is etched and removed, and the parameters include: the etching solution used is a mixture of hydrofluoric acid aqueous solution, hydrochloric acid aqueous solution and water solvent, the mass concentration of the hydrofluoric acid aqueous solution is 35% to 50%, the mass concentration of the hydrochloric acid aqueous solution is 30% to 50%, the volume proportion of the hydrofluoric acid aqueous solution is 1% to 4%, the volume proportion of the hydrochloric acid aqueous solution is 1% to 3%, and the etching time is 100s to 300s.
  • the etching solution used is a mixture of hydrofluoric acid aqueous solution, hydrochloric acid aqueous solution and water solvent
  • the mass concentration of the hydrofluoric acid aqueous solution is 35% to 50%
  • the mass concentration of the hydrochloric acid aqueous solution is 30% to 50%
  • the volume proportion of the hydrofluoric acid aqueous solution is
  • the parameters for etching and removing the second area of the first protective layer 210 include: the etching solution is an aqueous solution of 48% hydrofluoric acid and 37% hydrochloric acid, the volume proportion of the hydrofluoric acid aqueous solution is 3% and the volume proportion of the hydrochloric acid aqueous solution is 2%, and the etching time is 150s.
  • the second cover layer is removed.
  • the fourth area of the second protective layer 220 is removed with the third area 320 of the second protective layer 220 as protection.
  • the fourth area of the second protective layer 220 is etched away, and the parameters for etching away the fourth area of the second protective layer 220 are the same as the parameters for etching away the second area of the first protective layer 210, which will not be repeated here.
  • the second region of the first protective layer 210 of the semiconductor substrate 100 is first etched away, and then the fourth region of the second protective layer 220 of the semiconductor substrate 100 is etched away.
  • the fourth region of the second protective layer 220 of the semiconductor substrate 100 is first etched away, and then the second region of the first protective layer 210 of the semiconductor substrate 100 is etched away.
  • the second region of the first protective layer 210 of the semiconductor substrate 100 and the fourth region of the second protective layer 220 of the semiconductor substrate 100 are simultaneously etched away.
  • the semiconductor substrate 100 exposed by the first region 310 is subjected to a texturing process to form a first texturing region 111 of the semiconductor substrate 100
  • the semiconductor substrate 100 exposed by the third region 320 is subjected to a texturing process to form a second texturing region 121 of the semiconductor substrate 100.
  • the semiconductor substrate 100 exposed by the first region 310 is first subjected to a texturing process to form the first texturing region 111 of the semiconductor substrate 100
  • the semiconductor substrate 100 exposed by the third region 320 is subjected to a texturing process to form the second texturing region 121 of the semiconductor substrate 100.
  • the semiconductor substrate 100 exposed by the third region 320 is first subjected to a texturing process to form the second texturing region 121 of the semiconductor substrate 100, and then the semiconductor substrate 100 exposed by the first region 310 is subjected to a texturing process to form the first texturing region 111 of the semiconductor substrate 100.
  • the semiconductor substrate 100 exposed by the first region 310 is textured to form a first textured region 111 of the semiconductor substrate 100
  • the semiconductor substrate 100 exposed by the third region 320 is textured to form a second textured region 121 of the semiconductor substrate 100.
  • the texturing treatment includes treatment with a texturing agent.
  • the texturing agent is a 2% to 5% potassium hydroxide aqueous solution, and exemplarily, the texturing agent is a 2% potassium hydroxide aqueous solution, a 3% potassium hydroxide aqueous solution, a 4% potassium hydroxide aqueous solution, or a 5% potassium hydroxide aqueous solution;
  • the texturing treatment time is 150s to 300s, and exemplarily, the time is 150s, 180s, 200, 250s, 280s, or 300s;
  • the temperature is 60°C to 70°C, and exemplarily, the temperature is 60°C, 62°C, 65°C, 67°C, or 70°C.
  • the first region 310 is etched away to form the first light region 112 of the semiconductor substrate 100, and the third region 320 is etched away to form the second light region 122 of the semiconductor substrate 100.
  • the first region 310 is first etched away to form the first light region 112 of the semiconductor substrate 100, and then the third region 320 is etched away to form the second light region 122 of the semiconductor substrate 100.
  • the third region 320 is first etched away to form the second light region 122 of the semiconductor substrate 100, and then the first region 310 is etched away to form the first light region 112 of the semiconductor substrate 100.
  • the first region 310 is etched away to form the first light region 112 of the semiconductor substrate 100, and the third region 320 is etched away to form the second light region 122 of the semiconductor substrate 100, and simultaneously.
  • the first area 310 and the third area 320 are etched away.
  • the parameters for etching away the first area 310 and the third area 320 are the same as the parameters for etching away the second area of the first protective layer 210 and the parameters for etching away the fourth area of the second protective layer 220, and are not repeated here.
  • the other side of the semiconductor substrate 100 is processed to form a second polished area 122 and a second velvet area 121 adjacent to the second polished area 122 .
  • a first region 310 and a second region of the first protective layer 210 are formed on one side of the semiconductor substrate 100, the first region 310 of the first protective layer 210 is used as protection, the second region of the first protective layer 210 is removed by etching, the semiconductor substrate 100 exposed by the first region 310 of the first protective layer 210 is subjected to a texturing process to form a first texturing region 111, the first region 310 of the first protective layer 210 is removed by etching, and a first smooth region 112 is formed.
  • a third region 320 and a fourth region of the second protective layer 220 are formed on the other side of the semiconductor substrate 100, the third region 320 of the second protective layer 220 is used as protection, the fourth region of the second protective layer 220 is removed by etching, the semiconductor substrate 100 exposed by the third region 320 of the second protective layer 220 is subjected to a texturing process to form a second texturing region 121, the third region 320 of the second protective layer 220 is removed by etching, and a second smooth region 122 is formed.
  • One or more embodiments of the present application further provide a semiconductor substrate, at least one side of the semiconductor substrate having a smooth surface area and a velvet surface area adjacent to the smooth surface area, and an area of the smooth surface area is greater than or equal to an area of the velvet surface area.
  • one side of the semiconductor substrate 100 has a first polished area 112 and a first velvet area 111 adjacent to the first polished area 112 ; and/or, the other side of the semiconductor substrate 100 has a second polished area 122 and a second velvet area 121 adjacent to the second polished area 122 .
  • the semiconductor substrate 100 in the above embodiment is manufactured by the above-mentioned semiconductor substrate processing method, and has the same beneficial effects, which will not be described in detail here.
  • the area of the first polished area 112 is greater than or equal to the area of the first velvet area 111, for example, the ratio of the area of the first polished area 112 to the area of the first velvet area 111 is 1:1 to 1.2:1, and exemplarily, the ratio of the area of the first polished area 112 to the area of the first velvet area 111 is 1:1, 1.05:1, 1.1:1, 1.15:1 or 1.2:1; and/or, the area of the second polished area 122 is greater than or equal to the area of the second velvet area 121, for example, the ratio of the area of the second polished area 122 to the area of the second velvet area 121 is 1:1 to 1.2:1, and exemplarily, the ratio of the area of the second polished area 122 to the area of the second velvet area 121 is 1:1, 1.05:1, 1.1:1, 1.15:1 or 1.2:1.
  • the first light surface area 112 or the second light surface area 122 corresponds to the transparent conductive film and the gate line. Increasing the area of the first light surface area 112 or the second light surface area 122 can enable the above-mentioned functional layers to be fully in contact, which is beneficial to reducing the series resistance in the solar cell, increasing the current, reducing unnecessary power loss, and improving the photoelectric conversion performance of the solar cell.
  • first light surface area 112 and the second light surface area 122 both have a flat surface, which is beneficial to the uniform deposition of other material layers in the area; and the impurity ion concentration inside the first light surface area 112 and the second light surface area 122 is low, which is beneficial to reducing the probability of photogenerated carriers being captured by defects in the semiconductor substrate, thereby improving the photoelectric conversion efficiency.
  • One or more embodiments of the present application also provide a method for preparing a solar cell, comprising: providing a semiconductor substrate; processing the semiconductor substrate using the aforementioned semiconductor substrate processing method so that at least one side of the semiconductor substrate has a glossy area and a velvet area adjacent to the glossy area; forming a transparent conductive film on a side of the semiconductor substrate having the glossy area and the velvet area, the transparent conductive film being located and only located in the glossy area; and forming a gate line in at least a portion of the area on a side of the transparent conductive film that is away from the semiconductor substrate.
  • the transparent conductive film is disposed opposite to the glossy area, that is, the area of the orthographic projection of the transparent conductive film on the velvet area is zero.
  • the method for preparing a solar cell further includes: before forming the transparent conductive film, forming a doped semiconductor layer on a side of the semiconductor substrate having the smooth surface area and the velvet surface area; the doped semiconductor layer is located between the semiconductor substrate and the transparent conductive film.
  • an intrinsic semiconductor layer is formed on a side of the semiconductor substrate having the smooth surface area and the textured surface area; the intrinsic semiconductor layer is located between the semiconductor substrate and the doped semiconductor layer.
  • the solar cell provided by the present application has a transparent conductive film and a grid line located and only located in the light surface area. Since the surface of the light surface area is smooth, it is conducive to the uniform deposition of the transparent conductive film and the grid line in the light surface area. The flat light surface area is conducive to the transparent conductive film and the grid line being fully in contact with each other, thereby reducing the series resistance. The velvet surface area can provide excellent light trapping effect.
  • the solar cell provided by the present application can take into account both the light trapping effect and the low series resistance, which is conducive to improving the photoelectric conversion efficiency of the solar cell.
  • a smooth surface area and a velvet surface area can be formed only on one side of the semiconductor substrate to prepare a solar cell; a smooth surface area and a velvet surface area can be formed on both sides of the semiconductor substrate to prepare a solar cell.
  • a smooth surface area and a velvet surface area can be formed on both sides of the semiconductor substrate to prepare a solar cell.
  • a first intrinsic semiconductor layer 410 is formed on the side of the semiconductor substrate 101 having the first smooth surface area and the first velvet surface area
  • a second intrinsic semiconductor layer 420 is formed on the side of the semiconductor substrate 101 having the second smooth surface area and the second velvet surface area.
  • the first intrinsic semiconductor layer 410 and the second intrinsic semiconductor layer 420 include amorphous silicon or microcrystalline silicon, which plays a passivation role.
  • the first intrinsic semiconductor layer 410 can be uniformly deposited in the first optical area, thereby improving the uniformity of the first intrinsic semiconductor layer 410 and further improving the passivation effect, ultimately achieving the purpose of improving the photoelectric conversion efficiency of the solar cell.
  • a first doped semiconductor layer 510 is formed on a side of the first intrinsic semiconductor layer 410 facing away from the semiconductor substrate 101; a second doped semiconductor layer 520 is formed on a side of the second intrinsic semiconductor layer 420 facing away from the semiconductor substrate 101.
  • the first doped semiconductor layer 510 is N-type doped amorphous silicon or N-type doped microcrystalline silicon
  • the second doped semiconductor layer 520 is P-type doped amorphous silicon or P-type doped microcrystalline silicon, or vice versa.
  • a first transparent conductive film 610 is formed in a partial region of the first doped semiconductor layer 510 away from the first light surface region, and the first transparent conductive film 610 is only located in the first light surface region;
  • a second transparent conductive film 620 is formed in a partial region of the second doped semiconductor layer 520 away from the second light surface region, and the second transparent conductive film 620 is only located in the second light surface region.
  • the first transparent conductive film 610 and the second transparent conductive film 620 are indium-doped tin oxide.
  • the first transparent conductive film 610 is disposed opposite to the first smooth surface area, and the orthographic projection area of the first transparent conductive film 610 in the first velvet surface area is zero.
  • the second transparent conductive film 620 is disposed opposite to the second smooth surface area, and the orthographic projection area of the second transparent conductive film 620 in the second velvet surface area is zero.
  • a first gate line 710 is formed on a side of the first transparent conductive film 610 away from the first doped semiconductor layer 510, and a second gate line 720 is formed on a side of the second transparent conductive film 620 away from the second doped semiconductor layer 520.
  • the first gate line 710 and the second gate line 720 are silver.
  • the method for preparing a solar cell includes: forming a first intrinsic semiconductor layer 410, a first doped semiconductor layer 510, a first transparent conductive film 610 and a first gate line 710 in sequence on a side of a semiconductor substrate 101 having a first smooth surface area 112 and a first velvet area 111, and then forming a second intrinsic semiconductor layer 420, a second doped semiconductor layer 520, a second transparent conductive film 620 and a second gate line 720 in sequence on a side of the semiconductor substrate 101 having a second smooth surface area 122 and a second velvet area 121.
  • the solar energy preparation method in this embodiment differs from the solar cell preparation method in the aforementioned embodiment only in the order of forming various functional layers on both sides of the semiconductor substrate 101. Other parameters are the same and will not be described again.
  • One or more embodiments of the present application also provide a solar cell, comprising: a semiconductor substrate, at least one side of the semiconductor substrate having a smooth surface area and a velvet surface area adjacent to the smooth surface area, the area of the smooth surface area being greater than or equal to the area of the velvet surface area; a transparent conductive film, located on a side of the semiconductor substrate having the smooth surface area and the velvet surface area, and only located on the smooth surface area; a gate line, located on at least a portion of a side of the transparent conductive film facing away from the semiconductor substrate, and only located on the transparent conductive film.
  • the semiconductor substrate includes: a first light surface area located on one side of the semiconductor substrate and a first velvet surface area adjacent to the first light surface area; and/or, a second light surface area located on the other side of the semiconductor substrate and a second velvet surface area adjacent to the second light surface area; a doped semiconductor layer located between the semiconductor substrate and the transparent conductive film.
  • the solar cell further includes: an intrinsic semiconductor layer located between the semiconductor substrate and the doped semiconductor layer.
  • the solar cell includes: a first intrinsic semiconductor layer and a second intrinsic semiconductor layer, the first intrinsic semiconductor layer is located between the first doped semiconductor layer and the side of the semiconductor substrate having the first light surface area and the first velvet surface area, and the second intrinsic semiconductor layer is located between the second doped semiconductor layer and the side of the semiconductor substrate having the second light surface area and the second velvet surface area; a first doped semiconductor layer and a second doped semiconductor layer, the first doped semiconductor layer is located on the side of the first intrinsic semiconductor layer away from the semiconductor substrate, and the second doped semiconductor layer is located on the side of the second intrinsic semiconductor layer away from the semiconductor substrate; a first transparent conductive film and a second transparent conductive film, the first transparent conductive film is located between the first doped semiconductor layer and the side of the semiconductor substrate having the second light surface area and the second velvet surface area.
  • the first transparent conductive film is only located in the first light surface area
  • the second transparent conductive film is located on the side of the second doped semiconductor layer away from the second intrinsic semiconductor layer
  • the second transparent conductive film is only located in the second light surface area
  • the first gate line and the second gate line the first gate line is located on the side of the first transparent conductive film away from the first doped semiconductor layer, the first gate line is only located in the first light surface area, and the area of the first gate line is less than or equal to the area of the first transparent conductive film
  • the second gate line is located on the side of the second transparent conductive film away from the second doped semiconductor layer, the second gate line is only located in the second light surface area, and the area of the second gate line is less than or equal to the area of the second transparent conductive film.
  • the solar cell of the above embodiment includes the semiconductor substrate obtained in the above embodiment, and thus can achieve the same beneficial effects as the above semiconductor substrate, which will not be described in detail here.
  • a semiconductor substrate is provided.
  • the material of the semiconductor substrate is single crystal silicon and the thickness is 100 ⁇ m to 180 ⁇ m.
  • One side of the semiconductor substrate has a first light surface area and a first velvet area adjacent to the first light surface area, and the other side of the semiconductor substrate has a second light surface area and a second velvet area adjacent to the second light surface area.
  • a first intrinsic semiconductor layer is formed on the side of the semiconductor substrate having the first light surface area and the first velvet area.
  • the material of the first intrinsic semiconductor layer is amorphous silicon and the thickness is 5nm to 10nm;
  • a second intrinsic semiconductor layer is formed on the side of the semiconductor substrate having the second light surface area and the second velvet area.
  • the material of the second intrinsic semiconductor layer is amorphous silicon and the thickness is 5nm to 10nm.
  • a first doped semiconductor layer is formed on the first intrinsic semiconductor layer.
  • the material of the first doped semiconductor layer is N-type doped amorphous silicon and the thickness is 5nm to 15nm;
  • a second doped semiconductor layer is formed on the second intrinsic semiconductor layer.
  • the material of the second doped semiconductor layer is P-type doped amorphous silicon and the thickness is 5nm to 15nm.
  • a first transparent conductive film is formed on the first doped semiconductor layer.
  • the material of the first transparent conductive film is ITO, the thickness is 80nm-100nm, the first transparent conductive film is arranged opposite to the first light surface area, and the area of the orthographic projection on the first velvet surface area is zero; a second transparent conductive film is formed on the second doped semiconductor layer.
  • the material of the second transparent conductive film is ITO, the thickness is 80nm-100nm, the second transparent conductive film is arranged opposite to the second light surface area, and the area of the orthographic projection on the second velvet surface area is zero.
  • Silver paste is deposited on the first transparent conductive film to form a first grid line, the thickness is 10 ⁇ m-20 ⁇ m; silver paste is deposited on the second transparent conductive film to form a second grid line, the thickness is 10 ⁇ m-20 ⁇ m.
  • I SC short circuit current
  • U OC open circuit voltage
  • FF fill factor
  • E ta photoelectric conversion efficiency
  • R ser series resistance
  • R shunt shunt resistance
  • the fill factor of the solar cell in the embodiment is 0.84% higher, the short-circuit current is increased by 5mA, the open-circuit voltage is increased by 1mV, the series resistance is reduced by 0.56m ⁇ , and the photoelectric conversion efficiency is increased by 0.2604%.
  • the embodiment uses a semiconductor substrate having a smooth surface area and a velvet surface area on the surface, and the first gate line and the first transparent conductive film are designed to be arranged opposite to the first smooth surface area and not cover the first velvet surface area, and the second gate line and the second transparent conductive film are designed to be arranged opposite to the second smooth surface area and not cover the second velvet surface area, the deposition of each functional layer is more uniform, which is beneficial to reducing the series resistance and increasing the open circuit voltage.
  • the contact resistance between the polished area (smooth surface area) and the metallized electrode is lower, and the series resistance (R ser ) is also significantly reduced.

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Abstract

本申请涉及太阳能电池技术领域，具体提供了一种半导体衬底及其处理方法、太阳能电池及其制备方法，其中，半导体衬底的处理方法包括：包括：在半导体衬底的至少一面形成光面区和与光面区相邻的绒面区；光面区的面积大于或等于绒面区的面积。本申请通过在半导体衬底的至少一面形成光面区和与光面区相邻的绒面区，使得透明导电膜位于且仅位于光面区；且在对应透明导电膜背离半导体衬底的一侧形成栅线，能够提高太阳能电池的光电转换效率。

Description

半导体衬底及其处理方法、太阳能电池及其制备方法
本申请要求在2022年11月4日提交中国专利局、申请号为202211378975.9、发明名称为“半导体衬底及其处理方法、太阳能电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及太阳能电池技术领域，具体涉及一种半导体衬底及其处理方法、太阳能电池及其制备方法。
背景技术
太阳能电池(Solar Cell)是通过吸收太阳光，将太阳辐射能通过光电效应或者光化学效应直接或间接转换成电能的装置。太阳能电池是一种清洁能源电池，广泛的应用在生活和生产中。
太阳能电池中常用的半导体衬底之一是硅衬底。为了增大太阳能电池的吸光能力，通常会通过在硅衬底表面进行制绒处理形成绒面，增大硅衬底的陷光能力，从而提高太阳能电池的光电转换效率。然而，由于制绒处理后，会在硅衬底表面形成密集排布的金字塔结构，这些金字塔结构的高度的通常能达到1μm～2μm，造成后续工艺形成的其他材料层的均匀性变差，使得太阳能电池的开路电压降低；此外，各材料层之间的接触也会变差，使得载流子的传输受限，串联电阻较大，因而造成太阳能的光电转换性能降低。
由此可见，如何提高太阳能电池的光电转换效率，是太阳能电池领域的一个亟需解决的问题。
发明内容
因此，本申请要解决的技术问题在于克服现有技术中太阳能电池的光电转换效率低问题，从而提供一种半导体衬底及其处理方法、太阳能电池及其制备方法。
本申请的第一方面提供一种半导体衬底的处理方法，包括：在半导体衬底的至少一面形成光面区和与光面区相邻的绒面区；光面区的面积大于或等于绒面区的面积。
可选的，光面区的面积与绒面区的面积的比值为1:1～1.2:1。
可选的，在半导体衬底的任意一面形成光面区和与光面区相邻的绒面区的步骤包括：在半导体衬底的任意一侧表面形成保护层；在保护层背离半导体衬底的表面设置图案化的盖板层，盖板层中具有镂空区，保护层包括位于镂空区底部的第一区和被盖板层遮挡的第二区；利用盖板层，对保护层的第一区进行加厚处理；对保护层的第一区进行加厚处理之后，去除盖板层；以去除盖板层之后的保护层的第一区作为保护，刻蚀去除保护层的第二区；对去除保护层的第二区之后保护层暴露出的半导体衬底的一侧进行制绒处 理，使得保护层暴露出的半导体衬底的一侧形成绒面区；形成绒面区之后，刻蚀去除保护层对应的第一区，使半导体衬底的一侧的部分表面形成光面区。
可选的，所述镂空区至少包括多个间隔开设的条状开口、且条状开口彼此平行。
可选的，在半导体衬底的任意一侧形成保护层的步骤包括：在半导体衬底的任意一侧涂覆整面的底层膜；对底层膜进行扩散退火处理，以使底层膜和半导体衬底的一侧表面反应形成具有掺杂离子的保护层，使得半导体衬底内部的杂质迁移至保护层中。
可选的，对保护层的第一区进行加厚处理的步骤包括：以盖板层为掩膜，在第一区的表面涂覆顶层膜；对顶层膜进行扩散退火处理，以使顶层膜成为保护层的一部分，从而使第一区的厚度增加。
可选的，盖板层包括石英材料。
可选的，底层膜和顶层膜为液态源膜。
可选的，底层膜和顶层膜为含磷液态源膜，顶层膜的磷浓度大于底层膜的磷浓度。
可选的，对顶层膜进行扩散退火处理的时间大于对底层膜进行扩散退火处理的时间。
可选的，对顶层膜进行扩散退火处理的温度大于对底层膜进行扩散退火处理的温度。
可选的，刻蚀去除保护层的第一区的步骤和刻蚀去除保护层的第二区的步骤中，参数均包括：采用的刻蚀液为氢氟酸水溶液、盐酸水溶液和水溶剂的混合物，氢氟酸水溶液的质量浓度为35％～50％，盐酸水溶液的质量浓度为30％～50％，氢氟酸水溶液的体积占比为1％～4％，盐酸水溶液的体积占比为1％～3％，刻蚀时间为100s～300s。
本申请的第二方面提供一种半导体衬底，半导体衬底的至少一面具有光面区和与光面区相邻的绒面区，光面区的面积大于或等于绒面区的面积。
可选的，光面区的面积与绒面区的面积的比值为1:1～1.2:1。
本申请的第三方面提供一种太阳能电池的制备方法，包括：提供半导体衬底；采用前述半导体衬底的处理方法对半导体衬底进行处理，使得半导体衬底的至少一面具有光面区和与光面区相邻的绒面区；在半导体衬底具有光面区和绒面区的一侧形成透明导电膜，透明导电膜位于且仅位于光面区；在透明导电膜背离半导体衬底的一侧的至少部分区域形成栅线。
可选的，太阳能电池的制备方法还包括：在形成透明导电膜之前，在半导体衬底具有光面区和绒面区的一侧形成掺杂半导体层；掺杂半导体层位于半导体衬底与透明导电膜之间。
可选的，在形成掺杂半导体层之前，在半导体衬底具有光面区和绒面区的一侧形成本征半导体层；本征半导体层位于半导体衬底与掺杂半导体层之间。
本申请的第四方面提供一种太阳能电池，包括：半导体衬底，半导体衬底的至少一面具有光面区和与光面区相邻的绒面区，光面区的面积大于或等于绒面区的面积；透明导电膜，位于半导体衬底具有光面区和绒面区的一侧，且仅位于光面区；栅线，位于透明导电膜背离半导体衬底的一侧的至少部分区域。
可选的，太阳能电池还包括：掺杂半导体层，位于半导体衬底与透明导电膜之间。
可选的，太阳能电池还包括：本征半导体层，位于半导体衬底与掺杂半导体层之间。
本申请的技术方案可以实现以下有益效果：
1.本申请通过对半导体衬底进行处理，使得半导体衬底的至少一侧表面包括光面区和与光面区相邻的绒面区，其中，绒面区可以提供优异的陷光作用，光面区的表面光滑，有利于其他材料层在该区域的均匀沉积，从而获得更好的材料膜层均匀性，有利于提高光电转换效率，提升电池效率。
2.本申请通过在半导体衬底的表面形成保护层，通过扩散退火可以使得半导体衬底中的杂质离子迁移至保护层中，有助于降低半导体衬底中的缺陷。之后，利用盖板层对保护层的第一区进行加厚处理，半导体衬底的杂质离子可以继续扩散进入保护层的第一区中，有助于进一步降低半导体衬底与保护层的第一区对应区域的缺陷。在后续刻蚀去除第二区时保护层的第一区的至少部分厚度得以保留，保证在制绒处理时半导体衬底与保护层的第二区对应的区域形成绒面区；保护层的第一区可以保护半导体衬底的对应区域不会被刻蚀，之后刻蚀去除保护层的第一区，半导体衬底与保护层的第一区对应的区域形成具有平坦表面的光面区，且半导体衬底的光面区的杂质离子浓度低，因而半导体衬底的缺陷密度小。
3.本申请使用的盖板层采用耐高温的石英材料，成本低廉，清洗后可重复使用；此外，盖板层可以在扩散退火处理过程中保护半导体衬底，降低碎片风险。
4.本申请提供的太阳能电池，透明导电膜和栅线均位于且仅位于光面区，由于光面区表面光滑，有利于透明导电膜、栅线在光面区的均匀沉积，平坦的光面区有利于透明导电膜、栅线相互之间充分接触，降低串联电阻；绒面区可以提供优异的陷光作用。本申请提供的太阳能电池，可以同时兼顾陷光作用与低串联电阻，有利于提高太阳能电池的光电转换效率。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例的在半导体衬底的一侧形成光面区和绒面区的一个示例性的流程图；
图2-图10为本申请实施例的半导体衬底的处理过程中的结构示意图；
图11为本申请实施例的盖板层的结构示意图；
图12-图19为本申请实施例的太阳能电池的制备过程中的结构示意图。
附图标记说明：
100-半导体衬底；                   101-半导体衬底；
210-第一保护层；                    220-第二保护层；
310-第一区；                        320-第三区；
111-第一绒面区；                    112-第一光面区；
121-第二绒面区；                    122-第二光面区；
410-第一本征半导体层；              420-第二本征半导体层；
510-第一掺杂半导体层；              520-第二掺杂半导体层；
610-第一透明导电膜；                620-第二透明导电膜；
710-第一栅线；                      720-第二栅线；
810-第一盖板主体；                  820-第一镂空区。
具体实施方式
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
本申请的一个或多个实施例提供了一种半导体衬底的处理方法，包括：在半导体衬底的至少一面形成光面区和与光面区相邻的绒面区；光面区的面积大于或等于绒面区的面积。
本申请通过对半导体衬底进行处理，使得半导体衬底的至少一侧表面包括光面区和与光面区相邻的绒面区，其中，绒面区可以提供优异的陷光作用，光面区的表面光滑，有利于其他材料层在该区域的均匀沉积，有利于提高光电转换效率，提升电池效率。
在一个实施例中，光面区的面积与绒面区的面积的比值为1:1～1.2:1。示例性的，光面区的面积与绒面区的面积的比值为1:1、1.12:1、1.15:1、1.17:1或1.2:1。
在一个实施例中，在半导体衬底的任意一面形成光面区和与光面区相邻的绒面区的步骤包括：
步骤S100：在半导体衬底的任意一侧形成保护层；
步骤S200：在保护层背离半导体衬底的表面设置图案化的盖板层，盖板层中具有镂空区，保护层包括位于镂空区底部的第一区和被盖板层遮挡的第二区；
步骤S300：设置图案化的盖板层之后，对保护层的第一区进行加厚处理；
步骤S400：对保护层的第一区进行加厚处理之后，去除盖板层；
步骤S500：去除盖板层之后，以保护层的第一区作为保护刻蚀去除保护层的第二区；
步骤S600：刻蚀去除保护层的第二区之后，对保护层暴露出的半导体衬底的一侧进行制绒处理，使得保护层暴露出的半导体衬底的一侧形成绒面区；
步骤S700：形成绒面区之后，刻蚀去除保护层的第一区，使半导体衬底的一侧的部分表面形成光面区。
本申请通过在半导体衬底的表面形成保护层，可以使得半导体衬底中的杂质离子迁移至保护层中，有助于降低半导体衬底中的缺陷。之后，利用盖板层对保护层的第一区进行加厚处理，半导体衬底的杂质离子可以继续扩散进入保护层的第一区中，有助于进一步降低半导体衬底与保护层的第一区对应区域的缺陷。在后续刻蚀去除第二区时，保护层的第一区的至少部分厚度可以保留，在制绒处理时，半导体衬底与保护层的第二区对应的区域形成绒面区；保护层的第一区可以保护半导体衬底的对应区域不会被刻蚀，之后，刻蚀去除保护层的第一区，半导体衬底与保护层的第一区对应的区域形成光面区，且半导体衬底的光面区的杂质离子浓度低，因而，半导体衬底的缺陷密度小。
在本申请的一个实施例中，所述镂空区至少包括多个间隔开设的条状开口、且条状开口彼此平行。此时的所述镂空区可以用于制备主栅，形成无副栅电极结构。
在一个实施例中，在半导体衬底的任意一侧形成保护层的步骤包括：在半导体衬底的任意一侧涂覆整面的底层膜；对底层膜进行扩散退火处理，以使底层膜和半导体衬底的一侧表面反应形成具有掺杂离子的保护层，半导体衬底内部的杂质迁移至保护层中。
可以理解的是，对底层膜进行扩散退火处理，可以加速半导体衬底中的杂质离子扩散进入保护层中，并且可以使得反应更加充分。
在一个实施例中，对保护层的第一区进行加厚处理的步骤包括：以盖板层为掩膜，在第一区的表面涂覆顶层膜；对顶层膜进行扩散退火处理，以使第一区的厚度增加。
可以理解的是，盖板层可以限制顶层膜的涂覆位置和面积，根据具体的应用场景，采用具有不同形状和结构的盖板层。本申请的实施例对盖板层的形状和结构不做具体限制。
在一个实施例中，盖板层包括石英材料。本申请的实施例对此不作具体限制，只要盖板层能够在高温条件下不会融化或发生形变即可。
在一个实施例中，底层膜和顶层膜为液态源膜。在其他实施例中，底层膜和顶层膜也可以通过气相沉积形成。
在一个实施例中，底层膜和顶层膜为含磷液态源膜，顶层膜的磷浓度大于底层膜的磷浓度。
可以理解的是，保护层具有疏松结构，顶层膜可以渗透进入由底层膜形成的保护层中，从而与半导体衬底的表面接触进行反应；此外，顶层膜的磷浓度大于底层膜的磷浓 度有利于顶层膜中的磷元素扩散进入由底层膜形成的保护层中，使得由底层膜形成的保护层可以继续与半导体衬底发生反应。
在一个实施例中，对顶层膜进行扩散退火处理的时间大于对底层膜进行扩散退火处理的时间。
在一个实施例中，对顶层膜进行扩散退火处理的温度大于对底层膜进行扩散退火处理的温度。
在一个实施例中，刻蚀去除保护层的第一区的步骤和刻蚀去除保护层的第二区的步骤中，参数均包括：采用的刻蚀液为氢氟酸水溶液、盐酸水溶液和水溶剂的混合物，氢氟酸水溶液的质量浓度为35％～50％，盐酸水溶液的质量浓度为30％～50％，氢氟酸水溶液的体积占比为1％～4％，盐酸水溶液的体积占比为1％～3％，刻蚀时间为100s～300s。
在本申请的一个或多个实施例中，在半导体衬底的至少一面形成光面区和与光面区相邻的绒面区的步骤包括：在半导体衬底的一侧形成第一光面区和与第一光面区相邻的第一绒面区，第一光面区的面积大于或等于第一绒面区的面积；和/或，在半导体衬底的另一侧形成第二光面区和与第二光面区相邻的第二绒面区，第二光面区的面积大于或等于第二绒面区的面积。在下文中，以对半导体衬底的一侧表面形成第一光面区和第一绒面区、且在另一侧表面形成第二光面区和第二绒面区为例进行示例性说明，详细地介绍本申请的半导体衬底的处理方法。
下面结合图2-图10具体介绍半导体衬底的处理过程。
图2示出了本申请实施例的未经处理的半导体衬底100。
半导体衬底100的材料包括单晶硅。在其他实施例中，半导体衬底的材料为其他的半导体材料，如锗或者硅锗。半导体衬底的材料还可以为其他的半导体材料。
本实施例中，半导体衬底100的导电类型为N型，半导体衬底用于制备太阳能电池。
参见图3，在半导体衬底100的一侧上形成第一保护层。
具体的，在半导体衬底100的一侧涂覆整面的第一底层膜；进行第一扩散退火处理，以使第一底层膜和半导体衬底中的一侧反应形成具有掺杂离子的第一保护层，使得半导体衬底内部的杂质迁移至第一保护层中。
具体的，第一底层膜为液态源膜。在一个实施例中，第一底层膜为含磷液态源膜。
具体的，第一扩散退火处理为高温退火处理过程。将涂覆了第一底层膜的半导体衬底100置于烘箱或热台上，进行烘焙处理，使第一底层膜中的磷充分扩散进入半导体衬底100中，并且与半导体衬底100中的杂质进行反应，形成具有疏松结构的第一保护层210。其中，烘焙处理的温度为650℃～900℃，示例性的，温度为650℃、700℃、800℃、850℃或900℃；烘焙处理的时间为120s～1200s，示例性的，时间为120s、150s、200s、250s、300s、350s、400s、450s、500s、600s、700s、800s、900s、950s、1000s、1050s、1100s、1150s或1200s。
参见图4，在半导体衬底100的另一侧形成第二保护层。
具体的，在半导体衬底100的另一侧涂覆整面的第二底层膜；进行第三扩散退火处理，以使第二底层膜和半导体衬底中的另一侧反应形成具有掺杂离子的第二保护层，使得半导体衬底内部的杂质迁移至第二保护层中。
具体的，第二底层膜为液态源膜，与第一底层膜相同或不同。在一个实施例中，第二底层膜与第一底层膜相同。
具体的，第三扩散退火处理为高温退火处理过程。可以理解的是，第三扩散退火处理与第一扩散退火处理的工艺方法和产生的作用基本相同，在此不再赘述。
参见图5，在第一保护层210背离半导体衬底100的表面设置图案化的第一盖板层，第一盖板层中具有若干平行条状开口的第一镂空区，第一保护层210包括位于第一镂空区底部的第一区310和被第一盖板层遮挡的第二区；设置图案化的第一盖板层之后，对第一保护层210的第一区310进行加厚处理。
具体的，参见图11，第一盖板层包括第一盖板主体810和第一镂空区820。在本实施例中，第一镂空区820为在第一盖板主体810上均匀分布的若干条状开口的镂空结构。在其他实施例中，第一镂空区820也可以具有其他形状，例如：第一镂空区为在第一盖板主体810上规则排布的网络形状的镂空结构，此时适用于形成包括主栅和副栅的栅线电极结构，多条主栅互相平行，主栅与主栅平行设置，且主栅和副栅垂直设置或按照任一角度设置，副栅的宽度和高度均分别对应小于主栅的宽度和高度；此外，第一镂空区还可以为第一盖板主体810上不规则的排布的或者具有不同形状的镂空结构，此时适用于形成具有特殊图案的栅线。第一镂空区820的形状和布局与最终形成的太阳能电池的栅线的形状和布局一致，采用具有何种镂空结构的盖板层，这里不做限定。
具体的，在第一区310的表面涂覆第一顶层膜；进行第二扩散退火处理，以使第一顶层膜成为第一保护层210的一部分，从而使第一区310的厚度增加。第一顶层膜与第一底层膜的组分相同。需要注意的是，第一顶层膜的磷浓度大于第一底层膜的磷浓度，以利于第一顶层膜的磷可以充分的透过第一保护层210与半导体衬底100中的杂质进行反应。
在上述实施例中，由于第一保护层210为疏松结构，第一顶层膜可以通过第一保护层210的第一区310直接渗透到半导体衬底100的表面，并且扩散进入半导体衬底100中，以与半导体衬底100中的杂质进行反应；此外，第一保护层210的第一区310内部的磷依然可以参与吸杂反应，提供具有较高浓度的第一顶层膜，可以为第一保护层210的第一区310补充磷，使得第一保护层210的第一区310继续与半导体衬底100中的杂质进行反应；最终，使得第一保护层210的第一区310的厚度增大。可以理解的是，部分第一顶层膜可以渗透到第一保护层210的第二区，但是，渗透到该区域的第一顶层膜的量很少，与第一保护层210的第一区310相比可以忽略不计。
具体的，第二扩散退火处理为高温退火处理过程。第二扩散退火处理与第一扩散退 火处理的工艺方法相同，仅在温度和时间上存在差别。第二扩散退火处理的温度高于第一扩散退火处理的温度，第二扩散退火处理的时间大于第一扩散退火处理的时间，以利于第一顶层膜的磷可以充分的透过第一保护层210与半导体衬底100中的杂质进行反应，并且，可以提高第一顶层膜的磷和第一保护层210中的磷与半导体衬底中的杂质的反应活性。
在一个实施例中，第一盖板层为石英材料。石英材料的第一盖板层成本低廉，清洗后可重复使用，同时，可以在第二扩散退火处理过程中起到缓冲作用，保护半导体衬底100，降低碎片风险。
具体的，在形成第一保护层之后，在第一保护层背离半导体衬底100的表面设置第一盖板层。在后续的第二扩散退火处理过程中，由于第一盖板层的存在，可以保护半导体衬底100。
参见图6，在第二保护层220背离半导体衬底100的表面设置图案化的第二盖板层，第二盖板层中具有第二镂空区，第二保护层220包括位于第二镂空区底部的第三区320和被第二盖板层遮挡的第四区；设置图案化的第二盖板层之后，对第二保护层220的第三区320进行加厚处理。
具体的，根据具体的应用场景，第二盖板层与第一盖板层相同或不同。第二盖板层的第二镂空区的形状和布局与最终形成的太阳能电池的栅线的形状和布局一致。
具体的，在第三区320的表面涂覆第二顶层膜；进行第四扩散退火处理，以使第二顶层膜成为第二保护层的一部分，从而厚度增加形成第三区320。第二顶层膜与第二底层膜的组分相同。需要注意的是，第二顶层膜的磷浓度大于第二底层膜的磷浓度，以利于第二顶层膜的磷可以充分的透过第二保护层220与半导体衬底100中的杂质进行反应。
在上述实施例中，由于第二保护层220为疏松结构，第二顶层膜可以通过第二保护层220的第三区320直接渗透到半导体衬底100的表面，并且扩散进入半导体衬底100中，以与半导体衬底100中的杂质进行反应；此外，第二保护层220的第三区320内部的磷依然可以参与吸杂反应，提供具有较高浓度的第二顶层膜，可以为第二保护层220的第三区320补充磷，使得第二保护层220的第三区320继续与半导体衬底100中的杂质进行反应；最终，使得第二保护层220的第三区320的厚度增大。可以理解的是，部分第二顶层膜可以渗透到第二保护层220的第四区，但是，渗透到该区域的第二顶层膜的量很少，与第二保护层220的第三区320相比可以忽略不计。
具体的，第四扩散退火处理为高温退火处理过程。第四扩散退火处理与第三扩散退火处理的工艺方法相同，仅在温度和时间上存在差别。第四扩散退火处理的温度高于第三扩散退火处理的温度，第四扩散退火处理的时间大于第三扩散退火处理的时间，以利于第二顶层膜的磷可以充分的透过第二保护层220与半导体衬底100中的杂质进行反应，并且，可以提高第二顶层膜的磷和第二保护层220中的磷与半导体衬底中的杂质的 反应活性。
在一个实施例中，第二盖板层为石英材料。石英材料的第二盖板层成本低廉，清洗后可重复使用，同时，可以在第四扩散退火过程中起到缓冲作用，保护半导体衬底100，降低碎片风险。
在本实施例中，在进行第二扩散退火处理之后，在第二保护层表面设置第二盖板层，进行第四扩散退火处理的过程中，第二盖板层未被去除，能够继续起到缓冲作用，保护半导体层衬底层100，降低碎片风险。
参见图7，对第一保护层210的第一区310进行加厚处理之后，去除第一盖板层，去除第一盖板层之后，以第一保护层210的第一区310作为保护刻蚀去除第一保护层210的第二区。
具体的，刻蚀去除第一保护层210的第二区，参数包括：采用的刻蚀液为氢氟酸水溶液、盐酸水溶液和水溶剂的混合物，氢氟酸水溶液的质量浓度为35％～50％，盐酸水溶液的质量浓度为30％～50％，氢氟酸水溶液的体积占比为1％～4％，盐酸水溶液的体积占比为1％～3％，刻蚀时间为100s～300s。示例性的，刻蚀去除第一保护层210的第二区的参数包括：刻蚀液为48％氢氟酸和37％盐酸的水溶液，氢氟酸水溶液的体积占比为3％和盐酸水溶液的体积占比为2％，刻蚀时间为150s。
参见图8，对第二保护层220的第三区320进行加厚处理之后，去除第二盖板层，去除第二盖板层之后，以第二保护层220的第三区320作为保护去除第二保护层220的第四区。
具体地，刻蚀去除第二保护层220的第四区，刻蚀去除第二保护层220的第四区的参数与前述刻蚀去除第一保护层210的第二区的参数相同，在此不再赘述。
在本实施例中，先刻蚀去除半导体衬底100的第一保护层210的第二区，再刻蚀去除半导体衬底100的第二保护层220的第四区。在另一实施例中，先刻蚀去除半导体衬底100的第二保护层220的第四区，再刻蚀去除半导体衬底100的第一保护层210的第二区。在又一个实施例中，同时刻蚀去除半导体衬底100的第一保护层210的第二区和半导体衬底100的第二保护层220的第四区。
参见图9，对被第一区310暴露的半导体衬底100进行制绒处理，形成半导体衬底100的第一绒面区111，对被第三区320暴露的半导体衬底100进行制绒处理，形成半导体衬底100的第二绒面区121。在一个实施例中，先对被第一区310暴露的半导体衬底100进行制绒处理，形成半导体衬底100的第一绒面区111，再对被第三区320暴露的半导体衬底100进行制绒处理，形成半导体衬底100的第二绒面区121。在另一个实施例中，先对被第三区320暴露的半导体衬底100进行制绒处理，形成半导体衬底100的第二绒面区121，再对被第一区310暴露的半导体衬底100进行制绒处理，形成半导体衬底100的第一绒面区111。在又一个实施例中，同时对被第一区310暴露的半导体衬底100进行制绒处理，形成半导体衬底100的第一绒面区111，和对被第三区320暴 露的半导体衬底100进行制绒处理，形成半导体衬底100的第二绒面区121。
具体的，制绒处理包括使用制绒剂进行处理。在一个实施例中，制绒剂为2％～5％氢氧化钾的水溶液，示例性的，制绒剂为2％氢氧化钾的水溶液、3％氢氧化钾的水溶液、4％氢氧化钾的水溶液或5％氢氧化钾的水溶液；制绒处理的时间为150s～300s，示例性的，时间为150s、180s、200、250s、280s或300s；温度为60℃～70℃，示例性的，温度为60℃、62℃、65℃、67℃或70℃。
参见图10，刻蚀去除第一区310，形成半导体衬底100的第一光面区112，刻蚀去除第三区320，形成半导体衬底100的第二光面区122。在一个实施例中，先刻蚀去除第一区310，形成半导体衬底100的第一光面区112，再刻蚀去除第三区320，形成半导体衬底100的第二光面区122。在另一实施例中，先刻蚀去除第三区320，形成半导体衬底100的第二光面区122，再刻蚀去除第一区310，形成半导体衬底100的第一光面区112。在又一个实施例中，同时进行刻蚀去除第一区310，形成半导体衬底100的第一光面区112，和刻蚀去除第三区320，形成半导体衬底100的第二光面区122。
具体的，刻蚀去除第一区310和第三区320。刻蚀去除第一区310和第三区320的参数与刻蚀去除第一保护层210的第二区的参数和刻蚀去除第二保护层220的第四区的参数相同，在此不再赘述。
在本申请的其他实施例中，在半导体衬底100的一侧进行处理，形成第一光面区112和与第一光面区112相邻的第一绒面区111之后，再对半导体衬底100的另一侧进行处理，形成第二光面区122和与第二光面区122相邻的第二绒面区121。
具体的，在半导体衬底100的一侧形成第一保护层210的第一区310和第二区，以第一保护层210的第一区310为保护，刻蚀去除第一保护层210的第二区，对被第一保护层210的第一区310暴露的半导体衬底100进行制绒处理形成第一绒面区111，刻蚀去除第一保护层210的第一区310，形成第一光面区112。之后，在半导体衬底100的另一侧形成第二保护层220的第三区320和第四区，以第二保护层220的第三区320为保护，刻蚀去除第二保护层220的第四区，对被第二保护层220的第三区320暴露的半导体衬底100进行制绒处理形成第二绒面区121，刻蚀去除第二保护层220的第三区320，形成第二光面区122。
本申请的一个或多个实施例还提供了一种半导体衬底，半导体衬底的至少一面具有光面区和与光面区相邻的绒面区，光面区的面积大于或等于绒面区的面积。
参见图10，在一个实施例中，半导体衬底100的一侧具有第一光面区112和与第一光面区112相邻的第一绒面区111；和/或，半导体衬底100的另一侧具有第二光面区122和与第二光面区122相邻的第二绒面区121。
可以理解是，上述实施例中的半导体衬底100由前述半导体衬底的处理方法制得，具有相同的有益效果，在此不再赘述。
在一个实施例中，第一光面区112的面积大于或等于第一绒面区111的面积，例如， 第一光面区112的面积与第一绒面区111的面积的比值为1:1～1.2:1，示例性的，第一光面区112的面积与第一绒面区111的面积的比值为1:1、1.05:1、1.1:1、1.15:1或1.2:1；和/或，第二光面区122的面积大于或等于第二绒面区121的面积，例如，第二光面区122的面积与第二绒面区121的面积的比值为1:1～1.2:1，示例性的，第二光面区122的面积与第二绒面区121的面积的比值为1:1、1.05:1、1.1:1、1.15:1或1.2:1。
可以理解的是，在太阳能电池中，第一光面区112或第二光面区122与透明导电膜和栅线对应，增大第一光面区112的面积或第二光面区122的面积可以使得上述各个功能层能够充分地接触，有利于降低太阳能电池中的串联电阻，使得电流增大，减少不必要的功率损失，使得太阳能电池的光电转换性能提升。此外，第一光面区112和第二光面区122均具有平坦表面，有利于其他材料层在该区域的均匀沉积；并且，第一光面区112和第二光面区122的内部的杂质离子浓度低，有利于降低光生载流子在半导体衬底中被缺陷捕获的几率，进而提高光电转换效率。
本申请的一个或多个实施例还提供了一种太阳能电池的制备方法，包括：提供半导体衬底；采用前述半导体衬底的处理方法对半导体衬底进行处理，使得半导体衬底的至少一面具有光面区和与光面区相邻的绒面区；在半导体衬底具有光面区和绒面区的一侧形成透明导电膜，透明导电膜位于且仅位于光面区；在透明导电膜背离半导体衬底的一侧的至少部分区域形成栅线。
具体的，透明导电膜与光面区相对设置，也就是说，透明导电膜在绒面区的正投影的面积为零。
在一个实施例中，太阳能电池的制备方法还包括：在形成透明导电膜之前，在半导体衬底具有光面区和绒面区的一侧形成掺杂半导体层；掺杂半导体层位于半导体衬底与透明导电膜之间。
在一个实施例中，在形成掺杂半导体层之前，在半导体衬底具有光面区和绒面区的一侧形成本征半导体层；本征半导体层位于半导体衬底与掺杂半导体层之间。
本申请提供的太阳能电池，透明导电膜和栅线均位于且仅位于光面区，由于光面区表面光滑，有利于透明导电膜、栅线在光面区的均匀沉积，平坦的光面区有利于透明导电膜、栅线相互之间充分接触，降低串联电阻；绒面区可以提供优异的陷光作用。本申请提供的太阳能电池，可以同时兼顾陷光作用与低串联电阻，有利于提高太阳能电池的光电转换效率。
可以理解的是，可以仅在半导体衬底的任意一侧表面形成光面区和绒面区，进而制备太阳能电池；可以在半导体衬底的两侧表面均形成光面区和绒面区，进而制备太阳能电池。在下文中，以同时在半导体衬底的两侧形成太阳能电池为例，详细的介绍本申请的太阳能电池的制备方法。
下面结合图12-图19具体介绍太阳能电池的制备过程。
参见图12和图13，在半导体衬底101具有第一光面区和第一绒面区一侧形成第一 本征半导体层410，在半导体衬底101具有第二光面区和第二绒面区一侧形成第二本征半导体层420。示例性的，第一本征半导体层410和第二本征半导体层420包括非晶硅或者微晶硅，起到钝化作用。
可以理解的是，由于第一光面区具有平坦的表面，因而，第一本征半导体层410可以在第一光面区均匀沉积，提升第一本征半导体层410的均匀性，进而提升钝化效果，最终达到提升太阳能电池光电转换效率的目的。
参见图14和图15，在第一本征半导体层410背离半导体衬底101的一侧形成第一掺杂半导体层510；在第二本征半导体层420层背离半导体衬底101的一侧形成第二掺杂半导体层520。示例性的，第一掺杂半导体层510为N型掺杂非晶硅或N型掺杂微晶硅，第二掺杂半导体层520为P型掺杂非晶硅或P型掺杂微晶硅，反之亦可。
参见图16和图17，在第一掺杂半导体层510背离第一光面区的一侧的部分区域形成第一透明导电膜610，第一透明导电膜610仅位于第一光面区；在第二掺杂半导体层520背离第二光面区的一侧的部分区域形成第二透明导电膜620，第二透明导电膜620仅位于第二光面区。示例性的，第一透明导电膜610和第二透明导电膜620为掺铟氧化锡。
具体的，第一透明导电膜610与第一光面区相对设置，第一透明导电膜610在第一绒面区的正投影的面积为零。第二透明导电膜620与第二光面区相对设置，第二透明导电膜620在第二绒面区的正投影的面积为零。
参见图18和图19，在第一透明导电膜610背离第一掺杂半导体层510的一侧形成第一栅线710；在第二透明导电膜620背离第二掺杂半导体层520的一侧形成第二栅线720。示例性的，第一栅线710和第二栅线720为银。
在其他实施例中，太阳能电池的制备方法包括：在半导体衬底101的具有第一光面区112和第一绒面区111的一侧依次形成第一本征半导体层410、第一掺杂半导体层510、第一透明导电膜610和第一栅线710之后，再在半导体衬底101的具有第二光面区122和第二绒面区121的一侧依次形成第二本征半导体层420、第二掺杂半导体层520、第二透明导电膜620和第二栅线720。
具体的，在本实施例中的太阳能制备方法与前述实施例中的太阳能电池的制备方法，仅在半导体衬底101两侧形成各个功能层的顺序上存在区别，其他参数相同，在此不再赘述。
本申请的一个或多个实施例还提供了一种太阳能电池，包括：半导体衬底，半导体衬底的至少一面具有光面区和与光面区相邻的绒面区，光面区的面积大于或等于绒面区的面积；透明导电膜，位于半导体衬底具有光面区和绒面区的一侧，且仅位于光面区；栅线，位于透明导电膜背离半导体衬底的一侧的至少部分区域，且仅位于透明导电膜上。
在一个实施例中，半导体衬底包括：位于半导体衬底的一侧的第一光面区和与第一光面区相邻的第一绒面区；和/或，位于半导体衬底的另一侧的第二光面区和与第二光面 区相邻的第二绒面区；掺杂半导体层，位于半导体衬底与透明导电膜之间。可选的，太阳能电池还包括：本征半导体层，位于半导体衬底与掺杂半导体层之间。上述结构成为光生载流子产生的重要结构。
在本申请的一个具体的示例中，太阳能电池包括：第一本征半导体层和第二本征半导体层，第一本征半导体层位于第一掺杂半导体层与半导体衬底具有第一光面区和第一绒面区的一侧之间，第二本征半导体层位于第二掺杂半导体层与半导体衬底具有第二光面区和第二绒面区的一侧之间；第一掺杂半导体层和第二掺杂半导体层，第一掺杂半导体层位于第一本征半导体层背离半导体衬底的一侧，第二掺杂半导体层位于第二本征半导体层背离半导体衬底的一侧；第一透明导电膜和第二透明导电膜，第一透明导电膜位于第一掺杂半导体层背离第一本征半导体层的一侧，且第一透明导电膜仅位于第一光面区，第二透明导电膜位于第二掺杂半导体层背离第二本征半导体层的一侧，且第二透明导电膜仅位于第二光面区；第一栅线和第二栅线，第一栅线位于第一透明导电膜背离第一掺杂半导体层的一侧，第一栅线仅位于第一光面区，且第一栅线的面积小于或等于第一透明导电膜的面积，第二栅线位于第二透明导电膜背离第二掺杂半导体层的一侧，第二栅线仅位于第二光面区，且第二栅线的面积小于或等于第二透明导电膜的面积。
可以理解的是，上述实施例的太阳能电池包括前述实施例中得到半导体衬底，因而，可以实现与前述半导体衬底相同的有益效果，在此不再赘述。
下面结合具体的实施方式的测试例和对比例来描述本申请的太阳能电池。
测试例：
提供半导体衬底，半导体衬底的材料为单晶硅，厚度为100μm～180μm，半导体衬底的一侧具有第一光面区和与第一光面区相邻的第一绒面区，半导体衬底的另一侧具有第二光面区和与第二光面区相邻的第二绒面区。在半导体衬底的具有第一光面区和第一绒面区一侧上形成第一本征半导体层，第一本征半导体层的材料为非晶硅，厚度为5nm～10nm；在半导体衬底的具有第二光面区和第二绒面区的一侧形成第二本征半导体层，第二本征半导体层的材料为非晶硅，厚度为5nm～10nm。在第一本征半导体层上形成第一掺杂半导体层，第一掺杂半导体层的材料为N型掺杂非晶硅，厚度为5nm～15nm；在第二本征半导体层上形成第二掺杂半导体层，第二掺杂半导体层的材料为P型掺杂非晶硅，厚度为5nm～15nm。在第一掺杂半导体层上形成第一透明导电膜，第一透明导电膜的材料为ITO，厚度为80nm～100nm，第一透明导电膜与第一光面区相对设置，且在第一绒面区上的正投影的面积为零；在第二掺杂半导体层上形成第二透明导电膜，第二透明导电膜的材料为ITO，厚度为80nm～100nm，第二透明导电膜与第二光面区相对设置，且在第二绒面区上的正投影的面积为零。在第一透明导电膜上沉积银浆料形成第一栅线，厚度为10μm～20μm；在第二透明导电膜上沉积银浆料形成第二栅线，厚度为10μm～20μm。
对比例：
本对比例除了半导体衬底的两侧表面均为绒面之外，其余的制备方法和参数与测试例相同。
对上述测试例和对比例制得的太阳能电池进行光电转换性能转化测试，得到表1的数据。
Figure PCTCN2022141509-appb-000001
其中，I SC：短路电流；U OC：开路电压；FF：填充因子；E ta：光电转换效率；R ser：串联电阻；R shunt：并联电阻。
由表1中的数据可知，相较于对比例中使用传统的双面绒面的半导体衬底的太阳能电池，实施例中的太阳能电池的填充因子高出0.84％，短路电流提升5mA，开路电压提升1mV，串联电阻降低0.56mΩ，光电转换效率提升0.2604％。
可见，由于实施例使用了表面具有光面区和绒面区的半导体衬底，并且将第一栅线和第一透明导电膜设计为与第一光面区相对设置，且不覆盖第一绒面区，将第二栅线和第二透明导电膜设计为与第二光面区相对设置，且不覆盖第二绒面区，使得各个功能层沉积的更加均匀，有利于降低串联电阻和提升开路电压，此外，抛光区域(光面区)与金属化电极接触电阻更低，串联电阻(R ser)也显著降低，同时还有利于提升第一栅线和第二栅线对光生载流子的提取效率，使得在绒面区的面积减小的情况下，短路电流依然可以提升，最终可以改善太阳能电池的光电转换效率，提升电池效率。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请的保护范围之中。

Claims (10)

  1. 一种半导体衬底的处理方法，其特征在于，包括：
    在所述半导体衬底的至少一面形成光面区和与所述光面区相邻的绒面区；
    所述光面区的面积大于或等于所述绒面区的面积。
  2. 根据权利要求1所述的半导体衬底的处理方法，其特征在于，所述光面区的面积与所述绒面区的面积的比值为1:1～1.2:1。
  3. 根据权利要求1所述的半导体衬底的处理方法，其特征在于，在所述半导体衬底的任意一面形成光面区和与所述光面区相邻的绒面区的步骤包括：
    在所述半导体衬底的任意一侧表面形成保护层；
    在所述保护层背离所述半导体衬底的表面设置图案化的盖板层，所述盖板层中具有镂空区，所述保护层包括位于所述镂空区底部的第一区和被所述盖板层遮挡的第二区；
    利用所述盖板层对所述保护层的所述第一区进行加厚处理；
    对所述保护层的所述第一区进行加厚处理之后，去除所述盖板层；
    以去除所述盖板层之后的所述保护层的所述第一区作为保护，刻蚀去除所述保护层的所述第二区；
    对去除所述第二区之后所述保护层暴露出的所述半导体衬底的一侧进行制绒处理，使得所述保护层暴露出的所述半导体衬底的一侧形成所述绒面区；
    形成所述绒面区之后，刻蚀去除所述保护层对应的所述第一区，使所述半导体衬底的一侧的部分表面形成所述光面区；
    优选的，所述镂空区至少包括多个间隔开设的条状开口、且条状开口彼此平行。
  4. 根据权利要求3所述的半导体衬底的处理方法，在所述半导体衬底的任意一侧形成保护层的步骤包括：
    在所述半导体衬底的任意一侧涂覆整面的底层膜；
    对所述底层膜进行扩散退火处理，以使所述底层膜和所述半导体衬底的一侧表面反应形成具有掺杂离子的所述保护层，使得所述半导体衬底内部的杂质迁移至所述保护层中；
    优选的，对所述保护层的所述第一区进行加厚处理的步骤包括：以所述盖板层为掩膜，在所述第一区的表面涂覆顶层膜；对所述顶层膜进行扩散退火处理，以使所述顶层膜成为所述保护层的一部分，从而使所述第一区的厚度增加；
    优选的，所述盖板层包括石英材料；
    优选的，所述底层膜和所述顶层膜为液态源膜；
    优选的，所述底层膜和所述顶层膜为含磷液态源膜，所述顶层膜的磷浓度大于所述底层膜的磷浓度；
    优选的，对所述顶层膜进行扩散退火处理的时间大于对所述底层膜进行扩散退火处理的时间；
    优选的，对所述顶层膜进行扩散退火处理的温度大于对所述底层膜进行扩散退火处理的温度；
    优选的，刻蚀去除所述保护层的所述第一区的步骤和刻蚀去除所述保护层的所述第二区的步骤中，参数均包括：采用的刻蚀液为氢氟酸水溶液、盐酸水溶液和水溶剂的混合物，所述氢氟酸水溶液的质量浓度为35％～50％，所述盐酸水溶液的质量浓度为30％～50％，所述氢氟酸水溶液的体积占比为1％～4％，所述盐酸水溶液的体积占比为1％～3％，刻蚀时间为100s～300s。
  5. 一种半导体衬底，其特征在于，所述半导体衬底的至少一面具有光面区和与所述光面区相邻的绒面区，所述光面区的面积大于或等于所述绒面区的面积。
  6. 根据权利要求5所述的半导体衬底，其特征在于，所述光面区的面积与所述绒面区的面积的比值为1:1～1.2:1。
  7. 一种太阳能电池的制备方法，其特征在于，包括：
    提供半导体衬底；
    采用权利要求1至4中任一项所述的半导体衬底的处理方法对所述半导体衬底进行处理，使得所述半导体衬底的至少一面具有光面区和与所述光面区相邻的绒面区；
    在所述半导体衬底具有所述光面区和所述绒面区的一侧形成透明导电膜，所述透明导电膜位于且仅位于所述光面区；
    在所述透明导电膜背离所述半导体衬底的一侧的至少部分区域形成栅线。
  8. 根据权利要求7所述的太阳能电池的制备方法，其特征在于，还包括：在形成所述透明导电膜之前，在所述半导体衬底具有所述光面区和所述绒面区的一侧形成掺杂半导体层；所述掺杂半导体层位于所述半导体衬底与所述透明导电膜之间；
    优选的，在形成所述掺杂半导体层之前，在所述半导体衬底具有所述光面区和所述绒面区的一侧形成本征半导体层；所述本征半导体层位于所述半导体衬底与所述掺杂半导体层之间。
  9. 一种太阳能电池，其特征在于，包括：
    半导体衬底，所述半导体衬底的至少一面具有光面区和与所述光面区相邻的绒面区，所述光面区的面积大于或等于所述绒面区的面积；
    透明导电膜，位于所述半导体衬底具有所述光面区和所述绒面区的一侧，且仅位于所述光面区；
    栅线，位于所述透明导电膜背离所述半导体衬底的一侧的至少部分区域。
  10. 根据权利要求9所述的太阳能电池，其特征在于，还包括：掺杂半导体层，位于所述半导体衬底与所述透明导电膜之间；
    优选的，还包括：本征半导体层，位于所述半导体衬底与所述掺杂半导体层之间。
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CN114497288A (zh) * 2022-01-26 2022-05-13 中节能太阳能科技（镇江）有限公司 栅线嵌入选择性重掺杂区域的异质结太阳能电池制造方法
CN114843368A (zh) * 2022-04-29 2022-08-02 通威太阳能(眉山)有限公司 太阳电池及其制备方法和应用
CN115548144A (zh) * 2022-11-04 2022-12-30 安徽华晟新能源科技有限公司 半导体衬底及其处理方法、太阳能电池及其制备方法

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