WO2024092689A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2024092689A1
WO2024092689A1 PCT/CN2022/129755 CN2022129755W WO2024092689A1 WO 2024092689 A1 WO2024092689 A1 WO 2024092689A1 CN 2022129755 W CN2022129755 W CN 2022129755W WO 2024092689 A1 WO2024092689 A1 WO 2024092689A1
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Prior art keywords
well
contact
doped
region
highly
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PCT/CN2022/129755
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English (en)
Inventor
Sichao LI
Hui Yan
Chunhua Zhou
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Innoscience (suzhou) Semiconductor Co., Ltd.
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Application filed by Innoscience (suzhou) Semiconductor Co., Ltd. filed Critical Innoscience (suzhou) Semiconductor Co., Ltd.
Priority to CN202280044050.2A priority Critical patent/CN117616572A/zh
Priority to PCT/CN2022/129755 priority patent/WO2024092689A1/fr
Publication of WO2024092689A1 publication Critical patent/WO2024092689A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Definitions

  • the present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device.
  • the BCD (Bipolar-CMOS-DMOS) technology incorporates bipolar transistors, CMOS transistors and DMOS transistors on the same die.
  • the BCD technology can be used in power integrated circuits (IC) .
  • the BCD technology can be used in high-voltage integrated circuits (HVIC) .
  • a semiconductor device in some embodiments of the present disclosure, includes a substrate including a p-well; a first transistor; and a second transistor.
  • the first transistor includes a first high-voltage (HV) n-well in the p-well; a first source contact on the substrate; a first drain contact on the substrate; a first gate contact on the substrate and between the first source contact and the first drain contact.
  • the second transistor includes a second HV n-well in the p-well; a second source contact on the substrate; a second drain contact on the substrate; a second gate contact on the substrate and between the second source contact and the second drain contact.
  • a portion of the p-well is between the first HV n-well and the second HV n-well.
  • a method of manufacturing a semiconductor device includes: forming a p-well in a substrate; forming a first transistor; and forming a second transistor.
  • the first transistor includes a first high-voltage (HV) n-well in the p-well; a first source contact on the substrate; a first drain contact on the substrate; a first gate contact on the substrate and between the first source contact and the first drain contact.
  • the second transistor includes a second HV n-well in the p-well; a second source contact on the substrate; a second drain contact on the substrate; a second gate contact on the substrate and between the second source contact and the second drain contact.
  • a portion of the p-well is between the first HV n-well and the second HV n-well.
  • a semiconductor device in some embodiments of the present disclosure, includes: a substrate including a p-well; a first HV n-well in the p-well; a second HV n-well in the p-well; an HV p-body between the first HV n-well and the second HV n-well; a first source contact on the HV p-body; a first drain contact on the first HV n-well; a first gate contact on the HV p-body and between the first source contact and the first drain contact; a second source contact on the HV p-body; a second drain contact on the second HV n-well; and a second gate contact on the HV p-body and between the second source contact and the second drain contact.
  • a semiconductor device in some embodiments of the present disclosure, includes: a substrate including a first p-well and a second p-well; an n-type buried layer in the substrate and under the first p-well; an n-well in the substrate, wherein the n-well and the n-type buried layer together surround the first p-well; a first transistor; a second transistor; a first contact; and a second contact.
  • the first transistor includes a first source contact on the first p-well; a first drain contact on the first p-well; a first gate contact on the first p-well and between the first source contact and the first drain contact.
  • the second transistor includes a second source contact on the second p-well; a second drain contact on the second p-well; and a second gate contact on the second p-well and between the second source contact and the second drain contact.
  • the first contact and the second contact are on the first p-well.
  • the first contact and the second contact are electrically connected to the first p-well.
  • a method of manufacturing a semiconductor device includes: forming a first p-well and a second p-well in a substrate; forming an n-type buried layer in the substrate and under the first p-well; forming an n-well in the substrate, wherein the n-well and the n-type buried layer together surround the first p-well; forming a first transistor; forming a second transistor; forming a first contact; and forming a second contact.
  • the first transistor includes a first source contact on the first p-well; a first drain contact on the first p-well; a first gate contact on the first p-well and between the first source contact and the first drain contact.
  • the second transistor includes a second source contact on the second p-well; a second drain contact on the second p-well; and a second gate contact on the second p-well and between the second source contact and the second drain contact.
  • the first contact and the second contact are formed on the first p-well.
  • the first contact and the second contact are electrically connected to the first p-well.
  • a semiconductor device in some embodiments of the present disclosure, includes: a substrate including a first p-well and a second p-well; an n-type buried layer in the substrate and under the first p-well; an n-well in the substrate, wherein the n-well and the n-type buried layer together surround the first p-well; a first transistor; a second transistor; a first isolation structure; and a second isolation structure.
  • the first transistor includes a first high-voltage (HV) n-well in the first p-well; a first HV p-body in the first p-well, wherein the first HV p-body is in contact with the first HV n-well; a first source contact on the first HV p-body; a first drain contact on the first HV n-well; and a first gate contact on the first HV p-body and between the first source contact and the first drain contact.
  • HV high-voltage
  • the second transistor includes a second high-voltage (HV) n-well in the second p-well; a second HV p-body in the second p-well, wherein the second HV p-body is in contact with the second HV n-well; a second source contact on the second HV p-body; a second drain contact on the second HV n-well; and a second gate contact on the second HV p-body and between the second source contact and the second drain contact.
  • the first isolation structure is between the first HV p-body and the first p-well.
  • the second isolation structure is between the first HV n-well and the first p-well.
  • a semiconductor device in some embodiments of the present disclosure, includes: a substrate including an insulating layer buried in the substrate; a first transistor; a second transistor; and an isolation structure between the first transistor and the second transistor, wherein the isolation structure extends from an upper surface of the substrate to the insulating layer.
  • the first transistor includes a first high-voltage (HV) n-well in the substrate and on the insulating layer; and a first HV p-body in the substrate and on the insulating layer, wherein the first HV p-body is in contact with the first HV n-well.
  • HV high-voltage
  • the second transistor includes a second high-voltage (HV) n-well in the substrate and on the insulating layer; and a second HV p-body in the substrate and on the insulating layer, wherein the second HV p-body is in contact with the second HV n-well.
  • HV high-voltage
  • a method of manufacturing a semiconductor device includes: providing a substrate including an insulating layer buried in the substrate; forming a first transistor; forming a second transistor; and forming an isolation structure between the first transistor and the second transistor, wherein the isolation structure extends from an upper surface of the substrate to the insulating layer.
  • the first transistor includes a first high-voltage (HV) n-well in the substrate and on the insulating layer; and a first HV p-body in the substrate and on the insulating layer, wherein the first HV p-body is in contact with the first HV n-well.
  • HV high-voltage
  • the second transistor includes a second high-voltage (HV) n-well in the substrate and on the insulating layer; and a second HV p-body in the substrate and on the insulating layer, wherein the second HV p-body is in contact with the second HV n-well.
  • HV high-voltage
  • a semiconductor device in some embodiments of the present disclosure, includes: a substrate including an insulating layer buried in the substrate; a first transistor; a second transistor; a third transistor; a first isolation structure between the first transistor and the second transistor, wherein the first isolation structure extends from an upper surface of the substrate to the insulating layer; and a second isolation structure between the second transistor and the third transistor, wherein the second isolation structure extends from an upper surface of the substrate to the insulating layer.
  • the first transistor includes a first high-voltage (HV) n-well in the substrate and on the insulating layer; and a first HV p-body in the substrate and on the insulating layer, wherein the first HV p-body is in contact with the first HV n-well.
  • the second transistor includes a second high-voltage (HV) n-well in the substrate and on the insulating layer; and a second HV p-body in the substrate and on the insulating layer, wherein the second HV p-body is in contact with the second HV n-well.
  • the third transistor includes a third high-voltage (HV) n-well in the substrate and on the insulating layer; and a third HV p-body in the substrate and on the insulating layer, wherein the second HV p-body is in contact with the second HV n-well.
  • HV high-voltage
  • the semiconductor device reduces parasitic resistance and parasitic inductance resulting from the conductive wire (s) connecting high-side transistors and low-side transistors.
  • the performance of the semiconductor device is improved.
  • the current uniformity is improved, especially under high frequency switching status.
  • FIG. 1 is a schematic circuit diagram in accordance with some embodiments of the present disclosure.
  • FIG. 2 illustrates a top view of a semiconductor device in accordance with some comparative embodiments of the present disclosure.
  • FIG. 3 illustrates a cross-sectional view of a semiconductor device taken along line A-A' shown in FIG. 2 in accordance with some comparative embodiments of the present disclosure.
  • FIG. 4 illustrates a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure.
  • FIG. 5 illustrates a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure.
  • FIG. 6 illustrates a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure.
  • FIG. 7A, FIG. 7B, FIG. 7C, FIG. 7D, FIG. 7E, FIG. 7F and FIG. 7G illustrate some operations to manufacture a semiconductor device in accordance with some embodiments of the present disclosure.
  • FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, FIG. 8E, FIG. 8F, FIG. 8G and FIG. 8H illustrate some operations to manufacture a semiconductor device in accordance with some embodiments of the present disclosure.
  • FIG. 9A, FIG. 9B, FIG. 9C, FIG. 9D, FIG. 9E and FIG. 9F illustrate some operations to manufacture a semiconductor device in accordance with some embodiments of the present disclosure.
  • first and second features are formed in direct contact
  • additional features may have formed between the first and second features, such that the first and second features may not be in direct contact
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • an upper surface of a substrate refers to a surface of the substrate on which another element (s) (such as a layer (s) ) is disposed.
  • a lower surface of the substrate refers to a surface of the substrate opposite to the upper surface of the substrate.
  • a lower surface of an element refers to a surface of the element facing the substrate if the element is disposed on the substrate.
  • an upper surface of an element refers to a surface of the element facing away the substrate if the element is disposed on the substrate.
  • a lower surface of an element refers to a surface of the element relatively close to the substrate in comparison with an upper surface of the element if the element is disposed on the substrate.
  • a lower surface of an element refers to a surface of the element facing the lower surface of the substrate if the element is disposed in the substrate.
  • an upper surface of an element refers to a surface of the element facing away the lower surface of the substrate if the element is disposed in the substrate.
  • a lateral surface of an element refers to a surface of the element connecting the upper surface and the lower surface of the element.
  • a lateral surface of an element refers to a surface of the element connecting the upper surface and the lower surface of the element in a cross-sectional view.
  • a p-body may refer to a p-type doped region.
  • a p-well may refer to a p-type doped region.
  • a highly-doped p-region may refer to a p-type doped region.
  • a highly-doped p-region may have a smaller volume or a smaller cross-sectional area than that of a p-body.
  • a p-body may have a smaller volume or a smaller cross-sectional area than that of a p-well.
  • a highly-doped p-region may have dopant concentration approximately one to two orders of the magnitude higher than those in a p-body.
  • a highly-doped p-region may function to reduce the contact resistance between a metal contact and a p-body.
  • a highly-doped p-region may have a dopant concentration approximately one to two orders of the magnitude higher than those in a p-well.
  • a highly-doped p-region may function to reduce the contact resistance between a metal contact and a p-well.
  • An n-body may refer to an n-type doped region.
  • An n-well may refer to an n-type doped region.
  • a highly-doped n-region may refer to an n-type doped region.
  • a highly-doped n-region may have a smaller volume or a smaller cross-sectional area than that of an n-body.
  • An n-body may have a smaller volume or a smaller cross-sectional area than that of an n-well.
  • a highly-doped n-region may have a dopant concentration higher than that of an n-type buried layer.
  • An n-type buried layer may have a dopant concentration higher than that of an n-well.
  • An n-well may have a dopant concentration higher than that of a high-voltage (HV) n-well.
  • HV high-voltage
  • a highly-doped n-region may function to reduce the contact resistance between a metal contact and an n-well.
  • a p-well may surround an n-well.
  • a p-well may surround a p-body.
  • a p-well may surround an n-body.
  • An n-well may surround a p-well.
  • An n-well may surround a p-body.
  • An n-well may surround an n-body.
  • a p-body may surround an n-body.
  • a p-body may surround a highly-doped p-region.
  • a p-body may surround a highly-doped n-region.
  • a p-body and a highly-doped n-region surrounded by the p-body may form a p-n junction.
  • An n-body may surround a p-body.
  • An n-body may surround a highly-doped p-region.
  • An n-body and a highly-doped p-region surrounded by the n-body may form a p-n junction.
  • An n-body may surround a highly-doped n-region.
  • a high-voltage (HV) p-well refers to a p-well used in an active region of a transistor.
  • a high-voltage (HV) n-well refers to an n-well used in an active region of a transistor.
  • a high-voltage (HV) p-body refers to a p-body used in an active region of a transistor.
  • a high-voltage (HV) n-body refers to an n-body used in an active region of a transistor.
  • FIG. 1 is a schematic circuit diagram in accordance with some embodiments of the present disclosure.
  • the schematic circuit diagram of FIG. 1 shows a half-bridge circuit 1.
  • the half-bridge circuit 1 includes a transistor 10 and a transistor 12.
  • the transistor 10 and the transistor 12 are electrically connected in series.
  • the transistor 10 includes a source terminal 102, a drain terminal 104 and a gate terminal 106.
  • the transistor 10 further includes a substrate terminal (not shown in FIG. 1) .
  • the transistor 12 includes a source terminal 122, a drain terminal 124 and a gate terminal 126.
  • the transistor 12 further includes a substrate terminal (not shown in FIG. 1) .
  • the source terminal 102 of the transistor 10 and the drain terminal 124 of the transistor 12 are connected to the same potential at a switch node (SW) .
  • the drain terminal 104 of the transistor 10 is connected to a voltage supply (V in ) .
  • the substrate terminal of the transistor 10 is connected to the switch node (SW) .
  • the source terminal 122 of the transistor 12 is connected to ground (GND) .
  • the substrate terminal of the transistor 12 is connected to ground (GND) .
  • the transistor 10 may be referred to as a high-side (HS) transistor.
  • the transistor 12 may be referred to as a low-side (LS) transistor.
  • FIG. 2 illustrates a top view of a semiconductor device 2 in accordance with some comparative embodiments of the present disclosure.
  • FIG. 3 illustrates a cross-sectional view of the semiconductor device 2 taken along line A-A' shown in FIG. 2 in accordance with some comparative embodiments of the present disclosure.
  • the semiconductor device 2 includes a device region 20 and a device region 22.
  • the device region 20 includes source contacts 202, drain contacts 204 and gate contacts 206.
  • the source contacts 202, the drain contacts 204 and the gate contacts 206 are arranged interdigitatedly in the device region 20.
  • the source contacts 202, the drain contacts 204 and the gate contacts 206 are arranged alternatively in the device region 20.
  • a set of one source contact 202, one neighboring gate contact 206 and one neighboring drain contact 204 corresponds to one transistor, such as a transistor 20A, 20B, 20C or 20D shown in FIG. 3.
  • a plurality of the transistors 20A, 20B, 20C and 20D are electrically connected in parallel in the device region 20 to overall function as the transistor 10 shown in FIG. 1.
  • the number of transistors in the device region 20 shown in FIG. 3 are merely for illustration.
  • the number of transistors in the device region 20 is not particularly limited and may be up to hundreds or even thousands as needed.
  • the device region 22 includes source contacts 222, drain contacts 224 and gate contacts 226.
  • the source contacts 222, the drain contacts 224 and the gate contacts 226 are arranged interdigitatedly in the device region 22.
  • the source contacts 222, the drain contacts 224 and the gate contacts 226 are arranged alternately in the device region 22.
  • a set of one source contact 222, one neighboring gate contact 226 and one neighboring drain contact 224 corresponds to one transistor, such as a transistor 22A, 22B, 22C or 22D shown in FIG. 3.
  • a plurality of the transistors 22A, 22B, 22C and 22D are electrically connected in parallel in the device region 22 to overall function as the transistor 22 shown in FIG. 1.
  • the number of transistors in the device region 22 shown in FIG. 3 are merely for illustration.
  • the number of transistors in the device region 22 is not particularly limited and may be up to hundreds or even thousands as needed.
  • a p-well 213 surrounds the transistors 20A, 20B, 20C and 20D.
  • Contacts 201 and 203 are electrically connected to the p-well 213.
  • the contact 201 and 203 may be referred to as substrate contacts of the device region 20.
  • a p-well 233 surrounds the transistors 22A, 22B, 22C and 22D.
  • Contacts 221 and 223 are electrically connected to the p-well 233.
  • the contact 221 and 223 may be referred to as substrate contacts of the device region 22.
  • An n-well 211 together with an n-type buried layer 210 surrounds the p-well 213.
  • the n-well 211 and the n-type buried layer 210 form a p-n junction with the p-well 213 as an isolation ring.
  • the isolation ring surrounds the transistors 20A, 20B, 20C and 20D.
  • the isolation ring isolates the transistors 20A, 20B, 20C and 20D from the transistors 22A, 22B, 22C and 22D.
  • Contacts 205 and 207 are electrically connected to the n-well 211.
  • the contacts 205 and 207 may be referred to as isolation pickup contacts.
  • the device region 20 is electrically connected to the device region 22 in series.
  • the source contacts 202 of the device region 20 and the drain contacts 224 of the device region 22 are electrically connected to each other through a conductive wire (s) (not shown) .
  • the source contacts 202 of the device region 20 and the drain contacts 224 of the device region 22 are electrically connected to the same potential at a switch node (SW) .
  • the drain contacts 204 of the device region 20 are electrically connected to a voltage supply (V in ) .
  • the substrate contacts 201 and 203 are electrically connected to the switch node (SW) .
  • the isolation pickup contacts 205 and 207 are electrically connected to a voltage supply (V in ) .
  • the source contacts 222 of the device region 22 are electrically connected to ground (GND) .
  • the substrate contacts 221 and 223 are electrically connected to ground (GND) .
  • the semiconductor device 2 includes the device region 20 functioning as the transistor 10 shown in FIG. 1 and the device region 22 functioning as the transistor 12 shown in FIG. 1 to build a half-bridge circuit.
  • the device region 20 may be referred to as a high-side (HS) device region.
  • the device region 22 may be referred to as a low-side (LS) device region.
  • the transistors 20A, 20B, 20C and 20D may be referred to as high-side (HS) transistors.
  • the transistors 22A, 22B, 22C and 22D may be referred to as low-side (LS) transistors.
  • the conductive wire (s) (not shown) for connecting the source contacts 202 of the device region 20 and the drain contacts 224 of the device region 22 may introduce parasitic resistance or parasitic inductance, resulting in spike or surge in the voltage (V ds ) between the source and the drain during switching on and off at high speed.
  • the voltage spike or surge may increase the power loss of system, and even damage the semiconductor device 2.
  • the semiconductor device 2 can be designed so as to withstand a higher voltage than an input voltage. For example, for an input voltage of 10V, the semiconductor device 2 can be designed as if it is for an input voltage of 20V. However, such design may compromise the performance of the semiconductor device and cause loss.
  • the conductive wire (s) may take a relatively large area, resulting in a relatively large size of the semiconductor device.
  • the present disclosure provides semiconductor devices and methods of manufacturing semiconductor devices.
  • the semiconductor devices are manufactured by the BCD technology.
  • the semiconductor devices include a half-bridge circuit.
  • the layout of the semiconductor devices allow the conductive wire (s) for connecting a high-side transistor and a low-side transistor to be made with a smaller dimension (e.g., a smaller length) . As a result, the issue of the voltage spike or surge can be alleviated and the miniaturization of the semiconductor devices can be improved.
  • FIG. 4 illustrates a cross-sectional view of a semiconductor device 3 in accordance with some embodiments of the present disclosure.
  • the semiconductor device 3 includes a substrate 301, a p-well 313, transistors 30 and transistors 32.
  • the substrate 301 may include, for example, but is not limited to, silicon (Si) , doped silicon (doped Si) , silicon carbide (SiC) , germanium silicide (SiGe) , gallium arsenide (GaAs) , or other semiconductor materials.
  • the substrate 301 may include an intrinsic semiconductor material.
  • the substrate 301 may include a p-type semiconductor material.
  • the substrate 501 may include a silicon layer doped with boron (B) .
  • the substrate 501 may include a silicon layer doped with gallium (Ga) .
  • the substrate 301 may further include a doped region, such as a p-well, an n-well, or the like.
  • the substrate 301 may include, for example, but is not limited to, sapphire, silicon on insulator (SOI) , or other suitable materials.
  • the p-well 313 is within the substrate 301.
  • the p-well 313 is located closer to an upper surface of the substrate 301 than to a lower surface of the substrate 301.
  • An upper surface of the p-well 313 may be coplanar with the upper surface of the substrate 301.
  • a lowest surface of the p-well 313 may be higher than the lowest surface of the substrate 301. From a cross-sectional view as shown in FIG. 4, the p-well 313 surrounds the transistors 30 and the transistors 32. From a top view (not shown) , the p-well 313 may surround the transistors 30 and the transistors 32.
  • the transistors 30 and the transistors 32 are disposed alternately along a direction D.
  • One transistor 30 and one neighboring transistor 32 constitute a cell 300.
  • a plurality of the cells 300 are arranged repeatedly along the direction D.
  • One transistor 30 includes a source contact 302, a drain contact 304 and a gate contact 306.
  • the source contact 302 may extend along a direction substantially perpendicular to the direction D.
  • the drain contact 304 may extend along a direction substantially perpendicular to the direction D.
  • the gate contact 306 may extend along a direction substantially perpendicular to the direction D.
  • the source contact 302, the drain contact 304 and the gate contact 306 may include, for example, but is not limited to, a metal, such as Al, Ti, the like, or a combination thereof.
  • the source contact 302 is on the upper surface of the substrate 301.
  • the drain contact 304 is on the upper surface of the substrate 301.
  • the gate contact 306 is on the upper surface of the substrate 301.
  • the gate contact 306 is between the source contact 302 and the drain contact 304.
  • the transistor 30 includes a high-voltage (HV) n-well 317 in the substrate 301.
  • An upper surface of the HV n-well 317 may be coplanar with the upper surface of the substrate 301.
  • the high-voltage (HV) n-well 317 is within the p-well 313.
  • the upper surface of the HV n-well 317 may be coplanar with the upper surface of the p-well 313.
  • a lowest surface of the HV n- well 317 may be higher than the lowest surface of the p-well 313.
  • the HV n-well 317 may be in contact with the p-well 313.
  • the HV n-well 317 may have an interface with the p-well 313.
  • the interface between the HV n-well 317 and the p-well 313 is a p-n junction.
  • the drain contact 304 is on the HV n-well 317.
  • the drain contact 304 is on the upper surface of the HV n-well 317.
  • the HV n-well 317 is under the drain contact 304.
  • the transistor 30 includes a high-voltage (HV) p-body 315 in the substrate 301.
  • An upper surface of the HV p-body 315 may be coplanar with the upper surface of the substrate 301.
  • the high-voltage (HV) p-body 315 is within the p-well 313.
  • the upper surface of the HV p-body 315 may be coplanar with the upper surface of the p-well 313.
  • a lowest surface of the HV p-body 315 is higher than the lowest surface of the p-well 313.
  • the HV p-body 315 may be in contact with the p-well 313.
  • the HV p-body 315 may have an interface with the p-well 313.
  • the source contact 302 may be on the HV p-body 315.
  • the source contact 302 may be on the upper surface of the HV p-body 315.
  • the HV p-body 315 may be under the source contact 302.
  • the gate contact 306 may be on the HV p-body 315.
  • the gate contact 306 may be on the upper surface of the HV p-body 315.
  • the HV p-body 315 may be under the gate contact 306.
  • the HV p-body 315 may be in contact with the HV n-well 317.
  • the HV p-body 315 may have an interface with the HV n-well 317.
  • the gate contact 306 may be on the interface between the HV p-body 315 and the HV n-well 317.
  • the transistor 30 includes a highly-doped n-region 312 in the HV p-body 315.
  • An upper surface of the highly-doped n-region 312 may be coplanar with the upper surface of the HV p-body 315.
  • a lowest surface of the highly-doped n-region 312 may be higher than the lowest surface of the HV p-body 315.
  • the source contact 302 is on the highly-doped n-region 312.
  • the source contact 302 is on the upper surface of the highly-doped n-region 312.
  • the highly-doped n-region 312 is under the source contact 302.
  • the source contact 302 is in contact with the highly-doped n-region 312.
  • the transistor 30 includes a highly-doped n-region 314 in the HV n-well 317.
  • An upper surface of the highly-doped n-region 314 may be coplanar with the upper surface of the HV n-well 317.
  • a lowest surface of the highly-doped n-region 314 may be higher than the lowest surface of the HV n-well 317.
  • the drain contact 304 is on the highly-doped n-region 314.
  • the drain contact 304 is on the upper surface of the highly-doped n-region 314.
  • the highly-doped n-region 314 is under the drain contact 304.
  • the drain contact 304 is in contact with the highly-doped n-region 314.
  • one transistor 32 includes a source contact 322, a drain contact 324 and a gate contact 326.
  • the source contact 322 may extend along a direction substantially perpendicular to the direction D.
  • the drain contact 324 may extend along a direction substantially perpendicular to the direction D.
  • the gate contact 326 may extend along a direction substantially perpendicular to the direction D.
  • the source contact 322, the drain contact 324 and the gate contact 326 may include, for example, but is not limited to, a metal, such as Al, Ti, the like, or a combination thereof.
  • the source contact 322 is on the upper surface of the substrate 301.
  • the drain contact 324 is on the upper surface of the substrate 301.
  • the gate contact 326 is on the upper surface of the substrate 301.
  • the gate contact 326 is between the source contact 322 and the drain contact 324.
  • the transistor 32 includes a high-voltage (HV) n-well 337 in the substrate 301.
  • An upper surface of the HV n-well 337 may be coplanar with the upper surface of the substrate 301.
  • the high-voltage (HV) n-well 337 is within the p-well 313.
  • the upper surface of the HV n-well 337 may be coplanar with the upper surface of the p-well 313.
  • a lowest surface of the HV n-well 337 may be higher than the lowest surface of the p-well 313.
  • the HV n-well 337 may be in contact with the p-well 313.
  • the HV n-well 337 may have an interface with the p-well 313.
  • the interface between the HV n-well 337 and the p-well 313 is a p-n junction.
  • the drain contact 324 is on the HV n-well 337.
  • the drain contact 324 is on the upper surface of the HV n-well 337.
  • the HV n-well 337 is under the drain contact 304.
  • the transistor 32 includes a high-voltage (HV) p-body 335 in the substrate 301.
  • An upper surface of the HV p-body 335 may be coplanar with the upper surface of the substrate 301.
  • the high-voltage (HV) p-body 335 is within the p-well 313.
  • the upper surface of the HV p-body 335 may be coplanar with the upper surface of the p-well 313.
  • a lowest surface of the HV p-body 335 may be higher than the lowest surface of the p-well 313.
  • the HV p-body 335 may be in contact with the p-well 313.
  • the HV p-body 335 may have an interface with the p-well 313.
  • the source contact 322 is on the HV p-body 335.
  • the source contact 322 may be on the upper surface of the HV p-body 335.
  • the HV p-body 335 may be under the source contact 322.
  • the gate contact 326 may be on the HV p-body 335.
  • the gate contact 326 may be on the upper surface of the HV p-body 335.
  • the HV p-body 335 may be under the gate contact 326.
  • the HV p-body 335 may be in contact with the HV n-well 337.
  • the HV p-body 335 may have an interface with the HV n-well 337.
  • the gate contact 326 may be on the interface between the HV p-body 335 and the HV n-well 337.
  • the HV p-body 335 and the HV p-body 315 may be simultaneously formed.
  • the HV p-body 335 and the HV p-body 315 may together constitute an HV p-body between the HV n-well 337 and the HV n-well 317.
  • the transistor 32 includes a highly-doped n-region 332 in the HV p-body 335.
  • An upper surface of the highly-doped n-region 332 may be coplanar with the upper surface of the HV p-body 335.
  • a lowest surface of the highly-doped n-region 332 may be higher than the lowest surface of the HV p-body 335.
  • the source contact 322 is on the highly-doped n-region 332.
  • the source contact 322 is on the upper surface of the highly-doped n-region 332.
  • the highly-doped n-region 332 is under the source contact 322.
  • the source contact 322 is in contact with the highly-doped n-region 332.
  • the transistor 32 includes a highly-doped n-region 334 in the HV n-well 337.
  • An upper surface of the highly-doped n-region 334 may be coplanar with the upper surface of the HV n-well 337.
  • a lowest surface of the highly-doped n-region 334 may be higher than the lowest surface of the HV n-well 337.
  • the drain contact 324 is on the highly-doped n-region 334.
  • the drain contact 324 is on the upper surface of the highly-doped n-region 334.
  • the highly-doped n-region 334 is under the drain contact 324.
  • the drain contact 324 is in contact with the highly-doped n-region 334.
  • a portion of the p-well 313 is between the transistor 30 and the transistor 32.
  • the portion of the p-well 313 is between the HV n-well 317 and the HV n-well 337.
  • the portion of the p-well 313 may be in contact with the HV n-well 317.
  • the portion of the p-well 313 may be in contact with the HV n-well 337.
  • the portion of the p-well 313 may have an interface with the HV n-well 317.
  • the portion of the p-well 313 may have an interface with the HV n-well 337.
  • the HV n-well 317 and the p-well 313 may form a p-n junction.
  • the p-well 313 and the HV n-well 337 may form a p-n junction.
  • the HV n-well 317, the p-well 313 and the HV n-well 337 may form an n-p-n junction. Therefore, the p-well 313 may isolate the transistor 30 from the transistor 32.
  • the semiconductor device 3 may further include a contact 352 on the substrate 301.
  • the contact 352 may include, for example, but is not limited to, a metal, such as Al, Ti, the like, or a combination thereof.
  • the contact 352 is on the upper surface of the substrate 301.
  • the contact 352 is between the transistor 30 and the transistor 32.
  • the contact 352 may be next to the drain contact 304.
  • the contact 352 may be next to the drain contact 324.
  • the contact 352 may be between the drain contact 304 and the drain contact 324.
  • the contact 352 is on the p-well 313.
  • the contact 352 is on the upper surface of the p-well 313.
  • the contact 352 may be on the portion of the p-well 313 between the HV n-well 317 and the HV n-well 337.
  • the contact 352 is electrically connected to the p-well 313.
  • the contact 352 may be referred to as a substrate contact.
  • the semiconductor device 3 may further include a highly-doped p-region 362 in the p-well 313.
  • An upper surface of the highly-doped p-region 362 may be coplanar with the upper surface of the substrate 301.
  • An upper surface of the highly-doped p-region 362 may be coplanar with the upper surface of the p-well 313.
  • a lowest surface of the highly-doped p-region 362 is higher than the lowest surface of the p-well 313.
  • the highly-doped p-region 362 may be between the transistor 30 and the transistor 32.
  • the highly-doped p-region 362 may be between the HV n-well 317 and the HV n-well 337.
  • the highly-doped p-region 362 may be between the highly-doped n-region 314 and the highly-doped n-region 334.
  • the highly-doped p-region 362 is under the contact 352.
  • the contact 352 is on the highly-doped p-region 362.
  • the contact 352 is in contact with the highly-doped p-region 362.
  • the semiconductor device 3 may further include an isolation structure 372, 374 or 376.
  • the isolation structure 372, 374 or 376 may be a shallow trench isolation (STI) structure.
  • the isolation structure 372, 374 or 376 may include, for example, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or other suitable insulating material, or a combination thereof.
  • the isolation structure 372 is between the transistor 30 and the p-well 313.
  • the isolation structure 372 may be between the HV n-well 317 and the p-well 313.
  • the isolation structure 372 may be on an interface between the HV n-well 317 and the p-well 313.
  • the isolation structure 372 may be between the drain contact 304 and the contact 352.
  • the isolation structure 372 may be between the highly-doped n-region 314 and the highly-doped p-region 362.
  • the isolation structure 372 may contact the highly-doped n-region 314.
  • the isolation structure 372 may contact the highly-doped p-region 362.
  • the isolation structure 372 may isolate the highly-doped n-region 314 from the highly-doped p-region 362.
  • the isolation structure 372 may isolate the highly-doped n-region 314 from the p-well 313.
  • the isolation structure 372 may isolate the highly-doped p-region 362 from the HV n-well 317.
  • An upper surface of the isolation structure 372 may be coplanar with the upper surface of the substrate 301.
  • the upper surface of the isolation structure 372 may be coplanar with the upper surface of the HV n-well 317.
  • the upper surface of the isolation structure 372 may be coplanar with the upper surface of the p-well 313.
  • the upper surface of the isolation structure 372 may be coplanar with the upper surface of the highly-doped n-region 314.
  • the upper surface of the isolation structure 372 may be coplanar with the upper surface of the highly-doped p-region 362.
  • the lowest surface of the isolation structure 372 may be lower than the lowest surface of the highly-doped n-region 314.
  • the lowest surface of the isolation structure 372 may be lowest than the lower surface of the highly-doped p-region 362.
  • the isolation structure 374 is between the transistor 32 and the p-well 313.
  • the isolation structure 374 may be between the HV n-well 337 and the p-well 313.
  • the isolation structure 374 may be on an interface between the HV n-well 337 and the p-well 313.
  • the isolation structure 374 may be between the drain contact 324 and the contact 352.
  • the isolation structure 374 may be between the highly-doped n-region 334 and the highly-doped p-region 362.
  • the isolation structure 374 may contact the highly-doped n-region 334.
  • the isolation structure 374 may contact the highly-doped p-region 362.
  • the isolation structure 374 may isolate the highly-doped n-region 334 from the highly-doped p-region 362.
  • the isolation structure 374 may isolate the highly-doped n-region 334 from the p-well 313.
  • the isolation structure 374 may isolate the highly-doped p-region 362 from the HV n-well 337.
  • An upper surface of the isolation structure 374 may be coplanar with the upper surface of the substrate 301.
  • the upper surface of the isolation structure 374 may be coplanar with the upper surface of the HV n-well 337.
  • the upper surface of the isolation structure 374 may be coplanar with the upper surface of the p-well 313.
  • the upper surface of the isolation structure 374 may be coplanar with the upper surface of the highly-doped n-region 334.
  • the upper surface of the isolation structure 374 may be coplanar with the upper surface of the highly-doped p-region 362.
  • the lowest surface of the isolation structure 374 may be lower than the lowest surface of the highly-doped n-region 334.
  • the lowest surface of the isolation structure 374 may be lower than the lowest surface of the highly-doped p-region 362.
  • the isolation structure 376 is between the HV p-body 335 and the HV p-body 315.
  • the isolation structure 376 is between the highly-doped n-region 332 and the highly-doped n-region 312.
  • the isolation structure 376 may be in an HV p-body constituted by the HV p-body 335 and the HV p-body 315.
  • the isolation structure 376 isolates the highly-doped n-region 332 from the highly-doped n-region 312.
  • the isolation structure 376 may be between the source contact 322 and the source contact 302.
  • An upper surface of the isolation structure 376 may be coplanar with the upper surface of the substrate 301.
  • the upper surface of the isolation structure 376 may be coplanar with the upper surface of the HV p-body 335.
  • the upper surface of the isolation structure 376 may be coplanar with the upper surface of the HV p-body 315.
  • the lowest surface of the isolation structure 376 may be lower than the lowest surface of the highly-doped n-region 332.
  • the lowest surface of the isolation structure 376 may be lower than the lowest surface of the highly-doped n-region 312.
  • the transistor 30 may be electrically connected to the transistor 32 in series.
  • the source contact 302 of the transistor 30 may be electrically connected to the drain contact 324 of the transistor 32.
  • the source contact 302 and the drain contact 324 may be electrically connected to the same potential at a switch node (SW) .
  • the source contact 302 may be electrically connected to the drain contact 324 through a conductive wire (not shown) .
  • the drain contact 304 of the transistor 30 may be electrically connected to a voltage supply (V in ) .
  • the source contact 322 of the transistor 32 may be electrically connected to ground (GND) .
  • the transistor 30 may be represented by the transistor 10 shown in FIG. 1.
  • the transistor 30 may be referred to as a high-side (HS) transistor.
  • the transistor 32 may be represented by the transistor 12 shown in FIG. 1.
  • the transistor 32 may be referred to as a low-side (LS) transistor.
  • a plurality of the cells 300 may be electrically connected to each other in parallel to overall build a half-bridge circuit.
  • the contacts 352 may be electrically connected to ground (GND) .
  • the p-well 313 may be electrically connected to ground (GND) .
  • the p-well 313 under the transistors 30 and the transistors 32 are electrically connected to ground (GND) and may be referred to as common GND.
  • the semiconductor device 3 shown in FIG. 4 is compared to the semiconductor device 2 shown in FIG. 3.
  • the conductive wire (s) for connecting the source contacts 302 of the transistors 30 and the drain contacts 324 the transistors 32 has a shorter length compared to the conductive wire (s) for connecting the source contacts 202 of the transistors 20A, 20B, 20C, 20D and the drain contacts 224 of the transistors 22A, 22B, 22C, 22D.
  • FIG. 5 illustrates a cross-sectional view of a semiconductor device 4 in accordance with some embodiments of the present disclosure.
  • the semiconductor device 4 is similar to the semiconductor device 3 except for at least the following differences.
  • the semiconductor device 4 includes a substrate 401, p-wells 413, p-wells 433, n-type buried layers 410, n-wells 411, transistors 30 and transistors 32.
  • the material of the substrate 401 may be similar to the material of the substrate 301.
  • the p-well 413 is within the substrate 401.
  • the p-well 413 is located closer to an upper surface of the substrate 401 than to a lower surface of the substrate 401.
  • An upper surface of the p-well 413 may be coplanar with the upper surface of the substrate 401.
  • a lowest surface of the p-well 413 may be higher than the lowest surface of the substrate 401. From a cross-sectional view as shown in FIG. 5, the p-well 413 surrounds the transistor 30. From a top view (not shown) , the p-well 413 may surround the transistor 30.
  • the p-well 433 is within the substrate 401.
  • the p-well 433 is located closer to an upper surface of the substrate 401 than to a lower surface of the substrate 401.
  • An upper surface of the p-well 433 may be coplanar with the upper surface of the substrate 401.
  • a lowest surface of the p-well 433 may be higher than the lowest surface of the substrate 401.
  • the p-well 433 is formed next to the p-well 413.
  • the p-wells 413 and the p-wells 433 may be arranged alternately along the direction D as shown in FIG. 5. From a cross-sectional view as shown in FIG. 5, the p-well 433 surrounds the transistor 32. From a top view (not shown) , the p-well 413 may surround the transistor 32.
  • the n-type buried layer 410 is within the substrate 401.
  • the n-type buried layer 410 is disposed under the p-well 413.
  • the n-type buried layer 410 is disposed between the lowest surface of the p-well 413 and the lower surface of the substrate 401.
  • the n-type buried layer 410 may be in contact with the p-well 413.
  • the n-type buried layer 410 may be in contact with the lowest surface of the p-well 413.
  • the n-well 411 is within the substrate 401.
  • An upper surface of the n-well 411 may be coplanar with the upper surface of the substrate 401.
  • a lowest surface of the n-well 411 may be higher than the lowest surface of the substrate 401.
  • the n-well 411 is between the p-well 413 and the p-well 433.
  • the n-well 411 may be in contact with the p-well 413.
  • the n-well 411 may be in contact with the p-well 433.
  • the n-well 411 may be formed on the n-type buried layer 410.
  • the n-well 411 may be in contact with the n-type buried layer 410.
  • the n-well 411 may be connected to the n-type buried layer 410. From a top view (not shown) , the n-well 411 may surround the p-well 413. From a top view (not shown) , the n-well 411 may surround the transistor 30. From a cross-sectional view as shown in FIG. 5, the n-well 411 and the n-type buried layer 410 together surround the p-well 413. From a cross-sectional view as shown in FIG. 5, the n-well 411 and the n-type buried layer 410 together surround the transistor 30.
  • the n-well 411 and the n-type buried layer 410 form a p-n junction with the p-well 413 as an isolation ring.
  • the isolation ring surrounds the p-well 413.
  • the isolation ring surrounds the transistor 30.
  • the isolation ring isolates the transistor 30 from the transistor 32.
  • the transistors 30 and the transistors 32 are disposed alternately along the direction D.
  • the transistor 30 may be on the p-well 413.
  • the transistor 30 may be surrounded by the p-well 413.
  • the transistor 32 may be on the p-well 433.
  • the transistor 32 may be surrounded by the p-well 433.
  • One transistor 30 and one neighboring transistor 32 constitute a cell 400.
  • a plurality of the cells 400 are arranged repeatedly along the direction D.
  • One transistor 30 includes a source contact 302, a drain contact 304 and a gate contact 306.
  • the source contact 302 is on the p-well 413.
  • the drain contact 304 is on the p-well 413.
  • the gate contact 306 is on the p-well 413.
  • the gate contact 306 is between the source contact 302 and the drain contact 304.
  • the transistor 30 includes a high-voltage (HV) n-well 317 in the substrate 401.
  • An upper surface of the HV n-well 317 may be coplanar with the upper surface of the substrate 401.
  • the high-voltage (HV) n-well 317 is within the p-well 413.
  • the upper surface of the HV n-well 317 may be coplanar with the upper surface of the p-well 413.
  • a lowest surface of the HV n-well 317 may be higher than the lowest surface of the p-well 413.
  • the HV n-well 317 may be in contact with the p-well 413.
  • the HV n-well 317 may have an interface with the p-well 413.
  • the interface between the HV n-well 317 and the p-well 413 is a p-n junction.
  • the transistor 30 includes a high-voltage (HV) p-body 315 in the substrate 401.
  • An upper surface of the HV p-body 315 may be coplanar with the upper surface of the substrate 401.
  • the high-voltage (HV) p-body 315 is within the p-well 413.
  • the upper surface of the HV p-body 315 may be coplanar with the upper surface of the p-well 413.
  • a lowest surface of the HV p-body 315 may be higher than the lowest surface of the p-well 413.
  • the HV p-body 315 may be in contact with the p-well 413.
  • the HV p-body 315 may have an interface with the p-well 413.
  • the transistor 32 includes a source contact 322, a drain contact 324 and a gate contact 326.
  • the source contact 322 is on the p-well 433.
  • the drain contact 324 is on the p-well 433.
  • the gate contact 326 is on the p-well 433.
  • the gate contact 326 is between the source contact 322 and the drain contact 324.
  • the transistor 32 includes a high-voltage (HV) n-well 337 in the substrate 401.
  • An upper surface of the HV n-well 337 may be coplanar with the upper surface of the substrate 401.
  • the high-voltage (HV) n-well 337 is within the p-well 433.
  • the upper surface of the HV n-well 337 may be coplanar with the upper surface of the p-well 433.
  • a lowest surface of the HV n-well 337 may be higher than the lowest surface of the p-well 433.
  • the HV n-well 337 may be in contact with the p-well 433.
  • the HV n-well 337 may have an interface with the p-well 433.
  • the interface between the HV n-well 337 and the p-well 433 is a p-n junction.
  • the transistor 32 includes a high-voltage (HV) p-body 335 in the substrate 401.
  • An upper surface of the HV p-body 335 may be coplanar with the upper surface of the substrate 401.
  • the high-voltage (HV) p-body 335 is within the p-well 433.
  • the upper surface of the HV p-body 335 may be coplanar with the upper surface of the p-well 433.
  • a lowest surface of the HV p-body 335 may be higher than the lowest surface of the p-well 433.
  • the HV p-body 335 may be in contact with the p-well 433.
  • the HV p-body 335 may have an interface with the p-well 433.
  • the semiconductor device 4 may further include a contact 452 on the substrate 401.
  • the contact 452 may include, for example, but is not limited to, a metal, such as Al, Ti, the like, or a combination thereof.
  • the contact 452 is on the upper surface of the substrate 401.
  • the contact 452 may be between the transistor 30 and the transistor 32.
  • the contact 452 may be next to the source contact 302.
  • the contact 452 is on the p-well 413.
  • the contact 452 is on the upper surface of the p-well 413.
  • the contact 452 may be on a portion of the p-well 413 between the HV p-body 315 and the n-well 411.
  • the contact 452 is electrically connected to the p-well 413.
  • the contact 452 may be referred to as a substrate contact.
  • the semiconductor device 4 may further include a highly-doped p-region 462 in the p-well 413.
  • An upper surface of the highly-doped p-region 462 may be coplanar with the upper surface of the p-well 413.
  • a lowest surface of the highly-doped p-region 462 is higher than the lowest surface of the p-well 413.
  • the highly-doped p-region 462 is between the transistor 30 and the transistor 32.
  • the highly-doped p-region 462 may be between the HV p-body 315 and the n-well 411.
  • the highly-doped p-region 462 may be next to the highly-doped n-region 312.
  • the highly-doped p-region 462 is under the contact 452.
  • the contact 452 is on the highly-doped p-region 462.
  • the contact 452 is in contact with the highly-doped p-region 462.
  • the semiconductor device 4 may further include a contact 472 on the substrate 401.
  • the contact 472 may include, for example, but is not limited to, a metal, such as Al, Ti, the like, or a combination thereof.
  • the contact 472 is on the upper surface of the substrate 401.
  • the contact 472 may be between the transistor 32 and the transistor 30.
  • the contact 472 may be next to the drain contact 304.
  • the contact 472 is on the p-well 413.
  • the contact 472 may be on the upper surface of the p-well 413.
  • the contact 472 may be on a portion of the p-well 413 between the n-well 411 and the HV n-well 317.
  • the contact 472 is electrically connected to the p-well 413.
  • the contact 472 may be referred to as a substrate contact.
  • the semiconductor device 4 may further include a highly-doped p-region 482 in the p-well 413.
  • An upper surface of the highly-doped p-region 482 may be coplanar with the upper surface of the p-well 413.
  • a lowest surface of the highly-doped p-region 482 is higher than the lowest surface of the p-well 413.
  • the highly-doped p-region 482 may be between the transistor 32 and the transistor 30.
  • the highly-doped p-region 482 may be between the n-well 411 and the HV n-well 317.
  • the highly-doped p-region 482 may be next to the highly-doped n-region 314.
  • the highly-doped p-region 482 is under the contact 472.
  • the contact 472 is on the highly-doped p-region 482.
  • the contact 472 is in contact with the highly-doped p-region 482.
  • the semiconductor device 4 may further include a contact 454 on the substrate 401.
  • the contact 454 may include, for example, but is not limited to, a metal, such as Al, Ti, the like, or a combination thereof.
  • the contact 454 is on the upper surface of the substrate 401.
  • the contact 454 may be between the transistor 30 and the transistor 32.
  • the contact 454 may be next to the contact 452.
  • the contact 452 may be between the source contact 302 and the contact 454.
  • the contact 454 is on the n-well 411.
  • the contact 454 may be on the upper surface of the n-well 411.
  • the contact 454 is electrically connected to the n-well 411.
  • the contact 454 may be referred to as an isolation pickup contact.
  • the semiconductor device 4 may further include a highly-doped n-region 464 in the n-well 411.
  • An upper surface of the highly-doped n-region 464 may be coplanar with the upper surface of the n-well 411.
  • a lowest surface of the highly-doped n-region 464 is higher than the lowest surface of the n-well 411.
  • the highly-doped n-region 464 is between the transistor 30 and the transistor 32.
  • the highly-doped n-region 464 may be between the p-well 413 and the p-well 433.
  • the highly-doped n-region 464 may be next to the highly-doped p-region 462.
  • the highly-doped n-region 464 is under the contact 454.
  • the contact 454 is on the highly-doped n-region 464.
  • the contact 454 is in contact with the highly-doped n-region 464.
  • the semiconductor device 4 may further include a contact 474 on the substrate 401.
  • the contact 474 may include, for example, but is not limited to, a metal, such as Al, Ti, the like, or a combination thereof.
  • the contact 474 is on the upper surface of the substrate 401.
  • the contact 474 may be between the transistor 32 and the transistor 30.
  • the contact 474 may be next to the contact 472.
  • the contact 472 may be between the contact 474 and the drain contact 304.
  • the contact 474 is on the n-well 411.
  • the contact 474 may be on the upper surface of the n-well 411.
  • the contact 474 is electrically connected to the n-well 411.
  • the contact 474 may be referred to as an isolation pickup contact.
  • the semiconductor device 4 may further include a highly-doped n-region 484 in the n-well 411.
  • An upper surface of the highly-doped n-region 484 may be coplanar with the upper surface of the n-well 411.
  • a lowest surface of the highly-doped n-region 484 is higher than the lowest surface of the n-well 411.
  • the highly-doped n-region 484 is between the transistor 30 and the transistor 32.
  • the highly-doped n-region 484 may be between the p-well 433 and the p-well 413.
  • the highly-doped n-region 484 may be next to the highly-doped p-region 482.
  • the highly- doped n-region 484 is under the contact 474.
  • the contact 474 is on the highly-doped n-region 484.
  • the contact 474 is in contact with the highly-doped n-region 484.
  • the semiconductor device 4 may further include a contact 456 on the substrate 401.
  • the contact 456 may include, for example, but is not limited to, a metal, such as Al, Ti, the like, or a combination thereof.
  • the contact 456 is on the upper surface of the substrate 401.
  • the contact 456 may be between the transistor 30 and the transistor 32.
  • the contact 456 may be next to the drain contact 324.
  • the contact 456 may be next to the contact 454.
  • the contact 456 may be between the contact 454 and the drain contact 324.
  • the contact 456 is on the p-well 433.
  • the contact 456 may be on the upper surface of the p-well 433.
  • the contact 456 may be on a portion of the p-well 433 between the n-well 411 and the HV n-well 337.
  • the contact 456 is electrically connected to the p-well 433.
  • the contact 456 may be referred to as a substrate contact.
  • the semiconductor device 4 may further include a highly-doped p-region 466 in the p-well 433.
  • An upper surface of the highly-doped p-region 466 may be coplanar with the upper surface of the p-well 433.
  • a lowest surface of the highly-doped p-region 466 is higher than the lowest surface of the p-well 433.
  • the highly-doped p-region 466 is between the transistor 30 and the transistor 32.
  • the highly-doped p-region 466 may be between the n-well 411 and the HV n-well 337.
  • the highly-doped p-region 466 may be next to the highly-doped n-region 334.
  • the highly-doped p-region 466 may be next to the highly-doped n-region 464.
  • the highly-doped p-region 466 may be between the highly-doped n-region 464 and the highly-doped n-region 334.
  • the highly-doped p-region 466 is under the contact 456.
  • the contact 456 is on the highly-doped p-region 466.
  • the contact 456 is in contact with the highly-doped p-region 466.
  • the semiconductor device 4 may further include a contact 476 on the substrate 401.
  • the contact 476 may include, for example, but is not limited to, a metal, such as Al, Ti, the like, or a combination thereof.
  • the contact 476 is on the upper surface of the substrate 401.
  • the contact 476 may be between the transistor 32 and the transistor 30.
  • the contact 476 may be next to the source contact 322.
  • the contact 476 may be next to the contact 474.
  • the contact 476 may be between the source contact 322 and the contact 474.
  • the contact 476 is on the p-well 433.
  • the contact 476 may be on the upper surface of the p-well 433.
  • the contact 476 may be on a portion of the p-well 433 between the HV p-body 335 and the n-well 411.
  • the contact 476 is electrically connected to the p-well 433.
  • the contact 476 may be referred to as a substrate contact.
  • the semiconductor device 4 may further include a highly-doped p-region 486 in the p-well 433.
  • An upper surface of the highly-doped p-region 486 may be coplanar with the upper surface of the p-well 433.
  • a lowest surface of the highly-doped p-region 486 is higher than the lowest surface of the p-well 433.
  • the highly-doped p-region 486 is between the transistor 32 and the transistor 30.
  • the highly-doped p-region 486 may be between the HV p-body 335 and the n-well 411.
  • the highly-doped p-region 486 may be next to the highly-doped n-region 332.
  • the highly-doped p-region 486 may be next to the highly-doped n-region 484.
  • the highly-doped p-region 486 may be between the highly-doped n-region 332 and the highly-doped n-region 484.
  • the highly-doped p-region 486 is under the contact 476.
  • the contact 476 is on the highly-doped p-region 486.
  • the contact 476 is in contact with the highly-doped p-region 486.
  • the semiconductor device 4 may further include an isolation structure 442, 444, 446, 448, 492, 494, 496 or 498.
  • the isolation structure 442, 444, 446, 448, 492, 494, 496 or 498 may be a shallow trench isolation (STI) structure.
  • the isolation structure 442, 444, 446, 448, 492, 494, 496 or 498 may include, for example, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or other suitable insulating material, or a combination thereof.
  • the isolation structure 442 may be between the transistor 30 and the transistor 32.
  • the isolation structure 442 may be between the transistor 30 and the p-well 413.
  • the isolation structure 442 may be between the HV p-body 315 and the p-well 413.
  • the isolation structure 442 may be on an interface between the HV p-body 315 and the p-well 413.
  • the isolation structure 442 may be between the source contact 302 and the contact 452.
  • the isolation structure 442 may be between the highly-doped n-region 312 and the highly-doped p-region 462.
  • the isolation structure 442 may be in contact with the highly-doped n-region 312.
  • the isolation structure 442 may be in contact with the highly-doped p-region 462.
  • the isolation structure 442 may isolate the highly-doped n-region 312 from the highly-doped p-region 462.
  • the isolation structure 442 may isolate the highly-doped n-region 312 from the p-well 413.
  • the isolation structure 442 may isolate the highly-doped p-region 462 from the HV p-body 315.
  • An upper surface of the isolation structure 442 may be coplanar with the upper surface of the substrate 401.
  • the upper surface of the isolation structure 442 may be coplanar with the upper surface of the HV p-body 315.
  • the upper surface of the isolation structure 442 may be coplanar with the upper surface of the p-well 413.
  • the upper surface of the isolation structure 442 may be coplanar with the upper surface of the highly-doped n-region 312.
  • the upper surface of the isolation structure 442 may be coplanar with the upper surface of the highly-doped p-region 462.
  • the lowest surface of the isolation structure 442 may be lower than the lowest surface of the highly-doped n-region 312.
  • the lowest surface of the isolation structure 442 may be lower than the lowest surface of the highly-doped p-region 462.
  • the isolation structure 492 may be between the transistor 32 and the transistor 30.
  • the isolation structure 492 may be between the transistor 30 and the p-well 413.
  • the isolation structure 492 may be between the HV n-well 317 and the p-well 413.
  • the isolation structure 492 may be on an interface between the HV n-well 317 and the p-well 413.
  • the isolation structure 492 may be between the drain contact 304 and the contact 472.
  • the isolation structure 492 may be between the highly-doped n-region 314 and the highly-doped p-region 482.
  • the isolation structure 492 may be in contact with the highly-doped n-region 314.
  • the isolation structure 492 may be in contact with the highly-doped p-region 482.
  • the isolation structure 492 may isolate the highly-doped n-region 314 from the highly-doped p-region 482.
  • the isolation structure 492 may isolate the highly-doped n-region 314 from the p-well 413.
  • the isolation structure 492 may isolate the highly-doped p-region 482 from the HV n-well 317.
  • An upper surface of the isolation structure 492 may be coplanar with the upper surface of the substrate 401.
  • the upper surface of the isolation structure 492 may be coplanar with the upper surface of the HV n-well 317.
  • the upper surface of the isolation structure 492 may be coplanar with the upper surface of the p-well 413.
  • the upper surface of the isolation structure 492 may be coplanar with the upper surface of the highly-doped n-region 314.
  • the upper surface of the isolation structure 492 may be coplanar with the upper surface of the highly-doped p-region 482.
  • the lowest surface of the isolation structure 492 may be lower than the lowest surface of the highly-doped n-region 314.
  • the lowest surface of the isolation structure 492 may be lower than the lowest surface of the highly-doped p-region 482.
  • the isolation structure 444 may be between the transistor 30 and the transistor 32.
  • the isolation structure 444 may be between the p-well 413 and the n-well 411.
  • the isolation structure 444 may be on an interface between the p-well 413 and the n-well 411.
  • the isolation structure 444 may be between the contact 452 and the contact 454.
  • the isolation structure 444 may be between the highly-doped p-region 462 and the highly-doped n-region 464.
  • the isolation structure 444 may be in contact with the highly-doped p-region 462.
  • the isolation structure 444 may be in contact with the highly-doped n-region 464.
  • the isolation structure 444 may isolate the highly-doped p-region 462 from the highly-doped n-region 464.
  • the isolation structure 444 may isolate the highly-doped p-region 462 from the n-well 411.
  • the isolation structure 444 may isolate the highly-doped n-region 464 from the p-well 413.
  • An upper surface of the isolation structure 444 may be coplanar with the upper surface of the substrate 401.
  • the upper surface of the isolation structure 444 may be coplanar with the upper surface of the p-well 413.
  • the upper surface of the isolation structure 444 may be coplanar with the upper surface of the n-well 411.
  • the upper surface of the isolation structure 444 may be coplanar with the upper surface of the highly-doped p-region 462.
  • the upper surface of the isolation structure 444 may be coplanar with the upper surface of the highly-doped n-region 464.
  • the lowest surface of the isolation structure 444 may be lower than the lowest surface of the highly-doped p-region 462.
  • the lowest surface of the isolation structure 444 may be lower than the lowest surface of the highly-doped n-region 464.
  • the isolation structure 494 may be between the transistor 32 and the transistor 30.
  • the isolation structure 494 may be between the p-well 413 and the n-well 411.
  • the isolation structure 494 may be on an interface between the p-well 413 and the n-well 411.
  • the isolation structure 494 may be between the contact 472 and the contact 474.
  • the isolation structure 494 may be between the highly-doped p-region 482 and the highly-doped n-region 484.
  • the isolation structure 494 may be in contact with the highly-doped p-region 482.
  • the isolation structure 494 may be in contact with the highly-doped n-region 484.
  • the isolation structure 494 may isolate the highly-doped p-region 482 from the highly-doped n-region 484.
  • the isolation structure 494 may isolate the highly-doped p-region 482 from the n-well 411.
  • the isolation structure 494 may isolate the highly-doped n-region 484 from the p-well 413.
  • An upper surface of the isolation structure 494 may be coplanar with the upper surface of the substrate 401.
  • the upper surface of the isolation structure 494 may be coplanar with the upper surface of the p-well 413.
  • the upper surface of the isolation structure 494 may be coplanar with the upper surface of the n-well 411.
  • the upper surface of the isolation structure 494 may be coplanar with the upper surface of the highly-doped p-region 482.
  • the upper surface of the isolation structure 494 may be coplanar with the upper surface of the highly-doped n-region 484.
  • the lowest surface of the isolation structure 494 may be lower than the lowest surface of the highly-doped p-region 482.
  • the lowest surface of the isolation structure 494 may be lower than the lowest surface of the highly-doped n-region 484.
  • the isolation structure 446 may be between the transistor 30 and the transistor 32.
  • the isolation structure 446 may be between the n-well 411 and the p-well 433.
  • the isolation structure 446 may be on an interface between the n-well 411 and the p-well 433.
  • the isolation structure 446 may be between the contact 454 and the contact 456.
  • the isolation structure 446 may be between the highly-doped n-region 464 and the highly-doped p-region 466.
  • the isolation structure 446 may be in contact with the highly-doped n-region 464.
  • the isolation structure 446 may be in contact with the highly-doped p-region 466.
  • the isolation structure 446 may isolate the highly-doped n-region 464 from the highly-doped p-region 466.
  • the isolation structure 446 may isolate the highly-doped n-region 464 from the p-well 433.
  • the isolation structure 446 may isolate the highly-doped p-region 466 from the n-well 411.
  • An upper surface of the isolation structure 446 may be coplanar with the upper surface of the substrate 401.
  • the upper surface of the isolation structure 446 may be coplanar with the upper surface of the n-well 411.
  • the upper surface of the isolation structure 446 may be coplanar with the upper surface of the p-well 433.
  • the upper surface of the isolation structure 446 may be coplanar with the upper surface of the highly-doped n-region 464.
  • the upper surface of the isolation structure 446 may be coplanar with the upper surface of the highly-doped p-region 466.
  • the lowest surface of the isolation structure 446 may be lower than the lowest surface of the highly-doped n-region 464.
  • the lowest surface of the isolation structure 446 may be lower than the lowest surface of the highly-doped p-region 466.
  • the isolation structure 496 may be between the transistor 32 and the transistor 30.
  • the isolation structure 496 may be between the n-well 411 and the p-well 433.
  • the isolation structure 496 may be on an interface between the n-well 411 and the p-well 433.
  • the isolation structure 496 may be between the contact 474 and the contact 476.
  • the isolation structure 496 may be between the highly-doped n-region 484 and the highly-doped p-region 486.
  • the isolation structure 496 may be in contact with the highly-doped n-region 484.
  • the isolation structure 496 may be in contact with the highly-doped p-region 486.
  • the isolation structure 496 may isolate the highly-doped n-region 484 from the highly-doped p-region 486.
  • the isolation structure 496 may isolate the highly-doped n-region 484 from the p-well 433.
  • the isolation structure 496 may isolate the highly-doped p-region 486 from the n-well 411.
  • An upper surface of the isolation structure 496 may be coplanar with the upper surface of the substrate 401.
  • the upper surface of the isolation structure 496 may be coplanar with the upper surface of the n-well 411.
  • the upper surface of the isolation structure 496 may be coplanar with the upper surface of the p-well 433.
  • the upper surface of the isolation structure 496 may be coplanar with the upper surface of the highly-doped n-region 484.
  • the upper surface of the isolation structure 496 may be coplanar with the upper surface of the highly-doped p-region 486.
  • the lowest surface of the isolation structure 496 may be lower than the lowest surface of the highly-doped n-region 484.
  • the lowest surface of the isolation structure 496 may be lower than the lowest surface of the highly-doped p-region 486.
  • the isolation structure 448 may be between the transistor 30 and the transistor 32.
  • the isolation structure 448 may be between the transistor 32 and the p-well 433.
  • the isolation structure 448 may be between the HV n-well 337 and the p-well 433.
  • the isolation structure 448 may be on an interface between the HV n-well 337 and the p-well 433.
  • the isolation structure 448 may be between the drain contact 324 and the contact 456.
  • the isolation structure 448 may be between the highly-doped n-region 334 and the highly-doped p-region 466.
  • the isolation structure 448 may be in contact with the highly-doped n-region 334.
  • the isolation structure 448 may be in contact with the highly-doped p-region 466.
  • the isolation structure 448 may isolate the highly-doped n-region 334 from the highly-doped p-region 466.
  • the isolation structure 448 may isolate the highly-doped n-region 334 from the p-well 433.
  • the isolation structure 448 may isolate the highly-doped p-region 466 from the HV n-well 337.
  • An upper surface of the isolation structure 448 may be coplanar with the upper surface of the substrate 401.
  • the upper surface of the isolation structure 448 may be coplanar with the upper surface of the HV n-well 337.
  • the upper surface of the isolation structure 448 may be coplanar with the upper surface of the p-well 433.
  • the upper surface of the isolation structure 448 may be coplanar with the upper surface of the highly-doped n-region 334.
  • the upper surface of the isolation structure 448 may be coplanar with the upper surface of the highly-doped p-region 466.
  • the lowest surface of the isolation structure 448 may be lower than the lowest surface of the highly-doped n-region 334.
  • the lowest surface of the isolation structure 448 may be lower than the lowest surface of the highly-doped p-region 466.
  • the isolation structure 498 may be between the transistor 32 and the transistor 30.
  • the isolation structure 498 may be between the transistor 32 and the p-well 433.
  • the isolation structure 498 may be between the HV p-body 335 and the p-well 433.
  • the isolation structure 498 may be on an interface between the HV p-body 335 and the p-well 433.
  • the isolation structure 498 may be between the source contact 322 and the contact 476.
  • the isolation structure 498 may be between the highly-doped n-region 332 and the highly-doped p-region 486.
  • the isolation structure 498 may be in contact with the highly-doped n-region 332.
  • the isolation structure 498 may be in contact with the highly-doped p-region 486.
  • the isolation structure 498 may isolate the highly-doped n-region 332 from the highly-doped p-region 486.
  • the isolation structure 498 may isolate the highly-doped n-region 332 from the p-well 433.
  • the isolation structure 498 may isolate the highly-doped p-region 486 from the HV p-body 335.
  • An upper surface of the isolation structure 498 may be coplanar with the upper surface of the substrate 401.
  • the upper surface of the isolation structure 498 may be coplanar with the upper surface of the HV p-body 335.
  • the upper surface of the isolation structure 498 may be coplanar with the upper surface of the p-well 433.
  • the upper surface of the isolation structure 498 may be coplanar with the upper surface of the highly-doped n-region 332.
  • the upper surface of the isolation structure 498 may be coplanar with the upper surface of the highly-doped p-region 486.
  • the lowest surface of the isolation structure 498 may be lower than the lowest surface of the highly-doped n-region 332.
  • the lowest surface of the isolation structure 498 may be lower than the lowest surface of the highly-doped p-region 486.
  • the transistor 30 may be electrically connected to the transistor 32 in series.
  • the source contact 302 of the transistor 30 may be electrically connected to the drain contact 324 of the transistor 32.
  • the source contact 302 and the drain contact 324 may be electrically connected to the same potential at a switch node (SW) .
  • the source contact 302 may be electrically connected to the drain contact 324 through a conductive wire (not shown) .
  • the drain contact 304 of the transistor 30 may be electrically connected to a voltage supply (V in ) .
  • the source contact 322 of the transistor 32 may be electrically connected to ground (GND) .
  • the transistor 30 may be represented by the transistor 10 shown in FIG. 1.
  • the transistor 30 may be referred to as a high-side (HS) transistor.
  • the transistor 32 may be represented by the transistor 12 shown in FIG. 1.
  • the transistor 32 may be referred to as a low-side (LS) transistor.
  • a plurality of the cells 400 may be electrically connected to each other in parallel to overall build a half-bridge circuit.
  • the contacts 452 may be electrically connected to the same potential as the source contacts 302 and the drain contacts 324 at the switch node (SW) .
  • the contacts 472 may be electrically connected to the same potential as the source contacts 302 and the drain contacts 324 at the switch node (SW) .
  • the contacts 454 may be electrically connected to a voltage supply (V in ) .
  • the contacts 474 may be electrically connected to a voltage supply (V in ) .
  • the contacts 456 may be electrically connected to ground (GND) .
  • the contacts 476 may be electrically connected to ground (GND) .
  • the semiconductor device 4 shown in FIG. 5 is compared to the semiconductor device 2 shown in FIG. 3.
  • the conductive wire (s) for connecting the source contacts 302 of the transistors 30 and the drain contacts 324 the transistors 32 has a shorter length compared to the conductive wire (s) for connecting the source contacts 202 of the transistors 20A, 20B, 20C, 20D and the drain contacts 224 of the transistors 22A, 22B, 22C, 22D.
  • parasitic resistance and parasitic inductance can be reduced.
  • the issues of voltage spike or surge can be alleviated.
  • the performance of the semiconductor device can thus be improved.
  • the current uniformity is improved, especially under high frequency switching status.
  • the crosstalk between the transistors 30 and the transistors 32 in the semiconductor device 4 can be decreased due to the presence of the isolation ring. The performance of the semiconductor device can thus be further improved.
  • FIG. 6 illustrates a cross-sectional view of a semiconductor device 5 in accordance with some embodiments of the present disclosure.
  • the semiconductor device 5 is similar to the semiconductor device 3 except for at least the following differences.
  • the semiconductor device 5 includes a substrate 501, isolation structures 505, 507, transistors 30 and transistors 32.
  • the material of the substrate 501 may be similar to the substrate 301.
  • the substrate 501 includes an insulating layer 503.
  • the insulating layer 503 may be buried in the substrate 501.
  • the insulating layer 503 may be a buried insulating layer.
  • the insulating layer 503 may be a buried oxide layer.
  • the insulating layer 503 may include, but is not limited to, silicon oxide (SiO x ) .
  • the insulating layer 503 may extend from a lateral surface of the substrate 501 to another lateral surface of the substrate 501.
  • the isolation structure 505 is within the substrate 501.
  • the isolation structure 505 may be a deep trench isolation (DTI) structure.
  • the isolation structure 505 may include, for example, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or other suitable insulating material, or a combination thereof.
  • An upper surface of the isolation structure 505 may be coplanar with an upper surface of the substrate 501.
  • the isolation structure 505 may be on the insulating layer 503.
  • the isolation structure 505 may be in contact with the insulating layer 503.
  • the isolation structure 505 may be connected to the insulating layer 503.
  • the isolation structure 505 may extend from an upper surface of the substrate 501 to the insulating layer 503.
  • the isolation structure 505 is between the transistor 30 and the transistor 32.
  • the isolation structure 507 is within the substrate 501.
  • the isolation structure 507 may be a deep trench isolation (DTI) structure.
  • the isolation structure 507 may include, for example, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or other suitable insulating material, or a combination thereof.
  • An upper surface of the isolation structure 507 may be coplanar with an upper surface of the substrate 501.
  • the isolation structure 507 may be on the insulating layer 503.
  • the isolation structure 507 may be in contact with the insulating layer 503.
  • the isolation structure 507 may be connected to the insulating layer 503.
  • the isolation structure 507 may extend from an upper surface of the substrate 501 to the insulating layer 503.
  • the isolation structure 507 is between the transistor 32 and the transistor 30.
  • the isolation structure 507 from a cross-sectional view as shown in FIG. 6, the isolation structure 507 the insulating layer 503 and the isolation structure 505 together surround the transistor 30. In some embodiments, from a cross-sectional view as shown in FIG. 6, the isolation structure 505, the insulating layer 503 and the isolation structure 507 together surround the transistor 32.
  • the transistors 30 and the transistors 32 are disposed alternately along the direction D as shown in FIG. 6.
  • One transistor 30 and one neighboring transistor 32 constitute a cell 500.
  • a plurality of the cells 500 are arranged repeatedly along the direction D.
  • the transistor 30 includes a source contact 302, a drain contact 304 and a gate contact 306.
  • the source contact 302 is on the substrate 501.
  • the drain contact 304 is on the substrate 501.
  • the gate contact 306 is on the on the substrate 501.
  • the gate contact 306 is between the source contact 302 and the drain contact 304.
  • the transistor 30 includes a high-voltage (HV) n-well 317 in the substrate 501.
  • An upper surface of the HV n-well 317 may be coplanar with the upper surface of the substrate 501.
  • the HV n-well 317 may be in contact with the insulating layer 503.
  • the HV n-well 317 may be in contact with the isolation structure 505.
  • the transistor 30 includes a high-voltage (HV) p-body 315 in the substrate 501.
  • An upper surface of the HV p-body 315 may be coplanar with the upper surface of the substrate 501.
  • the HV p-body 315 may be in contact with the insulating layer 503.
  • the HV p-body 315 may be in contact with the isolation structure 507.
  • the transistor 32 includes a source contact 322, a drain contact 324 and a gate contact 326.
  • the source contact 322 is on the substrate 501.
  • the drain contact 324 is on the substrate 501.
  • the gate contact 326 is on the substrate 501.
  • the gate contact 326 is between the source contact 322 and the drain contact 324.
  • the isolation structure 505 may be between the drain contact 304 and the drain contact 324.
  • the isolation structure 507 may be between the source contact 322 and the source contact 302.
  • the transistor 32 includes a high-voltage (HV) n-well 337 in the substrate 501.
  • An upper surface of the HV n-well 337 may be coplanar with the upper surface of the substrate 501.
  • the HV n-well 337 may be in contact with the insulating layer 503.
  • the HV n-well 337 may be in contact with the isolation structure 505.
  • the isolation structure 505 may be between the HV n-well 317 and the HV n-well 337.
  • the transistor 32 includes a high-voltage (HV) p-body 335 in the substrate 501.
  • An upper surface of the HV p-body 335 may be coplanar with the upper surface of the substrate 501.
  • the HV p-body 335 may be in contact with the insulating layer 503.
  • the HV p-body 335 may be in contact with the isolation structure 507.
  • the isolation structure 507 may be between the HV p-body 335 and the HV p-body 315.
  • the transistor 30 includes a highly-doped n-region 312 in the HV p-body 315. In some embodiments, the transistor 30 includes a highly-doped n-region 314 in the HV n-well 317. In some embodiments, the transistor 32 includes a highly-doped n-region 332 in the HV p-body 335. In some embodiments, the transistor 32 includes a highly-doped n-region 334 in the HV n- well 337. The highly-doped n-region 312 may be in contact with the isolation structure 507. An upper surface of the highly-doped n-region 312 may be coplanar with an upper surface of the substrate 501.
  • An upper surface of the highly-doped n-region 312 may be coplanar with an upper surface of the isolation structure 507.
  • the highly-doped n-region 314 may be in contact with the isolation structure 505.
  • An upper surface of the highly-doped n-region 314 may be coplanar with an upper surface of the substrate 501.
  • An upper surface of the highly-doped n-region 314 may be coplanar with an upper surface of the isolation structure 505.
  • the highly-doped n-region 332 may be in contact with the isolation structure 507.
  • An upper surface of the highly-doped n-region 332 may be coplanar with an upper surface of the substrate 501.
  • An upper surface of the highly-doped n-region 332 may be coplanar with an upper surface of the isolation structure 507.
  • the highly-doped n-region 334 may be in contact with the isolation structure 505.
  • An upper surface of the highly-doped n-region 334 may be coplanar with an upper surface of the substrate 501.
  • An upper surface of the highly-doped n-region 334 may be coplanar with an upper surface of the isolation structure 505.
  • the isolation structure 505 may be between the highly-doped n-region 314 and the highly-doped n-region 334.
  • the isolation structure 507 may be between the highly-doped n-region 332 and the highly-doped n-region 312.
  • the transistor 30 may be electrically connected to the transistor 32 in series.
  • the source contact 302 of the transistor 30 may be electrically connected to the drain contact 324 of the transistor 32.
  • the source contact 302 and the drain contact 324 may be electrically connected to the same potential at a switch node (SW) .
  • the source contact 302 may be electrically connected to the drain contact 324 through a conductive wire (not shown) .
  • the drain contact 304 of the transistor 30 may be electrically connected to a voltage supply (V in ) .
  • the source contact 322 of the transistor 32 may be electrically connected to ground (GND) .
  • the transistor 30 may be represented by the transistor 10 shown in FIG. 1.
  • the transistor 30 may be referred to as a high-side (HS) transistor.
  • the transistor 32 may be represented by the transistor 12 shown in FIG. 1.
  • the transistor 32 may be referred to as a low-side (LS) transistor.
  • a plurality of the cells 500 may be electrically connected to each other in parallel to overall build a half-bridge circuit.
  • the semiconductor device 5 shown in FIG. 6 is compared to the semiconductor device 2 shown in FIG. 3.
  • the conductive wire (s) for connecting the source contacts 302 of the transistors 30 and the drain contacts 324 the transistors 32 has a shorter length compared to the conductive wire (s) for connecting the source contacts 202 of the transistors 20A, 20B, 20C, 20D and the drain contacts 224 of the transistors 22A, 22B, 22C, 22D.
  • the crosstalk between the transistors 30 and the transistors 32 in the semiconductor device 5 can be decreased due to the presence of the insulating layer 503 and the isolation structures 505, 507.
  • the performance of the semiconductor device can thus be further improved.
  • the isolation structures 505, 507 allow to decrease the dimension of the semiconductor device and facilitate miniaturization of the semiconductor device or chip.
  • FIG. 7A, FIG. 7B, FIG. 7C, FIG. 7D, FIG. 7E, FIG. 7F and FIG. 7G illustrate some operations to manufacture the semiconductor device 3 in accordance with some embodiments of the present disclosure.
  • a substrate 301 is provided.
  • the substrate 301 may include an intrinsic semiconductor material.
  • the substrate 301 may be a p-type substrate.
  • the substrate 301 may have a dopant concentration of around 10 16 -10 17 cm -3 .
  • a p-well 313 is formed in substrate 301.
  • the p-well 313 may be formed by diffusion, ion implantation and/or another suitable doping operation.
  • the p-well 313 may have a dopant concentration of around 10 17 -10 18 cm -3 .
  • HV p-bodies 315 and 335 are formed in the p-well 313.
  • the HV p-bodies 315 and 335 may be formed by diffusion, ion implantation and/or another suitable doping operation.
  • the HV p-bodies 315 and 335 each may have a dopant concentration of around 10 17 -10 19 cm -3 .
  • the HV p-bodies 315 and 335 each and independently may have a higher dopant concentration than the dopant concentration of the p-well 313.
  • a highly-doped p-region 362 is formed in the p-well 313.
  • the highly-doped p-region 362 may be formed by diffusion, ion implantation and/or another suitable doping operation.
  • the highly-doped p-region 362 may have a dopant concentration of around >10 18 cm -3 .
  • HV n-wells 317 and 337 are formed in the p-well 313.
  • the HV n-wells 317 and 337 each and independently may have a dopant concentration of around 10 16 -10 18 cm -3 .
  • the HV n-wells 317 and 337 may be formed by diffusion, ion implantation and/or another suitable doping operation.
  • highly-doped n-regions 312, 314, 332 and 334 are formed.
  • the highly-doped n-region 312 is formed in the HV p-body 315.
  • the highly-doped n-region 314 is formed in the HV n-well 317.
  • the highly-doped n-region 332 is formed in the HV p-body 335.
  • the highly-doped n-region 334 is formed in the HV n-well 337.
  • the highly-doped n-regions 312, 314, 332 and 334 may be formed by diffusion, ion implantation and/or another suitable doping operation.
  • the highly-doped n-regions 312, 314, 332 and 334 each and independently may have a dopant concentration of around >10 18 cm - 3 . In some embodiments, the highly-doped n-regions 312, 314, 332 and 334 may be formed simultaneously. In some embodiments, the highly-doped n-regions 312, 314, 332 and 334 may be formed in different steps.
  • isolation structures 372, 374 and 376 are formed.
  • the isolation structures 372, 374 and 376 may be formed by forming trenches and depositing an insulating material in the trenches.
  • the trenches may be formed by etching and/or another suitable removing operation.
  • a planarization operation is carried out to remove excess insulating material.
  • the planarization operation may be CMP.
  • the isolation structures 372, 374 and 376 may be formed simultaneously.
  • the isolation structures 372, 374 and 374 and 334 may be formed in different steps.
  • contacts 302, 304, 306, 322, 324 and 326 are formed on the substrate 301.
  • the contacts 302, 304, 306, 322, 324 and 326 may be formed by ALD, CVD, PVD and/or another suitable deposition operation. In some embodiments, the contacts 302, 304, 306, 322, 324 and 326 may be formed simultaneously. In some embodiments, the contacts 302, 304, 306, 322, 324 and 326 may be formed in different steps.
  • FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, FIG. 8E, FIG. 8F, FIG. 8G and FIG. 8H illustrate some operations to manufacture the semiconductor device 4 in accordance with some embodiments of the present disclosure.
  • a substrate 401 is provided.
  • the substrate 401 includes an insulating layer 410.
  • the substrate 401 may include a base substrate 401A and an epitaxial layer 401B on the base substrate 401A.
  • the base substrate 401A may include an intrinsic semiconductor material.
  • the base substrate 401A may be a p-type substrate.
  • the base substrate 401A may have a dopant concentration of around 10 16 -10 17 cm -3 .
  • the epitaxial layer 401B may include a p-type semiconductor material.
  • the epitaxial layer 401B may have a dopant concentration of around 10 16 -10 17 cm -3 .
  • the insulating layer 410 may be formed in the base substrate 401A. An upper surface of the insulating layer 410 may be coplanar with an upper surface of the base substrate 401A. The insulating layer 410 may be formed by diffusion, ion implantation, and/or another suitable doping operation.
  • the epitaxial layer 401B is formed on the base substrate 401A.
  • the epitaxial layer 401B may be formed by CVD, PVD, ALD, and/or another suitable deposition operation.
  • an n-well 411 and p-wells 413 and 433 are formed in the substrate 401.
  • the n-well 411 and the p-wells 413 and 433 may be formed in the epitaxial layer 401B.
  • the n-well 411 and the p-wells 413 and 433 may be formed by diffusion, ion implantation, and/or another suitable doping operation.
  • the n-well 411 may have a dopant concentration of approximately 10 17 -10 18 cm -3 .
  • the p-wells 413 and 433 each and independently may have a dopant concentration of approximately 10 17 -10 18 cm -3 .
  • the n-well 411 may be formed before the p-wells 413 and 433 are formed. In some embodiments, the n-well 411 may be formed after the p-wells 413 and 433 are formed. In some embodiments, from a top view (not shown) , the n-well 411 may surround the p-well 413.
  • HV p-bodies 315 and 335 are formed.
  • the HV p-body 315 is formed in the p-well 413.
  • the HV p-body 335 is formed in the p-well 433.
  • the HV p-bodies 315 and 335 may be formed by diffusion, ion implantation, and/or another suitable doping operation.
  • the HV p-bodies 315 and 335 each and independently may have a dopant concentration of around 10 17 -10 19 cm -3 .
  • the HV p-body 315 may have a higher dopant concentration than the dopant concentration of the p-well 413.
  • the HV p-body 335 may have a higher dopant concentration than the dopant concentration of the p-well 433.
  • highly-doped p-regions 462, 466, 482 and 486 are formed.
  • the highly-doped p-regions 462 and 482 are formed in the p-well 413.
  • the highly-doped p-regions 466 and 486 are formed in the p-well 433.
  • the highly-doped p-regions 462, 466, 482 and 486 may be formed by diffusion, ion implantation and/or another suitable doping operation.
  • the highly-doped p-regions 462, 466, 482 and 486 each and independently may have a dopant concentration of around >10 18 cm -3 .
  • the highly-doped p-regions 462, 466, 482 and 486 may be formed simultaneously. In some embodiments, the highly-doped p-regions 462, 466, 482 and 486 may be formed in different steps.
  • HV n-wells 317 and 337 are formed.
  • the HV n-well 317 is formed in the p-well 413.
  • the HV n-well 337 is formed in the p-well 433.
  • the HV n-wells 317 and 337 may be formed by diffusion, ion implantation and/or another suitable doping operation.
  • the HV n-wells 317 and 337 each and independently may have a dopant concentration of around 10 16 -10 18 cm -3 .
  • highly-doped n-regions 312, 314, 332, 334, 464 and 484 are formed.
  • the highly-doped n-region 312 is formed in the HV p-body 315.
  • the highly-doped n-region 314 is formed in the HV n-well 317.
  • the highly-doped n-region 332 is formed in the HV p-body 335.
  • the highly-doped n-region 334 is formed in the HV n-well 337.
  • the highly-doped n-region 464 is formed in the n-well 411.
  • the highly-doped n-region 484 is formed in the n-well 411.
  • the highly-doped n-regions 312, 314, 332, 334, 464 and 484 may be formed by diffusion, ion implantation and/or another suitable doping operation. In some embodiments, the highly-doped n-regions 312, 314, 332, 334, 464 and 484 each and independently may have a dopant concentration of around >10 18 cm -3 . In some embodiments, the highly-doped n-regions 312, 314, 332, 334, 464 and 484 may be formed simultaneously. In some embodiments, the highly-doped n-regions 312, 314, 332, 334, 464 and 484 may be formed in different steps.
  • isolation structures 442, 444, 446, 448, 492, 494, 496 and 498 are formed.
  • the isolation structures 442, 444, 446, 448, 492, 494, 496 and 498 may be formed by forming trenches and depositing an insulating material in the trenches.
  • the trenches may be formed by etching and/or another suitable removing operation.
  • a planarization operation is carried out to remove excess insulating material.
  • the planarization operation may be CMP.
  • the isolation structures 442, 444, 446, 448, 492, 494, 496 and 498 may be formed simultaneously.
  • the isolation structures 442, 444, 446, 448, 492, 494, 496 and 498 may be formed in different steps.
  • contacts 302, 304, 306, 322, 324, 326, 452, 454, 456, 472, 474 and 476 are formed on the substrate 401.
  • the contacts 302, 304, 306, 322, 324, 326, 452, 454, 456, 472, 474 and 476 may be formed by ALD, CVD, PVD and/or another suitable deposition operation.
  • the contacts 302, 304, 306, 322, 324, 326, 452, 454, 456, 472, 474 and 476 may be formed simultaneously.
  • the contacts 302, 304, 306, 322, 324, 326, 452, 454, 456, 472, 474 and 476 may be formed in different steps.
  • FIG. 9A, FIG. 9B, FIG. 9C, FIG. 9D, FIG. 9E and FIG. 9F illustrate some operations to manufacture the semiconductor device 5 in accordance with some embodiments of the present disclosure.
  • a substrate 501 is provided.
  • the substrate 501 includes an insulating layer 503.
  • the insulating layer 503 may be buried in the substrate 501.
  • the insulating layer 503 may be a buried insulating layer.
  • the insulating layer 503 may be a buried oxide layer.
  • the substrate 501 may include an intrinsic semiconductor material.
  • the substrate 501 may include a p-type semiconductor material.
  • the substrate 501 may have a dopant concentration of around 10 16 -10 17 cm -3 .
  • the substrate 501 may be intrinsic.
  • HV p-bodies 315 and 335 are formed in the substrate 501.
  • the HV p-bodies 315 and 335 may be formed by diffusion, ion implantation and/or another suitable doping operation.
  • the HV p-bodies 315 and 335 each and independently may have a dopant concentration of around 10 17 -10 19 cm -3 .
  • the HV p-bodies 315 and 335 are formed on the insulating layer 503.
  • an HV n-well 917 is formed in the substrate 501.
  • the HV n-well 917 may be formed by diffusion, ion implantation and/or another suitable doping operation.
  • the HV n-well 917 is formed on the insulating layer 503.
  • the HV n-well 917 may have a dopant concentration of around 10 16 -10 18 cm - 3 .
  • highly-doped n-regions 312, 332 and 914 are formed.
  • the highly-doped n-region 312 is formed in the HV p-body 315.
  • the highly-doped n-region 332 is formed in the HV p-body 335.
  • the highly-doped n-region 914 is formed in the HV n-well 917.
  • the highly-doped n-regions 312, 332 and 914 may be formed by diffusion, ion implantation and/or another suitable doping operation.
  • the highly-doped n-regions 312, 332 and 914 each and independently may have a dopant concentration of around >10 18 cm -3 .
  • the highly-doped n-regions 312, 332 and 914 may be formed simultaneously.
  • the highly-doped n-regions 312, 332 and 914 may be formed in different steps.
  • isolation structures 505 and 507 are formed.
  • the isolation structures 505 and 507 may be formed by forming trenches and depositing an insulating material in the trenches.
  • the trenches may be formed by etching and/or another suitable removing operation.
  • a planarization operation is carried out to remove excess insulating material.
  • the planarization operation may be CMP.
  • the isolation structure 505 divides the HV n-well 917 into an HV n-well 317 and an HV n-well 337.
  • the isolation structure 505 divides the highly-doped n-region 914 into a highly-doped n-region 314 and a highly-doped n-region 334.
  • the isolation structures 505 and 507 may be formed simultaneously. In some embodiments, the isolation structures 505 and 507 may be formed in different steps.
  • contacts 302, 304, 306, 322, 324 and 326 are formed on the substrate 501.
  • the contacts 302, 304, 306, 322, 324 and 326 may be formed by ALD, CVD, PVD and/or another suitable deposition operation. In some embodiments, the contacts 302, 304, 306, 322, 324 and 326 may be formed simultaneously. In some embodiments, the contacts 302, 304, 306, 322, 324 and 326 may be formed in different steps.
  • Embodiment 1-1 A semiconductor device (3) , comprising:
  • a substrate (301) comprising a p-well (313) ;
  • a first transistor (30) comprising:
  • HV high-voltage
  • a second transistor (32) comprising:
  • a portion of the p-well is between the first HV n-well and the second HV n-well.
  • Embodiment 1-2 The semiconductor device of the preceding embodiment, further comprising a contact (352) on the portion of the p-well between the first HV n-well and the second HV n-well.
  • Embodiment 1-3 The semiconductor device of any of the preceding embodiments, further comprising a highly-doped p-region (362) in the portion of the p-well between the first HV n-well and the second HV n-well.
  • Embodiment 1-4 The semiconductor device of any of the preceding embodiments, wherein the first transistor further comprises a first HV p-body (315) in the p-well, and wherein the first HV p-body is in contact with the first HV n-well.
  • Embodiment 1-5 The semiconductor device of any of the preceding embodiments, wherein the first source contact (302) is on the first HV p-body (315) .
  • Embodiment 1-6 The semiconductor device of any of the preceding embodiments, wherein the first drain contact (304) is on the first HV n-well (317) .
  • Embodiment 1-7 The semiconductor device of any of the preceding embodiments, wherein the first transistor further comprises a highly-doped n-region (312) in the first HV p-body.
  • Embodiment 1-8 The semiconductor device of any of the preceding embodiments, wherein the first transistor further comprises a highly-doped n-region (314) in the first HV n-well.
  • Embodiment 1-9 The semiconductor device of any of the preceding embodiments, further comprising an isolation structure (372) between the first HV n-well (317) and the p-well (313) .
  • Embodiment 1-10 The semiconductor device of any of the preceding embodiments, wherein the second transistor further comprises a second HV p-body (335) in the p-well, and wherein the second HV p-body is in contact with the second HV n-well.
  • the second transistor further comprises a second HV p-body (335) in the p-well, and wherein the second HV p-body is in contact with the second HV n-well.
  • Embodiment 1-11 The semiconductor device of any of the preceding embodiments, wherein the second source contact (322) is on the second HV p-body.
  • Embodiment 1-12 The semiconductor device of any of the preceding embodiments, wherein the second drain contact (324) is on the second HV n-well.
  • Embodiment 1-13 The semiconductor device of any of the preceding embodiments, wherein the second transistor further comprises a highly-doped n-region (332) in the second HV p-body.
  • Embodiment 1-14 The semiconductor device of any of the preceding embodiments, wherein the second transistor further comprises a highly-doped n-region (334) in the second HV n-well.
  • Embodiment 1-15 The semiconductor device of any of the preceding embodiments, further comprising an isolation structure (374) between the second HV n-well and the p-well.
  • Embodiment 1-16 A method of manufacturing semiconductor device (3) , comprising:
  • a first transistor (30) comprising:
  • HV high-voltage
  • a second transistor (32) comprising:
  • a portion of the p-well is between the first HV n-well and the second HV n-well.
  • Embodiment 1-17 The method of the preceding embodiment, further comprising forming a contact (352) on the portion of the p-well between the first HV n-well and the second HV n-well.
  • Embodiment 1-18 The method of any of the preceding embodiments, further comprising forming a highly-doped p-region (362) in the portion of the p-well between the first HV n-well and the second HV n-well, wherein forming the contact (352) on the portion of the p-well comprising forming the contact on the highly-doped p-region.
  • Embodiment 1-19 The method of any of the preceding embodiments, wherein the first transistor further comprises a first HV p-body (315) in the p-well, and wherein the first HV p-body is in contact with the first HV n-well
  • Embodiment 1-20 The method of any of the preceding embodiments, wherein the second transistor further comprises a second HV p-body (335) in the p-well, and wherein the second HV p-body is in contact with the second HV n-well.
  • Embodiment 1-21 A semiconductor device (3) , comprising:
  • a substrate (301) comprising a p-well (313) ;
  • HV p-body (315, 335) between the first HV n-well and the second HV n-well;
  • Embodiment 1-22 The semiconductor device of the preceding embodiment, further comprising an isolation structure (376) in the HV p-body and between the first source contact (302) and the second source contact (322) .
  • Embodiment 1-23 The semiconductor device of any of the preceding embodiments, further comprising a highly-doped n-region (312, 332) in the HV p-body and under the first source contact (302) or the second source contact (322) .
  • Embodiment 1-24 The semiconductor device of any of the preceding embodiments, further comprising a highly-doped n-region (314) in the first HV n-well and under the first drain contact (304) .
  • Embodiment 1-25 The semiconductor device of any of the preceding embodiments, further comprising a highly-doped n-region (334) in the second HV n-well and under the second drain contact (324) .
  • Embodiment 2-1 A semiconductor device (4) , comprising:
  • a substrate comprising a first p-well (413) and a second p-well (433) ;
  • n-well (411) in the substrate, wherein the n-well and the n-type buried layer together surround the first p-well;
  • a first transistor (30) comprising:
  • a second transistor (32) comprising:
  • first contact 452
  • second contact 472
  • Embodiment 2-2 The semiconductor device of the preceding embodiment, further comprising a third contact (454) on the n-well (411) and next to the first contact (452) , wherein the third contact is electrically connected to the n-well.
  • Embodiment 2-3 The semiconductor device of any of the preceding embodiments, further comprising a fourth contact (474) on the n-well (411) and next to the second contact (472) , wherein the fourth contact is electrically connected to the n-well.
  • Embodiment 2-4 The semiconductor device of any of the preceding embodiments, further comprising a fifth contact (456) on the second p-well (433) and next to the second drain contact (324) , wherein the fifth contact is electrically connected to the second p-well.
  • Embodiment 2-5 The semiconductor device of any of the preceding embodiments, further comprising a sixth contact (476) on the second p-well (456) and next to the second source contact (322) , wherein the sixth contact is electrically connected to the second p-well.
  • Embodiment 2-6 The semiconductor device of any of the preceding embodiments, wherein the first transistor further comprises a first high-voltage (HV) n-well (317) in the first p-well.
  • HV high-voltage
  • Embodiment 2-7 The semiconductor device of any of the preceding embodiments, wherein the first transistor further comprises a first HV p-body (315) in the first p-well, and wherein the first HV p-body is in contact with the first HV n-well.
  • Embodiment 2-8 The semiconductor device of any of the preceding embodiments, further comprising an isolation structure (492) between the first HV n-well and the first p-well.
  • Embodiment 2-9 The semiconductor device of any of the preceding embodiments, further comprising an isolation structure (442) between the first HV p-body and the first p-well.
  • Embodiment 2-10 The semiconductor device of any of the preceding embodiments, wherein the first transistor further comprises a highly-doped n-region (314) in the first HV n-well.
  • Embodiment 2-11 The semiconductor device of any of the preceding embodiments, wherein the first transistor further comprises a highly-doped n-region (312) in the first HV p-body.
  • Embodiment 2-12 The semiconductor device of any of the preceding embodiments, wherein the second transistor further comprises a second high-voltage (HV) n-well (337) in the second p-well.
  • HV high-voltage
  • Embodiment 2-13 The semiconductor device of any of the preceding embodiments, wherein the second transistor further comprises a second HV p-body (335) in the second p-well, and wherein the second HV p-body is in contact with the second HV n-well.
  • the second transistor further comprises a second HV p-body (335) in the second p-well, and wherein the second HV p-body is in contact with the second HV n-well.
  • Embodiment 2-14 The semiconductor device of any of the preceding embodiments, further comprising an isolation structure (478) between the second HV n-well and the second p-well.
  • Embodiment 2-15 The semiconductor device of any of the preceding embodiments, further comprising an isolation structure (498) between the second HV p-body and the second p-well.
  • Embodiment 2-16 A method of manufacturing a semiconductor device (4) , comprising:
  • n-well (411) in the substrate, wherein the n-well and the n-type buried layer together surround the first p-well;
  • a first transistor (30) comprising:
  • a second transistor (32) comprising:
  • first contact (452) and a second contact (472) on the first p-well, wherein the first contact and the second contact (472) are electrically connected to the first p-well.
  • Embodiment 2-17 The method of the preceding embodiment, further comprising forming a third contact (454) on the n-well (411) and next to the first contact (452) , wherein the third contact is electrically connected to the n-well.
  • Embodiment 2-18 The method of any of the preceding embodiments, further comprising forming a fourth contact (474) on the n-well (411) and next to the second contact (472) , wherein the fourth contact is electrically connected to the n-well.
  • Embodiment 2-19 The method of any of the preceding embodiments, further comprising forming a fifth contact (456) on the second p-well (433) and next to the second drain contact (324) , wherein the fifth contact is electrically connected to the second p-well.
  • Embodiment 2-20 The method of any of the preceding embodiments, further comprising forming a sixth contact (476) on the second p-well (456) and next to the second source contact (322) , wherein the sixth contact is electrically connected to the second p-well.
  • Embodiment 2-21 A semiconductor device (4) , comprising:
  • a substrate comprising a first p-well (413) and a second p-well (433) ;
  • n-well (411) in the substrate, wherein the n-well and the n-type buried layer together surround the first p-well;
  • a first transistor (30) comprising:
  • HV high-voltage
  • first HV p-body (315) in the first p-well, wherein the first HV p-body is in contact with the first HV n-well;
  • a second transistor (32) comprising:
  • HV high-voltage
  • first isolation structure (442) between the first HV p-body and the first p-well;
  • a second isolation structure (492) between the first HV n-well and the first p-well.
  • Embodiment 2-22 The semiconductor device of the preceding embodiment, further comprising a contact (452) on the first p-well and next to the first source contact (302) , wherein the contact is electrically connected to the first p-well.
  • Embodiment 2-23 The semiconductor device of any of the preceding embodiments, further comprising a contact (472) on the first p-well and next to the first drain contact (304) , wherein the contact is electrically connected to the first p-well.
  • Embodiment 2-24 The semiconductor device of any of the preceding embodiments, further comprising a contact (454, 474) on the n-well (411) , wherein the contact is electrically connected to the n-well.
  • Embodiment 2-25 The semiconductor device of any of the preceding embodiments, further comprising a contact (456, 476) on the second p-well (433) and next to the second source contact or the second drain contact, wherein the contact is electrically connected to the second p-well.
  • Embodiment 3-1 A semiconductor device (5) , comprising:
  • a substrate (501) comprising an insulating layer (503) buried in the substrate;
  • a first transistor (30) comprising:
  • HV high-voltage
  • first HV p-body (315) in the substrate and on the insulating layer, wherein the first HV p-body is in contact with the first HV n-well;
  • a second transistor (32) comprising:
  • HV high-voltage
  • an isolation structure (505, 507) between the first transistor and the second transistor, wherein the isolation structure extends from an upper surface of the substrate to the insulating layer.
  • Embodiment 3-2 The semiconductor device of the preceding embodiment, wherein the first HV n-well (317) is in contact with the isolation structure (505) .
  • Embodiment 3-3 The semiconductor device of any of the preceding embodiments, wherein the first HV n-well (317) is in contact with the insulating layer (503) .
  • Embodiment 3-4 The semiconductor device of any of the preceding embodiments, wherein the first HV p-body (315) is in contact with the isolation structure (507) .
  • Embodiment 3-5 The semiconductor device of any of the preceding embodiments, wherein the first HV p-body (315) is in contact with the insulating layer (503) .
  • Embodiment 3-6 The semiconductor device of any of the preceding embodiments, wherein the second HV n-well (337) is in contact with the isolation structure (505) .
  • Embodiment 3-7 The semiconductor device of any of the preceding embodiments, wherein the second HV n-well (337) is in contact with the insulating layer (503) .
  • Embodiment 3-8 The semiconductor device of any of the preceding embodiments, wherein the second HV p-body (335) is in contact with the isolation structure (507) .
  • Embodiment 3-9 The semiconductor device of any of the preceding embodiments, wherein the second HV p-body (335) is in contact with the insulating layer (503) .
  • Embodiment 3-10 The semiconductor device of any of the preceding embodiments, wherein the first transistor further comprises a highly-doped n-region (312) in the first HV p-body.
  • Embodiment 3-11 The semiconductor device of any of the preceding embodiments, wherein the highly-doped n-region (312) in the first HV p-body is in contact with the isolation structure (507) .
  • Embodiment 3-12 The semiconductor device of any of the preceding embodiments, wherein the first transistor further comprises a highly-doped n-region (314) in the first HV n-well.
  • Embodiment 3-13 The semiconductor device of any of the preceding embodiments, wherein the highly-doped n-region (314) in the first HV n-well is in contact with the isolation structure (505) .
  • Embodiment 3-14 The semiconductor device of any of the preceding embodiments, wherein the second transistor further comprises a highly-doped n-region (332) in the second HV p-body.
  • Embodiment 3-15 The semiconductor device of any of the preceding embodiments, wherein the second transistor further comprises a highly-doped n-region (334) in the second HV n-well.
  • Embodiment 3-16 A method of manufacturing a semiconductor device (5) , comprising:
  • a first transistor (30) comprising:
  • HV high-voltage
  • first HV p-body (315) in the substrate and on the insulating layer, wherein the first HV p-body is in contact with the first HV n-well;
  • a second transistor (32) comprising:
  • HV high-voltage
  • an isolation structure (505, 507) between the first transistor and the second transistor, wherein the isolation structure extends from an upper surface of the substrate to the insulating layer.
  • Embodiment 3-17 The method of the preceding embodiment, wherein the first HV n-well (317) is in contact with the isolation structure (505) .
  • Embodiment 3-18 The method of any of the preceding embodiments, wherein the first HV n-well (317) is in contact with the insulating layer (503) .
  • Embodiment 3-19 The method of any of the preceding embodiments, wherein the first HV p-body (315) is in contact with the isolation structure (507) .
  • Embodiment 3-20 The method of any of the preceding embodiments, wherein the first HV p-body (315) is in contact with the insulating layer (503) .
  • Embodiment 3-21 A semiconductor device (5) , comprising:
  • a substrate (501) comprising an insulating layer (503) buried in the substrate;
  • a first transistor (30) comprising:
  • HV high-voltage
  • first HV p-body (315) in the substrate and on the insulating layer, wherein the first HV p-body is in contact with the first HV n-well;
  • a second transistor (32) comprising:
  • HV high-voltage
  • a third transistor (30) comprising:
  • HV high-voltage
  • first isolation structure (505) between the first transistor and the second transistor, wherein the first isolation structure extends from an upper surface of the substrate to the insulating layer;
  • a second isolation structure (507) between the second transistor and the third transistor, wherein the second isolation structure extends from an upper surface of the substrate to the insulating layer.
  • Embodiment 3-22 The semiconductor device of the preceding embodiment, wherein the first isolation structure (505) is in contact with the first HV n-well (317) .
  • Embodiment 3-23 The semiconductor device of any of the preceding embodiments, wherein the first isolation structure (505) is in contact with the second HV n-well (337) .
  • Embodiment 3-24 The semiconductor device of any of the preceding embodiments, wherein the second isolation structure (507) is in contact with the second HV p-body (335) .
  • Embodiment 3-25 The semiconductor device of any of the preceding embodiments, wherein the second isolation structure (507) is in contact with the third HV p-body (315) .
  • spatially relative terms such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” “higher, “ “left, “ “right” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.
  • the terms “approximately, “ “substantially, “ “substantial” and “about” are used to describe and account for small variations. When used in conduction with an event or circumstance, the terms can refer to instances in which the event of circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally means within ⁇ 10%, ⁇ 5%, ⁇ 1%, or ⁇ 0.5%of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.
  • substantially coplanar can refer to two surfaces within micrometers ( ⁇ m) of lying along a same plane, such as within 10 ⁇ m, within 5 ⁇ m, within 1 ⁇ m, or within 0.5 ⁇ m of lying along the same plane.
  • ⁇ m micrometers
  • the term can refer to the values lying within ⁇ 10%, ⁇ 5%, ⁇ 1%, or ⁇ 0.5%of an average of the values.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La présente divulgation concerne un dispositif à semi-conducteur et son procédé de fabrication. Le dispositif à semi-conducteur comprend un substrat comprenant un puits p ; un premier transistor ; et un second transistor. Le premier transistor comprend un premier puits n à haute tension (HT) dans le puits p ; un premier contact de source sur le substrat ; un premier contact de drain sur le substrat ; un premier contact de grille sur le substrat et entre le premier contact de source et le premier contact de drain. Le second transistor comprend un second puits n HT dans le puits p ; un second contact de source sur le substrat ; un second contact de drain sur le substrat ; un second contact de grille sur le substrat et entre le second contact de source et le second contact de drain. Une partie du puits p se trouve entre le premier puits n HT et le second puits n HT.
PCT/CN2022/129755 2022-11-04 2022-11-04 Dispositif à semi-conducteur et son procédé de fabrication WO2024092689A1 (fr)

Priority Applications (2)

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CN202280044050.2A CN117616572A (zh) 2022-11-04 2022-11-04 半导体装置及其制造方法
PCT/CN2022/129755 WO2024092689A1 (fr) 2022-11-04 2022-11-04 Dispositif à semi-conducteur et son procédé de fabrication

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040150018A1 (en) * 2003-01-31 2004-08-05 Renesas Technology Corp. Semiconductor device having sense amplifier including paired transistors
US20050280101A1 (en) * 2004-06-16 2005-12-22 Cree Microwave, Inc. Laterally diffused MOS transistor having N+ source contact to N-doped substrate
US20170012043A1 (en) * 2015-07-09 2017-01-12 Stmicroelectronics Sa Substrate contact land for an mos transistor in an soi substrate, in particular an fdsoi substrate
US20170141105A1 (en) * 2015-11-16 2017-05-18 Infineon Technologies Ag Semiconductor device comprising a first transistor and a second transistor
US20170221885A1 (en) * 2016-01-29 2017-08-03 Infineon Technologies Ag Electric Circuit Including a Semiconductor Device with a First Transistor, a Second Transistor and a Control Circuit
CN108701693A (zh) * 2017-04-12 2018-10-23 香港应用科技研究院有限公司 用于静电放电(esd)保护的具有抑制环的嵌入式pmos-触发可控硅整流器(scr)

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040150018A1 (en) * 2003-01-31 2004-08-05 Renesas Technology Corp. Semiconductor device having sense amplifier including paired transistors
US20050280101A1 (en) * 2004-06-16 2005-12-22 Cree Microwave, Inc. Laterally diffused MOS transistor having N+ source contact to N-doped substrate
US20170012043A1 (en) * 2015-07-09 2017-01-12 Stmicroelectronics Sa Substrate contact land for an mos transistor in an soi substrate, in particular an fdsoi substrate
US20170141105A1 (en) * 2015-11-16 2017-05-18 Infineon Technologies Ag Semiconductor device comprising a first transistor and a second transistor
US20170221885A1 (en) * 2016-01-29 2017-08-03 Infineon Technologies Ag Electric Circuit Including a Semiconductor Device with a First Transistor, a Second Transistor and a Control Circuit
CN108701693A (zh) * 2017-04-12 2018-10-23 香港应用科技研究院有限公司 用于静电放电(esd)保护的具有抑制环的嵌入式pmos-触发可控硅整流器(scr)

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