TWI655777B - 具有深溝槽空乏和隔離結構的開關 - Google Patents

具有深溝槽空乏和隔離結構的開關 Download PDF

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TWI655777B
TWI655777B TW106125513A TW106125513A TWI655777B TW I655777 B TWI655777 B TW I655777B TW 106125513 A TW106125513 A TW 106125513A TW 106125513 A TW106125513 A TW 106125513A TW I655777 B TWI655777 B TW I655777B
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deep trench
trench isolation
region
well
isolation structures
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TW201904070A (zh
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史蒂芬Ｍ 尚克
安東尼Ｋ 史坦普
莫納漢 約翰Ｊ 艾立斯
東　泰
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格羅方德美國公司
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Abstract

本發明所揭示的內容係關於半導體結構，尤其係關於具有深溝槽空乏和隔離結構的開關和製造方法。該結構包括一塊體基板，其具有至少一個閘極堆疊之源極區和汲極區下方的一完全空乏區，並受到用摻雜材料襯裡的深溝槽隔離結構局限。

Description

具有深溝槽空乏和隔離結構的開關
本發明所揭示內容係關於半導體結構，尤其係關於具有深溝槽空乏和隔離結構的開關和製造方法。
射頻(Radio frequency，RF)裝置在許多不同類型之通訊應用中使用。舉例來說，RF裝置可與無線通訊組件(例如開關、金氧半導體場效電晶體(MOSFET)、電晶體和二極管)一起在行動電話中使用。
隨著行動電話變得更加複雜和商品化，越來越需要為該等無線通訊組件提供更高的性能和更低的價格點。舉例來說，製造RF開關成本之很大一部分，是設計製造非常高線性度以使諧波失真極低並滿足產品規格的成本。
RF裝置通常係在高電阻率矽晶圓或基板上製造，以達成所需rf線性度。最先進的阱豐富(trap rich)矽覆絕緣體(Silicon on insulator，SOI)高電阻率基板提供極佳的垂直隔離和線性度，但由於其可為高電阻率非SOI基板之成本的四倍，因此可高達該總製造成本之50%，即在阱豐富SOI晶圓上形成的rf裝置可具有1.0之總標準化製造成本，而在高電阻率非SOI塊體晶圓上形成的類似裝置可具有0.6之總標準化製造成本。然而，建構在塊體Si(矽)基板上的裝置已習知會受到降低的線性度、諧波、雜訊和漏電 流影響，其中任一者皆會降低裝置的性能，因而需要SOI晶圓之更高成本。
在所揭示內容之態樣中，一種結構包含一塊體基板，其具有至少一個閘極堆疊之源極區和汲極區下方的一完全空乏區，並受到用摻雜材料襯裡的深溝槽隔離結構局限。
在所揭示內容之態樣中，一種結構包含：一高電阻率塊體基板，其具有至少一個井區；複數射頻(RF)裝置，其在該至少一個井區上方形成；複數深溝槽隔離結構，其延伸於該至少一個井區下方，該等複數深溝槽隔離結構具有用摻雜材料襯裡的一空氣間隙或孔隙；一完全空乏區，其受到該等複數深溝槽隔離結構局限；以及一合併空乏區，其在該完全空乏區下方。
在所揭示內容之態樣中，一種方法包含：在一塊體高電阻率基板中形成至少一個井；在該塊體高電阻率基板上和該至少一個井上方形成複數主動裝置；在該至少一個井下方的基板中形成一深溝槽結構；以及用夾止的一摻雜材料襯裡該深溝槽結構，以形成一空氣間隙或孔隙。
10、10'‧‧‧結構
12‧‧‧高電阻率塊體Si(矽)基板
14‧‧‧p井
16‧‧‧淺溝槽隔離(STI)結構
18‧‧‧電晶體
18a‧‧‧源極區
18b‧‧‧汲極區
20、20"、20'''‧‧‧深溝槽隔離結構
22‧‧‧摻雜多晶矽材料
24‧‧‧空氣間隙或孔隙
24a‧‧‧球形襯裡空氣間隙或孔隙
25‧‧‧完全空乏區
25a‧‧‧合併空乏區
26‧‧‧矽化物接點
28‧‧‧阻障層
30‧‧‧層間介電體材料
32、32a‧‧‧接點
34‧‧‧線路結構
50、50a、50b‧‧‧共用閘極
100‧‧‧佈局視圖
本發明所揭示內容藉由本發明所揭示內容之示例性具體實施例之非限制性範例，參照該等所提及的複數圖式在接下來的實施方式中進行說明。
圖1顯示依據本發明所揭示內容之態樣的結構和各自製程。
圖2顯示依據本發明所揭示內容之附加態樣的結構和各自製程。
圖3顯示依據本發明所揭示內容之態樣的圖1至圖2之該等結構之佈局視圖。
本發明所揭示內容係關於半導體結構，尤其係關於具有深溝槽空乏和隔離結構的開關和製造方法。更具體而言，本發明所揭示內容係關於具有前端模組收發器中所使用的深溝槽隔離結構的射頻(RF)開關。具優勢地，與該等RF開關一起使用的該等深溝槽隔離結構，為建構在塊體Si基板和高電阻率塊體Si基板上的裝置改進漏電流、雜訊和線性度(諧波)。此外，文中所說明的該等結構更可減少待機功率。
在具體實施例中，該等深溝槽隔離結構圍繞場效電晶體(FET)開關和其他互補金氧半導體(CMOS)裝置，以為空乏區提供隔離。事實上，文中所說明的該等深溝槽隔離結構可與具有不同基板偏壓的任何主動裝置一起使用。舉例來說，該等深溝槽隔離結構可在具有受到最小基本規範(例如溝槽關鍵尺寸(CD)和覆蓋層)限制的間隔的雙井或三井堆疊開關FET中使用。該等深溝槽隔離結構與已習知溝槽隔離(trench isolation，簡稱TI)結構或淺溝槽隔離(shallow trench isolation，簡稱STI)結構不同。舉例來說，TI或STI為未延伸超出該p井(即0.5-1.0微米深)的淺結構；而該等深溝槽隔離結構形成為數μm深，例如5μm-60μm深，這提供與生成諧波失真的井電荷隔離。舉例來說，文中所說明的該等深溝槽隔離結構之實作可達成使基板漏電流減少100倍，即1uA/um至1nA/um，同時也基於130-180nm技術提供20dBm「H2」和15dBm「H3」改進。
本發明所揭示內容之該等結構可使用若干不同的工具以若干方式製造。不過，一般來說，該等方法和工具係用於形成尺寸為微米和奈米尺度的結構。製造本發明所揭示內容之該等結構所採用的該等方法(即技術)，係從積體電路(IC)技術導入。舉例來說，該等結構建構在晶圓上，並在晶圓上方以光微影成像製程所圖案化的材料膜實現。特別是，該等結構之製造使用三種基本建構模塊：(i)在基板上沉積材料薄膜、(ii)透過光微 影成像在該等膜上方施加圖案化圖罩，以及(iii)對該圖罩選擇性地蝕刻該等膜。
圖1顯示依據本發明所揭示內容之態樣的結構和各自製程。特別是，結構10可為建構在基板12上的RF開關FET，例如P型基板。在具體實施例中，基板12可為具有高電阻率的塊體Si。在具體實施例中，作為例示性範例，高電阻率塊體Si基板12可具有在約1Kohm-cm至10Kohm-cm之間或更大之範圍內的電阻率。更高的電阻率也可設想成高達20Kohm-cm。應可認可10Kohm-cm之電阻率足以大幅減少基板誘發諧波失真。在具體實施例中，基板12可由任何適合的半導體材料組成，例如Si(矽)、SiGe(鍺化矽)、SiGeC(矽鍺碳)、SiC(碳化矽)、GaAs(砷化鎵)、InAs(砷化銦)、InP(磷化銦)和其他III/V族或II/VI族化合物半導體。
仍參照圖1，基板12包括一p井區14。在具體實施例中，p井區14可透過使用例如硼的任何慣用離子植入或擴散製程形成，以獲得適合的井深度和摻雜分布。複數淺溝槽隔離(STI)結構16在延伸穿越p井區14和電晶體18之間的基板12中形成。在具體實施例中，作為範例，該等STI結構16可由氧化物材料組成。該等STI結構16可透過使用慣用微影、蝕刻和沉積步驟，接著為化學機械拋光(chemical mechanical polishing，簡稱CMP)步驟而形成。在較佳具體實施例中，該等STI結構16創建出圍繞該等電晶體18的凸環，並延伸於p井區14下方，以防止p井區14中的崩潰。舉例來說，該等STI結構16之深度可為約0.5μm至約10μm。
圖1進一步顯示穿越該等p井區14所形成並圍繞該等電晶體18的深溝槽隔離結構20。在具體實施例中，該等深溝槽隔離結構20可穿越該等STI結構16形成，且較佳為超出p井區14之深度。該等深溝槽隔離結構20可間隔預定距離「Y」。在具體實施例中，該預定距離「Y」可為約10μm至15μm；然而文中也設想其他尺寸。該等深溝槽隔離結構20將該等p井區14與相鄰井區(例如n井和p井區)隔離。據此，透過提供該 等深溝槽隔離結構20，現在可能減少高電阻率塊體基板上的諧波、改進漏電流，並減少雜訊。
該等深溝槽隔離結構20可在形成該等STI結構16之前或之後，使用慣用微影和蝕刻製程，接著為沉積襯裡製程而形成。舉例來說，光阻可在基板12上方形成，並暴露於能量(光)以形成圖案(開孔)。具有選擇性化學性質的反應性離子蝕刻(reactive ion etching，簡稱RIE)製程可用於在基板12中形成深溝槽。該深溝槽之深度可為低於p井區14，且更佳可為30μm或更大，例如深度約30μm至約100μm，且更佳為約30μm至約50μm。在進一步具體實施例中，該等深溝槽隔離結構20可形成為塊體基板12之背面研磨介面，以將相鄰井區和該等RF裝置與DC基板電流完全隔離。該深溝槽之直徑或寬度可為約1μm；然而除了其他因素之外，文中也依該技術節點而定設想其他尺寸。該光阻可透過慣用剝離劑或氧氣灰化製程去除。
如圖1進一步所示，該深溝槽可用多晶矽材料22、更具體而言可用摻雜多晶矽材料22襯裡，以形成深溝槽隔離結構20。在具體實施例中，該摻雜物可為n型摻雜物(例如砷或磷)，或p型摻雜物(例如硼)。在具體實施例中，摻雜多晶矽材料22可在深溝槽隔離結構20之該等側壁上沉積成約0.25μm之厚度。
摻雜多晶矽材料22可透過原位製程摻雜，或者可由包含本質(未摻雜)多晶矽材料、接著為摻雜多晶矽材料之交替層的雙層或多層襯裡組成。在該後者情境下，該本質(未摻雜)多晶矽材料可在深溝槽隔離結構20之側壁上直接形成，以防止摻雜物擴散到基板12中。在具體實施例中，摻雜多晶矽材料22可使用任何慣用化學氣相沉積(CVD)製程沉積，其中包括例如一低壓化學氣相沉積(low pressure chemical vapor deposition，簡稱LPCVD)製程或一快速熱化學氣相沉積(rapid thermal chemical vapor deposition，簡稱RTCVD)製程。在任何沉積製程中，空氣間隙或孔隙24皆 透過「夾止(p inch off)」深溝槽隔離結構20上方處的摻雜多晶矽材料22，在深溝槽隔離結構20內創建出。如此，摻雜材料22將形成或包覆提供深溝槽隔離結構20之減低電容的空氣間隙或孔隙24。
圖1進一步顯示受到該等深溝槽隔離結構20局限的完全空乏矽區25。在具體實施例中，完全空乏區25在該等源極/汲極擴散(例如源極區18a和汲極區18b)之底部和通道區下方並與其接觸。合併空乏區25a透過對摻雜多晶矽材料22施加偏壓，跨越該開關(例如電晶體18)之寬度創建出。在具體實施例中，該偏壓或電壓可對與摻雜多晶矽材料22直接電接觸的接點32a施加。在具體實施例中，作為範例，摻雜多晶矽材料22上的偏壓可為-3.3V；然而除了其他因素之外，其他偏壓可依摻雜多晶矽材料22之帶隙電壓、摻雜物濃度而定施加。在具體實施例中，在-3.3V下，合併空乏區25a可距離該等深溝槽隔離結構20之側壁約5μm至8μm，如由「X」表示。
已查出跨越該開關(例如電晶體18)之寬度的合併空乏區在該本體偏壓時減少待機功率100倍(相較於慣用結構)。這透過將基板電流從uA減少為nA達成。此外，合併空乏區25a並非幾何尺寸相關，其中該空乏深度無關於裝置偏壓。此外，由於相較於三井接面裝置的廣大面積空乏區，因此非線性電容減少且線性度改進。再者，如熟習此項技術者應可理解，進入基板12的源極/汲極接面空乏深度將隨著該開關(例如電晶體18)之該等導通/截止循環而振盪，而該等深溝槽隔離結構20之空乏維持固定。
仍參照圖1，在具體實施例中，該等電晶體18可為主動RF裝置(例如RF開關)，或其他主動或被動裝置。如本領域已習知，該等電晶體18可使用交替源極/汲極/源極/汲極/等配置之陣列中的多個閘極形成。在具體實施例中，該等堆疊(例如電晶體)之間的間隔可為小於2μm；然而也依該技術節點而定設想其他尺寸。如此領域一般技術者應也可理解，該等電晶體18可透過慣用CMOS製程形成，其中包括沉積閘極介電體(例如氧 化鉿等高k介電體)，接著為閘極金屬(例如不同的功函數金屬)，使用微影和蝕刻(例如反應離子蝕刻(RIB)以形成該等閘極堆疊，接著為側壁形成(例如在該等閘極堆疊上沉積的氧化物或氮化物材料))圖案化該等材料。源極區18a和汲極區18b使用慣用摻雜物或離子植入製程，(例如為凸起的源極區和汲極區)在基板12內或基板12上形成，因此無需進一步解說。在具體實施例中，磊晶成長製程可用於形成凸起的源極區和汲極區。
如圖1進一步所示，矽化物接點26在該等源極區18a和汲極區18b上形成，以及如有需要在深溝槽隔離結構20上方形成。在具體實施例中，該矽化物製程開始於在完全形成和圖案化的半導體裝置(例如摻雜或離子植入源極區和汲極區18a、18b以及各自裝置18)上方沉積薄過渡金屬層，例如鎳、鈷或鈦。在沉積該材料之後，將該結構加熱允許該過渡金屬與形成低電阻過渡金屬矽化物的半導體裝置(例如源極、汲極、閘極接觸區)之該等主動區中的暴露矽(或如文中所說明的其他半導體材料)反應。接著該反應，任何剩餘的過渡金屬皆透過化學蝕刻去除，從而在該等裝置(例如電晶體18)之該等主動區中留下矽化物接點26。阻障層28可在該等裝置(例如電晶體18)之該等主動區中的該等矽化物接點26上方形成。阻障層28可為使用慣用沉積製程(例如CVD製程)沉積的阻障氮化物膜。
層間介電體材料30可在該結構之該等暴露表面上方形成，例如在該等電晶體18和阻障層28上方。層間介電體材料30可為使用任何慣用沉積製程(例如CVD)沉積的氧化物材料。接點32、32a使用金屬或金屬合金製程之慣用微影、蝕刻和沉積，在層間介電體材料30內形成。該等接點32將與該等矽化物接點26直接電接觸；而該等接點32a與深溝槽隔離結構20之摻雜多晶矽材料22(在具體實施例中穿越矽化物區)直接電接觸。在替代具體實施例中，電阻(例如多晶矽、擴散等)可連結到該等深溝槽隔離結構20，其將透過該電阻偏壓深溝槽隔離結構20(例如深溝槽隔離結構20之摻雜材料)以改進崩潰。該電阻也在參考號碼26處反映。在附加具 體實施例中，接面場效電晶體(JFET)空乏區可用作沒有該新增寄生的三井。該等線路結構34之佈線層和其他後端，再次使用慣用CMOS沉積和圖案化製程與該等接點32、32a接觸形成。
圖2顯示依據本發明所揭示內容之附加態樣的結構和各自製程。更具體而言，除了從深溝槽隔離結構20之底部延伸的球形襯裡空氣間隙或孔隙24a之外，圖2所示的結構10'包括圖1所說明的該等結構和材料。在具體實施例中，球形襯裡空氣間隙或孔隙24a可擴展空乏區25，並促進p井14下方的合併25a。
在具體實施例中，深溝槽隔離結構20和球形襯裡空氣間隙或孔隙24a可用多晶矽材料22、更具體而言摻雜多晶矽材料22襯裡。在具體實施例中，該摻雜物可為n型摻雜物(例如砷或磷)，或p型摻雜物(例如硼)。在進一步具體實施例中，摻雜多晶矽材料22可在深溝槽隔離結構20和球形襯裡空氣間隙或孔隙24a之該等側壁上沉積成約0.25μm之厚度。
在具體實施例中，球形襯裡空氣間隙或孔隙24a可透過慣用微影和蝕刻製程形成。舉例來說，在形成深溝槽隔離結構20之後，熱氧化物材料(TEOS)或CVD氧化物可在該等深溝槽隔離結構20內沉積，以襯裡其底部和側壁。該等襯裡深溝槽隔離結構20隨後經歷各向異性蝕刻製程，以從深溝槽隔離結構20之底面去除該氧化物材料，例如以暴露基板12。接著該各向異性蝕刻製程，進行各向同性蝕刻製程以蝕刻暴露的基板12，以形成球形空氣間隙或孔隙24a。球形空氣間隙或孔隙24a和該等深溝槽隔離結構20隨後可用摻雜多晶矽材料22襯裡。在具體實施例中，球形空氣間隙或孔隙24a可具有約6μm之圓周。
如關於圖1之結構10所說明，合併空乏區25a透過對摻雜多晶矽材料22施加偏壓，跨越該開關(例如電晶體18)之寬度形成。在具體實施例中，合併空乏區25a可距離深溝槽隔離結構20之側壁約5μm至8μm，如由「X」表示，以及距離球形襯裡空氣間隙或孔隙24a之側壁約2μm 至5μm，如由「X'」表示。
如先前所說明，摻雜多晶矽材料22可透過原位製程摻雜，或者可由該等深溝槽隔離結構20之該等側壁上該剩餘的氧化物襯裡上方的本質(未摻雜)多晶矽材料、接著為摻雜多晶矽材料之交替層之雙層或多層襯墊組成，如也由參考號碼22表示。該本質(未摻雜)多晶矽材料和/或氧化物材料將防止摻雜物擴散到基板12中。摻雜多晶矽材料22可使用任何慣用化學氣相沉積(CVD)製程(例如LPCVD、RTCVD等)沉積。
圖3顯示依據本發明所揭示內容之態樣的圖1和圖2之該等結構之俯視圖佈局視圖。更具體而言，佈局視圖100顯示平行對準的複數電晶體18，例如RF開關或其他FET。源極區和汲極區18a、18b在該等複數電晶體18之間提供。共用閘極50顯示連接到每個該等複數電晶體18。在具體實施例中，共用閘極50可為例如多晶矽閘極(poly gate)。深溝槽隔離結構20可在共用閘極50之側面上和/或底下或其任何組合提供。舉例來說，該等深溝槽隔離結構20"可在共用閘極50a底下，且該等深溝槽隔離結構20'''可在共用閘極50b之側面上。應可進一步理解，可提供圖3所示的多個佈局，其中深溝槽隔離結構20"在該等複數電晶體18之上部和下部之中分享。
相較於文中所說明的該等結構，高電阻率Si晶圓應用透過減少基板載具誘發諧波提供改進線性度；然而，高電阻率空乏區可延展5μm至100μm深或更深到該基板中，從而導致相鄰裝置之間的洩漏和諧波失真。三井阻止空乏區合併(即相鄰p井之空乏區)，並防止DC基板電流與p井區和FET交互作用。然而，合併的三井空乏區可因該等井區之間的耦合而導致諧波失真、新增寄生電容，這會降低負通道場效電晶體(NFET)開關電性質，例如關斷電容(off capacitance，Coff)，並增加成本。三井區也導致新增進一步增加諧波失真的非線性電容的附加電接面。這些問題現在透過實行文中所說明的該等結構和方法，以更低的成本滿足需求並加以解決。應注意，儘管該描述顯示參照開關，但在高電阻率基板上形成的任何主動 或被動裝置皆可能使用該等製程，並產生文中所說明的結構以改進裝置隔離和線性度。
如上述所說明的該(等)方法係用於製造積體電路晶片。該等所得到的積體電路晶片可由該製造者以原始晶圓形式(即作為具有多個未封裝晶片的單一晶圓)、作為裸晶粒或以封裝形式分布。在該後者情況下，該晶片以單一晶片封裝(例如具有貼附於母板或其他更高層載體的引線的塑料載體)或以多晶片封裝(例如具有表面內連線或埋藏內連線任一者或兩者的陶瓷載體)進行封固。在任何情況下，該晶片隨後皆與其他晶片、分立電路元件和/或其他信號處理裝置整合，擇一作為(a)中間產品(例如母板)或(b)最終產品之一部分。該最終產品可為包括積體電路晶片的任何產品，範圍從玩具和其他低階應用到具有顯示器、鍵盤或其他輸入裝置和中央處理器的先進電腦產品皆包括。
本發明所揭示內容之該等各種具體實施例之該等說明已為了例示之目的而進行描述，但不欲為全面性或限於所揭示的該等具體實施例。許多修飾例和變化例對此領域一般技術者而言應為顯而易見，而不悖離該等所說明的具體實施例之範疇與精神。文中所使用的術語係選擇以最好地解說該等具體實施例之該等原理、對市場中所發現的技術的實際應用或技術改進，或讓此領域其他一般技術者能理解文中所揭示的該等具體實施例。

Claims (20)

  1. 一種開關結構包含一塊體基板，其具有至少一個閘極堆疊之源極區和汲極區下方的一完全空乏區，並受到用摻雜材料襯裡的深溝槽隔離結構局限。
  2. 如申請專利範圍第1項所述之結構，其中該塊體基板為電阻率大於或等於約10Kohm-cm的一高電阻率塊體基板。
  3. 如申請專利範圍第1項所述之結構，其中該完全空乏區接觸該等源極區和汲極區之一底部。
  4. 如申請專利範圍第1項所述之結構，其中閘極堆疊之間的一間隔小於2μm。
  5. 如申請專利範圍第1項所述之結構，其中該摻雜材料為該等深溝槽隔離結構之一側壁上的一n型摻雜多晶矽材料或p型摻雜多晶矽材料。
  6. 如申請專利範圍第5項所述之結構，更包含未摻雜材料，其在該摻雜材料底下和該深溝槽隔離結構之側壁上。
  7. 如申請專利範圍第1項所述之結構，其中該等深溝槽隔離結構包括一空氣間隙或孔隙。
  8. 如申請專利範圍第1項所述之結構，其中該等深溝槽隔離結構具有一深度，其大於在該等源極區和汲極區下方的塊體基板中形成的一井區。
  9. 如申請專利範圍第8項所述之結構，更包含一合併空乏區，其在該等深溝槽隔離結構之間和該井區下方。
  10. 如申請專利範圍第1項所述之結構，其中該等深溝槽隔離結構隔離在該井區上形成的射頻(RF)開關。
  11. 如申請專利範圍第1項所述之結構，其中該等深溝槽隔離結構包括一球形空氣間隙或孔隙，其用該摻雜材料襯裡，且該等深溝槽隔離結構用該摻雜材料底下的一氧化物材料襯裡。
  12. 如申請專利範圍第1項所述之結構，更包含接點，其向該摻雜材料提供一電偏壓。
  13. 一種開關結構包含：一高電阻率塊體基板，其具有至少一個井區；複數射頻(RF)裝置，其在該至少一個井區上方形成；複數深溝槽隔離結構，其延伸於該至少一個井區下方，該等複數深溝槽隔離結構具有用摻雜材料襯裡的一空氣間隙或孔隙；一完全空乏區，其受到該等複數深溝槽隔離結構局限；以及一合併空乏區，其在該完全空乏區下方。
  14. 如申請專利範圍第13項所述之結構，其中該等複數深溝槽隔離結構隔離在該至少一個井區上形成的射頻開關。
  15. 如申請專利範圍第13項所述之結構，其中該等複數深溝槽隔離結構包括一球形空氣間隙或孔隙，其用該摻雜材料襯裡，且該等深溝槽隔離 結構用該摻雜材料底下的一氧化物材料襯裡。
  16. 如申請專利範圍第13項所述之結構，其中該摻雜材料可為具有摻雜多晶矽和未摻雜多晶矽的一雙層或多層。
  17. 如申請專利範圍第13項所述之結構，更包含接點，其向該摻雜材料提供一電偏壓。
  18. 如申請專利範圍第13項所述之結構，其中該深溝槽隔離結構形成為該塊體基板之一背面研磨介面，以將相鄰井區和該等RF裝置與直流(DC)基板電流完全隔離。
  19. 一種製造具有深溝槽空乏和隔離結構的開關的方法，包含：在一塊體高電阻率基板中形成至少一個井；在該塊體高電阻率基板上和該至少一個井上方形成複數主動裝置；在該至少一個井下方的基板中形成一深溝槽結構；以及用夾止(pinch off)的一摻雜材料襯裡該深溝槽結構，以形成一空氣間隙或孔隙；其中該複數主動裝置下方的一完全空乏區受到用摻雜材料襯裡的深溝槽隔離結構局限。
  20. 如申請專利範圍第19項所述之方法，更包含形成用從該深溝槽結構延伸的摻雜材料襯裡的一球形空氣間隙或孔隙。
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