CN108987462B - 具有深沟槽耗尽和隔离结构的开关 - Google Patents

具有深沟槽耗尽和隔离结构的开关 Download PDF

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CN108987462B
CN108987462B CN201710817698.XA CN201710817698A CN108987462B CN 108987462 B CN108987462 B CN 108987462B CN 201710817698 A CN201710817698 A CN 201710817698A CN 108987462 B CN108987462 B CN 108987462B
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deep trench
trench isolation
semiconductor structure
doped
bulk substrate
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CN108987462A (zh
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S·M·尚克
A·K·斯塔珀
J·J·埃利斯-莫纳甘
T·段
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Lattice Core Usa Inc
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Abstract

本公开涉及半导体结构，更具体地，涉及具有深沟槽耗尽和隔离结构的开关及其制造方法。所述结构包括具有在至少一个栅极叠层的源极区和漏极区之下且被衬有掺杂材料的深沟槽隔离结构限定的全耗尽区的体衬底。

Description

具有深沟槽耗尽和隔离结构的开关
技术领域
本公开涉及半导体结构，更具体地，涉及具有深沟槽耗尽和隔离结构的开关及其制造方法。
背景技术
射频(RF)器件用于许多不同类型的通信应用中。例如，RF器件可以用于具有诸如开关、MOSFET、晶体管和二极管的无线通信部件的蜂窝电话中。
随着蜂窝电话变得更复杂和商品化，越来越需要为无线通信部件提供更高的性能和更低的价格点。例如，制造RF开关的成本的显著一部分是设计非常高的线性度以使得谐波失真非常低并且满足产品规格的成本。
RF器件通常在高电阻率硅晶片或衬底上制造以实现所需的rf线性度。目前的富陷阱绝缘体上硅(SOI)高电阻率衬底提供良好的垂直隔离和线性度，但高达总制造成本的50％，因为它们可以是高电阻率非SOI衬底的成本的四倍。即，形成在富陷阱SOI晶片上的rf器件具有1.0的总归一化制造成本，而形成在高电阻率非SOI体晶片上的类似器件可以具有0.6的总归一化制造成本。然而，已经知道在体Si衬底上构建的器件遭受劣化的线性度、谐波、噪声和泄漏电流，其中任何一种将劣化器件性能，从而需要更高成本的SOI晶片。
发明内容
在本公开的一个方面中，结构包括具有在至少一个栅极叠层的源极和漏极区之下且被衬有掺杂材料的深沟槽隔离结构限定的全耗尽区的体衬底。
在本公开的一个方面中，结构包括：具有至少一个阱区的高电阻率体衬底；在该至少一个阱区上形成的多个射频(RF)器件；在该至少一个阱区之下延伸的多个深沟槽隔离结构，多个深沟槽隔离结构具有衬有掺杂材料的空气隙或空隙；由多个深沟槽隔离结构限定的全耗尽区；以及在该全耗尽区之下的合并耗尽区。
在本公开的一个方面中，方法包括：在体高电阻率衬底中形成至少一个阱；在该体高电阻率衬底上并在该至少一个阱上方形成多个有源器件；在该至少一个阱之下的衬底中形成深沟槽结构；并用掺杂的材料来加衬深沟槽结构，其可以夹断以形成空气隙或空隙。
附图说明
在下面的详细描述中通过本公开的示例性实施例的非限制性示例参考所述多个附图来描述本公开。
图1示出了根据本公开的方面的结构和相应的制造工艺。
图2示出了根据本公开的附加方面的结构和相应的制造工艺。
图3示出了根据本公开的方面的图1和图2的结构的布局图。
具体实施方式
本公开涉及半导体结构，更具体地，涉及具有深沟槽耗尽和隔离结构的开关及其制造方法。更具体地，本公开涉及用于前端模块收发器的具有深沟槽隔离结构的射频(RF)开关。有利地，与RF开关一起使用的深沟槽隔离结构改善了构建在体Si衬底和高电阻率体Si衬底上的器件的泄漏电流、噪声和线性度(谐波)。此外，在此所述的结构进一步降低待机功率。
在实施例中，深沟槽隔离结构围绕FET开关和其它CMOS器件，以为耗尽区提供隔离。事实上，在此所述的深沟槽隔离结构可以与具有不同衬底偏置的任何有源器件一起使用。例如，深沟槽隔离结构可用于具有由最小基准规则(例如，沟槽CD和覆盖层)限制的间隔的双阱或三阱叠层开关FET。深沟槽隔离结构与已知的沟槽隔离(TI)结构或浅沟槽隔离(STI)结构不同。作为示例，TI或STI是不延伸超过p阱，即0.5至1.0微米深的浅结构；而深沟槽隔离结构形成为几个μm深，例如5μm至60μm深，这提供了与产生谐波失真的阱电荷的隔离。例如，在此所述的深沟槽隔离结构的实施可以使衬底泄漏电流减少100倍，即1uA/μm至1nA/um，同时基于130至180nm技术还提供20dBm“H2”和15dBm“H3”的改善。
本公开的结构可以使用多个不同的工具以多种方式来制造。通常，方法和工具用于形成尺寸在微米和纳米级的结构。用于制造本公开的结构的方法，即技术，已经采用自集成电路(IC)技术。例如，这些结构构建在晶片上，并且在晶片顶部上通过光刻工艺图案化的材料膜来实现。具体地，结构的制造使用三个基本构建块：(i)在衬底上沉积材料薄膜，(ii)通过光刻成像在膜的顶部上施加图案化掩模，以及(iii)将膜选择性地蚀刻到掩模。
图1示出了根据本公开的方面的结构和相应的制造工艺。具体地，结构10可以是构建在衬底12(例如，P型衬底)上的RF开关FET。在实施例中，衬底12可以是具有高电阻率的体Si。在实施例中，作为说明性示例，高电阻率体Si衬底12可以具有如下范围内的电阻率：在大约1Kohm-cm至10Kohm-cm或更大的电阻率之间。还可以考虑高达20Kohm-cm的更高电阻率。应当认识到，10Kohm-cm的电阻率足以显著降低衬底诱导的谐波失真。在实施例中，衬底12可以由任何合适的诸如Si、SiGe、SiGeC、SiC、GaAs、InAs、InP以及其它III/V或II/VI化合物半导体的半导体材料构成。
仍参考图1，衬底12包括p阱区14。在实施例中，p阱区14可以通过使用例如硼的任何常规的离子注入或扩散工艺来形成，以获得合适的阱深度和掺杂分布。多个浅沟槽隔离(STI)结构16延伸穿过p阱区14且在晶体管18之间的衬底12中形成。在实施例中，作为示例，STI结构16可以由氧化物材料构成。STI结构16可以通过使用常规的光刻、蚀刻和沉积步骤以及之后的化学机械抛光(CMP)步骤来形成。在优选实施例中，STI结构16生成围绕晶体管18的环(collar)，并且在p阱区14下方延伸，以防止p阱区14中的击穿。作为示例，STI结构16的深度可以是大约0.5μm至大约10μm。
图1还示出了穿过p阱区14且围绕晶体管18形成的深沟槽隔离结构20。在实施例中，深沟槽隔离结构20可以通过STI结构16形成，并且优选地超过p阱区14的深度。深沟槽隔离结构20可以以预定距离“Y”间隔开。在实施例中，预定距离“Y”可以是大约10μm至15μm；尽管在此考虑了其它尺寸。深沟槽隔离结构20将p阱区14与相邻的阱区(例如，n阱区和p阱区)隔离。因此，通过提供深沟槽隔离结构20，现在可以在高电阻率体衬底上减少谐波、改善泄漏电流，并降低噪声。
深沟槽隔离结构20可以在形成STI结构16之前或之后，使用常规的光刻和蚀刻工艺以及之后的沉积衬里工艺来形成。例如，抗蚀剂可以在衬底12之上形成并暴露于能量(光)以形成图案(开口)。具有选择性化学反应的RIE工艺可用于在衬底12中形成深沟槽。深沟槽的深度可以在p阱区14的之下，更优选地，可以是30μm或更大的深度，例如，大约30μm至大约100μm，更优选为大约30μm至大约50μm。在另一实施例中，深沟槽隔离结构20可以形成至体衬底12的背面研磨界面，以将相邻的阱区和RF器件与DC衬底电流完全隔离。深沟槽的直径或宽度可以为大约1μm；尽管取决于技术节点以及其它因素，在此也考虑其它尺寸。抗蚀剂可以通过常规的剥离剂(stripant)或氧灰化工艺去除。
如图1进一步所示，深沟槽可以衬有多晶硅材料22，更具体地，掺杂多晶硅材料22以形成深沟槽隔离结构20。在实施例中，掺杂剂可以是例如砷或磷的n型掺杂剂，或例如硼的p型掺杂剂。在实施例中，掺杂的多晶硅材料22可以在深沟槽隔离结构20的侧壁上沉积至大约0.25μm的厚度。
掺杂的多晶硅材料22可以通过原位工艺来掺杂，或者可选地，可以由双层或多层衬里构成，该双层或多层衬里包括本征(未掺杂)的多晶硅材料和之后的掺杂的多晶硅材料的交替层。在后一种情况下，本征(未掺杂)多晶硅材料可以直接形成在深沟槽隔离结构20的侧壁上，以防止掺杂剂扩散到衬底12中。在实施例中，掺杂的多晶硅材料22可以使用任何常规的化学气相沉积(CVD)工艺来沉积，包括例如低压化学气相沉积(LPCVD)工艺或快速热化学气相沉积(RTCVD)工艺。在任何沉积工艺中，在深沟槽隔离结构20的顶部处，通过掺杂的多晶硅材料22的“夹断”，在深沟槽隔离结构20内产生空气隙或空隙24。以这种方式，掺杂材料22将形成或包封空气隙或空隙24，空气隙或空隙24提供深沟槽隔离结构20的减小的电容。
图1还示出了由深沟槽隔离结构20限定的全耗尽硅区25。在实施例中，全耗尽区25在源极/漏极扩散(例如，源极区18a和漏极区18b)和沟道区的底部之下，并与源极/漏极扩散(例如，源极区18a和漏极区18b)和沟道区的底部接触。通过向掺杂的多晶硅材料22施加偏置，合并的(merged)耗尽区25a跨越开关(例如，晶体管18)的宽度而产生。在实施例中，可以将偏置或电压施加到与掺杂的多晶硅材料22直接电接触的接触32a。在实施例中，作为示例，掺杂的多晶硅材料22上的偏置可以是-3.3V；尽管可以根据带隙电压、掺杂的多晶硅材料22的掺杂剂浓度等其它因素来施加其它偏置。在实施例中，在-3.3V时，合并的耗尽区25a可以距离深沟槽隔离结构20的侧壁大约5μm至8μm，如通过“X”所示。
已经发现在体被偏置时，跨越开关(例如，晶体管18)宽度的合并耗尽区将待机功率降低100倍(与传统结构相比)。这是通过将衬底电流从uA减少到nA来实现。此外，合并耗尽区25a不是几何依赖的，耗尽深度与器件偏置电压无关。此外，与三阱结器件相比，由于大面积的耗尽区，非线性电容被减小并且线性度得到改善。此外，如本领域技术人员应当理解的，进入到衬底12的源极/漏极结耗尽深度将随着开关(例如，晶体管18)的导通/截止循环而振荡，而深沟槽隔离结构20的耗尽保持固定。
仍然参考图1，在实施例中，晶体管18可以是有源RF器件，例如，RF开关或其它有源或无源器件。如本领域已知的，晶体管18可以使用以阵列形式交替的源极/漏极/源极/漏极/等结构的多栅极来形成。在实施例中，叠层(例如，晶体管)之间的间隔可以小于2μm；尽管根据技术节点考虑其它尺寸。本领域普通技术人员还应该理解，晶体管18可以通过常规的CMOS工艺形成，包括沉积栅极电介质(例如，高k电介质，诸如氧化铪等)，之后是栅极金属(例如，不同功函数金属)，使用光刻和蚀刻(例如，反应离子蚀刻(RIE))图案化材料以形成栅极叠层，之后是侧壁的形成(例如，沉积在栅极叠层上的氧化物或氮化物材料)。源极区18a和漏极区18b使用常规的掺杂剂或离子注入工艺在衬底12内或衬底12上(例如，对于凸起的源极区和漏极区)形成，以使得不需要进一步的解释。在实施例中，外延生长工艺可用于形成凸起的源极区和漏极区。
如图1进一步所示，硅化物接触26形成在源极区18a和漏极区18b上，并且如果需要，形成在深沟槽隔离结构20之上。在实施例中，硅化物工艺开始于薄的过渡金属层(例如，镍、钴或钛)的沉积，结束于完全形成且图案化的半导体器件(例如，掺杂或离子注入的源极和漏极区18a、18b和相应的器件18)。在沉积材料之后，加热该结构，允许过渡金属在半导体器件的有源区(例如，源极、漏极、栅极接触区)中与暴露的硅(或在此所述的其它半导体材料)反应，形成低电阻过渡金属硅化物。在反应之后，通过化学蚀刻去除任何剩余的过渡金属，将硅化物接触26留在器件(例如，晶体管18)的有源区中。阻挡层28可以在器件(例如，晶体管18)的有源区中的硅化物接触26之上形成。阻挡层28可以是使用常规的沉积工艺(例如，CVD工艺)来沉积的阻挡氮化物膜。
层间电介质材料30可以形成在暴露的结构表面之上，例如，在晶体管18和阻挡层28之上。层间电介质材料30可以是使用任何常规的沉积工艺(例如，CVD)来沉积的氧化物材料。使用常规的光刻、蚀刻和沉积金属或金属合金工艺，在层间电介质材料30内形成接触32、32a。接触32将与硅化物接触26直接电接触；而接触32a与深沟槽隔离结构20的掺杂的多晶硅材料22(在实施例中通过硅化物区)直接电接触。在可替代实施例中，电阻器(例如，多晶硅、扩散等)可被连接到深沟槽隔离结构20，其将通过电阻器偏置深沟槽隔离结构20(例如，深沟槽隔离结构20的掺杂材料)以改善击穿。电阻器也在参考标记26处反映。在另外的实施例中，JFET耗尽区可以用作三阱而没有增加的寄生。线结构34的接线层和其它后端形成为与接触32、32a接触，再次使用常规的CMOS沉积和图案化工艺。
图2示出了根据本公开的附加方面的结构和相应的制造工艺。更具体地，图2中所示的结构10'包括图1中所描述的结构和材料，除了从深沟槽隔离结构20的底部延伸的球形衬里的空气隙或空隙24a之外。在实施例中，该球形衬里的空气隙或空隙24a可以扩大耗尽区25并促进在p阱14之下的合并25a。
在实施例中，深沟槽隔离结构20和球形衬里的空气隙或空隙24a可以衬有多晶硅材料22，更具体地，掺杂的多晶硅材料22。在实施例中，掺杂剂可以是例如砷或磷的n型掺杂剂，或例如硼的p型掺杂剂。在另外的实施例中，掺杂的多晶硅材料22可以在深沟槽隔离结构20的侧壁和球形衬里的空气隙或空隙24a上沉积至大约0.25μm的厚度。
在实施例中，球形衬里的空气隙或空隙24a可以通过常规的光刻和蚀刻工艺来形成。通过示例，在形成深沟槽隔离结构20之后，可以在深沟槽隔离结构20内沉积热氧化物材料(TEOS)或CVD氧化物以加衬底部及其侧壁。加衬的深沟槽隔离结构20然后进行各向异性蚀刻工艺以从深沟槽隔离结构20的底表面去除氧化物材料，例如，以暴露衬底12。在各向异性蚀刻工艺之后，执行各向同性蚀刻工艺以蚀刻暴露的衬底12以形成球形空气隙或空隙24a。球形空气隙或空隙24a和深沟槽隔离结构20然后可以衬有掺杂的多晶硅材料22。在实施例中，球形空气隙或空隙24a可以具有大约6μm的周长。
如关于图1的结构10所描述的，通过向掺杂的多晶硅材料22施加偏置，合并的耗尽区25a跨越开关(例如，晶体管18)的宽度而产生。在实施例中，合并的耗尽区25a可以远离深沟槽隔离结构20的侧壁大约5μm至8μm，如通过“X”所示，以及远离球形衬里的空气隙或空隙24a的侧壁大约2μm至5μm，如通过“X”所示。
如前所述，掺杂的多晶硅材料22可以通过原位工艺掺杂，可替代地，可以由在深沟槽隔离结构20的侧壁上的剩余氧化物衬里之上的本征(未掺杂)多晶硅材料和之后的掺杂多晶硅材料的交替层的双层或多层衬里组成，也是由参考标记22表示。本征(未掺杂)多晶硅材料和/或氧化物材料将防止掺杂剂扩散到衬底12中。掺杂的多晶硅材料22可以使用任何常规的化学气相沉积(CVD)工艺(例如，LPCVD、RTCVD等)来沉积。
图3示出了根据本公开方面的图1和图2的结构的顶视布局图。更具体地，布局图100示出了平行排列的多个晶体管18，例如，RF开关或其它FET。源极区和漏极区18a、18b设置在多个晶体管18之间。公共栅极50被示出为连接到多个晶体管18中的每一个。在实施例中，公共栅极50可以是例如多栅极。深沟槽隔离结构20可以设置在公共栅极50的下面和/或侧面上或其任何组合。例如，深沟槽隔离结构20”可以在公共栅极50a的下面，并且深沟槽隔离结构20”’可以在公共栅极50b的侧面上。还应当理解，图3中所示的多个布局可以设置有在多个晶体管18的上部和下部之中的共享的深沟槽隔离结构28。
与在此所述的结构相比，高电阻率Si晶片应用通过减少衬底载流子诱导的谐波来提供改善的线性度；然而，高电阻率耗尽区可以在衬底中延伸5μm至100μm深或更深，导致相邻器件之间的泄漏和谐波失真。三阱从合并中阻止耗尽区，即相邻p阱的耗尽区，并防止DC衬底电流与p阱区和FET互相作用。然而，合并的三阱耗尽区由于阱区之间的耦合而导致谐波失真，增加寄生电容，这劣化了诸如关断电容(Coff)的NFET开关电特性并增加了成本。三阱区还导致额外的增加非线性电容的电连接，非线性电容进一步增加谐波失真。现在解决了这些问题，并通过实施在此所述的结构和方法以更低的成本解决了这些问题。注意，虽然以开关示出了描述，但是形成在高电阻率衬底上的任何有源或无源器件可以使用该制造工艺并且得到在此所述的结构，以改善器件隔离度和线性度。
如上所述的方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶片形式(也就是说，作为具有多个未封装芯片的单个晶片)作为裸芯片或以封装形式分发。在后一种情况下，芯片安装在单个芯片封装(诸如塑料载体，具有固定到母板或其它更高级别载体的引线)或多芯片封装(诸如具有单面或双面表面互连或掩埋互连的陶瓷载体)中。在任何情况下，芯片然后与其它芯片、分立电路元件和/或其它信号处理设备集成，作为(a)中间产品(诸如母板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
为了说明的目的，已经呈现了本公开的各种实施例的描述，但并不旨在穷举或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。选择在此所使用的术语是为了最好地解释实施例的原理、对市场中发现的技术的实际应用或技术改进，或使得本领域普通技术人员能够理解在此所公开的实施例。

Claims (19)

1.一种半导体结构，包括：具有在至少一个栅极叠层的源极区和漏极区之下且具有含有空气隙或空隙并衬有掺杂材料的深沟槽隔离结构限定的全耗尽区的体衬底，所述掺杂材料包括掺杂多晶硅材料。
2.根据权利要求1所述的半导体结构，其中，所述体衬底是具有大于或等于10Kohm-cm的高电阻率体衬底。
3.根据权利要求1所述的半导体结构，其中，所述全耗尽区接触所述源极区和所述漏极区的底部。
4.根据权利要求1所述的半导体结构，其中，栅极叠层之间的间隔小于2μm。
5.根据权利要求1所述的半导体结构，其中，所述掺杂材料是所述深沟槽隔离结构的侧壁上的n型掺杂的多晶硅材料或p型掺杂的多晶硅材料。
6.根据权利要求5所述的半导体结构，还包括在所述掺杂材料之下并在所述深沟槽隔离结构的侧壁上的未掺杂材料。
7.根据权利要求1所述的半导体结构，其中，所述深沟槽隔离结构具有大于在所述源极区和所述漏极区之下的所述体衬底中形成的阱区的深度。
8.根据权利要求7所述的半导体结构，还包括在所述深沟槽隔离结构之间并且在所述阱区之下的合并耗尽区。
9.根据权利要求8所述的半导体结构，其中，所述深沟槽隔离结构隔离形成在所述阱区上的射频开关。
10.根据权利要求1所述的半导体结构，其中，所述空气隙或空隙是球形的，并且所述深沟槽隔离结构衬有在所述掺杂材料之下的氧化物材料。
11.根据权利要求1所述的结构，还包括向所述掺杂材料提供电偏置的接触。
12.一种半导体结构，包括：
具有至少一个阱区的高电阻率体衬底；
在所述至少一个阱区之上形成的多个射频器件；
在所述至少一个阱区之下延伸的多个深沟槽隔离结构，所述多个深沟槽隔离结构衬有掺杂材料并具有空气隙或空隙，其中所述掺杂材料包括掺杂多晶硅材料；
由所述多个深沟槽隔离结构限定的全耗尽区；以及
在所述全耗尽区之下的合并耗尽区。
13.根据权利要求12所述的半导体结构，其中，所述多个深沟槽隔离结构隔离形成在所述至少一个阱区上的射频开关。
14.根据权利要求12所述的半导体结构，其中，所述空气隙或空隙是球形的，并且所述深沟槽隔离结构衬有在所述掺杂材料之下的氧化物材料。
15.根据权利要求12所述的半导体结构，其中，所述掺杂材料是具有所述掺杂多晶硅材料和未掺杂多晶硅材料的双层或多层。
16.根据权利要求12所述的结构，还包括向所述掺杂材料提供电偏置的接触。
17.根据权利要求12所述的半导体结构，其中，所述深沟槽隔离结构被形成至所述体衬底的背面研磨界面，以将相邻的阱区和所述射频器件与DC衬底电流完全隔离。
18.一种用于制造半导体结构的方法，包括：
在高电阻率体衬底中形成至少一个阱；
在所述高电阻率体衬底上并在所述至少一个阱之上形成多个有源器件；
在所述至少一个阱之下的所述高电阻率体衬底中形成深沟槽结构；以及
用夹断以形成空气隙或空隙的掺杂材料加衬所述深沟槽结构，其中所述深沟槽结构在所述高电阻率体衬底中限定全耗尽区，其中所述掺杂材料包括掺杂多晶硅材料。
19.根据权利要求18所述的方法，其中，所述空气隙或空隙包括从所述深沟槽结构延伸的球形空气隙或空隙。
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