WO2024092417A1 - 驱动电路、显示面板、显示基板和显示装置 - Google Patents

驱动电路、显示面板、显示基板和显示装置 Download PDF

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Publication number
WO2024092417A1
WO2024092417A1 PCT/CN2022/128669 CN2022128669W WO2024092417A1 WO 2024092417 A1 WO2024092417 A1 WO 2024092417A1 CN 2022128669 W CN2022128669 W CN 2022128669W WO 2024092417 A1 WO2024092417 A1 WO 2024092417A1
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Prior art keywords
node
electrically connected
low voltage
transistor
input terminal
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PCT/CN2022/128669
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English (en)
French (fr)
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WO2024092417A9 (zh
Inventor
黄耀
刘庭良
胡明
董向丹
王本莲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/128669 priority Critical patent/WO2024092417A1/zh
Publication of WO2024092417A1 publication Critical patent/WO2024092417A1/zh
Publication of WO2024092417A9 publication Critical patent/WO2024092417A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a display panel, a display substrate and a display device.
  • AMOLED Active-matrix organic light-emitting diode
  • an AMOLED display device generally includes: an AMOLED display panel and a gate drive circuit.
  • the AMOLED display panel includes multiple rows of pixels.
  • the gate drive circuit includes multiple cascaded shift register units. Each shift register unit is coupled to a row of pixels and is used to transmit a gate drive signal to the row of pixels to drive the row of pixels to emit light.
  • the multiple cascaded shift register units can realize a row-by-row scanning drive of multiple rows of pixels, so that the AMOLED display panel displays an image.
  • the related shift register units use the same voltage input terminal, and the potential of each node cannot be flexibly set.
  • an embodiment of the present disclosure provides a driving circuit, including a first node control circuit, a second node control circuit, and a first output circuit;
  • the second node control circuit is electrically connected to the first low voltage input terminal, the first node and the second node respectively, and is used to control the connection between the first node and the second node under the control of the low voltage signal provided by the first low voltage input terminal;
  • the first node control circuit is electrically connected to the second low voltage input terminal, the first clock signal line and the first node respectively, and is used to control the first node to be electrically connected to the second low voltage input terminal under the control of the first clock signal provided by the first clock signal line;
  • the first output circuit is electrically connected to the pull-down node, the drive signal output terminal and the third low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the third low voltage input terminal under the control of the potential of the pull-down node;
  • At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second output circuit and a fourth node control circuit;
  • the second output circuit is electrically connected to the pull-up node, the first high voltage input terminal and the drive signal output terminal respectively, and is used to control the connection between the first high voltage input terminal and the drive signal output terminal under the control of the potential of the pull-up node;
  • the fourth node control circuit is electrically connected to the first node, the fourth node and the fourth high voltage input terminal respectively, and is used to control the fourth node to be connected to the fourth high voltage input terminal under the control of the potential of the first node;
  • the first high voltage input terminal is different from the fourth high voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a third node reset circuit
  • the third node reset circuit is electrically connected to the reset line, the third high voltage input terminal and the third node respectively, and is used to control the connection between the third high voltage input terminal and the third node under the control of the reset signal provided by the reset line;
  • the third high voltage input terminal is different from at least one of the first high voltage input terminal and the fourth high voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a pull-up node control circuit
  • the pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node;
  • the second high voltage input terminal is different from at least one of the first high voltage input terminal and the fourth high voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a pull-up node control circuit
  • the pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node;
  • the second high voltage input terminal is different from the third high voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a pull-down node control circuit
  • the pull-down node control circuit is electrically connected to the fourth low voltage input terminal, the third node and the pull-down node respectively, and is used to control the connection between the third node and the pull-down node under the control of the low voltage signal provided by the fourth low voltage input terminal;
  • the fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a fifth node control circuit and a pull-up node control circuit;
  • the fifth node control circuit is electrically connected to the second node, the fifth node and the second clock signal line respectively, and is used to control the connection between the second clock signal line and the fifth node under the control of the potential of the second node, and control the potential of the fifth node according to the potential of the second node;
  • the pull-up node control circuit is also electrically connected to the fifth node, the second clock signal line and the pull-up node, respectively, and is used to control the connection between the fifth node and the pull-up node under the control of the second clock signal provided by the second clock signal line, and to maintain the potential of the pull-up node.
  • the driving circuit further includes a third node control circuit
  • the third node control circuit is electrically connected to the starting voltage terminal, the first clock signal line and the third node respectively, and is used to control the connection between the starting voltage terminal and the third node under the control of the first clock signal provided by the first clock signal line;
  • the first node control circuit is also electrically connected to the third node, the first node and the first clock signal line respectively, and is used to control the connection between the first node and the first clock signal line under the control of the potential of the third node;
  • the fourth node control circuit is also electrically connected to the pull-down node and the second clock signal line respectively, and is used to control the connection between the fourth node and the second clock signal line under the control of the potential of the pull-down node, and control the potential of the fourth node according to the potential of the pull-down node.
  • the first node control circuit includes a first transistor, and the second node control circuit includes a second transistor;
  • the control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second low voltage input terminal, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first low voltage input terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;
  • the first output circuit includes an output reset transistor, a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low voltage input terminal.
  • the second output circuit includes an output transistor, and the pull-up node control circuit includes a third transistor and a first capacitor;
  • the control electrode of the output transistor is electrically connected to the pull-up node, the first electrode of the output transistor is electrically connected to the first high voltage input terminal, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;
  • the control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-up node;
  • the first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the first high voltage input terminal.
  • the third node reset circuit includes a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the reset line, the first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the third node.
  • the fourth node control circuit includes a fifth transistor
  • the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node.
  • the pull-down node control circuit includes a sixth transistor
  • the control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the pull-down node.
  • the fifth node control circuit includes a seventh transistor and a second capacitor; the pull-up node control circuit also includes an eighth transistor;
  • the control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the second clock signal line, and the second electrode of the seventh transistor is electrically connected to the fifth node;
  • the first electrode plate of the second capacitor is electrically connected to the second node, and the second electrode plate of the second capacitor is electrically connected to the fifth node;
  • the control electrode of the eighth transistor is electrically connected to the second clock signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the pull-up node.
  • the first node control circuit further includes a ninth transistor
  • the control electrode of the ninth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the first clock signal line, and the second electrode of the ninth transistor is electrically connected to the first node;
  • the fourth node control circuit also includes a tenth transistor and a third capacitor
  • the control electrode of the tenth transistor is electrically connected to the pull-down node, the first electrode of the tenth transistor is electrically connected to the second clock signal line, and the second electrode of the tenth transistor is electrically connected to the fourth node;
  • a first plate of a third capacitor is electrically connected to the pull-down node, and a second plate of the third capacitor is electrically connected to the fourth node;
  • the third node control circuit includes an eleventh transistor
  • the control electrode of the eleventh transistor is electrically connected to the first clock signal line, the first electrode of the eleventh transistor is electrically connected to the starting voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the third node.
  • an embodiment of the present disclosure provides a driving circuit, comprising a first transistor, a second transistor, an output reset transistor, and a sixth transistor;
  • the control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second low voltage input terminal, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first low voltage input terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;
  • the first output circuit comprises an output reset transistor, a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low voltage input terminal;
  • the control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the pull-down node;
  • the first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal and the low voltage input terminal are not completely the same.
  • an embodiment of the present disclosure provides a driving circuit, including an output transistor, a third transistor, a fourth transistor, and a fifth transistor;
  • the control electrode of the output transistor is electrically connected to the pull-up node, the first electrode of the output transistor is electrically connected to the first high voltage input terminal, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;
  • the control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-up node;
  • the control electrode of the fourth transistor is electrically connected to the reset line, the first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the third node;
  • the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node;
  • the first high voltage input terminal, the second high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are not completely the same.
  • an embodiment of the present disclosure provides a display panel, comprising the above-mentioned driving circuit; the display panel further comprises a display driving chip;
  • the first low voltage input terminal is electrically connected to the first low voltage line
  • the second low voltage input terminal is electrically connected to the second low voltage line
  • the third low voltage input terminal is electrically connected to the third low voltage line
  • the first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line, provide a second low voltage signal for the second low voltage line, and provide a third low voltage signal for the third low voltage line; or
  • the first low voltage input terminal is electrically connected to the first low voltage line
  • the second low voltage input terminal and the third low voltage input terminal are both electrically connected to the second low voltage line
  • the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line;
  • the first low voltage input terminal and the second low voltage input terminal are both electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line; or
  • the first low voltage input terminal and the third low voltage input terminal are both electrically connected to the first low voltage line
  • the second low voltage input terminal is electrically connected to the second low voltage line
  • the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip respectively
  • the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line.
  • an embodiment of the present disclosure provides a display panel, comprising the above-mentioned driving circuit; the display panel further comprises a display driving chip;
  • the first high voltage input terminal is electrically connected to the first high voltage line
  • the second high voltage input terminal is electrically connected to the second high voltage line
  • the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip
  • the display driver chip is used to provide a first high voltage signal for the first high voltage line
  • the display driver chip is used to provide a second high voltage signal for the second high voltage line.
  • an embodiment of the present disclosure provides a display substrate, comprising a base substrate and a driving circuit disposed on the base substrate.
  • the driving circuit includes a first low voltage line, a second low voltage line, a first high voltage line, a second high voltage line, a first node control circuit, a second node control circuit, a first output circuit, a second output circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit and a third node control circuit;
  • the second low voltage line is arranged at a side of the driving circuit away from the display area, and the first low voltage line is arranged at a side of the driving circuit close to the display area;
  • the first high voltage line and the second high voltage line are arranged between a first circuit part included in the driving circuit and a second circuit part included in the driving circuit;
  • the first circuit portion includes a first node control circuit, a second node control circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit and a third node control circuit, and the second circuit portion includes a first output circuit and a second output circuit;
  • the first circuit portion is disposed between the second low voltage line and the second high voltage line
  • the second circuit portion is disposed between the first high voltage line and the first low voltage line.
  • the driving circuit further includes a third node reset circuit, and the first circuit portion includes the third node reset circuit.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned driving circuit.
  • FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG7 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG8A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG8B is a working timing diagram of at least one embodiment of the driving circuit shown in FIG8A of the present disclosure.
  • FIG9 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG10 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG11 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG12 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG14 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG15 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 19A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG19B is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG20 is a circuit diagram of a related pixel circuit
  • FIG21 is a layout diagram of at least one embodiment of the driving circuit shown in FIG15 of the present disclosure.
  • FIG22 is a layout diagram of the active layer in FIG21;
  • FIG23 is a layout diagram of the first gate metal layer in FIG21;
  • FIG24 is a layout diagram of the second gate metal layer in FIG21;
  • FIG25 is a layout diagram of the source/drain metal layer in FIG21 ;
  • FIG26 is a layout diagram of at least one embodiment of the driving circuit shown in FIG19 of the present disclosure.
  • FIG27 is a layout diagram of the active layer in FIG26.
  • FIG28 is a layout diagram of the first gate metal layer in FIG26 ;
  • FIG29 is a layout diagram of the second gate metal layer in FIG26.
  • FIG30 is a layout diagram of the source/drain metal layer in FIG26 ;
  • FIG31 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG32 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG33 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG34 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 35 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the driving circuit described in the embodiment of the present disclosure includes a first node control circuit 11 , a second node control circuit 12 and a first output circuit 13 ;
  • the second node control circuit 12 is electrically connected to the first low voltage input terminal VL1, the first node N1 and the second node N2 respectively, and is used to control the connection between the first node N1 and the second node N2 under the control of the low voltage signal provided by the first low voltage input terminal VL1;
  • the first node control circuit 11 is electrically connected to the second low voltage input terminal VL2, the first clock signal line CK and the first node N1 respectively, and is used to control the first node N1 to be electrically connected to the second low voltage input terminal VL2 under the control of the first clock signal provided by the first clock signal line CK;
  • the first output circuit 13 is electrically connected to the pull-down node PD, the drive signal output terminal O1 and the third low voltage input terminal VL3 respectively, and is used to control the connection between the drive signal output terminal O1 and the third low voltage input terminal VL3 under the control of the potential of the pull-down node PD;
  • At least two of the first low voltage input terminal VL1 , the second low voltage input terminal VL2 , and the third low voltage input terminal VL3 are different from each other.
  • the two low voltage input terminals being different may mean that the two low voltage input terminals respectively provide different low voltage signals.
  • the low voltage signal provided by the first low voltage input terminal VL1 may be different from the low voltage signal provided by the second low voltage input terminal VL2 .
  • the voltage value of the low voltage signal may be a negative voltage.
  • the absolute value of the low voltage signal provided by the second low voltage input terminal VL2 is greater than the absolute value of the low voltage signal provided by the first low voltage input terminal VL1, so that the potential of N1 and the potential of N2 are lower.
  • the first low voltage input terminal may provide a first low voltage signal
  • the second low voltage input terminal may provide a second low voltage signal
  • the first low voltage line VGL may provide a first low voltage signal
  • the second low voltage line VGL2 may provide a second low voltage signal
  • the first low voltage input terminal VL1 may provide a first low voltage signal
  • the second low voltage input terminal VL2 may provide a second low voltage signal
  • the third low voltage input terminal VL3 may provide a first low voltage signal
  • the first low voltage input terminal VL1 may provide a second low voltage signal
  • the second low voltage input terminal VL2 may provide a second low voltage signal
  • the third low voltage input terminal VL3 may provide a first low voltage signal
  • the first low voltage input terminal VL1 may provide a first low voltage signal
  • the second low voltage input terminal VL2 may provide a first low voltage signal
  • the third low voltage input terminal VL3 may provide a second low voltage signal
  • the first low voltage input terminal VL1 can provide a first low voltage signal
  • the second low voltage input terminal VL2 can provide a second low voltage signal
  • the third low voltage input terminal VL3 can provide a second low voltage signal
  • the driving circuit according to at least one embodiment of the present disclosure further includes a second output circuit 21 and a fourth node control circuit 41 ;
  • the second output circuit 21 is electrically connected to the pull-up node PU, the first high voltage input terminal VH1 and the drive signal output terminal O1 respectively, and is used to control the connection between the first high voltage input terminal VH1 and the drive signal output terminal O1 under the control of the potential of the pull-up node PU;
  • the fourth node control circuit 41 is electrically connected to the first node N1, the fourth node N4 and the fourth high voltage input terminal VH4, respectively, and is used to control the connection between the fourth node N4 and the fourth high voltage input terminal VH4 under the control of the potential of the first node N1; the first high voltage input terminal VH1 is different from the fourth high voltage input terminal VH4.
  • the two high voltage input terminals being different may mean that the high voltage signals respectively provided by the two high voltage input terminals are different.
  • the first high voltage input terminal VH1 may provide a first high voltage signal
  • the second high voltage input terminal VH2 may provide a second high voltage signal
  • a first high voltage line VGH may provide a first high voltage signal
  • a second high voltage line VGH2 may provide a second high voltage signal
  • the voltage value of the high voltage signal provided by the first high voltage input terminal can be set to be smaller than the voltage value of the high voltage signal provided by the second high voltage input terminal, so that when the transistor included in the pull-up node control circuit 22 is turned on, the transistor included in the second output circuit 21 can be better turned off;
  • the voltage value of the high voltage signal provided by the first high voltage input terminal can be set to be greater than the voltage value of the high voltage signal provided by the second high voltage input terminal, so that when the transistor included in the pull-up node control circuit 22 is turned on, the transistor included in the second output circuit 21 can be better turned off;
  • the driving circuit further includes a third node reset circuit
  • the third node reset circuit is electrically connected to the reset line, the third high voltage input terminal and the third node respectively, and is used to control the connection between the third high voltage input terminal and the third node under the control of the reset signal provided by the reset line;
  • the third high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.
  • the driving circuit may further include a third node reset circuit 31;
  • the third node reset circuit 31 is electrically connected to the reset line VEL, the third high voltage input terminal VH3 and the third node N3 respectively, and is used to control the connection between the third high voltage input terminal VH3 and the third node N3 under the control of the reset signal provided by the reset line VEL.
  • the third high voltage input terminal VH3 may be used to provide a second high voltage signal, or the third high voltage input terminal VH3 may be used to provide a first high voltage signal, but the present invention is not limited thereto.
  • the voltage value of the first low voltage signal may be greater than the voltage value of the second low voltage signal; or, the voltage value of the first low voltage signal may be less than the voltage value of the second low voltage signal;
  • the voltage value of the first high voltage signal may be greater than the voltage value of the second high voltage signal; or, the voltage value of the first high voltage signal may be less than the voltage value of the second high voltage signal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a pull-up node control circuit
  • the pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node;
  • the second high voltage input terminal is different from at least one of the first high voltage input terminal and the fourth high voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a pull-up node control circuit
  • the pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node;
  • the second high voltage input terminal is different from the third high voltage input terminal.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a pull-up node control circuit 22 ;
  • the pull-up node control circuit 22 is electrically connected to the third node N3, the second high voltage input terminal VH2 and the pull-up node PU respectively, and is used to control the connection between the second high voltage input terminal VH2 and the pull-up node PU under the control of the potential of the third node N3;
  • the second high voltage input terminal VH2 is different from at least one of the first high voltage input terminal VH1 , the fourth high voltage input terminal VH4 , and the third high voltage input terminal VH3 .
  • the fourth high voltage input terminal VH4 can provide a first high voltage signal or a second high voltage signal, but is not limited thereto.
  • the driving circuit further includes a pull-down node control circuit
  • the pull-down node control circuit is electrically connected to the fourth low voltage input terminal, the third node and the pull-down node respectively, and is used to control the connection between the third node and the pull-down node under the control of the fourth low voltage signal provided by the fourth low voltage input terminal;
  • the fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a pull-down node control circuit 51 ;
  • the pull-down node control circuit 51 is electrically connected to the fourth low voltage input terminal VL4, the third node N3 and the pull-down node PD respectively, and is used to control the connection between the third node N3 and the pull-down node PD under the control of the fourth low voltage signal provided by the fourth low voltage input terminal VL4;
  • the fourth low voltage input terminal VL4 is different from at least one of the first low voltage input terminal VL1 , the second low voltage input terminal VL2 , and the third low voltage input terminal VL3 .
  • the fourth low voltage input terminal VL4 can provide a first low voltage signal or a second low voltage signal, but is not limited thereto.
  • the driving circuit further includes a fifth node control circuit and a pull-up node control circuit;
  • the fifth node control circuit is electrically connected to the second node, the fifth node and the second clock signal line respectively, and is used to control the connection between the second clock signal line and the fifth node under the control of the potential of the second node, and control the potential of the fifth node according to the potential of the second node;
  • the pull-up node control circuit is also electrically connected to the fifth node, the second clock signal line and the pull-up node, respectively, and is used to control the connection between the fifth node and the pull-up node under the control of the second clock signal provided by the second clock signal line, and to maintain the potential of the pull-up node.
  • the driving circuit further includes a fifth node control circuit, the fifth node control circuit is used to control the potential of the fifth node, and the pull-up node control circuit is used to control the potential of the pull-up node.
  • the driving circuit further includes a third node control circuit
  • the third node control circuit is electrically connected to the starting voltage terminal, the first clock signal line and the third node respectively, and is used to control the connection between the starting voltage terminal and the third node under the control of the first clock signal provided by the first clock signal line;
  • the first node control circuit is also electrically connected to the third node, the first node and the first clock signal line respectively, and is used to control the connection between the first node and the first clock signal line under the control of the potential of the third node;
  • the fourth node control circuit is also electrically connected to the pull-down node and the second clock signal line respectively, and is used to control the connection between the fourth node and the second clock signal line under the control of the potential of the pull-down node, and control the potential of the fourth node according to the potential of the pull-down node.
  • the driving circuit further includes a third node control circuit, the third node control circuit controls the potential of the third node, the first node control circuit controls the potential of the first node, and the fourth node control circuit controls the potential of the fourth node.
  • the driving circuit further includes a fifth node control circuit 71 and a third node control circuit 72;
  • the fifth node control circuit 71 is electrically connected to the second node N2, the fifth node N5 and the second clock signal line CB respectively, and is used to control the connection between the second clock signal line CB and the fifth node N5 under the control of the potential of the second node N2, and control the potential of the fifth node N5 according to the potential of the second node N2;
  • the pull-up node control circuit 22 is also electrically connected to the fifth node N5, the second clock signal line CB and the pull-up node PU respectively, and is used to control the connection between the fifth node N5 and the pull-up node PU under the control of the second clock signal provided by the second clock signal line CB, and to maintain the potential of the pull-up node PU;
  • the third node control circuit 72 is electrically connected to the start voltage terminal STV, the first clock signal line CK and the third node N3 respectively, and is used to control the connection between the start voltage terminal STV and the third node N3 under the control of the first clock signal provided by the first clock signal line CK;
  • the first node control circuit 11 is also electrically connected to the third node N3, the first node N1 and the first clock signal line CK respectively, and is used to control the connection between the first node N1 and the first clock signal line CK under the control of the potential of the third node N3;
  • the fourth node control circuit 41 is also electrically connected to the pull-down node PD and the second clock signal line CB, respectively, and is used to control the connection between the fourth node N4 and the second clock signal line CB under the control of the potential of the pull-down node PD, and control the potential of the fourth node N4 according to the potential of the pull-down node PD.
  • the first node control circuit includes a first transistor, and the second node control circuit includes a second transistor;
  • the control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second low voltage input terminal, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first low voltage input terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;
  • the first output circuit includes an output reset transistor
  • the control electrode of the output reset transistor is electrically connected to the pull-down node, the first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and the second electrode of the output reset transistor is electrically connected to the third low voltage input terminal.
  • the second output circuit includes an output transistor, and the pull-up node control circuit includes a third transistor and a first capacitor;
  • the control electrode of the output transistor is electrically connected to the pull-up node, the first electrode of the output transistor is electrically connected to the first high voltage input terminal, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;
  • the control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-up node;
  • the first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the first high voltage input terminal.
  • the third node reset circuit includes a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the reset line, the first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the third node.
  • the fourth node control circuit includes a fifth transistor
  • the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node.
  • the pull-down node control circuit includes a sixth transistor
  • the control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the pull-down node.
  • the fifth node control circuit includes a seventh transistor and a second capacitor; the pull-up node control circuit also includes an eighth transistor;
  • the control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the second clock signal line, and the second electrode of the seventh transistor is electrically connected to the fifth node;
  • the first electrode plate of the second capacitor is electrically connected to the second node, and the second electrode plate of the second capacitor is electrically connected to the fifth node;
  • the control electrode of the eighth transistor is electrically connected to the second clock signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the pull-up node.
  • the first node control circuit further includes a ninth transistor
  • the control electrode of the ninth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the first clock signal line, and the second electrode of the ninth transistor is electrically connected to the first node;
  • the fourth node control circuit also includes a tenth transistor and a third capacitor
  • the control electrode of the tenth transistor is electrically connected to the pull-down node, the first electrode of the tenth transistor is electrically connected to the second clock signal line, and the second electrode of the tenth transistor is electrically connected to the fourth node;
  • a first plate of a third capacitor is electrically connected to the pull-down node, and a second plate of the third capacitor is electrically connected to the fourth node;
  • the third node control circuit includes an eleventh transistor
  • the control electrode of the eleventh transistor is electrically connected to the first clock signal line, the first electrode of the eleventh transistor is electrically connected to the starting voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the third node.
  • the first node control circuit includes a first transistor T1
  • the second node control circuit includes a second transistor T2 ;
  • the gate of the first transistor T1 is electrically connected to the first clock signal line CK, the source of the first transistor T1 is electrically connected to the second low voltage input terminal VL2, and the drain of the first transistor T1 is electrically connected to the first node N1;
  • the gate of the second transistor T2 is electrically connected to the first low voltage input terminal VL1, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the second node N2;
  • the first output circuit comprises an output reset transistor Tf;
  • the gate of the output reset transistor Tf is electrically connected to the pull-down node PD, the source of the output reset transistor Tf is electrically connected to the drive signal output terminal O1, and the drain of the output reset transistor Tf is electrically connected to the third low voltage input terminal VL3;
  • the second output circuit includes an output transistor To, and the pull-up node control circuit includes a third transistor T3 and a first capacitor C1;
  • the gate of the output transistor To is electrically connected to the pull-up node PU, the source of the output transistor To is electrically connected to the first high voltage input terminal VH1, and the drain of the output transistor To is electrically connected to the drive signal output terminal O1;
  • the gate of the third transistor T3 is electrically connected to the third node N3, the source of the third transistor T3 is electrically connected to the second high voltage input terminal VH2, and the drain of the third transistor T3 is electrically connected to the pull-up node PU;
  • the first plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the first high voltage input terminal VH1;
  • the third node reset circuit includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the reset line VEL, the source of the fourth transistor T4 is electrically connected to the third high voltage input terminal VH3, and the drain of the fourth transistor T4 is electrically connected to the third node N3;
  • the fourth node control circuit includes a fifth transistor T5;
  • the gate of the fifth transistor T5 is electrically connected to the first node N1, the source of the fifth transistor T5 is electrically connected to the fourth high voltage input terminal VH4, and the drain of the fifth transistor T5 is electrically connected to the fourth node N4;
  • the pull-down node control circuit includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the fourth low voltage input terminal VL4, the source of the sixth transistor T6 is electrically connected to the third node N3, and the drain of the sixth transistor T6 is electrically connected to the pull-down node PD;
  • the fifth node control circuit includes a seventh transistor T7 and a second capacitor C2; the pull-up node control circuit also includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the second node N2, the source of the seventh transistor T7 is electrically connected to the second clock signal line CB, and the drain of the seventh transistor T7 is electrically connected to the fifth node N5;
  • the first electrode plate of the second capacitor C2 is electrically connected to the second node N2, and the second electrode plate of the second capacitor C2 is electrically connected to the fifth node N5;
  • the gate of the eighth transistor T8 is electrically connected to the second clock signal line CB, the source of the eighth transistor T8 is electrically connected to the fifth node N5, and the drain of the eighth transistor T8 is electrically connected to the pull-up node PU;
  • the first node control circuit also includes a ninth transistor T9;
  • the gate of the ninth transistor T9 is electrically connected to the third node N3, the source of the ninth transistor T9 is electrically connected to the first clock signal line CK, and the drain of the ninth transistor T9 is electrically connected to the first node N1;
  • the fourth node control circuit further includes a tenth transistor T10 and a third capacitor C3;
  • the gate of the tenth transistor T10 is electrically connected to the pull-down node PD, the source of the tenth transistor T10 is electrically connected to the second clock signal line CB, and the drain of the tenth transistor T10 is electrically connected to the fourth node N4;
  • a first plate of the third capacitor C3 is electrically connected to the pull-down node PD, and a second plate of the third capacitor C3 is electrically connected to the fourth node N4;
  • the third node control circuit includes an eleventh transistor T11;
  • a gate of the eleventh transistor T11 is electrically connected to the first clock signal line CK, a source of the eleventh transistor T11 is electrically connected to the starting voltage terminal STV, and a drain of the eleventh transistor T11 is electrically connected to the third node N3.
  • all transistors are p-type transistors, but the present invention is not limited thereto. In actual operation, the transistors in FIG7 may also be n-type transistors.
  • the first low voltage input terminal VL1 may provide a first low voltage signal
  • the second low voltage input terminal VL2 may provide a second low voltage signal
  • the third low voltage input terminal VL3 may provide a first low voltage signal
  • the fourth low voltage input terminal VL4 may provide a first low voltage signal
  • the first low voltage input terminal VL1 can provide a second low voltage signal
  • the second low voltage input terminal VL2 can provide a second low voltage signal
  • the third low voltage input terminal VL3 can provide a first low voltage signal
  • the fourth low voltage input terminal VL4 can provide a second low voltage signal
  • the first low voltage input terminal VL1 can provide a first low voltage signal
  • the second low voltage input terminal VL2 can provide a first low voltage signal
  • the third low voltage input terminal VL3 can provide a first low voltage signal
  • the fourth low voltage input terminal VL4 can provide a second low voltage signal
  • the first low voltage input terminal VL1 can provide a second low voltage signal
  • the second low voltage input terminal VL2 can provide a first low voltage signal
  • the third low voltage input terminal VL3 can provide a first low voltage signal
  • the fourth low voltage input terminal VL4 can provide a first low voltage signal
  • the first low voltage input terminal VL1 can provide a second low voltage signal
  • the second low voltage input terminal VL2 can provide a first low voltage signal
  • the third low voltage input terminal VL3 can provide a first low voltage signal
  • the fourth low voltage input terminal VL4 can provide a second low voltage signal
  • the first low voltage input terminal VL1 can provide a second low voltage signal
  • the second low voltage input terminal VL2 can provide a second low voltage signal
  • the third low voltage input terminal VL3 can provide a second low voltage signal
  • the fourth low voltage input terminal VL4 can provide a first low voltage signal
  • the first low voltage input terminal VL1 can provide a first low voltage signal
  • the second low voltage input terminal VL2 can provide a second low voltage signal
  • the third low voltage input terminal VL3 can provide a second low voltage signal
  • the fourth low voltage input terminal VL4 can provide a first low voltage signal
  • the first low voltage input terminal VL1 can provide a first low voltage signal
  • the second low voltage input terminal VL2 can provide a first low voltage signal
  • the third low voltage input terminal VL3 can provide a second low voltage signal
  • the fourth low voltage input terminal VL4 can provide a first low voltage signal
  • the first high voltage input terminal VH1 can provide a first high voltage signal
  • the second high voltage input terminal VH2 can provide a second high voltage signal
  • the third high voltage input terminal VH3 can provide a second high voltage signal
  • the fourth high voltage input terminal VH4 can provide a first high voltage signal
  • the first high voltage input terminal VH1 can provide a first high voltage signal
  • the second high voltage input terminal VH2 can provide a second high voltage signal
  • the third high voltage input terminal VH3 can provide a first high voltage signal
  • the fourth high voltage input terminal VH4 can provide a first high voltage signal
  • the first high voltage input terminal VH1 can provide a first high voltage signal
  • the second high voltage input terminal VH2 can provide a second high voltage signal
  • the third high voltage input terminal VH3 can provide a first high voltage signal
  • the fourth high voltage input terminal VH4 can provide a second high voltage signal
  • the first high voltage input terminal VH1 can provide a second high voltage signal
  • the second high voltage input terminal VH2 can provide a first high voltage signal
  • the third high voltage input terminal VH3 can provide a second high voltage signal
  • the fourth high voltage input terminal VH4 can provide a first high voltage signal
  • the first high voltage input terminal VH1 can provide a second high voltage signal
  • the second high voltage input terminal VH2 can provide a first high voltage signal
  • the third high voltage input terminal VH3 can provide a first high voltage signal
  • the fourth high voltage input terminal VH4 can provide a first high voltage signal
  • the first high voltage input terminal VH1 can provide a second high voltage signal
  • the second high voltage input terminal VH2 can provide a first high voltage signal
  • the third high voltage input terminal VH3 can provide a first high voltage signal
  • the fourth high voltage input terminal VH4 can provide a second high voltage signal
  • the first low voltage input terminal VL1 provides a first low voltage signal
  • the second low voltage input terminal VL2 provides a second low voltage signal
  • the third low voltage input terminal VL3 provides a first low voltage signal
  • the fourth low voltage input terminal VL4 provides a first low voltage signal
  • the first low voltage signal is provided by the first low voltage line VGL
  • the second low voltage signal is provided by the second low voltage line VGL2;
  • the first high voltage input terminal VH1 provides a first high voltage signal
  • the second high voltage input terminal VH2 provides a second high voltage signal
  • the third high voltage input terminal VH3 provides a second high voltage signal
  • the fourth high voltage input terminal VH4 provides a first high voltage signal
  • the first high voltage signal is provided by the first high voltage line VGH
  • the second high voltage signal is provided by the second high voltage line VGH2.
  • the voltage value of the second low voltage signal provided by VGL2 may be lower than the voltage value of the first low voltage signal provided by VGL.
  • the voltage value of the second low voltage signal provided by VGL2 may be -6.5V. Since there is a threshold voltage loss when the p-type transistor transmits a low level, the voltage value of may be set to a voltage value lower than that of, so that when T1 and T2 are turned on, the potentials of N1 and N2 may be lower, so that the pull-up node PU is turned on faster and the Delay of the driving signal output by O1 is smaller.
  • a difference between a voltage value of the second low voltage signal and a voltage value of the first low voltage signal may be slightly greater than a threshold voltage of the p-type transistor, or may be equal to the threshold voltage.
  • At least one embodiment of the driving circuit shown in FIG. 8A of the present disclosure employs two high voltage input terminals and two low voltage input terminals;
  • the voltage value of a high voltage signal provided by a high voltage input terminal and the absolute value of the voltage value of a low voltage signal provided by a low voltage input terminal may be appropriately reduced to reduce power consumption;
  • the voltage value of the first high voltage signal and the voltage value of the first low voltage signal can be controlled to remain unchanged, but the voltage value of the second high voltage signal is reduced from 7V to 6V, and the voltage value of the second low voltage signal is adjusted from -7V to -6V to reduce power consumption.
  • At least one embodiment of the driving circuit shown in FIG. 8A of the present disclosure can adjust the voltage value of the second high voltage signal from 7V to 10V, and adjust the voltage value of the second low voltage signal from -7V to -10V, so as to enhance the switching capability of To and Tf.
  • the first low voltage input terminal VL1 provides a second low voltage signal
  • the second low voltage input terminal VL2 provides a second low voltage signal
  • the third low voltage input terminal VL3 provides a first low voltage signal
  • the fourth low voltage input terminal VL4 provides a second low voltage signal
  • the first low voltage signal is provided by the first low voltage line VGL
  • the second low voltage signal is provided by the second low voltage line VGL2;
  • the first high voltage input terminal VH1 provides a first high voltage signal
  • the second high voltage input terminal VH2 provides a second high voltage signal
  • the third high voltage input terminal VH3 provides a second high voltage signal
  • the fourth high voltage input terminal VH4 provides a first high voltage signal
  • the first high voltage signal is provided by the first high voltage line VGH
  • the second high voltage signal is provided by the second high voltage line VGH2.
  • the voltage value of VGH2 may be greater than the voltage value of VGH1 to compensate for leakage effects caused by threshold voltage drift, but the present invention is not limited thereto.
  • the gates of T2 and T6 are both electrically connected to the second low voltage line VGL2 providing the second low voltage signal, which facilitates layout and improves space utilization.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 12 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 8A of the present disclosure is that the source of To is electrically connected to the second high voltage line VGH2, and the source of T3 is electrically connected to the first high voltage line VGH.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 12 of the present disclosure is that the source of T4 is electrically connected to the first high voltage line VGH.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is that the source of T5 is electrically connected to the second high voltage line VGH2 .
  • the difference between at least one embodiment of the driving circuit shown in FIG. 15 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure is that the source of T4 is electrically connected to the second high voltage line VGH2 .
  • the difference between at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 12 of the present disclosure is that the gate of T2 and the gate of T6 are both electrically connected to the second low voltage line VGL2.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 17 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure is that the gate of T2 is electrically connected to the first low voltage line VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 18 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure is that the gate of T6 is electrically connected to the first low voltage line VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 19A of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 15 of the present disclosure is that T4 is not included.
  • the driving circuit described in at least one embodiment of the present disclosure includes a second output circuit and a pull-up node control circuit
  • the second output circuit is electrically connected to the pull-up node, the first high voltage input terminal and the drive signal output terminal respectively, and is used to control the connection between the first high voltage input terminal and the drive signal output terminal under the control of the potential of the pull-up node;
  • the pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node;
  • the first high voltage input terminal is different from the second high voltage input terminal.
  • the driving circuit further includes a third node reset circuit
  • the third node reset circuit is electrically connected to the reset line, the third high voltage input terminal and the third node respectively, and is used to control the connection between the third high voltage input terminal and the third node under the control of the reset signal provided by the reset line;
  • the third high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.
  • the driving circuit further includes a fourth node control circuit
  • the fourth node control circuit is electrically connected to the first node, the fourth node and the fourth high voltage input terminal respectively, and is used to control the fourth node to be connected to the fourth high voltage input terminal under the control of the potential of the first node;
  • the fourth high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.
  • the driving circuit further includes a fourth node control circuit
  • the fourth node control circuit is electrically connected to the first node, the fourth node and the fourth high voltage input terminal respectively, and is used to control the fourth node to be connected to the fourth high voltage input terminal under the control of the potential of the first node;
  • the fourth high voltage input terminal is different from the third high voltage input terminal.
  • the embodiment of the present disclosure further provides a display panel, comprising the above-mentioned driving circuit; the display panel also comprises a display driving chip;
  • the first high voltage input terminal is electrically connected to the first high voltage line
  • the second high voltage input terminal is electrically connected to the second high voltage line
  • the first high voltage line and the second high voltage line are electrically connected to different pins of the display driver chip respectively
  • the display driver chip is used to provide a first high voltage signal for the first high voltage line
  • the display driver chip is used to provide a second high voltage signal for the second high voltage line.
  • the first high voltage input terminal is electrically connected to the first high voltage line
  • the second high voltage input terminal is electrically connected to the second high voltage line
  • the first high voltage line is electrically connected to the first pin of the display driver chip
  • the second high voltage line is electrically connected to the second pin of the display driver chip.
  • the display driver chip provides a first high voltage signal to the first high voltage line through the first pin
  • the display driver chip provides a second high voltage signal to the second high voltage line through the second pin.
  • the display panel includes a display driver chip 320 ;
  • the first high voltage input terminal VH1 is electrically connected to the first high voltage line LH1
  • the second high voltage input terminal VH2 is electrically connected to the second high voltage line LH2;
  • the first high voltage line LH1 is electrically connected to the first pin P1 of the display driver chip 320, and the second high voltage line LH2 is electrically connected to the second pin P2 of the display driver chip 320;
  • the display driver chip 320 is used to provide a first high voltage signal for the first high voltage line LH1 , and the display driver chip 320 is used to provide a second high voltage signal for the second high voltage line LH2 .
  • the relevant pixel circuit includes a first display control transistor M1, a second display control transistor M2, a third display control transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, a storage capacitor C0 and an organic light emitting diode E1;
  • the line labeled EM is the light-emitting control line
  • the line labeled R1 is the first reset control line
  • the line labeled R2 is the second reset control line
  • the line labeled NG is the first scanning line
  • the line labeled PG is the second scanning line
  • the line labeled Vi1 is the first initial voltage
  • the line labeled Vi2 is the second initial voltage
  • the line labeled Vi3 is the third initial voltage
  • the line labeled VDD is the high level end
  • the line labeled VSS is the low level end.
  • the driving circuit described in at least one embodiment of the present disclosure can be used to provide a first scanning signal for the first scanning line NG, a light emitting control signal for the light emitting control line EM, a first reset control signal for the first reset control line R1, and a second reset control signal for the second reset control line R2.
  • the driving circuit includes a first transistor, a second transistor, an output reset transistor and a sixth transistor;
  • the control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second low voltage input terminal, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first low voltage input terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;
  • the first output circuit comprises an output reset transistor, a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low voltage input terminal;
  • the control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the pull-down node;
  • the first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal and the fourth low voltage input terminal are not completely the same.
  • the first low voltage input terminal VL1, the second low voltage input terminal VL2, the third low voltage input terminal VL3 and the fourth low voltage input terminal VL4 are not completely the same, as follows:
  • VL1 and VL2 are not the same; or,
  • VL1 and VL3 are not the same; or,
  • VL1 and VL4 are not the same; or,
  • VL2 is not the same as VL3; or,
  • VL2 is not the same as VL4; or,
  • VL3 and VL4 are not the same; or,
  • VL1, VL2 and VL3 are different from each other; or,
  • VL1, VL2 and VL4 are different from each other; or,
  • VL1, VL3 and VL4 are different from each other; or,
  • VL2, VL3 and VL4 are different from each other; or,
  • VL1, VL2, VL3 and VL4 are different from each other.
  • the driving circuit includes an output transistor, a third transistor, a fourth transistor and a fifth transistor;
  • the control electrode of the output transistor is electrically connected to the pull-up node, the first electrode of the output transistor is electrically connected to the first high voltage input terminal, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;
  • the control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-up node;
  • the control electrode of the fourth transistor is electrically connected to the reset line, the first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the third node;
  • the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node;
  • the first high voltage input terminal, the second high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are not completely the same.
  • the first high voltage input terminal VH1, the second high voltage input terminal VH2, the third high voltage input terminal VH3 and the fourth high voltage input terminal VH4 are not completely the same, specifically as follows:
  • VH1 and VH2 are not identical; or,
  • VH1 and VH3 are not identical; or,
  • VH1 and VH4 are not identical; or,
  • VH2 and VH3 are not identical; or,
  • VH2 and VH4 are not identical; or,
  • VH3 and VH4 are not identical; or,
  • VH1, VH2 and VH3 are different from each other; or,
  • VH1, VH2 and VH4 are different from each other; or,
  • VH1, VH3 and VH4 are different from each other; or,
  • VH2, VH3 and VH4 are different from each other; or,
  • VH1, VH2, VH3 and VH4 are different from each other.
  • the display substrate described in the embodiment of the present disclosure includes a base substrate and the above-mentioned driving circuit arranged on the base substrate.
  • the driving circuit includes a first low voltage line, a second low voltage line, a first high voltage line, a second high voltage line, a first node control circuit, a second node control circuit, a first output circuit, a second output circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit and a third node control circuit;
  • the second low voltage line is arranged at a side of the driving circuit away from the display area, and the first low voltage line is arranged at a side of the driving circuit close to the display area;
  • the first high voltage line and the second high voltage line are arranged between a first circuit part included in the driving circuit and a second circuit part included in the driving circuit;
  • the first circuit portion includes a first node control circuit, a second node control circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit and a third node control circuit, and the second circuit portion includes a first output circuit and a second output circuit;
  • the first circuit portion is arranged between the second low voltage line and the second high voltage line, and the second circuit portion is arranged between the first high voltage line and the first low voltage line, so that the electrodes of each transistor in the driving circuit are electrically connected to the corresponding voltage line.
  • the driving circuit further includes a third node reset circuit, and the first circuit portion includes the third node reset circuit.
  • FIG21 is a layout diagram of at least one embodiment of the driving circuit shown in FIG15 of the present disclosure.
  • Figure 22 is a layout diagram of the active layer in Figure 21
  • Figure 23 is a layout diagram of the first gate metal layer in Figure 21
  • Figure 24 is a layout diagram of the second gate metal layer in Figure 21
  • Figure 25 is a layout diagram of the source and drain metal layers in Figure 21.
  • the start signal line ESTV, the second clock signal line CB, the first clock signal line CK, the reset line VEL, the second low voltage line VGL2, the second high voltage line VGH2, the first high voltage line VGH and the first low voltage line VGL all extend in the vertical direction;
  • the start signal line ESTV, the second clock signal line CB, the first clock signal line CK, the reset line VEL and the second low voltage line VGL2 are arranged on a side of the driving circuit away from the display area;
  • the start signal line ESTV, the second clock signal line CB, the first clock signal line CK, the reset line VEL and the second low voltage line VGL2 are arranged in a direction close to the display area.
  • the first low voltage line VGL is arranged on a side of the driving circuit close to the display area;
  • the first high voltage line VGH is connected to the first electrode So of To, and the second high voltage line VGH2 is arranged on a side of the first high voltage line VGH away from To;
  • the first low voltage line VGL is connected to the second electrode Df of Tf.
  • the driving circuit includes a first circuit portion and a second circuit portion; the first circuit portion includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11, and the second circuit portion includes an output transistor To and an output reset transistor Tf;
  • the first circuit portion is disposed between the second low voltage line VGL2 and the second high voltage line VGH2
  • the second circuit portion is disposed between the second high voltage line VGH2 and the first low voltage line VGL.
  • T2 and T6 are adjacent to VGL2 , so that the gate G2 of T2 and the gate G6 of T6 are electrically connected to VGL;
  • T1 is adjacent to VGL2 so that a first electrode of T1 is electrically connected to VGL2.
  • G1 is the gate of T1
  • G2 is the gate of T2
  • G3 is the gate of T3
  • G4 is the gate of T4
  • G5 is the gate of T5
  • G6 is the gate of T6
  • G7 is the gate of T7
  • G8 is the gate of T8
  • G9 is the gate of T9
  • G10 is the gate of T10
  • G11 is the gate of T11
  • Go is the gate of To
  • Gf is the gate of Tf;
  • the first electrode plate of C2 is labeled C2a
  • the second electrode plate of C2 is labeled C2b;
  • the first electrode plate of C3 is labeled C3a
  • the second electrode plate of C3 is labeled C3b
  • the first electrode plate of C1 is labeled C1a
  • the second electrode plate of C2 is labeled C1b.
  • the gate G4 of T4 is electrically connected to VEL
  • the first electrode of T4 is electrically connected to VGH2 through a via hole
  • the first electrode of T5 is electrically connected to VGH2 through a via hole.
  • A1 is an active layer pattern of T1
  • A2 is an active layer pattern of T2
  • A3 is an active layer pattern of T3
  • A4 is an active layer pattern of T4
  • A5 is an active layer pattern of T5
  • A6 is an active layer pattern of T6
  • A7 is an active layer pattern of T7
  • A8 is an active layer pattern of T8
  • A9 is an active layer pattern of T9
  • A10 is an active layer pattern of T10
  • A11 is an active layer pattern of T11
  • A0 is a first active layer pattern;
  • the first active layer pattern A0 includes an active layer pattern of To and an active layer pattern of Tf.
  • FIG. 26 is a layout diagram of at least one embodiment of the driving circuit shown in FIG. 19 of the present disclosure.
  • Figure 27 is a layout diagram of the active layer in Figure 26
  • Figure 28 is a layout diagram of the first gate metal layer in Figure 26
  • Figure 29 is a layout diagram of the second gate metal layer in Figure 26
  • Figure 30 is a layout diagram of the source and drain metal layers in Figure 26.
  • the display panel described in the embodiment of the present disclosure includes the above-mentioned driving circuit; the display panel also includes a display driving chip;
  • the first low voltage input terminal is electrically connected to the first low voltage line
  • the second low voltage input terminal is electrically connected to the second low voltage line
  • the third low voltage input terminal is electrically connected to the third low voltage line
  • the first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line, provide a second low voltage signal for the second low voltage line, and provide a third low voltage signal for the third low voltage line; or
  • the first low voltage input terminal is electrically connected to the first low voltage line
  • the second low voltage input terminal and the third low voltage input terminal are both electrically connected to the second low voltage line
  • the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line;
  • the first low voltage input terminal and the second low voltage input terminal are both electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line; or
  • the first low voltage input terminal and the third low voltage input terminal are both electrically connected to the first low voltage line
  • the second low voltage input terminal is electrically connected to the second low voltage line
  • the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driver chip
  • the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line.
  • the display panel includes a display driver chip 320 ;
  • the first low voltage input terminal VL1 is electrically connected to the first low voltage line Ld1
  • the second low voltage input terminal VL2 is electrically connected to the second low voltage line Ld2
  • the third low voltage input terminal VL3 is electrically connected to the third low voltage line Ld3
  • the first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320
  • the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320
  • the third low voltage line Ld3 is electrically connected to the third pin P3 of the display driver chip 320;
  • the display driving chip 320 is used to provide a first low voltage signal for the first low voltage line Ld1 , provide a second low voltage signal for the second low voltage line Ld2 , and provide a third low voltage signal for the third low voltage line Ld3 .
  • the display panel includes a display driver chip 320 ;
  • the first low voltage input terminal VL1 is electrically connected to the first low voltage line Ld1, and the second low voltage input terminal VL2 and the third low voltage input terminal VL3 are both electrically connected to the second low voltage line Ld2;
  • the first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;
  • the display driving chip 320 is used to provide a first low voltage signal for the first low voltage line Ld1 and provide a second low voltage signal for the second low voltage line Ld2.
  • the display panel includes a display driver chip 320 ;
  • the first low voltage input terminal VL1 and the second low voltage input terminal VL2 are both electrically connected to the first low voltage line Ld1, and the third low voltage input terminal VL3 is electrically connected to the second low voltage line Ld2;
  • the first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;
  • the display driving chip 320 is used to provide a first low voltage signal for the first low voltage line Ld1 and provide a second low voltage signal for the second low voltage line Ld2.
  • the display panel includes a display driver chip 320 ;
  • the first low voltage input terminal VL1 and the third low voltage input terminal VL3 are both electrically connected to the first low voltage line Ld1, and the second low voltage input terminal VL2 is electrically connected to the second low voltage line Ld2;
  • the first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;
  • the display driving chip 320 is used to provide a first low voltage signal for the first low voltage line Ld1 and provide a second low voltage signal for the second low voltage line Ld2.
  • the display panel described in the embodiment of the present disclosure includes the above-mentioned driving circuit; the display panel also includes a display driving chip;
  • the first high voltage input terminal is electrically connected to the first high voltage line
  • the second high voltage input terminal is electrically connected to the second high voltage line
  • the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip
  • the display driver chip is used to provide a first high voltage signal for the first high voltage line
  • the display driver chip is used to provide a second high voltage signal for the second high voltage line.
  • the display panel includes a display driver chip 320 ;
  • the first low voltage input terminal VL1 and the third low voltage input terminal VL3 are both electrically connected to the first low voltage line Ld1, and the second low voltage input terminal VL2 is electrically connected to the second low voltage line Ld2;
  • the first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;
  • the display driving chip 320 is used to provide a first low voltage signal for the first low voltage line Ld1 and provide a second low voltage signal for the second low voltage line Ld2.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.
  • the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

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Abstract

提供了一种驱动电路、显示面板、显示基板和显示装置。驱动电路包括第一节点控制电路(11)、第二节点控制电路(12)和第一输出电路(13)；第二节点控制电路(12)在第一低电压输出端(VL1)提供的低电压信号的控制下，控制电一节点(N1)与第二节点(N2)之间连通；第一节点控制电路(11)在第一时钟信号(CK)的控制下，控制第一节点(N1)与第二低电压输入端(VL2)电连接；第一输出电路(13)在下拉节点(PD)的电位的控制下，控制驱动信号输出端(O1)与第三低电压输入端(VL3)之间连通；第一低电压输入端(VL1)、第二低电压输入端(VL2)、第三低电压输入端(VL3)中的至少两个互不相同，采用至少两个低电压信号。

Description

驱动电路、显示面板、显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、显示面板、显示基板和显示装置。
背景技术
有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED)显示装置因可弯曲、对比度高和功耗低等优点而被广泛用于各类产品中。
在相关技术中，AMOLED显示装置通常包括：AMOLED显示面板和栅极驱动电路。AMOLED显示面板包括多行像素。栅极驱动电路包括多个级联的移位寄存器单元。每个移位寄存器单元与一行像素耦接，并用于向该一行像素传输栅极驱动信号，以驱动该一行像素发光。由该多个级联的移位寄存器单元可以实现对多行像素的逐行扫描驱动，以使得AMOLED显示面板显示图像。
但是，相关的移位寄存器单元采用相同的电压输入端，无法灵活的设置各节点的电位。
发明内容
在一个方面中，本公开实施例提供一种驱动电路，包括第一节点控制电路、第二节点控制电路和第一输出电路；
所述第二节点控制电路分别与第一低电压输入端、第一节点和第二节点电连接，用于在所述第一低电压输入端提供的低电压信号的控制下，控制所述第一节点与所述第二节点之间连通；
所述第一节点控制电路分别与第二低电压输入端、第一时钟信号线和第一节点电连接，用于在所述第一时钟信号线提供的第一时钟信号的控制下，控制所述第一节点与所述第二低电压输入端电连接；
所述第一输出电路分别与下拉节点、驱动信号输出端和第三低电压输入 端电连接，用于在所述下拉节点的电位的控制下，控制所述驱动信号输出端与所述第三低电压输入端之间连通；
所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少两个互不相同。
可选的，本公开至少一实施例所述的驱动电路还包括第二输出电路和第四节点控制电路；
所述第二输出电路分别与上拉节点、第一高电压输入端和驱动信号输出端电连接，用于在所述上拉节点的电位的控制下，控制所述第一高电压输入端与所述驱动信号输出端之间连通；
所述第四节点控制电路分别与第一节点、第四节点和第四高电压输入端电连接，用于在所述第一节点的电位的控制下，控制所述第四节点与所述第四高电压输入端之间连通；
所述第一高电压输入端与所述第四高电压输入端不同。
可选的，本公开至少一实施例所述的驱动电路还包括第三节点复位电路；
所述第三节点复位电路分别与复位线、第三高电压输入端和所述第三节点电连接，用于在所述复位线提供的复位信号的控制下，控制所述第三高电压输入端与所述第三节点之间连通；
所述第三高电压输入端与所述第一高电压输入端、所述第四高电压输入端中的至少一个不同。
可选的，本公开至少一实施例所述的驱动电路还包括上拉节点控制电路；
所述上拉节点控制电路分别与第三节点、第二高电压输入端和所述上拉节点电连接，用于在所述第三节点的电位的控制下，控制所述第二高电压输入端与所述上拉节点之间连通；
所述第二高电压输入端与第一高电压输入端、第四高电压输入端中的至少一个不相同。
可选的，本公开至少一实施例所述的驱动电路还包括上拉节点控制电路；
所述上拉节点控制电路分别与第三节点、第二高电压输入端和所述上拉节点电连接，用于在所述第三节点的电位的控制下，控制所述第二高电压输入端与所述上拉节点之间连通；
所述第二高电压输入端与所述第三高电压输入端不同。
可选的，本公开至少一实施例所述的驱动电路还包括下拉节点控制电路；
所述下拉节点控制电路分别与第四低电压输入端、第三节点和下拉节点电连接，用于在所述第四低电压输入端提供的低电压信号的控制下，控制所述第三节点与所述下拉节点之间连通；
所述第四低电压输入端与第一低电压输入端、第二低电压输入端、第三低电压输入端中的至少一个不同。
可选的，本公开至少一实施例所述的驱动电路还包括第五节点控制电路和上拉节点控制电路；
所述第五节点控制电路分别与第二节点、第五节点和第二时钟信号线电连接，用于在所述第二节点的电位的控制下，控制所述第二时钟信号线与所述第五节点之间连通，并根据所述第二节点的电位控制所述第五节点的电位；
所述上拉节点控制电路还分别与第五节点、第二时钟信号线和上拉节点电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第五节点与所述上拉节点之间连通，并用于维持所述上拉节点的电位。
可选的，所述驱动电路还包括第三节点控制电路；
所述第三节点控制电路分别与起始电压端、第一时钟信号线和第三节点电连接，用于在所述第一时钟信号线提供的第一时钟信号的控制下，控制所述起始电压端与所述第三节点之间连通；
第一节点控制电路还分别与第三节点、第一节点和第一时钟信号线电连接，用于在所述第三节点的电位的控制下，控制所述第一节点与所述第一时钟信号线之间连通；
所述第四节点控制电路还分别与下拉节点和第二时钟信号线电连接，用于在在所述下拉节点的电位的控制下，控制所述第四节点与所述第二时钟信号线之间连通，并根据所述下拉节点的电位控制所述第四节点的电位。
可选的，所述第一节点控制电路包括第一晶体管，所述第二节点控制电路包括第二晶体管；
所述第一晶体管的控制极与第一时钟信号线电连接，所述第一晶体管的第一极与第二低电压输入端电连接，所述第一晶体管的第二极与第一节点电 连接；
所述第二晶体管的控制极与第一低电压输入端电连接，所述第二晶体管的第一极与第一节点电连接，所述第二晶体管的第二极与第二节点电连接；
所述第一输出电路包括输出复位晶体管，所述输出复位晶体管的控制极与所述下拉节点电连接，所述输出复位晶体管的第一极与驱动信号输出端电连接，所述输出复位晶体管的第二极与第三低电压输入端电连接。
可选的，所述第二输出电路包括输出晶体管，所述上拉节点控制电路包括第三晶体管和第一电容；
所述输出晶体管的控制极与所述上拉节点电连接，所述输出晶体管的第一极与第一高电压输入端电连接，所述输出晶体管的第二极与所述驱动信号输出端电连接；
所述第三晶体管的控制极与第三节点电连接，所述第三晶体管的第一极与第二高电压输入端电连接，所述第三晶体管的第二极与上拉节点电连接；
所述第一电容的第一极板与上拉节点电连接，所述第一电容的第二极板与所述第一高电压输入端电连接。
可选的，所述第三节点复位电路包括第四晶体管；
所述第四晶体管的控制极与所述复位线电连接，所述第四晶体管的第一极与第三高电压输入端电连接，所述第四晶体管的第二极与第三节点电连接。
可选的，所述第四节点控制电路包括第五晶体管；
所述第五晶体管的控制极与第一节点电连接，所述第五晶体管的第一极与第四高电压输入端电连接，所述第五晶体管的第二极与第四节点电连接。
可选的，所述下拉节点控制电路包括第六晶体管；
所述第六晶体管的控制极与第四低电压输入端电连接，所述第六晶体管的第一极与第三节点电连接，所述第六晶体管的第二极与下拉节点电连接。
可选的，所述第五节点控制电路包括第七晶体管和第二电容；所述上拉节点控制电路还包括第八晶体管；
所述第七晶体管的控制极与所述第二节点电连接，所述第七晶体管的第一极与第二时钟信号线电连接，所述第七晶体管的第二极与第五节点电连接；
所述第二电容的第一极板与第二节点电连接，所述第二电容的第二极板 与第五节点电连接；
所述第八晶体管的控制极与第二时钟信号线电连接，所述第八晶体管的第一极与第五节点电连接，所述第八晶体管的第二极与上拉节点电连接。
可选的，第一节点控制电路还包括第九晶体管；
所述第九晶体管的控制极与所述第三节点电连接，所述第九晶体管的第一极与所述第一时钟信号线电连接，所述第九晶体管的第二极与第一节点电连接；
所述第四节点控制电路还包括第十晶体管和第三电容；
所述第十晶体管的控制极与下拉节点电连接，所述第十晶体管的第一极与第二时钟信号线电连接，所述第十晶体管的第二极与第四节点电连接；
第三电容的第一极板与所述下拉节点电连接，第三电容的第二极板与第四节点电连接；
所述第三节点控制电路包括第十一晶体管；
所述第十一晶体管的控制极与所述第一时钟信号线电连接，所述第十一晶体管的第一极与起始电压端电连接，所述第十一晶体管的第二极与第三节点电连接。
在第二个方面中，本公开实施例提供一种驱动电路，包括第一晶体管、第二晶体管、输出复位晶体管和第六晶体管；
所述第一晶体管的控制极与第一时钟信号线电连接，所述第一晶体管的第一极与第二低电压输入端电连接，所述第一晶体管的第二极与第一节点电连接；
所述第二晶体管的控制极与第一低电压输入端电连接，所述第二晶体管的第一极与第一节点电连接，所述第二晶体管的第二极与第二节点电连接；
所述第一输出电路包括输出复位晶体管，所述输出复位晶体管的控制极与所述下拉节点电连接，所述输出复位晶体管的第一极与驱动信号输出端电连接，所述输出复位晶体管的第二极与第三低电压输入端电连接；
所述第六晶体管的控制极与第四低电压输入端电连接，所述第六晶体管的第一极与第三节点电连接，所述第六晶体管的第二极与下拉节点电连接；
所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入 端和所述低电压输入端不完全相同。
在第三个方面中，本公开实施例提供一种驱动电路，包括输出晶体管、第三晶体管、第四晶体管和第五晶体管；
所述输出晶体管的控制极与所述上拉节点电连接，所述输出晶体管的第一极与第一高电压输入端电连接，所述输出晶体管的第二极与所述驱动信号输出端电连接；
所述第三晶体管的控制极与第三节点电连接，所述第三晶体管的第一极与第二高电压输入端电连接，所述第三晶体管的第二极与上拉节点电连接；
所述第四晶体管的控制极与所述复位线电连接，所述第四晶体管的第一极与第三高电压输入端电连接，所述第四晶体管的第二极与第三节点电连接；
所述第五晶体管的控制极与第一节点电连接，所述第五晶体管的第一极与第四高电压输入端电连接，所述第五晶体管的第二极与第四节点电连接；
所述第一高电压输入端、所述第二高电压输入端、所述第三高电压输入端和所述第四高电压输入端不完全相同。
在第四个方面中，本公开实施例提供一种显示面板，包括上述的驱动电路；所述显示面板还包括显示驱动芯片；
第一低电压输入端与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第三低电压输入端与第三低电压线电连接，第一低电压线、第二低电压线、第三低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号，为第三低电压线提供第三低电压信号；或者，
第一低电压输入端与第一低电压线电连接，第二低电压输入端和第三低电压输入端都与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
第一低电压输入端和第二低电压输入端都与第一低电压线电连接，第三低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
第一低电压输入端和第三低电压输入端都与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号。
在第六个方面中，本公开实施例提供一种显示面板，包括上述的驱动电路；所述显示面板还包括显示驱动芯片；
第一高电压输入端与第一高电压线电连接，第二高电压输入端与第二高电压线电连接；所述第一高电压线、所述第二高电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一高电压线提供第一高电压信号，所述显示驱动芯片用于为第二高电压线提供第二高电压信号。
在第七个方面中，本公开实施例提供一种显示基板，包括衬底基板和设置于衬底基板上的上的驱动电路。
可选的，所述驱动电路包括第一低电压线、第二低电压线、第一高电压线、第二高电压线、第一节点控制电路、第二节点控制电路、第一输出电路、第二输出电路、上拉节点控制电路、第四节点控制电路、下拉节点控制电路、第五节点控制电路和第三节点控制电路；
所述第二低电压线设置于所述驱动电路远离显示区域的一侧，所述第一低电压线设置于所述驱动电路靠近显示区域的一侧；
所述第一高电压线和所述第二高电压线设置于所述驱动电路包括的第一电路部分和所述驱动电路包括的第二电路部分之间；
所述第一电路部分包括第一节点控制电路、第二节点控制电路、上拉节点控制电路、第四节点控制电路、下拉节点控制电路、第五节点控制电路和第三节点控制电路，所述第二电路部分包括第一输出电路和第二输出电路；
所述第一电路部分设置于第二低电压线与第二高电压线之间，所述第二电路部分设置于第一高电压线与第一低电压线之间。
可选的，所述驱动电路还包括第三节点复位电路，所述第一电路部分包括所述第三节点复位电路。
在第八个公开中，本公开实施例提供一种显示装置，包括上述的驱动电路。
附图说明
图1是本公开实施例所述的驱动电路的结构图；
图2是本公开至少一实施例所述的驱动电路的结构图；
图3是本公开至少一实施例所述的驱动电路的结构图；
图4是本公开至少一实施例所述的驱动电路的结构图；
图5是本公开至少一实施例所述的驱动电路的结构图；
图6是本公开至少一实施例所述的驱动电路的结构图；
图7是本公开至少一实施例所述的驱动电路的电路图；
图8A是本公开至少一实施例所述的驱动电路的电路图；
图8B是本公开如图8A所示的驱动电路的至少一实施例的工作时序图；
图9是本公开至少一实施例所述的驱动电路的电路图；
图10是本公开至少一实施例所述的驱动电路的电路图；
图11是本公开至少一实施例所述的驱动电路的电路图；
图12是本公开至少一实施例所述的驱动电路的电路图；
图13是本公开至少一实施例所述的驱动电路的电路图；
图14是本公开至少一实施例所述的驱动电路的电路图；
图15是本公开至少一实施例所述的驱动电路的电路图；
图16是本公开至少一实施例所述的驱动电路的电路图；
图17是本公开至少一实施例所述的驱动电路的电路图；
图18是本公开至少一实施例所述的驱动电路的电路图；
图19A是本公开至少一实施例所述的驱动电路的电路图；
图19B是本公开至少一实施例所述的显示面板的结构图；
图20是相关的像素电路的电路图；
图21是本公开图15所示的驱动电路的至少一实施例的布局图；
图22是图21中的有源层的布局图；
图23是图21中的第一栅金属层的布局图；
图24是图21中的第二栅金属层的布局图；
图25是图21中的源漏金属层的布局图；
图26是本公开图19所示的驱动电路的至少一实施例的布局图；
图27是图26中的有源层的布局图；
图28是图26中的第一栅金属层的布局图；
图29是图26中的第二栅金属层的布局图；
图30是图26中的源漏金属层的布局图；
图31是本公开至少一实施例所述的显示面板的结构图；
图32是本公开至少一实施例所述的显示面板的结构图；
图33是本公开至少一实施例所述的显示面板的结构图；
图34是本公开至少一实施例所述的显示面板的结构图；
图35是本公开至少一实施例所述的显示面板的结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的驱动电路包括第一节点控制电路11、第二节点控制电路12和第一输出电路13；
所述第二节点控制电路12分别与第一低电压输入端VL1、第一节点N1和第二节点N2电连接，用于在所述第一低电压输入端VL1提供的低电压信号的控制下，控制所述第一节点N1与所述第二节点N2之间连通；
所述第一节点控制电路11分别与第二低电压输入端VL2、第一时钟信号线CK和第一节点N1电连接，用于在所述第一时钟信号线CK提供的第一时 钟信号的控制下，控制所述第一节点N1与所述第二低电压输入端VL2电连接；
所述第一输出电路13分别与下拉节点PD、驱动信号输出端O1和第三低电压输入端VL3电连接，用于在所述下拉节点PD的电位的控制下，控制所述驱动信号输出端O1与所述第三低电压输入端VL3之间连通；
所述第一低电压输入端VL1、所述第二低电压输入端VL2、所述第三低电压输入端VL3中至少两个互不相同。
在本公开至少一实施例中，两个低电压输入端不同指的可以是：所述两个低电压输入端分别提供的低电压信号不同。
在图1所示的驱动电路的实施例中，第一低电压输入端VL1提供的低电压信号可以与第二低电压输入端VL2提供的低电压信号不同。
在本公开至少一实施例中，所述低电压信号的电压值可以为负电压。
例如，当第一节点控制电路11包括的晶体管和第二节点控制电路12包括的晶体管为p型晶体管时，第二低电压输入端VL2提供的低电压信号的绝对值大于第一低电压输入端VL1提供的低电压信号的绝对值，以使得N1的电位和N2的电位更低。
在本公开至少一实施例中，所述第一低电压输入端可以提供第一低电压信号，所述第二低电压输入端可以提供第二低电压信号，但不以此为限。
在本公开至少一实施例中，可以由第一低电压线VGL提供第一低电压信号，由第二低电压线VGL2提供第二低电压信号。
在图1所示的驱动电路的实施例中，第一低电压输入端VL1可以提供第一低电压信号，第二低电压输入端VL2可以提供第二低电压信号，所述第三低电压输入端VL3可以提供第一低电压信号；或者，
所述第一低电压输入端VL1可以提供第二低电压信号，所述第二低电压输入端VL2可以提供第二低电压信号，所述第三低电压输入端VL3可以提供第一低电压信号；或者，
所述第一低电压输入端VL1可以提供第一低电压信号，所述第二低电压输入端VL2可以提供第一低电压信号，所述第三低电压输入端VL3可以提供第二低电压信号；或者，
所述第一低电压输入端VL1可以提供第一低电压信号，所述第二低电压输入端VL2可以提供第二低电压信号，所述第三低电压输入端VL3可以提供第二低电压信号；
但不以此为限。
如图2所示，在图1所示的驱动电路的实施例的基础上，本公开至少一实施例所述的驱动电路还包括第二输出电路21和第四节点控制电路41；
所述第二输出电路21分别与上拉节点PU、第一高电压输入端VH1和驱动信号输出端O1电连接，用于在所述上拉节点PU的电位的控制下，控制所述第一高电压输入端VH1与所述驱动信号输出端O1之间连通；
所述第四节点控制电路41分别与第一节点N1、第四节点N4和第四高电压输入端VH4电连接，用于在所述第一节点N1的电位的控制下，控制所述第四节点N4与所述第四高电压输入端VH4之间连通；所述第一高电压输入端VH1与所述第四高电压输入端VH4不同。
在本公开至少一实施例中，两个高电压输入端不同指的可以是：两个高电压输入端分别提供的高电压信号不同。
在本公开至少一实施例中，第一高电压输入端VH1可以提供第一高电压信号，第二高电压输入端VH2可以提供第二高电压信号。
在本公开至少一实施例中，可以由第一高电压线VGH提供第一高电压信号，由第二高电压线VGH2提供第二高电压信号。
在具体实施时，当第二输出电路21包括的晶体管为p型晶体管时，可以将第一高电压输入端提供的高电压信号的电压值设置为小于第二高电压输入端提供的高电压信号的电压值，以使得当所述上拉节点控制电路22包括的晶体管导通时，所述第二输出电路21包括的晶体管可以更好的关断；
当第二输出电路21包括的晶体管为n型晶体管时，可以将第一高电压输入端提供的高电压信号的电压值设置为大于第二高电压输入端提供的高电压信号的电压值，以使得当所述上拉节点控制电路22包括的晶体管导通时，所述第二输出电路21包括的晶体管可以更好的关断；
但不以此为限。
在本公开至少一实施例中，所述驱动电路还包括第三节点复位电路；
所述第三节点复位电路分别与复位线、第三高电压输入端和所述第三节点电连接，用于在所述复位线提供的复位信号的控制下，控制所述第三高电压输入端与所述第三节点之间连通；
所述第三高电压输入端与所述第一高电压输入端、所述第二高电压输入端中的至少一个不同。
如图3所示，在图2所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括第三节点复位电路31；
所述第三节点复位电路31分别与复位线VEL、第三高电压输入端VH3和所述第三节点N3电连接，用于在所述复位线VEL提供的复位信号的控制下，控制所述第三高电压输入端VH3与所述第三节点N3之间连通。
在图3所示的至少一实施例中，所述第三高电压输入端VH3可以用于提供第二高电压信号，或者，所述第三高电压输入端VH3可以用于提供第一高电压信号，但不以此为限。
在本公开至少一实施例中，第一低电压信号的电压值可以大于第二低电压信号的电压值；或者，第一低电压信号的电压值可以小于第二低电压信号的电压值；
第一高电压信号的电压值可以大于第二高电压信号的电压值；或者，第一高电压信号的电压值可以小于第二高电压信号的电压值。
本公开至少一实施例所述的驱动电路还包括上拉节点控制电路；
所述上拉节点控制电路分别与第三节点、第二高电压输入端和所述上拉节点电连接，用于在所述第三节点的电位的控制下，控制所述第二高电压输入端与所述上拉节点之间连通；
所述第二高电压输入端与第一高电压输入端、第四高电压输入端中的至少一个不相同。
本公开至少一实施例所述的驱动电路还包括上拉节点控制电路；
所述上拉节点控制电路分别与第三节点、第二高电压输入端和所述上拉节点电连接，用于在所述第三节点的电位的控制下，控制所述第二高电压输入端与所述上拉节点之间连通；
所述第二高电压输入端与所述第三高电压输入端不同。
如图4所示，在图3所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括上拉节点控制电路22；
所述上拉节点控制电路22分别与第三节点N3、第二高电压输入端VH2和所述上拉节点PU电连接，用于在所述第三节点N3的电位的控制下，控制所述第二高电压输入端VH2与所述上拉节点PU之间连通；
所述第二高电压输入端VH2与第一高电压输入端VH1、第四高电压输入端VH4、第三高电压输入端VH3中至少之一不同。
在具体实施时，所述第四高电压输入端VH4可以提供第一高电压信号或第二高电压信号，但不以此为限。
在本公开至少一实施例中，所述驱动电路还包括下拉节点控制电路；
所述下拉节点控制电路分别与第四低电压输入端、第三节点和下拉节点电连接，用于在所述第四低电压输入端提供的第四低电压信号的控制下，控制所述第三节点与所述下拉节点之间连通；
所述第四低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少一个不同。
如图5所示，在图4所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括下拉节点控制电路51；
所述下拉节点控制电路51分别与第四低电压输入端VL4、第三节点N3和下拉节点PD电连接，用于在所述第四低电压输入端VL4提供的第四低电压信号的控制下，控制所述第三节点N3与所述下拉节点PD之间连通；
所述第四低电压输入端VL4与所述第一低电压输入端VL1、所述第二低电压输入端VL2、所述第三低电压输入端VL3中的至少一个不同。
在本公开至少一实施例中，所述第四低电压输入端VL4可以提供第一低电压信号或第二低电压信号，但不以此为限。
在本公开至少一实施例中，所述驱动电路还包括第五节点控制电路和上拉节点控制电路；
所述第五节点控制电路分别与第二节点、第五节点和第二时钟信号线电连接，用于在所述第二节点的电位的控制下，控制所述第二时钟信号线与所述第五节点之间连通，并根据所述第二节点的电位控制所述第五节点的电位；
所述上拉节点控制电路还分别与第五节点、第二时钟信号线和上拉节点电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第五节点与所述上拉节点之间连通，并用于维持所述上拉节点的电位。
在具体实施时，所述驱动电路还包括第五节点控制电路，第五节点控制电路用于控制第五节点的电位，所述上拉节点控制电路用于控制上拉节点的电位。
在本公开至少一实施例中，所述驱动电路还包括第三节点控制电路；
所述第三节点控制电路分别与起始电压端、第一时钟信号线和第三节点电连接，用于在所述第一时钟信号线提供的第一时钟信号的控制下，控制所述起始电压端与所述第三节点之间连通；
第一节点控制电路还分别与第三节点、第一节点和第一时钟信号线电连接，用于在所述第三节点的电位的控制下，控制所述第一节点与所述第一时钟信号线之间连通；
所述第四节点控制电路还分别与下拉节点和第二时钟信号线电连接，用于在在所述下拉节点的电位的控制下，控制所述第四节点与所述第二时钟信号线之间连通，并根据所述下拉节点的电位控制所述第四节点的电位。
在具体实施时，所述驱动电路还包括第三节点控制电路，所述第三节点控制电路控制第三节点的电位，第一节点控制电路控制第一节点的电位，第四节点控制电路控制第四节点的电位。
如图6所示，在图5所示的驱动电路的至少一实施例的基础上，所述驱动电路还包括第五节点控制电路71和第三节点控制电路72；
所述第五节点控制电路71分别与第二节点N2、第五节点N5和第二时钟信号线CB电连接，用于在所述第二节点N2的电位的控制下，控制所述第二时钟信号线CB与所述第五节点N5之间连通，并根据所述第二节点N2的电位控制所述第五节点N5的电位；
所述上拉节点控制电路22还分别与第五节点N5、第二时钟信号线CB和上拉节点PU电连接，用于在所述第二时钟信号线CB提供的第二时钟信号的控制下，控制所述第五节点N5与所述上拉节点PU之间连通，并用于维持所述上拉节点PU的电位；
所述第三节点控制电路72分别与起始电压端STV、第一时钟信号线CK和第三节点N3电连接，用于在所述第一时钟信号线CK提供的第一时钟信号的控制下，控制所述起始电压端STV与所述第三节点N3之间连通；
第一节点控制电路11还分别与第三节点N3、第一节点N1和第一时钟信号线CK电连接，用于在所述第三节点N3的电位的控制下，控制所述第一节点N1与所述第一时钟信号线CK之间连通；
所述第四节点控制电路41还分别与下拉节点PD和第二时钟信号线CB电连接，用于在在所述下拉节点PD的电位的控制下，控制所述第四节点N4与所述第二时钟信号线CB之间连通，并根据所述下拉节点PD的电位控制所述第四节点N4的电位。
可选的，所述第一节点控制电路包括第一晶体管，所述第二节点控制电路包括第二晶体管；
所述第一晶体管的控制极与第一时钟信号线电连接，所述第一晶体管的第一极与第二低电压输入端电连接，所述第一晶体管的第二极与第一节点电连接；
所述第二晶体管的控制极与第一低电压输入端电连接，所述第二晶体管的第一极与第一节点电连接，所述第二晶体管的第二极与第二节点电连接；
所述第一输出电路包括输出复位晶体管；
所述输出复位晶体管的控制极与所述下拉节点电连接，所述输出复位晶体管的第一极与驱动信号输出端电连接，所述输出复位晶体管的第二极与第三低电压输入端电连接。
可选的，所述第二输出电路包括输出晶体管，所述上拉节点控制电路包括第三晶体管和第一电容；
所述输出晶体管的控制极与所述上拉节点电连接，所述输出晶体管的第一极与第一高电压输入端电连接，所述输出晶体管的第二极与所述驱动信号输出端电连接；
所述第三晶体管的控制极与第三节点电连接，所述第三晶体管的第一极与第二高电压输入端电连接，所述第三晶体管的第二极与上拉节点电连接；
所述第一电容的第一极板与上拉节点电连接，所述第一电容的第二极板 与所述第一高电压输入端电连接。
可选的，所述第三节点复位电路包括第四晶体管；
所述第四晶体管的控制极与所述复位线电连接，所述第四晶体管的第一极与第三高电压输入端电连接，所述第四晶体管的第二极与第三节点电连接。
可选的，所述第四节点控制电路包括第五晶体管；
所述第五晶体管的控制极与第一节点电连接，所述第五晶体管的第一极与第四高电压输入端电连接，所述第五晶体管的第二极与第四节点电连接。
可选的，所述下拉节点控制电路包括第六晶体管；
所述第六晶体管的控制极与第四低电压输入端电连接，所述第六晶体管的第一极与第三节点电连接，所述第六晶体管的第二极与下拉节点电连接。
可选的，所述第五节点控制电路包括第七晶体管和第二电容；所述上拉节点控制电路还包括第八晶体管；
所述第七晶体管的控制极与所述第二节点电连接，所述第七晶体管的第一极与第二时钟信号线电连接，所述第七晶体管的第二极与第五节点电连接；
所述第二电容的第一极板与第二节点电连接，所述第二电容的第二极板与第五节点电连接；
所述第八晶体管的控制极与第二时钟信号线电连接，所述第八晶体管的第一极与第五节点电连接，所述第八晶体管的第二极与上拉节点电连接。
可选的，第一节点控制电路还包括第九晶体管；
所述第九晶体管的控制极与所述第三节点电连接，所述第九晶体管的第一极与所述第一时钟信号线电连接，所述第九晶体管的第二极与第一节点电连接；
所述第四节点控制电路还包括第十晶体管和第三电容；
所述第十晶体管的控制极与下拉节点电连接，所述第十晶体管的第一极与第二时钟信号线电连接，所述第十晶体管的第二极与第四节点电连接；
第三电容的第一极板与所述下拉节点电连接，第三电容的第二极板与第四节点电连接；
所述第三节点控制电路包括第十一晶体管；
所述第十一晶体管的控制极与所述第一时钟信号线电连接，所述第十一 晶体管的第一极与起始电压端电连接，所述第十一晶体管的第二极与第三节点电连接。
如图7所示，在图6所示的驱动电路的至少一实施例的基础上，所述第一节点控制电路包括第一晶体管T1，所述第二节点控制电路包括第二晶体管T2；
所述第一晶体管T1的栅极与第一时钟信号线CK电连接，所述第一晶体管T1的源极与第二低电压输入端VL2电连接，所述第一晶体管T1的漏极与第一节点N1电连接；
所述第二晶体管T2的栅极与第一低电压输入端VL1电连接，所述第二晶体管T2的源极与第一节点N1电连接，所述第二晶体管T2的漏极与第二节点N2电连接；
所述第一输出电路包括输出复位晶体管Tf；
所述输出复位晶体管Tf的栅极与所述下拉节点PD电连接，所述输出复位晶体管Tf的源极与驱动信号输出端O1电连接，所述输出复位晶体管Tf的漏极与第三低电压输入端VL3电连接；
所述第二输出电路包括输出晶体管To，所述上拉节点控制电路包括第三晶体管T3和第一电容C1；
所述输出晶体管To的栅极与所述上拉节点PU电连接，所述输出晶体管To的源极与第一高电压输入端VH1电连接，所述输出晶体管To的漏极与所述驱动信号输出端O1电连接；
所述第三晶体管T3的栅极与第三节点N3电连接，所述第三晶体管T3的源极与第二高电压输入端VH2电连接，所述第三晶体管T3的漏极与上拉节点PU电连接；
所述第一电容C1的第一极板与上拉节点PU电连接，所述第一电容C1的第二极板与所述第一高电压输入端VH1电连接；
所述第三节点复位电路包括第四晶体管T4；
所述第四晶体管T4的栅极与所述复位线VEL电连接，所述第四晶体管T4的源极与第三高电压输入端VH3电连接，所述第四晶体管T4的漏极与第三节点N3电连接；
所述第四节点控制电路包括第五晶体管T5；
所述第五晶体管T5的栅极与第一节点N1电连接，所述第五晶体管T5的源极与第四高电压输入端VH4电连接，所述第五晶体管T5的漏极与第四节点N4电连接；
所述下拉节点控制电路包括第六晶体管T6；
所述第六晶体管T6的栅极与第四低电压输入端VL4电连接，所述第六晶体管T6的源极与第三节点N3电连接，所述第六晶体管T6的漏极与下拉节点PD电连接；
所述第五节点控制电路包括第七晶体管T7和第二电容C2；所述上拉节点控制电路还包括第八晶体管T8；
所述第七晶体管T7的栅极与所述第二节点N2电连接，所述第七晶体管T7的源极与第二时钟信号线CB电连接，所述第七晶体管T7的漏极与第五节点N5电连接；
所述第二电容C2的第一极板与第二节点N2电连接，所述第二电容C2的第二极板与第五节点N5电连接；
所述第八晶体管T8的栅极与第二时钟信号线CB电连接，所述第八晶体管T8的源极与第五节点N5电连接，所述第八晶体管T8的漏极与上拉节点PU电连接；
第一节点控制电路还包括第九晶体管T9；
所述第九晶体管T9的栅极与所述第三节点N3电连接，所述第九晶体管T9的源极与所述第一时钟信号线CK电连接，所述第九晶体管T9的漏极与第一节点N1电连接；
所述第四节点控制电路还包括第十晶体管T10和第三电容C3；
所述第十晶体管T10的栅极与下拉节点PD电连接，所述第十晶体管T10的源极与第二时钟信号线CB电连接，所述第十晶体管T10的漏极与第四节点N4电连接；
第三电容C3的第一极板与所述下拉节点PD电连接，第三电容C3的第二极板与第四节点N4电连接；
所述第三节点控制电路包括第十一晶体管T11；
所述第十一晶体管T11的栅极与所述第一时钟信号线CK电连接，所述第十一晶体管T11的源极与起始电压端STV电连接，所述第十一晶体管T11的漏极与第三节点N3电连接。
在图7所示的驱动电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。在实际操作时，图7中的晶体管也可以为n型晶体管。
在图7所示的驱动电路的至少一实施例中，第一低电压输入端VL1可以提供第一低电压信号，第二低电压输入端VL2可以提供第二低电压信号，第三低电压输入端VL3可以提供第一低电压信号，第四低电压输入端VL4可以提供第一低电压信号；或者，
第一低电压输入端VL1可以提供第二低电压信号，第二低电压输入端VL2可以提供第二低电压信号，第三低电压输入端VL3可以提供第一低电压信号，第四低电压输入端VL4可以提供第二低电压信号；或者，
第一低电压输入端VL1可以提供第一低电压信号，第二低电压输入端VL2可以提供第一低电压信号，第三低电压输入端VL3可以提供第一低电压信号，第四低电压输入端VL4可以提供第二低电压信号；或者，
第一低电压输入端VL1可以提供第二低电压信号，第二低电压输入端VL2可以提供第一低电压信号，第三低电压输入端VL3可以提供第一低电压信号，第四低电压输入端VL4可以提供第一低电压信号；或者，
第一低电压输入端VL1可以提供第二低电压信号，第二低电压输入端VL2可以提供第一低电压信号，第三低电压输入端VL3可以提供第一低电压信号，第四低电压输入端VL4可以提供第二低电压信号；或者，
第一低电压输入端VL1可以提供第二低电压信号，第二低电压输入端VL2可以提供第二低电压信号，第三低电压输入端VL3可以提供第二低电压信号，第四低电压输入端VL4可以提供第一低电压信号；或者，
第一低电压输入端VL1可以提供第一低电压信号，第二低电压输入端VL2可以提供第二低电压信号，第三低电压输入端VL3可以提供第二低电压信号，第四低电压输入端VL4可以提供第一低电压信号；或者，
第一低电压输入端VL1可以提供第一低电压信号，第二低电压输入端VL2可以提供第一低电压信号，第三低电压输入端VL3可以提供第二低电压 信号，第四低电压输入端VL4可以提供第一低电压信号；
但不以此为限。
在图7所示的驱动电路的至少一实施例中，
第一高电压输入端VH1可以提供第一高电压信号，第二高电压输入端VH2可以提供第二高电压信号，第三高电压输入端VH3可以提供第二高电压信号，第四高电压输入端VH4可以提供第一高电压信号；或者，
第一高电压输入端VH1可以提供第一高电压信号，第二高电压输入端VH2可以提供第二高电压信号，第三高电压输入端VH3可以提供第一高电压信号，第四高电压输入端VH4可以提供第一高电压信号；或者，
第一高电压输入端VH1可以提供第一高电压信号，第二高电压输入端VH2可以提供第二高电压信号，第三高电压输入端VH3可以提供第一高电压信号，第四高电压输入端VH4可以提供第二高电压信号；或者，
第一高电压输入端VH1可以提供第二高电压信号，第二高电压输入端VH2可以提供第一高电压信号，第三高电压输入端VH3可以提供第二高电压信号，第四高电压输入端VH4可以提供第一高电压信号；或者，
第一高电压输入端VH1可以提供第二高电压信号，第二高电压输入端VH2可以提供第一高电压信号，第三高电压输入端VH3可以提供第一高电压信号，第四高电压输入端VH4可以提供第一高电压信号；或者，
第一高电压输入端VH1可以提供第二高电压信号，第二高电压输入端VH2可以提供第一高电压信号，第三高电压输入端VH3可以提供第一高电压信号，第四高电压输入端VH4可以提供第二高电压信号；
但不以此为限。
如图8A所示，在图7所示的驱动电路的至少一实施例的基础上，第一低电压输入端VL1提供第一低电压信号，第二低电压输入端VL2提供第二低电压信号，第三低电压输入端VL3提供第一低电压信号，第四低电压输入端VL4提供第一低电压信号；所述第一低电压信号由第一低电压线VGL提供，所述的第二低电压信号由第二低电压线VGL2提供；
第一高电压输入端VH1提供第一高电压信号，第二高电压输入端VH2提供第二高电压信号，第三高电压输入端VH3提供第二高电压信号，第四高 电压输入端VH4提供第一高电压信号；所述第一高电压信号由第一高电压线VGH提供，所述第二高电压信号由第二高电压线VGH2提供。
本公开图8A所示的驱动电路的至少一实施例在工作时，VGL2提供的第二低电压信号的电压值可以小于VGL提供的第一低电压信号的电压值，例如，当VGL提供的第一低电压信号的电压值为-6V时，VGL2提供的第二低电压信号的电压值可以为-6.5V；由于p型晶体管传递低电平时有阈值电压损失，因此可以将的电压值设置为低于的电压值，以能够使得当T1和T2导通时，N1的电位和N2的电位能够更低，使得上拉节点PU开启更快，O1输出的驱动信号的Delay(延迟)更小。
在本公开至少一实施例中，第二低电压信号的电压值与第一低电压信号的电压值之间的差值可以略大于p型晶体管的阈值电压，或等于该阈值电压。
本公开图8A所示的驱动电路的至少一实施例采用了两个高电压输入端和两个低电压输入端；
在进行低频显示时，可以适当降低一个高电压输入端提供的高电压信号的电压值，以及一个低电压输入端提供的低电压信号的电压值的绝对值，以降低功耗；
例如，在进行低频显示时，可以控制第一高电压信号的电压值和第一低电压信号的电压值不变，但是将第二高电压信号的电压值从7V降至6V，将第二低电压信号的电压值从-7V调节为-6V，以降低功耗。
本公开图8A所示的驱动电路的至少一实施例在工作时，可以将第二高电压信号的电压值由7V调高为10V，将第二低电压信号的电压值由-7V调节为-10V，以提升To和Tf的开关能力。
如图9所示，在图7所示的驱动电路的至少一实施例的基础上，第一低电压输入端VL1提供第二低电压信号，第二低电压输入端VL2提供第二低电压信号，第三低电压输入端VL3提供第一低电压信号，第四低电压输入端VL4提供第二低电压信号；所述第一低电压信号由第一低电压线VGL提供，所述的第二低电压信号由第二低电压线VGL2提供；
第一高电压输入端VH1提供第一高电压信号，第二高电压输入端VH2提供第二高电压信号，第三高电压输入端VH3提供第二高电压信号，第四高 电压输入端VH4提供第一高电压信号；所述第一高电压信号由第一高电压线VGH提供，所述第二高电压信号由第二高电压线VGH2提供。
在本公开至少一实施例中，VGH2的电压值可以大于VGH1的电压值，以补偿阈值电压漂移带来的漏电影响，但不以此为限。
在图9所示的驱动电路的至少一实施例中，将T2的栅极和T6的栅极设置为都与提供第二低电压信号的第二低电压线VGL2电连接，利于布局，提升空间利用率。
本公开图10所示的驱动电路的至少一实施例与本公开图8A所示的驱动电路的至少一实施例的区别在于：不设置有T4。
本公开图11所示的驱动电路的至少一实施例与本公开图9所示的驱动电路的至少一实施例的区别在于：不设置有T4。
本公开图12所示的驱动电路的至少一实施例与本公开图8A所示的驱动电路的至少一实施例的区别在于：To的源极与第二高电压线VGH2电连接，T3的源极与第一高电压线VGH电连接。
本公开图13所示的驱动电路的至少一实施例与本公开图12所示的驱动电路的至少一实施例的区别在于：T4的源极与第一高电压线VGH电连接。
本公开图14所示的驱动电路的至少一实施例与本公开图13所示的驱动电路的至少一实施例的区别在于：T5的源极与第二高电压线VGH2电连接。
本公开图15所示的驱动电路的至少一实施例与本公开图14所示的驱动电路的至少一实施例的区别在于：T4的源极与第二高电压线VGH2电连接。
本公开图16所示的驱动电路的至少一实施例与本公开图12所示的驱动电路的至少一实施例的区别在于：T2的栅极和T6的栅极都与第二低电压线VGL2电连接。
本公开图17所示的驱动电路的至少一实施例与本公开图16所示的驱动电路的至少一实施例的区别在于：T2的栅极与第一低电压线VGL电连接。
本公开图18所示的驱动电路的至少一实施例与本公开图16所示的驱动电路的至少一实施例的区别在于：T6的栅极与第一低电压线VGL电连接。
本公开图19A所示的驱动电路的至少一实施例与本公开图15所示的驱动电路的至少一实施例的区别在于：不包含T4。
本公开至少一实施例所述的驱动电路包括第二输出电路和上拉节点控制电路；
所述第二输出电路分别与上拉节点、第一高电压输入端和驱动信号输出端电连接，用于在所述上拉节点的电位的控制下，控制所述第一高电压输入端与所述驱动信号输出端之间连通；
所述上拉节点控制电路分别与第三节点、第二高电压输入端和所述上拉节点电连接，用于在所述第三节点的电位的控制下，控制所述第二高电压输入端与所述上拉节点之间连通；
所述第一高电压输入端与所述第二高电压输入端不同。
在本公开至少一实施例中，所述的驱动电路还包括第三节点复位电路；
所述第三节点复位电路分别与复位线、第三高电压输入端和所述第三节点电连接，用于在所述复位线提供的复位信号的控制下，控制所述第三高电压输入端与所述第三节点之间连通；
所述第三高电压输入端与所述第一高电压输入端、所述第二高电压输入端中的至少一个不同。
在本公开至少一实施例中，所述的驱动电路还包括第四节点控制电路；
所述第四节点控制电路分别与第一节点、第四节点和第四高电压输入端电连接，用于在所述第一节点的电位的控制下，控制所述第四节点与所述第四高电压输入端之间连通；
所述第四高电压输入端与第一高电压输入端、第二高电压输入端中的至少一个不相同。
在本公开至少一实施例中，所述的驱动电路还包括第四节点控制电路；
所述第四节点控制电路分别与第一节点、第四节点和第四高电压输入端电连接，用于在所述第一节点的电位的控制下，控制所述第四节点与所述第四高电压输入端之间连通；
所述第四高电压输入端与所述第三高电压输入端不同。
本公开实施例还提供一种显示面板，包括上述的驱动电路；所述显示面板还包括显示驱动芯片；
第一高电压输入端与第一高电压线电连接，第二高电压输入端与第二高 电压线电连接；所述第一高电压线、所述第二高电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一高电压线提供第一高电压信号，所述显示驱动芯片用于为第二高电压线提供第二高电压信号。
在本公开实施例所述的显示面板中，第一高电压输入端与第一高电压线电连接，第二高电压输入端与第二高电压线电连接，第一高电压线与显示驱动芯片的第一引脚电连接，第二高电压线与显示驱动芯片的第二引脚电连接，显示驱动芯片通过第一引脚向所述第一高电压线提供第一高电压信号，显示驱动芯片通过第二引脚向所述所述第二高电压线提供第二高电压信号。
如图19B所示，所述显示面板包括显示驱动芯片320；
第一高电压输入端VH1与第一高电压线LH1电连接，第二高电压输入端VH2与第二高电压线LH2电连接；
所述第一高电压线LH1与所述显示驱动芯片320的第一引脚P1电连接，所述第二高电压线LH2与所述显示驱动芯片320的第二引脚P2电连接；
所述显示驱动芯片320用于为第一高电压线LH1提供第一高电压信号，所述显示驱动芯片320用于为第二高电压线LH2提供第二高电压信号。
如图20所示，相关的像素电路包括第一显示控制晶体管M1、第二显示控制晶体管M2、第三显示控制晶体管M3、第四显示控制晶体管M4、第五显示控制晶体管M5、第六显示控制晶体管M6、第七显示控制晶体管M7、第八显示控制晶体管M8、存储电容C0和有机发光二极管E1；
在图20中，标号为EM的为发光控制线，标号为R1的为第一复位控制线，标号为R2的为第二复位控制线，标号为NG的为第一扫描线，标号为PG的为第二扫描线，标号为Vi1的为第一初始电压，标号为Vi2的为第二初始电压，标号为Vi3的为第三初始电压，标号为VDD的为高电平端，标号为VSS的为低电平端。
本公开至少一实施例所述的驱动电路能够用于为第一扫描线NG提供第一扫描信号，为发光控制线EM提供发光控制信号，为第一复位控制线R1提供第一复位控制信号，为第二复位控制线R2提供第二复位控制信号。
本公开至少一实施例所述的驱动电路包括第一晶体管、第二晶体管、输出复位晶体管和第六晶体管；
所述第一晶体管的控制极与第一时钟信号线电连接，所述第一晶体管的第一极与第二低电压输入端电连接，所述第一晶体管的第二极与第一节点电连接；
所述第二晶体管的控制极与第一低电压输入端电连接，所述第二晶体管的第一极与第一节点电连接，所述第二晶体管的第二极与第二节点电连接；
所述第一输出电路包括输出复位晶体管，所述输出复位晶体管的控制极与所述下拉节点电连接，所述输出复位晶体管的第一极与驱动信号输出端电连接，所述输出复位晶体管的第二极与第三低电压输入端电连接；
所述第六晶体管的控制极与第四低电压输入端电连接，所述第六晶体管的第一极与第三节点电连接，所述第六晶体管的第二极与下拉节点电连接；
所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端和所述第四低电压输入端不完全相同。
在本公开至少一实施例中，第一低电压输入端VL1、第二低电压输入端VL2、第三低电压输入端VL3和第四低电压输入端VL4不完全相同，具体如下：
VL1与VL2不相同；或者，
VL1和VL3不相同；或者，
VL1和VL4不相同；或者，
VL2与VL3不相同；或者，
VL2与VL4不相同；或者，
VL3和VL4不相同；或者，
VL1、VL2和VL3互不相同；或者，
VL1、VL2和VL4互不相同；或者，
VL1、VL3和VL4互不相同；或者，
VL2、VL3和VL4互不相同；或者，
VL1、VL2、VL3和VL4互不相同。
本公开至少一实施例所述的驱动电路包括输出晶体管、第三晶体管、第四晶体管和第五晶体管；
所述输出晶体管的控制极与所述上拉节点电连接，所述输出晶体管的第 一极与第一高电压输入端电连接，所述输出晶体管的第二极与所述驱动信号输出端电连接；
所述第三晶体管的控制极与第三节点电连接，所述第三晶体管的第一极与第二高电压输入端电连接，所述第三晶体管的第二极与上拉节点电连接；
所述第四晶体管的控制极与所述复位线电连接，所述第四晶体管的第一极与第三高电压输入端电连接，所述第四晶体管的第二极与第三节点电连接；
所述第五晶体管的控制极与第一节点电连接，所述第五晶体管的第一极与第四高电压输入端电连接，所述第五晶体管的第二极与第四节点电连接；
所述第一高电压输入端、所述第二高电压输入端、所述第三高电压输入端和所述第四高电压输入端不完全相同。
在本公开至少一实施例中，所述第一高电压输入端VH1、所述第二高电压输入端VH2、所述第三高电压输入端VH3和所述第四高电压输入端VH4不完全相同，具体如下：
VH1与VH2不相同；或者，
VH1和VH3不相同；或者，
VH1和VH4不相同；或者，
VH2与VH3不相同；或者，
VH2与VH4不相同；或者，
VH3和VH4不相同；或者，
VH1、VH2和VH3互不相同；或者，
VH1、VH2和VH4互不相同；或者，
VH1、VH3和VH4互不相同；或者，
VH2、VH3和VH4互不相同；或者，
VH1、VH2、VH3和VH4互不相同。
本公开实施例所述的显示基板包括衬底基板和设置于衬底基板上的上述的驱动电路。
可选的，所述驱动电路包括第一低电压线、第二低电压线、第一高电压线、第二高电压线、第一节点控制电路、第二节点控制电路、第一输出电路、第二输出电路、上拉节点控制电路、第四节点控制电路、下拉节点控制电路、 第五节点控制电路和第三节点控制电路；
所述第二低电压线设置于所述驱动电路远离显示区域的一侧，所述第一低电压线设置于所述驱动电路靠近显示区域的一侧；
所述第一高电压线和所述第二高电压线设置于所述驱动电路包括的第一电路部分和所述驱动电路包括的第二电路部分之间；
所述第一电路部分包括第一节点控制电路、第二节点控制电路、上拉节点控制电路、第四节点控制电路、下拉节点控制电路、第五节点控制电路和第三节点控制电路，所述第二电路部分包括第一输出电路和第二输出电路；
所述第一电路部分设置于第二低电压线与第二高电压线之间，所述第二电路部分设置于第一高电压线与第一低电压线之间，以便驱动电路中的各晶体管的电极与相应的电压线电连接。
在本公开至少一实施例中，所述驱动电路还包括第三节点复位电路，所述第一电路部分包括所述第三节点复位电路。图21是本公开图15所示的驱动电路的至少一实施例的布局图。
图22是图21中的有源层的布局图，图23是图21中的第一栅金属层的布局图，图24是图21中的第二栅金属层的布局图，图25是图21中的源漏金属层的布局图。
在图21和图25中，标号为ESTV的为起始信号线，标号为CB的为第二时钟信号线，标号为CK的为第一时钟信号线，标号为VEL的为复位线，标号为VGL2的为第一低电压线，标号为VGH2的为第二高电压线，标号为VGH的为第一高电压线，标号为VGL的为第一低电压线。
如图21所示，起始信号线ESTV、第二时钟信号线CB、第一时钟信号线CK、复位线VEL、第二低电压线VGL2、第二高电压线VGH2、第一高电压线VGH和第一低电压线VGL都沿竖直方向延伸；
起始信号线ESTV、第二时钟信号线CB、第一时钟信号线CK、复位线VEL和第二低电压线VGL2设置于驱动电路远离显示区域的一侧；
起始信号线ESTV、第二时钟信号线CB、第一时钟信号线CK、复位线VEL和第二低电压线VGL2沿着靠近显示区域的方向排列。
第一低电压线VGL设置于驱动电路靠近显示区域的一侧；
如图25所示，第一高电压线VGH与To的第一极So连通，第二高电压线VGH2设置于第一高电压线VGH远离To的一侧；
第一低电压线VGL与Tf的第二极Df连通。
在图21对应的至少一实施例中，所述驱动电路包括第一电路部分和第二电路部分；第一电路部分包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10和第十一晶体管T11，第二电路部分包括输出晶体管To和输出复位晶体管Tf；
第一电路部分设置于第二低电压线VGL2与第二高电压线VGH2之间，第二电路部分设置于第二高电压线VGH2与第一低电压线VGL之间。
如图21-图25所示，T2与T6与VGL2相邻，便于T2的栅极G2与T6的栅极G6与VGL电连接；
T1与VGL2紧邻，以便T1的第一极与VGL2电连接。
在图23中，标号为G1的为T1的栅极，标号为G2的为T2的栅极，标号为G3的为T3的栅极，标号为G4的为T4的栅极，标号为G5的为T5的栅极，标号为G6的为T6的栅极，标号为G7的为T7的栅极，标号为G8的为T8的栅极，标号为G9的为T9的栅极，标号为G10的为T10的栅极，标号为G11的为T11的栅极，标号为Go的为To的栅极，标号为Gf的为Tf的栅极；
在图23中，标号为C2a的为C2的第一极板，在图24中，标号为C2b的为C2的第二极板；
在图23中，标号为C3a的为C3的第一极板，在图24中，标号为C3b的为C3的第二极板；
在图23中，标号为C1a的为C1的第一极板，在图24中，标号为C1b的为C2的第二极板。
如图21-图25所示，T4的栅极G4与VEL电连接，T4的第一极通过过孔与VGH2电连接，T5的第一极通过过孔与VGH2电连接。
在图22中，标号为A1的为T1的有源层图形，标号为A2的为T2的有源层图形，标号为A3的为T3的有源层图形，标号为A4的为T4的有源层图 形，标号为A5的为T5的有源层图形，标号为A6的为T6的有源层图形，标号为A7的为T7的有源层图形，标号为A8的为T8的有源层图形，标号为A9的为T9的有源层图形，标号为A10的为T10的有源层图形，标号为A11的为T11的有源层图形，标号为A0的为第一有源层图形；
第一有源层图形A0包括To的有源层图形和Tf的有源层图形。
图26是本公开图19所示的驱动电路的至少一实施例的布局图。
图26所示的布局图与图21所示的驱动电路的至少一实施例的区别在于：不包含T4。
图27是图26中的有源层的布局图，图28是图26中的第一栅金属层的布局图，图29是图26中的第二栅金属层的布局图，图30是图26中的源漏金属层的布局图。
本公开实施例所述的显示面板，包括上述的驱动电路；所述显示面板还包括显示驱动芯片；
第一低电压输入端与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第三低电压输入端与第三低电压线电连接，第一低电压线、第二低电压线、第三低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号，为第三低电压线提供第三低电压信号；或者，
第一低电压输入端与第一低电压线电连接，第二低电压输入端和第三低电压输入端都与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
第一低电压输入端和第二低电压输入端都与第一低电压线电连接，第三低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
第一低电压输入端和第三低电压输入端都与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压 线提供第一低电压信号，为第二低电压线提供第二低电压信号。
如图31所示，所述显示面板包括显示驱动芯片320；
第一低电压输入端VL1与第一低电压线Ld1电连接，第二低电压输入端VL2与第二低电压线Ld2电连接，第三低电压输入端VL3与第三低电压线Ld3电连接，第一低电压线Ld1与所述显示驱动芯片320的第一引脚P1电连接，第二低电压线Ld2与所述显示驱动芯片320的第二引脚P2电连接，第三低电压线Ld3与所述显示驱动芯片320的第三引脚P3电连接；
所述显示驱动芯片320用于为第一低电压线Ld1提供第一低电压信号，为第二低电压线Ld2提供第二低电压信号，为第三低电压线Ld3提供第三低电压信号。
如图32所示，所述显示面板包括显示驱动芯片320；
第一低电压输入端VL1与第一低电压线Ld1电连接，第二低电压输入端VL2和第三低电压输入端VL3都与第二低电压线Ld2电连接；
第一低电压线Ld1与所述显示驱动芯片320的第一引脚P1电连接，第二低电压线Ld2与所述显示驱动芯片320的第二引脚P2电连接；
所述显示驱动芯片320用于为第一低电压线Ld1提供第一低电压信号，为第二低电压线Ld2提供第二低电压信号。
如图33所示，所述显示面板包括显示驱动芯片320；
第一低电压输入端VL1和第二低电压输入端VL2都与第一低电压线Ld1电连接，第三低电压输入端VL3与第二低电压线Ld2电连接；
第一低电压线Ld1与所述显示驱动芯片320的第一引脚P1电连接，第二低电压线Ld2与所述显示驱动芯片320的第二引脚P2电连接；
所述显示驱动芯片320用于为第一低电压线Ld1提供第一低电压信号，为第二低电压线Ld2提供第二低电压信号。
如图34所示，所述显示面板包括显示驱动芯片320；
第一低电压输入端VL1和第三低电压输入端VL3都与第一低电压线Ld1电连接，第二低电压输入端VL2与第二低电压线Ld2电连接；
第一低电压线Ld1与所述显示驱动芯片320的第一引脚P1电连接，第二低电压线Ld2与所述显示驱动芯片320的第二引脚P2电连接；
所述显示驱动芯片320用于为第一低电压线Ld1提供第一低电压信号，为第二低电压线Ld2提供第二低电压信号。
本公开实施例所述的显示面板包括上述的驱动电路；所述显示面板还包括显示驱动芯片；
第一高电压输入端与第一高电压线电连接，第二高电压输入端与第二高电压线电连接；所述第一高电压线、所述第二高电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一高电压线提供第一高电压信号，所述显示驱动芯片用于为第二高电压线提供第二高电压信号。
如图35所示，所述显示面板包括显示驱动芯片320；
第一低电压输入端VL1和第三低电压输入端VL3都与第一低电压线Ld1电连接，第二低电压输入端VL2与第二低电压线Ld2电连接；
第一低电压线Ld1与所述显示驱动芯片320的第一引脚P1电连接，第二低电压线Ld2与所述显示驱动芯片320的第二引脚P2电连接；
所述显示驱动芯片320用于为第一低电压线Ld1提供第一低电压信号，为第二低电压线Ld2提供第二低电压信号。
本公开实施例所述的显示装置包括上述的驱动电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (23)

  1. 一种驱动电路，包括第一节点控制电路、第二节点控制电路和第一输出电路；
    所述第二节点控制电路分别与第一低电压输入端、第一节点和第二节点电连接，用于在所述第一低电压输入端提供的低电压信号的控制下，控制所述第一节点与所述第二节点之间连通；
    所述第一节点控制电路分别与第二低电压输入端、第一时钟信号线和第一节点电连接，用于在所述第一时钟信号线提供的第一时钟信号的控制下，控制所述第一节点与所述第二低电压输入端电连接；
    所述第一输出电路分别与下拉节点、驱动信号输出端和第三低电压输入端电连接，用于在所述下拉节点的电位的控制下，控制所述驱动信号输出端与所述第三低电压输入端之间连通；
    所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少两个互不相同。
  2. 如权利要求1所述的驱动电路，其中，还包括第二输出电路和第四节点控制电路；
    所述第二输出电路分别与上拉节点、第一高电压输入端和驱动信号输出端电连接，用于在所述上拉节点的电位的控制下，控制所述第一高电压输入端与所述驱动信号输出端之间连通；
    所述第四节点控制电路分别与第一节点、第四节点和第四高电压输入端电连接，用于在所述第一节点的电位的控制下，控制所述第四节点与所述第四高电压输入端之间连通；
    所述第一高电压输入端与所述第四高电压输入端不同。
  3. 如权利要求2所述的驱动电路，其中，还包括第三节点复位电路；
    所述第三节点复位电路分别与复位线、第三高电压输入端和所述第三节点电连接，用于在所述复位线提供的复位信号的控制下，控制所述第三高电压输入端与所述第三节点之间连通；
    所述第三高电压输入端与所述第一高电压输入端、所述第四高电压输入 端中的至少一个不同。
  4. 如权利要求2所述的驱动电路，其中，还包括上拉节点控制电路；
    所述上拉节点控制电路分别与第三节点、第二高电压输入端和所述上拉节点电连接，用于在所述第三节点的电位的控制下，控制所述第二高电压输入端与所述上拉节点之间连通；
    所述第二高电压输入端与第一高电压输入端、第四高电压输入端中的至少一个不相同。
  5. 如权利要求3所述的驱动电路，其中，还包括上拉节点控制电路；
    所述上拉节点控制电路分别与第三节点、第二高电压输入端和所述上拉节点电连接，用于在所述第三节点的电位的控制下，控制所述第二高电压输入端与所述上拉节点之间连通；
    所述第二高电压输入端与所述第三高电压输入端不同。
  6. 如权利要求1至5中任一权利要求所述的驱动电路，其中，还包括下拉节点控制电路；
    所述下拉节点控制电路分别与第四低电压输入端、第三节点和下拉节点电连接，用于在所述第四低电压输入端提供的低电压信号的控制下，控制所述第三节点与所述下拉节点之间连通；
    所述第四低电压输入端与第一低电压输入端、第二低电压输入端、第三低电压输入端中的至少一个不同。
  7. 如权利要求2至5中任一权利要求所述的驱动电路，其中，还包括第五节点控制电路和上拉节点控制电路；
    所述第五节点控制电路分别与第二节点、第五节点和第二时钟信号线电连接，用于在所述第二节点的电位的控制下，控制所述第二时钟信号线与所述第五节点之间连通，并根据所述第二节点的电位控制所述第五节点的电位；
    所述上拉节点控制电路还分别与第五节点、第二时钟信号线和上拉节点电连接，用于在所述第二时钟信号线提供的第二时钟信号的控制下，控制所述第五节点与所述上拉节点之间连通，并用于维持所述上拉节点的电位。
  8. 如权利要求4所述的驱动电路，其中，所述驱动电路还包括第三节点控制电路；
    所述第三节点控制电路分别与起始电压端、第一时钟信号线和第三节点电连接，用于在所述第一时钟信号线提供的第一时钟信号的控制下，控制所述起始电压端与所述第三节点之间连通；
    所述第一节点控制电路还分别与第三节点、第一节点和第一时钟信号线电连接，用于在所述第三节点的电位的控制下，控制所述第一节点与所述第一时钟信号线之间连通；
    所述第四节点控制电路还分别与下拉节点和第二时钟信号线电连接，用于在在所述下拉节点的电位的控制下，控制所述第四节点与所述第二时钟信号线之间连通，并根据所述下拉节点的电位控制所述第四节点的电位。
  9. 如权利要求1所述的驱动电路，其中，所述第一节点控制电路包括第一晶体管，所述第二节点控制电路包括第二晶体管；
    所述第一晶体管的控制极与第一时钟信号线电连接，所述第一晶体管的第一极与第二低电压输入端电连接，所述第一晶体管的第二极与第一节点电连接；
    所述第二晶体管的控制极与第一低电压输入端电连接，所述第二晶体管的第一极与第一节点电连接，所述第二晶体管的第二极与第二节点电连接；
    所述第一输出电路包括输出复位晶体管，所述输出复位晶体管的控制极与所述下拉节点电连接，所述输出复位晶体管的第一极与驱动信号输出端电连接，所述输出复位晶体管的第二极与第三低电压输入端电连接。
  10. 如权利要求4或5所述的驱动电路，其中，所述第二输出电路包括输出晶体管，所述上拉节点控制电路包括第三晶体管和第一电容；
    所述输出晶体管的控制极与所述上拉节点电连接，所述输出晶体管的第一极与第一高电压输入端电连接，所述输出晶体管的第二极与所述驱动信号输出端电连接；
    所述第三晶体管的控制极与第三节点电连接，所述第三晶体管的第一极与第二高电压输入端电连接，所述第三晶体管的第二极与上拉节点电连接；
    所述第一电容的第一极板与上拉节点电连接，所述第一电容的第二极板与所述第一高电压输入端电连接。
  11. 如权利要求3所述的驱动电路，其中，所述第三节点复位电路包括 第四晶体管；
    所述第四晶体管的控制极与所述复位线电连接，所述第四晶体管的第一极与第三高电压输入端电连接，所述第四晶体管的第二极与第三节点电连接。
  12. 如权利要求2所述的驱动电路，其中，所述第四节点控制电路包括第五晶体管；
    所述第五晶体管的控制极与第一节点电连接，所述第五晶体管的第一极与第四高电压输入端电连接，所述第五晶体管的第二极与第四节点电连接。
  13. 如权利要求6所述的驱动电路，其中，所述下拉节点控制电路包括第六晶体管；
    所述第六晶体管的控制极与第四低电压输入端电连接，所述第六晶体管的第一极与第三节点电连接，所述第六晶体管的第二极与下拉节点电连接。
  14. 如权利要求7所述的驱动电路，其中，所述第五节点控制电路包括第七晶体管和第二电容；所述上拉节点控制电路还包括第八晶体管；
    所述第七晶体管的控制极与所述第二节点电连接，所述第七晶体管的第一极与第二时钟信号线电连接，所述第七晶体管的第二极与第五节点电连接；
    所述第二电容的第一极板与第二节点电连接，所述第二电容的第二极板与第五节点电连接；
    所述第八晶体管的控制极与第二时钟信号线电连接，所述第八晶体管的第一极与第五节点电连接，所述第八晶体管的第二极与上拉节点电连接。
  15. 如权利要求8所述的驱动电路，其中，第一节点控制电路还包括第九晶体管；
    所述第九晶体管的控制极与所述第三节点电连接，所述第九晶体管的第一极与所述第一时钟信号线电连接，所述第九晶体管的第二极与第一节点电连接；
    所述第四节点控制电路还包括第十晶体管和第三电容；
    所述第十晶体管的控制极与下拉节点电连接，所述第十晶体管的第一极与第二时钟信号线电连接，所述第十晶体管的第二极与第四节点电连接；
    第三电容的第一极板与所述下拉节点电连接，第三电容的第二极板与第四节点电连接；
    所述第三节点控制电路包括第十一晶体管；
    所述第十一晶体管的控制极与所述第一时钟信号线电连接，所述第十一晶体管的第一极与起始电压端电连接，所述第十一晶体管的第二极与第三节点电连接。
  16. 一种驱动电路，包括第一晶体管、第二晶体管、输出复位晶体管和第六晶体管；
    所述第一晶体管的控制极与第一时钟信号线电连接，所述第一晶体管的第一极与第二低电压输入端电连接，所述第一晶体管的第二极与第一节点电连接；
    所述第二晶体管的控制极与第一低电压输入端电连接，所述第二晶体管的第一极与第一节点电连接，所述第二晶体管的第二极与第二节点电连接；
    所述第一输出电路包括输出复位晶体管，所述输出复位晶体管的控制极与所述下拉节点电连接，所述输出复位晶体管的第一极与驱动信号输出端电连接，所述输出复位晶体管的第二极与第三低电压输入端电连接；
    所述第六晶体管的控制极与第四低电压输入端电连接，所述第六晶体管的第一极与第三节点电连接，所述第六晶体管的第二极与下拉节点电连接；
    所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端和所述低电压输入端不完全相同。
  17. 一种驱动电路，包括输出晶体管、第三晶体管、第四晶体管和第五晶体管；
    所述输出晶体管的控制极与所述上拉节点电连接，所述输出晶体管的第一极与第一高电压输入端电连接，所述输出晶体管的第二极与所述驱动信号输出端电连接；
    所述第三晶体管的控制极与第三节点电连接，所述第三晶体管的第一极与第二高电压输入端电连接，所述第三晶体管的第二极与上拉节点电连接；
    所述第四晶体管的控制极与所述复位线电连接，所述第四晶体管的第一极与第三高电压输入端电连接，所述第四晶体管的第二极与第三节点电连接；
    所述第五晶体管的控制极与第一节点电连接，所述第五晶体管的第一极与第四高电压输入端电连接，所述第五晶体管的第二极与第四节点电连接；
    所述第一高电压输入端、所述第二高电压输入端、所述第三高电压输入端和所述第四高电压输入端不完全相同。
  18. 一种显示面板，包括如权利要求1至15中任一权利要求所述的驱动电路；所述显示面板还包括显示驱动芯片；
    第一低电压输入端与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第三低电压输入端与第三低电压线电连接，第一低电压线、第二低电压线、第三低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号，为第三低电压线提供第三低电压信号；或者，
    第一低电压输入端与第一低电压线电连接，第二低电压输入端和第三低电压输入端都与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
    第一低电压输入端和第二低电压输入端都与第一低电压线电连接，第三低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
    第一低电压输入端和第三低电压输入端都与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号。
  19. 一种显示面板，包括如权利要求4至15中任一权利要求所述的驱动电路；所述显示面板还包括显示驱动芯片；
    第一高电压输入端与第一高电压线电连接，第二高电压输入端与第二高电压线电连接；所述第一高电压线、所述第二高电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一高电压线提供第一高电压信号，所述显示驱动芯片用于为第二高电压线提供第二高电压信号。
  20. 一种显示基板，包括衬底基板和设置于衬底基板上的如权利要求1至17中任一权利要求所述的驱动电路。
  21. 如权利要求20所述的显示基板，其中，所述驱动电路包括第一低电压线、第二低电压线、第一高电压线、第二高电压线、第一节点控制电路、第二节点控制电路、第一输出电路、第二输出电路、上拉节点控制电路、第四节点控制电路、下拉节点控制电路、第五节点控制电路和第三节点控制电路；
    所述第二低电压线设置于所述驱动电路远离显示区域的一侧，所述第一低电压线设置于所述驱动电路靠近显示区域的一侧；
    所述第一高电压线和所述第二高电压线设置于所述驱动电路包括的第一电路部分和所述驱动电路包括的第二电路部分之间；
    所述第一电路部分包括第一节点控制电路、第二节点控制电路、上拉节点控制电路、第四节点控制电路、下拉节点控制电路、第五节点控制电路和第三节点控制电路，所述第二电路部分包括第一输出电路和第二输出电路；
    所述第一电路部分设置于第二低电压线与第二高电压线之间，所述第二电路部分设置于第一高电压线与第一低电压线之间。
  22. 如权利要求21所述的显示基板，其中，所述驱动电路还包括第三节点复位电路，所述第一电路部分包括所述第三节点复位电路。
  23. 一种显示装置，包括如权利要求1至17中任一权利要求所述的驱动电路。
PCT/CN2022/128669 2022-10-31 2022-10-31 驱动电路、显示面板、显示基板和显示装置 WO2024092417A1 (zh)

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