WO2024092400A1 - 驱动电路、显示面板和显示装置 - Google Patents

驱动电路、显示面板和显示装置 Download PDF

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Publication number
WO2024092400A1
WO2024092400A1 PCT/CN2022/128610 CN2022128610W WO2024092400A1 WO 2024092400 A1 WO2024092400 A1 WO 2024092400A1 CN 2022128610 W CN2022128610 W CN 2022128610W WO 2024092400 A1 WO2024092400 A1 WO 2024092400A1
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WIPO (PCT)
Prior art keywords
node
control
input terminal
low voltage
voltage input
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Application number
PCT/CN2022/128610
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English (en)
French (fr)
Inventor
王本莲
黄耀
张波
郑海
胡明
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280003941.3A priority Critical patent/CN118525322A/zh
Priority to PCT/CN2022/128610 priority patent/WO2024092400A1/zh
Publication of WO2024092400A1 publication Critical patent/WO2024092400A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a display panel and a display device.
  • AMOLED Active-matrix organic light-emitting diode
  • an AMOLED display device generally includes: an AMOLED display panel and a gate drive circuit.
  • the AMOLED display panel includes multiple rows of pixels.
  • the gate drive circuit includes multiple cascaded shift register units. Each shift register unit is coupled to a row of pixels and is used to transmit a gate drive signal to the row of pixels to drive the row of pixels to emit light.
  • the multiple cascaded shift register units can realize a row-by-row scanning drive of multiple rows of pixels, so that the AMOLED display panel displays an image.
  • the related shift register units use the same voltage input terminal, and the potential of each node cannot be flexibly set.
  • an embodiment of the present disclosure provides a driving circuit, including a first output circuit and a first pull-up node control circuit;
  • the first output circuit is electrically connected to the pull-up node, the first high voltage input terminal and the drive signal output terminal respectively, and is used to control the connection between the first high voltage input terminal and the drive signal output terminal under the control of the potential of the pull-up node;
  • the first pull-up node control circuit is electrically connected to the pull-down node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the pull-up node and the second high voltage input terminal under the control of the potential of the pull-down node;
  • the first high voltage input terminal and the second high voltage input terminal are different.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a first pull-down node control circuit
  • the first pull-down node control circuit is electrically connected to the pull-down node, the third high voltage input terminal and the pull-down control terminal respectively, and is used to control the connection between the third high voltage input terminal and the pull-down node under the control of the pull-down control signal provided by the pull-down control terminal;
  • the third high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first node control circuit and a fourth high voltage input terminal;
  • the first node control circuit is electrically connected to the first node, the first control terminal and the fourth high voltage input terminal respectively, and is used to control the connection between the first node and the fourth high voltage input terminal under the control of the potential of the first control terminal;
  • the first control terminal is the first control node or the second control node;
  • the fourth high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second output circuit, a second pull-down node control circuit and a first control node control circuit;
  • the second output circuit is electrically connected to the pull-down node, the drive signal output terminal and the first low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the first low voltage input terminal under the control of the potential of the pull-down node;
  • the second pull-down node control circuit is electrically connected to the third control node, the pull-down node and the second low voltage input terminal respectively, and is used to control the connection between the third control node and the pull-down node under the control of the low voltage signal provided by the second low voltage input terminal;
  • the first control node control circuit is electrically connected to the first clock signal terminal, the third low voltage input terminal and the first control node respectively, and is used to control the first control node to be electrically connected to the third low voltage input terminal under the control of the first clock signal provided by the first clock signal terminal;
  • At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second control node control circuit
  • the second control node control circuit is electrically connected to the fourth low voltage input terminal, the first control node and the second control node respectively, and is used to control the connection between the first control node and the second control node under the control of the low voltage signal provided by the fourth low voltage input terminal.
  • the fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a third pull-down node control circuit
  • the third pull-down node control circuit is electrically connected to the first node and the second clock signal terminal, respectively, and is used to control the on-off between the first node and the second clock signal terminal.
  • the third pull-down node control circuit is also electrically connected to the pull-down node, the second node, the third node, the fifth low voltage input terminal, the first clock signal terminal and the start signal terminal, respectively, and controls the connection between the first node and the second clock signal terminal under the control of the potential of the second node, controls the potential of the second node according to the potential of the first node, controls the connection between the start signal terminal and the third node under the control of the first clock signal provided by the first clock signal terminal, controls the connection between the third node and the second node under the control of the low voltage signal provided by the fifth low voltage input terminal, and controls the connection between the second node and the pull-down node under the control of the potential of the second node.
  • the fifth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.
  • the first output circuit includes a first transistor, the first pull-up node control circuit includes a second transistor, and the first pull-down node control circuit includes a third transistor;
  • the control electrode of the first transistor is electrically connected to the pull-up node, the first electrode of the first transistor is electrically connected to the first high voltage input terminal, and the second electrode of the first transistor is electrically connected to the drive signal output terminal;
  • the control electrode of the second transistor is electrically connected to the pull-down node, the first electrode of the second transistor is electrically connected to the second high voltage input terminal, and the second electrode of the second transistor is electrically connected to the pull-up node;
  • the control electrode of the third transistor is electrically connected to the pull-down control terminal, the first electrode of the third transistor is electrically connected to the third high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-down node;
  • the first high voltage input terminal is a first high voltage terminal
  • the second high voltage input terminal and the third high voltage input terminal are second high voltage terminals
  • the first high voltage input terminal is the second high voltage terminal, and the second high voltage input terminal and the third high voltage input terminal are the first high voltage terminal; or,
  • the first high voltage input terminal is a first high voltage terminal
  • the second high voltage input terminal is a second high voltage terminal
  • the third high voltage input terminal is a third high voltage terminal
  • the first high voltage input terminal and the third high voltage input terminal are first high voltage terminals, and the second high voltage input terminal is a second high voltage terminal.
  • the first node control circuit includes a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the first control node, the first electrode of the fourth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the first node;
  • the first high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are first high voltage terminals, and the second high voltage input terminal is a second high voltage terminal; or,
  • the first high voltage input terminal and the fourth high voltage input terminal are first high voltage terminals, and the second high voltage input terminal and the third high voltage input terminal are second high voltage terminals; or,
  • the first high voltage input terminal and the third high voltage input terminal are first high voltage terminals, and the second high voltage input terminal and the fourth high voltage input terminal are second high voltage terminals; or,
  • the first high voltage input terminal is a first high voltage terminal
  • the second high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are second high voltage terminals.
  • the second output circuit includes a fifth transistor
  • the second pull-down node control circuit includes a sixth transistor
  • the first control node control circuit includes a seventh transistor
  • the control electrode of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first low voltage input terminal;
  • the control electrode of the sixth transistor is electrically connected to the second low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third control node, and the second electrode of the sixth transistor is electrically connected to the pull-down node;
  • the control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third low voltage input terminal, and the second electrode of the seventh transistor is electrically connected to the first control node;
  • the first low voltage input terminal and the second low voltage input terminal are first low voltage terminals, and the third low voltage input terminal is a second low voltage terminal; or,
  • the first low voltage input terminal is a first low voltage terminal
  • the second low voltage input terminal and the third low voltage input terminal are second low voltage terminals.
  • the second control node control circuit includes an eighth transistor
  • the control electrode of the eighth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the eighth transistor is electrically connected to the first control node, and the second electrode of the eighth transistor is electrically connected to the second control node;
  • the fourth low voltage input terminal is the first low voltage terminal or the second low voltage terminal.
  • the third pull-down node control circuit includes a first capacitor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor;
  • a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node;
  • the control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second clock signal terminal;
  • the control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the pull-down node, and the second electrode of the tenth transistor is electrically connected to the second node;
  • the control electrode of the eleventh transistor is electrically connected to the fifth low voltage input terminal, the first electrode of the eleventh transistor is electrically connected to the third node, and the second electrode of the eleventh transistor is electrically connected to the second node;
  • the control electrode of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the start signal terminal, and the second electrode of the twelfth transistor is electrically connected to the third node.
  • the fifth low voltage input terminal is the first low voltage terminal or the second low voltage terminal.
  • the driving circuit includes a first control node control circuit, a third control node control circuit and a second pull-up node control circuit;
  • the first control node control circuit is electrically connected to the first control node, and the first control node control circuit is also electrically connected to the third control node, and is used to control the first control node to be connected to the first clock signal terminal under the control of the potential of the third control node;
  • the third control node control circuit is electrically connected to the first clock signal terminal, the start signal terminal and the third control node respectively, and is used to control the start signal terminal to be electrically connected to the third control node under the control of the first clock signal provided by the first clock signal terminal;
  • the second pull-up node control circuit is also electrically connected to the first control node or the second control node, the fourth control node, the second clock signal terminal and the first high voltage input terminal, respectively, and is used to control the potential of the fourth control node according to the potential of the second control node, and under the control of the potential of the first control node or the potential of the second control node, control the connection between the second clock signal terminal and the fourth control node, and under the control of the second clock signal provided by the second clock signal terminal, control the connection between the fourth control node and the pull-up node, and maintain the potential of the pull-up node.
  • the first control node control circuit includes a thirteenth transistor
  • the third control node control circuit includes a fourteenth transistor
  • the second pull-up node control circuit includes a second capacitor, a third capacitor, a fifteenth transistor, and a sixteenth transistor
  • the control electrode of the thirteenth transistor is electrically connected to the third control node, the first electrode of the thirteenth transistor is electrically connected to the first control node, and the second electrode of the thirteenth transistor is electrically connected to the first clock signal terminal;
  • the control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the start signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the third control node;
  • a first end of the second capacitor is electrically connected to the second control node, and a second end of the second capacitor is electrically connected to the fourth control node;
  • a first end of the third capacitor is electrically connected to the pull-up node, and a second end of the third capacitor is electrically connected to the first high voltage input terminal;
  • the control electrode of the fifteenth transistor is electrically connected to the second control node, the first electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the fourth control node;
  • the control electrode of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the fourth control node, and the second electrode of the sixteenth transistor is electrically connected to the pull-up node.
  • an embodiment of the present disclosure further provides a driving circuit, the driving circuit comprising a second output circuit, a second pull-down node control circuit, and a first control node control circuit;
  • the second output circuit is electrically connected to the pull-down node, the drive signal output terminal and the first low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the first low voltage input terminal under the control of the potential of the pull-down node;
  • the second pull-down node control circuit is electrically connected to the third control node, the pull-down node and the second low voltage input terminal respectively, and is used to control the connection between the third control node and the pull-down node under the control of the low voltage signal provided by the second low voltage input terminal;
  • the first control node control circuit is electrically connected to the first clock signal terminal, the third low voltage input terminal and the first control node respectively, and is used to control the first control node to be electrically connected to the third low voltage input terminal under the control of the first clock signal provided by the first clock signal terminal;
  • At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second control node control circuit
  • the second control node control circuit is electrically connected to the fourth low voltage input terminal, the first control node and the second control node respectively, and is used to control the connection between the first control node and the second control node under the control of the low voltage signal provided by the fourth low voltage input terminal;
  • the fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a third pull-down node control circuit
  • the third pull-down node control circuit is electrically connected to the first node and the second clock signal terminal respectively, and is used to control the on-off between the first node and the second clock signal terminal;
  • the third pull-down node control circuit is also electrically connected to the second node, the third node, the fifth low voltage input terminal, the first clock signal terminal and the start signal terminal respectively, and controls the first node to be connected to the second clock signal terminal under the control of the potential of the second node, controls the potential of the second node according to the potential of the first node, controls the start signal terminal to be connected to the third node under the control of the first clock signal provided by the first clock signal terminal, controls the third node to be connected to the second node under the control of the low voltage signal provided by the fifth low voltage input terminal, and controls the second node to be connected to the pull-down node under the control of the potential of the second node;
  • the fifth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal, and the fourth low voltage input terminal.
  • an embodiment of the present disclosure provides a display panel, comprising the above-mentioned driving circuit; the display panel further comprises a display driving chip;
  • the first high voltage input terminal is electrically connected to the first high voltage line
  • the second high voltage input terminal is electrically connected to the second high voltage line
  • the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip
  • the display driver chip is used to provide a first high voltage signal for the first high voltage line
  • the display driver chip is used to provide a second high voltage signal for the second high voltage line.
  • an embodiment of the present disclosure provides a display panel, comprising the above-mentioned driving circuit; the display panel further comprises a display driving chip;
  • the first low voltage input terminal is electrically connected to the first low voltage line
  • the second low voltage input terminal is electrically connected to the second low voltage line
  • the third low voltage input terminal is electrically connected to the third low voltage line
  • the first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line, provide a second low voltage signal for the second low voltage line, and provide a third low voltage signal for the third low voltage line; or
  • the first low voltage input terminal is electrically connected to the first low voltage line
  • the second low voltage input terminal and the third low voltage input terminal are both electrically connected to the second low voltage line
  • the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line;
  • the first low voltage input terminal and the second low voltage input terminal are both electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line; or
  • the first low voltage input terminal and the third low voltage input terminal are both electrically connected to the first low voltage line
  • the second low voltage input terminal is electrically connected to the second low voltage line
  • the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driver chip
  • the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned driving circuit.
  • FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG8 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG9 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG10 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG11 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG12 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG14 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG15 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG19 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG20 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG21 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG22 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG23 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG24 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG25 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG26 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG27 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG28 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG29 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG30 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG31 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG32 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG33 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG34 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG35 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 36 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the gate electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the driving circuit described in the embodiment of the present disclosure includes a first output circuit 11 and a first pull-up node control circuit 12 ;
  • the first output circuit 11 is electrically connected to the pull-up node PU, the first high voltage input terminal VH1 and the drive signal output terminal O1 respectively, and is used to control the connection between the first high voltage input terminal VH1 and the drive signal output terminal O1 under the control of the potential of the pull-up node PU;
  • the first pull-up node control circuit 12 is electrically connected to the pull-down node PD, the second high voltage input terminal VH2 and the pull-up node PU respectively, and is used to control the connection between the pull-up node PU and the second high voltage input terminal VH2 under the control of the potential of the pull-down node PD;
  • the first high voltage input terminal VH1 and the second high voltage input terminal VH2 are different.
  • the driving circuit described in the embodiment of the present disclosure adopts two high voltage input terminals to flexibly control the potential of each node.
  • two high voltage input terminals being different may mean that voltage values of high voltage signals respectively provided by the two high voltage input terminals are different.
  • the first high voltage input terminal VH1 electrically connected to the first output circuit 11 and the second high voltage input terminal VH2 electrically connected to the first pull-up node control circuit 12 are different.
  • the voltage value of the high voltage signal provided by the first high voltage input terminal can be set to be smaller than the voltage value of the high voltage signal provided by the second high voltage input terminal, so that when the transistor included in the first pull-up node control circuit 12 is turned on, the transistor included in the first output circuit 11 can be better turned off;
  • the voltage value of the high voltage signal provided by the first high voltage input terminal can be set to be greater than the voltage value of the high voltage signal provided by the second high voltage input terminal, so that when the transistor included in the first pull-up node control circuit 12 is turned on, the transistor included in the first output circuit 11 can be better turned off;
  • VH1 may provide a first high voltage signal VGH, and VH2 may provide a second high voltage signal VGH2; or VH1 may provide a second high voltage signal VGH2, and VH2 may provide a first high voltage signal VGH; but the present invention is not limited thereto.
  • the voltage value of the high voltage signal provided by each high voltage input terminal can be a positive value; the voltage value of the first high voltage signal VGH can be greater than the voltage value of the second high voltage signal VGH2, or the voltage value of the first high voltage signal VGH can be less than the voltage value of the second high voltage signal VGH2.
  • the voltage value of the first high voltage signal VGH may be greater than or equal to 7V and less than or equal to 12V.
  • the voltage value of VGH may be about 9.5V.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a first pull-down node control circuit 21 ;
  • the first pull-down node control circuit 21 is electrically connected to the pull-down node PD, the third high voltage input terminal VH3 and the pull-down control terminal VEL respectively, and is used to control the connection between the third high voltage input terminal VH3 and the pull-down node PD under the control of the pull-down control signal provided by the pull-down control terminal VEL;
  • the third high voltage input terminal VH3 is different from at least one of the first high voltage input terminal VH1 and the second high voltage input terminal VH2.
  • the driving circuit may further include a first pull-down node control circuit 21, which, under the control of a pull-down control signal, controls the connection between the third high voltage input terminal VH3 and the pull-down node PD, and the third high voltage input terminal VH3 is different from the first high voltage input terminal VH1; and/or the third high voltage input terminal VH3 is different from the second high voltage input terminal VH2.
  • a first pull-down node control circuit 21 which, under the control of a pull-down control signal, controls the connection between the third high voltage input terminal VH3 and the pull-down node PD, and the third high voltage input terminal VH3 is different from the first high voltage input terminal VH1; and/or the third high voltage input terminal VH3 is different from the second high voltage input terminal VH2.
  • the pull-down control terminal VEL may write the high voltage signal provided by the third high voltage input terminal VH3 into the pull-down node PD before normal display, but the present invention is not limited thereto.
  • the third high voltage input terminal VH3 can provide the first high voltage signal VGH or the second high voltage signal VGH2 , but is not limited thereto.
  • the driving circuit further includes a first node control circuit and a fourth high voltage input terminal;
  • the first node control circuit is electrically connected to the first node, the first control terminal and the fourth high voltage input terminal respectively, and is used to control the connection between the first node and the fourth high voltage input terminal under the control of the potential of the first control terminal;
  • the first control terminal is the first control node or the second control node;
  • the fourth high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.
  • the first node control circuit can be used to control the potential of the first node, and the fourth high voltage input terminal electrically connected to the first node control circuit can be different from at least one of the first high voltage input terminal, the second high voltage input terminal, and the third high voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first node control circuit 31 and a fourth high voltage input terminal VH4;
  • the first node control circuit 31 is electrically connected to the first node N1, the first control node Ct1 and the fourth high voltage input terminal VH4 respectively, and is used to control the connection between the first node N1 and the fourth high voltage input terminal VH4 under the control of the potential of the first control node Ct1.
  • the fourth high voltage input terminal VH4 can provide the first high voltage signal VGH or the second high voltage signal VGH2 , but is not limited thereto.
  • the first high voltage input terminal VH1, the second high voltage input terminal VH2, the third high voltage input terminal VH3 and the fourth high voltage input terminal VH4 are not completely the same, specifically as follows:
  • VH1 and VH2 are not identical; or,
  • VH1 and VH3 are not identical; or,
  • VH1 and VH4 are not identical; or,
  • VH2 and VH3 are not identical; or,
  • VH2 and VH4 are not identical; or,
  • VH3 and VH4 are not identical; or,
  • VH1, VH2 and VH3 are different from each other; or,
  • VH1, VH2 and VH4 are different from each other; or,
  • VH1, VH3 and VH4 are different from each other; or,
  • VH2, VH3 and VH4 are different from each other; or,
  • VH1, VH2, VH3 and VH4 are different from each other.
  • the driving circuit further includes a second output circuit, a second pull-down node control circuit and a first control node control circuit;
  • the second output circuit is electrically connected to the pull-down node, the drive signal output terminal and the first low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the first low voltage input terminal under the control of the potential of the pull-down node;
  • the second pull-down node control circuit is electrically connected to the third control node, the pull-down node and the second low voltage input terminal respectively, and is used to control the connection between the third control node and the pull-down node under the control of the low voltage signal provided by the second low voltage input terminal;
  • the first control node control circuit is electrically connected to the first clock signal terminal, the third low voltage input terminal and the first control node respectively, and is used to control the first control node to be electrically connected to the third low voltage input terminal under the control of the first clock signal provided by the first clock signal terminal;
  • At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.
  • two low voltage input terminals being different may mean that voltage values of low voltage signals respectively provided by the two low voltage input terminals are different.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a second output circuit 41 , a second pull-down node control circuit 42 and a first control node control circuit 43 ;
  • the second output circuit 41 is electrically connected to the pull-down node PD, the drive signal output terminal O1 and the first low voltage input terminal VL1 respectively, and is used to control the connection between the drive signal output terminal O1 and the first low voltage input terminal VL1 under the control of the potential of the pull-down node PD;
  • the second pull-down node control circuit 42 is electrically connected to the third control node Ct3, the pull-down node PD and the second low voltage input terminal VL2 respectively, and is used to control the connection between the third control node Ct3 and the pull-down node PD under the control of the low voltage signal provided by the second low voltage input terminal VL2;
  • the first control node control circuit 43 is electrically connected to the first clock signal terminal CK, the third low voltage input terminal VL3 and the first control node Ct1 respectively, and is used to control the first control node Ct1 to be electrically connected to the third low voltage input terminal VL3 under the control of the first clock signal provided by the first clock signal terminal CK;
  • At least two of the first low voltage input terminal VL1 , the second low voltage input terminal VL2 , and the third low voltage input terminal VL3 are different from each other.
  • the first low voltage input terminal VL1 provides the first low voltage signal VGL
  • the second low voltage input terminal VL2 provides the first low voltage signal VGL
  • the third low voltage input terminal VL3 provides the second low voltage signal VL2;
  • the first low voltage input terminal VL1 provides the second low voltage signal VGL2
  • the second low voltage input terminal VL2 provides the first low voltage signal VGL
  • the third low voltage input terminal VL3 provides the first low voltage signal VGL
  • the first low voltage input terminal VL1 provides a first low voltage signal VGL
  • the second low voltage input terminal VL2 provides a second low voltage signal VGL2
  • the third low voltage input terminal VL3 provides a second low voltage signal VGL2;
  • the first low voltage input terminal VL1 , the second low voltage input terminal VL2 , and the third low voltage input terminal VL3 may also be the same, but not limited thereto.
  • the voltage value of the low voltage signal provided by each low voltage input terminal can be a negative value; the voltage value of the first low voltage signal VGL can be greater than the voltage value of the second low voltage signal VGL2, or the voltage value of the first low voltage signal VGL can be less than the voltage value of the second low voltage signal VGL2.
  • the voltage value of the first low voltage signal VGL may be greater than or equal to -11V and less than or equal to -6V.
  • the voltage value of VGL may be approximately -8.5V, but is not limited thereto.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second control node control circuit 51 ;
  • the second control node control circuit 51 is electrically connected to the fourth low voltage input terminal VL4, the first control node Ct1 and the second control node Ct2 respectively, and is used to control the connection between the first control node Ct1 and the second control node Ct2 under the control of the low voltage signal provided by the fourth low voltage input terminal VL4.
  • the fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.
  • the fourth low voltage input terminal VL4 can provide the first low voltage signal VGL or the second low voltage signal VGL2 , but is not limited thereto.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a third pull-down node control circuit 61 ;
  • the third pull-down node control circuit 61 is electrically connected to the first node N1 and the second clock signal terminal CB respectively, and is used to control the connection between the first node N1 and the second clock signal terminal CB.
  • the driving circuit may further include a third pull-down node control circuit 61 for controlling the potential of the pull-down node PD.
  • the third pull-down node control circuit 61 is also electrically connected to the pull-down node PD, the second node N2, the third node N3, the fifth low voltage input terminal VL5, the first clock signal terminal CK and the start signal terminal STV, respectively.
  • the first node N1 is controlled to be connected to the second clock signal terminal CB.
  • the potential of the first node N1 is controlled.
  • the start signal terminal STV is controlled to be connected to the third node N3.
  • the third node N3 is controlled to be connected to the second node N2.
  • the second node N2 is controlled to be connected to the pull-down node PD.
  • the fifth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.
  • the fifth low voltage input terminal can provide the first low voltage signal VGL or the second low voltage signal VGL2, but is not limited thereto. In actual operation, the fifth low voltage input terminal can also provide other low voltage signals.
  • VL1, VL2, VL3, VL4 and VL5 are not completely the same; specifically, as follows:
  • VL1 and VL2 are not the same; or,
  • VL1 and VL3 are not the same; or,
  • VL1 and VL4 are not the same; or,
  • VL1 and VL5 are not the same; or,
  • VL2 and VL3 are not the same; or,
  • VL2 and VL4 are not the same; or,
  • VL2 and VL5 are not the same; or,
  • VL3 and VL4 are not the same; or,
  • VL3 and VL5 are not the same; or;
  • VL4 and VL5 are not the same; or;
  • VL1, VL2 and VL3 are different from each other; or;
  • VL1, VL2 and VL4 are different from each other; or,
  • VL1, VL2 and VL5 are different from each other; or,
  • VL1, VL3 and VL4 are different from each other; or,
  • VL1, VL3 and VL5 are different from each other; or,
  • VL1, VL4 and VL5 are different from each other; or,
  • VL2, VL3 and VL4 are different from each other; or,
  • VL2, VL3 and VL5 are different from each other; or,
  • VL2, VL4 and VL5 are different from each other; or;
  • VL1, VL2, VL3 and VL4 are different from each other; or,
  • VL1, VL2, VL3 and VL5 are different from each other; or,
  • VL1, VL3, VL4 and VL5 are different from each other; or,
  • VL2, VL3, VL4 and VL5 are different from each other; or,
  • VL1, VL2, VL3, VL4 and VL5 are different from each other.
  • the first output circuit includes a first transistor, the first pull-up node control circuit includes a second transistor, and the first pull-down node control circuit includes a third transistor;
  • the control electrode of the first transistor is electrically connected to the pull-up node, the first electrode of the first transistor is electrically connected to the first high voltage input terminal, and the second electrode of the first transistor is electrically connected to the drive signal output terminal;
  • the control electrode of the second transistor is electrically connected to the pull-down node, the first electrode of the second transistor is electrically connected to the second high voltage input terminal, and the second electrode of the second transistor is electrically connected to the pull-up node;
  • the control electrode of the third transistor is electrically connected to the pull-down control terminal, the first electrode of the third transistor is electrically connected to the third high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-down node;
  • the first high voltage input terminal is a first high voltage terminal
  • the second high voltage input terminal and the third high voltage input terminal are second high voltage terminals
  • the first high voltage input terminal is the second high voltage terminal, and the second high voltage input terminal and the third high voltage input terminal are the first high voltage terminal; or,
  • the first high voltage input terminal is a first high voltage terminal
  • the second high voltage input terminal is a second high voltage terminal
  • the third high voltage input terminal is a third high voltage terminal
  • the first high voltage input terminal and the third high voltage input terminal are first high voltage terminals, and the second high voltage input terminal is a second high voltage terminal.
  • the first high voltage terminal may be used to provide a first high voltage signal
  • the second high voltage terminal may be used to provide a second high voltage signal
  • the first node control circuit includes a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the first control node, the first electrode of the fourth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the first node;
  • the first high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are first high voltage terminals, and the second high voltage input terminal is a second high voltage terminal; or,
  • the first high voltage input terminal and the fourth high voltage input terminal are first high voltage terminals, and the second high voltage input terminal and the third high voltage input terminal are second high voltage terminals; or,
  • the first high voltage input terminal and the third high voltage input terminal are first high voltage terminals, and the second high voltage input terminal and the fourth high voltage input terminal are second high voltage terminals; or,
  • the first high voltage input terminal is a first high voltage terminal
  • the second high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are second high voltage terminals.
  • the second output circuit includes a fifth transistor
  • the second pull-down node control circuit includes a sixth transistor
  • the first control node control circuit includes a seventh transistor
  • the control electrode of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first low voltage input terminal;
  • the control electrode of the sixth transistor is electrically connected to the second low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third control node, and the second electrode of the sixth transistor is electrically connected to the pull-down node;
  • the control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third low voltage input terminal, and the second electrode of the seventh transistor is electrically connected to the first control node;
  • the first low voltage input terminal and the second low voltage input terminal are first low voltage terminals; the third low voltage input terminal is a second low voltage terminal; or,
  • the first low voltage input terminal is a first low voltage terminal
  • the second low voltage input terminal and the third low voltage input terminal are second low voltage terminals.
  • the first low voltage terminal can be used to provide a first low voltage signal
  • the second low voltage terminal can be used to provide a second low voltage signal
  • the second control node control circuit includes an eighth transistor
  • the control electrode of the eighth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the eighth transistor is electrically connected to the first control node, and the second electrode of the eighth transistor is electrically connected to the second control node;
  • the fourth low voltage input terminal is the first low voltage terminal or the second low voltage terminal.
  • the third pull-down node control circuit includes a first capacitor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor;
  • a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node;
  • the control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second clock signal terminal;
  • the control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the pull-down node, and the second electrode of the tenth transistor is electrically connected to the second node;
  • the control electrode of the eleventh transistor is electrically connected to the fifth low voltage input terminal, the first electrode of the eleventh transistor is electrically connected to the third node, and the second electrode of the eleventh transistor is electrically connected to the second node;
  • the control electrode of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the start signal terminal, and the second electrode of the twelfth transistor is electrically connected to the third node.
  • the fifth low voltage input terminal is the first low voltage terminal or the second low voltage terminal, but is not limited thereto.
  • the driving circuit includes a first control node control circuit, a third control node control circuit and a second pull-up node control circuit;
  • the first control node control circuit is electrically connected to the first control node, and the first control node control circuit is also electrically connected to the third control node, and is used to control the connection between the first control node and the first clock signal terminal under the control of the potential of the third control node;
  • the third control node control circuit is electrically connected to the first clock signal terminal, the start signal terminal and the third control node respectively, and is used to control the start signal terminal to be electrically connected to the third control node under the control of the first clock signal provided by the first clock signal terminal;
  • the second pull-up node control circuit is also electrically connected to the first control node or the second control node, the fourth control node, the second clock signal terminal and the first high voltage input terminal, respectively, and is used to control the potential of the fourth control node according to the potential of the second control node, and control the connection between the second clock signal terminal and the fourth control node under the control of the potential of the first control node or the potential of the second control node, and control the connection between the fourth control node and the pull-up node under the control of the second clock signal provided by the second clock signal terminal, and is used to maintain the potential of the pull-up node.
  • the driving circuit includes a third control node control circuit 72 and a second pull-up node control circuit 73 ;
  • the first control node control circuit 43 is also electrically connected to the third control node Ct3, and is used to control the connection between the first control node Ct1 and the first clock signal terminal CK under the control of the potential of the third control node Ct3;
  • the third control node control circuit 72 is electrically connected to the first clock signal terminal CK, the start signal terminal STV and the third control node Ct3 respectively, and is used to control the start signal terminal STV to be electrically connected to the third control node Ct3 under the control of the first clock signal provided by the first clock signal terminal CK;
  • the second pull-up node control circuit 73 is also electrically connected to the second control node Ct2, the fourth control node Ct4, the second clock signal terminal CB and the first high voltage input terminal VH1, respectively, and is used to control the potential of the fourth control node Ct4 according to the potential of the second control node Ct2, and under the control of the potential of the second control node Ct2, control the connection between the second clock signal terminal CB and the fourth control node Ct4, and under the control of the second clock signal provided by the second clock signal terminal CB, control the connection between the fourth control node Ct4 and the pull-up node PU, and is used to maintain the potential of the pull-up node PU.
  • the first control node control circuit includes a thirteenth transistor
  • the third control node control circuit includes a fourteenth transistor
  • the second pull-up node control circuit includes a second capacitor, a third capacitor, a fifteenth transistor, and a sixteenth transistor
  • the control electrode of the thirteenth transistor is electrically connected to the third control node, the first electrode of the thirteenth transistor is electrically connected to the first control node, and the second electrode of the thirteenth transistor is electrically connected to the first clock signal terminal;
  • the control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the start signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the third control node;
  • a first end of the second capacitor is electrically connected to the second control node, and a second end of the second capacitor is electrically connected to the fourth control node;
  • a first end of the third capacitor is electrically connected to the pull-up node, and a second end of the third capacitor is electrically connected to the first high voltage input terminal;
  • the control electrode of the fifteenth transistor is electrically connected to the second control node, the first electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the fourth control node;
  • the control electrode of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the fourth control node, and the second electrode of the sixteenth transistor is electrically connected to the pull-up node.
  • the first output circuit includes a first transistor T1
  • the first pull-up node control circuit includes a second transistor T2
  • the first pull-down node control circuit includes a third transistor T3;
  • the gate of the first transistor T1 is electrically connected to the pull-up node PU, the source of the first transistor T1 is electrically connected to the first high voltage input terminal VH1, and the drain of the first transistor T1 is electrically connected to the drive signal output terminal O1;
  • the gate of the second transistor T2 is electrically connected to the pull-down node PD, the source of the second transistor T2 is electrically connected to the second high voltage input terminal VH2, and the drain of the second transistor T2 is electrically connected to the pull-up node PU;
  • the gate of the third transistor T3 is electrically connected to the pull-down control terminal VEL, the source of the third transistor T3 is electrically connected to the third high voltage input terminal VH3, and the drain of the third transistor T3 is electrically connected to the pull-down node PD;
  • the first node control circuit includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the first control node Ct1, the source of the fourth transistor T4 is electrically connected to the fourth high voltage input terminal VH4, and the drain of the fourth transistor T4 is electrically connected to the first node N1;
  • the second output circuit includes a fifth transistor T5, the second pull-down node control circuit includes a sixth transistor T6, and the first control node control circuit includes a seventh transistor T7;
  • the gate of the fifth transistor T5 is electrically connected to the pull-down node PD, the source of the fifth transistor T5 is electrically connected to the drive signal output terminal O1, and the drain of the fifth transistor T5 is electrically connected to the first low voltage input terminal VL1;
  • the gate of the sixth transistor T6 is electrically connected to the second low voltage input terminal VL2, the source of the sixth transistor T6 is electrically connected to the third control node Ct3, and the drain of the sixth transistor T6 is electrically connected to the pull-down node PD;
  • the gate of the seventh transistor T7 is electrically connected to the first clock signal terminal CK, the source of the seventh transistor T7 is electrically connected to the third low voltage input terminal VL3, and the drain of the seventh transistor T7 is electrically connected to the first control node Ct1;
  • the second control node control circuit includes an eighth transistor T8;
  • the gate of the eighth transistor T8 is electrically connected to the fourth low voltage input terminal VL4, the source of the eighth transistor T8 is electrically connected to the first control node Ct1, and the drain of the eighth transistor T8 is electrically connected to the second control node Ct2;
  • the third pull-down node control circuit includes a first capacitor C1, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12;
  • a first end of the first capacitor C1 is electrically connected to a first node N1, and a second end of the first capacitor C1 is electrically connected to a second node N2;
  • the gate of the ninth transistor T9 is electrically connected to the second node N2, the source of the ninth transistor T9 is electrically connected to the first node N1, and the drain of the ninth transistor T9 is electrically connected to the second clock signal terminal CB;
  • the gate of the tenth transistor T10 is electrically connected to the second node N2, the source of the tenth transistor T10 is electrically connected to the pull-down node PD, and the drain of the tenth transistor T10 is electrically connected to the second node N2;
  • the gate of the eleventh transistor T11 is electrically connected to the fifth low voltage input terminal VL5, the source of the eleventh transistor T11 is electrically connected to the third node N3, and the drain of the eleventh transistor T11 is electrically connected to the second node N2;
  • the gate of the twelfth transistor T12 is electrically connected to the first clock signal terminal CK, the source of the twelfth transistor T12 is electrically connected to the start signal terminal STV, and the drain of the twelfth transistor T12 is electrically connected to the third node N3;
  • the first control node control circuit includes a thirteenth transistor T13
  • the third control node control circuit includes a fourteenth transistor T14
  • the second pull-up node control circuit includes a second capacitor C2, a third capacitor C3, a fifteenth transistor T15, and a sixteenth transistor T16;
  • the gate of the thirteenth transistor T13 is electrically connected to the third control node Ct3, the source of the thirteenth transistor T13 is electrically connected to the first control node Ct1, and the drain of the thirteenth transistor T13 is electrically connected to the first clock signal terminal CK;
  • the gate of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK, the source of the fourteenth transistor T14 is electrically connected to the start signal terminal STV, and the drain of the fourteenth transistor T14 is electrically connected to the third control node Ct3;
  • a first end of the second capacitor C2 is electrically connected to the second control node Ct2, and a second end of the second capacitor C2 is electrically connected to the fourth control node Ct4;
  • a first end of the third capacitor C3 is electrically connected to the pull-up node PU, and a second end of the third capacitor C3 is electrically connected to the first high voltage input terminal VH1;
  • the gate of the fifteenth transistor T15 is electrically connected to the second control node Ct2, the source of the fifteenth transistor T15 is electrically connected to the second clock signal terminal CB, and the drain of the fifteenth transistor T15 is electrically connected to the fourth control node Ct4;
  • a gate of the sixteenth transistor T16 is electrically connected to the second clock signal terminal CB, a source of the sixteenth transistor T16 is electrically connected to the fourth control node Ct4, and a drain of the sixteenth transistor T16 is electrically connected to the pull-up node PU.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • At least one embodiment of the driving circuit as shown in FIG8 of the present disclosure is working, due to the parasitic capacitance between the data line, the scan line and the light-emitting control line, the data signal on the data line often jumps, so the scan signal and the light-emitting control signal will be coupled and changed due to the change of the data signal, causing brightness deviation problems such as crosstalk. Therefore, at least one embodiment of the driving circuit as shown in FIG8 of the present disclosure sets a diode-connected T10 between PD and N2, which can stabilize the potential of PD at a low level in the operation mode of a charge pump, thereby ensuring the relative stability of the output signal and preventing the occurrence of brightness deviation caused by coupling crosstalk.
  • T8 is connected between the source of T13 and the gate of T4.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a first high voltage signal VGH
  • VL1, VL2, VL3, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a second high voltage signal VGH2
  • VH2 provides a first high voltage signal VGH
  • VH3 provides a first high voltage signal VGH
  • VH4 provides a first high voltage signal VGH
  • VL1, VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a first high voltage signal VGH
  • VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL
  • VL3 provides a second low voltage signal VGL2.
  • the VGL connected to T5 when working, the VGL connected to T5 is only used for output, will not be interfered by other transistors, and the wiring is simple.
  • the voltage value of VGL2 can be set slightly lower than the voltage value of VGL. For example, when the voltage value of VGL is -6V, the voltage value of VGL2 can be -6.5V, but it is not limited thereto.
  • VH1 provides a second high voltage signal VGH2
  • VH2 provides a first high voltage signal VGH
  • VH3 provides a first high voltage signal VGH
  • VH4 provides a first high voltage signal VGH
  • VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL
  • VL3 provides a second low voltage signal VGL2.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a first high voltage signal VGH
  • VL1 provides a second low voltage signal VGL2
  • VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a second high voltage signal VGH2
  • VH2 provides a first high voltage signal VGH
  • VH3 provides a first high voltage signal VGH
  • VH4 provides a first high voltage signal VGH
  • VL1 provides a second low voltage signal VGL2
  • VL2, VL3, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a first high voltage signal VGH
  • VH4 provides a first high voltage signal VGH
  • VL1, VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a first high voltage signal VGH
  • VL1, VL2, VL3, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a first high voltage signal VGH
  • VH4 provides a second high voltage signal VGH2
  • VL1, VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a second high voltage signal VGH2
  • VL1, VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a first high voltage signal VGH1
  • VH4 provides a first high voltage signal VGH
  • VL3 provides a second low voltage signal VGL2
  • VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a first high voltage signal VGH
  • VL3 provides a second low voltage signal VGL2
  • VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a first high voltage signal VGH
  • VH4 provides a second high voltage signal VGH
  • VL3 provides a second low voltage signal VGL2
  • VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a second high voltage signal VGH2
  • VL3 provides a second low voltage signal VGL2
  • VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a first high voltage signal VGH
  • VH4 provides a first high voltage signal VGH
  • VL3 provides a second low voltage signal VGL2
  • VL2 provides a second low voltage signal VGL2
  • VL1, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a first high voltage signal VGH
  • VL3 provides a second low voltage signal VGL2
  • VL2 provides a second low voltage signal VGL2
  • VL1, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a first high voltage signal VGH
  • VH4 provides a second high voltage signal VGH
  • VL3 provides a second low voltage signal VGL2
  • VL2 provides a second low voltage signal VGL2
  • VL1, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a second high voltage signal VGH2
  • VL3 provides a second low voltage signal VGL2
  • VL2 provides a second low voltage signal VGL2
  • VL1, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a first high voltage signal VGH
  • VH4 provides a first high voltage signal VGH
  • VL3 provides a second low voltage signal VGL2
  • VL2 provides a first low voltage signal VGL
  • VL1, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a first high voltage signal VGH
  • VL3 provides a second low voltage signal VGL2
  • VL2 provides a first low voltage signal VGL
  • VL1, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a first high voltage signal VGH
  • VH4 provides a second high voltage signal VGH
  • VL3 provides a second low voltage signal VGL2
  • VL2 provides a first low voltage signal VGL
  • VL1, VL4 and VL5 all provide a first low voltage signal VGL.
  • VH1 provides a first high voltage signal VGH
  • VH2 provides a second high voltage signal VGH2
  • VH3 provides a second high voltage signal VGH2
  • VH4 provides a second high voltage signal VGH2
  • VL3 provides a second low voltage signal VGL2
  • VL2 provides a first low voltage signal VGL
  • VL1, VL4 and VL5 all provide a first low voltage signal VGL.
  • the display panel described in at least one embodiment of the present disclosure includes the above-mentioned driving circuit; the display panel also includes a display driving chip;
  • the first high voltage input terminal is electrically connected to the first high voltage line
  • the second high voltage input terminal is electrically connected to the second high voltage line
  • the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip
  • the display driver chip is used to provide a first high voltage signal for the first high voltage line
  • the display driver chip is used to provide a second high voltage signal for the second high voltage line.
  • the first high voltage input terminal is electrically connected to the first high voltage line
  • the second high voltage input terminal is electrically connected to the second high voltage line
  • the first high voltage line is electrically connected to the first pin of the display driver chip
  • the second high voltage line is electrically connected to the second pin of the display driver chip.
  • the display driver chip provides a first high voltage signal to the first high voltage line through the first pin
  • the display driver chip provides a second high voltage signal to the second high voltage line through the second pin.
  • the display panel includes a display driver chip 320 ;
  • the first high voltage input terminal VH1 is electrically connected to the first high voltage line LH1
  • the second high voltage input terminal VH2 is electrically connected to the second high voltage line LH2;
  • the first high voltage line LH1 is electrically connected to the first pin P1 of the display driver chip 320, and the second high voltage line LH2 is electrically connected to the second pin P2 of the display driver chip 320;
  • the display driver chip 320 is used to provide a first high voltage signal for the first high voltage line LH1 , and the display driver chip 320 is used to provide a second high voltage signal for the second high voltage line LH2 .
  • the driving circuit described in at least one embodiment of the present disclosure includes a second output circuit, a second pull-down node control circuit and a first control node control circuit;
  • the second output circuit is electrically connected to the pull-down node, the drive signal output terminal and the first low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the first low voltage input terminal under the control of the potential of the pull-down node;
  • the second pull-down node control circuit is electrically connected to the third control node, the pull-down node and the second low voltage input terminal respectively, and is used to control the connection between the third control node and the pull-down node under the control of the low voltage signal provided by the second low voltage input terminal;
  • the first control node control circuit is electrically connected to the first clock signal terminal, the third low voltage input terminal and the first control node respectively, and is used to control the first control node to be electrically connected to the third low voltage input terminal under the control of the first clock signal provided by the first clock signal terminal;
  • At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second control node control circuit
  • the second control node control circuit is electrically connected to the fourth low voltage input terminal, the first control node and the second control node respectively, and is used to control the connection between the first control node and the second control node under the control of the low voltage signal provided by the fourth low voltage input terminal;
  • the fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a third pull-down node control circuit
  • the third pull-down node control circuit is electrically connected to the first node and the second clock signal terminal respectively, and is used to control the on-off between the first node and the second clock signal terminal;
  • the third pull-down node control circuit is also electrically connected to the second node, the third node, the fifth low voltage input terminal, the first clock signal terminal and the start signal terminal respectively, and controls the first node to be connected to the second clock signal terminal under the control of the potential of the second node, controls the potential of the second node according to the potential of the first node, controls the start signal terminal to be connected to the third node under the control of the first clock signal provided by the first clock signal terminal, controls the third node to be connected to the second node under the control of the low voltage signal provided by the fifth low voltage input terminal, and controls the second node to be connected to the pull-down node under the control of the potential of the second node;
  • the fifth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal, and the fourth low voltage input terminal.
  • the display panel described in at least one embodiment of the present disclosure includes the above-mentioned driving circuit; the display panel also includes a display driving chip;
  • the first low voltage input terminal is electrically connected to the first low voltage line
  • the second low voltage input terminal is electrically connected to the second low voltage line
  • the third low voltage input terminal is electrically connected to the third low voltage line
  • the first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line, provide a second low voltage signal for the second low voltage line, and provide a third low voltage signal for the third low voltage line; or
  • the first low voltage input terminal is electrically connected to the first low voltage line
  • the second low voltage input terminal and the third low voltage input terminal are both electrically connected to the second low voltage line
  • the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line;
  • the first low voltage input terminal and the second low voltage input terminal are both electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line; or
  • the first low voltage input terminal and the third low voltage input terminal are both electrically connected to the first low voltage line
  • the second low voltage input terminal is electrically connected to the second low voltage line
  • the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driver chip
  • the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line.
  • the display panel includes a display driver chip 320 ;
  • the first low voltage input terminal VL1 is electrically connected to the first low voltage line Ld1
  • the second low voltage input terminal VL2 is electrically connected to the second low voltage line Ld2
  • the third low voltage input terminal VL3 is electrically connected to the third low voltage line Ld3
  • the first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320
  • the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320
  • the third low voltage line Ld3 is electrically connected to the third pin P3 of the display driver chip 320;
  • the display driving chip 320 is used to provide a first low voltage signal for the first low voltage line Ld1 , provide a second low voltage signal for the second low voltage line Ld2 , and provide a third low voltage signal for the third low voltage line Ld3 .
  • the display panel includes a display driver chip 320 ;
  • the first low voltage input terminal VL1 is electrically connected to the first low voltage line Ld1, and the second low voltage input terminal VL2 and the third low voltage input terminal VL3 are both electrically connected to the second low voltage line Ld2;
  • the first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;
  • the display driving chip 320 is used to provide a first low voltage signal for the first low voltage line Ld1 and provide a second low voltage signal for the second low voltage line Ld2.
  • the display panel includes a display driver chip 320 ;
  • the first low voltage input terminal VL1 and the second low voltage input terminal VL2 are both electrically connected to the first low voltage line Ld1, and the third low voltage input terminal VL3 is electrically connected to the second low voltage line Ld2;
  • the first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;
  • the display driving chip 320 is used to provide a first low voltage signal for the first low voltage line Ld1 and provide a second low voltage signal for the second low voltage line Ld2.
  • the display panel includes a display driver chip 320 ;
  • the first low voltage input terminal VL1 and the third low voltage input terminal VL3 are both electrically connected to the first low voltage line Ld1, and the second low voltage input terminal VL2 is electrically connected to the second low voltage line Ld2;
  • the first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320;
  • the display driving chip 320 is used to provide a first low voltage signal for the first low voltage line Ld1 and provide a second low voltage signal for the second low voltage line Ld2.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.
  • the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

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Abstract

提供了一种驱动电路、显示面板和显示装置。驱动电路包括第一输出电路（11）和第一上拉节点控制电路（12）；第一输出电路（11）分别与上拉节点（PU）、第一高电压输入端（VH1）和驱动信号输出端（O1）电连接，用于在上拉节点（PU）的电位的控制下，控制第一高电压输入端（VH1）与驱动信号输出端（O1）之间连通；第一上拉节点控制电路（12）分别与下拉节点（PD）、第二高电压输入端（VH2）和上拉节点（PU）电连接，用于在下拉节点（PD）的电位的控制下，控制上拉节点（PU）与第二高电压输入端（VH2）之间连通；第一高电压输入端（VH1）和第二高电压输入端（VH2）不相同。驱动电路采用至少两个高电压输入端，以能够灵活的控制各节点的电位。

Description

驱动电路、显示面板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、显示面板和显示装置。
背景技术
有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED)显示装置因可弯曲、对比度高和功耗低等优点而被广泛用于各类产品中。
在相关技术中，AMOLED显示装置通常包括：AMOLED显示面板和栅极驱动电路。AMOLED显示面板包括多行像素。栅极驱动电路包括多个级联的移位寄存器单元。每个移位寄存器单元与一行像素耦接，并用于向该一行像素传输栅极驱动信号，以驱动该一行像素发光。由该多个级联的移位寄存器单元可以实现对多行像素的逐行扫描驱动，以使得AMOLED显示面板显示图像。
但是，相关的移位寄存器单元采用相同的电压输入端，无法灵活的设置各节点的电位。
公开内容
在一个方面中，本公开实施例提供一种驱动电路，包括第一输出电路和第一上拉节点控制电路；
所述第一输出电路分别与上拉节点、第一高电压输入端和驱动信号输出端电连接，用于在所述上拉节点的电位的控制下，控制所述第一高电压输入端与所述驱动信号输出端之间连通；
所述第一上拉节点控制电路分别与下拉节点、第二高电压输入端和上拉节点电连接，用于在所述下拉节点的电位的控制下，控制所述上拉节点与所述第二高电压输入端之间连通；
所述第一高电压输入端和所述第二高电压输入端不相同。
可选的，本公开至少一实施例所述的驱动电路还可以包括第一下拉节点控制电路；
所述第一下拉节点控制电路分别与下拉节点、第三高电压输入端和下拉控制端电连接，用于在所述下拉控制端提供的下拉控制信号的控制下，控制所述第三高电压输入端与所述下拉节点之间连通；
所述第三高电压输入端与所述第一高电压输入端、所述第二高电压输入端中至少之一不相同。
可选的，本公开至少一实施例所述的驱动电路还包括第一节点控制电路和第四高电压输入端；
所述第一节点控制电路分别与第一节点、第一控制端和第四高电压输入端电连接，用于在第一控制端的电位的控制下，控制所述第一节点与第四高电压输入端之间连通；所述第一控制端为第一控制节点或第二控制节点；
所述第四高电压输入端与所述第一高电压输入端、所述第二高电压输入端中的至少一个不相同。
可选的，本公开至少一实施例所述的驱动电路还包括第二输出电路、第二下拉节点控制电路和第一控制节点控制电路；
所述第二输出电路分别与下拉节点、所述驱动信号输出端和第一低电压输入端电连接，用于在所述下拉节点的电位的控制下，控制所述驱动信号输出端与所述第一低电压输入端之间连通；
所述第二下拉节点控制电路分别与第三控制节点、下拉节点和第二低电压输入端电连接，用于在所述第二低电压输入端提供的低电压信号的控制下，控制所述第三控制节点与所述下拉节点之间连通；
所述第一控制节点控制电路分别与第一时钟信号端、第三低电压输入端和第一控制节点电连接，用于在所述第一时钟信号端提供的第一时钟信号的控制下，控制所述第一控制节点与所述第三低电压输入端电连接；
所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中至少两个互不相同。
可选的，本公开至少一实施例所述的驱动电路还包括第二控制节点控制电路；
所述第二控制节点控制电路分别与第四低电压输入端、第一控制节点和第二控制节点电连接，用于在所述第四低电压输入端提供的低电压信号的控制下，控制所述第一控制节点和所述第二控制节点之间连通。
可选的，所述第四低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少一个不相同。
可选的，本公开至少一实施例所述的驱动电路还包括第三下拉节点控制电路；
所述第三下拉节点控制电路分别与第一节点和第二时钟信号端电连接，用于控制所述第一节点与所述第二时钟信号端之间的通断。可选的，所述第三下拉节点控制电路还分别与下拉节点、第二节点、第三节点、第五低电压输入端、第一时钟信号端和起始信号端电连接，在第二节点的电位的控制下，控制所述第一节点与所述第二时钟信号端之间连通，根据所述第一节点的电位，控制所述第二节点的电位，在第一时钟信号端提供的第一时钟信号的控制下，控制所述起始信号端与第三节点连通，在所述第五低电压输入端提供的低电压信号的控制下，控制第三节点与第二节点之间连通，在所述第二节点的电位的控制下，控制所述第二节点与下拉节点之间连通。
可选的，所述第五低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少一个不相同。
可选的，所述第一输出电路包括第一晶体管、第一上拉节点控制电路包括第二晶体管，所述第一下拉节点控制电路包括第三晶体管；
所述第一晶体管的控制极与所述上拉节点电连接，所述第一晶体管的第一极与所述第一高电压输入端电连接，所述第一晶体管的第二极与所述驱动信号输出端电连接；
所述第二晶体管的控制极与所述下拉节点电连接，所述第二晶体管的第一极与所述第二高电压输入端电连接，所述第二晶体管的第二极与所述上拉节点电连接；
所述第三晶体管的控制极与所述下拉控制端电连接，所述第三晶体管的第一极与第三高电压输入端电连接，所述第三晶体管的第二极与所述下拉节点电连接；
所述第一高电压输入端为第一高电压端，所述第二高电压输入端和所述第三高电压输入端为第二高电压端；或者，
所述第一高电压输入端为第二高电压端，所述第二高电压输入端和所述第三高电压输入端为第一高电压端；或者，
所述第一高电压输入端为第一高电压端，所述第二高电压输入端为第二高电压端，所述第三高电压输入端为第三高电压端；或者，
所述第一高电压输入端和所述第三高电压输入端为第一高电压端，所述第二高电压输入端为第二高电压端。
可选的，所述第一节点控制电路包括第四晶体管；
所述第四晶体管的控制极与第一控制节点电连接，所述第四晶体管的第一极与第四高电压输入端电连接，所述第四晶体管的第二极与第一节点电连接；
所述第一高电压输入端、所述第三高电压输入端和所述第四高电压输入端为第一高电压端，所述第二高电压输入端为第二高电压端；或者，
所述第一高电压输入端和所述第四高电压输入端为第一高电压端，所述第二高电压输入端和所述第三高电压输入端为第二高电压端；或者，
所述第一高电压输入端和所述第三高电压输入端为第一高电压端，所述第二高电压输入端和所述第四高电压输入端为第二高电压端；或者，
所述第一高电压输入端为第一高电压端，所述第二高电压输入端、所述第三高电压输入端和所述第四高电压输入端为第二高电压端。
可选的，所述第二输出电路包括第五晶体管，所述第二下拉节点控制电路包括第六晶体管，所述第一控制节点控制电路包括第七晶体管；
所述第五晶体管的控制极与下拉节点电连接，所述第五晶体管的第一极与所述驱动信号输出端电连接，所述第五晶体管的第二极与第一低电压输入端电连接；
所述第六晶体管的控制极与所述第二低电压输入端电连接，所述第六晶体管的第一极与第三控制节点电连接，所述第六晶体管的第二极与下拉节点电连接；
所述第七晶体管的控制极与第一时钟信号端电连接，所述第七晶体管的 第一极与第三低电压输入端电连接，所述第七晶体管的第二极与第一控制节点电连接；
所述第一低电压输入端和所述第二低电压输入端为第一低电压端，所述第三低电压输入端为第二低电压端；或者，
所述第一低电压输入端为第一低电压端，所述第二低电压输入端和所述第三低电压输入端为第二低电压端。
可选的，所述第二控制节点控制电路包括第八晶体管；
所述第八晶体管的控制极与第四低电压输入端电连接，所述第八晶体管的第一极与第一控制节点电连接，所述第八晶体管的第二极与第二控制节点电连接；
所述第四低电压输入端为第一低电压端或第二低电压端。
可选的，所述第三下拉节点控制电路包括第一电容、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管；
所述第一电容的第一端与第一节点电连接，所述第一电容的第二端与第二节点电连接；
所述第九晶体管的控制极与第二节点电连接，所述第九晶体管的第一极与第一节点电连接，所述第九晶体管的第二极与第二时钟信号端电连接；
所述第十晶体管的控制极与第二节点电连接，所述第十晶体管的第一极与下拉节点电连接，所述第十晶体管的第二极与第二节点电连接；
所述第十一晶体管的控制极与第五低电压输入端电连接，所述第十一晶体管的第一极与第三节点电连接，所述第十一晶体管的第二极与第二节点电连接；
所述第十二晶体管的控制极与第一时钟信号端电连接，所述第十二晶体管的第一极与起始信号端电连接，所述第十二晶体管的第二极与第三节点电连接。
可选的，所述第五低电压输入端为第一低电压端或第二低电压端。
可选的，所述驱动电路包括第一控制节点控制电路、第三控制节点控制电路和第二上拉节点控制电路；
所述第一控制节点控制电路与第一控制节点电连接，所述第一控制节点 控制电路还与第三控制节点电连接，用于在所述第三控制节点的电位的控制下，控制所述第一控制节点与第一时钟信号端之间连通；
所述第三控制节点控制电路分别与第一时钟信号端、起始信号端和第三控制节点电连接，用于在所述第一时钟信号端提供的第一时钟信号的控制下，控制所述起始信号端与所述第三控制节点电连接；
所述第二上拉节点控制电路还分别与第一控制节点或者第二控制节点、第四控制节点、第二时钟信号端和第一高电压输入端电连接，用于根据第二控制节点的电位控制第四控制节点的电位，在所述第一控制节点的电位或者所述第二控制节点的电位的控制下，控制所述第二时钟信号端与所述第四控制节点之间连通，在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第四控制节点与上拉节点之间连通，并用于维持上拉节点的电位。
可选的，所述第一控制节点控制电路包括第十三晶体管，所述第三控制节点控制电路包括第十四晶体管，所述第二上拉节点控制电路包括第二电容、第三电容、第十五晶体管和第十六晶体管；
所述第十三晶体管的控制极与第三控制节点电连接，所述第十三晶体管的第一极与第一控制节点电连接，所述第十三晶体管的第二极与第一时钟信号端电连接；
所述第十四晶体管的控制极与第一时钟信号端电连接，所述第十四晶体管的第一极与起始信号端电连接，所述第十四晶体管的第二极与第三控制节点电连接；
第二电容的第一端与第二控制节点电连接，第二电容的第二端与第四控制节点电连接；
第三电容的第一端与上拉节点电连接，第三电容的第二端与第一高电压输入端电连接；
所述第十五晶体管的控制极与第二控制节点电连接，所述第十五晶体管的第一极与第二时钟信号端电连接，所述第十五晶体管的第二极与第四控制节点电连接；
所述第十六晶体管的控制极与第二时钟信号端电连接，所述第十六晶体管的第一极与第四控制节点电连接，所述第十六晶体管的第二极与上拉节点 电连接。
在第二个方面中，本公开实施例还提供一种驱动电路，所述驱动电路包括第二输出电路、第二下拉节点控制电路和第一控制节点控制电路；
所述第二输出电路分别与下拉节点、驱动信号输出端和第一低电压输入端电连接，用于在所述下拉节点的电位的控制下，控制所述驱动信号输出端与所述第一低电压输入端之间连通；
所述第二下拉节点控制电路分别与第三控制节点、下拉节点和第二低电压输入端电连接，用于在所述第二低电压输入端提供的低电压信号的控制下，控制所述第三控制节点与所述下拉节点之间连通；
所述第一控制节点控制电路分别与第一时钟信号端、第三低电压输入端和第一控制节点电连接，用于在所述第一时钟信号端提供的第一时钟信号的控制下，控制所述第一控制节点与所述第三低电压输入端电连接；
所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中至少两个互不相同。
可选的，本公开至少一实施例所述的驱动电路还包括第二控制节点控制电路；
所述第二控制节点控制电路分别与第四低电压输入端、第一控制节点和第二控制节点电连接，用于在所述第四低电压输入端提供的低电压信号的控制下，控制所述第一控制节点和所述第二控制节点之间连通；
所述第四低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少一个不相同。
可选的，本公开至少一实施例所述的驱动电路还包括第三下拉节点控制电路；
所述第三下拉节点控制电路分别与第一节点和第二时钟信号端电连接，用于控制所述第一节点与所述第二时钟信号端之间的通断；
所述第三下拉节点控制电路还分别与第二节点、第三节点、第五低电压输入端、第一时钟信号端和起始信号端电连接，在第二节点的电位的控制下，控制所述第一节点与所述第二时钟信号端之间连通，根据所述第一节点的电位，控制所述第二节点的电位，在第一时钟信号端提供的第一时钟信号的控 制下，控制所述起始信号端与第三节点连通，在所述第五低电压输入端提供的低电压信号的控制下，控制第三节点与第二节点之间连通，在所述第二节点的电位的控制下，控制所述第二节点与下拉节点之间连通；
所述第五低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端、所述第四低电压输入端中的至少一个不相同。
在第三个方面中，本公开实施例提供一种显示面板，包括上述的驱动电路；所述显示面板还包括显示驱动芯片；
第一高电压输入端与第一高电压线电连接，第二高电压输入端与第二高电压线电连接；所述第一高电压线、所述第二高电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一高电压线提供第一高电压信号，所述显示驱动芯片用于为第二高电压线提供第二高电压信号。
在第四个方面中，本公开实施例提供一种显示面板，包括上述的驱动电路；所述显示面板还包括显示驱动芯片；
第一低电压输入端与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第三低电压输入端与第三低电压线电连接，第一低电压线、第二低电压线、第三低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号，为第三低电压线提供第三低电压信号；或者，
第一低电压输入端与第一低电压线电连接，第二低电压输入端和第三低电压输入端都与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
第一低电压输入端和第二低电压输入端都与第一低电压线电连接，第三低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
第一低电压输入端和第三低电压输入端都与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压 线提供第一低电压信号，为第二低电压线提供第二低电压信号。
在第五个方面中，本公开实施例提供一种显示装置，包括上述的驱动电路。
附图说明
图1是本公开实施例所述的驱动电路的结构图；
图2是本公开至少一实施例所述的驱动电路的结构图；
图3是本公开至少一实施例所述的驱动电路的结构图；
图4是本公开至少一实施例所述的驱动电路的结构图；
图5是本公开至少一实施例所述的驱动电路的结构图；
图6是本公开至少一实施例所述的驱动电路的结构图；
图7是本公开至少一实施例所述的驱动电路的结构图；
图8是本公开至少一实施例所述的驱动电路的电路图；
图9是本公开至少一实施例所述的驱动电路的电路图；
图10是本公开至少一实施例所述的驱动电路的电路图；
图11是本公开至少一实施例所述的驱动电路的电路图；
图12是本公开至少一实施例所述的驱动电路的电路图；
图13本公开至少一实施例所述的驱动电路的电路图；
图14是本公开至少一实施例所述的驱动电路的电路图；
图15是本公开至少一实施例所述的驱动电路的电路图；
图16是本公开至少一实施例所述的驱动电路的电路图；
图17是本公开至少一实施例所述的驱动电路的电路图；
图18是本公开至少一实施例所述的驱动电路的电路图；
图19是本公开至少一实施例所述的驱动电路的电路图；
图20是本公开至少一实施例所述的驱动电路的电路图；
图21是本公开至少一实施例所述的驱动电路的电路图；
图22是本公开至少一实施例所述的驱动电路的电路图；
图23是本公开至少一实施例所述的驱动电路的电路图；
图24是本公开至少一实施例所述的驱动电路的电路图；
图25是本公开至少一实施例所述的驱动电路的电路图；
图26是本公开至少一实施例所述的驱动电路的电路图；
图27是本公开至少一实施例所述的驱动电路的电路图；
图28是本公开至少一实施例所述的驱动电路的电路图；
图29是本公开至少一实施例所述的驱动电路的电路图；
图30是本公开至少一实施例所述的驱动电路的电路图；
图31是本公开至少一实施例所述的驱动电路的电路图；
图32是本公开至少一实施例所述的显示面板的结构图；
图33是本公开至少一实施例所述的显示面板的结构图；
图34是本公开至少一实施例所述的显示面板的结构图；
图35是本公开至少一实施例所述的显示面板的结构图；
图36是本公开至少一实施例所述的显示面板的结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述栅极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的驱动电路包括第一输出电路11和第一上拉节点控制电路12；
所述第一输出电路11分别与上拉节点PU、第一高电压输入端VH1和驱动信号输出端O1电连接，用于在所述上拉节点PU的电位的控制下，控制所述第一高电压输入端VH1与所述驱动信号输出端O1之间连通；
所述第一上拉节点控制电路12分别与下拉节点PD、第二高电压输入端VH2和上拉节点PU电连接，用于在所述下拉节点PD的电位的控制下，控制所述上拉节点PU与所述第二高电压输入端VH2之间连通；
所述第一高电压输入端VH1和所述第二高电压输入端VH2不相同。
本公开实施例所述的驱动电路采用两个高电压输入端，以能够灵活的控制各节点的电位。
在本公开至少一实施例中，两个高电压输入端不相同指的可以是：该两个高电压输入端分别提供的高电压信号的电压值不同。
在图1所示的驱动电路的至少一实施例中，第一输出电路11电连接的第一高电压输入端VH1和第一上拉节点控制电路12电连接的第二高电压输入端VH2不相同。
在具体实施时，当第一输出电路11包括的晶体管为p型晶体管时，可以将第一高电压输入端提供的高电压信号的电压值设置为小于第二高电压输入端提供的高电压信号的电压值，以使得当所述第一上拉节点控制电路12包括的晶体管导通时，所述第一输出电路11包括的晶体管可以更好的关断；
当第一输出电路11包括的晶体管为n型晶体管时，可以将第一高电压输入端提供的高电压信号的电压值设置为大于第二高电压输入端提供的高电压信号的电压值，以使得当所述第一上拉节点控制电路12包括的晶体管导通时，所述第一输出电路11包括的晶体管可以更好的关断；
但不以此为限。
在本公开至少一实施例中，VH1可以提供第一高电压信号VGH，VH2可以提供第二高电压信号VGH2；或者，VH1可以提供第二高电压信号VGH2，VH2可以提供第一高电压信号VGH；但不以此为限。
在本公开至少一实施例中，各高电压输入端提供的高电压信号的电压值可以为正值；第一高电压信号VGH的电压值可以大于第二高电压信号VGH2的电压值，或者，第一高电压信号VGH的电压值可以小于第二高电压信号VGH2的电压值。
在本公开至少一实施例中，第一高电压信号VGH的电压值可以大于等于7V而小于等于12V，例如，VGH的电压值可以为9.5V左右。
如图2所示，在图1所示的驱动电路的实施例的基础上，本公开至少一实施例所述的驱动电路还包括第一下拉节点控制电路21；
所述第一下拉节点控制电路21分别与下拉节点PD、第三高电压输入端VH3和下拉控制端VEL电连接，用于在所述下拉控制端VEL提供的下拉控制信号的控制下，控制所述第三高电压输入端VH3与所述下拉节点PD之间连通；
所述第三高电压输入端VH3与所述第一高电压输入端VH1、所述第二高电压输入端VH2中至少之一不相同。
在本公开至少一实施例中，所述驱动电路还可以包括第一下拉节点控制电路21，其在下拉控制信号的控制下，控制第三高电压输入端VH3与下拉节点PD之间连通，第三高电压输入端VH3与第一高电压输入端VH1不同；和/或，所述第三高电压输入端VH3与第二高电压输入端VH2不同。
在具体实施时，所述下拉控制端VEL可以在正常显示之前将第三高电压输入端VH3提供的高电压信号写入下拉节点PD，但不以此为限。
在本公开至少一实施例中，第三高电压输入端VH3可以提供第一高电压信号VGH或第二高电压信号VGH2，但不以此为限。
本公开至少一实施例所述的驱动电路还包括第一节点控制电路和第四高电压输入端；
所述第一节点控制电路分别与第一节点、第一控制端和第四高电压输入端电连接，用于在第一控制端的电位的控制下，控制所述第一节点与第四高电压输入端之间连通；所述第一控制端为第一控制节点或第二控制节点；
所述第四高电压输入端与所述第一高电压输入端、所述第二高电压输入端中的至少一个不相同。
在本公开至少一实施例中，所述第一节点控制电路可以用于控制第一节点的电位，所述第一节点控制电路电连接的第四高电压输入端可以与所述第一高电压输入端、所述第二高电压输入端、所述第三高电压输入端中的至少一个不相同。
如图3所示，在图2所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括第一节点控制电路31和第四高电压输 入端VH4；
所述第一节点控制电路31分别与第一节点N1、第一控制节点Ct1和第四高电压输入端VH4电连接，用于在第一控制节点Ct1的电位的控制下，控制所述第一节点N1与第四高电压输入端VH4之间连通。
在图3所示的驱动电路的至少一实施例中，所述第四高电压输入端VH4可以提供第一高电压信号VGH或第二高电压信号VGH2，但不以此为限。
在本公开至少一实施例中，所述第一高电压输入端VH1、所述第二高电压输入端VH2、所述第三高电压输入端VH3和所述第四高电压输入端VH4不完全相同，具体如下：
VH1与VH2不相同；或者，
VH1和VH3不相同；或者，
VH1和VH4不相同；或者，
VH2与VH3不相同；或者，
VH2与VH4不相同；或者，
VH3和VH4不相同；或者，
VH1、VH2和VH3互不相同；或者，
VH1、VH2和VH4互不相同；或者，
VH1、VH3和VH4互不相同；或者，
VH2、VH3和VH4互不相同；或者，
VH1、VH2、VH3和VH4互不相同。
本公开至少一实施例所述的驱动电路还包括第二输出电路、第二下拉节点控制电路和第一控制节点控制电路；
所述第二输出电路分别与下拉节点、所述驱动信号输出端和第一低电压输入端电连接，用于在所述下拉节点的电位的控制下，控制所述驱动信号输出端与所述第一低电压输入端之间连通；
所述第二下拉节点控制电路分别与第三控制节点、下拉节点和第二低电压输入端电连接，用于在所述第二低电压输入端提供的低电压信号的控制下，控制所述第三控制节点与所述下拉节点之间连通；
所述第一控制节点控制电路分别与第一时钟信号端、第三低电压输入端 和第一控制节点电连接，用于在所述第一时钟信号端提供的第一时钟信号的控制下，控制所述第一控制节点与所述第三低电压输入端电连接；
所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中至少两个互不相同。
在本公开至少一实施例中，两个低电压输入端不相同指的可以是：该两个低电压输入端分别提供的低电压信号的电压值不同。
如图4所示，在图3所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括第二输出电路41、第二下拉节点控制电路42和第一控制节点控制电路43；
所述第二输出电路41分别与下拉节点PD、所述驱动信号输出端O1和第一低电压输入端VL1电连接，用于在所述下拉节点PD的电位的控制下，控制所述驱动信号输出端O1与所述第一低电压输入端VL1之间连通；
所述第二下拉节点控制电路42分别与第三控制节点Ct3、下拉节点PD和第二低电压输入端VL2电连接，用于在所述第二低电压输入端VL2提供的低电压信号的控制下，控制所述第三控制节点Ct3与所述下拉节点PD之间连通；
所述第一控制节点控制电路43分别与第一时钟信号端CK、第三低电压输入端VL3和第一控制节点Ct1电连接，用于在所述第一时钟信号端CK提供的第一时钟信号的控制下，控制所述第一控制节点Ct1与所述第三低电压输入端VL3电连接；
所述第一低电压输入端VL1、所述第二低电压输入端VL2、所述第三低电压输入端VL3中至少两个互不相同。
在图4所示的驱动电路的至少一实施例中，第一低电压输入端VL1提供第一低电压信号VGL，第二低电压输入端VL2提供第一低电压信号VGL，第三低电压输入端VL3提供第二低电压信号VL2；或者，
第一低电压输入端VL1提供第二低电压信号VGL2，第二低电压输入端VL2提供第一低电压信号VGL，第三低电压输入端VL3提供第一低电压信号VGL；或者，
第一低电压输入端VL1提供第一低电压信号VGL，第二低电压输入端 VL2提供第二低电压信号VGL2，第三低电压输入端VL3提供第二低电压信号VGL2；
但不以此为限。
在本公开至少一实施例中，所述第一低电压输入端VL1、所述第二低电压输入端VL2和所述第三低电压输入端VL3也可以相同，但不以此为限。
在本公开至少一实施例中，各低电压输入端提供的低电压信号的电压值可以为负值；第一低电压信号VGL的电压值可以大于第二低电压信号VGL2的电压值，或者，第一低电压信号VGL的电压值可以小于第二低电压信号VGL2的电压值。
在本公开至少一实施例中，第一低电压信号VGL的电压值可以大于等于-11V而小于等于-6V，例如，VGL的电压值可以为-8.5V左右，但不以此为限。
如图5所示，在图4所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述驱动电路还包括第二控制节点控制电路51；
所述第二控制节点控制电路51分别与第四低电压输入端VL4、第一控制节点Ct1和第二控制节点Ct2电连接，用于在所述第四低电压输入端VL4提供的低电压信号的控制下，控制所述第一控制节点Ct1和所述第二控制节点Ct2之间连通。
在本公开至少一实施例中，所述第四低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少一个不相同。
在本公开至少一实施例中，所述第四低电压输入端VL4可以提供第一低电压信号VGL或第二低电压信号VGL2，但不以此为限。
如图6所示，在图5所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括第三下拉节点控制电路61；
所述第三下拉节点控制电路61分别与第一节点N1和第二时钟信号端CB电连接，用于控制第一节点N1与所述第二时钟信号端CB之间的通断。
在具体实施时，所述驱动电路还可以包括第三下拉节点控制电路61，用于控制下拉节点PD的电位。
如图6所示，所述第三下拉节点控制电路61还分别与下拉节点PD、第二节点N2、第三节点N3、第五低电压输入端VL5、第一时钟信号端CK和 起始信号端STV电连接，在第二节点N2的电位的控制下，控制所述第一节点N1与所述第二时钟信号端CB之间连通，根据所述第一节点N1的电位，控制所述第二节点N2的电位，在第一时钟信号端CK提供的第一时钟信号的控制下，控制所述起始信号端STV与第三节点N3连通，在所述第五低电压输入端VL5提供的低电压信号的控制下，控制第三节点N3与第二节点N2之间连通，在所述第二节点N2的电位的控制下，控制所述第二节点N2与下拉节点PD之间连通。
在本公开至少一实施例中，所述第五低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少一个不相同。
在本公开至少一实施例中，第五低电压输入端可以提供第一低电压信号VGL或第二低电压信号VGL2，但不以此为限，在实际操作时，所述第五低电压输入端也可以提供其他的低电压信号。
在本公开至少实施例中，VL1、VL2、VL3、VL4和VL5不完全相同；具体如下：
VL1和VL2不相同；或者，
VL1和VL3不相同；或者，
VL1和VL4不相同；或者，
VL1和VL5不相同；或者，
VL2和VL3不相同；或者，
VL2和VL4不相同；或者，
VL2和VL5不相同；或者，
VL3和VL4不相同；或者，
VL3和VL5不相同；或者；
VL4和VL5不相同；或者；
VL1、VL2和VL3互不相同；或者；
VL1、VL2和VL4互不相同；或者，
VL1、VL2和VL5互不相同；或者，
VL1、VL3和VL4互不相同；或者，
VL1、VL3和VL5互不相同；或者，
VL1、VL4和VL5互不相同；或者，
VL2、VL3和VL4互不相同；或者，
VL2、VL3和VL5互不相同；或者，
VL2、VL4和VL5互不相同；或者；
VL1、VL2、VL3和VL4互不相同；或者，
VL1、VL2、VL3和VL5互不相同；或者，
VL1、VL3、VL4和VL5互不相同；或者，
VL2、VL3、VL4和VL5互不相同；或者，
VL1、VL2、VL3、VL4和VL5互不相同。
可选的，所述第一输出电路包括第一晶体管、第一上拉节点控制电路包括第二晶体管，所述第一下拉节点控制电路包括第三晶体管；
所述第一晶体管的控制极与所述上拉节点电连接，所述第一晶体管的第一极与所述第一高电压输入端电连接，所述第一晶体管的第二极与所述驱动信号输出端电连接；
所述第二晶体管的控制极与所述下拉节点电连接，所述第二晶体管的第一极与所述第二高电压输入端电连接，所述第二晶体管的第二极与所述上拉节点电连接；
所述第三晶体管的控制极与所述下拉控制端电连接，所述第三晶体管的第一极与第三高电压输入端电连接，所述第三晶体管的第二极与所述下拉节点电连接；
所述第一高电压输入端为第一高电压端，所述第二高电压输入端和所述第三高电压输入端为第二高电压端；或者，
所述第一高电压输入端为第二高电压端，所述第二高电压输入端和所述第三高电压输入端为第一高电压端；或者，
所述第一高电压输入端为第一高电压端，所述第二高电压输入端为第二高电压端，所述第三高电压输入端为第三高电压端；或者，
所述第一高电压输入端和所述第三高电压输入端为第一高电压端，所述第二高电压输入端为第二高电压端。
在本公开至少一实施例中，第一高电压端可以用于提供第一高电压信号， 第二高电压端可以用于提供第二高电压信号。
可选的，所述第一节点控制电路包括第四晶体管；
所述第四晶体管的控制极与第一控制节点电连接，所述第四晶体管的第一极与第四高电压输入端电连接，所述第四晶体管的第二极与第一节点电连接；
所述第一高电压输入端、所述第三高电压输入端和所述第四高电压输入端为第一高电压端，所述第二高电压输入端为第二高电压端；或者，
所述第一高电压输入端和所述第四高电压输入端为第一高电压端，所述第二高电压输入端和所述第三高电压输入端为第二高电压端；或者，
所述第一高电压输入端和所述第三高电压输入端为第一高电压端，所述第二高电压输入端和所述第四高电压输入端为第二高电压端；或者，
所述第一高电压输入端为第一高电压端，所述第二高电压输入端、所述第三高电压输入端和所述第四高电压输入端为第二高电压端。
可选的，所述第二输出电路包括第五晶体管，所述第二下拉节点控制电路包括第六晶体管，所述第一控制节点控制电路包括第七晶体管；
所述第五晶体管的控制极与下拉节点电连接，所述第五晶体管的第一极与所述驱动信号输出端电连接，所述第五晶体管的第二极与第一低电压输入端电连接；
所述第六晶体管的控制极与所述第二低电压输入端电连接，所述第六晶体管的第一极与第三控制节点电连接，所述第六晶体管的第二极与下拉节点电连接；
所述第七晶体管的控制极与第一时钟信号端电连接，所述第七晶体管的第一极与第三低电压输入端电连接，所述第七晶体管的第二极与第一控制节点电连接；
所述第一低电压输入端和所述第二低电压输入端为第一低电压端；所述第三低电压输入端为第二低电压端；或者，
所述第一低电压输入端为第一低电压端，所述第二低电压输入端和所述第三低电压输入端为第二低电压端。
在本公开至少一实施例中，所述第一低电压端可以用于提供第一低电压 信号，所述第二低电压端可以用于提供第二低电压信号。
可选的，所述第二控制节点控制电路包括第八晶体管；
所述第八晶体管的控制极与第四低电压输入端电连接，所述第八晶体管的第一极与第一控制节点电连接，所述第八晶体管的第二极与第二控制节点电连接；
所述第四低电压输入端为第一低电压端或第二低电压端。
可选的，所述第三下拉节点控制电路包括第一电容、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管；
所述第一电容的第一端与第一节点电连接，所述第一电容的第二端与第二节点电连接；
所述第九晶体管的控制极与第二节点电连接，所述第九晶体管的第一极与第一节点电连接，所述第九晶体管的第二极与第二时钟信号端电连接；
所述第十晶体管的控制极与第二节点电连接，所述第十晶体管的第一极与下拉节点电连接，所述第十晶体管的第二极与第二节点电连接；
所述第十一晶体管的控制极与第五低电压输入端电连接，所述第十一晶体管的第一极与第三节点电连接，所述第十一晶体管的第二极与第二节点电连接；
所述第十二晶体管的控制极与第一时钟信号端电连接，所述第十二晶体管的第一极与起始信号端电连接，所述第十二晶体管的第二极与第三节点电连接。
在本公开至少一实施例中，所述第五低电压输入端为第一低电压端或第二低电压端，但不以此为限。
可选的，所述驱动电路包括第一控制节点控制电路、第三控制节点控制电路和第二上拉节点控制电路；
所述第一控制节点控制电路与第一控制节点电连接，所述第一控制节点控制电路还与第三控制节点电连接，用于在所述第三控制节点的电位的控制下，控制所述第一控制节点与第一时钟信号端之间连通；
所述第三控制节点控制电路分别与第一时钟信号端、起始信号端和第三控制节点电连接，用于在所述第一时钟信号端提供的第一时钟信号的控制下， 控制所述起始信号端与所述第三控制节点电连接；
所述第二上拉节点控制电路还分别与第一控制节点或者第二控制节点、第四控制节点、第二时钟信号端和第一高电压输入端电连接，用于根据第二控制节点的电位控制第四控制节点的电位，在所述第一控制节点的电位或者所述第二控制节点的电位的控制下，控制所述第二时钟信号端与所述第四控制节点之间连通，在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第四控制节点与上拉节点之间连通，并用于维持上拉节点的电位。
在本公开至少一实施例中，如图7所示，在图6所示的驱动电路的至少一实施例的基础上，所述驱动电路包括第三控制节点控制电路72和第二上拉节点控制电路73；
所述第一控制节点控制电路43还与第三控制节点Ct3电连接，用于在所述第三控制节点Ct3的电位的控制下，控制所述第一控制节点Ct1与第一时钟信号端CK之间连通；
所述第三控制节点控制电路72分别与第一时钟信号端CK、起始信号端STV和第三控制节点Ct3电连接，用于在所述第一时钟信号端CK提供的第一时钟信号的控制下，控制所述起始信号端STV与所述第三控制节点Ct3电连接；
所述第二上拉节点控制电路73还分别与第二控制节点Ct2、第四控制节点Ct4、第二时钟信号端CB和第一高电压输入端VH1电连接，用于根据第二控制节点Ct2的电位控制第四控制节点Ct4的电位，在所述第二控制节点Ct2的电位的控制下，控制所述第二时钟信号端CB与所述第四控制节点Ct4之间连通，在所述第二时钟信号端CB提供的第二时钟信号的控制下，控制所述第四控制节点Ct4与上拉节点PU之间连通，并用于维持上拉节点PU的电位。
可选的，所述第一控制节点控制电路包括第十三晶体管，所述第三控制节点控制电路包括第十四晶体管，所述第二上拉节点控制电路包括第二电容、第三电容、第十五晶体管和第十六晶体管；
所述第十三晶体管的控制极与第三控制节点电连接，所述第十三晶体管的第一极与第一控制节点电连接，所述第十三晶体管的第二极与第一时钟信 号端电连接；
所述第十四晶体管的控制极与第一时钟信号端电连接，所述第十四晶体管的第一极与起始信号端电连接，所述第十四晶体管的第二极与第三控制节点电连接；
第二电容的第一端与第二控制节点电连接，第二电容的第二端与第四控制节点电连接；
第三电容的第一端与上拉节点电连接，第三电容的第二端与第一高电压输入端电连接；
所述第十五晶体管的控制极与第二控制节点电连接，所述第十五晶体管的第一极与第二时钟信号端电连接，所述第十五晶体管的第二极与第四控制节点电连接；
所述第十六晶体管的控制极与第二时钟信号端电连接，所述第十六晶体管的第一极与第四控制节点电连接，所述第十六晶体管的第二极与上拉节点电连接。
如图8所示，在图7所示的驱动电路的至少一实施例的基础上，所述第一输出电路包括第一晶体管T1、第一上拉节点控制电路包括第二晶体管T2，所述第一下拉节点控制电路包括第三晶体管T3；
所述第一晶体管T1的栅极与所述上拉节点PU电连接，所述第一晶体管T1的源极与所述第一高电压输入端VH1电连接，所述第一晶体管T1的漏极与所述驱动信号输出端O1电连接；
所述第二晶体管T2的栅极与所述下拉节点PD电连接，所述第二晶体管T2的源极与所述第二高电压输入端VH2电连接，所述第二晶体管T2的漏极与所述上拉节点PU电连接；
所述第三晶体管T3的栅极与所述下拉控制端VEL电连接，所述第三晶体管T3的源极与第三高电压输入端VH3电连接，所述第三晶体管T3的漏极与所述下拉节点PD电连接；
所述第一节点控制电路包括第四晶体管T4；
所述第四晶体管T4的栅极与第一控制节点Ct1电连接，所述第四晶体管T4的源极与第四高电压输入端VH4电连接，所述第四晶体管T4的漏极与第 一节点N1电连接；
所述第二输出电路包括第五晶体管T5，所述第二下拉节点控制电路包括第六晶体管T6，所述第一控制节点控制电路包括第七晶体管T7；
所述第五晶体管T5的栅极与下拉节点PD电连接，所述第五晶体管T5的源极与所述驱动信号输出端O1电连接，所述第五晶体管T5的漏极与第一低电压输入端VL1电连接；
所述第六晶体管T6的栅极与所述第二低电压输入端VL2电连接，所述第六晶体管T6的源极与第三控制节点Ct3电连接，所述第六晶体管T6的漏极与下拉节点PD电连接；
所述第七晶体管T7的栅极与第一时钟信号端CK电连接，所述第七晶体管T7的源极与第三低电压输入端VL3电连接，所述第七晶体管T7的漏极与第一控制节点Ct1电连接；
所述第二控制节点控制电路包括第八晶体管T8；
所述第八晶体管T8的栅极与第四低电压输入端VL4电连接，所述第八晶体管T8的源极与第一控制节点Ct1电连接，所述第八晶体管T8的漏极与第二控制节点Ct2电连接；
所述第三下拉节点控制电路包括第一电容C1、第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12；
所述第一电容C1的第一端与第一节点N1电连接，所述第一电容C1的第二端与第二节点N2电连接；
所述第九晶体管T9的栅极与第二节点N2电连接，所述第九晶体管T9的源极与第一节点N1电连接，所述第九晶体管T9的漏极与第二时钟信号端CB电连接；
所述第十晶体管T10的栅极与第二节点N2电连接，所述第十晶体管T10的源极与下拉节点PD电连接，所述第十晶体管T10的漏极与第二节点N2电连接；
所述第十一晶体管T11的栅极与第五低电压输入端VL5电连接，所述第十一晶体管T11的源极与第三节点N3电连接，所述第十一晶体管T11的漏极与第二节点N2电连接；
所述第十二晶体管T12的栅极与第一时钟信号端CK电连接，所述第十二晶体管T12的源极与起始信号端STV电连接，所述第十二晶体管T12的漏极与第三节点N3电连接；
所述第一控制节点控制电路包括第十三晶体管T13，所述第三控制节点控制电路包括第十四晶体管T14，所述第二上拉节点控制电路包括第二电容C2、第三电容C3、第十五晶体管T15和第十六晶体管T16；
所述第十三晶体管T13的栅极与第三控制节点Ct3电连接，所述第十三晶体管T13的源极与第一控制节点Ct1电连接，所述第十三晶体管T13的漏极与第一时钟信号端CK电连接；
所述第十四晶体管T14的栅极与第一时钟信号端CK电连接，所述第十四晶体管T14的源极与起始信号端STV电连接，所述第十四晶体管T14的漏极与第三控制节点Ct3电连接；
第二电容C2的第一端与第二控制节点Ct2电连接，第二电容C2的第二端与第四控制节点Ct4电连接；
第三电容C3的第一端与上拉节点PU电连接，第三电容C3的第二端与第一高电压输入端VH1电连接；
所述第十五晶体管T15的栅极与第二控制节点Ct2电连接，所述第十五晶体管T15的源极与第二时钟信号端CB电连接，所述第十五晶体管T15的漏极与第四控制节点Ct4电连接；
所述第十六晶体管T16的栅极与第二时钟信号端CB电连接，所述第十六晶体管T16的源极与第四控制节点Ct4电连接，所述第十六晶体管T16的漏极与上拉节点PU电连接。
在图8所示的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
本公开如图8所示的驱动电路的至少一实施例在工作时，由于数据线、扫描线和发光控制线之间存在寄生电容，数据线上的数据信号时常跳动，故扫描信号和发光控制信号会受到数据信号的变化而发生耦合改变，造成诸如串扰的亮度偏差问题，因此本公开如图8所示的驱动电路的至少一实施例在PD和N2之间设置二极管连接型的T10，可以以电荷泵的操作方式将PD的 电位稳定在低电平，从而可以保证输出信号的相对稳定，防止耦合串扰造成的亮度偏差发生等。
本公开图9所示的驱动电路的至少一实施例与本公开图8所示的驱动电路的至少一实施例的区别在于，T8连接于T13的源极与T4的栅极之间。
如图10所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第一高电压信号VGH，VL1、VL2、VL3、VL4和VL5都提供第一低电压信号VGL。
如图11所示，在图8所示的驱动电路的至少一实施例中，VH1提供第二高电压信号VGH2，VH2提供第一高电压信号VGH，VH3提供第一高电压信号VGH，VH4提供第一高电压信号VGH，VL1、VL2、VL3、VL4和VL5都提供第一低电压信号VGL。
如图12所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第一高电压信号VGH，VL1、VL2、VL4和VL5都提供第一低电压信号VGL，VL3提供第二低电压信号VGL2。
本公开图12所示的驱动电路的至少一实施例在工作时，T5接入的VGL仅用于输出，不会受到其他晶体管的干扰，并且布线简单。并且，由于p型晶体管传输低电平有阈值电压损失，因此可以将VGL2的电压值设置的比VGL的电压值稍低一些，例如，当VGL的电压值为-6V时，VGL2的电压值可以为-6.5V，但不以此为限。
如图13所示，在图8所示的驱动电路的至少一实施例中，VH1提供第二高电压信号VGH2，VH2提供第一高电压信号VGH，VH3提供第一高电压信号VGH，VH4提供第一高电压信号VGH，VL1、VL2、VL4和VL5都提供第一低电压信号VGL，VL3提供第二低电压信号VGL2。
如图14所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第一高电压信号VGH，VL1提供第二低电压信号VGL2，VL2、VL3、VL4和VL5都提供第一低电压信号VGL。
如图15所示，在图8所示的驱动电路的至少一实施例中，VH1提供第二高电压信号VGH2，VH2提供第一高电压信号VGH，VH3提供第一高电压信号VGH，VH4提供第一高电压信号VGH，VL1提供第二低电压信号VGL2，VL2、VL3、VL4和VL5都提供第一低电压信号VGL。
如图16所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第一高电压信号VGH，VH4提供第一高电压信号VGH，VL1、VL2、VL3、VL4和VL5都提供第一低电压信号VGL。
如图17所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第一高电压信号VGH，VL1、VL2、VL3、VL4和VL5都提供第一低电压信号VGL。
如图18所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第一高电压信号VGH，VH4提供第二高电压信号VGH2，VL1、VL2、VL3、VL4和VL5都提供第一低电压信号VGL。
如图19所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第二高电压信号VGH2，VL1、VL2、VL3、VL4和VL5都提供第一低电压信号VGL。
如图20所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第一高电压信号VGH1，VH4提供第一高电压信号VGH，VL3提供第二低电压信号VGL2，VL1、VL2、VL4和VL5都提供第一低电压信号VGL。
如图21所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第一高电压信号VGH，VL3提供第二低电压信号VGL2，VL1、VL2、VL4和VL5都提供第一低电压信号VGL。
如图22所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一 高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第一高电压信号VGH，VH4提供第二高电压信号VGH2，VL3提供第二低电压信号VGL2，VL1、VL2、VL4和VL5都提供第一低电压信号VGL。
如图23所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第二高电压信号VGH2，VL3提供第二低电压信号VGL2，VL1、VL2、VL4和VL5都提供第一低电压信号VGL。
如图24所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第一高电压信号VGH，VH4提供第一高电压信号VGH，VL3提供第二低电压信号VGL2，VL2提供第二低电压信号VGL2，VL1、VL4和VL5都提供第一低电压信号VGL。
如图25所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第一高电压信号VGH，VL3提供第二低电压信号VGL2，VL2提供第二低电压信号VGL2，VL1、VL4和VL5都提供第一低电压信号VGL。
如图26所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第一高电压信号VGH，VH4提供第二高电压信号VGH2，VL3提供第二低电压信号VGL2，VL2提供第二低电压信号VGL2，VL1、VL4和VL5都提供第一低电压信号VGL。
如图27所示，在图8所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第二高电压信号VGH2，VL3提供第二低电压信号VGL2，VL2提供第二低电压信号VGL2，VL1、VL4和VL5都提供第一低电压信号VGL。
如图28所示，在图9所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第一高电压 信号VGH，VH4提供第一高电压信号VGH，VL3提供第二低电压信号VGL2，VL2提供第一低电压信号VGL，VL1、VL4和VL5都提供第一低电压信号VGL。
如图29所示，在图9所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第一高电压信号VGH，VL3提供第二低电压信号VGL2，VL2提供第一低电压信号VGL，VL1、VL4和VL5都提供第一低电压信号VGL。
如图30所示，在图9所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第一高电压信号VGH，VH4提供第二高电压信号VGH2，VL3提供第二低电压信号VGL2，VL2提供第一低电压信号VGL，VL1、VL4和VL5都提供第一低电压信号VGL。
如图31所示，在图9所示的驱动电路的至少一实施例中，VH1提供第一高电压信号VGH，VH2提供第二高电压信号VGH2，VH3提供第二高电压信号VGH2，VH4提供第二高电压信号VGH2，VL3提供第二低电压信号VGL2，VL2提供第一低电压信号VGL，VL1、VL4和VL5都提供第一低电压信号VGL。
本公开至少一实施例所述的显示面板包括上述的驱动电路；所述显示面板还包括显示驱动芯片；
第一高电压输入端与第一高电压线电连接，第二高电压输入端与第二高电压线电连接；所述第一高电压线、所述第二高电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一高电压线提供第一高电压信号，所述显示驱动芯片用于为第二高电压线提供第二高电压信号。
在本公开实施例所述的显示面板中，第一高电压输入端与第一高电压线电连接，第二高电压输入端与第二高电压线电连接，第一高电压线与显示驱动芯片的第一引脚电连接，第二高电压线与显示驱动芯片的第二引脚电连接，显示驱动芯片通过第一引脚向所述第一高电压线提供第一高电压信号，显示驱动芯片通过第二引脚向所述所述第二高电压线提供第二高电压信号。
如图32所示，所述显示面板包括显示驱动芯片320；
第一高电压输入端VH1与第一高电压线LH1电连接，第二高电压输入端VH2与第二高电压线LH2电连接；
所述第一高电压线LH1与所述显示驱动芯片320的第一引脚P1电连接，所述第二高电压线LH2与所述显示驱动芯片320的第二引脚P2电连接；
所述显示驱动芯片320用于为第一高电压线LH1提供第一高电压信号，所述显示驱动芯片320用于为第二高电压线LH2提供第二高电压信号。
本公开至少一实施例所述的驱动电路包括第二输出电路、第二下拉节点控制电路和第一控制节点控制电路；
所述第二输出电路分别与下拉节点、驱动信号输出端和第一低电压输入端电连接，用于在所述下拉节点的电位的控制下，控制所述驱动信号输出端与所述第一低电压输入端之间连通；
所述第二下拉节点控制电路分别与第三控制节点、下拉节点和第二低电压输入端电连接，用于在所述第二低电压输入端提供的低电压信号的控制下，控制所述第三控制节点与所述下拉节点之间连通；
所述第一控制节点控制电路分别与第一时钟信号端、第三低电压输入端和第一控制节点电连接，用于在所述第一时钟信号端提供的第一时钟信号的控制下，控制所述第一控制节点与所述第三低电压输入端电连接；
所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中至少两个互不相同。
可选的，本公开至少一实施例所述的驱动电路还包括第二控制节点控制电路；
所述第二控制节点控制电路分别与第四低电压输入端、第一控制节点和第二控制节点电连接，用于在所述第四低电压输入端提供的低电压信号的控制下，控制所述第一控制节点和所述第二控制节点之间连通；
所述第四低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少一个不相同。
可选的，本公开至少一实施例所述的驱动电路还包括第三下拉节点控制电路；
所述第三下拉节点控制电路分别与第一节点和第二时钟信号端电连接，用于控制所述第一节点与所述第二时钟信号端之间的通断；
所述第三下拉节点控制电路还分别与第二节点、第三节点、第五低电压输入端、第一时钟信号端和起始信号端电连接，在第二节点的电位的控制下，控制所述第一节点与所述第二时钟信号端之间连通，根据所述第一节点的电位，控制所述第二节点的电位，在第一时钟信号端提供的第一时钟信号的控制下，控制所述起始信号端与第三节点连通，在所述第五低电压输入端提供的低电压信号的控制下，控制第三节点与第二节点之间连通，在所述第二节点的电位的控制下，控制所述第二节点与下拉节点之间连通；
所述第五低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端、所述第四低电压输入端中的至少一个不相同。
本公开至少一实施例所述的显示面板包括上述的驱动电路；所述显示面板还包括显示驱动芯片；
第一低电压输入端与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第三低电压输入端与第三低电压线电连接，第一低电压线、第二低电压线、第三低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号，为第三低电压线提供第三低电压信号；或者，
第一低电压输入端与第一低电压线电连接，第二低电压输入端和第三低电压输入端都与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
第一低电压输入端和第二低电压输入端都与第一低电压线电连接，第三低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
第一低电压输入端和第三低电压输入端都与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压 线提供第一低电压信号，为第二低电压线提供第二低电压信号。
如图33所示，所述显示面板包括显示驱动芯片320；
第一低电压输入端VL1与第一低电压线Ld1电连接，第二低电压输入端VL2与第二低电压线Ld2电连接，第三低电压输入端VL3与第三低电压线Ld3电连接，第一低电压线Ld1与所述显示驱动芯片320的第一引脚P1电连接，第二低电压线Ld2与所述显示驱动芯片320的第二引脚P2电连接，第三低电压线Ld3与所述显示驱动芯片320的第三引脚P3电连接；
所述显示驱动芯片320用于为第一低电压线Ld1提供第一低电压信号，为第二低电压线Ld2提供第二低电压信号，为第三低电压线Ld3提供第三低电压信号。
如图34所示，所述显示面板包括显示驱动芯片320；
第一低电压输入端VL1与第一低电压线Ld1电连接，第二低电压输入端VL2和第三低电压输入端VL3都与第二低电压线Ld2电连接；
第一低电压线Ld1与所述显示驱动芯片320的第一引脚P1电连接，第二低电压线Ld2与所述显示驱动芯片320的第二引脚P2电连接；
所述显示驱动芯片320用于为第一低电压线Ld1提供第一低电压信号，为第二低电压线Ld2提供第二低电压信号。
如图35所示，所述显示面板包括显示驱动芯片320；
第一低电压输入端VL1和第二低电压输入端VL2都与第一低电压线Ld1电连接，第三低电压输入端VL3与第二低电压线Ld2电连接；
第一低电压线Ld1与所述显示驱动芯片320的第一引脚P1电连接，第二低电压线Ld2与所述显示驱动芯片320的第二引脚P2电连接；
所述显示驱动芯片320用于为第一低电压线Ld1提供第一低电压信号，为第二低电压线Ld2提供第二低电压信号。
如图36所示，所述显示面板包括显示驱动芯片320；
第一低电压输入端VL1和第三低电压输入端VL3都与第一低电压线Ld1电连接，第二低电压输入端VL2与第二低电压线Ld2电连接；
第一低电压线Ld1与所述显示驱动芯片320的第一引脚P1电连接，第二低电压线Ld2与所述显示驱动芯片320的第二引脚P2电连接；
所述显示驱动芯片320用于为第一低电压线Ld1提供第一低电压信号，为第二低电压线Ld2提供第二低电压信号。
本公开实施例所述的显示装置包括上述的驱动电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (23)

  1. 一种驱动电路，包括第一输出电路和第一上拉节点控制电路；
    所述第一输出电路分别与上拉节点、第一高电压输入端和驱动信号输出端电连接，用于在所述上拉节点的电位的控制下，控制所述第一高电压输入端与所述驱动信号输出端之间连通；
    所述第一上拉节点控制电路分别与下拉节点、第二高电压输入端和上拉节点电连接，用于在所述下拉节点的电位的控制下，控制所述上拉节点与所述第二高电压输入端之间连通；
    所述第一高电压输入端和所述第二高电压输入端不相同。
  2. 如权利要求1所述的驱动电路，其中，还包括第一下拉节点控制电路；
    所述第一下拉节点控制电路分别与下拉节点、第三高电压输入端和下拉控制端电连接，用于在所述下拉控制端提供的下拉控制信号的控制下，控制所述第三高电压输入端与所述下拉节点之间连通；
    所述第三高电压输入端与所述第一高电压输入端、所述第二高电压输入端中至少之一不相同。
  3. 如权利要求1所述的驱动电路，其中，还包括第一节点控制电路和第四高电压输入端；
    所述第一节点控制电路分别与第一节点、第一控制端和第四高电压输入端电连接，用于在第一控制端的电位的控制下，控制所述第一节点与第四高电压输入端之间连通；所述第一控制端为第一控制节点或第二控制节点；
    所述第四高电压输入端与所述第一高电压输入端、所述第二高电压输入端中的至少一个不相同。
  4. 如权利要求1所述的驱动电路，其中，还包括第二输出电路、第二下拉节点控制电路和第一控制节点控制电路；
    所述第二输出电路分别与下拉节点、所述驱动信号输出端和第一低电压输入端电连接，用于在所述下拉节点的电位的控制下，控制所述驱动信号输出端与所述第一低电压输入端之间连通；
    所述第二下拉节点控制电路分别与第三控制节点、下拉节点和第二低电 压输入端电连接，用于在所述第二低电压输入端提供的低电压信号的控制下，控制所述第三控制节点与所述下拉节点之间连通；
    所述第一控制节点控制电路分别与第一时钟信号端、第三低电压输入端和第一控制节点电连接，用于在所述第一时钟信号端提供的第一时钟信号的控制下，控制所述第一控制节点与所述第三低电压输入端电连接；
    所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中至少两个互不相同。
  5. 如权利要求4所述的驱动电路，其中，还包括第二控制节点控制电路；
    所述第二控制节点控制电路分别与第四低电压输入端、第一控制节点和第二控制节点电连接，用于在所述第四低电压输入端提供的低电压信号的控制下，控制所述第一控制节点和所述第二控制节点之间连通。
  6. 如权利要求5所述的驱动电路，其中，所述第四低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少一个不相同。
  7. 如权利要求4所述的驱动电路，其中，还包括第三下拉节点控制电路；
    所述第三下拉节点控制电路分别与第一节点和第二时钟信号端电连接，用于控制所述第一节点与所述第二时钟信号端之间的通断。
  8. 如权利要求7所述的驱动电路，其中，所述第三下拉节点控制电路还分别与下拉节点、第二节点、第三节点、第五低电压输入端、第一时钟信号端和起始信号端电连接，在第二节点的电位的控制下，控制所述第一节点与所述第二时钟信号端之间连通，根据所述第一节点的电位，控制所述第二节点的电位，在第一时钟信号端提供的第一时钟信号的控制下，控制所述起始信号端与第三节点连通，在所述第五低电压输入端提供的低电压信号的控制下，控制第三节点与第二节点之间连通，在所述第二节点的电位的控制下，控制所述第二节点与下拉节点之间连通。
  9. 如权利要求8所述的驱动电路，其中，所述第五低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少一个不相同。
  10. 如权利要求3所述的驱动电路，其中，所述第一输出电路包括第一 晶体管、第一上拉节点控制电路包括第二晶体管，所述第一下拉节点控制电路包括第三晶体管；
    所述第一晶体管的控制极与所述上拉节点电连接，所述第一晶体管的第一极与所述第一高电压输入端电连接，所述第一晶体管的第二极与所述驱动信号输出端电连接；
    所述第二晶体管的控制极与所述下拉节点电连接，所述第二晶体管的第一极与所述第二高电压输入端电连接，所述第二晶体管的第二极与所述上拉节点电连接；
    所述第三晶体管的控制极与所述下拉控制端电连接，所述第三晶体管的第一极与第三高电压输入端电连接，所述第三晶体管的第二极与所述下拉节点电连接；
    所述第一高电压输入端为第一高电压端，所述第二高电压输入端和所述第三高电压输入端为第二高电压端；或者，
    所述第一高电压输入端为第二高电压端，所述第二高电压输入端和所述第三高电压输入端为第一高电压端；或者，
    所述第一高电压输入端为第一高电压端，所述第二高电压输入端为第二高电压端，所述第三高电压输入端为第三高电压端；或者，
    所述第一高电压输入端和所述第三高电压输入端为第一高电压端，所述第二高电压输入端为第二高电压端。
  11. 如权利要求10所述的驱动电路，其中，所述第一节点控制电路包括第四晶体管；
    所述第四晶体管的控制极与第一控制节点电连接，所述第四晶体管的第一极与第四高电压输入端电连接，所述第四晶体管的第二极与第一节点电连接；
    所述第一高电压输入端、所述第三高电压输入端和所述第四高电压输入端为第一高电压端，所述第二高电压输入端为第二高电压端；或者，
    所述第一高电压输入端和所述第四高电压输入端为第一高电压端，所述第二高电压输入端和所述第三高电压输入端为第二高电压端；或者，
    所述第一高电压输入端和所述第三高电压输入端为第一高电压端，所述 第二高电压输入端和所述第四高电压输入端为第二高电压端；或者，
    所述第一高电压输入端为第一高电压端，所述第二高电压输入端、所述第三高电压输入端和所述第四高电压输入端为第二高电压端。
  12. 如权利要求4所述的驱动电路，其中，所述第二输出电路包括第五晶体管，所述第二下拉节点控制电路包括第六晶体管，所述第一控制节点控制电路包括第七晶体管；
    所述第五晶体管的控制极与下拉节点电连接，所述第五晶体管的第一极与所述驱动信号输出端电连接，所述第五晶体管的第二极与第一低电压输入端电连接；
    所述第六晶体管的控制极与所述第二低电压输入端电连接，所述第六晶体管的第一极与第三控制节点电连接，所述第六晶体管的第二极与下拉节点电连接；
    所述第七晶体管的控制极与第一时钟信号端电连接，所述第七晶体管的第一极与第三低电压输入端电连接，所述第七晶体管的第二极与第一控制节点电连接；
    所述第一低电压输入端和所述第二低电压输入端为第一低电压端，所述第三低电压输入端为第二低电压端；或者，
    所述第一低电压输入端为第一低电压端，所述第二低电压输入端和所述第三低电压输入端为第二低电压端。
  13. 如权利要求5所述的驱动电路，其中，所述第二控制节点控制电路包括第八晶体管；
    所述第八晶体管的控制极与第四低电压输入端电连接，所述第八晶体管的第一极与第一控制节点电连接，所述第八晶体管的第二极与第二控制节点电连接；
    所述第四低电压输入端为第一低电压端或第二低电压端。
  14. 如权利要求7所述的驱动电路，其中，所述第三下拉节点控制电路包括第一电容、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管；
    所述第一电容的第一端与第一节点电连接，所述第一电容的第二端与第二节点电连接；
    所述第九晶体管的控制极与第二节点电连接，所述第九晶体管的第一极与第一节点电连接，所述第九晶体管的第二极与第二时钟信号端电连接；
    所述第十晶体管的控制极与第二节点电连接，所述第十晶体管的第一极与下拉节点电连接，所述第十晶体管的第二极与第二节点电连接；
    所述第十一晶体管的控制极与第五低电压输入端电连接，所述第十一晶体管的第一极与第三节点电连接，所述第十一晶体管的第二极与第二节点电连接；
    所述第十二晶体管的控制极与第一时钟信号端电连接，所述第十二晶体管的第一极与起始信号端电连接，所述第十二晶体管的第二极与第三节点电连接。
  15. 如权利要求14所述的驱动电路，其中，所述第五低电压输入端为第一低电压端或第二低电压端。
  16. 如权利要求4至15中任一权利要求所述的驱动电路，其中，所述驱动电路包括第一控制节点控制电路、第三控制节点控制电路和第二上拉节点控制电路；
    所述第一控制节点控制电路与第一控制节点电连接，所述第一控制节点控制电路还与第三控制节点电连接，用于在所述第三控制节点的电位的控制下，控制所述第一控制节点与第一时钟信号端之间连通；
    所述第三控制节点控制电路分别与第一时钟信号端、起始信号端和第三控制节点电连接，用于在所述第一时钟信号端提供的第一时钟信号的控制下，控制所述起始信号端与所述第三控制节点电连接；
    所述第二上拉节点控制电路还分别与第一控制节点或者第二控制节点、第四控制节点、第二时钟信号端和第一高电压输入端电连接，用于根据第二控制节点的电位控制第四控制节点的电位，在所述第一控制节点的电位或者所述第二控制节点的电位的控制下，控制所述第二时钟信号端与所述第四控制节点之间连通，在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第四控制节点与上拉节点之间连通，并用于维持上拉节点的电位。
  17. 如权利要求16所述的驱动电路，其中，所述第一控制节点控制电路包括第十三晶体管，所述第三控制节点控制电路包括第十四晶体管，所述第 二上拉节点控制电路包括第二电容、第三电容、第十五晶体管和第十六晶体管；
    所述第十三晶体管的控制极与第三控制节点电连接，所述第十三晶体管的第一极与第一控制节点电连接，所述第十三晶体管的第二极与第一时钟信号端电连接；
    所述第十四晶体管的控制极与第一时钟信号端电连接，所述第十四晶体管的第一极与起始信号端电连接，所述第十四晶体管的第二极与第三控制节点电连接；
    第二电容的第一端与第二控制节点电连接，第二电容的第二端与第四控制节点电连接；
    第三电容的第一端与上拉节点电连接，第三电容的第二端与第一高电压输入端电连接；
    所述第十五晶体管的控制极与第二控制节点电连接，所述第十五晶体管的第一极与第二时钟信号端电连接，所述第十五晶体管的第二极与第四控制节点电连接；
    所述第十六晶体管的控制极与第二时钟信号端电连接，所述第十六晶体管的第一极与第四控制节点电连接，所述第十六晶体管的第二极与上拉节点电连接。
  18. 一种驱动电路，所述驱动电路包括第二输出电路、第二下拉节点控制电路和第一控制节点控制电路；
    所述第二输出电路分别与下拉节点、驱动信号输出端和第一低电压输入端电连接，用于在所述下拉节点的电位的控制下，控制所述驱动信号输出端与所述第一低电压输入端之间连通；
    所述第二下拉节点控制电路分别与第三控制节点、下拉节点和第二低电压输入端电连接，用于在所述第二低电压输入端提供的低电压信号的控制下，控制所述第三控制节点与所述下拉节点之间连通；
    所述第一控制节点控制电路分别与第一时钟信号端、第三低电压输入端和第一控制节点电连接，用于在所述第一时钟信号端提供的第一时钟信号的控制下，控制所述第一控制节点与所述第三低电压输入端电连接；
    所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中至少两个互不相同。
  19. 如权利要求18所述的驱动电路，其中，还包括第二控制节点控制电路；
    所述第二控制节点控制电路分别与第四低电压输入端、第一控制节点和第二控制节点电连接，用于在所述第四低电压输入端提供的低电压信号的控制下，控制所述第一控制节点和所述第二控制节点之间连通；
    所述第四低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端中的至少一个不相同。
  20. 如权利要求19所述的驱动电路，其中，还包括第三下拉节点控制电路；
    所述第三下拉节点控制电路分别与第一节点和第二时钟信号端电连接，用于控制所述第一节点与所述第二时钟信号端之间的通断；
    所述第三下拉节点控制电路还分别与第二节点、第三节点、第五低电压输入端、第一时钟信号端和起始信号端电连接，在第二节点的电位的控制下，控制所述第一节点与所述第二时钟信号端之间连通，根据所述第一节点的电位，控制所述第二节点的电位，在第一时钟信号端提供的第一时钟信号的控制下，控制所述起始信号端与第三节点连通，在所述第五低电压输入端提供的低电压信号的控制下，控制第三节点与第二节点之间连通，在所述第二节点的电位的控制下，控制所述第二节点与下拉节点之间连通；
    所述第五低电压输入端与所述第一低电压输入端、所述第二低电压输入端、所述第三低电压输入端、所述第四低电压输入端中的至少一个不相同。
  21. 一种显示面板，包括如权利要求1至20中任一权利要求所述的驱动电路；所述显示面板还包括显示驱动芯片；
    第一高电压输入端与第一高电压线电连接，第二高电压输入端与第二高电压线电连接；所述第一高电压线、所述第二高电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一高电压线提供第一高电压信号，所述显示驱动芯片用于为第二高电压线提供第二高电压信号。
  22. 一种显示面板，包括如权利要求18至20中任一权利要求所述的驱 动电路；所述显示面板还包括显示驱动芯片；
    第一低电压输入端与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第三低电压输入端与第三低电压线电连接，第一低电压线、第二低电压线、第三低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号，为第三低电压线提供第三低电压信号；或者，
    第一低电压输入端与第一低电压线电连接，第二低电压输入端和第三低电压输入端都与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
    第一低电压输入端和第二低电压输入端都与第一低电压线电连接，第三低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号；或者，
    第一低电压输入端和第三低电压输入端都与第一低电压线电连接，第二低电压输入端与第二低电压线电连接，第一低电压线、第二低电压线分别与所述显示驱动芯片的不同引脚电连接，所述显示驱动芯片用于为第一低电压线提供第一低电压信号，为第二低电压线提供第二低电压信号。
  23. 一种显示装置，包括如权利要求1至20中任一权利要求所述的驱动电路。
PCT/CN2022/128610 2022-10-31 2022-10-31 驱动电路、显示面板和显示装置 WO2024092400A1 (zh)

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