Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/42—Plated through-holes or plated via connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers

Definitions

• the present invention relates to a wiring board and a mounting structure using the same.
• via holes formed in the insulating layer are filled with a plating film (via hole conductor).
• the via hole conductor is usually connected to a via land at the bottom of the via.
• the wiring board according to the present disclosure comprises a first insulating layer having a first surface, a land conductor located on the first surface, a second insulating layer covering the first surface and the land conductor and having a second surface opposite the first insulating layer, a via hole penetrating from the second surface of the second insulating layer to the land conductor, and a via hole conductor located in the via hole and in contact with the land conductor.
• the via hole conductor has a first region of the surface of the via hole conductor that is in contact with the land conductor. The first region partially has a nichrome oxide layer.
• the mounting structure according to the present disclosure includes the above-mentioned wiring board and an electronic component located on at least one of the upper and lower surfaces of the wiring board.
• FIG. 2 is an explanatory diagram for explaining a wiring board according to an embodiment of the present disclosure.
• 2 is an enlarged cross-sectional view for explaining a region X shown in FIG. 1 .
• 1A to 1C are explanatory diagrams for explaining an example of a method for forming a via-hole conductor in a wiring board according to an embodiment of the present disclosure.
• 1A to 1C are explanatory diagrams for explaining an example of a method for forming a via-hole conductor in a wiring board according to an embodiment of the present disclosure.
• 1A to 1C are explanatory diagrams for explaining an example of a method for forming a via-hole conductor in a wiring board according to an embodiment of the present disclosure.
• 11 is a cross-sectional photograph showing a state after a via-hole conductor pull test in a wiring board according to an embodiment of the present disclosure.
• the via hole conductor is usually connected to the via land at the bottom of the via. Due to the difference in the thermal expansion coefficient and Young's modulus between the via hole conductor (such as copper) and the resin forming the insulating layer, stress is likely to concentrate at the connection between the via bottom and the via land. This makes the connection between the via bottom and the via land prone to destruction, reducing the connection reliability of the via hole conductor. Therefore, there is a demand for a wiring board that provides excellent connection reliability of the via hole conductor without degrading the electrical characteristics.
• the wiring board according to the present disclosure has the configuration described in the section on means for solving the above problems, which reduces the deterioration of electrical characteristics and provides excellent connection reliability of the via hole conductors.
• FIG. 1 is an explanatory diagram for explaining a wiring board 1 according to an embodiment of the present disclosure.
• the wiring board 1 according to the embodiment includes an insulating layer 2, a conductor layer 3, and a solder resist 4.
• the insulating layer 2 includes a core insulating layer 20, a first insulating layer 21, and a second insulating layer 22.
• the core insulating layer 20 is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed together.
• the thickness of the core insulating layer 20 is not particularly limited, and is, for example, 40 ⁇ m or more and 20 mm or less.
• the core insulating layer 20 is not necessarily required.
• the core insulating layer is not used in a substrate called a coreless substrate or a 2.3D substrate.
• the thickness of the core insulating layer 20 may exceed 10 mm, such as in a motherboard.
• the core insulating layer 20 may contain a reinforcing material.
• reinforcing materials include insulating cloth materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination.
• the core insulating layer 20 may have inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide dispersed therein. Two or more types of inorganic insulating fillers may be used in combination.
• inorganic insulating fillers such as silica and alumina that are chemically uncorrosive to acids and alkalis are often used in boards intended for fine wiring. This reduces insulation deterioration such as ion migration under high temperature and humidity conditions or under applied conditions.
• the through-hole conductor 20a is located in the core insulating layer 20 to electrically connect the top and bottom surfaces of the core insulating layer 20.
• the through-hole conductor 20a is located in a through-hole that penetrates the core insulating layer 20 from the top surface to the bottom surface.
• the through-hole conductor 20a is formed, for example, by metal plating such as copper plating.
• the through-hole conductor 20a is connected to the conductor layer 3 formed on both sides of the core insulating layer 20.
• the through-hole conductor 20a may be located only on the inner wall surface of the through-hole, or may be filled in the through-hole.
• the conductor layer 3 is not limited as long as it is a conductor such as a metal.
• the conductor layer 3 is formed of a metal foil such as copper foil, a metal plating such as copper plating, or the like.
• the thickness of the conductor layer 3 is not particularly limited, and is, for example, 2 ⁇ m or more and 50 ⁇ m or less. The thickness of the conductor layer 3 tends to become thinner as the wiring becomes finer.
• Build-up layers are located on both sides of the core insulating layer 20.
• the build-up layers have a structure in which conductor layers 3 and insulating layers 2 are alternately stacked.
• the insulating layer 2 closer to the core insulating layer 20 corresponds to the first insulating layer 21, and the other insulating layer 2 corresponds to the second insulating layer 22.
• the build-up layer has three insulating layers
• first insulating layer first insulating layer
• second insulating layer the first insulating layer closer to the core insulating layer corresponds to the first insulating layer
• second insulating layer corresponds to the second insulating layer.
• the second insulating layer closer to the core insulating layer corresponds to the first insulating layer
• the third insulating layer corresponds to the second insulating layer.
• the insulating layer 2 (first insulating layer 21 and second insulating layer 22) constituting the build-up layer is not particularly limited as long as it is made of a material having insulating properties, similar to the core insulating layer 20, and as described above, examples of the resin include epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed and used.
• the insulating layers 2 constituting the build-up layer may be made of the same resin or different resins.
• the insulating layers 2 constituting the build-up layer and the core insulating layer 20 may be made of the same resin or different resins.
• the thickness of the insulating layer 2 constituting the build-up layer is not particularly limited, and is, for example, 5 ⁇ m or more and 100 ⁇ m or less.
• the insulating layers 2 constituting the build-up layer may have the same thickness or different thicknesses.
• the insulating layer 2 constituting the build-up layer may contain a reinforcing material.
• reinforcing materials include insulating cloth materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination.
• the insulating layer 2 constituting the build-up layer may have inorganic insulating fillers such as silica, alumina, aluminum oxide, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide dispersed therein. Two or more types of inorganic insulating fillers may be used in combination.
• a solder resist 4 may be located on the surface of the build-up layer.
• the solder resist 4 is made of a resin, such as an acrylic-modified epoxy resin.
• the solder resist 4 has openings to electrically connect the conductor layer 3 and the electrodes of the elements via solder 5. Examples of the elements include semiconductor integrated circuit elements and optoelectronic elements.
• a via hole conductor 3b is formed to electrically connect the upper and lower surfaces of the insulating layer 2 constituting the build-up layer.
• the via hole conductor 3b is located in a via hole 31 formed to penetrate the insulating layer 2 constituting the build-up layer. That is, as shown in FIG. 2, the via hole conductor 3b is located in a via hole 31 that penetrates from the second surface 222 of the second insulating layer 22 to the land conductor 3a.
• FIG. 2 is an enlarged cross-sectional view for explaining the region X shown in FIG. 1.
• the second insulating layer 22 covers the first surface 211 of the first insulating layer 21 and the land conductor 3a located on the first surface 211.
• the second surface 222 of the second insulating layer 22 is the surface opposite to the first insulating layer 21.
• the via hole conductor 3b is filled in the via hole 31 formed in the second insulating layer 22, and its bottom (the bottom surface closer to the first surface 211) is in contact with the land conductor 3a.
• the land conductor 3a and the via hole conductor 3b are part of the conductor layer 3.
• the land conductor 3a is located on the first surface 211 of the first insulating layer 21, and includes a seed layer 3a1, a plating layer 3a2, and a surface treatment layer 3a3.
• the seed layer 3a1 may contain, for example, nichrome, and have a thickness of 1 nm or more and 100 nm or less.
• the plating layer 3a2 is located on the surface of the seed layer 3a1.
• the plating layer 3a2 contains, for example, a metal such as copper.
• the surface treatment layer 3a3 is located so as to cover the plating layer 3a2.
• the surface treatment layer 3a3 contains a metal or alloy such as tin, titanium, chromium, and nichrome.
• the via-hole conductor 3b includes a nichrome oxide layer 3b1, a nichrome layer 3b2, and a plating layer 3b3.
• the nichrome oxide layer 3b1 is formed by oxidizing a portion of the nichrome layer 3b2.
• the thickness of the nichrome oxide layer 3b1 may be, for example, 1 nm or more and 100 nm or less.
• the nichrome oxide layer 3b1 shown in FIG. 2 is located from the surface of the second side 222 of the second insulating layer 22 to the inner wall surface of the via hole 31.
• the region on the surface of the second side 222 of the second insulating layer 22 where the nichrome oxide layer 3b1 is located is defined as the third region 3b13.
• the region on the inner wall surface of the via hole 31 where the nichrome oxide layer 3b1 is located is defined as the second region 3b12.
• the nichrome oxide layer 3b1 is partially located in the region (first region 3b11) where the land conductor 3a and the via hole conductor 3b are in contact.
• the partial location of the nichrome oxide layer 3b1 in the first region 3b11 relieves the stress on the via bottom (first region 3b11).
• the Young's modulus decreases and the stress on the first region 3b11 is relieved.
• the partial location of the nichrome oxide layer 3b1 in the first region 3b11 provides a stress relief effect without deteriorating the electrical resistance.
• the nichrome oxide layer 3b1 is not limited as long as it is partially located. In other words, it can be said that the nichrome oxide layer 3b1 is scattered in the first region 3b11 in a planar view.
• the nichrome oxide layer 3b1 may be unevenly distributed in the first region 3b11 in a planar view. If it is scattered, the unevenness of stress relaxation in the first region 3b11 is reduced.
• the area occupied by the nichrome oxide layer 3b1 may be 30% or more and 70% or less.
• the area ratio occupied by the nichrome oxide layer 3b1 in the first region 3b11 may be calculated, for example, by performing a surface analysis so as not to oxidize the first region 3b11. Specifically, the first region 3b11 in the wiring board 1 is exposed using a focused ion beam (FIB) or the like, and surface analysis is performed using time-of-flight secondary ion mass spectrometry (TOF-SIMS) or the like in the same chamber used for the focused ion beam or the like.
• FIB focused ion beam
• TOF-SIMS time-of-flight secondary ion mass spectrometry
• the land conductor 3a may have a plurality of recesses 32 (not shown in FIG. 2) located in the region (first region 3b11) that contacts the via hole conductor 3b.
• a nichrome oxide layer 3b1 may be located in at least one of the recesses 32. When the nichrome oxide layer 3b1 is located in the recess 32, an anchor effect is exerted, and adhesion is further improved.
• the thickness of the nichrome oxide layer 3b1 may be 1 nm or more and 100 nm or less as described above, and may be smaller than the depth of the recess 32. If the thickness of the nichrome oxide layer 3b1 is smaller than the depth of the recess 32, the nichrome oxide layer 3b1 conforms to the recess 32. Therefore, the upper surface of the nichrome oxide layer 3b1 becomes curved. As a result, the stress relaxation effect is more effectively exerted.
• the thickness of the nichrome oxide layer 3b1 and the depth of the recess 32 can be measured, for example, by checking images from a scanning electron microscope or a transmission electron microscope.
• the nichrome oxide layer 3b1 may be located from the surface in contact with the via-hole conductor 3b to within the recess 32.
• the wiring board 1 according to one embodiment has the nichrome oxide layer 3b1 located also at the boundary between the surface of the land conductor 3a and the recess 32, where stress is likely to concentrate. This makes it easier to relieve stress.
• the nichrome oxide may be located in the third region 3b13. With this configuration, the wiring board 1 according to one embodiment can relieve stress between the third region 3b13 and the second insulating layer 22. As a result, for example, peeling of the via-hole conductor 3b from the second insulating layer 22 is reduced.
• the nichrome oxide layer 3b1 is located in the second region 3b12 and the third region 3b13.
• the nichrome oxide layer 3b1 does not have to be located in the second region 3b12 and the third region 3b13.
• the stress relaxation effect can reduce the peeling of the via hole conductor 3b from the second insulating layer 22, for example.
• the movement (migration) of ions from the nichrome layer 3b2 and the plating layer 3b3 to the insulating layer 2 can be reduced.
• the via hole conductor 3b and the land conductor 3a may have a continuous crystal 7 that straddles the boundary between the via hole conductor 3b and the land conductor 3a.
• This configuration increases the connection strength between the via hole conductor 3b and the land conductor 3a.
• the continuous crystal 7 may be formed via a nichrome oxide layer 3b1 having a thickness of 1 nm to 30 nm. This structure provides a stress relaxation effect and further increases the connection strength.
• the thickness of the nichrome oxide layer 3b1 may be 10 nm to 20 nm. By providing the nichrome oxide layer 3b1 with this thickness, the stress relaxation effect is effectively obtained without inhibiting the formation of the continuous crystal 7.
• the presence or absence of the continuous crystal 7 and the boundary between the via hole conductor 3b and the land conductor 3a can be confirmed, for example, by a scanning electron microscope or a transmission electron microscope.
• Figure 6 shows a cross-sectional photograph after a via hole conductor pull test.
• Figure 6A illustrates the via hole conductor 3b and the land conductor 3a.
• Figure 6B is an enlarged view of the area Y enclosed in a square in Figure 6A.
• Figure 6B shows that a nichrome oxide layer 3b1 can be confirmed at the interface between the via hole conductor 3b and the land conductor 3a, indicating that the nichrome oxide layer 3b1 contributes to stress relaxation.
• the nichrome oxide layer 3b1 can be easily analyzed using EDX, etc.
• Figures 3 to 5 are explanatory diagrams for explaining an example of a method for forming a via hole conductor 3b in a wiring board 1 according to an embodiment of the present disclosure.
• the first insulating layer 21 is prepared with a seed layer 3a1 deposited on the first surface 211 as shown in FIG. 3A.
• masking is performed with a resist 6 to form a plating layer 3a2.
• the seed layer 3a1 and plating layer 3a2 are as described above, and a detailed description will be omitted.
• the resist 6 is peeled off, and the seed layer 3a1 in the portion masked by the resist 6 is removed.
• Methods for removing the seed layer 3a1 include, for example, etching.
• plating layer 3a2 is subjected to an annealing treatment as shown in FIG. 3D.
• the annealing treatment may be performed, for example, at a temperature of 170°C to 220°C for 20 minutes to 90 minutes.
• recesses 32 are formed that have an opening diameter of 50 nm to 1000 nm and a depth of 50 nm to 300 nm.
• the surface of the plating layer 3a2 on which the recesses 32 are formed is subjected to a soft etching process.
• the soft etching process may be performed, for example, with a mixed solution of sulfuric acid and hydrogen peroxide for 20 to 60 seconds.
• the opening diameter of the recesses 32 is set to 10 to 500 nm, and the depth is set to 5 to 50 nm.
• the recesses are not an essential requirement. Therefore, if no recesses are formed, the annealing process and the soft etching process may be omitted.
• the conductor (seed layer 3a1 and plating layer 3a2) is subjected to a surface treatment.
• a tin plating process is performed to cover the seed layer 3a1 and plating layer 3a2, followed by a nitric acid treatment and a silane coupling treatment.
• a tin layer is formed by the tin plating process.
• the thickness of the tin layer is, for example, 2 nm to 5 nm.
• the silane coupling agent is a compound having a functional group that reacts with inorganic materials and a functional group that reacts with organic materials within the molecule.
• the silane coupling agent layer has a thickness of, for example, 15 nm or less, and may be thicker than the tin layer.
• the second insulating layer 22 is laminated on the first surface 211 of the first insulating layer 21.
• the second insulating layer 22 is as described above, and a detailed description will be omitted.
• the method of laminating the second insulating layer 22 on the first surface 211 may be, for example, to place an uncured or semi-cured resin sheet on the first surface 211 and cure it by applying heat and pressure.
• a via hole 31 is formed that penetrates from the second surface 222 of the second insulating layer 22 to the land conductor 3a.
• the via hole 31 is formed using a laser.
• the plating layer 3a2 of the land conductor 3a that has been exposed by the laser irradiation is cleaned.
• the cleaning may be performed by subjecting it to oxygen plasma treatment and treating it with a potassium permanganate solution.
• an oxide film 33 is formed on the entire surface of the exposed plating layer 3a2.
• the substrate is dried at around 125°C for about 1 to 2 hours. This drying removes about 80% of the moisture.
• the substrate from which moisture has been removed is subjected to a first sputtering process (nitrogen plasma process).
• This first sputtering process removes the oxide film 33 on the surface of the plating layer 3a2, while leaving the oxide film 33 located in the recesses. By changing the plasma output, it is also possible to partially remove the oxide film 33.
• the second sputtering process (nichrome sputtering process) is performed.
• the second sputtering process forms a nichrome layer 3b2 on the second surface 222 of the second insulating layer 22, the side surface of the via hole 31, and the plating layer 3a2 of the land conductor 3a exposed at the bottom of the via hole 31.
• the nichrome layer 3b2 located in the recess 32 is supplied with oxygen from the oxide film 33 and changes to a nichrome oxide layer 3b1.
• the nichrome oxide layer 3b1 may be located across from the recess 32 to the flat portion. The stress relaxation effect is enhanced by having the nichrome oxide layer 3b1 located at the boundary (corner) between the recess 32 and the flat portion, where stress is likely to concentrate.
• a plating layer 3b3 is formed by electrolytic plating.
• a resist is usually formed to mask areas other than the vicinity of the via hole 31.
• the resist is removed, and if necessary, the excess nichrome oxide layer 3b1 and nichrome layer 3b2 formed in unnecessary areas on the second surface 222 of the second insulating layer 22 may be removed.
• a via hole conductor 3b included in the wiring board 1 is formed.
• the mounting structure according to one embodiment includes a wiring board 1 according to one embodiment and an element located on the surface of the wiring board 1.
• the conductor layer 3 in the opening of the solder resist 4 and the electrodes of the element are connected via solder 5.
• Examples of the element include a semiconductor integrated circuit element and an optoelectronic element.
• the elements may be located on both sides of the wiring board 1, or the elements may be located on one surface and, for example, a motherboard may be located on the other surface.
• the wiring board according to the present disclosure is not limited to the wiring board 1 according to the embodiment described above.
• the insulating layer 2 constituting the build-up layer has a two-layer structure.
• the insulating layer constituting the build-up layer in the wiring board according to the present disclosure is not limited to a two-layer structure, and may have a laminated structure of three or more layers.
• a first insulating layer having a first surface, a land conductor located on the first surface, a second insulating layer covering the first surface and the land conductor and having a second surface on the opposite side to the first insulating layer, a via hole penetrating from the second surface of the second insulating layer to the land conductor, and a via hole conductor located in the via hole and in contact with the land conductor.
• the via hole conductor has a first region of the surface of the via hole conductor that is in contact with the land conductor. The first region partially has a nichrome oxide layer.
• the area ratio of the nichrome oxide layer in the first region is 30% or more and 70% or less.
• the land conductor has a plurality of recesses on a surface in contact with the via-hole conductor, and the nichrome oxide layer is located in at least one of the plurality of recesses.
• the thickness of the nichrome oxide layer is smaller than the depth of the recess.
• the nichrome oxide layer is positioned from the surface in contact with the via-hole conductor to within the recess.
• the via-hole conductor has a nichrome oxide layer in a second region of the surface of the via-hole conductor that contacts the inner wall of the via hole.
• the via-hole conductors and the land conductors have continuous crystals that straddle the boundaries between the via-hole conductors and the land conductors.
• the nichrome oxide layer has a thickness of 1 nm or more and 100 nm or less.
• (9) Includes a wiring board described in any one of (1) to (8) above and an electronic component located on at least one of the upper and lower surfaces of the wiring board.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)
• Parts Printed On Printed Circuit Boards (AREA)
• Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

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Citations (3)

• 2023
  • 2023-10-20 JP JP2024553013A patent/JPWO2024090336A1/ja not_active Withdrawn
  • 2023-10-20 WO PCT/JP2023/037966 patent/WO2024090336A1/ja not_active Ceased
  • 2023-10-25 TW TW112140904A patent/TW202428076A/zh unknown

Patent Citations (3)

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