WO2024088294A1 - 一种晶片调度方法和一种电子设备 - Google Patents

一种晶片调度方法和一种电子设备 Download PDF

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Publication number
WO2024088294A1
WO2024088294A1 PCT/CN2023/126409 CN2023126409W WO2024088294A1 WO 2024088294 A1 WO2024088294 A1 WO 2024088294A1 CN 2023126409 W CN2023126409 W CN 2023126409W WO 2024088294 A1 WO2024088294 A1 WO 2024088294A1
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processed
wafer
scheduling
time point
test piece
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French (fr)
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WO2024088294A9 (zh
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李�杰
张璐
刘慕雅
曾为鹏
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Beijing Naura Microelectronics Equipment Co Ltd
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Beijing Naura Microelectronics Equipment Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00—Administration; Management
    • G06Q10/06—Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
    • G06Q10/063—Operations research, analysis or management
    • G06Q10/0631—Resource planning, allocation, distributing or scheduling for enterprises or organisations

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a wafer scheduling method and an electronic device.
  • the production capacity of semiconductor cluster tools is one of the important factors affecting the overall production capacity of semiconductor chip processing.
  • the process complexity and control accuracy of semiconductor cluster tools for processing chips are also constantly improving to obtain a higher production yield.
  • test (Dummy) wafer In addition to the normal scheduling of the process wafers to be processed in the semiconductor assembly equipment, there is also a wafer for restoring the chamber, called a test (Dummy) wafer.
  • the processing chamber is restored and cleaned by sending the wafer of the recovery chamber into the processing chamber for processing.
  • the use of the test piece is usually affected by the setting of the chamber of the semiconductor assembly equipment and the setting of the wafer to be processed.
  • a test piece can be inserted before the processing of the wafer to be processed, after the processing is completed, or at a fixed interval to restore the processing chamber.
  • a test piece can also be inserted after the processing chamber accumulates several wafers to be processed to restore the processing chamber.
  • the insertion order of the test piece for different wafer settings is also different, and the existing insertion order may also be changed during the processing process. It is difficult to predict the insertion time in advance and deliver the test piece to the processing chamber that needs to be restored in a timely and accurate manner, resulting in the processing chamber being idle waiting for the test piece, reducing the utilization rate of the semiconductor assembly equipment, and thus reducing the production capacity of semiconductor chips.
  • embodiments of the present invention are proposed to provide a wafer scheduling method and a corresponding electronic device that overcome the above problems or at least partially solve the above problems.
  • an embodiment of the present invention discloses a wafer scheduling method, wherein the wafer includes a test wafer and a wafer to be processed, and the method includes:
  • simulation scheduling sequence runs to the test wafer scheduling time point, a target wafer to be processed is determined, and the simulation scheduling sequence is used to schedule the wafer to be processed;
  • a test wafer process path is set at the target wafer to be processed scheduling time point to generate an executable scheduling sequence.
  • the method further comprises:
  • test piece usage rule includes the test piece scheduling time point and the test piece process path.
  • the simulation scheduling sequence includes a transmission path corresponding to the wafer to be processed, and the transmission path sequentially passes through a wafer loading and unloading module, a first manipulator, a calibration module, an atmospheric environment vacuum lock chamber, a vacuum environment vacuum lock chamber, and a second manipulator; when the simulation scheduling sequence runs to the test piece scheduling time point, determining the target wafer to be processed includes:
  • the wafers to be processed on the transmission path are sorted according to the transmission order of the transmission path to generate a sequence of wafers to be processed;
  • the wafer to be processed at the end of the sequence of wafers to be processed is determined as the target wafer to be processed.
  • rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed includes:
  • the data from the target wafer to be processed scheduling time point to the test wafer scheduling time point corresponding to the target wafer to be processed in the simulation scheduling sequence is deleted.
  • rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed includes:
  • the current path point is one of the first manipulator, the calibration module, the second manipulator, the atmospheric environment vacuum lock chamber, and the vacuum environment vacuum lock chamber;
  • the data from the target wafer to be processed scheduling time point to the test wafer scheduling time point corresponding to the target wafer to be processed in the simulation scheduling sequence is deleted.
  • test wafer process path corresponds to a test wafer priority
  • test wafer process path is set at the target wafer to be processed scheduling time point to generate an executable scheduling sequence, including:
  • the process duration is added to obtain the target test wafer process completion time point;
  • the priority of the test piece is cleared to generate an executable scheduling sequence.
  • the method further includes:
  • next test piece scheduling time point exists, determining the next test piece scheduling time point as the test piece scheduling time point, and executing the step of determining the target wafer to be processed when the simulation scheduling sequence runs to the test piece scheduling time point until the next test piece scheduling time point does not exist;
  • the method further comprises:
  • the executable scheduling sequence is sent to a preset semiconductor process equipment, and the preset semiconductor process equipment is used to schedule the test piece for production based on the executable scheduling sequence.
  • the method further comprises:
  • the simulation scheduling sequence is generated based on the operating status of the preset semiconductor process equipment.
  • the embodiment of the present invention further discloses an electronic device, which is connected to a semiconductor process device.
  • the electronic device is used to execute the wafer scheduling method as described above.
  • the embodiment of the present invention determines the target wafer to be processed when the simulation scheduling sequence runs to the test wafer scheduling time point, and the simulation scheduling sequence is used to schedule the wafer to be processed; rolls back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed; and schedules the target wafer to be processed.
  • the process path of the test piece is set at a time point to generate an executable scheduling sequence. When the test piece needs to be scheduled, the wafer to be processed at this time is determined, and the target wafer to be processed scheduling time point is rolled back.
  • the process path of the test piece is set at the target wafer to be processed scheduling time point, so that the test piece is scheduled first at this time, so that when the test piece is needed to enter the processing chamber, the test piece in the process path can be used quickly, saving idle waiting time, thereby improving production efficiency.
  • the scheduling of the test piece is performed on the basis of the normal scheduling time of the wafer to be processed, so that even in the case of complex scheduling of the wafer to be processed, it can be accurately scheduled, and it can adapt to changes in different processing technology requirements more quickly, further improving the production capacity of semiconductor chips.
  • FIG1 is a flow chart of the steps of a wafer scheduling method according to an embodiment of the present invention.
  • FIG2 is a flowchart of another wafer scheduling method according to an embodiment of the present invention.
  • FIG3 is a schematic diagram of a wafer transmission path according to an embodiment of the present invention.
  • FIG4 is a schematic diagram of an application system of a wafer scheduling method according to an embodiment of the present invention.
  • FIG5 is a flowchart of an exemplary wafer scheduling method according to an embodiment of the present invention.
  • FIG. 6 is a structural block diagram of an electronic device according to an embodiment of the present invention.
  • the wafers scheduled in the embodiment of the present invention include a test wafer and a wafer to be processed.
  • the test wafer is a dummy wafer; the wafer to be processed is a wafer to be processed, such as a silicon wafer.
  • the wafer scheduling method may specifically include the following steps:
  • Step 101 when the simulation scheduling sequence runs to the test wafer scheduling time point, the target wafer to be processed is determined, and the simulation scheduling sequence is used to schedule the wafer to be processed.
  • test wafer and the wafer to be processed are both in the same semiconductor assembly equipment and can be dispatched using the same mechanical parts.
  • the difference between the test wafer and the wafer to be processed is that the storage boxes of the two are located at different loading and unloading positions.
  • a simulation scheduling sequence can be determined according to the process flow.
  • the simulation scheduling sequence can be used to schedule the wafer to be processed in the semiconductor assembly equipment during the processing.
  • the above-mentioned simulation scheduling sequence will run in chronological order to determine the actions that need to be performed at each time point in the processing process.
  • the time point that the simulation scheduling sequence is currently running to matches the test piece scheduling time point it is determined that the simulation scheduling sequence runs to the test piece scheduling time point.
  • the wafer to be processed that is closest to the processing chamber is determined from the multiple wafers to be processed that are currently being scheduled as the target wafer to be processed, that is, the wafer to be processed that is in the process path but has not been processed, and is closest to the end of the process path.
  • the test piece scheduling time point is the time point when the processing chamber needs to schedule the test piece to enter in order to clean and calibrate the processing chamber; it uses the same timeline as the simulation scheduling sequence.
  • Step 102 rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed.
  • the actions that have been executed by the target wafer to be processed can be determined in the simulation scheduling sequence, and the time point at which the target wafer to be processed starts to be scheduled can be calculated according to the time of executing these actions, which is the target wafer to be processed scheduling time point corresponding to the target wafer to be processed.
  • the simulation scheduling sequence is rolled back from the current time point to the target wafer to be processed scheduling time point, and is re-run from the target wafer to be processed scheduling time point.
  • Step 103 setting a test wafer process path at the target wafer to be processed scheduling time point, and generating an executable scheduling sequence.
  • the test piece process path is set at the wafer scheduling time point, that is, the action performed by the simulation scheduling sequence at the target wafer to be processed scheduling time point is to schedule the test piece according to the test piece process path.
  • the updated simulation scheduling sequence is determined as the executable scheduling sequence.
  • the executable scheduling sequence is the actual operation control sequence that can meet the scheduling requirements of the test piece.
  • the embodiment of the present invention determines the target wafer to be processed when the simulation scheduling sequence runs to the test piece scheduling time point, and the simulation scheduling sequence is used to schedule the wafer to be processed; rolls back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed; sets the test piece process path at the target wafer to be processed scheduling time point to generate an executable scheduling sequence.
  • the wafer to be processed at this time is determined, rolled back to the target wafer to be processed scheduling time point, and the test piece process path is set at the target wafer to be processed scheduling time point, so that the test piece is first scheduled at this time, so that when the test piece needs to be scheduled to enter the processing chamber, the test piece in the process path can be quickly scheduled for use, saving idle waiting time, thereby improving production efficiency.
  • the scheduling of the test piece is performed on the basis of the normal scheduling time of the wafer to be processed, so that even in the case of complex scheduling of the wafer to be processed, it can be accurately scheduled, and can adapt to changes in different processing technology requirements more quickly, further improving the production capacity of semiconductor chips.
  • the wafers to be scheduled include test wafers and wafers to be processed; the scheduling method may specifically include the following steps:
  • Step 201 recording the operating status of a preset semiconductor process equipment.
  • the semiconductor process equipment that needs to schedule the use of test pieces during the processing process can be used as the semiconductor process equipment for action simulation, that is, the preset semiconductor process equipment.
  • the operation status of the semiconductor process equipment can be recorded. That is, all process actions and states of the semiconductor process equipment without considering the potential test piece requirements are recorded.
  • Step 202 Generate a simulation scheduling sequence based on the operating status of the preset semiconductor process equipment.
  • the recorded operating status of the preset semiconductor process equipment is used as configuration data to generate a simulation scheduling sequence, and the simulation scheduling sequence is started to simulate the actions of the preset semiconductor process equipment. Based on the time sequence, the actions of the simulation scheduling sequence are executed to take out the wafers to be processed from the specified wafer box for scheduling.
  • Step 203 when running the simulation scheduling sequence, obtain the test piece usage rules, the test piece usage rules including the test piece scheduling time point and the test piece process path.
  • the simulation scheduling sequence is run, and the corresponding actions are executed to schedule the wafers to be processed, and the actions of the semiconductor assembly equipment are simulated.
  • the test piece usage rules can be obtained at the same time as the simulation scheduling sequence starts.
  • the test piece usage rules are used to determine the time when the test piece needs to be scheduled, and the path for scheduling the test piece. Therefore, the test piece usage rules include the test piece scheduling time point and the test piece process path. Among them, the test piece process path is the path that the test piece passes through when scheduling the test piece.
  • the test piece usage rule is information determined jointly according to the process requirements of the wafer to be processed and the setting of the processing chamber of the preset semiconductor process equipment.
  • the determination of the test piece scheduling time point of the test piece usage rule are that the test piece is required before the job (process) starts, the number of wafers to be processed is processed at intervals, and the job is completed;
  • the setting requirements of the processing chamber of the preset semiconductor process equipment are that the test piece is required after the processing chamber is idle for a period of time and the fixed number of wafers to be processed are continuously executed. Therefore, based on this condition, there is a unique test piece scheduling time point and test piece process path.
  • the test piece scheduling time point and the time when the simulation scheduling sequence runs are on the same time axis.
  • the time point can be expressed in a relative time manner. For example, the time when the simulation scheduling sequence starts running is "0", and the subsequent test piece scheduling time point can be expressed as 10 seconds; that is, the test piece scheduling time point is the 10th second after the simulation scheduling sequence runs.
  • the accuracy of the corresponding time point can be determined according to production requirements, and the accuracy of the time is not limited here.
  • the usage rules for the test piece can be obtained from the specified storage space address. It can be a local storage space address or a third-party storage space address, which is not specifically limited in the embodiment of the present invention.
  • Step 204 When the simulation scheduling sequence runs to the test wafer scheduling time point, the target wafer to be processed is determined.
  • the simulation scheduling sequence runs in chronological order to perform the corresponding actions.
  • the time point of the simulation scheduling sequence runs matches the test piece scheduling time point, it is determined that the simulation scheduling sequence runs to the test piece scheduling time point.
  • the simulation scheduling sequence runs to the 10th second it is determined that the simulation scheduling sequence runs to the test piece scheduling time point.
  • the wafers to be processed that are in the process path but have not been processed at the test piece scheduling time point are determined. From the wafers to be processed that are in the process path but have not been processed, the wafer to be processed closest to the end of the process path is determined as the target wafer to be processed. If there is no wafer to be processed that is in the process path but has not been processed at the test piece scheduling time point, it can be determined that the target wafer to be processed is empty.
  • the simulation scheduling sequence includes a transmission path corresponding to the wafer to be processed, and the transmission path sequentially passes through the wafer loading and unloading module, the first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator;
  • the process path corresponding to processing a wafer to be processed into a semiconductor chip is a wafer loading and unloading module (LoadPort), a first manipulator (ATM), an alignment module (Aligner), an atmospheric vacuum lock chamber (one of the slots of LoadLock), a vacuum vacuum lock chamber (another slot of LoadLock), a second manipulator (VTM), a processing chamber (PM1, PM2, PM3, PM4), a second manipulator, a vacuum vacuum lock chamber, an atmospheric vacuum lock chamber, a first manipulator, and a wafer loading and unloading module.
  • the transmission path is the path that the wafer to be processed passes through when it is in the process path but not processed, that is, it passes through the wafer loading and unloading module, the first manipulator, the alignment module, the atmospheric vacuum lock chamber, the vacuum vacuum lock chamber, and the second manipulator in sequence.
  • the first manipulator can be a single-arm manipulator
  • the second manipulator can be a double-arm manipulator.
  • the target wafer to be processed is determined, including:
  • Sub-step S2041 when the simulation scheduling sequence runs to the test wafer scheduling time point, determining whether there is a wafer to be processed in the transmission path;
  • the first manipulator If there is no wafer to be processed at the wafer loading and unloading module, the first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator position, it is determined that there is no wafer to be processed on the transmission path.
  • Sub-step S2042 when there is no wafer to be processed in the transmission path, determining that the target wafer to be processed is empty;
  • Sub-step S2043 when there are wafers to be processed in the transmission path, sorting the wafers to be processed in the transmission path according to the transmission order of the transmission path to generate a sequence of wafers to be processed;
  • the wafers to be processed currently in the transmission path are sorted in the order of the wafer loading and unloading module, the first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator, and the obtained sequence is the sequence of wafers to be processed.
  • Sub-step S2044 determining the last wafer to be processed in the sequence of wafers to be processed as the target wafer to be processed.
  • Step 205 rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed.
  • the corresponding time of all actions performed by the target wafer to be processed from the wafer to the position point is calculated, and based on the time, the scheduling time point of the target wafer to be processed is determined in the simulation scheduling sequence.
  • the determination of the scheduling time point of the target wafer to be processed can be determined according to the type of the target wafer to be processed.
  • simulation scheduling sequence is rolled back to the target wafer to be processed scheduling time point, so that the next action of the simulation scheduling sequence can be adjusted at the target wafer to be processed scheduling time point.
  • rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed includes:
  • Sub-step S2051 determining the test wafer scheduling time point as the target wafer to be processed scheduling time point corresponding to the target wafer to be processed.
  • test piece scheduling time point is determined to be the target wafer to be processed scheduling time point.
  • Sub-step S2052 deleting the data from the target wafer to be processed scheduling time point to the test wafer scheduling time point corresponding to the target wafer to be processed in the simulation scheduling sequence.
  • the data from the scheduling time point of the target wafer to be processed to the scheduling time point of the test wafer in the simulation scheduling sequence is deleted.
  • all actions and parameters executed in the simulation scheduling sequence during the period from the target wafer to be processed scheduling time point to the test wafer scheduling time point can be deleted, and the current time point can be rolled back to the target wafer to be processed scheduling time point.
  • rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed includes:
  • Sub-step S2053 determining a current path point corresponding to the target wafer to be processed, where the current path point is one of the first manipulator, the calibration module, the second manipulator, the atmospheric environment vacuum lock chamber, and the vacuum environment vacuum lock chamber;
  • a current path point of the target wafer to be processed on the transmission path at the current moment is determined, wherein the current path point is one of the first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator.
  • Sub-step S2054 calculating the running time from the wafer loading and unloading module to the current path point;
  • the first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator have corresponding action durations.
  • the action duration corresponding to each current path point is determined according to the duration of the semiconductor process equipment in the action during actual processing. According to the action duration corresponding to the current path point of the target wafer to be processed, the running time of the target wafer to be processed from the wafer loading and unloading module to the current path point is calculated.
  • the action time of the first manipulator is 1 second
  • the action time of the calibration module is 2 seconds
  • the action time of the atmospheric vacuum lock chamber is 1 second
  • the action time of the vacuum vacuum lock chamber is 1 second
  • the action time of the vacuum vacuum lock chamber is 1 second
  • the action time of the second manipulator is 1 second.
  • the current path point of the target wafer to be processed is the atmospheric vacuum lock chamber, that is, the running time of the target wafer to be processed from the wafer loading and unloading module to the atmospheric vacuum lock chamber is 4 seconds (the sum of the action time of the first manipulator, the action time of the calibration module and the action time of the atmospheric vacuum lock chamber).
  • Sub-step S2055 subtracting the running time from the test wafer scheduling time point to obtain the target wafer to be processed scheduling time point corresponding to the target wafer to be processed.
  • the time point obtained by subtracting the running time from the test chip scheduling time point is the target wafer to be processed corresponding to the target wafer to be processed scheduling time point.
  • the simulation scheduling sequence starts scheduling the target wafer to be processed at the target wafer to be processed scheduling time point.
  • Sub-step S2056 deleting the data from the target wafer to be processed scheduling time point to the test wafer scheduling time point corresponding to the target wafer to be processed in the simulation scheduling sequence.
  • the data from the target wafer to be processed scheduling time point to the test wafer scheduling time point in the simulation scheduling sequence is deleted. All the actions and parameters executed in the simulation scheduling sequence during the period from the target wafer to be processed scheduling time point to the test wafer scheduling time point can be deleted, and the data can be rolled back to the target wafer to be processed scheduling time point at the current time.
  • Step 206 setting a test wafer process path at the target wafer to be processed scheduling time point, and generating an executable scheduling sequence.
  • the process path of the test piece is set at the scheduling time point of the target wafer to be processed, and the priority of scheduling the test piece is raised to the highest level, so that when the simulation scheduling sequence runs to the scheduling time point of the target wafer to be processed, the test piece is scheduled first. After the scheduling requirements of all test pieces are met, the updated simulation scheduling sequence is determined as the executable scheduling sequence.
  • the process path of the test piece can be determined according to the actual path of the test piece from its loading and unloading position to the target processing chamber and then back to its loading and unloading position.
  • test wafer process path corresponds to the test wafer priority
  • test wafer process path is set at the target wafer to be processed scheduling time point
  • an executable scheduling sequence is generated, including:
  • Sub-step S2061 determining a target test piece process path based on the test piece priority
  • test piece process path with the highest priority is the test piece process path currently required. Therefore, based on the test piece priority, the test piece process path with the highest priority can be determined from the test piece process paths as the target test piece process path.
  • Sub-step S2062 adding the target test wafer process path to the target wafer to be processed scheduling time point;
  • Add the target test piece process path to the target wafer to be processed scheduling time point that is, the next step after the target wafer to be processed scheduling time point is to execute the target test piece process path scheduling test piece.
  • the process duration required to complete the entire process path of the target test piece is calculated.
  • the target test piece process path is a test piece loading and unloading module (DummyPort), a first manipulator (ATM), a calibration module (Aligner), an atmospheric environment vacuum lock chamber (one of the slots of LoadLock), a vacuum environment vacuum lock chamber (another slot of LoadLock), a second manipulator (VTM), (, a processing chamber (PM1, PM2, PM3, PM4), a second manipulator, a vacuum environment vacuum lock chamber, an atmospheric environment vacuum lock chamber, a first manipulator, and a test piece loading and unloading module.
  • the corresponding action durations are 1 second, 1 second, 2 seconds, 1 second, 1 second, 2 seconds, 3 seconds, 2 seconds, 1 second, 1 second, 1 second, and 1 second.
  • the process duration is 17 seconds (the sum of the action durations corresponding to all path points of the target test piece process path).
  • Sub-step S2064 adding the process duration to the target wafer to be processed scheduling time point to obtain the target test wafer process completion time point;
  • the process duration is added on this basis, and the obtained time point is determined as the target test piece process completion time point.
  • the target test piece process completion time point is used to represent the time point when the current test piece is completed.
  • Sub-step S2065 at the target test piece process completion time point, clear the test piece priority and generate an executable scheduling sequence.
  • the test piece priority is cleared so that the simulation scheduling sequence does not continue to schedule the test piece at the time point when the target test piece process is completed, and waits for the next test piece process with a higher priority to be scheduled again; thereby updating the simulation scheduling sequence to generate an executable scheduling sequence.
  • test wafer scheduling time points there may be a situation where multiple different processing chambers need to schedule the use of test wafers, that is, there may be a situation where there are multiple test wafer scheduling time points.
  • the target wafer to be processed scheduling time point After the step of setting the process path of the test piece, determine whether there is a next test piece scheduling time point in the simulation scheduling sequence according to the time sequence;
  • next test piece scheduling time point is the last time point at which the semiconductor process equipment needs to schedule a test piece.
  • next test piece scheduling time point determines the next test piece scheduling time point as the test piece scheduling time point, and perform the step of determining the target wafer to be processed when the simulation scheduling sequence runs to the test piece scheduling time point until there is no next test piece scheduling time point;
  • the currently updated simulation scheduling sequence cannot be used as an executable scheduling sequence for controlling the processing of the preset semiconductor process equipment. It is necessary to continue to update the action of scheduling the test piece in the simulation scheduling sequence.
  • the next test piece scheduling time point can be determined as the test piece scheduling time point, and the simulation scheduling sequence is continued to be executed at the test piece scheduling time point to run to the test piece scheduling time point, and the steps of determining the target wafer to be processed are determined, and the new target wafer to be processed and the corresponding target wafer to be processed scheduling time point are determined, so as to insert the action of scheduling the test piece at the new target wafer to be processed scheduling time point, and further update the simulation scheduling sequence; until there is no next test piece scheduling time point.
  • the updated simulation scheduling sequence can accurately control the preset semiconductor process equipment to produce semiconductor chips.
  • the step of generating an executable scheduling sequence is executed, and the simulation scheduling sequence updated at this time is determined as the executable scheduling sequence.
  • Step 207 sending the executable scheduling sequence to a preset semiconductor process equipment, where the preset semiconductor process equipment is used to schedule the test piece for production based on the executable scheduling sequence.
  • the executable scheduling sequence can be sent to a preset semiconductor process equipment.
  • the preset semiconductor process equipment receives the executable scheduling sequence, controls the corresponding modules to run based on the actions in the executable scheduling sequence, and produces semiconductor chips.
  • the test piece scheduling method of the embodiment of the present invention has good versatility and can support various types of wafers. And when the simulation scheduling sequence is run to schedule the wafer to be processed, the test piece scheduling is adjusted in parallel, so that the logic of scheduling the wafer to be processed and scheduling the test piece are decoupled, and the two are independent of each other, which can adapt to the changes of different process requirements more quickly.
  • the priority of the test piece is adjusted to achieve the earliest test piece output, and re-scheduling, so that when the processing chamber needs a test piece, the test piece in the process path is closest to the processing chamber, saving the idle waiting time of the processing chamber, thereby improving the production capacity of semiconductor chips.
  • the application system may specifically include the following five modules:
  • Optimization scheduling module It adopts optimization scheduling algorithms such as finite state machine and extended finite state machine. According to the real-time status of the simulated system, it can optimize and calculate the optimal scheduling strategy (simulation scheduling sequence) without considering the potential test piece requirements.
  • Simulation module The simulation of each equipment unit of the semiconductor combination equipment can be used to simulate the process control execution process of actual semiconductor process equipment.
  • Dummy demand logic judgment module According to the system status of the simulation and the logic of the test piece usage rules, it is judged whether each processing chamber needs the test piece usage rules in this simulation state, and the required test piece usage rule information is output;
  • State rollback module determines the rollback time point, triggers the simulation module to perform state rollback, and modifies the process path and priority of the corresponding test piece in the simulation module;
  • Scheduling sequence output module According to the scheduling action sequence recorded by the simulation system, organize and output the scheduling sequence list (executable sequence).
  • the wafer scheduling method flow may refer to FIG. 5 .
  • Step 1 Use a computer program to simulate the machine, record all process actions and states of the machine, and initialize or update the simulation program according to the actual state of the semiconductor assembly equipment;
  • Step 2 Remove the wafers to be processed in LoadPort (wafer loading and unloading position) and DummyPort (test wafer loading and unloading position) in order of priority;
  • Step 3 Using the optimization scheduling algorithm, the scheduling sequence (simulation scheduling sequence) is solved without considering the potential dummy demand (i.e., the test wafer is scheduled as the wafer to be processed);
  • Step 4 Run the simulation program and execute the next action in the simulation program in chronological order; if the next action is that the Dummy piece (test piece) that has completed the process returns to the DummyPort (test piece loading and unloading position), clear the process path and priority of the Dummy piece.
  • Step 5 Determine whether all (test slice) scheduling tasks are completed. If yes, execute step 6; otherwise, execute step 7.
  • Step 6 Arrange and output all process actions recorded by the simulation program as the machine executable scheduling sequence, and the program ends and the executable scheduling sequence is output;
  • Step 7 According to the usage logic rules of the Dummy sheet (test sheet usage rules), loop to determine whether each PM (processing chamber) currently needs a Dummy sheet. If all PMs do not need it, execute step 4, otherwise execute step 8.
  • Step 8 Record the PM that needs the dummy piece as PM_dummy (target processing chamber). If there are multiple PMs that need the dummy piece, select a PM record according to the priority.
  • Step 9 Determine whether there are wafers that have left the LoadPort (wafer loading and unloading position to be processed) and have not been processed (i.e., wafers to be processed on the transport path). If so, execute step 10; otherwise, execute step eleven;
  • Step 10 Find the last wafer to be processed in the steps of LoadPort (wafer loading and unloading position to be processed) -> ATM (first manipulator) -> Aligner (calibration module) -> ATM (second manipulator) -> LoadLock atmospheric environment (atmospheric environment vacuum lock chamber) -> LoadLock vacuum environment (vacuum environment vacuum lock chamber);
  • T2 The time point when this chip leaves LoadPort is obtained as T2 (the scheduling time point of the target chip to be processed); roll back the status of all devices, chips and Dummy chips in the simulation system to the T2 time point, and delete all action and status records from T2 to the current time in the simulation program.
  • Step 11 Find the first Dummy slice according to the priority of the Dummy slice; initialize the process path of this Dummy slice, and set the target pm to PM_dummy; regard this Dummy slice as a wafer to be processed, and set the priority to the highest; go to step 2.
  • FIG. 6 a block diagram of an electronic device according to an embodiment of the present invention is shown; an electronic device 601 is connected to a semiconductor process device,
  • the electronic device 601 is used to execute the above wafer scheduling method.
  • the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
  • An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored.
  • a computer program is stored.
  • the various processes of the above-mentioned test piece scheduling method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
  • the embodiments of the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate a device for implementing the functions specified in one process or multiple processes in the flowchart and/or one box or multiple boxes in the block diagram.
  • These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

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Abstract

提供了一种晶片调度方法和一种电子设备。晶片调度方法包括当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片，仿真调度序列用于调度待加工晶片（101）；将仿真调度序列回滚至目标待加工晶片对应的目标待加工晶片调度时间点（102）；在目标待加工晶片调度时间点上设定测试片工艺路径，生成可执行调度序列（103）。通过在需要调度测试片时，确定此时的待加工晶片，回滚到目标待加工晶片调度时间点，在目标待加工晶片调度时间点设定测试片工艺路径，实现在此时最先调度测试片，使得当需要测试片进入加工腔室时，工艺路径中的测试片可以快速被使用，节省空闲等待时间，提高半导体芯片的产能。

Description

一种晶片调度方法和一种电子设备 技术领域
本发明涉及半导体技术领域，特别是涉及一种晶片调度方法和一种电子设备。
背景技术
半导体组合设备(Cluster Tool)的产能是影响半导体芯片加工整体产能的重要影响因素之一。随着半导体芯片先进制程的不断提升，半导体组合设备加工处理芯片的工艺复杂度和控制精度也在不断提升，以获得较高的生产良品率。
目前，为了在生产过程中可以对加工腔室进行校准和清洁，出现一种新的加工工艺，在半导体组合设备中除了正常调度使用待加工的工艺晶片外，还有一种用于恢复腔室的晶片，称为测试(Dummy)片。通过将该恢复腔室的晶片送入加工腔室进行加工，来对加工腔室进行恢复和清洁。测试片的使用通常会受半导体组合设备腔室的设置和待加工晶片设置双重影响，既可以在待加工晶片开始加工前、结束后或者间隔固定片数插入一片测试片来恢复加工腔室，又可以在加工腔室累积完成若干片待加工晶片后插入一片测试片来恢复加工腔室。由于设置测试片插入规则比较复杂，不同晶片设置的测试片插入顺序也不同，加工过程中也可能会改变已有的插入顺序，难以提前预判插入时机并及时准确的将测试片送达需要恢复的加工腔室，从而导致加工腔室空闲等待测试片，降低了半导体组合设备的利用率，进而降低了半导体芯片的产能。
发明内容
鉴于上述问题，提出了本发明实施例以便提供一种克服上述问题或者至少部分地解决上述问题的一种晶片调度方法和相应的一种电子设备。
为了解决上述问题，本发明实施例公开了一种晶片调度方法，晶片包括测试片和待加工晶片，所述方法包括：
当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片，所述仿真调度序列用于调度所述待加工晶片；
将所述仿真调度序列回滚至所述目标待加工晶片对应的目标待加工晶片调度时间点；
在所述目标待加工晶片调度时间点上设定测试片工艺路径，生成可执行调度序列。
可选地，所述方法还包括：
在运行所述仿真调度序列时，获取测试片使用规则，所述测试片使用规则包括所述测试片调度时间点和所述测试片工艺路径。
可选地，所述仿真调度序列包括所述待加工晶片对应的传输路径，所述传输路径依次经过晶片装卸模块、第一机械手、校准模块、大气环境真空锁腔、真空环境真空锁腔、第二机械手；所述当仿真调度序列运行至所述测试片调度时间点时，确定目标待加工晶片，包括：
当所述仿真调度序列运行至所述测试片调度时间点时，确定是否存在处于所述传输路径的待加工晶片；
当不存在处于所述传输路径的待加工晶片时，确定所述目标待加工晶片为空；
当存在处于所述传输路径的待加工晶片时，按照所述传输路径的传输顺序对所述处于所述传输路径的待加工晶片进行排序，生成待加工晶片序列；
确定所述待加工晶片序列中末端的待加工晶片为所述目标待加工晶片。
可选地，所述目标待加工晶片为空时，所述将所述仿真调度序列回滚至所述目标待加工晶片对应的目标待加工晶片调度时间点，包括：
确定所述测试片调度时间点为所述目标待加工晶片对应的目标待加工晶片调度时间点；
将所述仿真调度序列中所述目标待加工晶片对应的目标待加工晶片调度时间点至所述测试片调度时间点内的数据删除。
可选地，当所述目标待加工晶片为所述待加工晶片序列中末端的待加工晶片时，所述将所述仿真调度序列回滚至所述目标待加工晶片对应的目标待加工晶片调度时间点，包括：
确定所述目标待加工晶片对应的当前路径点，所述当前路径点为所述第一机械手、所述校准模块、所述第二机械手、所述大气环境真空锁腔、所述真空环境真空锁腔中的一个；
计算由所述晶片装卸模块运行至所述当前路径点的运行时长；
将所述测试片调度时间点减去所述运行时长，得到所述目标待加工晶片对应的目标待加工晶片调度时间点；
将所述仿真调度序列中所述目标待加工晶片对应的目标待加工晶片调度时间点至所述测试片调度时间点内的数据删除。
可选地，所述测试片工艺路径对应有测试片优先级，所述在所述目标待加工晶片调度时间点上设定所述测试片工艺路径，生成可执行调度序列，包括：
基于所述测试片优先级，确定目标测试片工艺路径；
将所述目标测试片工艺路径添加至所述目标待加工晶片调度时间点上；
计算所述目标测试片工艺路径的工艺时长；
在所述目标待加工晶片调度时间点上，增加所述工艺时长，得到目标测试片工艺完成时间点；
在所述目标测试片工艺完成时间点上，对所述测试片优先级清零，生成可执行调度序列。
可选地，所述测试片调度时间点为多个，在所述目标待加工晶片调度时间点上设定测试片工艺路径的步骤之后，所述方法还包括：
按照时间顺序，判断所述仿真调度序列是否存在下一个测试片调度时间点；
当存在所述下一个测试片调度时间点时，确定所述下一个测试片调度时间点为所述测试片调度时间点，执行所述当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片的步骤，直至不存在所述下一个测试片调度时间点；
当不存在所述下一个测试片调度时间点时，执行所述生成可执行调度序列的步骤。
可选地，所述方法还包括：
发送所述可执行调度序列至预设半导体工艺设备，所述预设半导体工艺设备用于基于所述可执行调度序列调度所述测试片进行生产。
可选地，所述方法还包括：
记录预设半导体工艺设备的运行状态；
基于所述预设半导体工艺设备的运行状态，生成所述仿真调度序列。
本发明实施例还公开了一种电子设备，所述电子设备与半导体工艺设备连接，
所述电子设备用于执行如上所述的晶片调度方法。
本发明实施例包括以下优点：
本发明实施例通过当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片，仿真调度序列用于调度待加工晶片；将仿真调度序列回滚至目标待加工晶片对应的目标待加工晶片调度时间点；在目标待加工晶片调度 时间点上设定测试片工艺路径，生成可执行调度序列。通过在需要调度测试片时，确定此时的待加工晶片，回滚到目标待加工晶片调度时间点，在该目标待加工晶片调度时间点设定测试片工艺路径，实现在此时最先调度测试片，使得当需要测试片进入加工腔室时，工艺路径中的测试片可以快速被使用，节省空闲等待时间，从而提高了生产效率。并且测试片的调度是在正常调用待加工晶片的调度时间基础上进行，使得即使在待加工晶片调度复杂的情况下，也能准确调度，可以更快的适应不同加工工艺需求的变化，进一步提高半导体芯片的产能。
附图说明
图1是本发明实施例的一种晶片调度方法的步骤流程图；
图2是本发明实施例的另一种晶片调度方法的步骤流程图；
图3是本发明实施例的一种晶片传输路径的示意图；
图4是本发明实施例的一种晶片调度方法应用系统的示意图；
图5是本发明实施例的一种晶片调度方法示例的步骤流程图；
图6是本发明实施例的一种电子设备的结构框图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
参照图1，示出了本发明实施例的一种晶片调度方法的步骤流程图。在本发明实施例中调度的晶片包括测试片和待加工晶片。其中，测试片为Dummy片；待加工晶片为待进行加工的晶片，例如硅晶片。晶片调度方法具体可以包括如下步骤：
步骤101，当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片，仿真调度序列用于调度待加工晶片。
在半导体芯片的加工过程中，测试片和待加工晶片都处于同一台半导体组合设备中，可以采用相同的机械部分进行调度。测试片和待加工晶片的区别在于，两者存储盒所处装卸位并不相同。
在一款半导体芯片(由待加工晶片加工而成)的加工工艺确定后，即可根据工艺流程确定仿真调度序列，该仿真调度序列可用于在加工过程中，在半导体组合设备对待加工晶片进行调度。
上述仿真调度序列会按照时间顺序运行，确定加工过程中每一时间点需要执行的动作。当仿真调度序列当前运行到的时间点与测试片调度时间点匹配时，确定仿真调度序列运行至测试片调度时间点。在此时，从当前正在被调度的多个待加工晶片中确定出位置最靠近加工腔室的待加工晶片为目标待加工晶片，即处于工艺路径中但并未进行加工，且最靠近工艺路径末端的待加工晶片。其中，测试片调度时间点为加工腔室需要调度测试片入内，以对加工腔室进行清洁和校准的时间点；其与仿真调度序列采用相同的时间轴。
步骤102，将仿真调度序列回滚至目标待加工晶片对应的目标待加工晶片调度时间点。
在确定目标待加工晶片后，可以在仿真调度序列中，确定该目标待加工晶片已经执行的动作，根据执行这些动作的时间，计算出该目标待加工晶片开始调度的时间点，即为目标待加工晶片对应的目标待加工晶片调度时间点。在确定目标待加工晶片调度时间点之后，将仿真调度序列从当前时间点回滚至目标待加工晶片调度时间点，从目标待加工晶片调度时间点重新进行运行。
步骤103，在目标待加工晶片调度时间点上设定测试片工艺路径，生成可执行调度序列。
仿真调度序列回滚至目标待加工晶片调度时间点时，在该目标待加工晶 片调度时间点上设定测试片工艺路径，即仿真调度序列在该目标待加工晶片调度时间点上，执行的动作即为根据测试片工艺路径调度测试片。在全部需要调度测试片的时间点上，都设定有对应的测试片工艺路径后，将更新后的仿真调度序列确定为可执行调度序列。可执行调度序列即为可以满足调度测试片需求的实际作业控制序列。
本发明实施例通过当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片，仿真调度序列用于调度待加工晶片；将仿真调度序列回滚至目标待加工晶片对应的目标待加工晶片调度时间点；在目标待加工晶片调度时间点上设定测试片工艺路径，生成可执行调度序列。通过在需要调度测试片时，确定此时的待加工晶片，回滚至目标待加工晶片调度时间点，在该目标待加工晶片调度时间点设定测试片工艺路径，实现在此时最先调度测试片，使得当需要调度测试片进入加工腔室时，工艺路径中的测试片可以快速被调度使用，节省空闲等待时间，从而提高了生产效率。并且测试片的调度是在正常调用待加工晶片的调度时间基础上进行，使得即使在待加工晶片调度复杂的情况下，也能准确调度，可以更快的适应不同加工工艺需求的变化，进一步提高半导体芯片的产能。
参照图2，示出了本发明实施例的另一种晶片调度方法的步骤流程图。调度的晶片包括测试片和待加工晶片；调度方法具体可以包括如下步骤：
步骤201，记录预设半导体工艺设备的运行状态。
在本发明实施例中，由于不同的半导体工艺设备的运行存在差异，可以将需要在加工过程中调度使用测试片的半导体工艺设备作为进行动作仿真模拟的半导体工艺设备，即预设半导体工艺设备。可以记录该半导体工艺设备的运行状态。即记录该半导体工艺设备在不考虑潜在测试片需求的情况下的所有过程动作和状态。
步骤202，基于预设半导体工艺设备的运行状态生成仿真调度序列。
将记录的预设半导体工艺设备的运行状态作为配置数据，生成仿真调度序列，并开始启动该仿真调度序列对预设半导体工艺设备的动作进行模拟仿真，基于时间顺序，执行仿真调度序列的动作从指定的晶片盒中取出待加工晶片进行调度。
步骤203，在运行仿真调度序列时，获取测试片使用规则，测试片使用规则包括测试片调度时间点和测试片工艺路径。
在实际应用中，运行仿真调度序列，执行对应的动作来调度待加工晶片，对半导体组合设备的动作进行模拟仿真。在该仿真调度序列开始的同时可以获取测试片使用规则。该测试片使用规则用于确定需要调度测试片时刻，以及调度测试片的路径。因此，该测试片使用规则包括测试片调度时间点和测试片工艺路径。其中，测试片工艺路径为在调度测试片时，测试片经过的路径。
该测试片使用规则为根据待加工晶片的工艺要求和预设半导体工艺设备的加工腔室的设定共同确定的信息，对于测试片使用规则的测试片调度时间点确定并不做具体限定。举例而言，待加工晶片的工艺要求为在job(工艺)开始前、间隔固定加工待加工晶片的片数、job结束后都需要测试片；预设半导体工艺设备的加工腔室设定要求为当加工腔室空闲一段时间后、连续执行固定片数待加工晶片后需要测试片。从而基于该条件对应有唯一的测试片调度时间点和测试片工艺路径。其中，测试片调度时间点与仿真调度序列运行的时间是处于同一时间轴上。时间点的方式可以采用相对时间的方式表达，举例而言，以仿真调度序列开始运行的时刻为“0”，后续的测试片调度时间点可以采用10秒来表示；即测试片调度时间点在仿真调度序列运行后的第10秒。对应时间点的精度则可以根据生产要求确定，在此不对时间的精度进行限定。
对于测试片使用规则可以从指定存储空间地址中获取。该指定存储空间 可以为本地存储空间地址，也可以为第三方存储空间地址。本发明实施例对此不作具体限定。
步骤204，当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片。
仿真调度序列按照时间顺序运行执行对应动作，当仿真调度序列运行的时间点与测试片调度时间点匹配时，确定仿真调度序列运行至测试片调度时间点。继续以上述例子进行说明，当仿真调度序列运行至第10秒时，确定仿真调度序列运行至测试片调度时间点。
在仿真调度序列中，确定在测试片调度时间点，处于工艺路径中但并未进行加工的待加工晶片。从处于工艺路径中但并未进行加工的待加工晶片确定最靠近工艺路径末端的待加工晶片为目标待加工晶片。其中，若在测试片调度时间点时，并不存在工艺路径中但并未进行加工的待加工晶片，可以确定目标待加工晶片为空。
可选地，仿真调度序列包括待加工晶片对应传输路径，该传输路径依次经过晶片装卸模块、第一机械手、校准模块、大气环境真空锁腔、真空环境真空锁腔、第二机械手；
参照图3，在一个待加工晶片加工成半导体芯片对应的工艺路径为晶片装卸模块(LoadPort)、第一机械手(ATM)、校准模块(Aligner)、大气环境真空锁腔(LoadLock的其中一个槽位)、真空环境真空锁腔(LoadLock的另一个槽位)、第二机械手(VTM)、加工腔室(PM1、PM2、PM3、PM4)、第二机械手、真空环境真空锁腔、大气环境真空锁腔、第一机械手、晶片装卸模块。其中，传输路径即为处于工艺路径中但并未进行加工时待加工晶片经过的路径，即依次经过晶片装卸模块、第一机械手、校准模块、大气环境真空锁腔、真空环境真空锁腔、第二机械手。其中，第一机械手可以为单臂机械手、第二机械手可以为双臂机械手。
当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片，包括：
子步骤S2041，当仿真调度序列运行至测试片调度时间点时，确定是否存在处于传输路径的待加工晶片；
确定当仿真调度序列运行至测试片调度时间点时，在传输路径上是否存在待加工晶片。具体地，可以逐一确定晶片装卸模块、第一机械手、校准模块、大气环境真空锁腔、真空环境真空锁腔、第二机械手位置上是否存在待加工晶片，如果其中一个路径点上存在待加工晶片，即可确定存在处于传输路径的待加工晶片。如果在晶片装卸模块、第一机械手、校准模块、大气环境真空锁腔、真空环境真空锁腔、第二机械手位置上都不存在待加工晶片，则确定不存在处于传输路径的待加工晶片。
子步骤S2042，当不存在处于传输路径的待加工晶片时，确定目标待加工晶片为空；
当不存在处于传输路径的待加工晶片时，即当前传输路径上并没有待加工晶片，可以确定目标待加工晶片为空。
子步骤S2043，当存在处于传输路径的待加工晶片时，按照传输路径的传输顺序对处于传输路径的待加工晶片进行排序，生成待加工晶片序列；
当存在处于传输路径的待加工晶片时，需要进一步地按照传输路径的传输顺序对处于传输路径的待加工晶片进行排序。将目前处于传输路径的待加工晶片按照处于晶片装卸模块、第一机械手、校准模块、大气环境真空锁腔、真空环境真空锁腔、第二机械手的顺序进行排序，得到的序列即为待加工晶片序列。
子步骤S2044，确定待加工晶片序列中末端的待加工晶片为目标待加工晶片。
在待加工晶片序列中，越靠近末端即越靠近加工腔室，即更快可以进入 到加工腔室中。因此，可以确定待加工晶片序列中末端的待加工晶片为目标待加工晶片，令后续替换为测试片时，测试片可以更快进入到加工腔室。
步骤205，将仿真调度序列回滚至目标待加工晶片对应的目标待加工晶片调度时间点。
根据目标待加工晶片在传输路径上的位置点，计算目标待加工晶片从晶片传输到该位置点执行的全部动作对应时间，基于该时间在仿真调度序列中，确定出目标待加工晶片调度时间点。其中，对于目标待加工晶片调度时间点的确定可以根据目标待加工晶片的类型确定。
然后将仿真调度序列回滚至目标待加工晶片调度时间点，使得可以在目标待加工晶片调度时间点处调整仿真调度序列的下一步动作。
具体地，当目标待加工晶片为空时，将仿真调度序列回滚至目标待加工晶片对应的目标待加工晶片调度时间点，包括：
子步骤S2051，确定测试片调度时间点为目标待加工晶片对应的目标待加工晶片调度时间点。
在实际应用中，当目标待加工晶片为空时，即仿真调度序列在测试片调度时间点上时，并不存在已经出晶片装卸模块而未进行加工腔室的待加工晶片，测试片此时可以直接调用，目标待加工晶片对应的调度时间为零，确定测试片调度时间点为目标待加工晶片调度时间点。
子步骤S2052，将仿真调度序列中目标待加工晶片对应的目标待加工晶片调度时间点至测试片调度时间点内的数据删除。
对于仿真调度序列回滚方式，是将仿真调度序列中目标待加工晶片调度时间点至测试片调度时间点内的数据删除。
在实际应用中，可以将从目标待加工晶片调度时间点至测试片调度时间点这一段时间内，仿真调度序列中执行的动作以及参数等数据全部删除，并将当前时间点回退至目标待加工晶片调度时间点。
当目标待加工晶片为待加工晶片序列中末端的待加工晶片时，将仿真调度序列回滚至目标待加工晶片对应的目标待加工晶片调度时间点，包括：
子步骤S2053，确定目标待加工晶片对应的当前路径点，当前路径点为第一机械手、校准模块、第二机械手、大气环境真空锁腔、真空环境真空锁腔中的一个；
当存在目标待加工晶片时，确定该目标待加工晶片当前时刻在传输路径上的当前路径点。其中，当前路径点为第一机械手、校准模块、大气环境真空锁腔、真空环境真空锁腔、第二机械手中的其中一个。
子步骤S2054，计算由晶片装卸模块运行至当前路径点的运行时长；
第一机械手、校准模块、大气环境真空锁腔、真空环境真空锁腔、第二机械手对应有动作时长，每个当前路径点对应动作时长根据在实际加工时，半导体工艺设备的在该动作运行的时长确定。根据目标待加工晶片的当前路径点对应的动作时长，计算出目标待加工晶片由晶片装卸模块运行至当前路径点的运行时长。
举例而言，第一机械手的动作时长为1秒、校准模块的动作时长为2秒、大气环境真空锁腔的动作时长为1秒、真空环境真空锁腔的动作时长为1秒、第二机械手的动作时长为1秒。目标待加工晶片的当前路径点为大气环境真空锁腔，即目标待加工晶片由晶片装卸模块运行至大气环境真空锁腔的运行时长为4秒(第一机械手的动作时长、校准模块的动作时长和大气环境真空锁腔的动作时长之和)。
子步骤S2055，将测试片调度时间点减去运行时长，得到目标待加工晶片对应的目标待加工晶片调度时间点。
将测试片调度时间点减去运行时长，得到的时间点即为目标待加工晶片对应目标待加工晶片调度时间点。在仿真调度序列在该目标待加工晶片调度时间点时开始调度目标待加工晶片。
子步骤S2056，将仿真调度序列中目标待加工晶片对应的目标待加工晶片调度时间点至测试片调度时间点内的数据删除。
对于仿真调度序列回滚方式，是将仿真调度序列中目标待加工晶片调度时间点至测试片调度时间点内的数据删除。可以将从目标待加工晶片调度时间点至测试片调度时间点这一段时间内，仿真调度序列中执行的动作以及参数等数据全部删除，并在当前时间为回退至目标待加工晶片调度时间点。
步骤206，在目标待加工晶片调度时间点上设定测试片工艺路径，生成可执行调度序列。
在目标待加工晶片调度时间点上设定测试片工艺路径，并将调度测试片的优先级提升至最高级别，使得仿真调度序列在运行到目标待加工晶片调度时间点时，优先调度测试片。在全部测试片的调度需求都满足后，将更新后的仿真调度序列确定为可执行调度序列。其中，对于测试片工艺路径可以根据测试片从其装卸位至目标加工腔室，再回到其装卸位的实际路径确定。
具体地，测试片工艺路径对应有测试片优先级，在目标待加工晶片调度时间点上设定测试片工艺路径，生成可执行调度序列，包括：
子步骤S2061，基于测试片优先级，确定目标测试片工艺路径；
在实际应用中，在测试片使用规则的测试片工艺路径会存在多条，但是在某一时间点，测试片工艺路径对应的优先级并不相同，优先级最高的测试片工艺路径即为当前所需要的测试片工艺路径。因此，可以基于测试片优先级，从测试片工艺路径中，确定优先级最高的测试片工艺路径为目标测试片工艺路径。
子步骤S2062，将目标测试片工艺路径添加至目标待加工晶片调度时间点上；
将目标测试片工艺路径添加至目标待加工晶片调度时间点，即在目标待加工晶片调度时间点后的下一步动作即为执行目标测试片工艺路径调度测试 片。
子步骤S2063，计算目标测试片工艺路径的工艺时长；
并且根据目标测试片工艺路径中经过的每一个路径点，对应的动作时长，计算出完成整个目标测试片工艺路径所需要的工艺时长。
举例而言，如图3所示，目标测试片工艺路径为测试片装卸模块(DummyPort)、第一机械手(ATM)、校准模块(Aligner)、大气环境真空锁腔(LoadLock其中一个槽位)、真空环境真空锁腔(LoadLock另一个槽位)、第二机械手(VTM)、(、加工腔室(PM1、PM2、PM3、PM4)、第二机械手、真空环境真空锁腔、大气环境真空锁腔、第一机械手、测试片装卸模块。依次对应动作时长为1秒、1秒、2秒、1秒、1秒、2秒、3秒、2秒、1秒、1秒、1秒、1秒。工艺时长即为17秒(目标测试片工艺路径全部路径点对应动作时长之和)。
子步骤S2064，在目标待加工晶片调度时间点上，增加工艺时长，得到目标测试片工艺完成时间点；
再基于目标待加工晶片调度时间点，在此基础上增加工艺时长，得到的时间点确定为目标测试片工艺完成时间点。以该目标测试片工艺完成时间点表征当前测试片完成的时间点。
子步骤S2065，在目标测试片工艺完成时间点上，对测试片优先级清零，生成可执行调度序列。
在该目标测试片工艺完成时间点上，将测试片优先级清零，使得仿真调度序列在该目标测试片工艺完成时间点上不继续调度测试片，等待下一次优先级更高的测试片工艺再进行调度；以此更新仿真调度序列，生成可执行调度序列。
此外，可能会存在多个不同的加工腔室需要调度使用测试片的情况，即，存在测试片调度时间点为多个的情况，此时，在目标待加工晶片调度时间点 上设定测试片工艺路径的步骤之后，按照时间顺序判断仿真调度序列是否存在下一个测试片调度时间点；
具体地，可以循环判断不同加工腔室是否存在调度使用测试片的需求，当存在调度需求即存在下一个测试片调度时间点；否则即不存在下一个测试片调度时间点，当前的下一个测试片调度时间点是预设半导体工艺设备最后一个需要调度测试片调度的时间点。
当存在下一个测试片调度时间点时，确定下一个测试片调度时间点为测试片调度时间点，执行当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片的步骤，直至不存在下一个测试片调度时间点；
具体地，当存在下一个测试片调度时间点时，当前更新的仿真调度序列并不能作为控制预设半导体工艺设备加工的可执行调度序列。需要继续在仿真调度序列中更新调度测试片的动作。为此，可以将下一个测试片调度时间点确定为测试片调度时间点，以该测试片调度时间点继续执行仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片的步骤，确定出新的目标待加工晶片，和对应的目标待加工晶片调度时间点，从而在新的目标待加工晶片调度时间点插入调度测试片的动作，进一步更新仿真调度序列；直至不存在下一个测试片调度时间点。
当不存在下一个测试片调度时间点时，执行生成可执行调度序列的步骤。
当不存在下一个测试片调度时间点，说明每个加工腔室调度测试片的需求都得到满足，此时更新的仿真调度序列即可准确控制预设半导体工艺设备对半导体芯片进行生产。执行生成可执行调度序列的步骤，将此时更新得到的仿真调度序列确定为可执行调度序列。
步骤207，发送可执行调度序列至预设半导体工艺设备，预设半导体工艺设备用于基于可执行调度序列调度测试片进行生产。
生成可执行调度序列后，可以将可执行调度序列发送至预设半导体工艺设备。预设半导体工艺设备接收该可执行调度序列，基于该可执行调度序列中的动作控制对应模块运行，生产半导体芯片。
本发明实施例中，通过在运行仿真调度序列时进行测试片调用调整，由于各种不同类型的晶片的仿真调度序列并不存在本质性差异，使得本发明实施例的测试片调度方法具有较好的通用性，可以支持各种不同类型的晶片。并且运行仿真调度序列调度待加工晶片时，并行调整测试片调度，令调度待加工晶片与调度测试片的逻辑解耦，两者相互独立，可以更快的适应不同工艺需求的变化。在加工腔室需要测试片的时候，通过找到传输工艺路径中加工腔室最近的待加工晶片并确定其调用时间，然后通过回滚到目标待加工晶片调用时间，调整测试片的优先级实现测试片最早出片，并重新调度，达到当加工腔室需要测试片的时候，工艺路径中的测试片最接近该加工腔室，节省了加工腔室的空闲等待时间，进而提高了半导体芯片的产能。
为了使本领域技术人员能够更好地理解本发明实施例步骤，下面通过一个例子加以说明：
参照图4，示出了本发明实施例的一种晶片调度方法应用系统的示意图。该应用系统具体可以包括如下五个模块：
优化调度模块：采用有限状态机、扩展有限状态机等优化调度算法，根据模拟仿真的系统实时状态，实现在不考虑潜在测试片需求的情况下可以优化计算出最优的调度策略(仿真调度序列)。
模拟仿真模块：对半导体组合设备各个设备单元的模拟仿真，可以用于模拟实际半导体工艺设备的工序控制执行过程。
Dummy需求逻辑判断模块：根据模拟仿真的系统状态，按照测试片使用规则的逻辑，判断各个加工腔室在此仿真状态下是否需要测试片使用规则，输出需要的测试片使用规则信息；
状态回滚模块：确定回滚时间点，触发模拟仿真模块进行状态回滚，并修改模拟仿真模块中对应测试片的工艺路径和优先级；
调度序列输出模块：根据仿真模拟系统记录的调度动作序列，整理输出调度序列清单(可执行序列)。
具体地，晶片调度方法流程可以参照图5。
步骤一：利用计算机程序实现对机台的模拟仿真，记录机台所有过程动作和状态，并根据实际半导体组合设备状态初始化或更新仿真程序；
步骤二：对LoadPort(待加工晶片装卸位)和DummyPort(测试片装卸位)内待加工晶片按照优先级高低顺序出栈；
步骤三：利用优化调度算法，在不考虑潜在dummy需求的情况下(即将测试片作为待加工晶片调度)求解出调度序列(仿真调度序列)；
步骤四：运行仿真程序，在仿真程序中按照时间顺序执行下一步动作；如果下一步动作为完成工艺的Dummy片(测试片)回到DummyPort(测试片装卸位)则清空Dummy片的工艺路径和优先级。
步骤五：判断是否所有的(测试片)调度任务完成，如果是，则执行步骤六，否则执行步骤七；
步骤六：整理输出仿真程序记录的所有过程动作即为机台可执行调度序列，程序结束，输出可执行调度序列；
步骤七：根据Dummy片的使用逻辑规则(测试片使用规则)循环判断各个pm(加工腔室)当前是否需要Dummy片，如果所有pm都不需要则执行步骤四，否则执行步骤八。
步骤八：记录需要dummy片的pm为PM_dummy(目标加工腔室)，如果有多个pm需要dummy片则按照优先级选择一个pm记录。
步骤九：判断是否有已经出LoadPort(待加工晶片装卸位)且未工艺的晶片(即搬运路径上的待加工晶片)，如果有则执行步骤十，否则执行步骤 十一；
步骤十：找到在LoadPort(待加工晶片装卸位)->ATM(第一机械手)->Aligner(校准模块)->ATM(第二机械手)->LoadLock大气环境(大气环境真空锁腔)->LoadLock真空环境(真空环境真空锁腔)步骤中最靠后的待加工晶片；
获取此晶片从LoadPort离开时的时间点为T2(目标待加工晶片调度时间点)；将仿真系统所有设备、晶片和Dummy片状态回滚到T2时间点，删除仿真程序中所有从T2到当前时间的动作和状态记录。
步骤十一：根据Dummy片的优先级找出最先出的Dummy片；初始化此Dummy片的工艺路径，并设定目标pm为PM_dummy；将此Dummy片视为待加工晶片调度，并将优先级设为最高；转向执行步骤二。
需要说明的是，对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明实施例并不受所描述的动作顺序的限制，因为依据本发明实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定是本发明实施例所必须的。
参照图6，示出本发明实施例的一种电子设备的结构框图；电子设备601与半导体工艺设备连接，
电子设备601用于执行如上的晶片调度方法。
对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
本发明实施例还提供了一种计算机可读存储介质，计算机可读存储介质上存储计算机程序，计算机程序被处理器执行时实现上述测试片调度方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明 的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
本领域内的技术人员应明白，本发明实施例的实施例可提供为方法、装置、或计算机程序产品。因此，本发明实施例可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明实施例可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明实施例是参照根据本发明实施例的方法、终端设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理终端设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理终端设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理终端设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理终端设备上，使得在计算机或其他可编程终端设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程终端设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本发明实施例的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明实施例范围的所有变更和修改。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者终端设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者终端设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者终端设备中还存在另外的相同要素。
以上对本发明所提供的一种晶片调度方法和一种电子设备，进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本发明的限制。

Claims (10)

  1. 一种晶片调度方法，其特征在于，所述晶片包括测试片和待加工晶片，所述方法包括：
    当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片，所述仿真调度序列用于调度所述待加工晶片；
    将所述仿真调度序列回滚至所述目标待加工晶片对应的目标待加工晶片调度时间点；
    在所述目标待加工晶片调度时间点上设定测试片工艺路径，生成可执行调度序列。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    在运行所述仿真调度序列时，获取测试片使用规则，所述测试片使用规则包括所述测试片调度时间点和所述测试片工艺路径。
  3. 根据权利要求1所述的方法，其特征在于，所述仿真调度序列包括所述待加工晶片对应的传输路径，所述传输路径依次经过晶片装卸模块、第一机械手、校准模块、大气环境真空锁腔、真空环境真空锁腔、第二机械手；所述当仿真调度序列运行至所述测试片调度时间点时，确定目标待加工晶片，包括：
    当所述仿真调度序列运行至所述测试片调度时间点时，确定是否存在处于所述传输路径的待加工晶片；
    当不存在处于所述传输路径的待加工晶片时，确定所述目标待加工晶片为空；
    当存在处于所述传输路径的待加工晶片时，按照所述传输路径的传输顺序对所述处于所述传输路径的待加工晶片进行排序，生成待加工晶片序列；
    确定所述待加工晶片序列中末端的待加工晶片为所述目标待加工晶片。
  4. 根据权利要求3所述的方法，其特征在于，所述目标待加工晶片为空时，所述将所述仿真调度序列回滚至所述目标待加工晶片对应的目标待加工晶片调度时间点，包括：
    确定所述测试片调度时间点为所述目标待加工晶片对应的目标待加工晶片调度时间点；
    将所述仿真调度序列中所述目标待加工晶片对应的目标待加工晶片调度时间点至所述测试片调度时间点内的数据删除。
  5. 根据权利要求3所述的方法，其特征在于，当所述目标待加工晶片为所述待加工晶片序列中末端的待加工晶片时，所述将所述仿真调度序列回滚至所述目标待加工晶片对应的目标待加工晶片调度时间点，包括：
    确定所述目标待加工晶片对应的当前路径点，所述当前路径点为所述第一机械手、所述校准模块、所述第二机械手、所述大气环境真空锁腔、所述真空环境真空锁腔中的一个；
    计算由所述晶片装卸模块运行至所述当前路径点的运行时长；
    将所述测试片调度时间点减去所述运行时长，得到所述目标待加工晶片对应的目标待加工晶片调度时间点；
    将所述仿真调度序列中所述目标待加工晶片对应的目标待加工晶片调度时间点至所述测试片调度时间点内的数据删除。
  6. 根据权利要求1所述的方法，其特征在于，所述测试片工艺路径对应有测试片优先级，所述在所述目标待加工晶片调度时间点上设定所述测试片工艺路径，生成可执行调度序列，包括：
    基于所述测试片优先级，确定目标测试片工艺路径；
    将所述目标测试片工艺路径添加至所述目标待加工晶片调度时间点上；
    计算所述目标测试片工艺路径的工艺时长；
    在所述目标待加工晶片调度时间点上，增加所述工艺时长，得到目标测试片工艺完成时间点；
    在所述目标测试片工艺完成时间点上，对所述测试片优先级清零，生成可执行调度序列。
  7. 根据权利要求6所述的方法，其特征在于，所述测试片调度时间点为多个，在所述目标待加工晶片调度时间点上设定测试片工艺路径的步骤之后，所述方法还包括：
    按照时间顺序，判断所述仿真调度序列是否存在下一个测试片调度时间点；
    当存在所述下一个测试片调度时间点时，确定所述下一个测试片调度时间点为所述测试片调度时间点，执行所述当仿真调度序列运行至测试片调度时间点时，确定目标待加工晶片的步骤，直至不存在所述下一个测试片调度时间点；
    当不存在所述下一个测试片调度时间点时，执行所述生成可执行调度序列的步骤。
  8. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    发送所述可执行调度序列至预设半导体工艺设备，所述预设半导体工艺设备用于基于所述可执行调度序列调度所述测试片进行生产。
  9. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    记录预设半导体工艺设备的运行状态；
    基于所述预设半导体工艺设备的运行状态，生成所述仿真调度序列。
  10. 一种电子设备，其特征在于，所述电子设备与半导体工艺设备连接，
    所述电子设备用于执行权利要求1-9任一项所述的晶片调度方法。
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