WO2024088294A1

WO2024088294A1 - Wafer dispatching method and electronic device

Info

Publication number: WO2024088294A1
Application number: PCT/CN2023/126409
Authority: WO
Inventors: 李�杰; 张璐; 刘慕雅; 曾为鹏
Original assignee: 北京北方华创微电子装备有限公司
Priority date: 2022-10-26
Filing date: 2023-10-25
Publication date: 2024-05-02
Also published as: CN115794506B; CN115794506A

Abstract

Provided are a wafer dispatching method and an electronic device. The wafer dispatching method comprises: when a simulation dispatching sequence runs to a test wafer dispatching time point, determining a target wafer to be processed, the simulation dispatching sequence being used for dispatching wafers to be processed (101); rolling back the simulation dispatching sequence to a target wafer to be processed dispatching time point corresponding to the target wafer to be processed (102); and setting a test wafer process path on the target wafer to be processed dispatching time point, and generating an executable dispatching sequence (103). When a test wafer needs to be dispatched, a wafer to be processed at this time is determined, rollback to a target wafer to be processed dispatching time point is enabled, and a test wafer process path is set at the target wafer to be processed dispatching time point, so that the test wafer is first dispatched at this time. Therefore, when the test wafer is required to enter a processing chamber, the test wafer in the process path can be quickly used, the idle waiting time is saved, and the productivity of semiconductor chips is improved.

Description

A chip scheduling method and an electronic device

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a wafer scheduling method and an electronic device.

Background technique

The production capacity of semiconductor cluster tools is one of the important factors affecting the overall production capacity of semiconductor chip processing. With the continuous improvement of advanced semiconductor chip manufacturing processes, the process complexity and control accuracy of semiconductor cluster tools for processing chips are also constantly improving to obtain a higher production yield.

At present, in order to calibrate and clean the processing chamber during the production process, a new processing technology has emerged. In addition to the normal scheduling of the process wafers to be processed in the semiconductor assembly equipment, there is also a wafer for restoring the chamber, called a test (Dummy) wafer. The processing chamber is restored and cleaned by sending the wafer of the recovery chamber into the processing chamber for processing. The use of the test piece is usually affected by the setting of the chamber of the semiconductor assembly equipment and the setting of the wafer to be processed. A test piece can be inserted before the processing of the wafer to be processed, after the processing is completed, or at a fixed interval to restore the processing chamber. A test piece can also be inserted after the processing chamber accumulates several wafers to be processed to restore the processing chamber. Since the setting of the test piece insertion rule is relatively complicated, the insertion order of the test piece for different wafer settings is also different, and the existing insertion order may also be changed during the processing process. It is difficult to predict the insertion time in advance and deliver the test piece to the processing chamber that needs to be restored in a timely and accurate manner, resulting in the processing chamber being idle waiting for the test piece, reducing the utilization rate of the semiconductor assembly equipment, and thus reducing the production capacity of semiconductor chips.

Summary of the invention

In view of the above problems, embodiments of the present invention are proposed to provide a wafer scheduling method and a corresponding electronic device that overcome the above problems or at least partially solve the above problems.

In order to solve the above problems, an embodiment of the present invention discloses a wafer scheduling method, wherein the wafer includes a test wafer and a wafer to be processed, and the method includes:

When the simulation scheduling sequence runs to the test wafer scheduling time point, a target wafer to be processed is determined, and the simulation scheduling sequence is used to schedule the wafer to be processed;

Rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed;

A test wafer process path is set at the target wafer to be processed scheduling time point to generate an executable scheduling sequence.

Optionally, the method further comprises:

When the simulation scheduling sequence is run, a test piece usage rule is obtained, wherein the test piece usage rule includes the test piece scheduling time point and the test piece process path.

Optionally, the simulation scheduling sequence includes a transmission path corresponding to the wafer to be processed, and the transmission path sequentially passes through a wafer loading and unloading module, a first manipulator, a calibration module, an atmospheric environment vacuum lock chamber, a vacuum environment vacuum lock chamber, and a second manipulator; when the simulation scheduling sequence runs to the test piece scheduling time point, determining the target wafer to be processed includes:

When the simulation scheduling sequence runs to the test piece scheduling time point, determining whether there is a wafer to be processed in the transmission path;

When there is no wafer to be processed in the transmission path, determining that the target wafer to be processed is empty;

When there are wafers to be processed on the transmission path, the wafers to be processed on the transmission path are sorted according to the transmission order of the transmission path to generate a sequence of wafers to be processed;

The wafer to be processed at the end of the sequence of wafers to be processed is determined as the target wafer to be processed.

Optionally, when the target wafer to be processed is empty, rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed includes:

Determine the test wafer scheduling time point as the target wafer to be processed scheduling time point corresponding to the target wafer to be processed;

The data from the target wafer to be processed scheduling time point to the test wafer scheduling time point corresponding to the target wafer to be processed in the simulation scheduling sequence is deleted.

Optionally, when the target wafer to be processed is the last wafer to be processed in the sequence of wafers to be processed, rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed includes:

Determine a current path point corresponding to the target wafer to be processed, wherein the current path point is one of the first manipulator, the calibration module, the second manipulator, the atmospheric environment vacuum lock chamber, and the vacuum environment vacuum lock chamber;

Calculating the running time from the wafer handling module to the current path point;

Subtract the running time from the test wafer scheduling time point to obtain a target wafer to be processed scheduling time point corresponding to the target wafer to be processed;

Optionally, the test wafer process path corresponds to a test wafer priority, and the test wafer process path is set at the target wafer to be processed scheduling time point to generate an executable scheduling sequence, including:

Based on the test piece priority, determining a target test piece process path;

Adding the target test wafer process path to the target wafer to be processed scheduling time point;

Calculating the process duration of the process path of the target test piece;

At the target wafer to be processed scheduling time point, the process duration is added to obtain the target test wafer process completion time point;

At the time point when the process of the target test piece is completed, the priority of the test piece is cleared to generate an executable scheduling sequence.

Optionally, there are multiple test piece scheduling time points, and after the step of setting the test piece process path at the target wafer to be processed scheduling time point, the method further includes:

According to the time sequence, determine whether there is a next test piece scheduling time point in the simulation scheduling sequence;

When the next test piece scheduling time point exists, determining the next test piece scheduling time point as the test piece scheduling time point, and executing the step of determining the target wafer to be processed when the simulation scheduling sequence runs to the test piece scheduling time point until the next test piece scheduling time point does not exist;

When the next test piece scheduling time point does not exist, the step of generating an executable scheduling sequence is performed.

Optionally, the method further comprises:

The executable scheduling sequence is sent to a preset semiconductor process equipment, and the preset semiconductor process equipment is used to schedule the test piece for production based on the executable scheduling sequence.

Optionally, the method further comprises:

Record the operating status of preset semiconductor process equipment;

The simulation scheduling sequence is generated based on the operating status of the preset semiconductor process equipment.

The embodiment of the present invention further discloses an electronic device, which is connected to a semiconductor process device.

The electronic device is used to execute the wafer scheduling method as described above.

The embodiments of the present invention include the following advantages:

The embodiment of the present invention determines the target wafer to be processed when the simulation scheduling sequence runs to the test wafer scheduling time point, and the simulation scheduling sequence is used to schedule the wafer to be processed; rolls back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed; and schedules the target wafer to be processed. The process path of the test piece is set at a time point to generate an executable scheduling sequence. When the test piece needs to be scheduled, the wafer to be processed at this time is determined, and the target wafer to be processed scheduling time point is rolled back. The process path of the test piece is set at the target wafer to be processed scheduling time point, so that the test piece is scheduled first at this time, so that when the test piece is needed to enter the processing chamber, the test piece in the process path can be used quickly, saving idle waiting time, thereby improving production efficiency. In addition, the scheduling of the test piece is performed on the basis of the normal scheduling time of the wafer to be processed, so that even in the case of complex scheduling of the wafer to be processed, it can be accurately scheduled, and it can adapt to changes in different processing technology requirements more quickly, further improving the production capacity of semiconductor chips.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of the steps of a wafer scheduling method according to an embodiment of the present invention;

FIG2 is a flowchart of another wafer scheduling method according to an embodiment of the present invention;

FIG3 is a schematic diagram of a wafer transmission path according to an embodiment of the present invention;

FIG4 is a schematic diagram of an application system of a wafer scheduling method according to an embodiment of the present invention;

FIG5 is a flowchart of an exemplary wafer scheduling method according to an embodiment of the present invention;

FIG. 6 is a structural block diagram of an electronic device according to an embodiment of the present invention.

Detailed ways

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

Referring to FIG. 1 , a flow chart of the steps of a wafer scheduling method according to an embodiment of the present invention is shown. The wafers scheduled in the embodiment of the present invention include a test wafer and a wafer to be processed. The test wafer is a dummy wafer; the wafer to be processed is a wafer to be processed, such as a silicon wafer. The wafer scheduling method may specifically include the following steps:

Step 101, when the simulation scheduling sequence runs to the test wafer scheduling time point, the target wafer to be processed is determined, and the simulation scheduling sequence is used to schedule the wafer to be processed.

During the processing of semiconductor chips, the test wafer and the wafer to be processed are both in the same semiconductor assembly equipment and can be dispatched using the same mechanical parts. The difference between the test wafer and the wafer to be processed is that the storage boxes of the two are located at different loading and unloading positions.

After the processing technology of a semiconductor chip (made from the wafer to be processed) is determined, a simulation scheduling sequence can be determined according to the process flow. The simulation scheduling sequence can be used to schedule the wafer to be processed in the semiconductor assembly equipment during the processing.

The above-mentioned simulation scheduling sequence will run in chronological order to determine the actions that need to be performed at each time point in the processing process. When the time point that the simulation scheduling sequence is currently running to matches the test piece scheduling time point, it is determined that the simulation scheduling sequence runs to the test piece scheduling time point. At this time, the wafer to be processed that is closest to the processing chamber is determined from the multiple wafers to be processed that are currently being scheduled as the target wafer to be processed, that is, the wafer to be processed that is in the process path but has not been processed, and is closest to the end of the process path. Among them, the test piece scheduling time point is the time point when the processing chamber needs to schedule the test piece to enter in order to clean and calibrate the processing chamber; it uses the same timeline as the simulation scheduling sequence.

Step 102 , rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed.

After determining the target wafer to be processed, the actions that have been executed by the target wafer to be processed can be determined in the simulation scheduling sequence, and the time point at which the target wafer to be processed starts to be scheduled can be calculated according to the time of executing these actions, which is the target wafer to be processed scheduling time point corresponding to the target wafer to be processed. After determining the target wafer to be processed scheduling time point, the simulation scheduling sequence is rolled back from the current time point to the target wafer to be processed scheduling time point, and is re-run from the target wafer to be processed scheduling time point.

Step 103, setting a test wafer process path at the target wafer to be processed scheduling time point, and generating an executable scheduling sequence.

When the simulation scheduling sequence rolls back to the scheduling time point of the target wafer to be processed, The test piece process path is set at the wafer scheduling time point, that is, the action performed by the simulation scheduling sequence at the target wafer to be processed scheduling time point is to schedule the test piece according to the test piece process path. After the corresponding test piece process path is set at all the time points where the test piece needs to be scheduled, the updated simulation scheduling sequence is determined as the executable scheduling sequence. The executable scheduling sequence is the actual operation control sequence that can meet the scheduling requirements of the test piece.

The embodiment of the present invention determines the target wafer to be processed when the simulation scheduling sequence runs to the test piece scheduling time point, and the simulation scheduling sequence is used to schedule the wafer to be processed; rolls back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed; sets the test piece process path at the target wafer to be processed scheduling time point to generate an executable scheduling sequence. When the test piece needs to be scheduled, the wafer to be processed at this time is determined, rolled back to the target wafer to be processed scheduling time point, and the test piece process path is set at the target wafer to be processed scheduling time point, so that the test piece is first scheduled at this time, so that when the test piece needs to be scheduled to enter the processing chamber, the test piece in the process path can be quickly scheduled for use, saving idle waiting time, thereby improving production efficiency. In addition, the scheduling of the test piece is performed on the basis of the normal scheduling time of the wafer to be processed, so that even in the case of complex scheduling of the wafer to be processed, it can be accurately scheduled, and can adapt to changes in different processing technology requirements more quickly, further improving the production capacity of semiconductor chips.

2, a flowchart of another wafer scheduling method according to an embodiment of the present invention is shown. The wafers to be scheduled include test wafers and wafers to be processed; the scheduling method may specifically include the following steps:

Step 201, recording the operating status of a preset semiconductor process equipment.

In the embodiment of the present invention, due to the differences in the operation of different semiconductor process equipment, the semiconductor process equipment that needs to schedule the use of test pieces during the processing process can be used as the semiconductor process equipment for action simulation, that is, the preset semiconductor process equipment. The operation status of the semiconductor process equipment can be recorded. That is, all process actions and states of the semiconductor process equipment without considering the potential test piece requirements are recorded.

Step 202: Generate a simulation scheduling sequence based on the operating status of the preset semiconductor process equipment.

The recorded operating status of the preset semiconductor process equipment is used as configuration data to generate a simulation scheduling sequence, and the simulation scheduling sequence is started to simulate the actions of the preset semiconductor process equipment. Based on the time sequence, the actions of the simulation scheduling sequence are executed to take out the wafers to be processed from the specified wafer box for scheduling.

Step 203, when running the simulation scheduling sequence, obtain the test piece usage rules, the test piece usage rules including the test piece scheduling time point and the test piece process path.

In actual applications, the simulation scheduling sequence is run, and the corresponding actions are executed to schedule the wafers to be processed, and the actions of the semiconductor assembly equipment are simulated. The test piece usage rules can be obtained at the same time as the simulation scheduling sequence starts. The test piece usage rules are used to determine the time when the test piece needs to be scheduled, and the path for scheduling the test piece. Therefore, the test piece usage rules include the test piece scheduling time point and the test piece process path. Among them, the test piece process path is the path that the test piece passes through when scheduling the test piece.

The test piece usage rule is information determined jointly according to the process requirements of the wafer to be processed and the setting of the processing chamber of the preset semiconductor process equipment. There is no specific limitation on the determination of the test piece scheduling time point of the test piece usage rule. For example, the process requirements of the wafer to be processed are that the test piece is required before the job (process) starts, the number of wafers to be processed is processed at intervals, and the job is completed; the setting requirements of the processing chamber of the preset semiconductor process equipment are that the test piece is required after the processing chamber is idle for a period of time and the fixed number of wafers to be processed are continuously executed. Therefore, based on this condition, there is a unique test piece scheduling time point and test piece process path. Among them, the test piece scheduling time point and the time when the simulation scheduling sequence runs are on the same time axis. The time point can be expressed in a relative time manner. For example, the time when the simulation scheduling sequence starts running is "0", and the subsequent test piece scheduling time point can be expressed as 10 seconds; that is, the test piece scheduling time point is the 10th second after the simulation scheduling sequence runs. The accuracy of the corresponding time point can be determined according to production requirements, and the accuracy of the time is not limited here.

The usage rules for the test piece can be obtained from the specified storage space address. It can be a local storage space address or a third-party storage space address, which is not specifically limited in the embodiment of the present invention.

Step 204 : When the simulation scheduling sequence runs to the test wafer scheduling time point, the target wafer to be processed is determined.

The simulation scheduling sequence runs in chronological order to perform the corresponding actions. When the time point of the simulation scheduling sequence runs matches the test piece scheduling time point, it is determined that the simulation scheduling sequence runs to the test piece scheduling time point. Continuing with the above example, when the simulation scheduling sequence runs to the 10th second, it is determined that the simulation scheduling sequence runs to the test piece scheduling time point.

In the simulation scheduling sequence, the wafers to be processed that are in the process path but have not been processed at the test piece scheduling time point are determined. From the wafers to be processed that are in the process path but have not been processed, the wafer to be processed closest to the end of the process path is determined as the target wafer to be processed. If there is no wafer to be processed that is in the process path but has not been processed at the test piece scheduling time point, it can be determined that the target wafer to be processed is empty.

Optionally, the simulation scheduling sequence includes a transmission path corresponding to the wafer to be processed, and the transmission path sequentially passes through the wafer loading and unloading module, the first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator;

Referring to FIG3 , the process path corresponding to processing a wafer to be processed into a semiconductor chip is a wafer loading and unloading module (LoadPort), a first manipulator (ATM), an alignment module (Aligner), an atmospheric vacuum lock chamber (one of the slots of LoadLock), a vacuum vacuum lock chamber (another slot of LoadLock), a second manipulator (VTM), a processing chamber (PM1, PM2, PM3, PM4), a second manipulator, a vacuum vacuum lock chamber, an atmospheric vacuum lock chamber, a first manipulator, and a wafer loading and unloading module. Among them, the transmission path is the path that the wafer to be processed passes through when it is in the process path but not processed, that is, it passes through the wafer loading and unloading module, the first manipulator, the alignment module, the atmospheric vacuum lock chamber, the vacuum vacuum lock chamber, and the second manipulator in sequence. Among them, the first manipulator can be a single-arm manipulator, and the second manipulator can be a double-arm manipulator.

When the simulation scheduling sequence runs to the test wafer scheduling time point, the target wafer to be processed is determined, including:

Sub-step S2041, when the simulation scheduling sequence runs to the test wafer scheduling time point, determining whether there is a wafer to be processed in the transmission path;

Determine whether there is a wafer to be processed on the transmission path when the simulation scheduling sequence runs to the test piece scheduling time point. Specifically, it can be determined one by one whether there is a wafer to be processed at the wafer loading and unloading module, the first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator position. If there is a wafer to be processed at one of the path points, it can be determined that there is a wafer to be processed on the transmission path. If there is no wafer to be processed at the wafer loading and unloading module, the first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator position, it is determined that there is no wafer to be processed on the transmission path.

Sub-step S2042, when there is no wafer to be processed in the transmission path, determining that the target wafer to be processed is empty;

When there is no wafer to be processed on the transmission path, that is, there is no wafer to be processed on the current transmission path, it can be determined that the target wafer to be processed is empty.

Sub-step S2043, when there are wafers to be processed in the transmission path, sorting the wafers to be processed in the transmission path according to the transmission order of the transmission path to generate a sequence of wafers to be processed;

When there are wafers to be processed in the transmission path, it is necessary to further sort the wafers to be processed in the transmission path according to the transmission order of the transmission path. The wafers to be processed currently in the transmission path are sorted in the order of the wafer loading and unloading module, the first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator, and the obtained sequence is the sequence of wafers to be processed.

Sub-step S2044, determining the last wafer to be processed in the sequence of wafers to be processed as the target wafer to be processed.

In the sequence of wafers to be processed, the closer to the end, the closer to the processing chamber, the faster it can enter. Therefore, the wafer to be processed at the end of the wafer sequence to be processed can be determined as the target wafer to be processed, so that when the test wafer is replaced with the test wafer later, the test wafer can enter the processing chamber more quickly.

Step 205 , rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed.

According to the position point of the target wafer to be processed on the transmission path, the corresponding time of all actions performed by the target wafer to be processed from the wafer to the position point is calculated, and based on the time, the scheduling time point of the target wafer to be processed is determined in the simulation scheduling sequence. The determination of the scheduling time point of the target wafer to be processed can be determined according to the type of the target wafer to be processed.

Then the simulation scheduling sequence is rolled back to the target wafer to be processed scheduling time point, so that the next action of the simulation scheduling sequence can be adjusted at the target wafer to be processed scheduling time point.

Specifically, when the target wafer to be processed is empty, rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed includes:

Sub-step S2051, determining the test wafer scheduling time point as the target wafer to be processed scheduling time point corresponding to the target wafer to be processed.

In actual applications, when the target wafer to be processed is empty, that is, when the simulation scheduling sequence is at the test piece scheduling time point, there is no wafer to be processed that has left the wafer loading and unloading module but has not entered the processing chamber. The test piece can be called directly at this time, and the scheduling time corresponding to the target wafer to be processed is zero. The test piece scheduling time point is determined to be the target wafer to be processed scheduling time point.

Sub-step S2052, deleting the data from the target wafer to be processed scheduling time point to the test wafer scheduling time point corresponding to the target wafer to be processed in the simulation scheduling sequence.

For the simulation scheduling sequence rollback method, the data from the scheduling time point of the target wafer to be processed to the scheduling time point of the test wafer in the simulation scheduling sequence is deleted.

In practical applications, all actions and parameters executed in the simulation scheduling sequence during the period from the target wafer to be processed scheduling time point to the test wafer scheduling time point can be deleted, and the current time point can be rolled back to the target wafer to be processed scheduling time point.

When the target wafer to be processed is the last wafer to be processed in the sequence of wafers to be processed, rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed includes:

Sub-step S2053, determining a current path point corresponding to the target wafer to be processed, where the current path point is one of the first manipulator, the calibration module, the second manipulator, the atmospheric environment vacuum lock chamber, and the vacuum environment vacuum lock chamber;

When there is a target wafer to be processed, a current path point of the target wafer to be processed on the transmission path at the current moment is determined, wherein the current path point is one of the first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator.

Sub-step S2054, calculating the running time from the wafer loading and unloading module to the current path point;

The first manipulator, the calibration module, the atmospheric environment vacuum lock chamber, the vacuum environment vacuum lock chamber, and the second manipulator have corresponding action durations. The action duration corresponding to each current path point is determined according to the duration of the semiconductor process equipment in the action during actual processing. According to the action duration corresponding to the current path point of the target wafer to be processed, the running time of the target wafer to be processed from the wafer loading and unloading module to the current path point is calculated.

For example, the action time of the first manipulator is 1 second, the action time of the calibration module is 2 seconds, the action time of the atmospheric vacuum lock chamber is 1 second, the action time of the vacuum vacuum lock chamber is 1 second, and the action time of the second manipulator is 1 second. The current path point of the target wafer to be processed is the atmospheric vacuum lock chamber, that is, the running time of the target wafer to be processed from the wafer loading and unloading module to the atmospheric vacuum lock chamber is 4 seconds (the sum of the action time of the first manipulator, the action time of the calibration module and the action time of the atmospheric vacuum lock chamber).

Sub-step S2055, subtracting the running time from the test wafer scheduling time point to obtain the target wafer to be processed scheduling time point corresponding to the target wafer to be processed.

The time point obtained by subtracting the running time from the test chip scheduling time point is the target wafer to be processed corresponding to the target wafer to be processed scheduling time point. The simulation scheduling sequence starts scheduling the target wafer to be processed at the target wafer to be processed scheduling time point.

Sub-step S2056, deleting the data from the target wafer to be processed scheduling time point to the test wafer scheduling time point corresponding to the target wafer to be processed in the simulation scheduling sequence.

For the simulation scheduling sequence rollback method, the data from the target wafer to be processed scheduling time point to the test wafer scheduling time point in the simulation scheduling sequence is deleted. All the actions and parameters executed in the simulation scheduling sequence during the period from the target wafer to be processed scheduling time point to the test wafer scheduling time point can be deleted, and the data can be rolled back to the target wafer to be processed scheduling time point at the current time.

Step 206 , setting a test wafer process path at the target wafer to be processed scheduling time point, and generating an executable scheduling sequence.

The process path of the test piece is set at the scheduling time point of the target wafer to be processed, and the priority of scheduling the test piece is raised to the highest level, so that when the simulation scheduling sequence runs to the scheduling time point of the target wafer to be processed, the test piece is scheduled first. After the scheduling requirements of all test pieces are met, the updated simulation scheduling sequence is determined as the executable scheduling sequence. Among them, the process path of the test piece can be determined according to the actual path of the test piece from its loading and unloading position to the target processing chamber and then back to its loading and unloading position.

Specifically, the test wafer process path corresponds to the test wafer priority, the test wafer process path is set at the target wafer to be processed scheduling time point, and an executable scheduling sequence is generated, including:

Sub-step S2061, determining a target test piece process path based on the test piece priority;

In actual applications, there are multiple test piece process paths in the test piece usage rules, but at a certain point in time, the priorities corresponding to the test piece process paths are not the same, and the test piece process path with the highest priority is the test piece process path currently required. Therefore, based on the test piece priority, the test piece process path with the highest priority can be determined from the test piece process paths as the target test piece process path.

Sub-step S2062, adding the target test wafer process path to the target wafer to be processed scheduling time point;

Add the target test piece process path to the target wafer to be processed scheduling time point, that is, the next step after the target wafer to be processed scheduling time point is to execute the target test piece process path scheduling test piece.

Sub-step S2063, calculating the process duration of the process path of the target test piece;

And according to each path point passed in the process path of the target test piece and the corresponding action duration, the process duration required to complete the entire process path of the target test piece is calculated.

For example, as shown in Figure 3, the target test piece process path is a test piece loading and unloading module (DummyPort), a first manipulator (ATM), a calibration module (Aligner), an atmospheric environment vacuum lock chamber (one of the slots of LoadLock), a vacuum environment vacuum lock chamber (another slot of LoadLock), a second manipulator (VTM), (, a processing chamber (PM1, PM2, PM3, PM4), a second manipulator, a vacuum environment vacuum lock chamber, an atmospheric environment vacuum lock chamber, a first manipulator, and a test piece loading and unloading module. The corresponding action durations are 1 second, 1 second, 2 seconds, 1 second, 1 second, 2 seconds, 3 seconds, 2 seconds, 1 second, 1 second, 1 second, and 1 second. The process duration is 17 seconds (the sum of the action durations corresponding to all path points of the target test piece process path).

Sub-step S2064, adding the process duration to the target wafer to be processed scheduling time point to obtain the target test wafer process completion time point;

Based on the target wafer to be processed scheduling time point, the process duration is added on this basis, and the obtained time point is determined as the target test piece process completion time point. The target test piece process completion time point is used to represent the time point when the current test piece is completed.

Sub-step S2065, at the target test piece process completion time point, clear the test piece priority and generate an executable scheduling sequence.

At the time point when the target test piece process is completed, the test piece priority is cleared so that the simulation scheduling sequence does not continue to schedule the test piece at the time point when the target test piece process is completed, and waits for the next test piece process with a higher priority to be scheduled again; thereby updating the simulation scheduling sequence to generate an executable scheduling sequence.

In addition, there may be a situation where multiple different processing chambers need to schedule the use of test wafers, that is, there may be a situation where there are multiple test wafer scheduling time points. In this case, at the target wafer to be processed scheduling time point After the step of setting the process path of the test piece, determine whether there is a next test piece scheduling time point in the simulation scheduling sequence according to the time sequence;

Specifically, it is possible to cyclically determine whether there is a need to schedule the use of test pieces in different processing chambers. When there is a scheduling need, there is a next test piece scheduling time point; otherwise, there is no next test piece scheduling time point. The current next test piece scheduling time point is the last time point at which the semiconductor process equipment needs to schedule a test piece.

When there is a next test piece scheduling time point, determine the next test piece scheduling time point as the test piece scheduling time point, and perform the step of determining the target wafer to be processed when the simulation scheduling sequence runs to the test piece scheduling time point until there is no next test piece scheduling time point;

Specifically, when there is a next test piece scheduling time point, the currently updated simulation scheduling sequence cannot be used as an executable scheduling sequence for controlling the processing of the preset semiconductor process equipment. It is necessary to continue to update the action of scheduling the test piece in the simulation scheduling sequence. To this end, the next test piece scheduling time point can be determined as the test piece scheduling time point, and the simulation scheduling sequence is continued to be executed at the test piece scheduling time point to run to the test piece scheduling time point, and the steps of determining the target wafer to be processed are determined, and the new target wafer to be processed and the corresponding target wafer to be processed scheduling time point are determined, so as to insert the action of scheduling the test piece at the new target wafer to be processed scheduling time point, and further update the simulation scheduling sequence; until there is no next test piece scheduling time point.

When there is no next test piece scheduling time point, the step of generating an executable scheduling sequence is performed.

When there is no next test piece scheduling time point, it means that the demand for scheduling test pieces in each processing chamber is met, and the updated simulation scheduling sequence can accurately control the preset semiconductor process equipment to produce semiconductor chips. The step of generating an executable scheduling sequence is executed, and the simulation scheduling sequence updated at this time is determined as the executable scheduling sequence.

Step 207 , sending the executable scheduling sequence to a preset semiconductor process equipment, where the preset semiconductor process equipment is used to schedule the test piece for production based on the executable scheduling sequence.

After the executable scheduling sequence is generated, the executable scheduling sequence can be sent to a preset semiconductor process equipment. The preset semiconductor process equipment receives the executable scheduling sequence, controls the corresponding modules to run based on the actions in the executable scheduling sequence, and produces semiconductor chips.

In the embodiment of the present invention, by adjusting the test piece call when running the simulation scheduling sequence, since there is no essential difference in the simulation scheduling sequences of various types of wafers, the test piece scheduling method of the embodiment of the present invention has good versatility and can support various types of wafers. And when the simulation scheduling sequence is run to schedule the wafer to be processed, the test piece scheduling is adjusted in parallel, so that the logic of scheduling the wafer to be processed and scheduling the test piece are decoupled, and the two are independent of each other, which can adapt to the changes of different process requirements more quickly. When the processing chamber needs a test piece, by finding the nearest wafer to be processed in the transmission process path and determining its call time, and then rolling back to the target wafer to be processed call time, the priority of the test piece is adjusted to achieve the earliest test piece output, and re-scheduling, so that when the processing chamber needs a test piece, the test piece in the process path is closest to the processing chamber, saving the idle waiting time of the processing chamber, thereby improving the production capacity of semiconductor chips.

In order to enable those skilled in the art to better understand the steps of the embodiments of the present invention, an example is given below to illustrate:

4, a schematic diagram of a wafer scheduling method application system according to an embodiment of the present invention is shown. The application system may specifically include the following five modules:

Optimization scheduling module: It adopts optimization scheduling algorithms such as finite state machine and extended finite state machine. According to the real-time status of the simulated system, it can optimize and calculate the optimal scheduling strategy (simulation scheduling sequence) without considering the potential test piece requirements.

Simulation module: The simulation of each equipment unit of the semiconductor combination equipment can be used to simulate the process control execution process of actual semiconductor process equipment.

Dummy demand logic judgment module: According to the system status of the simulation and the logic of the test piece usage rules, it is judged whether each processing chamber needs the test piece usage rules in this simulation state, and the required test piece usage rule information is output;

State rollback module: determines the rollback time point, triggers the simulation module to perform state rollback, and modifies the process path and priority of the corresponding test piece in the simulation module;

Scheduling sequence output module: According to the scheduling action sequence recorded by the simulation system, organize and output the scheduling sequence list (executable sequence).

Specifically, the wafer scheduling method flow may refer to FIG. 5 .

Step 1: Use a computer program to simulate the machine, record all process actions and states of the machine, and initialize or update the simulation program according to the actual state of the semiconductor assembly equipment;

Step 2: Remove the wafers to be processed in LoadPort (wafer loading and unloading position) and DummyPort (test wafer loading and unloading position) in order of priority;

Step 3: Using the optimization scheduling algorithm, the scheduling sequence (simulation scheduling sequence) is solved without considering the potential dummy demand (i.e., the test wafer is scheduled as the wafer to be processed);

Step 4: Run the simulation program and execute the next action in the simulation program in chronological order; if the next action is that the Dummy piece (test piece) that has completed the process returns to the DummyPort (test piece loading and unloading position), clear the process path and priority of the Dummy piece.

Step 5: Determine whether all (test slice) scheduling tasks are completed. If yes, execute step 6; otherwise, execute step 7.

Step 6: Arrange and output all process actions recorded by the simulation program as the machine executable scheduling sequence, and the program ends and the executable scheduling sequence is output;

Step 7: According to the usage logic rules of the Dummy sheet (test sheet usage rules), loop to determine whether each PM (processing chamber) currently needs a Dummy sheet. If all PMs do not need it, execute step 4, otherwise execute step 8.

Step 8: Record the PM that needs the dummy piece as PM_dummy (target processing chamber). If there are multiple PMs that need the dummy piece, select a PM record according to the priority.

Step 9: Determine whether there are wafers that have left the LoadPort (wafer loading and unloading position to be processed) and have not been processed (i.e., wafers to be processed on the transport path). If so, execute step 10; otherwise, execute step eleven;

Step 10: Find the last wafer to be processed in the steps of LoadPort (wafer loading and unloading position to be processed) -> ATM (first manipulator) -> Aligner (calibration module) -> ATM (second manipulator) -> LoadLock atmospheric environment (atmospheric environment vacuum lock chamber) -> LoadLock vacuum environment (vacuum environment vacuum lock chamber);

The time point when this chip leaves LoadPort is obtained as T2 (the scheduling time point of the target chip to be processed); roll back the status of all devices, chips and Dummy chips in the simulation system to the T2 time point, and delete all action and status records from T2 to the current time in the simulation program.

Step 11: Find the first Dummy slice according to the priority of the Dummy slice; initialize the process path of this Dummy slice, and set the target pm to PM_dummy; regard this Dummy slice as a wafer to be processed, and set the priority to the highest; go to step 2.

It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

6, a block diagram of an electronic device according to an embodiment of the present invention is shown; an electronic device 601 is connected to a semiconductor process device,

The electronic device 601 is used to execute the above wafer scheduling method.

As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned test piece scheduling method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on The differences between the embodiments are all from other embodiments, and the same or similar parts between the embodiments can be referenced to each other.

Those skilled in the art will appreciate that the embodiments of the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

The embodiments of the present invention are described with reference to the flowcharts and/or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and/or box in the flowchart and/or block diagram, as well as the combination of the processes and/or boxes in the flowchart and/or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate a device for implementing the functions specified in one process or multiple processes in the flowchart and/or one box or multiple boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

The above is a detailed introduction to a chip scheduling method and an electronic device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for general technicians in this field, according to the idea of the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

A wafer scheduling method, characterized in that the wafers include test wafers and wafers to be processed, and the method comprises:

When the simulation scheduling sequence runs to the test wafer scheduling time point, a target wafer to be processed is determined, and the simulation scheduling sequence is used to schedule the wafer to be processed;

Rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed;

A test wafer process path is set at the target wafer to be processed scheduling time point to generate an executable scheduling sequence.
The method according to claim 1, characterized in that the method further comprises:

When the simulation scheduling sequence is run, a test piece usage rule is obtained, wherein the test piece usage rule includes the test piece scheduling time point and the test piece process path.
The method according to claim 1 is characterized in that the simulation scheduling sequence includes a transmission path corresponding to the wafer to be processed, and the transmission path sequentially passes through a wafer loading and unloading module, a first manipulator, a calibration module, an atmospheric environment vacuum lock chamber, a vacuum environment vacuum lock chamber, and a second manipulator; when the simulation scheduling sequence runs to the test piece scheduling time point, determining the target wafer to be processed comprises:

When the simulation scheduling sequence runs to the test piece scheduling time point, determining whether there is a wafer to be processed in the transmission path;

When there is no wafer to be processed in the transmission path, determining that the target wafer to be processed is empty;

When there are wafers to be processed on the transmission path, the wafers to be processed on the transmission path are sorted according to the transmission order of the transmission path to generate a sequence of wafers to be processed;

The wafer to be processed at the end of the sequence of wafers to be processed is determined as the target wafer to be processed.
The method according to claim 3, characterized in that when the target wafer to be processed is empty, rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed comprises:

Determine the test wafer scheduling time point as the target wafer to be processed scheduling time point corresponding to the target wafer to be processed;

The data from the target wafer to be processed scheduling time point to the test wafer scheduling time point corresponding to the target wafer to be processed in the simulation scheduling sequence is deleted.
The method according to claim 3 is characterized in that, when the target wafer to be processed is the last wafer to be processed in the sequence of wafers to be processed, rolling back the simulation scheduling sequence to the target wafer to be processed scheduling time point corresponding to the target wafer to be processed comprises:

Determine a current path point corresponding to the target wafer to be processed, wherein the current path point is one of the first manipulator, the calibration module, the second manipulator, the atmospheric environment vacuum lock chamber, and the vacuum environment vacuum lock chamber;

Calculating the running time from the wafer handling module to the current path point;

Subtract the running time from the test wafer scheduling time point to obtain a target wafer to be processed scheduling time point corresponding to the target wafer to be processed;

The data from the target wafer to be processed scheduling time point to the test wafer scheduling time point corresponding to the target wafer to be processed in the simulation scheduling sequence is deleted.
The method according to claim 1, characterized in that the test wafer process path corresponds to a test wafer priority, and the test wafer process path is set at the scheduling time point of the target wafer to be processed to generate an executable scheduling sequence, comprising:

Based on the test piece priority, determining a target test piece process path;

Adding the target test wafer process path to the target wafer to be processed scheduling time point;

Calculating the process duration of the process path of the target test piece;

At the target wafer to be processed scheduling time point, the process duration is added to obtain the target test wafer process completion time point;

At the time point when the process of the target test piece is completed, the priority of the test piece is cleared to generate an executable scheduling sequence.
The method according to claim 6 is characterized in that the test piece scheduling time points are multiple, and after the step of setting the test piece process path at the target wafer to be processed scheduling time point, the method further comprises:

According to the time sequence, determine whether there is a next test piece scheduling time point in the simulation scheduling sequence;

When the next test piece scheduling time point exists, determining the next test piece scheduling time point as the test piece scheduling time point, and executing the step of determining the target wafer to be processed when the simulation scheduling sequence runs to the test piece scheduling time point until the next test piece scheduling time point does not exist;

When the next test piece scheduling time point does not exist, the step of generating an executable scheduling sequence is performed.
The method according to claim 1, characterized in that the method further comprises:

The executable scheduling sequence is sent to a preset semiconductor process equipment, and the preset semiconductor process equipment is used to schedule the test piece for production based on the executable scheduling sequence.
The method according to claim 1, characterized in that the method further comprises:

Record the operating status of preset semiconductor process equipment;

The simulation scheduling sequence is generated based on the operating status of the preset semiconductor process equipment.
An electronic device, characterized in that the electronic device is connected to a semiconductor process device,

The electronic device is used to execute the wafer scheduling method described in any one of claims 1-9.