WO2024087092A1 - 移位寄存器单元、栅极驱动电路和显示基板 - Google Patents

移位寄存器单元、栅极驱动电路和显示基板 Download PDF

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Publication number
WO2024087092A1
WO2024087092A1 PCT/CN2022/127926 CN2022127926W WO2024087092A1 WO 2024087092 A1 WO2024087092 A1 WO 2024087092A1 CN 2022127926 W CN2022127926 W CN 2022127926W WO 2024087092 A1 WO2024087092 A1 WO 2024087092A1
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Prior art keywords
node
circuit
control
pull
leakage
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PCT/CN2022/127926
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to PCT/CN2022/127926 priority Critical patent/WO2024087092A1/zh
Publication of WO2024087092A1 publication Critical patent/WO2024087092A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present invention relates to the field of display, and in particular to a shift register unit, a gate driving circuit and a display substrate.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • OLED organic light-emitting diode
  • AMOLED can emit light by driving the thin film transistor to generate a driving current in a saturated state, and the driving current drives the light-emitting device to emit light.
  • an embodiment of the present disclosure provides a shift register unit, comprising:
  • a first sensing control input circuit connected to a sensing control node, a sensing signal input terminal, a random signal input terminal, a clock control signal input terminal and a first pull-up node, and configured to write a signal provided by the sensing signal input terminal to the sensing control node in response to a control of a valid level signal provided by the random signal input terminal, and to write a valid level signal to the first pull-up node in response to a control of a valid level signal at the sensing control node and a valid level signal provided by the clock control signal;
  • the first output circuit being connected to the first pull-up node, the corresponding first clock signal input terminal and the corresponding first signal output terminal, and being configured to write the signal provided by the corresponding first clock signal input terminal to the corresponding first signal output terminal in response to control of the effective level signal at the first pull-up node;
  • the shift register unit further includes: a first voltage control circuit, a first sensing input leakage prevention circuit and a first current limiting circuit;
  • the first voltage control circuit is connected to the first power supply terminal, the first pull-up node and the first voltage control node, and the first voltage control circuit is configured to write the effective level signal provided by the first power supply terminal to the first voltage control node in response to the control of the effective level signal at the first pull-up node;
  • the first sensing control input circuit is connected to the first pull-up node through the first sensing input leakage prevention circuit, the first sensing control input circuit and the first sensing input leakage prevention circuit are connected to the first sensing input leakage prevention node, the first sensing input leakage prevention node is connected to the first voltage control node, the first sensing input leakage prevention circuit is connected to the clock control signal input terminal, and the first sensing input leakage prevention circuit is configured to form a path between the first sensing input leakage prevention node and the first pull-up node in response to the control of the effective level signal at the clock control signal input terminal, and to form a disconnection between the first sensing input leakage prevention node and the first pull-up node in response to the control of the ineffective level signal at the clock control signal input terminal;
  • the first current limiting circuit is connected to the first voltage control node.
  • the first current limiting circuit comprises:
  • the first load circuit is located between the first sensing input anti-leakage node and the first voltage control node, and is configured to increase the load resistance between the first sensing input anti-leakage node and the first voltage control node.
  • the first load circuit includes: an eighty-first transistor
  • the control electrode of the eighty-first transistor is connected to the first voltage control node, the first electrode of the eighty-first transistor is connected to the first sensing input anti-leakage node, and the second electrode of the eighty-first transistor is connected to the first voltage control node.
  • the first current limiting circuit comprises:
  • the second load circuit is connected to the first voltage control node and the second power supply terminal, and is configured to increase the load capacitance at the first voltage control node.
  • the second load circuit includes: an eleventh capacitor
  • the first end of the eleventh capacitor is connected to the first voltage control node, and the second end of the eleventh capacitor is connected to the second power supply end.
  • it also includes:
  • a first global reset circuit is connected to a global reset signal input terminal, a second power supply terminal, and the first pull-up node, wherein the first global reset circuit is configured to write a non-valid level signal provided by the second power supply terminal to the first pull-up node in response to control of a valid level signal provided by the global reset signal input terminal;
  • the first anti-leakage circuit, the first global reset circuit is connected to the second power supply terminal through the first anti-leakage circuit, the first global reset circuit and the first anti-leakage circuit are connected to a first anti-leakage node, the first anti-leakage node is connected to the first voltage control node, the first anti-leakage circuit is connected to the global reset signal input terminal, and the first anti-leakage circuit is configured to form a path between the first anti-leakage node and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal, and to form a disconnection between the first anti-leakage node and the second power supply terminal in response to the control of the non-valid level signal provided by the global reset signal input terminal.
  • the first current limiting circuit comprises:
  • the third load circuit is located between the first anti-leakage node and the first voltage control node, and is configured to increase the load resistance between the first anti-leakage node and the first voltage control node.
  • the third load circuit includes: an eighty-second transistor
  • the control electrode of the eighty-second transistor is connected to the first voltage control node, the first electrode of the eighty-second transistor is connected to the first anti-leakage node, and the second electrode of the eighty-second transistor is connected to the first voltage control node.
  • it also includes:
  • a fifth load circuit wherein at least one of the first global reset circuit and the first leakage protection circuit is connected to the global reset signal input terminal through the fifth load circuit, and the fifth load circuit is configured to increase the load resistance between at least one of the first global reset circuit and the first leakage protection circuit and the global reset signal input terminal.
  • the fifth load circuit includes: an eighty-fourth transistor
  • the control electrode of the eighty-fourth transistor is connected to the global reset signal input terminal, the first electrode of the eighty-fourth transistor is connected to the global reset signal input terminal, and the second electrode of the eighty-fourth transistor is connected to at least one of the first global reset circuit and the first anti-leakage circuit.
  • it also includes:
  • a first pull-down control circuit is connected to the second power supply terminal, the fifth power supply terminal, the first pull-up node and the first pull-down node, and is configured to write a voltage that is inversely proportional to the voltage at the first pull-up node to the first pull-down node;
  • a first pull-up noise reduction circuit is connected to the second power supply terminal, the first pull-up node and the first pull-down node, and is configured to write a non-valid level signal provided by the second power supply terminal to the first pull-up node in response to control of a valid level signal at the first pull-down node;
  • the first output circuit is also connected to the first pull-down node and the second power supply terminal, and the first output circuit is further configured to write the non-valid level signal provided by the second power supply terminal to the corresponding first signal output terminal in response to the control of the valid level signal at the first pull-down node;
  • it also includes:
  • a third leakage protection circuit wherein the first pull-up noise reduction circuit is connected to the second power supply terminal through the third leakage protection circuit, the first pull-up noise reduction circuit and the third leakage protection circuit are connected to a third leakage protection node, the third leakage protection node is connected to the first voltage control node, the third leakage protection circuit is connected to the first pull-down node, and the third leakage protection circuit is configured to form a path between the third leakage protection node and the second power supply terminal in response to the control of a valid level signal at the first pull-down node, and to form a disconnection between the third leakage protection node and the second power supply terminal in response to the control of a non-valid level signal at the first pull-down node.
  • the first voltage control node is located between the first sensing input anti-leakage node and the third anti-leakage node;
  • the first current limiting circuit comprises:
  • the fourth load circuit is located between the first voltage control node and the third leakage protection node, and is configured to increase the load resistance between the first voltage control node and the third leakage protection node.
  • the fourth load circuit comprises:
  • the control electrode of the eighty-third transistor is connected to the first voltage control node, the first electrode of the eighty-third transistor is connected to the first voltage control node, and the second electrode of the eighty-third transistor is connected to the third anti-leakage node.
  • it also includes:
  • the first pull-down noise reduction circuit is connected to the first pull-down node, the second power supply terminal, the sensing control node and the clock control signal input terminal, and is configured to write the non-valid level signal provided by the second power supply terminal to the first pull-down node in response to the control of the valid level signal at the sensing control node and the valid level signal provided by the clock control signal input terminal.
  • the first pull-down noise reduction circuit includes: a twenty-ninth transistor and a thirtieth transistor;
  • a control electrode of the twenty-ninth transistor is connected to the clock control signal input terminal, a first electrode of the twenty-ninth transistor is connected to the first pull-down node, and a second electrode of the twenty-ninth transistor is connected to the first electrode of the thirtieth transistor;
  • the control electrode of the 30th transistor is connected to the sensing control node, and the second electrode of the 30th transistor is connected to the second power supply terminal.
  • the first pull-down noise reduction circuit further includes: an eighty-fifth transistor, a first electrode of the twenty-ninth transistor being connected to the first pull-down node through the eighty-fifth transistor;
  • the control electrode of the eighty-fifth transistor is connected to the sensing control node, the first electrode of the eighty-fifth transistor is connected to the first pull-down node, and the second electrode of the eighty-fifth transistor is connected to the first electrode of the twenty-ninth transistor.
  • it also includes:
  • a first display input circuit is connected to a display signal input terminal, a first power supply terminal and a first pull-up node, and is configured to write a valid level signal provided by the first power supply terminal to the first pull-up node in response to control of a valid level signal provided by the display signal input terminal;
  • the first display reset circuit is connected to the display reset signal input terminal, the second power supply terminal, and the first pull-up node, and is configured to write the non-valid level signal provided by the second power supply terminal to the first pull-up node in response to the control of the valid level signal provided by the display reset signal input terminal.
  • the invention further includes: at least one of a first display input leakage prevention circuit and a second leakage prevention circuit;
  • the first display input circuit is connected to the first pull-up node through the first display input leakage prevention circuit, the first display input circuit and the first display input leakage prevention circuit are connected to the first display input leakage prevention node, the first display input leakage prevention node is connected to the first voltage control node, the first display input leakage prevention circuit is connected to the display signal input terminal, the first display input leakage prevention circuit is configured to form a path between the first display input leakage prevention node and the first pull-up node in response to the control of the effective level signal provided by the display signal input terminal, and to form a disconnection between the first display input leakage prevention node and the first pull-up node in response to the control of the ineffective level signal provided by the display signal input terminal;
  • the first display reset circuit is connected to the second power supply terminal through the second anti-leakage circuit
  • the first display reset circuit and the second anti-leakage circuit are connected to a second anti-leakage node
  • the second anti-leakage node is connected to the first voltage control node
  • the second anti-leakage circuit is connected to the display reset signal input terminal
  • the second anti-leakage circuit is configured to form a path between the second anti-leakage node and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal, and to form a break between the second anti-leakage node and the second power supply terminal in response to the control of the non-valid level signal provided by the display reset signal input terminal.
  • the first sensing control input circuit includes: a sensing control circuit and a first sensing input circuit
  • the sensing control circuit is connected to the sensing control node, the sensing signal input terminal and the random signal input terminal, and the sensing control circuit is configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to the control of the effective level signal provided by the random signal input terminal;
  • the first sensing input circuit is connected to the sensing control node, the clock control signal input terminal, the sensing intermediate node and the first pull-up node, and is configured to write the valid level signal to the sensing intermediate node in response to the control of the valid level signal at the sensing control node, and to form a path between the sensing intermediate node and the first pull-up node in response to the control of the valid level signal provided by the clock control signal input terminal.
  • the invention further includes: a sensing and controlling anti-leakage circuit
  • the sensing control circuit is connected to the sensing control node through the sensing control anti-leakage circuit, the sensing control anti-leakage circuit and the sensing control circuit are connected to the sensing control anti-leakage node, the sensing control anti-leakage circuit is also connected to the first power supply terminal, the sensing control node and the random signal input terminal, the sensing control anti-leakage circuit is configured to respond to the control of the valid level signal at the sensing control node, write the valid level signal provided by the first power supply terminal to the sensing control anti-leakage node, and is configured to respond to the control of the valid level signal provided by the random signal input terminal so that a path is formed between the sensing control anti-leakage node and the sensing control node, and respond to the control of the non-valid level signal provided by the random signal input terminal so that a break is formed between the sensing control anti-leakage node and the sensing control node.
  • it also includes:
  • a second sensing input circuit is connected to the clock control signal input terminal, the second pull-up node and the preset power supply node, and is configured to form a path between the preset power supply node and the second pull-up node in response to the control of the effective level signal provided by the clock control signal input terminal;
  • the second output circuit being connected to the second pull-up node, the corresponding second clock signal input terminal and the corresponding second signal output terminal, and being configured to write the signal provided by the corresponding second clock signal input terminal to the corresponding second signal output terminal in response to control of the effective level signal at the second pull-up node;
  • the preset power supply node is the sensing intermediate node or the first sensing input leakage prevention node
  • the preset power supply node is the first sensing input leakage prevention node
  • the shift register unit further includes: a second voltage control circuit and a second current limiting circuit;
  • the second voltage control circuit is connected to the first power supply terminal, the second pull-up node and the second voltage control node, and the second voltage control circuit is configured to write the effective level signal provided by the first power supply terminal to the second voltage control node in response to the control of the effective level signal at the second pull-up node;
  • the second current limiting circuit is connected to the second voltage control node, and the second current limiting circuit is configured to reduce the charge and discharge current at the second voltage control node.
  • the second current limiting circuit comprises:
  • An eleventh load circuit is located between the first sensing input anti-leakage node and the second voltage control node, and is configured to increase a load resistance between the first sensing input anti-leakage node and the second voltage control node.
  • the eleventh load circuit comprises: a ninety-first transistor
  • the control electrode of the ninety-first transistor is connected to the second voltage control node, the first electrode of the ninety-first transistor is connected to the second voltage control node, and the second electrode of the ninety-first transistor is connected to the first sensing input anti-leakage node.
  • the preset power supply node is the sensing intermediate node
  • the shift register unit further includes: a second voltage control circuit, a second sensing input leakage prevention circuit and a second current limiting circuit;
  • the second voltage control circuit is connected to the first power supply terminal, the second pull-up node and the second voltage control node, and the second voltage control circuit is configured to write the effective level signal provided by the first power supply terminal to the second voltage control node in response to the control of the effective level signal at the second pull-up node;
  • the second sensing input circuit is connected to the second pull-up node through the second sensing input leakage prevention circuit, the second sensing input circuit and the second sensing input leakage prevention circuit are connected to the second sensing input leakage prevention node, the second sensing input leakage prevention node is connected to the second voltage control node, the second sensing input leakage prevention circuit is connected to the clock control signal input terminal, and the second sensing input leakage prevention circuit is configured to form a path between the second sensing input leakage prevention node and the second pull-up node in response to the control of the effective level signal at the clock control signal input terminal, and to form an open circuit between the second sensing input leakage prevention node and the second pull-up node in response to the control of the ineffective level signal at the clock control signal input terminal;
  • the second current limiting circuit is connected to the second voltage control node, and the second current limiting circuit is configured to reduce the charge and discharge current at the second voltage control node.
  • the second current limiting circuit comprises:
  • An eleventh load circuit is located between the second sensing input anti-leakage node and the second voltage control node, and is configured to increase a load resistance between the second sensing input anti-leakage node and the second voltage control node.
  • the eleventh load circuit comprises: a ninety-first transistor
  • the control electrode of the ninety-first transistor is connected to the second voltage control node, the first electrode of the ninety-first transistor is connected to the second sensing input anti-leakage node, and the second electrode of the ninety-first transistor is connected to the second voltage control node.
  • the second current limiting circuit comprises:
  • a twelfth load circuit is connected to the second voltage control node and the second power supply terminal, and is configured to increase the load capacitance at the second voltage control node.
  • the twelfth load circuit includes: a twelfth capacitor
  • the first end of the twelfth capacitor is connected to the second voltage control node, and the second end of the twelfth capacitor is connected to the second power supply end.
  • it also includes:
  • a second global reset circuit is connected to a global reset signal input terminal, a second power supply terminal, and the second pull-up node, wherein the second global reset circuit is configured to write a non-valid level signal provided by the second power supply terminal to the second pull-up node in response to control of a valid level signal provided by the global reset signal input terminal;
  • the fourth anti-leakage circuit, the second global reset circuit is connected to the second power supply terminal through the fourth anti-leakage circuit, the second global reset circuit and the fourth anti-leakage circuit are connected to a fourth anti-leakage node, the fourth anti-leakage node is connected to the second voltage control node, the fourth anti-leakage circuit is connected to the global reset signal input terminal, and the fourth anti-leakage circuit is configured to form a path between the second anti-leakage node and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal, and to form a disconnection between the fourth anti-leakage node and the second power supply terminal in response to the control of the non-valid level signal provided by the global reset signal input terminal.
  • the second current limiting circuit comprises:
  • a thirteenth load circuit is located between the fourth anti-leakage node and the second voltage control node, and is configured to increase a load resistance between the fourth anti-leakage node and the second voltage control node.
  • the thirteenth load circuit includes: a ninety-second transistor
  • the control electrode of the ninety-second transistor is connected to the second voltage control node, the first electrode of the ninety-second transistor is connected to the fourth anti-leakage node, and the second electrode of the ninety-second transistor is connected to the second voltage control node.
  • it also includes:
  • a fifteenth load circuit at least one of the second global reset circuit and the fourth anti-leakage circuit is connected to the global reset signal input terminal through the fifteenth load circuit, and the fifteenth load circuit is configured to increase the load resistance between at least one of the first global reset circuit and the first anti-leakage circuit and the global reset signal input terminal.
  • the fifteenth load circuit comprises: a ninety-fourth transistor
  • the control electrode of the ninety-fourth transistor is connected to the global reset signal input terminal, the first electrode of the ninety-fourth transistor is connected to the global reset signal input terminal, and the second electrode of the ninety-fourth transistor is connected to at least one of the second global reset circuit and the fourth anti-leakage circuit.
  • it also includes:
  • a second pull-down control circuit is connected to the second power supply terminal, the fifth power supply terminal, the second pull-up node and the second pull-down node, and is configured to write a voltage that is inversely proportional to the voltage at the second pull-up node to the second pull-down node;
  • a second pull-up noise reduction circuit connected to the second power supply terminal, the second pull-up node and the second pull-down node, and configured to write the non-valid level signal provided by the second power supply terminal to the second pull-up node in response to the control of the valid level signal at the second pull-down node;
  • the second output circuit is also connected to the second pull-down node and the second power supply terminal, and the second output circuit is further configured to write the non-valid level signal provided by the second power supply terminal to the corresponding second signal output terminal in response to the control of the valid level signal at the second pull-down node;
  • it also includes:
  • a sixth leakage protection circuit the second pull-up noise reduction circuit is connected to the second power supply terminal through the sixth leakage protection circuit, the second pull-up noise reduction circuit and the sixth leakage protection circuit are connected to a sixth leakage protection node, the sixth leakage protection node is connected to the second voltage control node, the sixth leakage protection circuit is connected to the second pull-down node, and the sixth leakage protection circuit is configured to form a path between the sixth leakage protection node and the second power supply terminal in response to the control of the effective level signal at the second pull-down node, and to form a break between the sixth leakage protection node and the second power supply terminal in response to the control of the ineffective level signal at the second pull-down node.
  • the second voltage control node is located between the second sensing input anti-leakage node and the sixth anti-leakage node;
  • the second current limiting circuit comprises:
  • a fourteenth load circuit is located between the second voltage control node and the sixth leakage protection node, and is configured to increase a load resistance between the second voltage control node and the sixth leakage protection node.
  • the fourteenth load circuit comprises:
  • the control electrode of the ninety-third transistor is connected to the second voltage control node, the first electrode of the ninety-third transistor is connected to the second voltage control node, and the second electrode of the ninety-third transistor is connected to the sixth leakage protection node.
  • it also includes:
  • the third pull-down noise reduction circuit is connected to the second pull-down node, the second power supply terminal, the sensing control node and the clock control signal input terminal, and is configured to write the non-valid level signal provided by the second power supply terminal to the second pull-down node in response to the control of the valid level signal at the sensing control node and the valid level signal provided by the clock control signal input terminal.
  • the third pull-down noise reduction circuit includes: a fifty-ninth transistor and a sixtieth transistor;
  • the control electrode of the fifty-ninth transistor is connected to the clock control signal input terminal, the first electrode of the fifty-ninth transistor is connected to the second pull-down node, and the second electrode of the fifty-ninth transistor is connected to the first electrode of the sixtieth transistor.
  • the control electrode of the 60th transistor is connected to the sensing control node, and the second electrode of the 60th transistor is connected to the second power supply terminal.
  • the third pull-down noise reduction circuit further includes: a ninety-fifth transistor, the first electrode of the fifty-ninth transistor being connected to the second pull-down node through the ninety-fifth transistor;
  • the control electrode of the ninety-fifth transistor is connected to the sensing control node, the first electrode of the ninety-fifth transistor is connected to the second pull-down node, and the second electrode of the ninety-fifth transistor is connected to the first electrode of the fifty-ninth transistor.
  • it also includes:
  • a second display input circuit is connected to the display signal input terminal, the first power supply terminal and the second pull-up node, and is configured to write the effective level signal provided by the first power supply terminal to the second pull-up node in response to the control of the effective level signal provided by the display signal input terminal;
  • the second display reset circuit is connected to the display reset signal input terminal, the second power supply terminal, and the second pull-up node, and is configured to write the non-valid level signal provided by the second power supply terminal to the second pull-up node in response to the control of the valid level signal provided by the display reset signal input terminal.
  • the invention further includes: at least one of a second display input leakage prevention circuit and a fifth leakage prevention circuit;
  • the second display input circuit is connected to the second pull-up node through the second display input leakage prevention circuit, the second display input circuit and the second display input leakage prevention circuit are connected to the second display input leakage prevention node, the second display input leakage prevention node is connected to the second control voltage node, the second display input leakage prevention circuit is connected to the display signal input terminal, and the second display input leakage prevention circuit is configured to form a path between the second display input leakage prevention node and the second pull-up node in response to the control of the effective level signal provided by the display signal input terminal, and to form a disconnection between the second display input leakage prevention node and the second pull-up node in response to the control of the ineffective level signal provided by the display signal input terminal;
  • the second display reset circuit is connected to the second power supply terminal through the fifth anti-leakage circuit, the second display reset circuit and the fifth anti-leakage circuit are connected to the fifth anti-leakage node, the fifth anti-leakage node is connected to the second voltage control node, the fifth anti-leakage circuit is connected to the display reset signal input terminal, and the fifth anti-leakage circuit is configured to form a path between the fifth anti-leakage node and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal, and to form a break between the fifth anti-leakage node and the second power supply terminal in response to the control of the non-valid level signal provided by the display reset signal input terminal.
  • an embodiment of the present disclosure further provides a gate driving circuit, which includes: a plurality of cascaded shift register units, wherein the shift register units adopt the shift register units provided in the above-mentioned first aspect.
  • an embodiment of the present disclosure further provides a display substrate, which includes: a base substrate and a gate driving circuit located on the base substrate, wherein the gate driving circuit adopts the gate driving circuit provided in the second aspect.
  • FIG1 is a schematic diagram of a circuit structure of a pixel circuit in an organic light emitting diode display panel
  • FIG2 is a working timing diagram of the pixel circuit shown in FIG1 ;
  • FIG3 is a schematic diagram of a circuit structure of a shift register unit involved in the related art
  • FIG4 is a schematic diagram of another circuit structure of a shift register unit involved in the related art.
  • 5A and 5B are schematic diagrams of two circuit structures of a shift register unit provided in an embodiment of the present disclosure
  • 6A and 6B are schematic diagrams of two other circuit structures of the shift register unit provided in the embodiments of the present disclosure.
  • FIGS. 7A and 7B are schematic diagrams of two further circuit structures of the shift register unit provided in the embodiments of the present disclosure.
  • FIG8 is a working timing diagram of the shift register unit shown in FIG7A and FIG7B ;
  • 9A and 9B are schematic diagrams of two further circuit structures of the shift register unit provided in the embodiments of the present disclosure.
  • FIGS. 10A and 10B are schematic diagrams of two further circuit structures of the shift register unit provided in the embodiment of the present disclosure.
  • FIG11 is a working timing diagram of the shift register unit shown in FIG10A and FIG10B ;
  • 12A to 12D are schematic diagrams of four further circuit structures of the shift register unit provided in the embodiments of the present disclosure.
  • 12E is a simulation diagram of current changes at the first voltage control node and the second power supply terminal when the eighty-first transistor is not provided in the shift register unit shown in FIG. 12A ;
  • 12F is a simulation diagram of current changes at the first voltage control node and the second power supply terminal when the eighty-first transistor is provided in the shift register unit shown in FIG. 12A ;
  • FIG12G is a schematic diagram of another circuit structure of the shift register unit provided in an embodiment of the present disclosure.
  • FIGS. 13A and 13B are schematic diagrams of two further circuit structures of the shift register unit provided in the embodiments of the present disclosure.
  • FIGS. 14A and 14B are schematic diagrams of two further circuit structures of the shift register unit provided in the embodiments of the present disclosure.
  • 15A and 15B are schematic diagrams of two further circuit structures of the shift register unit provided in the embodiments of the present disclosure.
  • 16A to 16D are schematic diagrams of four further circuit structures of the shift register unit provided in the embodiments of the present disclosure.
  • FIG16E is a schematic diagram of another circuit structure of the shift register unit provided in the embodiment of the present disclosure.
  • FIG17 is a schematic diagram of another circuit structure of a shift register unit provided in an embodiment of the present disclosure.
  • FIG18 is a simulation diagram of current changes at the second power supply terminal after an inductor is provided between an output terminal used as the second power supply terminal on the power management chip and a gate driving circuit in an embodiment of the present disclosure
  • FIG19 is a schematic diagram of a circuit structure of a gate driving circuit provided in an embodiment of the present disclosure.
  • FIG. 20 is a working timing diagram of the gate driving circuit shown in FIG. 19 .
  • words “first”, “second” and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.
  • words such as “include” or “comprise” mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.
  • Words such as “connect”, “couple” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
  • the transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the coupling mode of the drain and source of each transistor can be interchangeable. Therefore, there is actually no difference between the drain and source of each transistor in the embodiments of the present disclosure.
  • the control electrode i.e., the gate
  • one of the poles is called the drain and the other pole is called the source.
  • the thin film transistor used in the embodiments of the present disclosure can be an N-type transistor or a P-type transistor. In the embodiments of the present disclosure, when an N-type thin film transistor is used, its first pole can be a source and the second pole can be a drain.
  • effective level signal refers to a signal that can control the transistor to turn on after being input to the control electrode of the transistor
  • ineffective level signal refers to a signal that can control the transistor to turn off after being input to the control electrode of the transistor.
  • a high-level signal is an effective level signal
  • a low-level signal is an ineffective level signal
  • a high-level signal is an ineffective level signal.
  • the transistor is an N-type transistor as an example.
  • the effective level signal refers to a high level signal
  • the ineffective level signal refers to a low level signal. It can be imagined that when a P-type transistor is used, the timing change of the control signal needs to be adjusted accordingly. The specific details are not repeated here, but should also be within the scope of protection of the present disclosure.
  • FIG1 is a schematic diagram of the circuit structure of a pixel circuit in an organic light emitting diode display panel.
  • FIG2 is a working timing diagram of the pixel circuit shown in FIG1.
  • a frame of an image can be divided into two stages: a display driving stage and a sensing stage; in the display driving stage, each row of pixel units in the display panel completes display driving; in the sensing stage, a row of pixel units in the display panel completes current extraction (i.e., sensing).
  • the pixel circuit includes a display switch transistor QTFT (the control electrode is connected to the first gate line G1), a driving transistor DTFT, a sensing switch transistor STFT (the control electrode is connected to the second gate line G2) and a Cst.
  • the pixel circuit includes at least the following two stages during operation: a pixel driving stage (including a data voltage writing process) and a pixel sensing stage (including a current reading process).
  • the data voltage Vdata in the data line Data needs to be written into the pixel unit; in the pixel sensing stage, a test voltage Vsence needs to be written into the pixel unit through the data line Data, and the electrical signal at the drain of the driving transistor needs to be read to the signal reading line Sence through the sensing switch transistor STFT.
  • the current reading process it is necessary to write an effective level voltage to the gate of the sensing switch transistor STFT through the corresponding second gate line G2. It should be noted that the pixel unit in the OLED display panel is externally compensated, and the specific compensation process and principle are not repeated here.
  • a corresponding gate driving circuit is configured in the peripheral area of the display panel.
  • the gate driving circuit includes a plurality of cascaded shift register units, which can provide a driving signal to the corresponding second gate line G2.
  • Fig. 3 is a schematic diagram of a circuit structure of a shift register unit involved in the related art.
  • the shift register unit includes: a first sensing control input circuit 100 and at least one first output circuit 200; wherein the first sensing control input circuit 100 is connected to the sensing signal input terminal INPUT2, the random signal input terminal OE, the clock control signal input terminal CLKA and the first pull-up node PU1, and the first sensing control input circuit 100 can write an effective level signal to the first pull-up node PU1; the first output circuit 200 is connected to the first pull-up node PU1, the corresponding first clock signal input terminal CLK and the corresponding first signal output terminal OUT, and the first output circuit 200 is configured to write the signal provided by the first clock signal input terminal CLK to the corresponding first signal output terminal OUT in response to the control of the effective level signal at the first pull-up node PU1.
  • the first sensing control input circuit 100 completes writing a valid level signal to the first pull-up node PU1
  • the first pull-up node PU1 will be in a floating state for a long period of time.
  • the first pull-up node PU1 is prone to leakage through the first sensing control input circuit 100, causing the voltage at the first pull-up node PU1 to drift; when the voltage drift at the first pull-up node PU1 is large (for example, drifting to a low level state), the first output circuit 200 will be unable to perform effective output; that is, the shift register unit operates abnormally.
  • Fig. 4 is another schematic diagram of the circuit structure of the shift register unit involved in the related art. As shown in Fig. 4, in order to effectively improve the problem of leakage of the first pull-up node PU1 through the first sensing control input circuit 100, the first voltage control circuit 14 and the first sensing input anti-leakage circuit 2' are added in the shift register unit in the related art.
  • the first voltage control circuit 14 is connected to the first power supply terminal, the first pull-up node PU1 and the first voltage control node OFF1, and the first voltage control circuit 14 is configured to write the effective level signal provided by the first power supply terminal to the first voltage control node OFF1 in response to the control of the effective level signal at the first pull-up node PU1.
  • the first sensing control input circuit 100 is connected to the first pull-up node PU1 through the first sensing input leakage protection circuit 2’, the first sensing control input circuit 100 and the first sensing input leakage protection circuit 2’ are connected to the first sensing input leakage protection node SQ1, the first sensing input leakage protection node SQ1 is connected to the first control voltage node OFF1, the first sensing input leakage protection circuit 2’ is connected to the clock control signal input terminal CLKA, and the first sensing input leakage protection circuit 2’ is configured to control the on and off between the first sensing input leakage protection node SQ1 and the first pull-up node PU1 in response to the control of the signal provided by the clock control signal input terminal CLKA.
  • the first voltage control circuit 14 responds to the control of the effective level signal at the first pull-up node PU1 to write the effective level signal provided by the first power supply terminal into the first voltage control node OFF1 and the first sensing input anti-leakage node SQ1. Since the first sensing input anti-leakage node SQ1 and the first pull-up node PU1 are both in an effective level state, the first pull-up node PU1 cannot leak through the first sensing control input circuit 100, thereby solving the problem of the first pull-up node PU1 leaking through the first sensing control input circuit 100.
  • the first sensing input leakage protection circuit 2' is controlled by the clock control signal input terminal CLKA, and there is a parasitic capacitance between the gate and the source and drain of the transistor in the first sensing input leakage protection circuit 2', when the level of the signal provided by the clock control signal input terminal CLKA switches, for example, from a high level to a low level or from a low level to a high level, a transient large current (the current peak value will exceed 75uA) will exist at the first sensing input leakage protection node SQ1 and the first voltage control node OFF1, and the voltage at the first voltage control node OFF1 will also drift.
  • the transient large current at the first voltage control node OFF1 will have an adverse effect on the electrical device connected to the first voltage control node OFF1 (for example, the transistor in the first voltage control circuit 14 or the transistor added later in the shift register unit and connected to the first voltage control node OFF1), thereby affecting the working yield of the shift register.
  • the embodiment of the present disclosure provides a corresponding solution.
  • the shift register unit includes: a first sensing control input circuit 100, at least one first output circuit, a first voltage control circuit 14, a first sensing input anti-leakage circuit 2' and a first current limiting circuit 300.
  • the first sensing control input circuit 100 is connected to the sensing control node, the sensing signal input terminal INPUT2, the random signal input terminal OE, the clock control signal input terminal and the first pull-up node PU1.
  • the first sensing control input circuit 100 is configured to write the signal provided by the sensing signal input terminal INPUT2 to the sensing control node in response to the control of the valid level signal provided by the random signal input terminal OE, and to write the valid level signal to the first pull-up node PU1 in response to the control of the valid level signal at the sensing control node and the valid level signal provided by the clock control signal.
  • the first output circuit is connected to the first pull-up node PU1, the corresponding first clock signal input terminal and the corresponding first signal output terminal.
  • the first output circuit is configured to write the signal provided by the corresponding first clock signal input terminal to the corresponding first signal output terminal in response to the control of the effective level signal at the first pull-up node PU1.
  • the above-mentioned at least one first output circuit at least includes a first drive output circuit 5; the first drive output circuit 5 is connected to the first pull-up node PU1, the first drive clock signal input terminal CLKE (the first clock signal input terminal corresponding to the first drive output circuit) and the first drive signal output terminal OUT2 (the first signal output terminal corresponding to the first drive output circuit), and the first drive output circuit 5 is configured to write the signal provided by the first drive clock signal input terminal CLKE to the first drive signal output terminal OUT2 in response to the control of the effective level signal at the first pull-up node PU1.
  • the first voltage control circuit 14 is connected to the first power supply terminal, the first pull-up node PU1 and the first voltage control node OFF1.
  • the first voltage control circuit 14 is configured to write the valid level signal provided by the first power supply terminal to the first voltage control node OFF1 in response to the control of the valid level signal at the first pull-up node PU1.
  • the first sensing control input circuit 100 is connected to the first pull-up node PU1 through the first sensing input leakage protection circuit 2’, the first sensing control input circuit 100 and the first sensing input leakage protection circuit 2’ are connected to the first sensing input leakage protection node SQ1, the first sensing input leakage protection node SQ1 is connected to the first control voltage node OFF1, the first sensing input leakage protection circuit 2’ is connected to the clock control signal input terminal CLKA, and the first sensing input leakage protection circuit 2’ is configured to form a path between the first sensing input leakage protection node SQ1 and the first pull-up node PU1 in response to the control of the valid level signal at the clock control signal input terminal CLKA, and to form a break between the first sensing input leakage protection node SQ1 and the first pull-up node PU1 in response to the control of the ineffective level signal at the clock control signal input terminal CLKA.
  • the first current limiting circuit 300 is connected to the first voltage control node OFF1 , and the first current limiting circuit 300 is configured to reduce the charge and discharge current at the first voltage control node OFF1 .
  • a first current limiting circuit 300 is provided at the first voltage control node OFF1.
  • the first current limiting circuit 300 can effectively reduce the charge and discharge current at the first voltage control node OFF1, so that the current peak value of the instantaneous current generated at the first voltage control node OFF1 is reduced, which can effectively solve various problems caused by excessive instantaneous current.
  • the first current limiting circuit 300 in the embodiment of the present disclosure can be arranged between the first sensing input anti-leakage node SQ1 and the first voltage control node OFF1 in the case shown in FIG5A , or can be not arranged between the first sensing input anti-leakage node SQ1 and the first voltage control node OFF1 in the case shown in FIG5B .
  • the first current limiting circuit 300 in the embodiment of the present disclosure can also be partially arranged between the first sensing input anti-leakage node SQ1 and the first voltage control node OFF1, and the other part is not arranged between the first sensing input anti-leakage node SQ1 and the first voltage control node OFF1, that is, it includes the cases shown in both FIG5A and FIG5B (the corresponding drawings are not shown).
  • the first current limiting circuit 300 includes: a first load circuit 301; the first load circuit 301 is located between the first sensing input anti-leakage node SQ1 and the first control voltage node OFF1, and the first load circuit 301 is configured to increase the load resistance between the first sensing input anti-leakage node SQ1 and the first control voltage node OFF1.
  • a first load circuit 301 is provided between the first sensing input anti-leakage node SQ1 and the first voltage control node OFF1, so that the load resistance between the first sensing input anti-leakage node SQ1 and the first voltage control node OFF1 is increased.
  • the instantaneous current generated at the first voltage control node OFF1 can be reduced when the level of the signal provided by the clock control signal input terminal CLKA is switched.
  • the first load circuit 301 includes: an eighty-first transistor M81; the control electrode of the eighty-first transistor M81 is connected to the first control voltage node OFF1, the first electrode of the eighty-first transistor M81 is connected to the first sensing input anti-leakage node SQ1, and the second electrode of the eighty-first transistor M81 is connected to the first control voltage node OFF1.
  • the eighty-first transistor M81 can be equivalent to a diode, which does not affect the first control voltage circuit 14 to write the effective level signal to the first sensing input anti-leakage node SQ1, and can also serve as a load resistor to limit the current.
  • the first current limiting circuit 300 includes: a second load circuit 302 , the second load circuit 302 is connected to the first voltage control node OFF1 and the second power supply terminal, and the second load circuit 302 is configured to increase the load capacitance at the first voltage control node OFF1 .
  • the second load circuit 302 is provided at the first voltage control node OFF1 so that the load capacitance at the first voltage control node OFF1 is increased.
  • the instantaneous current generated at the first voltage control node OFF1 can be reduced when the level of the signal provided by the clock control signal input terminal CLKA is switched; at the same time, since the load capacitance has a certain voltage stabilizing effect, the voltage offset at the first voltage control node OFF1 can be effectively reduced.
  • the second load circuit 302 includes: an eleventh capacitor C11; a first end of the eleventh capacitor C11 is connected to the first voltage control node OFF1, and a second end of the eleventh capacitor C11 is connected to the second power supply terminal.
  • FIG. 7A and 7B are schematic diagrams of two more circuit structures of the shift register unit provided in the embodiments of the present disclosure. As shown in FIG. 7A and FIG. 7B, FIG. 7A and FIG. 7B are a specific optional implementation scheme based on the shift register shown in FIG. 6A and FIG. 6B. In some embodiments, the shift register further includes: a first global reset circuit 6.
  • the first global reset circuit 6 is connected to the global reset signal input terminal T-RST, the second power supply terminal (the second power supply terminal provides a low level voltage VGL1), and the first pull-up node PU1.
  • the first global reset circuit 6 is configured to write the non-valid level signal provided by the second power supply terminal to the first pull-up node PU1 in response to the control of the valid level signal provided by the global reset signal input terminal T-RST.
  • the first sensing control input circuit 100 includes: a sensing control circuit 1 and a first sensing input circuit 2; the sensing control circuit 1 is connected to the sensing control node H, the sensing signal input terminal INPUT2 and the random signal input terminal OE, and the sensing control circuit 1 is configured to respond to the control of the valid level signal provided by the random signal input terminal OE, and write the signal provided by the sensing signal input terminal INPUT2 to the sensing control node H; the first sensing input circuit 2 is connected to the sensing control node H, the clock control signal input terminal CLKA, the sensing intermediate node Z and the first pull-up node PU1, and the first sensing input circuit 2 is configured to respond to the control of the valid level signal at the sensing control node H, write the valid level signal to the sensing intermediate node Z, and respond to the control of the valid level signal provided by the clock control signal input terminal CLKA, so that a path is formed between the sensing intermediate node Z and the first pull-up node
  • the sensing control circuit 1 includes a first transistor M1; a control electrode of the first transistor M1 is connected to the random signal input terminal, a first electrode of the first transistor M1 is connected to the sensing signal input terminal INPUT2, and a second electrode of the first transistor M1 is connected to the sensing control node H.
  • the sensing control circuit 1 is configured with a first capacitor C1 , a first end of the first capacitor C1 is connected to the sensing control node H, and a second end of the first capacitor C1 is connected to the second power supply end.
  • the first sensing input circuit 2 includes a second transistor M2 and a third transistor M3; the control electrode of the second transistor M2 is connected to the sensing control node H, the first electrode of the second transistor M2 is connected to the clock control signal input terminal CLKA, and the second electrode of the second transistor M2 is connected to the sensing intermediate node Z.
  • the control electrode of the third transistor M3 is connected to the clock control signal input terminal CLKA, the first electrode of the third transistor M3 is connected to the sensing intermediate node Z, and the second electrode of the third transistor M3 is connected to the first sensing input leakage protection circuit.
  • the first global reset circuit 6 includes a seventh transistor M7; the control electrode of the seventh transistor M7 is connected to the global reset signal input terminal T-RST, the first electrode of the seventh transistor M7 is connected to the first pull-up node PU1, and the second electrode of the seventh transistor M7 is connected to the second power supply terminal.
  • the first drive output circuit 5 includes a fifth transistor M5; the control electrode of the fifth transistor M5 is connected to the first pull-up post node PUB1, the first electrode of the fifth transistor M5 is connected to the first drive clock signal input terminal CLKE, and the second electrode of the fifth transistor M5 is connected to the first drive signal output terminal OUT2.
  • the first driving output circuit 5 is configured with a second capacitor C2, a first end of the second capacitor C2 is connected to the first pull-up node, and a second end of the second capacitor C2 is connected to the first driving signal output terminal OUT2.
  • the first voltage control circuit 14 includes a twentieth transistor M20; the control electrode of the twentieth transistor M20 is connected to the first pull-up node PU1, the first electrode of the twentieth transistor M20 is connected to the first power supply terminal (the first power supply terminal provides a high level voltage VDD1), and the second electrode of the twentieth transistor M20 is connected to the first voltage control node OFF1.
  • the first sensing input leakage protection circuit 2' includes: an eighth transistor M8; a control electrode of the eighth transistor M8 is connected to the clock control signal input terminal CLKA, a first electrode of the eighth transistor M8 is connected to the first sensing input leakage protection node SQ1, and a second electrode of the eighth transistor M8 is connected to the first pull-up node PU1.
  • FIG7A illustrates a case where the first current limiting circuit 300 includes a first load circuit 301, and the first load circuit 301 includes an eighty-first transistor M81;
  • FIG7B illustrates a case where the first current limiting circuit 300 includes a second load circuit 302, and the second load circuit 302 includes an eleventh capacitor C11.
  • FIG8 is a working timing diagram of the shift register unit shown in FIG7A and FIG7B. As shown in FIG8, the working process of the shift register unit includes the following stages:
  • the sensing signal input terminal INPUT2 provides a high level signal
  • the random signal input terminal OE provides a high level signal
  • the clock control signal input terminal CLKA provides a low level signal
  • the global reset signal input terminal T-RST provides a low level signal.
  • the first transistor M1 is turned on, and the high-level signal provided by the sensing signal input terminal INPUT2 is written to the sensing control node H, and the voltage at the sensing control node H is in a high-level state.
  • the second transistor M2 is turned on, and the low-level signal provided by the clock control signal input terminal CLKA is written to the sensing intermediate node Z through the second transistor M2, and the voltage at the sensing intermediate node Z is in a low-level state.
  • the third transistor M3 and the eighth transistor M8 are both turned off; the global reset signal input terminal T-RST provides a low level signal, so the seventh transistor M7 is turned off.
  • the p1 stage is located in the display driving stage in a frame.
  • the voltage loaded on the first pull-up node PU1 and the first drive signal output terminal OUT2 in the display driving stage can be referred to the description in the following embodiments. This implementation only describes in detail the specific working conditions of the shift register unit in the sensing stage.
  • the sensing signal input terminal INPUT2 provides a low level signal
  • the random signal input terminal OE provides a low level signal
  • the clock control signal input terminal CLKA provides a high level signal
  • the global reset signal input terminal T-RST provides a low level signal.
  • the second transistor M2 Since the voltage at the sensing control node H maintains the high level state of the previous stage, the second transistor M2 remains turned on, and the clock control signal input terminal CLKA provides a high level signal which is written to the sensing middle node Z through the second transistor M2; at the same time, since the high level signal provided by the clock control signal input terminal CLKA makes the third transistor M3 and the eighth transistor M8 turned on, the high level signal at the sensing middle node Z can be written to the first pull-up node PU1.
  • the fifth transistor M5 and the twentieth transistor M20 are turned on. Since the fifth transistor M5 is turned on, the low level signal provided by the first drive clock signal input terminal CLKE is written to the first drive signal output terminal OUT2 through the fifth transistor M5, and the first drive signal output terminal OUT2 outputs a low level signal.
  • the first capacitor C1 may be added at the sensing control node H.
  • the first current limiting circuit can prevent the instantaneous current at the first voltage control node from being too large.
  • the sensing signal input terminal INPUT2 provides a low level signal
  • the random signal input terminal OE provides a low level signal
  • the clock control signal input terminal CLKA provides a low level signal
  • the global reset signal input terminal T-RST provides a low level signal.
  • the third transistor M3 and the eighth transistor M8 are turned off, and since the second transistor M2 remains turned on, the low level signal provided by the clock control signal input terminal CLKA is written to the sensing intermediate node Z through the second transistor M2, and the sensing intermediate node Z is in a low level state.
  • the first pull-up node PU1 maintains the high level state of the previous stage, and the fifth transistor M5 and the twentieth transistor M20 remain turned on.
  • the first drive clock signal input terminal CLKE first provides a high level signal and then provides a low level signal.
  • the signal provided by the first drive clock signal input terminal CLKE is written to the first drive signal output terminal OUT2 through the fifth transistor M5.
  • the first drive signal output terminal OUT2 first outputs a high level signal and then outputs a low level signal.
  • the sensing signal input terminal INPUT2 provides a low level signal
  • the random signal input terminal OE provides a high level signal
  • the clock control signal input terminal CLKA provides a low level signal
  • the global reset signal input terminal T-RST provides a high level signal.
  • the first transistor M1 Since the random signal input terminal OE provides a high level signal, the first transistor M1 is turned on, and the low level signal provided by the sensing signal input terminal INPUT2 is written to the sensing control node H through the first transistor M1, and the voltage at the sensing control node H is in a low level state, and the second transistor M2 is turned off. Since the clock control signal input terminal CLKA provides a low level signal, the third transistor M3 and the eighth transistor M8 are both turned off. At this time, the sensing intermediate node Z is in a floating state and maintains a low level.
  • the seventh transistor M7 is turned on, and the low-level voltage VGL1 provided by the second power supply terminal is written to the first pull-up node PU1 through the seventh transistor M7.
  • the first pull-up node PU1 is in a low-level state
  • the fifth transistor M5 and the twentieth transistor are both cut off, and the first drive signal output terminal OUT2 maintains the low-level state of the previous stage, that is, maintains the output low-level signal.
  • the shift register unit further includes: a first display input circuit 7 and a first display reset circuit 8 .
  • the first display input circuit 7 is connected to the display signal input terminal INPUT1 and the first pull-up node PU1, and the first display input circuit 7 is configured to write the valid level signal provided by the display signal input terminal INPUT1 to the first pull-up node PU1 in response to the control of the valid level signal provided by the display signal input terminal INPUT1.
  • the first display reset circuit 8 is connected to the display reset signal input terminal RST, the second power supply terminal, and the first pull-up node PU1, and is configured to write the non-valid level signal provided by the second power supply terminal to the first pull-up node PU1 in response to the control of the valid level signal provided by the display reset signal input terminal RST.
  • the shift register unit also includes: a first pull-down control circuit 11; wherein the first pull-down control circuit 11 is connected to the second power supply terminal, the fifth power supply terminal, the first pull-up node PU1 and the first pull-down node PD1, and is configured to write a voltage that is opposite to the voltage at the first pull-up node PU1 to the first pull-down node PD1.
  • the shift register unit also includes: a first pull-up noise reduction circuit 12; wherein the first pull-up noise reduction circuit 12 is connected to the second power supply terminal, the first pull-up node PU1 and the first pull-down node PD1, and is configured to write the non-valid level signal provided by the second power supply terminal to the first pull-up node PU1 in response to the control of the valid level signal at the first pull-down node PD1, so as to perform noise reduction on the first pull-up node PU1.
  • a first pull-up noise reduction circuit 12 is connected to the second power supply terminal, the first pull-up node PU1 and the first pull-down node PD1, and is configured to write the non-valid level signal provided by the second power supply terminal to the first pull-up node PU1 in response to the control of the valid level signal at the first pull-down node PD1, so as to perform noise reduction on the first pull-up node PU1.
  • the first drive output circuit 5 is also connected to the first pull-down node PD1 and the fourth power supply terminal, and the first drive output circuit 5 is also configured to write the non-valid level signal provided by the fourth power supply terminal to the first drive signal output terminal OUT2 in response to the control of the valid level signal at the first pull-down node PD1.
  • At least one first output circuit in the shift register unit includes not only the first drive output circuit 5 , but also the second drive output circuit 9 and the first cascade output circuit 13 .
  • the second drive output circuit 9 is connected to the first pull-up node PU1, the first pull-down node PD1, the second drive clock signal input terminal CLKD, the second drive signal output terminal OUT1 and the fourth power supply terminal.
  • the second drive output circuit 9 is configured to write the signal provided by the second drive clock signal input terminal CLKD to the second drive signal output terminal OUT1 in response to the control of the effective level signal at the first pull-up node PU1, and write the non-effective level signal provided by the fourth power supply terminal to the second drive signal output terminal OUT1 in response to the control of the effective level signal at the first pull-down node PD1;
  • the first cascade output circuit 13 is connected to the first pull-up node PU1, the first pull-down node PD1, the first cascade clock signal input terminal CLKC, the first cascade signal output terminal CR and the fourth power supply terminal.
  • the first cascade output circuit 13 is configured to write the signal provided by the first cascade clock signal input terminal CLKC to the first cascade signal output terminal CR in response to the control of the valid level signal at the first pull-up node PU1, and to write the non-valid level signal provided by the second power supply terminal to the first cascade signal output terminal CR in response to the control of the valid level signal at the first pull-down node PD1.
  • the shift register unit shown in FIG. 9A and FIG. 9B not only has a sensing driving function, i.e., providing a driving signal to the second gate line G2 in FIG. 1 , but also has a display driving function, i.e., providing a driving signal to the first gate line G1 in FIG. 1 ).
  • the first gate line G1 and the second gate line G2 in the display panel can be driven by the same gate driving circuit, which can effectively reduce the number of gate driving circuits configured for the display panel, and is conducive to the narrow frame design of the product.
  • FIGS. 10A and 10B are schematic diagrams of two more circuit structures of the shift register unit provided in the embodiments of the present disclosure.
  • the shift register unit shown in FIG10A and FIG10B is a specific optional implementation scheme of the shift register unit shown in FIG9A and FIG9B.
  • the sensing control circuit 1 the first sensing input circuit 2, the first global reset circuit 6, the first voltage control circuit 14, and the first sensing input anti-leakage circuit 2' in FIG10A and FIG10B as an example
  • the situation shown in FIG7A and FIG7B can be adopted.
  • the first display input circuit 7 includes a ninth transistor M9
  • the first display reset circuit 8 includes a tenth transistor M10
  • the first pull-down control circuit 11 includes a twelfth transistor M12 and a thirteenth transistor M13
  • the first pull-up noise reduction circuit 12 includes a fourteenth transistor M14
  • the first drive output circuit 5 includes a fifth transistor M5 and a seventeenth transistor M17
  • the second drive output circuit 9 includes a fifteenth transistor M15 and an eighteenth transistor M18
  • the first cascade output circuit 13 includes a sixteenth transistor M16 and a nineteenth transistor M19.
  • the control electrode of the ninth transistor M9 is connected to the display signal input terminal INPUT1, the first electrode of the ninth transistor M9 is connected to the display signal input terminal INPUT1, and the second electrode of the ninth transistor M9 is connected to the first pull-up node PU1.
  • a control electrode of the tenth transistor M10 is connected to the display reset signal input terminal RST, a first electrode of the tenth transistor M10 is connected to the first pull-up node PU1, and a second electrode of the tenth transistor M10 is connected to the second power supply terminal.
  • a control electrode of the twelfth transistor M12 is connected to the fifth power supply terminal, a first electrode of the twelfth transistor M12 is connected to the fifth power supply terminal, and a second electrode of the twelfth transistor M12 is connected to the first pull-down node PD1.
  • a control electrode of the thirteenth transistor M13 is connected to the first pull-up node PU1 , a first electrode of the thirteenth transistor M13 is connected to the first pull-down node PD1 , and a second electrode of the thirteenth transistor M13 is connected to the second power supply terminal.
  • a control electrode of the fourteenth transistor M14 is connected to the first pull-down node PD1 , a first electrode of the fourteenth transistor M14 is connected to the first pull-up node PU1 , and a second electrode of the fourteenth transistor M14 is connected to the second power supply terminal.
  • a control electrode of the fifth transistor M5 is connected to the first pull-up node PU1 , a first electrode of the fifth transistor M5 is connected to the first driving clock signal input terminal CLKE, and a second electrode of the fifth transistor M5 is connected to the first driving signal output terminal OUT2 .
  • a control electrode of the seventeenth transistor M17 is connected to the first pull-down node PD1 , a first electrode of the seventeenth transistor M17 is connected to the first driving signal output terminal OUT2 , and a second electrode of the seventeenth transistor M17 is connected to the fourth power supply terminal.
  • a control electrode of the fifteenth transistor M15 is connected to the first pull-up node PU1 , a first electrode of the fifteenth transistor M15 is connected to the second driving clock signal input terminal CLKD, and a second electrode of the fifteenth transistor M15 is connected to the second driving signal output terminal OUT1 .
  • a control electrode of the eighteenth transistor M18 is connected to the first pull-down node PD1 , a first electrode of the eighteenth transistor M18 is connected to the second driving signal output terminal OUT1 , and a second electrode of the eighteenth transistor M18 is connected to the fourth power supply terminal.
  • a control electrode of the sixteenth transistor M16 is connected to the first pull-up node PU1 , a first electrode of the sixteenth transistor M16 is connected to the cascade driving clock signal input terminal, and a second electrode of the sixteenth transistor M16 is connected to the first cascade signal output terminal CR.
  • a control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD1 , a first electrode of the nineteenth transistor M19 is connected to the first cascade signal output terminal CR, and a second electrode of the nineteenth transistor M19 is connected to the fourth power supply terminal.
  • the first drive output circuit 5 and the second drive output circuit 6 are respectively configured with a second capacitor C2 and a third capacitor C3.
  • the first power terminal provides a high level voltage VDD1
  • the second power terminal provides a low level voltage VGL1
  • the fourth power terminal provides a low level voltage VGL2
  • the fifth power terminal provides a high level voltage VDDA.
  • Fig. 11 is a working timing diagram of the shift register unit shown in Fig. 10A and Fig. 10B. As shown in Fig. 11, the working process of the shift register unit includes: a display driving process and a sensing driving process.
  • the display driving process includes: a display input stage t1, a display output stage t2 and a display reset stage t3; the sensing driving process includes: a sensing preparation stage p1, a sensing input stage p2, a sensing output stage p3 and a global reset stage p4.
  • the display signal input terminal INPUT1 provides a high-level signal
  • the ninth transistor M9 is turned on
  • the high-level voltage VDD1 provided by the first power supply terminal is written to the first pull-up node PU1 through the ninth transistor M9.
  • the first pull-up node PU1 is in a high-level state, and accordingly, the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 are all turned on.
  • the thirteenth transistor M13 When the first pull-up node PU1 is in a high level state, the thirteenth transistor M13 is turned on, and the low level voltage VGL1 passed through the second power supply terminal is written to the first pull-down node PD1 through the thirteenth transistor M13, the first pull-down node PD1 is in a low level state, and the seventeenth transistor M17, the eighteenth transistor M18 and the nineteenth transistor M19 are all in the cut-off state.
  • the first drive clock signal input terminal CLKE writes a low level signal to the first drive signal output terminal OUT2 through the fifth transistor M5;
  • the second drive clock signal input terminal CLKD writes a low level signal to the second drive signal output terminal OUT1 through the fifteenth transistor M15;
  • the first cascade clock signal input terminal CLKC writes a low level signal to the first cascade signal output terminal CR through the sixteenth transistor M16. That is, the first drive signal output terminal OUT2, the second drive signal output terminal OUT1 and the first cascade signal output terminal CR all output low level signals.
  • the display signal input terminal INPUT1 provides a low level signal
  • the ninth transistor M9 is turned off
  • the first pull-up node PU1 is in a floating state and maintains the high level of the previous stage
  • the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 are all turned on.
  • the signal provided by the first drive clock signal input terminal CLKE changes from a low level signal to a high level signal, and under the bootstrap effect of the second capacitor C2, the voltage at the first pull-up node PU1 is pulled up to a higher level, and the first drive signal output terminal OUT2 outputs a high level signal.
  • the signal provided by the first drive clock signal input terminal CLKE changes from a high level signal to a low level signal, and under the bootstrap effect of the second capacitor C2, the voltage at the first pull-up node PU1 is pulled down to the initial high level voltage, the fifth transistor M5 remains turned on, and the first drive signal output terminal OUT2 outputs a low level signal.
  • the second drive signal output terminal OUT1 and the first cascade signal output terminal CR also output a high level signal first and then a low level signal.
  • the display reset signal input terminal RST provides a high level signal
  • the tenth transistor M10 is turned on
  • the low level signal provided by the second power supply terminal is written to the first pull-up node PU1 through the tenth transistor M10.
  • the first pull-up node PU1 is in a low level state
  • the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 are all turned off.
  • the thirteenth transistor M13 is also turned off, and the high-level voltage VDDA passing through the fifth power supply terminal is written to the first pull-down node PD1 through the twelfth transistor M12.
  • the first pull-down node PD1 is in a high-level state, and the seventeenth transistor M17, the eighteenth transistor M18 and the nineteenth transistor M19 are all in the on state.
  • the fourth power supply terminal writes a low level signal to the first drive signal output terminal OUT2 through the seventeenth transistor M17; the fourth power supply terminal writes a low level signal to the second drive signal output terminal OUT1 through the eighteenth transistor M18; the second power supply terminal writes a low level signal to the first cascade signal output terminal CR through the nineteenth transistor M19. That is, the first drive signal output terminal OUT2, the second drive signal output terminal OUT1 and the first cascade signal output terminal CR all output low level signals.
  • the fourteenth transistor M14 is also turned on, and the low level voltage VGL1 provided by the second power terminal is written to the first pull-up node PU1 through the fourteenth transistor M14 to perform noise reduction processing on the first pull-up node PU1.
  • the sensing signal input terminal INPUT2 and the random signal input terminal OE both provide high-level signals, and the first transistor M1 is turned on at this time; the high-level signal provided by the sensing signal input terminal INPUT2 is written to the sensing control node H through the first transistor M1 to charge the sensing control node H, and the voltage at the sensing control node H is in a high-level state. Accordingly, the second transistor M2 is turned on; however, since the clock control signal input terminal CLKA provides a low-level signal, the third transistor M3 and the eighth transistor M8 are both turned off, so the circuit between the clock control signal input terminal CLKA and the first pull-up node PU1 is disconnected.
  • the clock control signal input terminal CLKA provides a high level signal, so the third transistor M3 and the eighth transistor M8 are both turned on.
  • the second transistor M2 is kept turned on, so the high level signal provided by the clock control signal input terminal CLKA can be written to the first pull-up node PU1 through the second transistor M2, the third transistor M3 and the eighth transistor M8, that is, the voltage at the first pull-up node PU1 is in a high level state.
  • the twentieth transistor M20, the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 are all turned on.
  • the thirteenth transistor M13 When the first pull-up node PU1 is in a high level state, the thirteenth transistor M13 is turned on, the low level voltage VGL1 passing through the second power supply terminal is written to the first pull-down node PD1 through the thirteenth transistor M13, the first pull-down node PD1 is in a low level state, and the seventeenth transistor M17, the eighteenth transistor M18 and the nineteenth transistor M19 are all in the off state.
  • the first drive clock signal input terminal CLKE writes a low level signal to the first drive signal output terminal OUT2 through the fifth transistor M5;
  • the second drive clock signal input terminal CLKD writes a low level signal to the second drive signal output terminal OUT1 through the fifteenth transistor M15;
  • the first cascade clock signal input terminal CLKC writes a low level signal to the first cascade signal output terminal CR through the sixteenth transistor M16. That is, the first drive signal output terminal OUT2, the second drive signal output terminal OUT1 and the first cascade signal output terminal CR all output low level signals.
  • the clock control signal input terminal CLKA provides a low level signal, so the third transistor M3 is turned off, and a circuit is formed again between the clock control signal input terminal CLKA and the first pull-up node PU1.
  • the first pull-up node PU1 is in a floating state and maintains a high level in the previous stage; the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 are all turned on.
  • the signal provided by the first drive clock signal input terminal CLKE changes from a low level signal to a high level signal, and under the bootstrap effect of the second capacitor C2, the voltage at the first pull-up node PU1 is pulled up to a higher level, and the first drive signal output terminal OUT2 outputs a high level signal.
  • the signal provided by the first drive clock signal input terminal CLKE changes from a high level signal to a low level signal, and under the bootstrap effect of the second capacitor, the voltage at the first pull-up node PU1 is pulled down to the initial high level voltage, the fifth transistor M5 remains turned on, and the first drive signal output terminal OUT2 outputs a low level signal.
  • the second drive signal output terminal OUT1 first outputs a high level signal and then a low level signal during the entire sensing output stage p3.
  • the first cascade signal output terminal CR provides a low level signal during the entire sensing output stage p3, so the first cascade signal output terminal CR always outputs a low level signal during the entire sensing output stage p3.
  • the global reset signal input terminal T-RST provides a high level signal
  • the seventh transistor M7 is turned on
  • the low level voltage VGL1 provided by the second power supply terminal is written to the first pull-up node PU1 through the seventh transistor M7 to reset the first pull-up node PU1.
  • the high level voltage VDDA provided by the fifth power supply terminal is written to the first pull-down node PD1 through the twelfth transistor M12, the first pull-down node PD1 is in a high level state, and the seventeenth transistor M17, the eighteenth transistor M18 and the nineteenth transistor M19 are all in the on state.
  • the period during which the sensing signal input terminal INPUT2 and the random signal input terminal OE simultaneously provide valid level signals is the sensing preparation stage p1; the situation in which the sensing preparation stage p1 and the display input stage t1 overlap as shown in FIG. 11 is only an optional implementation scheme in the present disclosure, and at this time, the sensing signal input terminal INPUT2 and the display signal input terminal INPUT1 can be the same signal input terminal, which is only an optional implementation scheme in the present disclosure and does not limit the technical solution of the present disclosure.
  • the sensing preparation stage p1 can also be located before the display input stage t1, or after the display input stage t2, and it is only necessary to ensure that the sensing preparation stage p1 is located before the sensing input stage p2.
  • the shift register unit includes not only the first global reset circuit 6 but also the first leakage protection circuit 15 .
  • the first global reset circuit 6 is connected to the second power supply terminal through the first anti-leakage circuit 15, the first global reset circuit 6 and the first anti-leakage circuit 15 are connected to the first anti-leakage node Q1, the first anti-leakage node Q1 is connected to the first control voltage node OFF1, the first anti-leakage circuit 15 is connected to the global reset signal input terminal T-RST, and the first anti-leakage circuit 15 is configured to respond to the control of the valid level signal provided by the global reset signal input terminal T-RST to form a path between the first anti-leakage node Q1 and the second power supply terminal, and respond to the control of the non-valid level signal provided by the global reset signal input terminal T-RST to open the circuit between the first anti-leakage node Q1 and the second power supply terminal.
  • the first current limiting circuit 300 includes: a third load circuit 303, the third load circuit 303 is located between the first anti-leakage node Q1 and the first voltage control node OFF1, and is configured to increase the load resistance between the first anti-leakage node Q1 and the first voltage control node OFF1.
  • the third load circuit 303 includes: an eighty-second transistor M82; the control electrode of the eighty-second transistor M82 is connected to the first voltage control node OFF1, the first electrode of the eighty-second transistor M82 is connected to the first leakage prevention node Q1, and the second electrode of the eighty-second transistor M82 is connected to the first voltage control node OFF1.
  • the eighty-second transistor M82 can be equivalent to a diode, which does not affect the first voltage control circuit 14 to write the effective level signal to the first leakage prevention node Q1, and can also serve as a load resistor to limit the current.
  • the shift register unit includes not only the first pull-up noise reduction circuit 12 but also the third leakage prevention circuit 17.
  • the first pull-up noise reduction circuit 12 is connected to the second power supply terminal through the third leakage prevention circuit 17, the first pull-up noise reduction circuit 12 and the third leakage prevention circuit 17 are connected to the third leakage prevention node Q3, the third leakage prevention node Q3 is connected to the first voltage control node OFF1, the third leakage prevention circuit 17 is connected to the first pull-down node PD1, and the third leakage prevention circuit 17 is configured to form a path between the third leakage prevention node Q3 and the second power supply terminal in response to the control of the effective level signal at the first pull-down node PD1, and to disconnect the third leakage prevention node Q3 from the second power supply terminal in response to the control of the ineffective level signal at the first pull-down node PD1.
  • the first voltage control node when the third anti-leakage circuit 17 is provided, the first voltage control node will be connected to the third anti-leakage node Q3.
  • an instantaneous current is generated at the first voltage control node OFF1 if there is a path between the third anti-leakage node Q3 and the second power supply terminal, the instantaneous current generated at the first voltage control node OFF1 will flow to the second power supply terminal through the third anti-leakage node Q3 and the third anti-leakage circuit 17; if there is an open circuit between the third anti-leakage node Q3 and the second power supply terminal, the instantaneous current generated at the first voltage control node OFF1 will cause the third anti-leakage circuit 17 to generate a leakage current flowing to the second power supply terminal.
  • clock control signal input terminal CLKA and the global reset signal input terminal T-RST are both global signal input terminals, that is, all shift register units in the gate drive circuit are connected to the same clock control signal input terminal CLKA and the same global reset signal input terminal T-RST, when the level of the signal provided by the clock control signal input terminal CLKA or the global reset signal input terminal T-RST switches, instantaneous currents in the same direction will be generated at the first voltage control node OFF1 in all shift register units in the gate drive circuit at the same time. Correspondingly, instantaneous currents in the same direction will also be generated between the third leakage protection circuit 17 and the second power supply terminal in all shift register units at the same time.
  • the peak current of the instantaneous current between each shift register unit and the second power supply terminal is approximately I, and there are M-stage shift register units in the gate drive circuit.
  • the peak current of the instantaneous current at the second power supply terminal is approximately M*I, which can easily cause damage to the electrical devices connected to the second power supply terminal (for example, the signal transmission line connected to the second power supply terminal is burned out due to excessive loading current).
  • FIG12E is a simulation diagram of current changes at the first voltage control node and the second power supply terminal when the eighty-first transistor is not provided in the shift register unit shown in FIG12A.
  • the current peak value of the instantaneous current generated at the first voltage control node OFF1 is about 78uA
  • the current peak value of the instantaneous current at the second power supply terminal is about 0.42A.
  • FIG12F is a simulation diagram of the current change at the first voltage control node and the second power supply terminal when the eighty-first transistor is provided in the shift register unit shown in FIG12A. As shown in FIG12F, after the eighty-first transistor is provided, when the level of the signal provided by the clock control signal input terminal CLKA is switched, the current peak value of the instantaneous current generated at the first voltage control node OFF1 is about 38uA, and the current peak value of the instantaneous current at the second power supply terminal is about 0.28A.
  • the instantaneous current between the first voltage control node OFF1 and the third anti-leakage node Q3 in the shift register unit can be reduced, thereby reducing the instantaneous current between the third anti-leakage circuit 17 and the second power supply terminal, thereby reducing the instantaneous current at the second power supply terminal.
  • the instantaneous current between the first voltage control node OFF1 and the third anti-leakage node can be effectively reduced.
  • the schemes shown in FIG. 12A and FIG. 12B can both improve the problem of excessive instantaneous current at the second power supply terminal caused by the switching of the level of the signal provided by the clock control signal input terminal CLKA or the global reset signal input terminal T-RST.
  • the first current limiting circuit in the situations shown in Figures 12C and 12D includes: a fourth load circuit 304, which is located between the first voltage control node OFF1 and the third anti-leakage node Q3, and is configured to increase the load resistance between the first voltage control node OFF1 and the third anti-leakage node Q3.
  • the fourth load circuit 304 includes: a control electrode of an eighty-third transistor M83 connected to the first voltage control node OFF1, a first electrode of the eighty-third transistor M83 connected to the first voltage control node OFF1, and a second electrode of the eighty-third transistor M83 connected to the third leakage prevention node Q3.
  • the eighty-third transistor M83 can be equivalent to a diode, which does not affect the first voltage control circuit to write the effective level signal to the third leakage prevention node, and can also serve as a load resistor to limit the current.
  • the first current limiting circuit 300 may selectively include at least one of the first load circuit 301 (the eighty-first transistor M81), the second load circuit 302 (the eleventh capacitor C11), the third load circuit 303 (the eighty-second transistor M82), and the fourth load circuit 304 (the eighty-third transistor M83), all of which can effectively improve the problem of excessive instantaneous current at the second power supply terminal caused by switching of the level of the signal provided by the clock control signal input terminal CLKA or the global reset signal input terminal T-RST.
  • the first load circuit 301 the eighty-first transistor M81
  • the second load circuit 302 the eleventh capacitor C11
  • the third load circuit 303 the eighty-second transistor M82
  • the fourth load circuit 304 the eighty-third transistor M83
  • FIG12G is another circuit structure diagram of the shift register unit provided in the embodiment of the present disclosure.
  • the shift register unit shown in FIG12G includes a fifth load circuit 305; at least one of the first global reset circuit 6 and the first leakage protection circuit 15 is connected to the global reset signal input terminal T-RST through the fifth load circuit 305, and the fifth load circuit 305 is configured to increase the load resistance between at least one of the first global reset circuit 6 and the first leakage protection circuit 15 and the global reset signal input terminal T-RST.
  • both the first global reset circuit 6 and the first leakage protection circuit 15 are connected to the global reset signal input terminal T-RST through the fifth load circuit 305 as an example; by setting the fifth load circuit 305 to increase the load resistance between the first global reset circuit 6 and the first leakage protection circuit 15 and the global reset signal input terminal T-RST, the instantaneous current between the global reset signal input terminal T-RST and the first global reset circuit 6 and the first leakage protection circuit 15 can be reduced when the level of the signal provided by the global reset signal input terminal T-RST is switched, thereby reducing the instantaneous current between the first leakage protection node Q1 and the first voltage control node OFF1.
  • the fifth load circuit 305 includes: an eighty-fourth transistor M84; the control electrode of the eighty-fourth transistor M84 is connected to the global reset signal input terminal T-RST, the first electrode of the eighty-fourth transistor M84 is connected to the global reset signal input terminal T-RST, and the second electrode of the eighty-fourth transistor M84 is connected to at least one of the first global reset circuit 6 and the first anti-leakage circuit 15.
  • the fifth load circuit 305 shown in Figure 12G can also be selectively set as needed, and this situation should also fall within the protection scope of the present disclosure.
  • the shift register unit further includes: at least one of a first display input leakage protection circuit 7 ′ and a second leakage protection circuit 16 .
  • the first display input circuit 7 is connected to the first pull-up node through the first display input leakage protection circuit 7', the first display input circuit 7 and the first display input leakage protection circuit 7' are connected to the first display input leakage protection node XQ1, the first display input leakage protection node XQ1 is connected to the first voltage control node OFF1, the first display input leakage protection circuit 7' is connected to the display signal input terminal INPUT1, and the first display input leakage protection circuit 7' is configured to respond to the control of the valid level signal provided by the display signal input terminal INPUT1 so that a path is formed between the first display input leakage protection node XQ1 and the first pull-up node PU1, and respond to the control of the non-valid level signal provided by the display signal input terminal INPUT1 so that a break is formed between the first display input leakage protection node XQ1 and the first pull-up node PU1.
  • the first display reset circuit 8 is connected to the second power supply terminal through the first anti-leakage circuit 16.
  • the first display reset circuit 8 and the first anti-leakage circuit 16 are connected to the second anti-leakage node Q2.
  • the second anti-leakage node Q2 is connected to the first control voltage node OFF1.
  • the first anti-leakage circuit 16 is connected to the display reset signal input terminal RST.
  • the first anti-leakage circuit 16 is configured to form a path between the second anti-leakage node Q2 and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal RST, and to open the circuit between the second anti-leakage node Q2 and the second power supply terminal in response to the control of the non-valid level signal provided by the display reset signal input terminal RST.
  • the shift register unit further includes: a sensing control leakage prevention circuit 3; the sensing control circuit 1 is connected to the sensing control node H through the sensing control leakage prevention circuit 3, the sensing control leakage prevention circuit 3 and the sensing control circuit 1 are connected to the sensing control leakage prevention node, the sensing control leakage prevention circuit 3 is also connected to the first power supply terminal, the sensing control node H and the random signal input terminal OE, the sensing control leakage prevention circuit 3 is configured to respond to the control of the valid level signal at the sensing control node H, write the valid level signal provided by the first power supply terminal to the sensing control leakage prevention node, and is configured to respond to the control of the valid level signal provided by the random signal input terminal OE so that a path is formed between the sensing control leakage prevention node and the sensing control node H, and respond to the control of the non-valid level signal provided by the random signal input terminal OE so that a break is formed between the sensing control leakage prevention node and the sens
  • the sensing control circuit 1 the first sensing input circuit 2, the first global reset circuit 6, the first display input circuit 7, the first display reset circuit 8, the first drive signal output circuit 5, the second drive signal output circuit 9, the first cascade signal output circuit 13, the first pull-down control circuit 11, and the first pull-up noise reduction circuit 12 in Figures 12A to 12D and Figure 12G, please refer to those shown in Figures 10A and 10B above and will not be repeated here.
  • the first anti-leakage circuit 15 includes a twenty-first transistor M21
  • the second anti-leakage circuit 16 includes a twenty-second transistor M22
  • the third anti-leakage circuit 17 includes a twenty-third transistor M23
  • the sensing control anti-leakage circuit 3 includes a seventy-first transistor M71 and a seventy-second transistor M72
  • the first display input anti-leakage circuit 7' includes a seventy-third transistor M73.
  • the control electrode of the 21st transistor M21 is connected to the global reset signal input terminal T-RST, the first electrode of the 21st transistor M21 is connected to the global reset circuit and the first control voltage node OFF1, and the second electrode of the 22nd transistor M22 is connected to the second power supply terminal.
  • the control electrode of the 22nd transistor M22 is connected to the display reset signal input terminal RST, the first electrode of the 22nd transistor M22 is connected to the display reset circuit and the first control voltage node OFF1, and the second electrode of the 22nd transistor M22 is connected to the second power supply terminal.
  • the control electrode of the twenty-third transistor M23 is connected to the first pull-down node PD1, the first electrode of the twenty-third transistor M23 is connected to the first pull-down control circuit and the first control voltage node OFF1, and the second electrode of the twenty-third transistor M23 is connected to the second power supply terminal.
  • a control electrode of the seventy-first transistor M71 is connected to the sensing control node H, a first electrode of the seventy-first transistor M71 is connected to the sensing control anti-leakage node, and a second electrode of the seventy-first transistor M71 is connected to the first power supply terminal.
  • a control electrode of the seventy-second transistor M72 is connected to the random signal input terminal OE, a first electrode of the seventy-second transistor M72 is connected to the sensing control anti-leakage node, and a second electrode of the seventy-second transistor M72 is connected to the sensing control node H.
  • a control electrode of the seventy-third transistor M73 is connected to the display signal input terminal INPUT1, a first electrode of the seventy-third transistor M73 is connected to the first display input leakage prevention node XQ1, and a second electrode of the seventy-third transistor M72 is connected to the first pull-up node PU1.
  • the shift register unit also includes: a first pull-down noise reduction circuit 18; the first pull-down noise reduction circuit 18 is connected to the first pull-down node PD1, the second power supply terminal, the sensing control node H and the clock control signal input terminal CLKA, and the first pull-down noise reduction circuit 18 is configured to respond to the effective level signal at the sensing control node H and the effective level signal provided by the clock control signal input terminal CLKA, and write the non-effective level signal provided by the second power supply terminal to the first pull-down node PD1 to perform noise reduction processing on the voltage at the first pull-down node PD1.
  • the first pull-down noise reduction circuit 18 includes: a twenty-ninth transistor M29 and a thirtieth transistor M30; the control electrode of the twenty-ninth transistor M29 is connected to the clock control signal input terminal CLKA, the first electrode of the twenty-ninth transistor M29 is connected to the first pull-down node PD1, and the second electrode of the twenty-ninth transistor M29 is connected to the first electrode of the thirtieth transistor M30; the control electrode of the thirtieth transistor M30 is connected to the sensing control node H, and the second electrode of the thirtieth transistor M30 is connected to the second power supply terminal.
  • the first pull-down noise reduction circuit 18 also includes: an eighty-fifth transistor M85; wherein the first electrode of the twenty-ninth transistor M29 is connected to the first pull-down node PD1 through the eighty-fifth transistor M85; the control electrode of the eighty-fifth transistor M85 is connected to the sensing control node H, the first electrode of the eighty-fifth transistor M85 is connected to the first pull-down node PD1, and the second electrode of the eighty-fifth transistor M85 is connected to the first electrode of the twenty-ninth transistor M29.
  • the shift register unit also includes a second pull-down noise reduction circuit 19, which is connected to the first pull-down node PD1, the second power supply terminal and the pull-down noise reduction signal input terminal INPUT3.
  • the second pull-down noise reduction circuit 19 is configured to respond to the control of the valid level signal provided by the pull-down noise reduction signal input terminal INPUT3, and write the non-valid level signal provided by the second power supply terminal to the first pull-down node PD1 to perform noise reduction processing on the voltage at the first pull-down node PD1.
  • the second pull-down noise reduction circuit 19 includes: a thirty-first transistor M31; the control electrode of the thirty-first transistor M31 is connected to the pull-down noise reduction signal input terminal INPUT3, the first electrode of the thirty-first transistor M31 is connected to the first pull-down node PD1, and the second electrode of the thirty-first transistor M31 is connected to the second power supply terminal.
  • the pull-down noise reduction signal input terminal INPUT3 may be the sensing signal input terminal INPUT2.
  • FIG13A and FIG13B are schematic diagrams of two more circuit structures of the shift register unit provided in the embodiments of the present disclosure.
  • the shift register unit includes not only a sensing control circuit 1, a first sensing input circuit 2, and at least one first output circuit (e.g., a first drive output circuit), but also a second sensing input circuit 23 and at least one second output circuit (e.g., a third drive output circuit).
  • the shift register unit can provide drive signals for pixel units located in different rows in the display substrate.
  • the second sensing input circuit 23 is connected to the clock control signal input terminal CLKA, the second pull-up node PU2 and the preset power supply node.
  • the second sensing input circuit 23 is configured to respond to the control of the effective level signal provided by the clock control signal input terminal CLKA, so that a path is formed between the preset power supply node and the second pull-up node PU2;
  • At least one second output circuit is connected to the second pull-up node PU2, the corresponding second clock signal input terminal and the corresponding second signal output terminal, and is configured to write the signal provided by the corresponding second clock signal input terminal to the corresponding second signal output terminal in response to the control of the effective level signal at the second pull-up node PU2.
  • the above-mentioned at least one second output circuit at least includes a third drive output circuit 25; the third drive output circuit 25 is connected to the second pull-up node PU2, the third drive clock signal input terminal CLKE’ (the second clock signal input terminal corresponding to the third drive output circuit 25) and the third drive signal output terminal OUT2’ (the second signal output terminal corresponding to the third drive output circuit 25), and the third drive output circuit 25 is configured to write the signal provided by the third drive clock signal input terminal CLKE’ to the third drive signal output terminal OUT2’ in response to the control of the effective level signal at the second pull-up node PU2.
  • the preset power supply node may be a first sensing input anti-leakage node, and in this case, the first sensing input circuit 2 and the second sensing input circuit 23 may share a voltage control node.
  • the second sensing input circuit 23 includes: a thirty-third transistor M33, the control electrode of the thirty-third transistor M33 is connected to the clock control signal input terminal CLKA, the first electrode of the thirty-third transistor M33 is connected to a preset power supply node (the first sensing input anti-leakage node SQ1 in Figures 13A and 13B), and the second electrode of the thirty-third transistor M33 is connected to the second pull-up node PU2.
  • the first sensing input circuit 2 and the second sensing input circuit 23 can share the first voltage control node.
  • the first sensing input circuit 2 and the second sensing input circuit 23 can also share the same first current limiting circuit to improve the problem of instantaneous large current generated at the first voltage control node when the level of the signal provided by the clock control signal input terminal CLKA (connected to both the first sensing input circuit and the second sensing input circuit 23) is switched.
  • the first current limiting circuit includes the first load circuit 301 and the first load circuit 301 includes the eighty-first transistor M81 is exemplarily drawn, and this case only serves as an example.
  • the shift register unit also includes: a second voltage control circuit 34 and a second current limiting circuit 400; the second voltage control circuit 34 is connected to the first power supply terminal, the second pull-up node PU2 and the second voltage control node OFF2, and the second voltage control circuit 34 is configured to write the valid level signal provided by the first power supply terminal to the second voltage control node OFF2 in response to the control of the valid level signal at the second pull-up node PU2; the second current limiting circuit 400 is connected to the second voltage control node OFF2, and the second current limiting circuit 400 is configured to reduce the charging and discharging current at the second voltage control node OFF2.
  • the second voltage control circuit 34 includes: a fiftieth transistor M50; the control electrode of the fiftieth transistor M50 is connected to the second pull-up node PU2, the first electrode of the fiftieth transistor M50 is connected to the first power supply terminal, and the second electrode of the fiftieth transistor M50 is connected to the second voltage control node OFF2.
  • the first sensing input circuit 2 and the second sensing input circuit 23 can realize the sharing of the first voltage control node OFF1 and the second voltage control node OFF2.
  • the first sensing input circuit 2 and the second sensing input circuit 23 can also realize the sharing of the first current limiting circuit 300 and the second current limiting circuit 400; wherein, the first current limiting circuit 300 can improve the problem of the instantaneous large current generated at the first voltage control node OFF1 when the level of the signal provided by the clock control signal input terminal switches, and the second current limiting circuit 400 can improve the problem of the instantaneous large current generated at the second voltage control node OFF2 when the level of the signal provided by the clock control signal input terminal switches.
  • the second current limiting circuit 400 includes: an eleventh load circuit 401, located between the first sensing input anti-leakage node SQ1 and the second control voltage node OFF2, configured to increase the load resistance between the first sensing input anti-leakage node SQ1 and the second control voltage node OFF2.
  • the eleventh load circuit 401 includes: a ninety-first transistor M91; the control electrode of the ninety-first transistor M91 is connected to the second control voltage node OFF2, the first electrode of the ninety-first transistor M91 is connected to the second control voltage node OFF2, and the second electrode of the ninety-first transistor M91 is connected to the first sensing input anti-leakage node SQ1.
  • the shift register unit further includes: a second voltage control circuit 34, a second sensing input anti-leakage circuit 23' and a second current limiting circuit 400.
  • the second voltage control circuit 34 is connected to the first power supply terminal, the second pull-up node PU2 and the second voltage control node OFF2.
  • the second voltage control circuit 34 is configured to write the valid level signal provided by the first power supply terminal to the second voltage control node OFF2 in response to the control of the valid level signal at the second pull-up node PU2.
  • the second sensing input circuit 23 is connected to the second pull-up node PU2 through the second sensing input leakage protection circuit 23’, the second sensing input circuit 23 and the second sensing input leakage protection circuit 23’ are connected to the second sensing input leakage protection node SQ2, the second sensing input leakage protection node SQ2 is connected to the second voltage control node OFF2, the second sensing input leakage protection circuit 23’ is connected to the clock control signal input terminal CLKA, and the second sensing input leakage protection circuit 23’ is configured to form a path between the second sensing input leakage protection node SQ2 and the second pull-up node PU2 in response to the control of the valid level signal at the clock control signal input terminal CLKA, and to form a break between the second sensing input leakage protection node SQ2 and the second pull-up node PU2 in response to the control of the ineffective level signal at the clock control signal input terminal CLKA.
  • the second current limiting circuit 400 is connected to the second voltage control node OFF2 , and the second current limiting circuit 400 is configured to reduce the charge and discharge current at the second voltage control node OFF2 .
  • the second current limiting circuit 400 can be arranged between the second sensing input anti-leakage node SQ2 and the second voltage control node OFF2 in the case shown in FIG. 14A, or not arranged between the second sensing input anti-leakage node SQ2 and the second voltage control node OFF2 in the case shown in FIG. 14B.
  • the second current limiting circuit 400 in the embodiment of the present disclosure can also be partially arranged between the second sensing input anti-leakage node SQ2 and the second voltage control node OFF2, and the other part is not arranged between the second sensing input anti-leakage node SQ2 and the second voltage control node OFF2, that is, it includes the cases shown in both FIG. 14A and FIG. 14B (the corresponding drawings are not shown).
  • the second sensing input anti-leakage circuit 23' includes: a 38th transistor M38; the control electrode of the 38th transistor M38 is connected to the clock control signal input terminal CLKA, the first electrode of the 38th transistor M38 is connected to the second sensing input circuit 23, and the second electrode of the 38th transistor M38 is connected to the second pull-up node PU2;
  • the second current limiting circuit 400 includes: an eleventh load circuit 401, which is located between the second sensing input anti-leakage node SQ2 and the second control voltage node OFF2, and is configured to increase the load resistance between the second sensing input anti-leakage node SQ2 and the second control voltage node OFF2.
  • the eleventh load circuit 401 includes: a ninety-first transistor M91; the control electrode of the ninety-first transistor M91 is connected to the second voltage control node OFF2, the first electrode of the ninety-first transistor M91 is connected to the second sensing input anti-leakage node SQ2, and the second electrode of the ninety-first transistor M91 is connected to the second voltage control node OFF2.
  • the ninety-first transistor M91 can be equivalent to a diode, which does not affect the second voltage control circuit to write the effective level signal to the second sensing input anti-leakage node SQ2, and can also serve as a load resistor to limit the current.
  • the second current limiting circuit 400 includes: a twelfth load circuit 402 connected to the second voltage control node OFF2 and the second power supply terminal, and configured to increase the load capacitance at the second voltage control node OFF2.
  • a twelfth load circuit 402 connected to the second voltage control node OFF2 and the second power supply terminal, and configured to increase the load capacitance at the second voltage control node OFF2.
  • the twelfth load circuit 402 includes: a twelfth capacitor C12; a first end of the twelfth capacitor C12 is connected to the second voltage control node OFF2, and a second end of the twelfth capacitor C12 is connected to the second power supply end.
  • the shift register unit further includes a second global reset circuit 26, a second display input circuit 27, and a second display reset circuit 28.
  • At least one second output circuit includes not only a third drive output circuit 25, but also a fourth drive output circuit 29.
  • the second global reset circuit 26 is connected to the global reset signal input terminal T-RST, the second power supply terminal, and the second pull-up node PU2.
  • the second global reset circuit 26 is configured to write the non-valid level signal provided by the second power supply terminal to the second pull-up node PU2 in response to the control of the valid level signal provided by the global reset signal input terminal T-RST.
  • the second display input circuit 27 is connected to the display signal input terminal INPUT1 and the second pull-up node PU2 , and is configured to write the effective level signal into the second pull-up node PU2 in response to the control of the effective level signal provided by the display signal input terminal INPUT1 .
  • the second display reset circuit 28 is connected to the display reset signal input terminal RST, the second power supply terminal, and the second pull-up node PU2, and is configured to write the non-valid level signal provided by the second power supply terminal to the second pull-up node PU2 in response to the control of the valid level signal provided by the display reset signal input terminal RST.
  • the fourth drive output circuit 29 is connected to the second pull-up node PU2, the fourth drive clock signal input terminal CLKD’, and the fourth drive signal output terminal OUT1’, and is configured to write the signal provided by the fourth drive clock signal input terminal CLKD’ to the fourth drive signal output terminal OUT1’ in response to the control of the effective level signal at the second pull-up node PU2.
  • the fourth drive output circuit 29 can provide a drive signal for another first gate line G1 on the display panel other than the first gate line G1 connected to the second drive output circuit 9 .
  • the shift register unit when the shift register unit includes the first drive output circuit 5, the second drive output circuit 9, the third drive output circuit 25, and the fourth drive output circuit 29, the first drive output circuit 5 and the second drive output circuit 9 can be used to provide corresponding drive signals to a first gate line and a second gate line configured by a row of pixel units in the display panel, respectively, and at the same time, the third drive output circuit 25 and the fourth drive output circuit 29 can be used to provide corresponding drive signals to a first gate line and a second gate line configured by another row of pixel units in the display panel, respectively.
  • the shift register unit provided in the present embodiment can be used to drive four gate lines configured by two rows of pixel units (for example, two adjacent rows of pixel units).
  • the shift register unit further includes: a second pull-down control circuit 31 and a second pull-up noise reduction circuit 32 .
  • the second pull-down control circuit 31 is connected to the second power supply terminal, the sixth power supply terminal, the second pull-up node PU2 and the second pull-down node PD2, and is configured to write a voltage that is inversely proportional to the voltage at the second pull-up node PU2 to the second pull-down node PD2;
  • the second pull-up noise reduction circuit 32 is connected to the second power supply terminal, the second pull-up node PU2 and the second pull-down node PD2, and is configured to write the non-valid level signal provided by the second power supply terminal to the second pull-up node PU2 in response to the control of the valid level signal at the second pull-down node PD2.
  • the third drive output circuit 25 is also connected to the second pull-down node PD2 and the fourth power supply terminal, and the third drive output circuit 25 is also configured to write the non-valid level signal provided by the fourth power supply terminal to the third drive signal output terminal OUT2' in response to the control of the valid level signal at the second pull-down node PD2.
  • the fourth drive output circuit 29 is also connected to the second pull-down node PD2 and the fourth power supply terminal.
  • the fourth drive output circuit 29 is also configured to write the non-valid level signal provided by the fourth power supply terminal to the fourth drive signal output terminal OUT1' in response to the control of the valid level signal at the second pull-down node PD2.
  • the shift register unit may further include a second cascade output circuit (not shown).
  • the second cascade output circuit is connected to the second pull-up node PU2, the second cascade clock signal input terminal, and the second cascade signal output terminal, and the second cascade output circuit is configured to respond to the control of the valid level signal at the second pull-up node PU2 to write the signal provided by the second cascade clock signal input terminal to the second cascade signal output terminal.
  • the second cascade output circuit may also be connected to the second power supply terminal and the second pull-down node PD2, and the second cascade output circuit is configured to respond to the control of the valid level signal at the second pull-down node PD2 to write the non-valid level signal provided by the second power supply terminal to the second cascade signal output terminal.
  • the second sensing input circuit 23 includes: a thirty-third transistor M33, the control electrode of the thirty-third transistor M33 is connected to the clock control signal input terminal CLKA, the first electrode of the thirty-third transistor M33 is connected to a preset power supply node (the sensing intermediate node in Figures 15A and 15B), and the second electrode of the thirty-third transistor M33 is connected to the second sensing input anti-leakage node SQ2.
  • the second sensing input anti-leakage circuit 23' comprises: a 38th transistor M38; the control electrode of the 38th transistor M38 is connected to the clock control signal input terminal CLKA, the first electrode of the 38th transistor M38 is connected to the second sensing input circuit 23, and the second electrode of the 38th transistor M38 is connected to the second pull-up node PU2;
  • the second display input circuit 27 includes a 39th transistor M39.
  • the control electrode of the 39th transistor M39 is connected to the display signal input terminal INPUT1, the first electrode of the 39th transistor M39 is connected to the first power supply terminal, and the second electrode of the 39th transistor M39 is connected to the second pull-up node PU2.
  • the third driving output circuit 25 includes a thirty-fifth transistor M35 and a forty-seventh transistor M47, and the fourth driving output circuit 29 includes a forty-fifth transistor M45 and a forty-eighth transistor M48;
  • control electrode of the thirty-fifth transistor M35 is connected to the second upper PU2, the first electrode of the thirty-fifth transistor M35 is connected to the third drive clock signal input terminal CLKE’, and the second electrode of the thirty-fifth transistor M35 is connected to the third drive signal output terminal OUT2’.
  • the control electrode of the forty-seventh transistor M47 is connected to the second pull-down node PD2, the first electrode of the forty-seventh transistor M47 is connected to the third drive signal output terminal OUT2', and the second electrode of the forty-seventh transistor M47 is connected to the fourth power supply terminal.
  • the control electrode of the forty-fifth transistor M45 is connected to the second pull-up node PU2, the first electrode of the forty-fifth transistor M45 is connected to the fourth drive clock signal input terminal CLKD’, and the second electrode of the forty-fifth transistor M45 is connected to the fourth drive signal output terminal OUT1’.
  • the control electrode of the forty-eighth transistor M48 is connected to the second pull-down node PD2, the first electrode of the forty-eighth transistor M48 is connected to the fourth drive signal output terminal OUT1', and the second electrode of the forty-eighth transistor M48 is connected to the fourth power supply terminal.
  • a fourth capacitor C4 is configured for the third driving signal output terminal OUT2'.
  • the second global reset circuit 26 includes a thirty-seventh transistor M37
  • the second display reset circuit 28 includes a fortieth transistor M40
  • the second pull-down control circuit 31 includes a forty-second transistor M42 and a forty-third transistor M43
  • the second pull-up noise reduction circuit 32 includes a forty-fourth transistor M44.
  • a control electrode of the 37th transistor M37 is connected to the global reset signal input terminal T-RST, a first electrode of the 37th transistor M37 is connected to the second pull-up node PU2, and a second electrode of the 37th transistor M37 is connected to the non-valid level supply terminal.
  • a control electrode of the 40th transistor M40 is connected to the display reset signal input terminal RST, a first electrode of the 40th transistor M40 is connected to the second pull-up node PU2, and a second electrode of the 40th transistor M40 is connected to the non-active level supply terminal.
  • the control electrode of the forty-second transistor M42 is connected to the sixth power supply terminal, the first electrode of the forty-second transistor M42 is connected to the sixth power supply terminal (the sixth power supply terminal provides a voltage VDDB), and the second electrode of the forty-second transistor M42 is connected to the second pull-down node PD2.
  • a control electrode of the forty-third transistor M43 is connected to the second pull-up node PU2, a first electrode of the forty-third transistor M43 is connected to the second pull-down node PD2, and a second electrode of the forty-third transistor M43 is connected to the non-effective level supply terminal.
  • a control electrode of the forty-fourth transistor M44 is connected to the second pull-down node PD2, a first electrode of the forty-fourth transistor M44 is connected to the second pull-up node PU2, and a second electrode of the forty-fourth transistor M44 is connected to the non-active level supply terminal.
  • the fifth power supply terminal provides a voltage VDDA and the sixth power supply terminal provides a voltage VDDB
  • VDDA and VDDB can be switched between a high level voltage and a low level voltage (for example, switching is performed every 1 frame or several frames), and at any time, one of VDDA and VDDB is a high level voltage and the other is a low level voltage.
  • 16A to 16D are schematic diagrams of four more circuit structures of the shift register unit provided in the embodiments of the present disclosure. As shown in FIGS. 16A to 16D , in some embodiments, the shift register unit includes not only a second global reset circuit but also a fourth anti-leakage circuit 35 .
  • the second global reset circuit 26 is connected to the second power supply terminal through the fourth anti-leakage circuit 35, the second global reset circuit 26 and the fourth anti-leakage circuit 35 are connected to the fourth anti-leakage node Q4, the fourth anti-leakage node Q4 is connected to the second control voltage node OFF2, the fourth anti-leakage circuit 35 is connected to the sensing reset signal input terminal T-RST, and the fourth anti-leakage circuit 35 is configured to respond to the control of the valid level signal provided by the sensing reset signal input terminal T-RST to form a path between the fourth anti-leakage node Q4 and the second power supply terminal, and respond to the control of the non-valid level signal provided by the cascade reset signal input terminal to open the circuit between the fourth anti-leakage node Q4 and the second power supply terminal.
  • the second current limiting circuit 400 includes: a thirteenth load circuit 403, the thirteenth load circuit 403 is located between the fourth anti-leakage node Q4 and the second voltage control node OFF2, and is configured to increase the load resistance between the fourth anti-leakage node Q4 and the second voltage control node OFF2.
  • the thirteenth load circuit 403 includes: a ninety-second transistor M92; the control electrode of the ninety-second transistor M92 is connected to the second voltage control node OFF2, the first electrode of the ninety-second transistor M92 is connected to the fourth leakage prevention node Q4, and the second electrode of the ninety-second transistor M92 is connected to the second voltage control node OFF2.
  • the ninety-second transistor M92 can be equivalent to a diode, which does not affect the second voltage control circuit to write the effective level signal to the fourth leakage prevention node Q4, and can also serve as a load resistor to limit the current.
  • the shift register unit includes not only the second pull-up noise reduction circuit 32 but also the sixth leakage prevention circuit 37.
  • the second pull-up noise reduction circuit 32 is connected to the second power supply terminal through the sixth leakage prevention circuit 37
  • the second pull-up noise reduction circuit 32 and the sixth leakage prevention circuit 37 are connected to the sixth leakage prevention node Q6
  • the sixth leakage prevention node Q6 is connected to the second voltage control node OFF2
  • the sixth leakage prevention circuit 37 is connected to the second pull-down node PD2
  • the sixth leakage prevention circuit 37 is configured to form a path between the sixth leakage prevention node Q6 and the second power supply terminal in response to the control of the effective level signal at the second pull-down node PD2, and to disconnect the sixth leakage prevention node Q6 from the second power supply terminal in response to the control of the ineffective level signal at the second pull-down node PD2.
  • clock control signal input terminal CLKA and the global reset signal input terminal T-RST are both global signal input terminals, that is, all shift register units in the gate drive circuit are connected to the same clock control signal input terminal CLKA and the same global reset signal input terminal T-RST, when the level of the signal provided by the clock control signal input terminal CLKA or the global reset signal input terminal T-RST switches, instantaneous currents in the same direction will be generated at the second voltage control node OFF2 in all shift register units in the gate drive circuit at the same time. Correspondingly, instantaneous currents in the same direction will also be generated between the sixth leakage protection circuit 37 and the second power supply terminal in all shift register units at the same time.
  • the instantaneous current between the second voltage control node OFF2 and the sixth leakage prevention node in the shift register unit can be reduced, thereby reducing the instantaneous current between the sixth leakage prevention circuit 37 and the second power supply terminal.
  • the instantaneous current between the second voltage control node OFF2 and the third leakage prevention node Q3 can be effectively reduced.
  • the schemes shown in FIG. 16A and FIG. 16B can both improve the problem of excessive instantaneous current at the second power supply terminal caused by the switching of the level of the signal provided by the clock control signal input terminal CLKA or the global reset signal input terminal T-RST.
  • the second current limiting circuit 400 shown in Figures 16C and 16D includes: a fourteenth load circuit 404, the fourteenth load circuit 404 is located between the second voltage control node OFF2 and the sixth anti-leakage node Q6, and the fourteenth load circuit 404 is configured to increase the load resistance between the second voltage control node OFF2 and the sixth anti-leakage node Q6.
  • the fourteenth load circuit 404 includes: a control electrode of a ninety-third transistor M93 connected to the second voltage control node OFF2, a first electrode of the ninety-third transistor M93 connected to the second voltage control node OFF2, and a second electrode of the ninety-third transistor M93 connected to the sixth leakage prevention node Q6.
  • the ninety-third transistor M93 can be equivalent to a diode, which does not affect the second voltage control circuit 34 writing the effective level signal to the sixth leakage prevention node Q6, and can also serve as a load resistor to limit the current.
  • the second current limiting circuit 400 may selectively include at least one of the eleventh load circuit 401 (ninety-first transistor M91), the twelfth load circuit 402 (twelfth capacitor C12), the thirteenth load circuit 403 (ninety-second transistor M92), and the fourteenth load circuit 404 (ninety-third transistor M93), all of which can effectively improve the problem of excessive instantaneous current at the second power supply terminal caused by switching of the level of the signal provided by the clock control signal input terminal CLKA or the global reset signal input terminal T-RST.
  • FIG16E is another circuit structure diagram of the shift register unit provided in the embodiment of the present disclosure.
  • the shift register unit shown in FIG16E includes a fifth load circuit 405; at least one of the second global reset circuit 26 and the fourth anti-leakage circuit 35 is connected to the global reset signal input terminal T-RST through the fifteenth load circuit 405, and the fifteenth load circuit 405 is configured to increase the load resistance between at least one of the second global reset circuit 26 and the fourth anti-leakage circuit 35 and the global reset signal input terminal T-RST.
  • the instantaneous current between the global reset signal input terminal T-RST and the second global reset circuit 26 and the fourth anti-leakage circuit 35 can be reduced when the level of the signal provided by the global reset signal input terminal T-RST is switched, thereby reducing the instantaneous current between the fourth anti-leakage node Q4 and the second voltage control node.
  • the fifteenth load circuit 405 includes: a ninety-fourth transistor M94; the control electrode of the ninety-fourth transistor M94 is connected to the global reset signal input terminal T-RST, the first electrode of the ninety-fourth transistor M94 is connected to the global reset signal input terminal T-RST, and the second electrode of the ninety-fourth transistor M94 is connected to at least one of the first global reset circuit and the fourth anti-leakage circuit 35.
  • the fifteenth load circuit 405 in FIG. 12G may also be selectively provided in the shift register unit shown in the previous embodiments (for example, the shift register unit shown in FIGS. 16B to 16D ) as required, and these situations should also fall within the protection scope of the present disclosure.
  • the shift register unit further includes: at least one of a second display input leakage protection circuit 27' and a fifth leakage protection circuit.
  • the second display input circuit 27 is connected to the second pull-up node through the second display input leakage protection circuit 27’, the second display input circuit 27 and the second display input leakage protection circuit 27’ are connected to the second display input leakage protection node XQ2, the second display input leakage protection node XQ2 is connected to the second voltage control node, the second display input leakage protection circuit 27’ is connected to the display signal input terminal INPUT1, and the second display input leakage protection circuit 27’ is configured to form a path between the second display input leakage protection node XQ2 and the second pull-up node PU2 in response to the control of the valid level signal provided by the second display input leakage protection node, and to form a break between the second display input leakage protection node XQ2 and the second pull-up node PU2 in response to the control of the non-valid level signal provided by the second display input leakage protection node.
  • the second display reset circuit 28 is connected to the second power supply terminal through the fifth anti-leakage circuit 36.
  • the second display reset circuit 28 and the fifth anti-leakage circuit 36 are connected to the fifth anti-leakage node Q5.
  • the fifth anti-leakage node Q5 is connected to the second voltage control node OFF2.
  • the fifth anti-leakage circuit 36 is connected to the display reset signal input terminal RST.
  • the fifth anti-leakage circuit 36 is configured to form a path between the fifth anti-leakage node Q5 and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal RST, and to form a break between the fifth anti-leakage node Q5 and the second power supply terminal in response to the control of the non-valid level signal provided by the display reset signal input terminal RST.
  • the fourth leakage protection circuit 35 includes a fifty-first transistor M51; the control electrode of the fifty-first transistor M51 is connected to the sensing reset signal input terminal T-RST, the first electrode of the fifty-first transistor M51 is connected to the sensing reset circuit and the second control voltage node OFF2, and the second electrode of the fifty-second transistor M52 is connected to the second power supply terminal.
  • the fifth leakage protection circuit 36 includes a fifty-second transistor M52; the control electrode of the fifty-second transistor M52 is connected to the display reset signal input terminal RST, the first electrode of the fifty-second transistor M52 is connected to the display reset circuit and the second control voltage node OFF2, and the second electrode of the fifty-second transistor M52 is connected to the second power supply terminal.
  • the sixth leakage protection circuit 37 includes: a fifty-third transistor M53; the control electrode of the fifty-third transistor M53 is connected to the second pull-down node PD2, the first electrode of the fifty-third transistor M53 is connected to the second pull-down control circuit and the second control voltage node OFF2, and the second electrode of the fifty-third transistor M53 is connected to the second power supply terminal.
  • the second display input leakage protection circuit 27' includes: a seventy-fourth transistor M74; the control electrode of the seventy-fourth transistor M74 is connected to the display signal input terminal INPUT1, the first electrode of the seventy-fourth transistor M74 is connected to the second display input leakage protection node XQ2, and the second electrode of the seventy-fourth transistor M74 is connected to the second pull-up node PU2.
  • the shift register unit also includes: a third pull-down noise reduction circuit 38; the third pull-down noise reduction circuit 38 is connected to the second pull-down node PD2, the second power supply terminal, the sensing control node H and the clock control signal input terminal CLKA, and the third pull-down noise reduction circuit 38 is configured to respond to the effective level signal at the sensing control node H and the effective level signal provided by the clock control signal input terminal CLKA, and write the non-effective level signal provided by the second power supply terminal to the second pull-down node PD2 to perform noise reduction processing on the voltage at the first pull-down node PD2.
  • the third pull-down noise reduction circuit 38 includes: a fifty-ninth transistor M59 and a sixtieth transistor M60; the control electrode of the fifty-ninth transistor M59 is connected to the clock control signal input terminal CLKA, the first electrode of the fifty-ninth transistor M59 is connected to the second pull-down node PD2, and the second electrode of the fifty-ninth transistor M59 is connected to the first electrode of the sixtieth transistor M60; the control electrode of the sixtieth transistor M60 is connected to the sensing control node H, and the second electrode of the sixtieth transistor M60 is connected to the second power supply terminal.
  • the third pull-down noise reduction circuit 38 also includes: a ninety-fifth transistor M95; the first electrode of the fifty-ninth transistor M59 is connected to the second pull-down node PD2 through the ninety-fifth transistor M95; the control electrode of the ninety-fifth transistor M95 is connected to the sensing control node H, the first electrode of the ninety-fifth transistor M95 is connected to the second pull-down node PD2, and the second electrode of the ninety-fifth transistor M95 is connected to the first electrode of the fifty-ninth transistor M59.
  • the shift register unit also includes a fourth pull-down noise reduction circuit 39, which is connected to the second pull-down node PD2, the second power supply terminal and the pull-down noise reduction signal input terminal INPUT3.
  • the second pull-down noise reduction circuit 19 is configured to respond to the control of the valid level signal provided by the pull-down noise reduction signal input terminal INPUT3, and write the non-valid level signal provided by the second power supply terminal to the second pull-down node PD2 to perform noise reduction processing on the voltage at the second pull-down node PD2.
  • control electrode of the sixty-first transistor M61 is connected to the pull-down noise reduction signal input terminal INPUT3, the first electrode of the sixty-first transistor M61 is connected to the second pull-down node PD2, and the second electrode of the sixty-first transistor M61 is connected to the second power supply terminal.
  • Fig. 17 is another schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure. As shown in Fig. 17, when the first pull-down node PD1 and the second pull-down node PD2 are configured in the shift register unit at the same time, in some embodiments, the third leakage protection circuit 17, the first pull-up noise reduction circuit 12, the first cascade output circuit 13, the first drive output circuit 5, and the second drive output circuit 9 are also connected to the second pull-down node PD2.
  • the third anti-leakage circuit 17 is also configured to write a non-valid level signal to the third anti-leakage point node in response to the control of the valid level signal at the second pull-down node PD2.
  • the third anti-leakage circuit 17 includes a twenty-third transistor M23 and a twenty-eighth transistor M28, wherein the control electrode of the twenty-third transistor M23 is connected to the first pull-down node PD1, and the control electrode of the twenty-eighth transistor M28 is connected to the second pull-down node PD2.
  • the first pull-up noise reduction circuit 12 is further configured to write a non-valid level signal to the first pull-up node PU1 in response to the control of the valid level signal at the second pull-down node PD2.
  • the first pull-up noise reduction circuit 12 includes a fourteenth transistor M14 and a twenty-seventh transistor M27, wherein the control electrode of the fourteenth transistor M14 is connected to the first pull-down node PD1, and the control electrode of the twenty-seventh transistor M27 is connected to the second pull-down node PD2.
  • the first cascade output circuit 13 is further configured to write a non-valid level signal to the first cascade signal output terminal CR in response to the control of the valid level signal at the second pull-down node PD2.
  • the cascade output circuit 13 includes a nineteenth transistor M19 and a twenty-fourth transistor M24, wherein the control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD1, and the control electrode of the twenty-fourth transistor M24 is connected to the second pull-down node PD2.
  • the first drive output circuit 5 is further configured to write a non-valid level signal to the first drive signal output terminal OUT2 in response to the control of the valid level signal at the second pull-down node PD2.
  • the first drive output circuit 5 also includes a seventeenth transistor M17 and a twenty-sixth transistor M26, wherein the control electrode of the seventeenth transistor M17 is connected to the first pull-down node PD1, and the control electrode of the twenty-sixth transistor M26 is connected to the second pull-down node PD2.
  • the second drive output circuit 9 is further configured to write a non-valid level signal to the second drive signal output terminal OUT1 in response to the control of the valid level signal at the second pull-down node PD2.
  • the second drive output circuit 9 also includes an eighteenth transistor M18 and a twenty-fifth transistor M25, wherein the control electrode of the eighteenth transistor M18 is connected to the first pull-down node PD1, and the control electrode of the twenty-fifth transistor M25 is connected to the second pull-down node PD2.
  • the sixth leakage protection circuit 37 , the second pull-up noise reduction circuit 32 , the third driving output circuit 25 , and the fourth driving output circuit 29 are connected to the first pull-down node PD1 .
  • the sixth anti-leakage circuit 37 is further configured to write a non-valid level signal to the sixth anti-leakage point node Q6 in response to the control of the valid level signal at the first pull-down node PD1.
  • the sixth anti-leakage circuit 37 includes a fifty-third transistor M53 and a fifty-eighth transistor M58, wherein the control electrode of the fifty-third transistor M53 is connected to the second pull-down node PD2, and the control electrode of the fifty-eighth transistor M58 is connected to the first pull-down node PD1.
  • the second pull-up noise reduction circuit 32 is further configured to write a non-valid level signal to the second pull-up node PU2 in response to the control of the valid level signal at the first pull-down node PD1.
  • the second pull-up noise reduction circuit 32 includes a 44th transistor M44 and a 57th transistor M57, wherein the control electrode of the 44th transistor M44 is connected to the second pull-down node PD2, and the control electrode of the 57th transistor M57 is connected to the first pull-down node PD1.
  • the third driver output circuit 25 is also configured to write a non-effective level signal to the third driver signal output terminal in response to the control of the effective level signal at the first pull-down node PD1.
  • the third driver output circuit 25 also includes a 47th transistor M47 and a 56th transistor M56, wherein the control electrode of the 47th transistor M47 is connected to the second pull-down node PD2, and the control electrode of the 56th transistor M56 is connected to the first pull-down node PD1.
  • the fourth drive output circuit 29 is further configured to write a non-effective level signal to the fourth drive signal output terminal in response to the control of the effective level signal at the first pull-down node PD1.
  • the fourth drive output circuit 29 also includes a 48th transistor M48 and a 55th transistor M55, wherein the control electrode of the 48th transistor M48 is connected to the second pull-down node PD2, and the control electrode of the 55th transistor M55 is connected to the first pull-down node PD1.
  • an inductor may be provided between each power supply terminal (especially the second power supply terminal) and the gate drive circuit (some output terminals of the general power management chip PMIC are used to provide power supply voltage to the display substrate as the power supply terminal configured by the gate drive circuit, so the inductor configured by the power supply terminal can be provided at the corresponding output terminal of the power management chip, and the power supply voltage output by the output terminal is transmitted to the gate drive circuit through the inductor), and an inductor may be provided between each first/second clock signal input terminal and the gate drive circuit (some output terminals of the general level conversion circuit level shifter are used to provide clock signals to the gate drive circuit, so the inductor configured by the clock signal input terminal can be provided at the corresponding output terminal of the level conversion circuit, and the clock signal output by the output terminal is transmitted to the gate drive circuit through the inductor).
  • FIG18 is a simulation diagram of the current change at the second power supply terminal after an inductor is set between the output terminal used as the second power supply terminal and the gate drive circuit on the power management chip in the embodiment of the present disclosure.
  • the current peak value of the instantaneous current at the second power supply terminal is about 47mA, which is much smaller than the current peak values of 0.42A and 0.28A at the second power supply terminal shown in FIG12E and FIG12F. It can be seen that the addition of the inductor can effectively slow down the current change of the second power supply terminal and reduce the current peak value of the instantaneous current.
  • FIG19 is a schematic diagram of a circuit structure of a gate drive circuit provided in an embodiment of the present disclosure.
  • FIG20 is a working timing diagram of the gate drive circuit shown in FIG19.
  • the gate drive circuit includes a plurality of cascaded shift register units SRU1 to SRU3, wherein the shift register units SRU1 to SRU3 may adopt the shift register units provided in any of the previous embodiments.
  • the shift register units please refer to the contents in the previous embodiments, which will not be repeated here.
  • each shift register unit SRU1 ⁇ SRU3 when each shift register unit SRU1 ⁇ SRU3 is used to drive the gate lines corresponding to two rows of pixel units, that is, the shift register unit includes a first drive output circuit 5, a second drive output circuit 9, a third drive output circuit 25, a fourth drive output circuit 29 and a first cascade output circuit 13.
  • each level of shift register units SRU1 ⁇ SRU3 can be regarded as two shift register circuits, for example, shift register unit SRU1 includes shift register circuits SR1 and SR2, shift register unit SRU2 includes shift register circuits SR3 and SR4, and shift register unit SRU3 includes shift register circuits SR5 and SR6.
  • N shift register units can be configured in the gate driving circuit.
  • the N shift register units are cascaded, which can be regarded as 2N shift register circuits cascaded, wherein the shift register circuit SR2n-1 located in the odd position is configured with a sensing signal input terminal INPUT2, a random signal input terminal OE, and a cascade signal output terminal CR, while the shift register circuit SR2n located in the even position is not configured with the sensing signal input terminal INPUT2 and the first cascade signal output terminal CR, wherein 1 ⁇ n ⁇ N and n is an integer.
  • FIG. 19 only exemplarily shows the case of three-stage shift register units SRU1 to SRU3 (six-stage shift register circuits SR1 to SR6 ), which is merely an example.
  • the sensing signal input terminal INPUT2 of each shift register unit SRU1 ⁇ SRU3 is connected to the first cascade signal output terminal CR configured by itself; the clock control signal input terminal CLKA of each shift register unit SRU1 ⁇ SRU3 is connected to the clock control signal line CKA, the global reset signal input terminal T-RST of each shift register unit SRU1 ⁇ SRU3 is connected to the global reset signal input line TRST’, and the random signal input terminal OE of each shift register unit is connected to the random signal input line OE’.
  • the sensing effective level supply end of the shift register unit is connected to the first pull-up node in a shift register unit located at the previous a level; or, for any shift register unit at a level except the shift register unit located at the last a level, the sensing effective level supply end of the shift register unit is connected to the first pull-up node in a shift register unit located at the next a level; wherein a is a positive integer (for example, a is 1).
  • the shift register unit at this level can use the voltage at the first pull-up node in a shift register unit located at the previous a level or the next a level to complete the charging of the first sensing control node in the shift register unit at this level.
  • the sensing signal input end of the shift register unit can also be connected to other terminals; for example, the sensing signal input end of the shift register unit at this level is connected to the cascade signal output end of a shift register unit at the previous b levels or the next b levels (b is a positive integer) of itself.
  • the technical solution disclosed in the present invention does not limit the terminal to which the sensing signal input terminal of the shift register unit is connected.
  • the sensing signal input terminal is connected to the third power supply terminal.
  • the display signal input terminal INPUT1 of the first-stage shift register unit SRU1 is connected to the frame start signal input terminal STV, and the display signal input terminal INPUT1 of any other stage of shift register unit except the first-stage shift register unit SRU1 is connected to the first cascade signal output terminal CR of the previous stage of shift register unit;
  • the global reset signal input terminal T-RST of each stage of shift register unit is connected to the global reset signal line;
  • the display reset signal input terminal RST of the shift register unit at the Nth stage and the shift register unit at the N-1th stage is connected to the frame end reset signal line, and the display reset signal input terminal RST of any other stage of shift register unit except the shift register units at the Nth stage and the N-1th stage is connected to the first cascade signal output terminal CR of the two subsequent stages of shift register units.
  • the gate driving circuit is configured with 6 first driving clock signal lines CKE1 ⁇ CKE6 and 6 second driving clock signal lines CKD1 ⁇ CKD6 ;
  • the first drive clock signal input terminal CLKE of the 3i+1-th shift register unit SRU3i+1 is connected to the first drive clock signal line CKE1
  • the second drive clock signal input terminal CLKD of the 3i+1-th shift register unit SRU3i+1 is connected to the second drive clock signal line CKD1
  • the third drive clock signal input terminal CLKE' of the 3i+1-th shift register unit SRU3i+1 is connected to the second drive clock signal line CKE2
  • the fourth drive clock signal input terminal CLKD' of the 3i+1-th shift register unit SRU3i+1 is connected to the second drive clock signal line CKD2
  • the cascade clock signal input terminal (not shown in Figure 19) of the 3i+1-th shift register unit SRU3i+1 is connected to the second drive clock signal line CKD2.
  • the first drive clock signal input terminal CLKE of the 3i+2-stage shift register unit SRU3i+2 is connected to the first drive clock signal line CKE3
  • the second drive clock signal input terminal CLKD of the 3i+2-stage shift register unit SRU3i+2 is connected to the second drive clock signal line CKD3
  • the third drive clock signal input terminal CLKE’ of the 3i+2-stage shift register unit SRU3i+2 is connected to the second drive clock signal line CKE4
  • the fourth drive clock signal input terminal CLKD’ of the 3i+2-stage shift register unit SRU3i+2 is connected to the second drive clock signal line CKD4
  • the cascade clock signal input terminal (not shown in FIG. 19 ) of the 3i+2-stage shift register unit SRU3i+2 is connected to the second drive clock signal line CKD4.
  • the first drive clock signal input terminal CLKE of the 3i+3rd-stage shift register unit SRU3i+3 is connected to the first drive clock signal line CKE5
  • the second drive clock signal input terminal CLKD of the 3i+3rd-stage shift register unit SRU3i+3 is connected to the second drive clock signal line CKD5
  • the third drive clock signal input terminal CLKE' of the 3i+3rd-stage shift register unit SRU3i+3 is connected to the second drive clock signal line CKE6
  • the fourth drive clock signal input terminal CLKD' of the 3i+3rd-stage shift register unit SRU3i+3 is connected to the second drive clock signal line CKD6
  • the cascade clock signal input terminal (not shown in FIG. 19) of the 3i+3rd-stage shift register unit SRU3i+3 is connected to the second drive clock signal line CKD6.
  • i is a positive integer and 3i+3 ⁇ N.
  • the embodiment of the present disclosure also provides a display substrate, wherein the display substrate includes a base substrate and a gate driving circuit located on the base substrate, wherein the gate driving circuit can adopt the gate driving circuit provided in the previous embodiment.
  • the gate driving circuit can adopt the gate driving circuit provided in the previous embodiment.
  • the gate driving circuit is prepared on a display substrate by using a GOA method, and the display substrate may specifically be an array substrate.
  • an embodiment of the present disclosure further provides a display device, which includes the display panel provided in the previous embodiment.
  • a display panel provided in the previous embodiment.
  • the display panel please refer to the content in the previous embodiment, which will not be repeated here.
  • the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a liquid crystal display, a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a liquid crystal display, a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device are well understood by those skilled in the art and will not be described in detail herein, nor should they be used as a limitation to the present disclosure.

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Abstract

一种移位寄存器单元，包括：第一感测控制输入电路（100）和至少一个第一输出电路，移位寄存器单元还包括：第一控压电路（14）、第一感测输入防漏电电路（2'）和第一限流电路（300），第一感测控制输入电路（100）通过第一感测输入防漏电电路（2'）与第一上拉节点（PU1）连接，第一感测控制输入电路（100）与第一感测输入防漏电电路（2'）连接于第一感测输入防漏电节点（SQ1），第一感测输入防漏电节点（SQ1）与第一控压节点连接（OFF1），第一感测输入防漏电电路（2'）与时钟控制信号输入端（CLKA）连接，第一感测输入防漏电电路（2'）配置为控制第一感测输入防漏电节点（SQ1）与第一上拉节点（PU1）之间的通断；第一限流电路（300）与第一控压节点（OFF1）连接。

Description

移位寄存器单元、栅极驱动电路和显示基板 技术领域
本发明涉及显示领域，特别涉及一种移位寄存器单元、栅极驱动电路和显示基板。
背景技术
有源矩阵有机发光二极体面板(Active Matrix Organic Light Emitting Diode，简称：AMOLED)的应用越来越广泛。AMOLED的像素显示器件为有机发光二极管(Organic Light-Emitting Diode,简称OLED)，AMOLED能够发光是通过驱动薄膜晶体管在饱和状态下产生驱动电流，该驱动电流驱动发光器件发光。
发明内容
第一方面，本公开实施例提供了一种移位寄存器单元，其中，包括：
第一感测控制输入电路，与感测控制节点、感测信号输入端、随机信号输入端、时钟控制信号输入端和第一上拉节点连接，配置为响应于所述随机信号输入端所提供有效电平信号的控制，将所述感测信号输入端所提供信号写入至所述感测控制节点，以及响应于所述感测控制节点处有效电平信号和所述时钟控制信号所提供有效电平信号的控制，将有效电平信号写入至所述第一上拉节点；
至少一个第一输出电路，所述第一输出电路与所述第一上拉节点、对应的第一时钟信号输入端和对应的第一信号输出端连接，配置为响应于所述第一上拉节点处有效电平信号的控制将对应的所述第一时钟信号输入端所提供信号写入至对应的所述第一信号输出端；
所述移位寄存器单元还包括：第一控压电路、第一感测输入防漏电 电路和第一限流电路；
所述第一控压电路与第一电源端、所述第一上拉节点和第一控压节点连接，所述第一控压电路配置为响应于所述第一上拉节点处有效电平信号的控制将所述第一电源端所提供有效电平信号写入至所述第一控压节点；
所述第一感测控制输入电路通过所述第一感测输入防漏电电路与所述第一上拉节点连接，所述第一感测控制输入电路与所述第一感测输入防漏电电路连接于第一感测输入防漏电节点，所述第一感测输入防漏电节点与所述第一控压节点连接，所述第一感测输入防漏电电路与所述时钟控制信号输入端连接，所述第一感测输入防漏电电路配置为响应于所述时钟控制信号输入端处有效电平信号的控制使得所述第一感测输入防漏电节点与所述第一上拉节点之间形成通路，以及响应于所述时钟控制信号输入端处非有效电平信号的控制使得所述第一感测输入防漏电节点与所述第一上拉节点之间形成断路；
所述第一限流电路与所述第一控压节点连接。
在一些实施例中，所述第一限流电路包括：
第一负载电路，位于所述第一感测输入防漏电节点与所述第一控压节点之间，配置为增大所述第一感测输入防漏电节点与所述第一控压节点之间的负载电阻。
在一些实施例中，所述第一负载电路包括：第八十一晶体管；
所述第八十一晶体管的控制极与所述第一控压节点连接，所述第八十一晶体管的第一极与所述第一感测输入防漏电节点连接，所述第八十一晶体管的第二极与所述第一控压节点连接。
在一些实施例中，所述第一限流电路包括：
第二负载电路，与所述第一控压节点和第二电源端连接，配置为增大所述第一控压节点处的负载电容。
在一些实施例中，所述第二负载电路包括：第十一电容；
所述第十一电容的第一端与所述第一控压节点连接，所述第十一电容的第二端与第二电源端连接。
在一些实施例中，还包括：
第一全局复位电路，与全局复位信号输入端、第二电源端、所述第一上拉节点连接，所述第一全局复位电路配置为响应于所述全局复位信号输入端所提供有效电平信号的控制将所述第二电源端所提供非有效电平信号写入至所述第一上拉节点；
所述第一防漏电电路，所述第一全局复位电路通过所述第一防漏电电路与第二电源端连接，所述第一全局复位电路与所述第一防漏电电路连接于第一防漏电节点，所述第一防漏电节点与所述第一控压节点连接，所述第一防漏电电路与全局复位信号输入端连接，所述第一防漏电电路配置为响应于所述全局复位信号输入端所提供有效电平信号的控制使得所述第一防漏电节点与所述第二电源端之间形成通路，以及响应于所述全局复位信号输入端所提供非有效电平信号的控制使得所述第一防漏电节点与所述第二电源端之间形成断路。
在一些实施例中，所述第一限流电路包括：
第三负载电路，位于所述第一防漏电节点与所述第一控压节点之间，配置为增大所述第一防漏电节点与所述第一控压节点之间的负载电阻。
在一些实施例中，所述第三负载电路包括：第八十二晶体管；
所述第八十二晶体管的控制极与所述第一控压节点连接，所述第八十二晶体管的第一极与所述第一防漏电节点连接，所述第八十二晶体管的第二极与所述第一控压节点连接。
在一些实施例中，还包括：
第五负载电路，所述第一全局复位电路和所述第一防漏电电路中至少之一通过所述第五负载电路与全局复位信号输入端连接，所述第五负 载电路配置增大所述第一全局复位电路和所述第一防漏电电路中至少之一与所述全局复位信号输入端之间的负载电阻。
在一些实施例中，所述第五负载电路包括：第八十四晶体管；
所述第八十四晶体管的控制极与所述全局复位信号输入端连接，所述第八十四晶体管的第一极与所述全局复位信号输入端连接，所述第八十四晶体管的第二极与所述第一全局复位电路和所述第一防漏电电路中至少之一连接。
在一些实施例中，还包括：
第一下拉控制电路，与第二电源端、第五电源端、所述第一上拉节点和第一下拉节点连接，配置为向所述第一下拉节点处写入与所述第一上拉节点处电压反相的电压；
第一上拉降噪电路，与所述第二电源端、所述第一上拉节点和第一下拉节点连接，配置为响应于所述第一下拉节点处有效电平信号的控制将所述第二电源端所提供非有效电平信号写入至所述第一上拉节点；
所述第一输出电路还与所述第一下拉节点和第二电源端连接，所述第一输出电路还配置为响应于所述第一下拉节点处有效电平信号的控制，将所述第二电源端提供的非有效电平信号写入至对应的所述第一信号输出端；
在一些实施例中，还包括：
第三防漏电电路，所述第一上拉降噪电路通过所述第三防漏电电路与第二电源端连接，所述第一上拉降噪电路与所述第三防漏电电路连接于第三防漏电节点，所述第三防漏电节点与所述第一控压节点连接，所述第三防漏电电路与第一下拉节点连接，所述第三防漏电电路配置为响应于所述第一下拉节点处有效电平信号的控制使得所述第三防漏电节点与所述第二电源端之间形成通路，以及响应于所述第一下拉节点处非有效电平信号的控制使得所述第三防漏电节点与所述第二电源端之间形成 断路。
在一些实施例中，所述第一控压节点位于所述第一感测输入防漏电节点与所述第三防漏电节点之间；
所述第一限流电路包括：
第四负载电路，位于所述第一控压节点与所述第三防漏电节点之间，配置为配置为增大所述第一控压节点与所述第三防漏电节点之间的负载电阻。
在一些实施例中，所述第四负载电路包括：
所述第八十三晶体管的控制极与所述第一控压节点连接，所述第八十三晶体管的第一极与所述第一控压节点连接，所述第八十三晶体管的第二极与所述第三防漏电节点连接。
在一些实施例中，还包括：
第一下拉降噪电路，与第一下拉节点、第二电源端、感测控制节点和时钟控制信号输入端连接，配置为响应于感测控制节点处有效电平信号和时钟控制信号输入端所提供有效电平信号的控制，将第二电源端提供的非有效电平信号写入至第一下拉节点。
在一些实施例中，所述第一下拉降噪电路包括：第二十九晶体管和第三十晶体管；
第二十九晶体管的控制极与时钟控制信号输入端连接，第二十九晶体管的第一极与第一下拉节点连接，第二十九晶体管的第二极与第三十晶体管的第一极连接；
第三十晶体管的控制极与感测控制节点连接，第三十晶体管的第二极与第二电源端连接。
在一些实施例中，所述第一下拉降噪电路还包括：第八十五晶体管，所述第二十九晶体管的第一极通过所述第八十五晶体管与所述第一下拉节点连接；
所述第八十五晶体管的控制极与所述感测控制节点连接，所述第八十五晶体管的第一极与所述第一下拉节点连接，所述第八十五晶体管的第二极与所述第二十九晶体管的第一极连接。
在一些实施例中，还包括：
第一显示输入电路，与显示信号输入端、第一电源端和第一上拉节点连接，配置为响应于所述显示信号输入端所提供有效电平信号的控制将所述第一电源端所提供有效电平信号写入至所述第一上拉节点；
第一显示复位电路，与显示复位信号输入端、第二电源端、所述第一上拉节点连接，配置为响应于所述显示复位信号输入端所提供有效电平信号的控制，将所述第二电源端所提供非有效电平信号写入至所述第一上拉节点。
在一些实施例中，还包括：第一显示输入防漏电电路和第二防漏电电路中至少之一；
所述第一显示输入电路通过所述第一显示输入防漏电电路与所述第一上拉节点连接，所述第一显示输入电路与所述第一显示输入防漏电电路连接于第一显示输入防漏电节点，所述第一显示输入防漏电节点与所述第一控压节点连接，所述第一显示输入防漏电电路与所述显示信号输入端连接，所述第一显示输入防漏电电路配置为响应于所述显示信号输入端所提供有效电平信号的控制使得所述第一显示输入防漏电节点与所述第一上拉节点之间形成通路，以及响应于所述显示信号输入端所提供非有效电平信号的控制使得所述第一显示输入防漏电节点与所述第一上拉节点之间形成断路；
所述第一显示复位电路通过所述第二防漏电电路与第二电源端连接，所述第一显示复位电路与所述第二防漏电电路连接于第二防漏电节点，所述第二防漏电节点与所述第一控压节点连接，所述第二防漏电电路与显示复位信号输入端连接，所述第二防漏电电路配置为响应于所述 显示复位信号输入端所提供有效电平信号的控制使得所述第二防漏电节点与所述第二电源端之间形成通路，以及响应于所述显示复位信号输入端所提供非有效电平信号的控制使得所述第二防漏电节点与所述第二电源端之间形成断路。
在一些实施例中，所述第一感测控制输入电路包括：感测控制电路和第一感测输入电路；
所述感测控制电路与所述感测控制节点、所述感测信号输入端和所述随机信号输入端连接，所述感测控制电路配置为响应于所述随机信号输入端所提供有效电平信号的控制，将所述感测信号输入端所提供信号写入至所述感测控制节点；
所述第一感测输入电路与所述感测控制节点、时钟控制信号输入端、感测中间节点和所述第一上拉节点连接，配置为响应于所述感测控制节点处有效电平信号的控制，将有效电平信号写入至所述感测中间节点，以及响应于所述时钟控制信号输入端所提供有效电平信号的控制，使得所述感测中间节点与所述第一上拉节点之间形成通路。
在一些实施例中，还包括：感测控制防漏电电路；
所述感测控制电路通过所述感测控制防漏电电路与感测控制节点连接，所述感测控制防漏电电路与所述感测控制电路连接于感测控制防漏电节点，所述感测控制防漏电电路还与所述第一电源端、感测控制节点和随机信号输入端连接，所述感测控制防漏电电路配置为响应于所述感测控制节点处有效电平信号的控制，将所述第一电源端提供的有效电平信号写入至所述感测控制防漏电节点，以及配置为响应于所述随机信号输入端所提供有效电平信号的控制使得所述感测控制防漏电节点与所述感测控制节点之间形成通路，以及响应于所述随机信号输入端所提供非有效电平信号的控制使得所述感测控制防漏电节点与所述感测控制节点之间形成断路。
在一些实施例中，还包括：
第二感测输入电路，与所述时钟控制信号输入端、第二上拉节点和预设供电节点连接，配置为响应于所述时钟控制信号输入端所提供有效电平信号的控制，使得所述预设供电节点与所述第二上拉节点之间形成通路；
至少一个第二输出电路，所述第二输出电路与所述第二上拉节点、对应的第二时钟信号输入端和对应的第二信号输出端连接，配置为响应于所述第二上拉节点处有效电平信号的控制将对应的所述第二时钟信号输入端所提供信号写入至对应的所述第二信号输出端；
所述预设供电节点为所述感测中间节点或所述第一感测输入防漏电节点
在一些实施例中，所述预设供电节点为所述第一感测输入防漏电节点；
所述移位寄存器单元还包括：第二控压电路和第二限流电路；
所述第二控压电路与第一电源端、所述第二上拉节点和第二控压节点连接，所述第二控压电路配置为响应于所述第二上拉节点处有效电平信号的控制将所述第一电源端所提供有效电平信号写入至所述第二控压节点；
所述第二限流电路与所述第二控压节点连接，所述第二限流电路配置为降低所述第二控压节点处的充放电电流。
在一些实施例中，所述第二限流电路包括：
第十一负载电路，位于所述第一感测输入防漏电节点与所述第二控压节点之间，配置为增大所述第一感测输入防漏电节点与所述第二控压节点之间的负载电阻。
在一些实施例中，所述第十一负载电路包括：第九十一晶体管；
所述第九十一晶体管的控制极与所述第二控压节点连接，所述第九 十一晶体管的第一极与所述第二控压节点，所述第九十一晶体管的第二极与所述第一感测输入防漏电节点连接。
在一些实施例中，所述预设供电节点为所述感测中间节点；
所述移位寄存器单元还包括：第二控压电路、第二感测输入防漏电电路和第二限流电路；
所述第二控压电路与第一电源端、所述第二上拉节点和第二控压节点连接，所述第二控压电路配置为响应于所述第二上拉节点处有效电平信号的控制将所述第一电源端所提供有效电平信号写入至所述第二控压节点；
所述第二感测输入电路通过所述第二感测输入防漏电电路与所述第二上拉节点连接，所述第二感测输入电路与所述第二感测输入防漏电电路连接于第二感测输入防漏电节点，所述第二感测输入防漏电节点与所述第二控压节点连接，所述第二感测输入防漏电电路与所述时钟控制信号输入端连接，所述第二感测输入防漏电电路配置为响应于所述时钟控制信号输入端处有效电平信号的控制使得所述第二感测输入防漏电节点与所述第二上拉节点之间形成通路，以及响应于所述时钟控制信号输入端处非有效电平信号的控制使得所述第二感测输入防漏电节点与所述第二上拉节点之间形成断路；
所述第二限流电路与所述第二控压节点连接，所述第二限流电路配置为降低所述第二控压节点处的充放电电流。
在一些实施例中，所述第二限流电路包括：
第十一负载电路，位于所述第二感测输入防漏电节点与所述第二控压节点之间，配置为增大所述第二感测输入防漏电节点与所述第二控压节点之间的负载电阻。
在一些实施例中，所述第十一负载电路包括：第九十一晶体管；
所述第九十一晶体管的控制极与所述第二控压节点连接，所述第九 十一晶体管的第一极与所述第二感测输入防漏电节点连接，所述第九十一晶体管的第二极与所述第二控压节点连接。
在一些实施例中，所述第二限流电路包括：
第十二负载电路，与所述第二控压节点和第二电源端连接，配置为增大所述第二控压节点处的负载电容。
在一些实施例中，所述第十二负载电路包括：第十二电容；
所述第十二电容的第一端与所述第二控压节点连接，所述第十二电容的第二端与第二电源端连接。
在一些实施例中，还包括：
第二全局复位电路，与全局复位信号输入端、第二电源端、所述第二上拉节点连接，所述第二全局复位电路配置为响应于所述全局复位信号输入端所提供有效电平信号的控制将所述第二电源端所提供非有效电平信号写入至所述第二上拉节点；
所述第四防漏电电路，所述第二全局复位电路通过所述第四防漏电电路与第二电源端连接，所述第二全局复位电路与所述第四防漏电电路连接于第四防漏电节点，所述第四防漏电节点与所述第二控压节点连接，所述第四防漏电电路与全局复位信号输入端连接，所述第四防漏电电路配置为响应于所述全局复位信号输入端所提供有效电平信号的控制使得所述第二防漏电节点与所述第二电源端之间形成通路，以及响应于所述全局复位信号输入端所提供非有效电平信号的控制使得所述第四防漏电节点与所述第二电源端之间形成断路。
在一些实施例中，所述第二限流电路包括：
第十三负载电路，位于所述第四防漏电节点与所述第二控压节点之间，配置为增大所述第四防漏电节点与所述第二控压节点之间的负载电阻。
在一些实施例中，所述第十三负载电路包括：第九十二晶体管；
所述第九十二晶体管的控制极与所述第二控压节点连接，所述第九十二晶体管的第一极与所述第四防漏电节点连接，所述第九十二晶体管的第二极与所述第二控压节点连接。
在一些实施例中，还包括：
第十五负载电路，所述第二全局复位电路和所述第四防漏电电路中至少之一通过所述第十五负载电路与全局复位信号输入端连接，所述第十五负载电路配置增大所述第一全局复位电路和所述第一防漏电电路中至少之一与所述全局复位信号输入端之间的负载电阻。
在一些实施例中，所述第十五负载电路包括：第九十四晶体管；
所述第九十四晶体管的控制极与所述全局复位信号输入端连接，所述第九十四晶体管的第一极与所述全局复位信号输入端连接，所述第九十四晶体管的第二极与所述第二全局复位电路和所述第四防漏电电路中至少之一连接。
在一些实施例中，还包括：
第二下拉控制电路，与第二电源端、第五电源端、所述第二上拉节点和第二下拉节点连接，配置为向所述第二下拉节点处写入与所述第二上拉节点处电压反相的电压；
第二上拉降噪电路，与所述第二电源端、所述第二上拉节点和第二下拉节点连接，配置为响应于所述第二下拉节点处有效电平信号的控制将所述第二电源端所提供非有效电平信号写入至所述第二上拉节点；
所述第二输出电路还与所述第二下拉节点和第二电源端连接，所述第二输出电路还配置为响应于所述第二下拉节点处有效电平信号的控制，将所述第二电源端提供的非有效电平信号写入至对应的所述第二信号输出端；
在一些实施例中，还包括：
第六防漏电电路，所述第二上拉降噪电路通过所述第六防漏电电路 与第二电源端连接，所述第二上拉降噪电路与所述第六防漏电电路连接于第六防漏电节点，所述第六防漏电节点与所述第二控压节点连接，所述第六防漏电电路与第二下拉节点连接，所述第六防漏电电路配置为响应于所述第二下拉节点处有效电平信号的控制使得所述第六防漏电节点与所述第二电源端之间形成通路，以及响应于所述第二下拉节点处非有效电平信号的控制使得所述第六防漏电节点与所述第二电源端之间形成断路。
在一些实施例中，所述第二控压节点位于所述第二感测输入防漏电节点与所述第六防漏电节点之间；
所述第二限流电路包括：
第十四负载电路，位于所述第二控压节点与所述第六防漏电节点之间，配置为配置为增大所述第二控压节点与所述第六防漏电节点之间的负载电阻。
在一些实施例中，所述第十四负载电路包括：
所述第九十三晶体管的控制极与所述第二控压节点连接，所述第九十三晶体管的第一极与所述第二控压节点连接，所述第九十三晶体管的第二极与所述第六防漏电节点连接。
在一些实施例中，还包括：
第三下拉降噪电路，与第二下拉节点、第二电源端、感测控制节点和时钟控制信号输入端连接，配置为响应于感测控制节点处有效电平信号和时钟控制信号输入端所提供有效电平信号的控制，将第二电源端提供的非有效电平信号写入至第二下拉节点。
在一些实施例中，所述第三下拉降噪电路包括：第五十九晶体管和第六十晶体管；
第五十九晶体管的控制极与时钟控制信号输入端连接，第五十九晶体管的第一极与第二下拉节点连接，第五十九晶体管的第二极与第六十 晶体管的第一极连接。
第六十晶体管的控制极与感测控制节点连接，第六十晶体管的第二极与第二电源端连接。
在一些实施例中，所述第三下拉降噪电路还包括：第九十五晶体管，所述第五十九晶体管的第一极通过所述第九十五晶体管与所述第二下拉节点连接；
所述第九十五晶体管的控制极与所述感测控制节点连接，所述第九十五晶体管的第一极与所述第二下拉节点连接，所述第九十五晶体管的第二极与所述第五十九晶体管的第一极连接。
在一些实施例中，还包括：
第二显示输入电路，与显示信号输入端、第一电源端和第二上拉节点连接，配置为响应于所述显示信号输入端所提供有效电平信号的控制将所述第一电源端所提供有效电平信号写入至所述第二上拉节点；
第二显示复位电路，与显示复位信号输入端、第二电源端、所述第二上拉节点连接，配置为响应于所述显示复位信号输入端所提供有效电平信号的控制，将所述第二电源端所提供非有效电平信号写入至所述第二上拉节点。
在一些实施例中，还包括：第二显示输入防漏电电路和第五防漏电电路中至少之一；
所述第二显示输入电路通过所述第二显示输入防漏电电路与所述第二上拉节点连接，所述第二显示输入电路与所述第二显示输入防漏电电路连接于第二显示输入防漏电节点，所述第二显示输入防漏电节点与所述第二控压节点连接，所述第二显示输入防漏电电路与所述显示信号输入端连接，所述第二显示输入防漏电电路配置为响应于所述显示信号输入端所提供有效电平信号的控制使得所述第二显示输入防漏电节点与所述第二上拉节点之间形成通路，以及响应于所述显示信号输入端所提供 非有效电平信号的控制使得所述第二显示输入防漏电节点与所述第二上拉节点之间形成断路；
所述第二显示复位电路通过所述第五防漏电电路与第二电源端连接，所述第二显示复位电路与所述第五防漏电电路连接于第五防漏电节点，所述第五防漏电节点与所述第二控压节点连接，所述第五防漏电电路与显示复位信号输入端连接，所述第五防漏电电路配置为响应于所述显示复位信号输入端所提供有效电平信号的控制使得所述第五防漏电节点与所述第二电源端之间形成通路，以及响应于所述显示复位信号输入端所提供非有效电平信号的控制使得所述第五防漏电节点与所述第二电源端之间形成断路。
第二方面，本公开实施例还提供了一种栅极驱动电路，其中，包括：级联的多个移位寄存器单元，所述移位寄存器单元采用上述第一方面中提供的所述移位寄存器单元。
第三方面，本公开实施例还提供了一种显示基板，其中，包括：衬底基板和位于衬底基板上的栅极驱动电路，所述栅极驱动电路采用第二方面中提供的栅极驱动电路。
附图说明
图1为有机发光二极管显示面板内的像素电路的电路结构示意图；
图2为图1所示像素电路的一种工作时序图；
图3为相关技术所涉及的移位寄存器单元的一种电路结构示意图；
图4为相关技术所涉及的移位寄存器单元的另一种电路结构示意图；
图5A和图5B为本公开实施例所提供的移位寄存器单元的两种电路结构示意图；
图6A和图6B为本公开实施例所提供的移位寄存器单元的另两种电 路结构示意图；
图7A和图7B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图；
图8为图7A和图7B所示移位寄存器单元的一种工作时序图；
图9A和图9B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图；
图10A和图10B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图；
图11为图10A和图10B所示移位寄存器单元的一种工作时序图；
图12A～图12D为本公开实施例所提供的移位寄存器单元的再四种电路结构示意图；
图12E为图12A所示移位寄存器单元中未设置有第八十一晶体管时的第一控压节点和第二电源端处电流变化的仿真图；
图12F为图12A所示移位寄存器单元中设置有第八十一晶体管时的第一控压节点和第二电源端处电流变化的仿真图；
图12G为本公开实施例所提供的移位寄存器单元的再一种电路结构示意图；
图13A和图13B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图；
图14A和图14B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图；
图15A和图15B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图；
图16A～图16D为本公开实施例所提供的移位寄存器单元的再四种电路结构示意图；
图16E为本公开实施例所提供的移位寄存器单元的再一种电路结构 示意图；
图17为本公开实施例提供的移位寄存器单元的再一种电路结构示意图；
图18为本公开实施例中在电源管理芯片上用作第二电源端的输出端与栅极驱动电路之间设置电感后第二电源端处电流变化的仿真图；
图19为本公开实施例提供的栅极驱动电路的一种电路结构示意图；
图20为图19所示栅极驱动电路的一种工作时序图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的一种移位寄存器单元、栅极驱动电路和栅极驱动方法进行详细描述。
本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的耦接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，仅仅是为了区分晶体管除控制极(即栅极)之外的两极，而将其中一极称为漏极，另一极称为源极。本公开实施例中采用的薄膜晶体管可以为N型晶体管，也可以为P型晶体管。在本公开实施例中，当采用N型薄膜晶体管时，其第一极可以是源极，第二极可以是漏极。
在本公开中“有效电平信号”是指输入至晶体管的控制极后能够控制晶体管导通的信号，“非有效电平信号”是指输入至晶体管的控制极后能够控制晶体管截止的信号。对于N型晶体管而言，高电平信号为有效电平信号，低电平信号为非有效电平信号；对于P型晶体管而言，低电平信号为有效电平信号，高电平信号为非有效电平信号。
在下面描述中，将以晶体管为N型晶体管为例进行描述，此时有效电平信号是指高电平信号，非有效电平信号是指低电平信号。可以想到，当采用P型晶体管时，需要相应调整控制信号的时序变化。具体细节不在此赘述，但也应该在本公开的保护范围内。
图1为有机发光二极管显示面板内的像素电路的电路结构示意图。图2为图1所示像素电路的一种工作时序图。如图1和图2所示，对于具有外部补偿功能的有机发光二极管显示面板而言，一帧画面可划分为两个阶段：显示驱动阶段和感测阶段；在显示驱动阶段中，显示面板中的各行像素单元完成显示驱动；在感测阶段，显示面板中的某一行像素单元完成电流抽取(即感测)。
参见图1所示，像素电路包括显示开关晶体管QTFT(控制极连第一栅线G1)、驱动晶体管DTFT、感测开关晶体管STFT(控制极连第二栅线G2)和一个Cst。在需要对该像素电路进行外部补偿时，该像素电路在工作过程中至少包括如下两个阶段：像素驱动阶段(包括数据电压写入过程)和像素感测阶段(包括电流读取过程)。
在像素驱动阶段，需要将数据线Data中的数据电压Vdata写入至像素单元；在像素感测阶段，需要通过数据线Data将一个测试电压Vsence写入至像素单元，并通过感测开关晶体管STFT将驱动晶体管的漏极处的电信号读取至信号读取线Sence。其中，在电流读取过程中，需要通过对应的第二栅线G2向感测开关晶体管STFT的栅极写入有效电平电压。需要说明的是，对OLED显示面板中的像素单元进行外部补偿，具体补偿 过程和原理，此处不再赘述。
针对用于控制感测开关晶体管STFT的第二栅线G2，在显示面板的周边区配置有对应的栅极驱动电路，栅极驱动电路包括多个级联的移位寄存器单元，通过移位寄存器单元可向对应的第二栅线G2提供驱动信号。
图3为相关技术所涉及的移位寄存器单元的一种电路结构示意图。如图3所示，该移位寄存器单元包括：第一感测控制输入电路100和至少一个第一输出电路200；其中，第一感测控制输入电路100与感测信号输入端INPUT2、随机信号输入端OE、时钟控制信号输入端CLKA和第一上拉节点PU1相连，第一感测控制输入电路100能够向第一上拉节点PU1写入有效电平信号；第一输出电路200与第一上拉节点PU1、对应的第一时钟信号输入端CLK和对应的第一信号输出端OUT相连，第一输出电路200配置为响应于第一上拉节点PU1处有效电平信号的控制将第一时钟信号输入端CLK所提供信号写入至对应的第一信号输出端OUT。
在实际应用中发现，在第一感测控制输入电路100完成向第一上拉节点PU1写入有效电平信号之后，第一上拉节点PU1会有较长一段时间处于浮接状态，此时第一上拉节点PU1容易通过第一感测控制输入电路100产生漏电，使得第一上拉节点PU1处电压发生漂移；当第一上拉节点PU1处的电压漂移程度较大(例如，漂移至低电平状态)时，会导致第一输出电路200无法进行有效输出；即，移位寄存器单元工作异常。
图4为相关技术所涉及的移位寄存器单元的另一种电路结构示意图。如图4所示，为了有效改善第一上拉节点PU1通过第一感测控制输入电路100漏电的问题，相关技术中在移位寄存器单元内增设了第一控压电路14和第一感测输入防漏电电路2’。
其中，第一控压电路14与第一电源端、第一上拉节点PU1和第一控压节点OFF1连接，第一控压电路14配置为响应于第一上拉节点PU1处 有效电平信号的控制将第一电源端所提供有效电平信号写入至第一控压节点OFF1。
第一感测控制输入电路100通过第一感测输入防漏电电路2’与第一上拉节点PU1连接，第一感测控制输入电路100与第一感测输入防漏电电路2’连接于第一感测输入防漏电节点SQ1，第一感测输入防漏电节点SQ1与第一控压节点OFF1连接，第一感测输入防漏电电路2’与时钟控制信号输入端CLKA连接，第一感测输入防漏电电路2’配置为响应于时钟控制信号输入端CLKA所提供信号的控制来控制第一感测输入防漏电节点SQ1与第一上拉节点PU1之间的通断。
具体地，在第一上拉节点PU1处于有效电平状态时，第一控压电路14响应第一上拉节点PU1处有效电平信号的控制将第一电源端所提供有效电平信号写入至第一控压节点OFF1和第一感测输入防漏电节点SQ1。由于第一感测输入防漏电节点SQ1和第一上拉节点PU1均处于有效电平状态，故第一上拉节点PU1无法通过第一感测控制输入电路100进行漏电,从而解决了第一上拉节点PU1通过第一感测控制输入电路100进行漏电的问题。
然而，在实际应用中发现，由于第一感测输入防漏电电路2’受控于时钟控制信号输入端CLKA，且第一感测输入防漏电电路2’内晶体管的栅极与源漏极之间存在寄生电容，故当时钟控制信号输入端CLKA所提供信号的电平发生切换时，例如由高电平切换至低电平或者由低电平切换至高电平，会使得第一感测输入防漏电节点SQ1和第一控压节点OFF1处存在瞬时大电流(电流峰值会超过75uA)，同时第一控压节点OFF1处的电压也会发生漂移。第一控压节点OFF1处的瞬时大电流会对与第一控压节点OFF1相连的电学器件(例如第一控压电路14内的晶体管或者是移位寄存器单元内后期所增设且与第一控压节点OFF1相连的晶体管)产生不利影响，进而影响到移位寄存器的工作良率。
为有效改善因时钟控制信号输入端CLKA所提供信号的电平发生切换时而导致第一控压节点OFF1处产生瞬时大电流的问题，本公开实施例提供了相应解决方案。
图5A和图5B为本公开实施例所提供的移位寄存器单元的两种电路结构示意图。如图5A和图5B所示，该移位寄存器单元包括：第一感测控制输入电路100、至少一个第一输出电路、第一控压电路14、第一感测输入防漏电电路2’和第一限流电路300。
其中，第一感测控制输入电路100与感测控制节点、感测信号输入端INPUT2、随机信号输入端OE、时钟控制信号输入端和第一上拉节点PU1连接，第一感测控制输入电路100配置为响应于随机信号输入端OE所提供有效电平信号的控制，将感测信号输入端INPUT2所提供信号写入至感测控制节点，以及响应于感测控制节点处有效电平信号和时钟控制信号所提供有效电平信号的控制，将有效电平信号写入至第一上拉节点PU1。
第一输出电路与第一上拉节点PU1、对应的第一时钟信号输入端和对应的第一信号输出端连接，第一输出电路配置为响应于第一上拉节点PU1处有效电平信号的控制将对应的第一时钟信号输入端所提供信号写入至对应的第一信号输出端。
在本公开中，上述至少一个第一输出电路至少包括第一驱动输出电路5；第一驱动输出电路5与第一上拉节点PU1、第一驱动时钟信号输入端CLKE(第一驱动输出电路所对应的第一时钟信号输入端)和第一驱动信号输出端OUT2(第一驱动输出电路所对应的第一信号输出端)连接，第一驱动输出电路5配置为响应于第一上拉节点PU1处有效电平信号的控制将第一驱动时钟信号输入端CLKE所提供信号写入至第一驱动信号输出端OUT2。
第一控压电路14与第一电源端、第一上拉节点PU1和第一控压节点 OFF1连接，第一控压电路14配置为响应于第一上拉节点PU1处有效电平信号的控制将第一电源端所提供有效电平信号写入至第一控压节点OFF1。
第一感测控制输入电路100通过第一感测输入防漏电电路2’与第一上拉节点PU1连接，第一感测控制输入电路100与第一感测输入防漏电电路2’连接于第一感测输入防漏电节点SQ1，第一感测输入防漏电节点SQ1与第一控压节点OFF1连接，第一感测输入防漏电电路2’与时钟控制信号输入端CLKA连接，第一感测输入防漏电电路2’配置为响应于时钟控制信号输入端CLKA处有效电平信号的控制使得第一感测输入防漏电节点SQ1与第一上拉节点PU1之间形成通路，以及响应于时钟控制信号输入端CLKA处非有效电平信号的控制使得第一感测输入防漏电节点SQ1与第一上拉节点PU1之间形成断路。
第一限流电路300与第一控压节点OFF1连接，第一限流电路300配置为降低第一控压节点OFF1处的充放电电流。
在本公开实施例中，在第一控压节点OFF1处设置有第一限流电路300，当时钟控制信号输入端CLKA所提供信号的电平发生切换时而导致第一控压节点OFF1处产生瞬时电流时，基于该第一限流电路300可以有效降低第一控压节点OFF1处的充放电电流，使得第一控压节点OFF1处产生瞬时电流的电流峰值降低，可有效解决因瞬时电流过大而导致的各种问题。
需要说明的是，本公开实施例中的第一限流电路300既可以采用图5A中所示情况设置在第一感测输入防漏电节点SQ1与第一控压节点OFF1之间，也可以采用图5B中所示情况未设置在第一感测输入防漏电节点SQ1与第一控压节点OFF1之间。当然，本公开实施例中的第一限流电路300也可以是部分设置在第一感测输入防漏电节点SQ1与第一控压节点OFF1之间，另一部分未设置在第一感测输入防漏电节点SQ1与第一控压 节点OFF1之间，即同时包含图5A和图5B中所示情况(未给出相应附图)。
图6A和图6B为本公开实施例所提供的移位寄存器单元的另两种电路结构示意图。参见图6A所示，在一些实施例中，第一限流电路300包括：第一负载电路301；第一负载电路301位于第一感测输入防漏电节点SQ1与第一控压节点OFF1之间，第一负载电路301配置为增大第一感测输入防漏电节点SQ1与第一控压节点OFF1之间的负载电阻。
在本公开实施例中，通过在第一感测输入防漏电节点SQ1与第一控压节点OFF1之间设置第一负载电路301，以使得第一感测输入防漏电节点SQ1与第一控压节点OFF1之间的负载电阻增大。通过增大第一感测输入防漏电节点SQ1与第一控压节点OFF1之间的负载电阻的方式，可使得在时钟控制信号输入端CLKA所提供信号的电平发生切换时第一控压节点OFF1处产生的瞬时电流减小。
第一负载电路301包括：第八十一晶体管M81；第八十一晶体管M81的控制极与第一控压节点OFF1连接，第八十一晶体管M81的第一极与第一感测输入防漏电节点SQ1连接，第八十一晶体管M81的第二极与第一控压节点OFF1连接。此时，第八十一晶体管M81可等同于一个二极管，其既不影响第一控压电路14将有效电平信号写入至第一感测输入防漏电节点SQ1，同时也还能作为负载电阻起到限流作用。
参见图6B所示，在一些实施例中，第一限流电路300包括：第二负载电路302，第二负载电路302与第一控压节点OFF1和第二电源端连接，第二负载电路302配置为增大第一控压节点OFF1处的负载电容。
在本公开实施例中，通过在第一控压节点OFF1处设置第二负载电路302，以使得第一控压节点OFF1处的负载电容增大。通过增大第一控压节点OFF1处的负载电容的方式，可使得在时钟控制信号输入端CLKA所提供信号的电平发生切换时第一控压节点OFF1处产生的瞬时电流减小；与此同时，由于负载电容具有一定的稳压作用，可有效降低第一控压节 点OFF1处的电压偏移。
在一些实施例中，第二负载电路302包括：第十一电容C11；第十一电容C11的第一端与第一控压节点OFF1连接，第十一电容C11的第二端与第二电源端连接。
图7A和图7B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图。如图7A和图7B所示，图7A和图7B为基于图6A和图6B所示移位寄存器的一种具体化可选实施方案。在一些实施例中，移位寄存器还包括：第一全局复位电路6。
第一全局复位电路6与全局复位信号输入端T-RST、第二电源端(第二电源端提供低电平电压VGL1)、第一上拉节点PU1连接，第一全局复位电路6配置为响应于全局复位信号输入端T-RST所提供有效电平信号的控制将第二电源端所提供非有效电平信号写入至第一上拉节点PU1。
在一些实施例中，第一感测控制输入电路100包括：感测控制电路1和第一感测输入电路2；感测控制电路1与感测控制节点H、感测信号输入端INPUT2和随机信号输入端OE连接，感测控制电路1配置为响应于随机信号输入端OE所提供有效电平信号的控制，将感测信号输入端INPUT2所提供信号写入至感测控制节点H；第一感测输入电路2与感测控制节点H、时钟控制信号输入端CLKA、感测中间节点Z和第一上拉节点PU1连接，第一感测输入电路2配置为响应于感测控制节点H处有效电平信号的控制，将有效电平信号写入至感测中间节点Z，以及响应于时钟控制信号输入端CLKA所提供有效电平信号的控制，使得感测中间节点Z与第一上拉节点PU1之间形成通路。
在一些实施例中，感测控制电路1包括第一晶体管M1；第一晶体管M1的控制极与随机信号输入端连接，第一晶体管M1的第一极与感测信号输入端INPUT2连接，第一晶体管M1的第二极与感测控制节点H连接。
在一些实施例中，感测控制电路1配置有第一电容C1，第一电容C1 的第一端与感测控制节点H连接，第一电容C1的第二端与第二电源端连接。
在一些实施例中，第一感测输入电路2包括第二晶体管M2和第三晶体管M3；第二晶体管M2的控制极与感测控制节点H连接，第二晶体管M2的第一极与时钟控制信号输入端CLKA连接，第二晶体管M2的第二极与感测中间节点Z连接。第三晶体管M3的控制极与时钟控制信号输入端CLKA连接，第三晶体管M3的第一极与感测中间节点Z连接，第三晶体管M3的第二极与第一感测输入防漏电电路连接。
在一些实施例中，第一全局复位电路6包括第七晶体管M7；第七晶体管M7的控制极与全局复位信号输入端T-RST连接，第七晶体管M7的第一极与第一上拉节点PU1连接，第七晶体管M7的第二极与第二电源端连接。
在一些实施例中，第一驱动输出电路5包括第五晶体管M5；第五晶体管M5的控制极与第一上拉后置节点PUB1连接，第五晶体管M5的第一极与第一驱动时钟信号输入端CLKE连接，第五晶体管M5的第二极与第一驱动信号输出端OUT2连接。
在一些实施例中，第一驱动输出电路5配置有第二电容C2，第二电容C2的第一端与第一上拉节点连接，第二电容C2的第二端与第一驱动信号输出端OUT2连接。
在一些实施例中，第一控压电路14包括第二十晶体管M20；第二十晶体管M20的控制极与第一上拉节点PU1连接，第二十晶体管M20的第一极与第一电源端(第一电源端提供高电平电压VDD1)连接，第二十晶体管M20的第二极与第一控压节点OFF1连接。
在一些实施例中，第一感测输入防漏电电路2'包括：第八晶体管M8；第八晶体管M8的控制极与时钟控制信号输入端CLKA连接，第八晶体管M8的第一极与第一感测输入防漏电节点SQ1连接，第八晶体管M8的第 二极与第一上拉节点PU1连接。
图7A示意出了第一限流电路300包括第一负载电路301，第一负载电路301包括第八十一晶体管M81的情况；图7B中示意出了第一限流电路300包括第二负载电路302，第二负载电路302包括第十一电容C11的情况。
图8为图7A和图7B所示移位寄存器单元的一种工作时序图。如图8所示，其中，该移位寄存器单元的工作过程包括如下几个阶段：
在p1阶段，感测信号输入端INPUT2提供高电平信号，随机信号输入端OE提供高电平信号，时钟控制信号输入端CLKA提供低电平信号，全局复位信号输入端T-RST提供低电平信号。
此时，第一晶体管M1导通，感测信号输入端INPUT2提供的高电平信号写入至感测控制节点H，感测控制节点H处电压处于高电平状态。相应地，第二晶体管M2导通，时钟控制信号输入端CLKA提供的低电平信号通过第二晶体管M2写入至感测中间节点Z，感测中间节点Z处电压处于低电平状态。
由于时钟控制信号输入端CLKA提供低电平信号，故第三晶体管M3和第八晶体管M8均截止；全局复位信号输入端T-RST提供低电平信号，故第七晶体管M7截止。
需要说明的是，p1阶段位于一帧中的显示驱动阶段，第一上拉节点PU1和第一驱动信号输出端OUT2在显示驱动阶段所加载电压情况，可参见后面实施例中的描述，本实施仅对移位寄存器单元在感测阶段具体工作情况作详细描述。
在p2阶段，感测信号输入端INPUT2提供低电平信号，随机信号输入端OE提供低电平信号，时钟控制信号输入端CLKA提供高电平信号，全局复位信号输入端T-RST提供低电平信号。
由于感测控制节点H处电压维持前一阶段的高电平状态，故第二晶 体管M2维持导通，时钟控制信号输入端CLKA提供高电平信号通过第二晶体管M2写入至感测中间节点Z；与此同时，由于时钟控制信号输入端CLKA所提供高电平信号使得第三晶体管M3和第八晶体管M8导通，故感测中间节点Z处的高电平信号可以写入至第一上拉节点PU1。
由于第一上拉节点PU1处于高电平状态，故第五晶体管M5和第二十晶体管M20导通。由于第五晶体管M5导通，故第一驱动时钟信号输入端CLKE提供的低电平信号通过第五晶体管M5写入至第一驱动信号输出端OUT2，第一驱动信号输出端OUT2输出低电平信号。
需要说明的是，p1阶段与p2阶段之间存在一个时间间隔，为保证感测控制节点H处电压在该时间间隔内保持稳定，故在感测控制节点H处可以增设上述第一电容C1。
另外，在p2阶段的起始阶段时钟控制信号输入端CLKA所提供的信号由低电平切换至高电平过程中，以及在p2阶段的结束阶段时钟控制信号输入端CLKA所提供的信号由高电平切换至低电平过程中，虽然第三晶体管M3和第八晶体管M8内栅极与源漏电极之间的寄生电容会使得第一控压节点处有瞬时电流产生，但是由于第一限流电路(例如图7A中的第八十一晶体管和图7B中的第十一电容)的存在，第一限流电路可使得第一控压节点处的瞬时电流不会过大。
在p3阶段，感测信号输入端INPUT2提供低电平信号，随机信号输入端OE提供低电平信号，时钟控制信号输入端CLKA提供低电平信号，全局复位信号输入端T-RST提供低电平信号。
由于时钟控制信号输入端CLKA提供低电平信号，故第三晶体管M3和第八晶体管M8截止，又由于第二晶体管M2维持导通，故时钟控制信号输入端CLKA提供的低电平信号通过第二晶体管M2写入至感测中间节点Z，感测中间节点Z处于低电平状态。此时第一上拉节点PU1维持前一阶段的高电平状态，第五晶体管M5和第二十晶体管M20维持导通。
在该阶段中，第一驱动时钟信号输入端CLKE先提供高电平信号后提供低电平信号，第一驱动时钟信号输入端CLKE所提供的信号通过第五晶体管M5写入至第一驱动信号输出端OUT2，第一驱动信号输出端OUT2先输出高电平信号，后输出低电平信号。需要说明的是，在第一驱动信号输出端OUT2由输出低电平信号切换至输出高电平信号的过程中，在第二电容C2的自举作用下，第一上拉节点PU1处电压被上拉至更高水平；在第一驱动信号输出端OUT2由输出高电平信号切换至输出低电平信号的过程中，在第二电容C2的自举作用下，第一上拉节点PU1处电压被下拉至初始高电平状态。
在p4阶段，感测信号输入端INPUT2提供低电平信号，随机信号输入端OE提供高电平信号，时钟控制信号输入端CLKA提供低电平信号，全局复位信号输入端T-RST提供高电平信号。
由于随机信号输入端OE提供高电平信号，故第一晶体管M1导通，感测信号输入端INPUT2提供的低电平信号通过第一晶体管M1写入至感测控制节点H，感测控制节点H处电压处于低电平状态，第二晶体管M2截止。又因为时钟控制信号输入端CLKA提供低电平信号，故第三晶体管M3和第八晶体管M8均截止，此时，感测中间节点Z处于浮接状态，维持低电平。
与此同时，由于全局复位信号输入端T-RST提供高电平信号，第七晶体管M7导通，第二电源端提供的低电平电压VGL1通过第七晶体管M7写入至第一上拉节点PU1，第一上拉节点PU1处于低电平状态，第五晶体管M5和第二十晶体管均截止，第一驱动信号输出端OUT2维持前一阶段的低电平状态，即维持输出低电平信号。
图9A和图9B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图。如图9A和图9B所示，在一些实施例中，移位寄存器单元还包括：第一显示输入电路7和第一显示复位电路8。
其中，第一显示输入电路7与显示信号输入端INPUT1和第一上拉节点PU1连接，第一显示输入电路7配置为响应于显示信号输入端INPUT1所提供有效电平信号的控制将显示信号输入端INPUT1所提供有效电平信号写入至第一上拉节点PU1。
第一显示复位电路8与显示复位信号输入端RST、第二电源端、第一上拉节点PU1连接，配置为响应于显示复位信号输入端RST所提供有效电平信号的控制，将第二电源端所提供的非有效电平信号写入至第一上拉节点PU1。
在一些实施例中，移位寄存器单元还包括：第一下拉控制电路11；其中，第一下拉控制电路11与第二电源端、第五电源端、第一上拉节点PU1和第一下拉节点PD1连接，配置为向第一下拉节点PD1处写入与第一上拉节点PU1处电压反相的电压。
在一些实施例中，移位寄存器单元还包括：第一上拉降噪电路12；其中，第一上拉降噪电路12与第二电源端、第一上拉节点PU1和第一下拉节点PD1连接，配置为响应于第一下拉节点PD1处有效电平信号的控制将第二电源端所提供非有效电平信号写入至第一上拉节点PU1，以对第一上拉节点PU1进行降噪。
此时，第一驱动输出电路5还与第一下拉节点PD1和第四电源端连接，第一驱动输出电路5还配置为响应于第一下拉节点PD1处有效电平信号的控制将第四电源端提供的非有效电平信号写入至第一驱动信号输出端OUT2。
在一些实施例中，移位寄存器单元内的至少一个第一输出电路不但包括第一驱动输出电路5，还包括有第二驱动输出电路9和第一级联输出电路13。
其中，第二驱动输出电路9与第一上拉节点PU1、第一下拉节点PD1、第二驱动时钟信号输入端CLKD、第二驱动信号输出端OUT1和第四电源 端连接，第二驱动输出电路9配置为响应于第一上拉节点PU1处有效电平信号的控制将第二驱动时钟信号输入端CLKD所提供信号写入至第二驱动信号输出端OUT1，以及响应于第一下拉节点PD1处有效电平信号的控制将第四电源端提供的非有效电平信号写入至第二驱动信号输出端OUT1；
第一级联输出电路13与第一上拉节点PU1、第一下拉节点PD1、第一级联时钟信号输入端CLKC、第一级联信号输出端CR和第四电源端连接，第一级联输出电路13配置为响应于第一上拉节点PU1处有效电平信号的控制将第一级联时钟信号输入端CLKC所提供信号写入至第一级联信号输出端CR，以及响应于第一下拉节点PD1处有效电平信号的控制将第二电源端提供的非有效电平信号写入至第一级联信号输出端CR。
图9A和图9B所示移位寄存器单元不但具备感测驱动功能，即向图1中第二栅线G2提供驱动信号，同时还具备显示驱动功能，即向图1中第一栅线G1提供驱动信号)。也就是说，针对显示面板内的第一栅线G1和第二栅线G2可以使用同一栅极驱动电路进行驱动，可有效降低显示面板所配置栅极驱动电路的数量，有利于产品的窄边框设计。
图10A和图10B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图。如图10A和图10B所示，图10A和图10B所示移位寄存器单元为图9A和图9B所示移位寄存器单元的一种具体化可选实施方案。以图10A和图10B内的感测控制电路1、第一感测输入电路2、第一全局复位电路6、第一控压电路14、第一感测输入防漏电电路2'可采用图7A和图7B中所示的情况为例。
在一些实施例中，第一显示输入电路7包括第九晶体管M9，第一显示复位电路8包括第十晶体管M10，第一下拉控制电路11包括第十二晶体管M12和第十三晶体管M13，第一上拉降噪电路12包括第十四晶体管M14，第一驱动输出电路5包括第五晶体管M5和第十七晶体管M17，第 二驱动输出电路9包括第十五晶体管M15和第十八晶体管M18，第一级联输出电路13包括第十六晶体管M16和第十九晶体管M19。
其中，第九晶体管M9的控制极与显示信号输入端INPUT1连接，第九晶体管M9的第一极与显示信号输入端INPUT1连接，第九晶体管M9的第二极与第一上拉节点PU1连接。
第十晶体管M10的控制极与显示复位信号输入端RST连接，第十晶体管M10的第一极与第一上拉节点PU1连接，第十晶体管M10的第二极与第二电源端连接。
第十二晶体管M12的控制极与第五电源端连接，第十二晶体管M12的第一极与第五电源端连接，第十二晶体管M12的第二极与第一下拉节点PD1连接。
第十三晶体管M13的控制极与第一上拉节点PU1连接，第十三晶体管M13的第一极与第一下拉节点PD1连接，第十三晶体管M13的第二极与第二电源端连接。
第十四晶体管M14的控制极与第一下拉节点PD1连接，第十四晶体管M14的第一极与第一上拉节点PU1连接，第十四晶体管M14的第二极与第二电源端连接。
第五晶体管M5的控制极与第一上拉节点PU1连接，第五晶体管M5的第一极与第一驱动时钟信号输入端CLKE连接，第五晶体管M5的第二极与第一驱动信号输出端OUT2连接。
第十七晶体管M17的控制极与第一下拉节点PD1连接，第十七晶体管M17的第一极与第一驱动信号输出端OUT2连接，第十七晶体管M17的第二极与第四电源端连接。
第十五晶体管M15的控制极与第一上拉节点PU1连接，第十五晶体管M15的第一极与第二驱动时钟信号输入端CLKD连接，第十五晶体管M15的第二极与第二驱动信号输出端OUT1连接。
第十八晶体管M18的控制极与第一下拉节点PD1连接，第十八晶体管M18的第一极与第二驱动信号输出端OUT1连接，第十八晶体管M18的第二极与第四电源端连接。
第十六晶体管M16的控制极与第一上拉节点PU1连接，第十六晶体管M16的第一极与级联驱动时钟信号输入端连接，第十六晶体管M16的第二极与第一级联信号输出端CR连接。
第十九晶体管M19的控制极与第一下拉节点PD1连接，第十九晶体管M19的第一极与第一级联信号输出端CR连接，第十九晶体管M19的第二极与第四电源端连接。
在一些实施例中，第一驱动输出电路5和第二驱动输出电路6分别配置有第二电容C2和第三电容C3。
在一些实施例中，第一电源端提供高电平电压VDD1，第二电源端提供低电平电压VGL1，第四电源端提供低电平电压VGL2，第五电源端提供高电平电压VDDA。
图11为图10A和图10B所示移位寄存器单元的一种工作时序图。如图11所示，该移位寄存器单元的工作过程包括：显示驱动过程和感测驱动过程。
其中，显示驱动过程包括：显示输入阶段t1、显示输出阶段t2和显示复位阶段t3；感测驱动过程包括：感测准备阶段p1、感测输入阶段p2、感测输出阶段p3和全局复位阶段p4。
在显示输入阶段t1，显示信号输入端INPUT1提供高电平信号，第九晶体管M9导通，第一电源端提供的高电平电压VDD1通过第九晶体管M9写入至第一上拉节点PU1，第一上拉节点PU1处于高电平状态，相应地，第五晶体管M5、第十五晶体管M15、第十六晶体管M16均导通。
在第一上拉节点PU1处于高电平状态时，第十三晶体管M13导通，第二电源端通过的低电平电压VGL1通过第十三晶体管M13写入至第一下 拉节点PD1，第一下拉节点PD1处于低电平状态，第十七晶体管M17、第十八晶体管M18和第十九晶体管M19均处于截止状态。
此时，第一驱动时钟信号输入端CLKE通过第五晶体管M5向第一驱动信号输出端OUT2写入低电平信号；第二驱动时钟信号输入端CLKD通过第十五晶体管M15向第二驱动信号输出端OUT1写入低电平信号；第一级联时钟信号输入端CLKC通过第十六晶体管M16向第一级联信号输出端CR写入低电平信号。即，第一驱动信号输出端OUT2、第二驱动信号输出端OUT1和第一级联信号输出端CR均输出低电平信号。
在显示输出阶段t2，显示信号输入端INPUT1提供低电平信号，第九晶体管M9截止，第一上拉节点PU1处于浮接状态并维持前一阶段的高电平；第五晶体管M5、第十五晶体管M15、第十六晶体管M16均维持导通。
其中，在显示输出阶段t2的初始时刻，第一驱动时钟信号输入端CLKE提供的信号由低电平信号变为高电平信号，在第二电容C2的自举作用下，第一上拉节点PU1处电压被上拉至更高水平，第一驱动信号输出端OUT2输出高电平信号。在显示输出阶段t2开始且经过一段时间后，第一驱动时钟信号输入端CLKE提供的信号由高电平信号变为低电平信号，在第二电容C2的自举作用下，第一上拉节点PU1处电压被下拉至初始的高电平电压，第五晶体管M5维持导通，第一驱动信号输出端OUT2输出低电平信号。
同理，在整个显示输出阶段t2中，第二驱动信号输出端OUT1和第一级联信号输出端CR也均是先输出高电平信号，再输出低电平信号。
在显示复位阶段t3，显示复位信号输入端RST提供高电平信号，第十晶体管M10导通，第二电源端提供的低电平信号通过第十晶体管M10写入至第一上拉节点PU1，第一上拉节点PU1处于低电平状态，第五晶体管M5、第十五晶体管M15、第十六晶体管M16均截止。
此时，第十三晶体管M13也截止，第五电源端通过的高电平电压VDDA通过第十二晶体管M12写入至第一下拉节点PD1，第一下拉节点PD1处于高电平状态，第十七晶体管M17、第十八晶体管M18和第十九晶体管M19均处于导通状态。
此时，第四电源端通过第十七晶体管M17向第一驱动信号输出端OUT2写入低电平信号；第四电源端通过第十八晶体管M18向第二驱动信号输出端OUT1写入低电平信号；第二电源端通过第十九晶体管M19向第一级联信号输出端CR写入低电平信号。即，第一驱动信号输出端OUT2、第二驱动信号输出端OUT1和第一级联信号输出端CR均输出低电平信号。
另外，由于第一下拉节点PD1处于高电平状态，故第十四晶体管M14也导通，第二电源端提供的低电平电压VGL1通过第十四晶体管M14写入至第一上拉节点PU1，以对第一上拉节点PU1进行降噪处理。
在感测准备阶段p1，感测信号输入端INPUT2和随机信号输入端OE均提供高电平信号，此时第一晶体管M1导通；感测信号输入端INPUT2提供的高电平信号会通过第一晶体管M1写入至感测控制节点H，以对感测控制节点H进行充电，感测控制节点H处的电压处于高电平状态。相应地，第二晶体管M2导通；但是，由于时钟控制信号输入端CLKA提供低电平信号，因此第三晶体管M3和第八晶体管M8均截止，故时钟控制信号输入端CLKA与第一上拉节点PU1之间断路。
在感测输入阶段p2，时钟控制信号输入端CLKA提供高电平信号，故第三晶体管M3和第八晶体管M8均导通。此时，又因为感测控制节点H处电压处于高电平状态会使得第二晶体管M2维持导通，故时钟控制信号输入端CLKA提供的高电平信号可通过第二晶体管M2、第三晶体管M3和第八晶体管M8写入至第一上拉节点PU1，即第一上拉节点PU1处电压处于高电平状态。
相应地，第二十晶体管M20、第五晶体管M5、第十五晶体管M15、 第十六晶体管M16均导通。
在第一上拉节点PU1处于高电平状态时，第十三晶体管M13导通，第二电源端通过的低电平电压VGL1通过第十三晶体管M13写入至第一下拉节点PD1，第一下拉节点PD1处于低电平状态，第十七晶体管M17、第十八晶体管M18和第十九晶体管M19均处于截止状态。
此时，第一驱动时钟信号输入端CLKE通过第五晶体管M5向第一驱动信号输出端OUT2写入低电平信号；第二驱动时钟信号输入端CLKD通过第十五晶体管M15向第二驱动信号输出端OUT1写入低电平信号；第一级联时钟信号输入端CLKC通过第十六晶体管M16向第一级联信号输出端CR写入低电平信号。即，第一驱动信号输出端OUT2、第二驱动信号输出端OUT1和第一级联信号输出端CR均输出低电平信号。
在感测输出阶段p3，时钟控制信号输入端CLKA提供低电平信号，故第三晶体管M3截止，时钟控制信号输入端CLKA与第一上拉节点PU1之间再次形成断路。第一上拉节点PU1处于浮接状态并维持前一阶段的高电平；第五晶体管M5、第十五晶体管M15、第十六晶体管M16均维持导通。
其中，在感测输出阶段p3的初始时刻，第一驱动时钟信号输入端CLKE提供的信号由低电平信号变为高电平信号，在第二电容C2的自举作用下，第一上拉节点PU1处电压被上拉至更高水平，第一驱动信号输出端OUT2输出高电平信号。在显示输出阶段t2开始且经过一段时间后，第一驱动时钟信号输入端CLKE提供的信号由高电平信号变为低电平信号，在第二电容的自举作用下，第一上拉节点PU1处电压被下拉至初始的高电平电压，第五晶体管M5维持导通，第一驱动信号输出端OUT2输出低电平信号。
同理，由于第一驱动时钟信号输入端CLKE在整个感测输出阶段p3过程中也是先提供高电平信号后提供低电平信号，故在整个感测输出阶 段p3中，第二驱动信号输出端OUT1先输出高电平信号，再输出低电平信号。而第一级联信号输出端CR在整个感测输出阶段p3过程中提供低电平信号，故在整个感测输出阶段p3中，第一级联信号输出端CR始终输出低电平信号。
在全局复位阶段p4，全局复位信号输入端T-RST提供高电平信号，第七晶体管M7导通，第二电源端提供的低电平电压VGL1通过第七晶体管M7写入至第一上拉节点PU1，以对第一上拉节点PU1进行复位。
其中，在第一上拉节点PU1处于低电平状态时，第五电源端提供的高电平电压VDDA通过第十二晶体管M12写入至第一下拉节点PD1，第一下拉节点PD1处于高电平状态，第十七晶体管M17、第十八晶体管M18和第十九晶体管M19均处于导通状态。
在本公开实施例中，感测信号输入端INPUT2和随机信号输入端OE同时提供有效电平信号的时段为感测准备阶段p1；图11中所示感测准备阶段p1与显示输入阶段t1重叠的情况仅为本公开中的一种可选实施方案，此时感测信号输入端INPUT2与显示信号输入端INPUT1可以为同一信号输入端，该情况仅为本公开中的一种可选实施方案，其不会对本公开的技术方案产生限制。在本公开实施例中，感测准备阶段p1也可以位于显示输入阶段t1之前，还可以位于显示输入阶段t2之后，仅需保证感测准备阶段p1位于感测输入阶段p2之前即可。
图12A～图12D为本公开实施例所提供的移位寄存器单元的再四种电路结构示意图。如图12A至图12D所示，在一些实施例中，移位寄存器单元不但包括有第一全局复位电路6还包括第一防漏电电路15。
其中，第一全局复位电路6通过第一防漏电电路15与第二电源端连接，第一全局复位电路6与第一防漏电电路15连接于第一防漏电节点Q1，第一防漏电节点Q1与第一控压节点OFF1连接，第一防漏电电路15与全局复位信号输入端T-RST连接，第一防漏电电路15配置为响应于全 局复位信号输入端T-RST所提供有效电平信号的控制使得第一防漏电节点Q1与第二电源端之间形成通路，以及响应于全局复位信号输入端T-RST所提供非有效电平信号的控制使得第一防漏电节点Q1与第二电源端之间断路。
与时钟控制信号输入端CLKA处类似，在全局复位信号输入端T-RST所提供信号的电平发生切换时，例如由高电平切换至低电平，或者由低电平切换至高电平，会使得第一防漏电节点Q1与第一控压节点OFF1之间存在瞬时大电流。
参见图12A和图12B所示，为有效改善因此全局复位信号输入端T-RST所提供信号发生切换而导致第一控压节点OFF1处产生瞬时大电流的问题，在一些实施例中，第一限流电路300包括：第三负载电路303，第三负载电路303位于第一防漏电节点Q1与第一控压节点OFF1之间，配置为增大第一防漏电节点Q1与第一控压节点OFF1之间的负载电阻。
在一些实施例中，第三负载电路303包括：第八十二晶体管M82；第八十二晶体管M82的控制极与第一控压节点OFF1连接，第八十二晶体管M82的第一极与第一防漏电节点Q1连接，第八十二晶体管M82的第二极与第一控压节点OFF1连接。此时，第八十二晶体管M82可等同于一个二极管，其既不影响第一控压电路14将有效电平信号写入至第一防漏电节点Q1，同时也还能作为负载电阻起到限流作用。
在一些实施例中，移位寄存器单元不但包括有第一上拉降噪电路12还包括第三防漏电电路17。其中，第一上拉降噪电路12通过第三防漏电电路17与第二电源端连接，第一上拉降噪电路12与第三防漏电电路17连接于第三防漏电节点Q3，第三防漏电节点Q3与第一控压节点OFF1连接，第三防漏电电路17与第一下拉节点PD1连接，第三防漏电电路17配置为响应于第一下拉节点PD1处有效电平信号的控制使得第三防漏电节点Q3与第二电源端之间形成通路，以及响应于第一下拉节点PD1 处非有效电平信号的控制使得第三防漏电节点Q3与第二电源端之间断路。
通过研究发现，在设置有第三防漏电电路17时，第一控压节点会与第三防漏电节点Q3连接。在第一控压节点OFF1处产生有瞬时电流时，若第三防漏电节点Q3与第二电源端之间为通路，则第一控压节点OFF1处产生瞬时电流会通过第三防漏电节点Q3、第三防漏电电路17流向第二电源端；若第三防漏电节点Q3与第二电源端之间为断路，则第一控压节点OFF1处产生的瞬时电流会导致第三防漏电电路17处产生流向第二电源端的漏电流。也就是说，在移位寄存器单元内设置有上述第三防漏电电路17时，一旦第一控压节点OFF1处产生瞬时电流，则在第三防漏电电路17与第二电源端之间也会产生瞬时电流。
由于时钟控制信号输入端CLKA和全局复位信号输入端T-RST均为全局信号信号输入端，也就是说栅极驱动电路内所有移位寄存器单元连接同一时钟控制信号输入端CLKA和同一全局复位信号输入端T-RST，在时钟控制信号输入端CLKA或全局复位信号输入端T-RST所提供信号的电平发生切换时，栅极驱动电路内所有移位寄存器单元内的第一控压节点OFF1处会同时产生相同方向的瞬时电流，相应地，所有移位寄存器单元内第三防漏电电路17与第二电源端之间也会同时产生相同方向的瞬时电流，这些瞬时电流最终会叠加到第二电源端或者是与第二电源端相连的某一条信号传输走线上，从而导致第二电源端或者是与第二电源端相连的某一条信号传输走线上存在极大的瞬时电流。例如，每个移位寄存器单元与第二电源端之间的瞬时电流的电流峰值约为I，栅极驱动电路内存在M级移位寄存器单元，此时第二电源端处的瞬时电流的电流峰值约为M*I，极其容易导致与第二电源端相连的电学器件的损坏(例如，与第二电源端相连的信号传输走线因加载电流过大被烧断)。
图12E为图12A所示移位寄存器单元中未设置有第八十一晶体管时 的第一控压节点和第二电源端处电流变化的仿真图。如图12E所示，在图12A中所示移位寄存器单元中用于增大负载电阻的第八十一晶体管被去除后，当时钟控制信号输入端CLKA所提供的信号的电平发生切换时，第一控压节点OFF1处所产生的瞬时电流的电流峰值约为78uA，第二电源端处的瞬时电流的电流峰值约为0.42A。
图12F为图12A所示移位寄存器单元中设置有第八十一晶体管时的第一控压节点和第二电源端处电流变化的仿真图。如图12F所示，在设置有第八十一晶体管后，当时钟控制信号输入端CLKA所提供的信号的电平发生切换时，第一控压节点OFF1处所产生的瞬时电流的电流峰值约为38uA，第二电源端处的瞬时电流的电流峰值约为0.28A。通过图12E和图12F可见，在增设第八十一晶体管后，第一控压节点OFF1处的瞬时电流的电流峰值可有效降低，第二电源端处的瞬时电流的电流峰值也可以有效降低。
在本公开实施例中，可通过降低移位寄存器单元内第一控压节点OFF1与第三防漏电节点Q3之间的瞬时电流，从而使得第三防漏电电路17与第二电源端之间的瞬时电流降低，进而使得第二电源端处的瞬时电流降低。例如，采用图12A和图12B中所示，通过设置第八十一晶体管M81、第八十二晶体管M82、第十一电容C11中至少之一，可有效降低第一控压节点OFF1与第三防漏电节点之间的瞬时电流。图12A和图12B所示方案均能够改善因时钟控制信号输入端CLKA或全局复位信号输入端T-RST所提供信号的电平发生切换而导致第二电源端处的瞬时电流过大的问题。
与图12A和图12B中所不同的是，图12C和图12D所示情况中第一限流电路包括：第四负载电路304，第四负载电路304位于第一控压节点OFF1与第三防漏电节点Q3之间，配置为配置为增大第一控压节点OFF1与第三防漏电节点Q3之间的负载电阻。
在一些实施例中，第四负载电路304包括：第八十三晶体管M83的控制极与第一控压节点OFF1连接，第八十三晶体管M83的第一极与第一控压节点OFF1连接，第八十三晶体管M83的第二极与第三防漏电节点Q3连接。此时，第八十三晶体管M83可等同于一个二极管，其既不影响第一控压电路将有效电平信号写入至第三防漏电节点，同时也还能作为负载电阻起到限流作用。
需要说明的是，在本公开实施例中，第一限流电路300可以选择性地包括第一负载电路301(第八十一晶体管M81)、第二负载电路302(第十一电容C11)、第三负载电路303(第八十二晶体管M82)、第四负载电路304(第八十三晶体管M83)中的至少之一，均可以有效改善因时钟控制信号输入端CLKA或全局复位信号输入端T-RST所提供信号的电平发生切换而导致第二电源端处的瞬时电流过大的问题。
图12G为本公开实施例所提供的移位寄存器单元的再一种电路结构示意图。如图12G所示，与前面实施例中不同的是，图12G所示移位寄存器单元包括有第五负载电路305；第一全局复位电路6和第一防漏电电路15中至少之一通过第五负载电路305与全局复位信号输入端T-RST连接，第五负载电路305配置增大第一全局复位电路6和第一防漏电电路15中至少之一与全局复位信号输入端T-RST之间的负载电阻。
以第一全局复位电路6和第一防漏电电路15均通过第五负载电路305与全局复位信号输入端T-RST连接的情况为例；通过设置第五负载电路305以增大第一全局复位电路6和第一防漏电电路15与全局复位信号输入端T-RST之间的负载电阻，可使得全局复位信号输入端T-RST所提供信号的电平发生切换时全局复位信号输入端T-RST与第一全局复位电路6和第一防漏电电路15之间的瞬时电流较小，从而使得第一防漏电节点Q1与第一控压节点OFF1之间的瞬时电流较小。
在一些实施例中，第五负载电路305包括：第八十四晶体管M84； 第八十四晶体管M84的控制极与全局复位信号输入端T-RST连接，第八十四晶体管M84的第一极与全局复位信号输入端T-RST连接，第八十四晶体管M84的第二极与第一全局复位电路6和第一防漏电电路15中至少之一连接。
需要说明的是，在前面实施例所示的移位寄存器单元(例如，图12B～图12D所示移位寄存器单元)中也可以根据需要,选择性的设置图12G中所示第五负载电路305，该情况也应属于本公开的保护范围。
继续参见图12A至图12D以及图12G所示，在一些实施例中，移位寄存器单元还包括：第一显示输入防漏电电路7’和第二防漏电电路16中至少之一。
其中，第一显示输入电路7通过第一显示输入防漏电电路7’与第一上拉节点连接，第一显示输入电路7与第一显示输入防漏电电路7’连接于第一显示输入防漏电节点XQ1，第一显示输入防漏电节点XQ1与第一控压节点OFF1连接，第一显示输入防漏电电路7’与显示信号输入端INPUT1连接，第一显示输入防漏电电路7’配置为响应于显示信号输入端INPUT1所提供有效电平信号的控制使得第一显示输入防漏电节点XQ1与第一上拉节点PU1之间形成通路，以及响应于显示信号输入端INPUT1所提供非有效电平信号的控制使得第一显示输入防漏电节点XQ1与第一上拉节PU1点之间形成断路。
第一显示复位电路8通过第一防漏电电路16与第二电源端连接，第一显示复位电路8与第一防漏电电路16连接于第二防漏电节点Q2，第二防漏电节点Q2与第一控压节点OFF1连接，第一防漏电电路16与显示复位信号输入端RST连接，第一防漏电电路16配置为响应于显示复位信号输入端RST所提供有效电平信号的控制使得第二防漏电节点Q2与第二电源端之间形成通路，以及响应于显示复位信号输入端RST所提供非有效电平信号的控制使得第二防漏电节点Q2与第二电源端之间断路。
在一些实施例中，移位寄存器单元还包括：感测控制防漏电电路3；感测控制电路1通过感测控制防漏电电路3与感测控制节点H连接，感测控制防漏电电路3与感测控制电路1连接于感测控制防漏电节点，感测控制防漏电电路3还与第一电源端、感测控制节点H和随机信号输入端OE连接，感测控制防漏电电路3配置为响应于感测控制节点H处有效电平信号的控制，将第一电源端提供的有效电平信号写入至感测控制防漏电节点，以及配置为响应于随机信号输入端OE所提供有效电平信号的控制使得感测控制防漏电节点与感测控制节点H之间形成通路，以及响应于随机信号输入端OE所提供非有效电平信号的控制使得感测控制防漏电节点与感测控制节点H之间形成断路。
对于图12A～图12D、图12G中感测控制电路1、第一感测输入电路2、第一全局复位电路6、第一显示输入电路7、第一显示复位电路8、第一驱动信号输出电路5、第二驱动信号输出电路9、第一级联信号输出电路13、第一下拉控制电路11、第一上拉降噪电路12的具体电路结构，可以参见前面对图10A和图10B中所示，此处不再赘述。
在一些实施例中，第一防漏电电路15包括第二十一晶体管M21，第二防漏电电路16包括第二十二晶体管M22，第三防漏电电路17包括第二十三晶体管M23，感测控制防漏电电路3包括第七十一晶体管M71和第七十二晶体管M72，第一显示输入防漏电电路7’包括第七十三晶体管M73。
其中，第二十一晶体管M21的控制极与全局复位信号输入端T-RST连接，第二十一晶体管M21的第一极与全局复位电路和第一控压节点OFF1连接，第二十二晶体管M22的第二极与第二电源端连接。
第二十二晶体管M22的控制极与显示复位信号输入端RST连接，第二十二晶体管M22的第一极与显示复位电路和第一控压节点OFF1连接，第二十二晶体管M22的第二极与第二电源端连接。
第二十三晶体管M23的控制极与第一下拉节点PD1连接，第二十三晶体管M23的第一极与第一下拉控电路和第一控压节点OFF1连接，第二十三晶体管M23的第二极与第二电源端连接。
第七十一晶体管M71的控制极与感测控制节点H连接，第七十一晶体管M71的第一极与感测控制防漏电节点连接，第七十一晶体管M71的第二极与第一电源端连接。
第七十二晶体管M72的控制极与随机信号输入端OE连接，第七十二晶体管M72的第一极与感测控制防漏电节点连接，第七十二晶体管M72的第二极与感测控制节点H连接。
第七十三晶体管M73的控制极与显示信号输入端INPUT1连接，第七十三晶体管M73的第一极与第一显示输入防漏电节点XQ1连接，第七十三晶体管M72的第二极与第一上拉节点PU1连接。
继续参见图12A～12E所示，在一些实施例中，移位寄存器单元还包括：还包括：第一下拉降噪电路18；第一下拉降噪电路18与第一下拉节点PD1、第二电源端、感测控制节点H和时钟控制信号输入端CLKA连接，第一下拉降噪电路18配置为响应于感测控制节点H处有效电平信号和时钟控制信号输入端CLKA所提供有效电平信号的控制，将第二电源端提供的非有效电平信号写入至第一下拉节点PD1，以对第一下拉节点PD1处电压进行降噪处理。
在一些实施例中，第一下拉降噪电路18包括：第二十九晶体管M29和第三十晶体管M30；第二十九晶体管M29的控制极与时钟控制信号输入端CLKA连接，第二十九晶体管M29的第一极与第一下拉节点PD1连接，第二十九晶体管M29的第二极与第三十晶体管M30的第一极连接；第三十晶体管M30的控制极与感测控制节点H连接，第三十晶体管M30的第二极与第二电源端连接。
在实际应用中发现，在时钟控制信号输入端所CLKA提供信号的电平 发生切换时，由于第二十九晶体管M29的栅极与源漏极之间耦合电容的影响，会导致第一下拉节点PD1处的电压产生漂移，存在移位寄存器单元工作异常的风险。
为避免时钟控制信号输入端CLKA所提供信号的电平发生切换时对第一下拉节点PD1处的电压产生影响；在一些实施例中，优选地，第一下拉降噪电路18还包括：第八十五晶体管M85；其中，第二十九晶体管M29的第一极通过第八十五晶体管M85与第一下拉节点PD1连接；第八十五晶体管M85的控制极与感测控制节点H连接，第八十五晶体管M85的第一极与第一下拉节点PD1连接，第八十五晶体管M85的第二极与第二十九晶体管M29的第一极连接。
在一些实施例中，移位寄存器单元还包括第二下拉降噪电路19，第二下拉降噪电路19与第一下拉节点PD1、第二电源端和下拉降噪信号输入端INPUT3连接，第二下拉降噪电路19配置为响应于下拉降噪信号输入端INPUT3所提供有效电平信号的控制，将第二电源端提供的非有效电平信号写入至第一下拉节点PD1，以对第一下拉节点PD1处电压进行降噪处理。
在一些实施例中，第二下拉降噪电路19包括：第三十一晶体管M31；第三十一晶体管M31的控制极与下拉降噪信号输入端INPUT3连接，第三十一晶体管M31的第一极与第一下拉节点PD1连接，第三十一晶体管M31的第二极与第二电源端连接。
在一些实施例中，下拉降噪信号输入端INPUT3可以为感测信号输入端INPUT2。
图13A和图13B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图。如图13A和图13B所示，在一些实施例中移位寄存器单元不但包括感测控制电路1、第一感测输入电路2和至少一个第一输出电路(例如第一驱动输出电路)，还包括第二感测输入电路23和至少 一个第二输出电路(例如第三驱动输出电路)。此时，基于至少一个第一输出电路和至少一个第二输出电路，该移位寄存器单元可以为显示基板中位于不同行的像素单元提供驱动信号。
其中，第二感测输入电路23与时钟控制信号输入端CLKA、第二上拉节点PU2和预设供电节点连接，第二感测输入电路23配置为响应于时钟控制信号输入端CLKA所提供有效电平信号的控制，使得预设供电节点与第二上拉节点PU2之间形成通路；
至少一个第二输出电路，第二输出电路与第二上拉节点PU2、对应的第二时钟信号输入端和对应的第二信号输出端连接，配置为响应于第二上拉节点PU2处有效电平信号的控制将对应的第二时钟信号输入端所提供信号写入至对应的第二信号输出端。
在本公开中，上述至少一个第二输出电路至少包括第三驱动输出电路25；第三驱动输出电路25与第二上拉节点PU2、第三驱动时钟信号输入端CLKE’(第三驱动输出电路25所对应的第二时钟信号输入端)和第三驱动信号输出端OUT2’(第三驱动输出电路25所对应的第二信号输出端)连接，第三驱动输出电路25配置为响应于第二上拉节点PU2处有效电平信号的控制将第三驱动时钟信号输入端CLKE’所提供信号写入至第三驱动信号输出端OUT2’。
继续参见图13A和图13B所示，在一些实施例中，预设供电节点可以为第一感测输入防漏电节点，此时第一感测输入电路2和第二感测输入电路23可以实现对控压节点的共用。
在一些实施例中，第二感测输入电路23包括：第三十三晶体管M33，第三十三晶体管M33的控制极与时钟控制信号输入端CLKA连接，第三十三晶体管M33的第一极与预设供电节点(图13A和图13B中为第一感测输入防漏电节点SQ1)连接，第三十三晶体管M33的第二极与第二上拉节点PU2连接。
在图13A所示情况中，第一感测输入电路2和第二感测输入电路23可以实现对第一控压节点的共用。此时，第一感测输入电路2和第二感测输入电路23也可以共用同一第一限流电路，以改善时钟控制信号输入端CLKA(与第一感测输入电路和第二感测输入电路23均连接)所提供信号的电平发生切换时而导致第一控压节点处产生瞬时大电流的问题。
在图13A所示情况中，仅示例性画出了第一限流电路包括第一负载电路301，第一负载电路301包括第八十一晶体管M81的情况，该情况仅起到示例性作用。
另外，相较于图13A所示方案，在图13B所示方案中，移位寄存器单元还包括：第二控压电路34和第二限流电路400；第二控压电路34与第一电源端、第二上拉节点PU2和第二控压节点OFF2连接，第二控压电路34配置为响应于第二上拉节点PU2处有效电平信号的控制将第一电源端所提供有效电平信号写入至第二控压节点OFF2；第二限流电路400与第二控压节点OFF2连接，第二限流电路400配置为降低第二控压节点OFF2处的充放电电流。
在一些实施例中，第二控压电路34包括：第五十晶体管M50；第五十晶体管M50的控制极与第二上拉节点PU2连接，第五十晶体管M50的第一极与第一电源端连接，第五十晶体管M50的第二极与第二控压节点OFF2连接。
在图13B所示情况中，第一感测输入电路2和第二感测输入电路23可以实现对第一控压节点OFF1和第二控压节点OFF2的共用。第一感测输入电路2和第二感测输入电路23也可以实现对第一限流电路300和第二限流电路400的共用；其中，通过第一限流电路300可以改善时钟控制信号输入端所提供信号的电平发生切换时而导致第一控压节点OFF1处产生瞬时大电流的问题，通过第二限流电路400可以改善时钟控制信号输入端所提供信号的电平发生切换时而导致第二控压节点OFF2处产 生瞬时大电流的问题。
在一些实施例中，第二限流电路400包括：第十一负载电路401，位于第一感测输入防漏电节点SQ1与第二控压节点OFF2之间，配置为增大第一感测输入防漏电节点SQ1与第二控压节点OFF2之间的负载电阻。
在一些实施例中，第十一负载电路401包括：第九十一晶体管M91；第九十一晶体管M91的控制极与第二控压节点OFF2连接，第九十一晶体管M91的第一极与第二控压节点OFF2，第九十一晶体管M91的第二极与第一感测输入防漏电节点SQ1连接。
图14A和图14B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图。如图14A和图14B所示，与图13A和图13B所不同的是，在图14A和图14B中的预设供电节点为感测中间节点Z。此时，移位寄存器单元还包括：第二控压电路34、第二感测输入防漏电电路23’和第二限流电路400。
第二控压电路34与第一电源端、第二上拉节点PU2和第二控压节点OFF2连接，第二控压电路34配置为响应于第二上拉节点PU2处有效电平信号的控制将第一电源端所提供有效电平信号写入至第二控压节点OFF2。
第二感测输入电路23通过第二感测输入防漏电电路23’与第二上拉节点PU2连接，第二感测输入电路23与第二感测输入防漏电电路23’连接于第二感测输入防漏电节点SQ2，第二感测输入防漏电节点SQ2与第二控压节点OFF2连接，第二感测输入防漏电电路23’与时钟控制信号输入端CLKA连接，第二感测输入防漏电电路23’配置为响应于时钟控制信号输入端CLKA处有效电平信号的控制使得第二感测输入防漏电节点SQ2与第二上拉节点PU2之间形成通路，以及响应于时钟控制信号输入端CLKA处非有效电平信号的控制使得第二感测输入防漏电节点SQ2与第二上拉节点PU2之间形成断路。
第二限流电路400与第二控压节点OFF2连接，第二限流电路400配置为降低第二控压节点OFF2处的充放电电流。
需要说明的是，在本公开实施例中，第二限流电路400既可以采用图14A中所示情况设置在第二感测输入防漏电节点SQ2与第二控压节点OFF2之间，也可以采用图14B中所示情况未设置在第二感测输入防漏电节点SQ2与第二控压节点OFF2之间。当然，本公开实施例中的第二限流电路400也可以是部分设置在第二感测输入防漏电节点SQ2与第二控压节点OFF2之间，另一部分未设置在第二感测输入防漏电节点SQ2与第二控压节点OFF2之间，即同时包含图14A和图14B中所示情况(未给出相应附图)。
在一些实施例中，第二感测输入防漏电电路23’包括：第三十八晶体管M38；第三十八晶体管M38的控制极与时钟控制信号输入端CLKA连接，第三十八晶体管M38的第一极与第二感测输入电路23连接，第三十八晶体管M38的第二极与第二上拉节点PU2连接；
参见图14A所示，在一些实施例中，第二限流电路400包括：第十一负载电路401，第十一负载电路401位于第二感测输入防漏电节点SQ2与第二控压节点OFF2之间，配置为增大第二感测输入防漏电节点SQ2与第二控压节点OFF2之间的负载电阻。
在一些实施例中，第十一负载电路401包括：第九十一晶体管M91；第九十一晶体管M91的控制极与第二控压节点OFF2连接，第九十一晶体管M91的第一极与第二感测输入防漏电节点SQ2连接，第九十一晶体管M91的第二极与第二控压节点OFF2连接。此时，第九十一晶体管M91可等同于一个二极管，其既不影响第二控压电路将有效电平信号写入至第二感测输入防漏电节点SQ2，同时也还能作为负载电阻起到限流作用。
参见图14B所示，在一些实施例中，第二限流电路400包括：第十二负载电路402，与第二控压节点OFF2和第二电源端连接，配置为增大 第二控压节点OFF2处的负载电容。通过增大第二控压节点OFF2处的负载电容的方式，可使得在时钟控制信号输入端CLKA所提供信号的电平发生切换时第二控压节点OFF2处产生的瞬时电流减小；同时由于负载电容具有一定的稳压作用，可有效降低第二控压节点OFF2处的电压偏移。
在一些实施例中，第十二负载电路402包括：第十二电容C12；第十二电容的C12第一端与第二控压节点OFF2连接，第十二电容C12的第二端与第二电源端连接。
图15A和图15B为本公开实施例所提供的移位寄存器单元的再两种电路结构示意图。如图15A和图15B所示，在一些实施例中，移位寄存器单元还包括有第二全局复位电路26、第二显示输入电路27、第二显示复位电路28。至少一个第二输出电路不但包括第三驱动输出电路25，还包括第四驱动输出电路29。
其中，第二全局复位电路26与全局复位信号输入端T-RST、第二电源端、第二上拉节点PU2连接，第二全局复位电路26配置为响应于全局复位信号输入端T-RST所提供有效电平信号的控制将第二电源端所提供的非有效电平信号写入至第二上拉节点PU2。
第二显示输入电路27与显示信号输入端INPUT1和第二上拉节点PU2连接，配置为响应于显示信号输入端INPUT1所提供有效电平信号的控制将有效电平信号写入至第二上拉节点PU2。
第二显示复位电路28与显示复位信号输入端RST、第二电源端、第二上拉节点PU2连接，配置为响应于显示复位信号输入端RST所提供有效电平信号的控制，将第二电源端所提供的非有效电平信号写入至第二上拉节点PU2。
第四驱动输出电路29与第二上拉节点PU2、第四驱动时钟信号输入端CLKD’、第四驱动信号输出端OUT1’连接，配置为响应于第二上拉节点PU2处有效电平信号的控制将第四驱动时钟信号输入端CLKD’所提供 信号写入至第四驱动信号输出端OUT1’。
第四驱动输出电路29可以为显示面板上处与第二驱动输出电路9相连的一条第一栅线G1外的另一条第一栅线G1提供驱动信号。
在本公开实施例中，在移位寄存器单元内同时包括第一驱动输出电路5、第二驱动输出电路9、第三驱动输出电路25、第四驱动输出电路29时，第一驱动输出电路5和第二驱动输出电路9可分别用于向显示面板内某一行像素单元所配置的一条第一栅线和一条第二栅线提供相应驱动信号，与此同时，第三驱动输出电路25和第四驱动输出电路29可分别用于向显示面板内另一行像素单元所配置的一条第一栅线和一条第二栅线提供相应驱动信号。也就是说，本实施例所提供的移位寄存器单元可用于驱动两行像素单元(例如相邻两行像素单元)所配置的四条栅线。通过该设计，可有效减少栅极驱动电路内移位寄存器单元的级数，降低栅极驱动电路所占用尺寸，有利于产品的窄边框设计。
在一些实施例中，移位寄存器单元还包括：第二下拉控制电路31和第二上拉降噪电路32。
其中，第二下拉控制电路31与第二电源端、第六电源端、第二上拉节点PU2和第二下拉节点PD2连接，配置为向第二下拉节点PD2处写入与第二上拉节点PU2处电压反相的电压；
第二上拉降噪电路32与第二电源端、第二上拉节点PU2和第二下拉节点PD2连接，配置为响应于第二下拉节点PD2处有效电平信号的控制将第二电源端所提供非有效电平信号写入至第二上拉节点PU2。
此时，第三驱动输出电路25还与第二下拉节点PD2和第四电源端连接，第三驱动输出电路25还配置为响应于第二下拉节点PD2处有效电平信号的控制将第四电源端提供的非有效电平信号写入至第三驱动信号输出端OUT2’。
第四驱动输出电路29还与第二下拉节点PD2和第四电源端连接，第 四驱动输出电路29还配置为响应于第二下拉节点PD2处有效电平信号的控制将第四电源端提供的非有效电平信号写入至第四驱动信号输出端OUT1’。
需要说明的是，在一些实施例中，移位寄存器单元中还可以包括第二级联输出电路(未示出)。第二级联输出电路与第二上拉节点PU2、第二级联时钟信号输入端、第二级联信号输出端连接，第二级联输出电路配置为响应于第二上拉节点PU2处有效电平信号的控制将第二级联时钟信号输入端所提供信号写入至第二级联信号输出端。另外，第二级联输出电路还可与第二电源端和第二下拉节点PD2连接，第二级联输出电路配置为响应于第二下拉节点PD2处有效电平信号的控制，将第二电源端提供的非有效电平信号写入至第二级联信号输出端。
在一些实施例中，第二感测输入电路23包括：第三十三晶体管M33，第三十三晶体管M33的控制极与时钟控制信号输入端CLKA连接，第三十三晶体管M33的第一极与预设供电节点(图15A和图15B中为感测中间节点)连接，第三十三晶体管M33的第二极与第二感测输入防漏电节点SQ2连接。
第二感测输入防漏电电路23'包括：第三十八晶体管M38；第三十八晶体管M38的控制极与时钟控制信号输入端CLKA连接，第三十八晶体管M38的第一极与第二感测输入电路23连接，第三十八晶体管M38的第二极与第二上拉节点PU2连接；
第二显示输入电路27包括第三十九晶体管M39。第三十九晶体管M39的控制极与显示信号输入端INPUT1连接，第三十九晶体管M39的第一极与第一电源端连接，第三十九晶体管M39的第二极与第二上拉节点PU2连接。
第三驱动输出电路25包括第三十五晶体管M35和第四十七晶体管M47，第四驱动输出电路29包括第四十五晶体管M45和第四十八晶体管 M48；
其中，第三十五晶体管M35的控制极与第二上PU2连接，第三十五晶体管M35的第一极与第三驱动时钟信号输入端CLKE’连接，第三十五晶体管M35的第二极与第三驱动信号输出端OUT2’连接。
第四十七晶体管M47的控制极与第二下拉节点PD2连接，第四十七晶体管M47的第一极与第三驱动信号输出端OUT2’连接，第四十七晶体管M47的第二极与第四电源端连接。
第四十五晶体管M45的控制极与第二上拉节点PU2连接，第四十五晶体管M45的第一极与第四驱动时钟信号输入端CLKD’连接，第四十五晶体管M45的第二极与第四驱动信号输出端OUT1’连接。
第四十八晶体管M48的控制极与第二下拉节点PD2连接，第四十八晶体管M48的第一极与第四驱动信号输出端OUT1’连接，第四十八晶体管M48的第二极与第四电源端连接。
在一些实施例中，针对第三驱动信号输出端OUT2’配置有第四电容C4。
在一些实施例中，第二全局复位电路26包括第三十七晶体管M37，第二显示复位电路28包括第四十晶体管M40，第二下拉控制电路31包括第四十二晶体管M42和第四十三晶体管M43，第二上拉降噪电路32包括第四十四晶体管M44。
第三十七晶体管M37的控制极与全局复位信号输入端T-RST连接，第三十七晶体管M37的第一极与第二上拉节点PU2连接，第三十七晶体管M37的第二极与非有效电平供给端连接。
第四十晶体管M40的控制极与显示复位信号输入端RST连接，第四十晶体管M40的第一极与第二上拉节点PU2连接，第四十晶体管M40的第二极与非有效电平供给端连接。
第四十二晶体管M42的控制极与第六电源端连接，第四十二晶体管 M42的第一极与第六电源端(第六电源端提供电压VDDB)连接，第四十二晶体管M42的第二极与第二下拉节点PD2连接。
第四十三晶体管M43的控制极与第二上拉节点PU2连接，第四十三晶体管M43的第一极与第二下拉节点PD2连接，第四十三晶体管M43的第二极与非有效电平供给端连接。
第四十四晶体管M44的控制极与第二下拉节点PD2连接，第四十四晶体管M44的第一极与第二上拉节点PU2接，第四十四晶体管M44的第二极与非有效电平供给端连接。
在一些实施例中，第五电源端提供电压VDDA与第六电源端提供电VDDB，VDDA和VDDB可以在高电平电压和低电平电压之间进行切换(例如，每1帧或几帧就进行一次切换)，且在任意时刻VDDA和VDDB二者中之一为高电平电压，另一为低电平电压。
图16A～图16D为本公开实施例所提供的移位寄存器单元的再四种电路结构示意图。如图16A至图16D所示，在一些实施例中，移位寄存器单元不但包括有第二全局复位电路还包括第四防漏电电路35。
其中，第二全局复位电路26通过第四防漏电电路35与第二电源端连接，第二全局复位电路26与第四防漏电电路35连接于第四防漏电节点Q4，第四防漏电节点Q4与第二控压节点OFF2连接，第四防漏电电路35与感测复位信号输入端T-RST连接，第四防漏电电路35配置为响应于感测复位信号输入端T-RST所提供有效电平信号的控制使得第四防漏电节点Q4与第二电源端之间形成通路，以及响应于级联复位信号输入端所提供非有效电平信号的控制使得第四防漏电节点Q4与第二电源端之间断路。
与时钟控制信号输入端CLKA处类似，全局复位信号输入端T-RST所提供信号的电平发生切换时，例如由高电平切换至低电平，或者由低电平切换至高电平，会使得第二防漏电节点与第二控压节点处存在瞬时 大电流。
参见图16A和图16B所示，为有效改善因此全局复位信号输入端所提供信号发生切换而导致第二控压节点OFF2处产生瞬时大电流的问题，在一些实施例中，第二限流电路400包括：第十三负载电路403，第十三负载电路403位于第四防漏电节点Q4与第二控压节点OFF2之间，配置为增大第四防漏电节点Q4与第二控压节点OFF2之间的负载电阻。
在一些实施例中，第十三负载电路403包括：第九十二晶体管M92；第九十二晶体管M92的控制极与第二控压节点OFF2连接，第九十二晶体管M92的第一极与第四防漏电节点Q4连接，第九十二晶体管M92的第二极与第二控压节点OFF2连接。此时，第九十二晶体管M92可等同于一个二极管，其既不影响第二控压电路将有效电平信号写入至第四防漏电节点Q4，同时也还能作为负载电阻起到限流作用。
在一些实施例中，移位寄存器单元不但包括有第二上拉降噪电路32还包括第六防漏电电路37。其中，第二上拉降噪电路32通过第六防漏电电路37与第二电源端连接，第二上拉降噪电路32与第六防漏电电路37连接于第六防漏电节点Q6，第六防漏电节点Q6与第二控压节点OFF2连接，第六防漏电电路37与第二下拉节点PD2连接，第六防漏电电路37配置为响应于第二下拉节点PD2处有效电平信号的控制使得第六防漏电节点Q6与第二电源端之间形成通路，以及响应于第二下拉节点PD2处非有效电平信号的控制使得第六防漏电节点Q6与第二电源端之间断路。
同设置有第三防漏电电路17时的情况类似，在在移位寄存器单元内设置有上述第六防漏电电路37时，一旦第二控压节点OFF2处产生瞬时电流，则在第六防漏电电路37与第二电源端之间也会产生瞬时电流。由于时钟控制信号输入端CLKA和全局复位信号输入端T-RST均为全局信号信号输入端，也就是说栅极驱动电路内所有移位寄存器单元连接同一时 钟控制信号输入端CLKA和同一全局复位信号输入端T-RST，在时钟控制信号输入端CLKA或全局复位信号输入端T-RST所提供信号的电平发生切换时，栅极驱动电路内所有移位寄存器单元内的第二控压节点OFF2处会同时产生相同方向的瞬时电流，相应地，所有移位寄存器单元内第六防漏电电路37与第二电源端之间也会同时产生相同方向的瞬时电流，这些瞬时电流最终会叠加到第二电源端或者是与第二电源端相连的某一条信号传输走线上，从而导致第二电源端或者是与第二电源端相连的某一条信号传输走线上存在极大的瞬时电流。
在本公开实施例中，可通过降低移位寄存器单元内第二控压节点OFF2与第六防漏电节点之间的瞬时电流，从而使得第六防漏电电路37与第二电源端之间的瞬时电流降低。例如，采用图16A和图16B中所示，通过设置第九十一晶体管、第九十二晶体管M92、第十二电容C12中至少之一，可有效降低第二控压节点OFF2与第三防漏电节点Q3之间的瞬时电流。图16A和图16B所示方案均能够改善因时钟控制信号输入端CLKA或全局复位信号输入端T-RST所提供信号的电平发生切换而导致第二电源端处的瞬时电流过大的问题。
与图16A和图16B中所不同的是，图16C和图16D所示情况中第二限流电路400包括：第十四负载电路404，第十四负载电路404位于第二控压节点OFF2与第六防漏电节点Q6之间，第十四负载电路404配置为配置为增大第二控压节点OFF2与第六防漏电节点Q6之间的负载电阻。
在一些实施例中，第十四负载电路404包括：第九十三晶体管M93的控制极与第二控压节点OFF2连接，第九十三晶体管M93的第一极与第二控压节点OFF2连接，第九十三晶体管M93的第二极与第六防漏电节点Q6连接。此时，第九十三晶体管M93可等同于一个二极管，其既不影响第二控压电路34将有效电平信号写入至第六防漏电节点Q6，同时也还能作为负载电阻起到限流作用。
需要说明的是，在本公开实施例中，第二限流电路400可以选择性地包括第十一负载电路401(第九十一晶体管M91)、第十二负载电路402(第十二电容C12)、第十三负载电路403(第九十二晶体管M92)、第十四负载电路404(第九十三晶体管M93)中的至少之一，均可以有效改善因时钟控制信号输入端CLKA或全局复位信号输入端T-RST所提供信号的电平发生切换而导致第二电源端处的瞬时电流过大的问题。
图16E为本公开实施例所提供的移位寄存器单元的再一种电路结构示意图。如图16E所示，与前面实施例中不同的是，图16E所示移位寄存器单元包括有第五负载电路405；第二全局复位电路26和第四防漏电电路35中至少之一通过第十五负载电路405与全局复位信号输入端T-RST连接，第十五负载电路405配置增大第二全局复位电路26和第四防漏电电路35中至少之一与全局复位信号输入端T-RST之间的负载电阻。
以第二全局复位电路26和第四防漏电电路35均通过第十五负载电路405与全局复位信号输入端T-RST连接的情况为例；通过设置第十五负载电路405以增大第二全局复位电路26和第四防漏电电路35与全局复位信号输入端T-RST之间的负载电阻，可使得全局复位信号输入端T-RST所提供信号的电平发生切换时全局复位信号输入端T-RST与第二全局复位电路26和第四防漏电电路35之间的瞬时电流较小，从而使得第四防漏电节点Q4与第二控压节点之间的瞬时电流较小。
在一些实施例中，第十五负载电路405包括：第九十四晶体管M94；第九十四晶体管M94的控制极与全局复位信号输入端T-RST连接，第九十四晶体管M94的第一极与全局复位信号输入端T-RST连接，第九十四晶体管M94的第二极与第一全局复位电路和第四防漏电电路35中至少之一连接。
需要说明的是，在前面实施例所示的移位寄存器单元(例如，图 16B～图16D所示移位寄存器单元)中也可以根据需要选择性的设置图12G中的第十五负载电路405，这些情况也应属于本公开的保护范围。
继续参见图12A至图12D以及图12G所示，在一些实施例中，移位寄存器单元还包括：第二显示输入防漏电电路27’和第五防漏电电路中至少之一。
第二显示输入电路27通过第二显示输入防漏电电路27’与第二上拉节点连接，第二显示输入电路27与第二显示输入防漏电电路27’连接于第二显示输入防漏电节点XQ2，第二显示输入防漏电节点XQ2与第二控压节点连接，第二显示输入防漏电电路27’与显示信号输入端INPUT1连接，第二显示输入防漏电电路27’配置为响应于第二显示输入防漏电节点所提供有效电平信号的控制使得第二显示输入防漏电节点XQ2与第二上拉节点PU2之间形成通路，以及响应于第二显示输入防漏电节点所提供非有效电平信号的控制使得第二显示输入防漏电节点XQ2与第二上拉节点PU2之间形成断路。
第二显示复位电路28通过第五防漏电电路36与第二电源端连接，第二显示复位电路28与第五防漏电电路36连接于第五防漏电节点Q5，第五防漏电节点Q5与第二控压节点OFF2连接，第五防漏电电路36与显示复位信号输入端RST连接，第五防漏电电路36配置为响应于显示复位信号输入端RST所提供有效电平信号的控制使得第五防漏电节点Q5与第二电源端之间形成通路，以及响应于显示复位信号输入端RST所提供非有效电平信号的控制使得第五防漏电节点Q5与第二电源端之间形成断路。
在一些实施例中，在一些实施例中，第四防漏电电路35包括第五十一晶体管M51；第五十一晶体管M51的控制极与感测复位信号输入端T-RST连接，第五十一晶体管M51的第一极与感测复位电路和第二控压节点OFF2连接，第五十二晶体管M52的第二极与第二电源端连接。
在一些实施例中，第五防漏电电路36包括第五十二晶体管M52；第五十二晶体管M52的控制极与显示复位信号输入端RST连接，第五十二晶体管M52的第一极与显示复位电路和第二控压节点OFF2连接，第五十二晶体管M52的第二极与第二电源端连接。
在一些实施例中，第六防漏电电路37包括：第五十三晶体管M53；第五十三晶体管M53的控制极与第二下拉节点PD2连接，第五十三晶体管M53的第一极与第二下拉控电路和第二控压节点OFF2连接，第五十三晶体管M53的第二极与第二电源端连接。
在一些实施例中，第二显示输入防漏电电路27’包括：第七十四晶体管M74；第七十四晶体管M74的控制极与显示信号输入端INPUT1连接，第七十四晶体管M74的第一极与第二显示输入防漏电节点XQ2连接，第七十四晶体管M74的第二极与第二上拉节点PU2连接。
继续参见图16A～16E所示，在一些实施例中，移位寄存器单元还包括：还包括：第三下拉降噪电路38；第三下拉降噪电路38与第二下拉节点PD2、第二电源端、感测控制节点H和时钟控制信号输入端CLKA连接，第三下拉降噪电路38配置为响应于感测控制节点H处有效电平信号和时钟控制信号输入端CLKA所提供有效电平信号的控制，将第二电源端提供的非有效电平信号写入至第二下拉节点PD2，以对第一下拉节点PD2处电压进行降噪处理。
在一些实施例中，第三下拉降噪电路38包括：第五十九晶体管M59和第六十晶体管M60；第五十九晶体管M59的控制极与时钟控制信号输入端CLKA连接，第五十九晶体管M59的第一极与第二下拉节点PD2连接，第五十九晶体管M59的第二极与第六十晶体管M60的第一极连接；第六十晶体管M60的控制极与感测控制节点H连接，第六十晶体管M60的第二极与第二电源端连接。
在实际应用中发现，在时钟控制信号输入端CLKA所提供信号的电平 发生切换时，由于第五十九晶体管M59的栅极与源漏极之间耦合电容的影响，会导致第二下拉节点PD2处的电压产生漂移，存在移位寄存器单元工作异常的风险。
为避免时钟控制信号输入端CLKA所提供信号的电平发生切换时对第二下拉节点PD2处的电压产生影响；在一些实施例中，优选地，第三下拉降噪电路38还包括：第九十五晶体管M95；第五十九晶体管M59的第一极通过第九十五晶体管M95与第二下拉节点PD2连接；第九十五晶体管M95的控制极与感测控制节点H连接，第九十五晶体管M95的第一极与第二下拉节点PD2连接，第九十五晶体管M95的第二极与第五十九晶体管M59的第一极连接。
在一些实施例中，移位寄存器单元还包括第四下拉降噪电路39，第四下拉降噪电路39与第二下拉节点PD2、第二电源端和下拉降噪信号输入端INPUT3连接，第二下拉降噪电路19配置为响应于下拉降噪信号输入端INPUT3所提供有效电平信号的控制，将第二电源端提供的非有效电平信号写入至第二下拉节点PD2，以对第二下拉节点PD2处电压进行降噪处理。
在一些实施例中，第六十一晶体管M61的控制极与下拉降噪信号输入端INPUT3连接，第六十一晶体管M61的第一极与第二下拉节点PD2连接，第六十一晶体管M61的第二极与第二电源端连接。
图17为本公开实施例提供的移位寄存器单元的再一种电路结构示意图。如图17所示，在移位寄存器单元内同时配置有第一下拉节点PD1和第二下拉节点PD2时，在一些实施例中，第三防漏电电路17、第一上拉降噪电路12、第一级联输出电路13、第一驱动输出电路5、第二驱动输出电路9还与第二下拉节点PD2连接。
第三防漏电电路17还配置为响应于第二下拉节点PD2处有效电平信号的控制，将非有效电平信号写入至第三防漏点节点。可选地，第三防 漏电电路17包括第二十三晶体管M23和第二十八晶体管M28，其中第二十三晶体管M23的控制极与第一下拉节点PD1连接，第二十八晶体管M28的控制极与第二下拉节点PD2连接。
第一上拉降噪电路12还配置为响应于第二下拉节点PD2处有效电平信号的控制，将非有效电平信号写入至第一上拉节点PU1。可选地，第一上拉降噪电路12包括第十四晶体管M14和第二十七晶体管M27，其中第十四晶体管M14的控制极与第一下拉节点PD1连接，第二十七晶体管M27的控制极与第二下拉节点PD2连接。
第一级联输出电路13还配置为响应于第二下拉节点PD2处有效电平信号的控制，将非有效电平信号写入至第一级联信号输出端CR。可选地，级联输出电路13包括第十九晶体管M19和第二十四晶体管M24，其中第十九晶体管M19的控制极与第一下拉节点PD1连接，第二十四晶体管M24的控制极与第二下拉节点PD2连接。
第一驱动输出电路5还配置为响应于第二下拉节点PD2处有效电平信号的控制，将非有效电平信号写入至第一驱动信号输出端OUT2。可选地，第一驱动输出电路5内还包括有第十七晶体管M17和第二十六晶体管M26，其中第十七晶体管M17的控制极与第一下拉节点PD1连接，第二十六晶体管M26的控制极与第二下拉节点PD2连接。
第二驱动输出电路9还配置为响应于第二下拉节点PD2处有效电平信号的控制，将非有效电平信号写入至第二驱动信号输出端OUT1。可选地，第二驱动输出电路9内还包括有第十八晶体管M18和第二十五晶体管M25，其中第十八晶体管M18的控制极与第一下拉节点PD1连接，第二十五晶体管M25的控制极与第二下拉节点PD2连接。
在一些实施例中，第六防漏电电路37、第二上拉降噪电路32、第三驱动输出电路25、第四驱动输出电路29与第一下拉节点PD1连接。
第六防漏电电路37还配置为响应于第一下拉节点PD1处有效电平信 号的控制，将非有效电平信号写入至第六防漏点节点Q6。可选地，第六防漏电电路37包括第五十三晶体管M53和第五十八晶体管M58，其中第五十三晶体管M53的控制极与第二下拉节点PD2连接，第五十八晶体管M58的控制极与第一下拉节点PD1连接。
第二上拉降噪电路32还配置为响应于第一下拉节点PD1处有效电平信号的控制，将非有效电平信号写入至第二上拉节点PU2。可选地，第二上拉降噪电路32包括第四十四晶体管M44和第五十七晶体管M57，其中第四十四晶体管M44的控制极与第二下拉节点PD2连接，第五十七晶体管M57的控制极与第一下拉节点PD1连接。
第三驱动输出电路25还配置为响应于第一下拉节点PD1处有效电平信号的控制，将非有效电平信号写入至第三驱动信号输出端。可选地，第三驱动输出电路25内还包括有第四十七晶体管M47和第五十六晶体管M56，其中第四十七晶体管M47的控制极与第二下拉节点PD2连接，第五十六晶体管M56的控制极与第一下拉节点PD1连接。
第四驱动输出电路29还配置为响应于第一下拉节点PD1处有效电平信号的控制，将非有效电平信号写入至第四驱动信号输出端。可选地，第四驱动输出电路29内还包括有第四十八晶体管M48和第五十五晶体管M55，其中第四十八晶体管M48的控制极与第二下拉节点PD2连接，第五十五晶体管M55的控制极与第一下拉节点PD1连接。
需要说明的是，上述各实施例中所示移位寄存器单元均可以采用图11中所示时序，具体工作过程此处不再赘述。
另外，在本公开中的不同实施例中的不同电路结构部分之间可以相互组合，通过组合后所得到的新技术方案也应属于本公开的保护范围。
此外，在实际应用中，也可以在各电源端(尤其是第二电源端)与栅极驱动电路之间设置电感(一般电源管理芯片PMIC的某些输出端用于向显示基板提供电源电压以作为栅极驱动电路所配置的电源端，故电源 端所配置的电感可设置在电源管理芯片的相应输出端处，输出端所输出的电源电压通过电感后传输至栅极驱动电路)，以及在各第一/第二时钟信号输入端与栅极驱动电路之间设置电感(一般电平转换电路level shifter的某些输出端用于向栅极驱动电路提供时钟信号，故钟信号输入端所配置的电感可设置在电平转换电路的相应输出端处，输出端所输出的时钟信号通过电感后传输至栅极驱动电路)。通过在各电源端、各时钟信号输入端与栅极驱动电路之间设置电感，可以有效降低各电源端、时钟信号输入端处的瞬时电流。
图18为本公开实施例中在电源管理芯片上用作第二电源端的输出端与栅极驱动电路之间设置电感后第二电源端处电流变化的仿真图。如图18所示，在电源管理芯片上用作第二电源端的输出端与栅极驱动电路之间设置电感后，当时钟控制信号输入端CLKA所提供的信号的电平发生切换时，第二电源端处的瞬时电流的电流峰值约为47mA，远小于图12E和图12F中所示第二电源端处的电流峰值0.42A和0.28A。由此可见，电感的增设，可以有效减缓第二电源端的电流变化以及降低瞬时电流的电流峰值。
图19为本公开实施例提供的栅极驱动电路的一种电路结构示意图。图20为图19所示栅极驱动电路的一种工作时序图。如图19和图20所示，该栅极驱动电路包括级联的多个移位寄存器单元SRU1～SRU3，其中该移位寄存器单元SRU1～SRU3可采用前面任一实施例所提供的移位寄存器单元，对于该移位寄存器单元的具体描述，可参见前面实施例中的内容，此处不再赘述。
在一些实施例中，每个移位寄存器单元SRU1～SRU3用于驱动两行像素单元所对应的栅线时，也就是说移位寄存器单元内包括有第一驱动输出电路5、第二驱动输出电路9、第三驱动输出电路25、第四驱动输出电路29和第一级联输出电路13，此时每一级移位寄存器单元SRU1～SRU3 可看作是两个移位寄存器电路，例如移位寄存器单元SRU1包含移位寄存器电路SR1、SR2，移位寄存器单元SRU2包含移位寄存器电路SR3、SR4，移位寄存器单元SRU3包含移位寄存器电路SR5、SR6。
作为一个示例，显示面板内设置有2N行像素单元，则栅极驱动电路内可配置N个移位寄存器单元，N个移位寄存器单元级联，可看作是2N个移位寄存器电路级联，其中位于奇数位次的移位寄存器电路SR2n-1配置有感测信号输入端INPUT2、随机信号输入端OE、级联信号输出端CR，而位于偶数位次的移位寄存器电路SR2n未配置有感测信号输入端INPUT2和第一级联信号输出端CR，其中1≤n≤N且n为整数。
图19中仅示例性画出了3级移位寄存器单元SRU1～SRU3(6级移位寄存器电路SR1～SR6)的情况，该情况仅起到示例性作用。
在一些实施例中，各级移位寄存器单元SRU1～SRU3的感测信号输入端INPUT2与自身所配置的第一级联信号输出端CR相连接；各级移位寄存器单元SRU1～SRU3的时钟控制信号输入端CLKA与时钟控制信号线CKA连接，各级移位寄存器单元SRU1～SRU3的全局复位信号输入端T-RST与全局复位信号输入线TRST’连接，各级移位寄存器单元的随机信号输入端OE与随机信号输入线OE’连接。
在一些实施例中，除位于前a级的移位寄存器单元外的任意一个移位寄存器单元，移位寄存器单元的感测有效电平供给端与位于自身前a级的一个移位寄存器单元内的第一上拉节点连接；或者，除位于最后a级的移位寄存器单元外的任意一级移位寄存器单元，移位寄存器单元的感测有效电平供给端与位于自身后a级的一个移位寄存器单元内的第一上拉节点连接；其中，a为正整数(例如，a为1)。也就是说，本级移位寄存器单元可利用位于自身前a级或后a级的一个位寄存器单元内的第一上拉节点处电压，来完成对本级移位寄存器单元内第一感测控制节点的充电。
当然，本公开实施例中，移位寄存器单元的感测信号输入端还可以与其他端子相连；例如，本级移位寄存器单元的感测信号输入端与自身前b级或后b级(b为正整数)的某个移位寄存器单元的级联信号输出端相连。
本公开的技术方案对移位寄存器单元的感测信号输入端所连接端子不作限定。当然，为保证感测信号输入端具有较佳的充电能力；优选地，感测信号输入端与第三电源端相连。
位于第一极移位寄存器单元SRU1的显示信号输入端INPUT1与帧起始信号输入端STV相连，除位于第一级移位寄存器单元SRU1之外的其他任意一级移位寄存器单元，该移位寄存器单元的显示信号输入端INPUT1与自身前一级移位寄存器单元的第一级联信号输出端CR连接；各级移位寄存器单元的全局复位信号输入端T-RST与全局复位信号线连接；位于第N级的移位寄存器单元和位于第N-1级的移位寄存器单元的显示复位信号输入端RST与帧结束复位信号线相连，除位于第N级和第N-1级的移位寄存器单元之外的其他任意一级移位寄存器单元，该移位寄存器单元的显示复位信号输入端RST与自身后两级移位寄存器单元的第一级联信号输出端CR连接。
当然，在实际应用中，可以根据实际需要来对具体的级联方式进行调整。
在一些实施例中，针对该栅极驱动电路配置有6条第一驱动时钟信号线CKE1～CKE6和6条第二驱动时钟信号线CKD1～CKD6；
位于第3i+1级移位寄存器单元SRU3i+1的第一驱动时钟信号输入端CLKE与第一驱动时钟信号线CKE1连接，位于第3i+1级移位寄存器单元SRU3i+1的第二驱动时钟信号输入端CLKD与第二驱动时钟信号线CKD1连接，位于第3i+1级移位寄存器单元SRU3i+1的第三驱动时钟信号输入端CLKE’与第二驱动时钟信号线CKE2连接，位于第3i+1级移位寄存器 单元SRU3i+1的第四驱动时钟信号输入端CLKD’与第二驱动时钟信号线CKD2连接，位于第3i+1级移位寄存器单元SRU3i+1的级联时钟信号输入端(图19中未示出)与第二驱动时钟信号线CKD2连接。
位于第3i+2级移位寄存器单元SRU3i+2的第一驱动时钟信号输入端CLKE与第一驱动时钟信号线CKE3连接，位于第3i+2级移位寄存器单元SRU3i+2的第二驱动时钟信号输入端CLKD与第二驱动时钟信号线CKD3连接，位于第3i+2级移位寄存器单元SRU3i+2的第三驱动时钟信号输入端CLKE’与第二驱动时钟信号线CKE4连接，位于第3i+2级移位寄存器单元SRU3i+2的第四驱动时钟信号输入端CLKD’与第二驱动时钟信号线CKD4连接，位于第3i+2级移位寄存器单元SRU3i+2的级联时钟信号输入端(图19中未示出)与第二驱动时钟信号线CKD4连接。
位于第3i+3级移位寄存器单元SRU3i+3的第一驱动时钟信号输入端CLKE与第一驱动时钟信号线CKE5连接，位于第3i+3级移位寄存器单元SRU3i+3的第二驱动时钟信号输入端CLKD与第二驱动时钟信号线CKD5连接，位于第3i+3级移位寄存器单元SRU3i+3的第三驱动时钟信号输入端CLKE’与第二驱动时钟信号线CKE6连接，位于第3i+3级移位寄存器单元SRU3i+3的第四驱动时钟信号输入端CLKD’与第二驱动时钟信号线CKD6连接，位于第3i+3级移位寄存器单元SRU3i+3的级联时钟信号输入端(图19中未示出)与第二驱动时钟信号线CKD6连接。其中，i为正整数且3i+3≤N。
基于同一发明构思，本公开实施例还提供了一种显示基板，其中该显示基板包括衬底基板和位于衬底基板上的栅极驱动电路，其中栅极驱动电路可采用前面实施例所提供栅极驱动电路，对于该栅极驱动电路的具体描述，可参见前面实施例中的内容，此处不再赘述。
在一些实施例中，栅极驱动电路采用GOA方式制备于显示基板上，显示基板具体可以为阵列基板。
基于同一发明构思，本公开实施例还提供了一种显示装置，该显示装置包括前面实施例所提供的显示面板，对于该显示面板的具体描述，可参见前面实施例中的内容，此处不再赘述。
本公开实施例所提供的显示装置可以为：液晶显示屏、可穿戴设备、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (46)

  1. 一种移位寄存器单元，其中，包括：
    第一感测控制输入电路，与感测控制节点、感测信号输入端、随机信号输入端、时钟控制信号输入端和第一上拉节点连接，配置为响应于所述随机信号输入端所提供有效电平信号的控制，将所述感测信号输入端所提供信号写入至所述感测控制节点，以及响应于所述感测控制节点处有效电平信号和所述时钟控制信号所提供有效电平信号的控制，将有效电平信号写入至所述第一上拉节点；
    至少一个第一输出电路，所述第一输出电路与所述第一上拉节点、第一时钟信号输入端和第一信号输出端连接，配置为响应于所述第一上拉节点处有效电平信号的控制将所述第一时钟信号输入端所提供信号写入至对应的所述第一信号输出端；
    所述移位寄存器单元还包括：第一控压电路、第一感测输入防漏电电路和第一限流电路；
    所述第一控压电路与第一电源端、所述第一上拉节点和第一控压节点连接，所述第一控压电路配置为响应于所述第一上拉节点处有效电平信号的控制将所述第一电源端所提供有效电平信号写入至所述第一控压节点；
    所述第一感测控制输入电路通过所述第一感测输入防漏电电路与所述第一上拉节点连接，所述第一感测控制输入电路与所述第一感测输入防漏电电路连接于第一感测输入防漏电节点，所述第一感测输入防漏电节点与所述第一控压节点连接，所述第一感测输入防漏电电路与所述时钟控制信号输入端连接，所述第一感测输入防漏电电路配置为响应于所述时钟控制信号输入端处有效电平信号的控制使得所述第一感测输入防漏电节点与所述第一上拉节点之间形成通路，以及响应于所述时钟控制 信号输入端处非有效电平信号的控制使得所述第一感测输入防漏电节点与所述第一上拉节点之间形成断路；
    所述第一限流电路与所述第一控压节点连接。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第一限流电路包括：
    第一负载电路，位于所述第一感测输入防漏电节点与所述第一控压节点之间，配置为增大所述第一感测输入防漏电节点与所述第一控压节点之间的负载电阻。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述第一负载电路包括：第八十一晶体管；
    所述第八十一晶体管的控制极与所述第一控压节点连接，所述第八十一晶体管的第一极与所述第一感测输入防漏电节点连接，所述第八十一晶体管的第二极与所述第一控压节点连接。
  4. 根据权利要求1至3中任一所述的移位寄存器单元，其中，所述第一限流电路包括：
    第二负载电路，与所述第一控压节点和第二电源端连接，配置为增大所述第一控压节点处的负载电容。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述第二负载电路包括：第十一电容；
    所述第十一电容的第一端与所述第一控压节点连接，所述第十一电容的第二端与第二电源端连接。
  6. 根据权利要求1至5中任一所述的移位寄存器单元，其中，还包括：
    第一全局复位电路，与全局复位信号输入端、第二电源端、所述第一上拉节点连接，所述第一全局复位电路配置为响应于所述全局复位信号输入端所提供有效电平信号的控制将所述第二电源端所提供非有效电平信号写入至所述第一上拉节点；
    所述第一防漏电电路，所述第一全局复位电路通过所述第一防漏电电路与第二电源端连接，所述第一全局复位电路与所述第一防漏电电路连接于第一防漏电节点，所述第一防漏电节点与所述第一控压节点连接，所述第一防漏电电路与全局复位信号输入端连接，所述第一防漏电电路配置为响应于所述全局复位信号输入端所提供有效电平信号的控制使得所述第一防漏电节点与所述第二电源端之间形成通路，以及响应于所述全局复位信号输入端所提供非有效电平信号的控制使得所述第一防漏电节点与所述第二电源端之间形成断路。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述第一限流电路包括：
    第三负载电路，位于所述第一防漏电节点与所述第一控压节点之间，配置为增大所述第一防漏电节点与所述第一控压节点之间的负载电阻。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述第三负载电路包括：第八十二晶体管；
    所述第八十二晶体管的控制极与所述第一控压节点连接，所述第八十二晶体管的第一极与所述第一防漏电节点连接，所述第八十二晶体管的第二极与所述第一控压节点连接。
  9. 根据权利要求6至8中任一所述的移位寄存器单元，其中，还包括：
    第五负载电路，所述第一全局复位电路和所述第一防漏电电路中至少之一通过所述第五负载电路与全局复位信号输入端连接，所述第五负载电路配置增大所述第一全局复位电路和所述第一防漏电电路中至少之一与所述全局复位信号输入端之间的负载电阻。
  10. 根据权利要求9所述的移位寄存器单元，其中，所述第五负载电路包括：第八十四晶体管；
    所述第八十四晶体管的控制极与所述全局复位信号输入端连接，所述第八十四晶体管的第一极与所述全局复位信号输入端连接，所述第八十四晶体管的第二极与所述第一全局复位电路和所述第一防漏电电路中至少之一连接。
  11. 根据权利要求1至10中任一所述的移位寄存器单元，其中，还包括：
    第一下拉控制电路，与第二电源端、第五电源端、所述第一上拉节点和第一下拉节点连接，配置为向所述第一下拉节点处写入与所述第一上拉节点处电压反相的电压；
    第一上拉降噪电路，与所述第二电源端、所述第一上拉节点和第一下拉节点连接，配置为响应于所述第一下拉节点处有效电平信号的控制将所述第二电源端所提供非有效电平信号写入至所述第一上拉节点；
    所述第一输出电路还与所述第一下拉节点和第二电源端连接，所述第一输出电路还配置为响应于所述第一下拉节点处有效电平信号的控制，将所述第二电源端提供的非有效电平信号写入至对应的所述第一信号输出端；
  12. 根据权利要求11所述的移位寄存器单元，其中，还包括：
    第三防漏电电路，所述第一上拉降噪电路通过所述第三防漏电电路与第二电源端连接，所述第一上拉降噪电路与所述第三防漏电电路连接于第三防漏电节点，所述第三防漏电节点与所述第一控压节点连接，所述第三防漏电电路与第一下拉节点连接，所述第三防漏电电路配置为响应于所述第一下拉节点处有效电平信号的控制使得所述第三防漏电节点与所述第二电源端之间形成通路，以及响应于所述第一下拉节点处非有效电平信号的控制使得所述第三防漏电节点与所述第二电源端之间形成断路。
  13. 根据权利要求12所述的移位寄存器单元，其中，所述第一控压节点位于所述第一感测输入防漏电节点与所述第三防漏电节点之间；
    所述第一限流电路包括：
    第四负载电路，位于所述第一控压节点与所述第三防漏电节点之间，配置为配置为增大所述第一控压节点与所述第三防漏电节点之间的负载电阻。
  14. 根据权利要求13所述的移位寄存器单元，其中，所述第四负载电路包括：
    所述第八十三晶体管的控制极与所述第一控压节点连接，所述第八十三晶体管的第一极与所述第一控压节点连接，所述第八十三晶体管的第二极与所述第三防漏电节点连接。
  15. 根据权利要求1至14中任一所述的移位寄存器单元，其中，还包括：
    第一下拉降噪电路，与第一下拉节点、第二电源端、感测控制节点和时钟控制信号输入端连接，配置为响应于感测控制节点处有效电平信号和时钟控制信号输入端所提供有效电平信号的控制，将第二电源端提供的非有效电平信号写入至第一下拉节点。
  16. 根据权利要求15所述的移位寄存器单元，其中，所述第一下拉降噪电路包括：第二十九晶体管和第三十晶体管；
    第二十九晶体管的控制极与时钟控制信号输入端连接，第二十九晶体管的第一极与第一下拉节点连接，第二十九晶体管的第二极与第三十晶体管的第一极连接；
    第三十晶体管的控制极与感测控制节点连接，第三十晶体管的第二极与第二电源端连接。
  17. 根据权利要求16所述的移位寄存器单元，其中，所述第一下拉降噪电路还包括：第八十五晶体管，所述第二十九晶体管的第一极通过所述第八十五晶体管与所述第一下拉节点连接；
    所述第八十五晶体管的控制极与所述感测控制节点连接，所述第八十五晶体管的第一极与所述第一下拉节点连接，所述第八十五晶体管的第二极与所述第二十九晶体管的第一极连接。
  18. 根据权利要求1至17中任一所述的移位寄存器单元，其中，还包括：
    第一显示输入电路，与显示信号输入端、第一电源端和第一上拉节点连接，配置为响应于所述显示信号输入端所提供有效电平信号的控制将所述第一电源端所提供有效电平信号写入至所述第一上拉节点；
    第一显示复位电路，与显示复位信号输入端、第二电源端、所述第 一上拉节点连接，配置为响应于所述显示复位信号输入端所提供有效电平信号的控制，将所述第二电源端所提供非有效电平信号写入至所述第一上拉节点。
  19. 根据权利要求18所述的移位寄存器单元，其中，还包括：第一显示输入防漏电电路和第二防漏电电路中至少之一；
    所述第一显示输入电路通过所述第一显示输入防漏电电路与所述第一上拉节点连接，所述第一显示输入电路与所述第一显示输入防漏电电路连接于第一显示输入防漏电节点，所述第一显示输入防漏电节点与所述第一控压节点连接，所述第一显示输入防漏电电路与所述显示信号输入端连接，所述第一显示输入防漏电电路配置为响应于所述显示信号输入端所提供有效电平信号的控制使得所述第一显示输入防漏电节点与所述第一上拉节点之间形成通路，以及响应于所述显示信号输入端所提供非有效电平信号的控制使得所述第一显示输入防漏电节点与所述第一上拉节点之间形成断路；
    所述第一显示复位电路通过所述第二防漏电电路与第二电源端连接，所述第一显示复位电路与所述第二防漏电电路连接于第二防漏电节点，所述第二防漏电节点与所述第一控压节点连接，所述第二防漏电电路与显示复位信号输入端连接，所述第二防漏电电路配置为响应于所述显示复位信号输入端所提供有效电平信号的控制使得所述第二防漏电节点与所述第二电源端之间形成通路，以及响应于所述显示复位信号输入端所提供非有效电平信号的控制使得所述第二防漏电节点与所述第二电源端之间形成断路。
  20. 根据权利要求1至19中任一所述的移位寄存器单元，其中，所述第一感测控制输入电路包括：感测控制电路和第一感测输入电路；
    所述感测控制电路与所述感测控制节点、所述感测信号输入端和所述随机信号输入端连接，所述感测控制电路配置为响应于所述随机信号输入端所提供有效电平信号的控制，将所述感测信号输入端所提供信号写入至所述感测控制节点；
    所述第一感测输入电路与所述感测控制节点、时钟控制信号输入端、感测中间节点和所述第一上拉节点连接，配置为响应于所述感测控制节点处有效电平信号的控制，将有效电平信号写入至所述感测中间节点，以及响应于所述时钟控制信号输入端所提供有效电平信号的控制，使得所述感测中间节点与所述第一上拉节点之间形成通路。
  21. 根据权利要求20所述的移位寄存器单元，其中，还包括：感测控制防漏电电路；
    所述感测控制电路通过所述感测控制防漏电电路与感测控制节点连接，所述感测控制防漏电电路与所述感测控制电路连接于感测控制防漏电节点，所述感测控制防漏电电路还与所述第一电源端、感测控制节点和随机信号输入端连接，所述感测控制防漏电电路配置为响应于所述感测控制节点处有效电平信号的控制，将所述第一电源端提供的有效电平信号写入至所述感测控制防漏电节点，以及配置为响应于所述随机信号输入端所提供有效电平信号的控制使得所述感测控制防漏电节点与所述感测控制节点之间形成通路，以及响应于所述随机信号输入端所提供非有效电平信号的控制使得所述感测控制防漏电节点与所述感测控制节点之间形成断路。
  22. 根据权利要求20或21中所述的移位寄存器单元，其中，还包括：
    第二感测输入电路，与所述时钟控制信号输入端、第二上拉节点和 预设供电节点连接，配置为响应于所述时钟控制信号输入端所提供有效电平信号的控制，使得所述预设供电节点与所述第二上拉节点之间形成通路；
    至少一个第二输出电路，所述第二输出电路与所述第二上拉节点、对应的第二时钟信号输入端和对应的第二信号输出端连接，配置为响应于所述第二上拉节点处有效电平信号的控制将对应的所述第二时钟信号输入端所提供信号写入至对应的所述第二信号输出端；
    所述预设供电节点为所述感测中间节点或所述第一感测输入防漏电节点
  23. 根据权利要求22所述的移位寄存器单元，其中，所述预设供电节点为所述第一感测输入防漏电节点；
    所述移位寄存器单元还包括：第二控压电路和第二限流电路；
    所述第二控压电路与第一电源端、所述第二上拉节点和第二控压节点连接，所述第二控压电路配置为响应于所述第二上拉节点处有效电平信号的控制将所述第一电源端所提供有效电平信号写入至所述第二控压节点；
    所述第二限流电路与所述第二控压节点连接，所述第二限流电路配置为降低所述第二控压节点处的充放电电流。
  24. 根据权利要求23所述的移位寄存器单元，其中，所述第二限流电路包括：
    第十一负载电路，位于所述第一感测输入防漏电节点与所述第二控压节点之间，配置为增大所述第一感测输入防漏电节点与所述第二控压节点之间的负载电阻。
  25. 根据权利要求24所述的移位寄存器单元，其中，所述第十一负载电路包括：第九十一晶体管；
    所述第九十一晶体管的控制极与所述第二控压节点连接，所述第九十一晶体管的第一极与所述第二控压节点，所述第九十一晶体管的第二极与所述第一感测输入防漏电节点连接。
  26. 根据权利要求22所述的移位寄存器单元，其中，所述预设供电节点为所述感测中间节点；
    所述移位寄存器单元还包括：第二控压电路、第二感测输入防漏电电路和第二限流电路；
    所述第二控压电路与第一电源端、所述第二上拉节点和第二控压节点连接，所述第二控压电路配置为响应于所述第二上拉节点处有效电平信号的控制将所述第一电源端所提供有效电平信号写入至所述第二控压节点；
    所述第二感测输入电路通过所述第二感测输入防漏电电路与所述第二上拉节点连接，所述第二感测输入电路与所述第二感测输入防漏电电路连接于第二感测输入防漏电节点，所述第二感测输入防漏电节点与所述第二控压节点连接，所述第二感测输入防漏电电路与所述时钟控制信号输入端连接，所述第二感测输入防漏电电路配置为响应于所述时钟控制信号输入端处有效电平信号的控制使得所述第二感测输入防漏电节点与所述第二上拉节点之间形成通路，以及响应于所述时钟控制信号输入端处非有效电平信号的控制使得所述第二感测输入防漏电节点与所述第二上拉节点之间形成断路；
    所述第二限流电路与所述第二控压节点连接，所述第二限流电路配置为降低所述第二控压节点处的充放电电流。
  27. 根据权利要求27所述的移位寄存器单元，其中，所述第二限流电路包括：
    第十一负载电路，位于所述第二感测输入防漏电节点与所述第二控压节点之间，配置为增大所述第二感测输入防漏电节点与所述第二控压节点之间的负载电阻。
  28. 根据权利要求28所述的移位寄存器单元，其中，所述第十一负载电路包括：第九十一晶体管；
    所述第九十一晶体管的控制极与所述第二控压节点连接，所述第九十一晶体管的第一极与所述第二感测输入防漏电节点连接，所述第九十一晶体管的第二极与所述第二控压节点连接。
  29. 根据权利要求23至29所述的移位寄存器单元，其中，所述第二限流电路包括：
    第十二负载电路，与所述第二控压节点和第二电源端连接，配置为增大所述第二控压节点处的负载电容。
  30. 根据权利要求30所述的移位寄存器单元，其中，所述第十二负载电路包括：第十二电容；
    所述第十二电容的第一端与所述第二控压节点连接，所述第十二电容的第二端与第二电源端连接。
  31. 根据权利要求23至31中任一所述的移位寄存器单元，其中，还包括：
    第二全局复位电路，与全局复位信号输入端、第二电源端、所述第二上拉节点连接，所述第二全局复位电路配置为响应于所述全局复位信 号输入端所提供有效电平信号的控制将所述第二电源端所提供非有效电平信号写入至所述第二上拉节点；
    所述第四防漏电电路，所述第二全局复位电路通过所述第四防漏电电路与第二电源端连接，所述第二全局复位电路与所述第四防漏电电路连接于第四防漏电节点，所述第四防漏电节点与所述第二控压节点连接，所述第四防漏电电路与全局复位信号输入端连接，所述第四防漏电电路配置为响应于所述全局复位信号输入端所提供有效电平信号的控制使得所述第二防漏电节点与所述第二电源端之间形成通路，以及响应于所述全局复位信号输入端所提供非有效电平信号的控制使得所述第四防漏电节点与所述第二电源端之间形成断路。
  32. 根据权利要求32所述的移位寄存器单元，其中，所述第二限流电路包括：
    第十三负载电路，位于所述第四防漏电节点与所述第二控压节点之间，配置为增大所述第四防漏电节点与所述第二控压节点之间的负载电阻。
  33. 根据权利要求33所述的移位寄存器单元，其中，所述第十三负载电路包括：第九十二晶体管；
    所述第九十二晶体管的控制极与所述第二控压节点连接，所述第九十二晶体管的第一极与所述第四防漏电节点连接，所述第九十二晶体管的第二极与所述第二控压节点连接。
  34. 根据权利要求32至34中任一所述的移位寄存器单元，其中，还包括：
    第十五负载电路，所述第二全局复位电路和所述第四防漏电电路中 至少之一通过所述第十五负载电路与全局复位信号输入端连接，所述第十五负载电路配置增大所述第一全局复位电路和所述第一防漏电电路中至少之一与所述全局复位信号输入端之间的负载电阻。
  35. 根据权利要求35所述的移位寄存器单元，其中，所述第十五负载电路包括：第九十四晶体管；
    所述第九十四晶体管的控制极与所述全局复位信号输入端连接，所述第九十四晶体管的第一极与所述全局复位信号输入端连接，所述第九十四晶体管的第二极与所述第二全局复位电路和所述第四防漏电电路中至少之一连接。
  36. 根据权利要求23至36中任一所述的移位寄存器单元，其中，还包括：
    第二下拉控制电路，与第二电源端、第五电源端、所述第二上拉节点和第二下拉节点连接，配置为向所述第二下拉节点处写入与所述第二上拉节点处电压反相的电压；
    第二上拉降噪电路，与所述第二电源端、所述第二上拉节点和第二下拉节点连接，配置为响应于所述第二下拉节点处有效电平信号的控制将所述第二电源端所提供非有效电平信号写入至所述第二上拉节点；
    所述第二输出电路还与所述第二下拉节点和第二电源端连接，所述第二输出电路还配置为响应于所述第二下拉节点处有效电平信号的控制，将所述第二电源端提供的非有效电平信号写入至对应的所述第二信号输出端；
  37. 根据权利要求37所述的移位寄存器单元，其中，还包括：
    第六防漏电电路，所述第二上拉降噪电路通过所述第六防漏电电路 与第二电源端连接，所述第二上拉降噪电路与所述第六防漏电电路连接于第六防漏电节点，所述第六防漏电节点与所述第二控压节点连接，所述第六防漏电电路与第二下拉节点连接，所述第六防漏电电路配置为响应于所述第二下拉节点处有效电平信号的控制使得所述第六防漏电节点与所述第二电源端之间形成通路，以及响应于所述第二下拉节点处非有效电平信号的控制使得所述第六防漏电节点与所述第二电源端之间形成断路。
  38. 根据权利要求12所述的移位寄存器单元，其中，所述第二控压节点位于所述第二感测输入防漏电节点与所述第六防漏电节点之间；
    所述第二限流电路包括：
    第十四负载电路，位于所述第二控压节点与所述第六防漏电节点之间，配置为配置为增大所述第二控压节点与所述第六防漏电节点之间的负载电阻。
  39. 根据权利要求39所述的移位寄存器单元，其中，所述第十四负载电路包括：
    所述第九十三晶体管的控制极与所述第二控压节点连接，所述第九十三晶体管的第一极与所述第二控压节点连接，所述第九十三晶体管的第二极与所述第六防漏电节点连接。
  40. 根据权利要求22至40中任一所述的移位寄存器单元，其中，还包括：
    第三下拉降噪电路，与第二下拉节点、第二电源端、感测控制节点和时钟控制信号输入端连接，配置为响应于感测控制节点处有效电平信号和时钟控制信号输入端所提供有效电平信号的控制，将第二电源端提 供的非有效电平信号写入至第二下拉节点。
  41. 根据权利要求41所述的移位寄存器单元，其中，所述第三下拉降噪电路包括：第五十九晶体管和第六十晶体管；
    第五十九晶体管的控制极与时钟控制信号输入端连接，第五十九晶体管的第一极与第二下拉节点连接，第五十九晶体管的第二极与第六十晶体管的第一极连接。
    第六十晶体管的控制极与感测控制节点连接，第六十晶体管的第二极与第二电源端连接。
  42. 根据权利要求42所述的移位寄存器单元，其中，所述第三下拉降噪电路还包括：第九十五晶体管，所述第五十九晶体管的第一极通过所述第九十五晶体管与所述第二下拉节点连接；
    所述第九十五晶体管的控制极与所述感测控制节点连接，所述第九十五晶体管的第一极与所述第二下拉节点连接，所述第九十五晶体管的第二极与所述第五十九晶体管的第一极连接。
  43. 根据权利要求22至43中任一所述的移位寄存器单元，其中，还包括：
    第二显示输入电路，与显示信号输入端、第一电源端和第二上拉节点连接，配置为响应于所述显示信号输入端所提供有效电平信号的控制将所述第一电源端所提供有效电平信号写入至所述第二上拉节点；
    第二显示复位电路，与显示复位信号输入端、第二电源端、所述第二上拉节点连接，配置为响应于所述显示复位信号输入端所提供有效电平信号的控制，将所述第二电源端所提供非有效电平信号写入至所述第二上拉节点。
  44. 根据权利要求44所述的移位寄存器单元，其中，还包括：第二显示输入防漏电电路和第五防漏电电路中至少之一；
    所述第二显示输入电路通过所述第二显示输入防漏电电路与所述第二上拉节点连接，所述第二显示输入电路与所述第二显示输入防漏电电路连接于第二显示输入防漏电节点，所述第二显示输入防漏电节点与所述第二控压节点连接，所述第二显示输入防漏电电路与所述显示信号输入端连接，所述第二显示输入防漏电电路配置为响应于所述显示信号输入端所提供有效电平信号的控制使得所述第二显示输入防漏电节点与所述第二上拉节点之间形成通路，以及响应于所述显示信号输入端所提供非有效电平信号的控制使得所述第二显示输入防漏电节点与所述第二上拉节点之间形成断路；
    所述第二显示复位电路通过所述第五防漏电电路与第二电源端连接，所述第二显示复位电路与所述第五防漏电电路连接于第五防漏电节点，所述第五防漏电节点与所述第二控压节点连接，所述第五防漏电电路与显示复位信号输入端连接，所述第五防漏电电路配置为响应于所述显示复位信号输入端所提供有效电平信号的控制使得所述第五防漏电节点与所述第二电源端之间形成通路，以及响应于所述显示复位信号输入端所提供非有效电平信号的控制使得所述第五防漏电节点与所述第二电源端之间形成断路。
  45. 一种栅极驱动电路，其中，包括：级联的多个移位寄存器单元，所述移位寄存器单元采用上述权利要求1至45中任一所述移位寄存器单元。
  46. 一种显示基板，其中，包括：衬底基板和位于衬底基板上的栅极驱动电路，所述栅极驱动电路采用权利要求46中所述栅极驱动电路。
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CN112634805A (zh) * 2020-12-15 2021-04-09 云谷（固安）科技有限公司 移位寄存器、显示面板及显示装置
CN114596817A (zh) * 2022-03-23 2022-06-07 合肥京东方卓印科技有限公司 移位寄存器单元、栅极驱动电路、显示面板和显示装置

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