WO2024087034A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024087034A1
WO2024087034A1 PCT/CN2022/127475 CN2022127475W WO2024087034A1 WO 2024087034 A1 WO2024087034 A1 WO 2024087034A1 CN 2022127475 W CN2022127475 W CN 2022127475W WO 2024087034 A1 WO2024087034 A1 WO 2024087034A1
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WO
WIPO (PCT)
Prior art keywords
clock signal
sub
connection
lines
signal line
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PCT/CN2022/127475
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/127475 priority Critical patent/WO2024087034A1/zh
Publication of WO2024087034A1 publication Critical patent/WO2024087034A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • This article relates to but is not limited to the field of display technology, and in particular to a display panel and a display device.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • PDP plasma display panel
  • FED field emission display
  • Embodiments of the present disclosure provide a display panel and a display device.
  • this embodiment provides a display panel, comprising: a substrate, and a gate drive circuit, a plurality of clock signal lines and a plurality of connecting lines arranged on the substrate; the plurality of clock signal lines are located on one side of the gate drive circuit along a first direction and are arranged in sequence; each connecting line electrically connects the gate drive circuit and a clock signal line.
  • At least one of the plurality of connecting lines comprises a load adjustment unit, and the load adjustment unit is configured to compensate for the load difference between different clock signal lines.
  • the load adjustment unit of the at least one connecting line at least partially overlaps the orthographic projection of the substrate with the orthographic projection of at least one clock signal line at the substrate; or, the plurality of connecting lines all comprise a load adjustment unit, and the load adjustment units of the plurality of connecting lines are located on a side of the plurality of clock signal lines away from the gate drive circuit, or on a side of the plurality of clock signal lines close to the gate drive circuit, or in a spacing area between two adjacent clock signal lines.
  • an orthographic projection of the load adjustment portion of the at least one connection line on the substrate at least partially overlaps with an orthographic projection of a clock signal line connected to the load adjustment portion on the substrate.
  • the orthographic projections of the load adjustment parts of the plurality of connection lines on the substrate overlap with the orthographic projection of the same clock signal line on the substrate.
  • the at least one connecting line further comprises: a first connecting portion and a second connecting portion, the load adjustment portion is connected between the first connecting portion and the second connecting portion, the first connecting portion is electrically connected to a clock signal line, and the second connecting portion is electrically connected to the gate driving circuit.
  • the plurality of clock signal lines extend along a second direction, the second direction intersecting the first direction; the second connecting portion of the at least one connecting line extends along the first direction.
  • the load regulating portion of the at least one connecting line includes: a first sub-connecting portion, a second sub-connecting portion, and a third sub-connecting portion, the first sub-connecting portion and the third sub-connecting portion extend along the second direction, the second sub-connecting portion extends along the first direction, and both ends of the second sub-connecting portion are respectively connected to the first sub-connecting portion and the third sub-connecting portion.
  • the load adjustment portion of the at least one connecting line further includes: a fourth sub-connection portion extending along the first direction, wherein both ends of the fourth sub-connection portion are respectively connected to the first sub-connection portion and the third sub-connection portion; and the second sub-connection portion and the fourth sub-connection portion have substantially the same length along the first direction.
  • the first sub-connection portions of the load adjustment portions of the plurality of connection lines have substantially the same length along the second direction
  • the third sub-connection portions of the load adjustment portions of the plurality of connection lines have substantially the same length along the second direction.
  • the distance along the second direction between the second sub-connection portion and the fourth sub-connection portion of the load regulation portion of the connection line electrically connected to the clock signal line close to the gate driving circuit is smaller than the distance along the second direction between the second sub-connection portion and the fourth sub-connection portion of the load regulation portion of the connection line electrically connected to the clock signal line far from the gate driving circuit.
  • the lengths of the first connection portions of the plurality of connection lines along the second direction are substantially the same, and the lengths of the second connection portions of the connection portions of the connection portions electrically connected to the clock signal lines close to the gate drive circuit along the first direction are smaller than the lengths of the second connection portions of the connection portions of the connection portions electrically connected to the clock signal lines far from the gate drive circuit along the first direction.
  • the distance along the second direction between the second sub-connection portion and the fourth sub-connection portion of the load adjustment portion of the connection line electrically connected to the clock signal line close to the gate driving circuit is greater than the distance along the second direction between the second sub-connection portion and the fourth sub-connection portion of the load adjustment portion of the connection line electrically connected to the clock signal line far from the gate driving circuit.
  • the lengths of the second connection portions of the multiple connection lines along the first direction are approximately the same, and the length of the first connection portion of the connection line electrically connected to the clock signal line close to the gate driving circuit along the first direction is greater than the length of the first connection portion of the connection line electrically connected to the clock signal line far from the gate driving circuit along the first direction.
  • an overlapping area between a load adjustment portion of a connection line electrically connected to a clock signal line away from the gate drive circuit and an orthographic projection of the clock signal line is greater than an overlapping area between a load adjustment portion of a connection line electrically connected to the clock signal line close to the gate drive circuit and an orthographic projection of the clock signal line.
  • the gate drive circuit includes a plurality of cascaded gate drive subcircuits; each gate drive subcircuit includes at least a first output transistor; the first output transistor is configured to provide a clock signal to a signal output terminal of the gate drive subcircuit.
  • the size of the first output transistor of the gate drive subcircuit electrically connected to the clock signal line away from the gate drive circuit is larger than the size of the first output transistor of the gate drive subcircuit electrically connected to the clock signal line close to the gate drive circuit.
  • a voltage amplitude of a clock signal transmitted by a clock signal line close to the gate driving circuit is smaller than a voltage amplitude of a clock signal transmitted by a clock signal line far from the gate driving circuit.
  • the resistances of the plurality of connection lines are substantially the same.
  • this embodiment provides a display device, including the display panel as described above.
  • FIG1 is a schematic diagram of the appearance of a display panel
  • FIG2 is a schematic diagram of a partial cross-sectional structure of a display area of a display panel
  • FIG3 is an equivalent circuit diagram of a pixel circuit
  • FIG4 is an equivalent circuit diagram of a gate drive subcircuit
  • FIG5 is a working timing diagram of the gate drive sub-circuit shown in FIG4 ;
  • FIG6 is a schematic diagram of a gate driving circuit
  • FIG. 7 is a partial schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG8 is another partial schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 9 is another partial schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG10 is another partial schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 11 is another partial schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG12 is another partial schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG13 is another partial schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG14 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure.
  • FIG15 is a schematic diagram of a clock signal according to at least one embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • one of the electrodes is called the first pole and the other electrode is called the second pole.
  • the first pole can be a source electrode or a drain electrode
  • the second pole can be a drain electrode or a source electrode.
  • the gate of the transistor can be called a control electrode.
  • parallel means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle may be greater than -5° and less than 5°.
  • perpendicular means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle may be greater than 85° and less than 95°.
  • triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • FIG1 is a schematic diagram of the appearance of a display panel, which is a rectangular rounded shape.
  • the display panel can be a closed polygon including linear edges, a circle or ellipse including curved edges, or a semicircle or semi-ellipse including linear edges and curved edges.
  • at least some corners of the display panel can be curves.
  • the portion where adjacent linear edges meet each other can be replaced by a curve with a predetermined curvature.
  • the curvature can be set according to the position of the curve. For example, the curvature can be changed according to the position where the curve starts, the length of the curve, etc.
  • the display panel may include a display area AA and a peripheral area BB located around the display area.
  • the display area AA may include a first edge (lower edge) and a second edge (upper edge) relatively arranged in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) relatively arranged in the first direction X. Adjacent edges may be connected by arc-shaped chamfers to form a rounded quadrilateral shape.
  • the peripheral area BB may include: a first frame (lower frame) and a second frame (upper frame) relatively arranged in the second direction Y, and a third frame (left frame) and a fourth frame (right frame) relatively arranged in the first direction X.
  • the first frame is connected to the third frame and the fourth frame, respectively, and the second frame is connected to the third frame and the fourth frame, respectively.
  • the display area AA may include at least a plurality of sub-pixels PX, a plurality of scan lines GL, and a plurality of data lines DL.
  • the plurality of scan lines GL may extend along a first direction X
  • the plurality of data lines DL may extend along a second direction Y.
  • the orthographic projections of the plurality of scan lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions, and a sub-pixel PX may be disposed in each sub-pixel region.
  • the plurality of data lines DL are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX.
  • the plurality of scan lines GL are electrically connected to the plurality of sub-pixels PX, and the plurality of scan lines GL may be configured to provide scan signals to the plurality of sub-pixels PX.
  • the first direction X may be an extension direction (row direction) of the scan lines GL in the display area AA
  • the second direction Y may be an extension direction (column direction) of the data lines DL in the display area AA.
  • the first direction X and the second direction Y may be perpendicular to each other.
  • a pixel unit of display area AA may include three sub-pixels, and the three sub-pixels are respectively a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • this embodiment is not limited to this.
  • a pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a square pattern.
  • this embodiment is not limited to this.
  • a sub-pixel may include: a pixel circuit and a light-emitting element connected to the pixel circuit.
  • the pixel circuit may include multiple transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C structure, a 7T1C structure, a 5T1C structure, an 8T1C structure, or an 8T2C structure, etc., wherein T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.
  • the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc.
  • the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit.
  • the color of the light emitted by the light-emitting element may be determined according to needs.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • the display panel may further include: a gate drive circuit and a data drive circuit.
  • the gate drive circuit may be provided at the third frame and the fourth frame of the display panel.
  • the gate drive circuit may be formed together with the sub-pixel in the process of forming the sub-pixel.
  • the data drive circuit may be provided on a separate chip or printed circuit board to be connected to the sub-pixel through a signal access pin on the display panel.
  • the data drive circuit may be formed by using a chip on glass, a chip on plastic, a chip on a film, etc. to be provided at the first frame of the display panel to be connected to the signal access pin.
  • this embodiment is not limited to this.
  • the data drive circuit may be provided directly on the display panel.
  • the gate drive circuit can generate a scan signal to be provided to the scan line GL by a clock signal, a start signal, etc. received from a timing controller.
  • the gate drive circuit can sequentially provide a scan signal having an on-level pulse to the gate line.
  • the gate drive circuit can include a shift register, which can sequentially transmit the start signal provided in the form of an on-level pulse to the next level circuit under the control of the clock signal to generate a scan signal.
  • FIG2 is a schematic diagram of a partial cross-sectional structure of a display area of a display panel.
  • FIG2 illustrates the structure of three sub-pixels in the display area.
  • the display panel may include: a substrate 101, and a circuit structure layer 102, a light-emitting structure layer 103, a packaging structure layer 104, and a packaging cover plate 200 sequentially arranged on the substrate 101.
  • the display panel may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the substrate 101 may be a rigid substrate or a flexible substrate.
  • the rigid substrate may be made of materials such as glass or quartz.
  • the flexible substrate may be made of materials such as polyimide (PI), and the flexible substrate may be a single-layer structure, or may be a laminated structure consisting of an inorganic material layer and a flexible material layer.
  • PI polyimide
  • the circuit structure layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel circuit, and FIG2 is illustrated by taking a transistor and a storage capacitor included in the pixel circuit of each sub-pixel as an example.
  • the circuit structure layer 102 of each sub-pixel may include: an active layer, a first insulating layer 11, a first gate metal layer (for example, including a gate electrode of a transistor and a first plate of a storage capacitor), a second insulating layer 12, a second gate metal layer (for example, including a second plate of a storage capacitor), a third insulating layer 13, a first source-drain metal layer (for example, including a source electrode and a drain electrode of a transistor), and a fourth insulating layer 14, which are sequentially arranged on the substrate 101.
  • a via hole is provided on the third insulating layer 13 to expose the surface of the active layer, and the source electrode and the drain electrode of the transistor can be connected to the active layer through the via hole, respectively.
  • the fourth insulating layer 14 may be provided with a via hole exposing the drain electrode of the transistor.
  • the active layer, the gate electrode, the source electrode, and the drain electrode may constitute a transistor 105, and the first plate and the second plate may constitute a storage capacitor 106.
  • the light emitting structure layer 103 may include an anode layer, a pixel definition layer, an organic light emitting layer, and a cathode.
  • the anode layer may include an anode of a light emitting element, and the anode may be disposed on the fourth insulating layer 14, and connected to the drain electrode of the transistor of the pixel circuit through a via hole provided on the fourth insulating layer 14.
  • the pixel definition layer may be disposed on the anode layer and the fourth insulating layer 14, and a pixel opening may be provided on the pixel definition layer, and the pixel opening may expose a portion of the surface of the anode.
  • the organic light emitting layer is at least partially disposed in the pixel opening, and the organic light emitting layer is connected to the anode.
  • the cathode is disposed on the organic light emitting layer, and the cathode is connected to the organic light emitting layer.
  • the organic light emitting layer emits light of corresponding colors when driven by the anode and the cathode.
  • the encapsulation structure layer 104 may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer 103 .
  • the organic light-emitting layer may include at least a hole injection layer, a hole transport layer, a light-emitting layer, and a hole blocking layer stacked on the anode.
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated
  • the hole blocking layer may be a common layer connected together.
  • this embodiment is not limited to this.
  • FIG3 is an equivalent circuit diagram of a pixel circuit.
  • the pixel circuit of this example is a 3T1C structure, which may include three transistors (i.e., a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor Cst.
  • the first transistor T1 may also be referred to as a switch transistor
  • the second transistor T2 may also be referred to as a drive transistor
  • the third transistor T3 may also be referred to as a compensation transistor.
  • the pixel circuit may be electrically connected to a data line DL, a scan line GL, a sensing control line SL, a sensing compensation line SE, a first power line VDD, and a second power line VSS.
  • a parasitic capacitor Ca may be formed between the gate electrode of the first transistor T1 and the gate electrode of the second transistor T2.
  • the gate electrode of the first transistor T1 is electrically connected to the scan line GL
  • the first electrode of the first transistor T1 is connected to the data line DL
  • the second electrode of the first transistor T1 is electrically connected to the gate electrode of the second transistor T2.
  • the first electrode of the second transistor T2 is electrically connected to the first power line PL1
  • the second electrode of the second transistor T2 is electrically connected to the first electrode of the light-emitting element EL.
  • the gate electrode of the third transistor T3 is electrically connected to the sensing control line SL
  • the first electrode of the third transistor T3 is electrically connected to the sensing compensation line SE
  • the second electrode of the third transistor T3 is electrically connected to the second electrode of the second transistor T2.
  • the first plate of the storage capacitor Cst is electrically connected to the gate electrode of the second transistor T2, and the second plate of the storage capacitor Cst is electrically connected to the second electrode of the second transistor T2.
  • the second electrode of the light-emitting element EL is electrically connected to the second power line PL2.
  • the light-emitting element EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).
  • the first transistor T1 may be configured to receive a data voltage transmitted by the data line DL under the control of the scan line GL, so that the gate electrode of the second transistor T2 receives the data voltage.
  • the second transistor T2 may be configured to generate a corresponding current at the second pole under the control of the data voltage received by its gate electrode.
  • the third transistor T3 is configured to extract the threshold voltage Vth and mobility of the second transistor T2 under the control of the sensing control line SL to compensate for the threshold voltage Vth.
  • the storage capacitor Cst may be configured to store the potential of the gate electrode of the second transistor T2.
  • the light emitting element EL is configured to emit light of corresponding brightness in response to the current of the second pole of the second transistor T2.
  • the first power line VDD may continuously provide a high level signal
  • the second power line VSS may continuously provide a low level signal.
  • the first power line VDD provides a first power voltage Vdd
  • the second power line VSS provides a second power voltage Vss.
  • the first transistor T1, the second transistor T2 and the third transistor T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.
  • multiple transistors in a pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors.
  • the active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • oxide thin-film transistor uses oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel namely the LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • LTPS+Oxide LTPO for short
  • the transistors in the pixel circuit shown in Fig. 3 are all N-type transistors.
  • the operation process of the pixel circuit shown in Fig. 3 may include the following stages.
  • the scanning line GL inputs a high level signal
  • the sensing control line SL inputs a high level signal
  • the first transistor T1 is turned on
  • the third transistor T3 is turned on.
  • the data voltage Vdata provided by the data line DL is transmitted to the gate electrode of the second transistor T2. That is, the gate electrode voltage Vg of the second transistor T2 is Vdata.
  • the second electrode voltage Vs of the second transistor T2 is Vsen+ ⁇ V.
  • Vsen is the compensation voltage provided by the sensing compensation line SE
  • ⁇ V is the voltage change of the second electrode of the second transistor T2 caused by the conduction of the second transistor T2 during the data writing stage.
  • the scan line GL inputs a low level signal
  • the sensing control line SL inputs a low level signal.
  • the first transistor T1 is turned off
  • the third transistor T3 is turned off.
  • the second transistor T2 can transfer the first power supply voltage Vdd provided by the first power supply line VDD to the second electrode of the second transistor T2, so as to drive the light emitting element EL to emit light.
  • the second electrode of the first transistor T1 changes from the third power supply voltage Vgh to the fourth power supply voltage Vgl, and this voltage change will produce a voltage coupling effect on the gate electrode of the second transistor T2, namely ⁇ Vp.
  • ⁇ Vp is also affected by the falling edge of the scanning signal provided by the scanning line GL, and the larger the falling edge of the scanning signal, the smaller ⁇ Vp.
  • the gate driving circuit may include a plurality of cascaded gate driving subcircuits.
  • each gate driving subcircuit may be used as a shift register to sequentially pass the scan signal to the next gate driving subcircuit, turn on the first transistor of the pixel circuit row by row, and complete the writing of the data signal.
  • FIG4 is an equivalent circuit diagram of a gate drive subcircuit.
  • the gate drive subcircuit of this example is only a schematic diagram.
  • the gate drive subcircuit may include: a shift unit 22 and an output unit 21.
  • the output unit 21 is electrically connected to the clock signal terminal CLK, the fourth power line VGL, the signal output terminal OUTPUT, the first control node Q, the second control node QA and the third control node QB, and is configured to provide the signal of the clock signal terminal CLK to the signal output terminal OUTPUT under the control of the first control node Q, and to provide the signal of the fourth power line VGL to the signal output terminal OUTPUT under the control of the second control node QA and the third control node QB.
  • the shift unit 22 is electrically connected to the signal input terminal INPUT, the reset signal terminal RESET, the third power line VGH, the first control node Q, the second control node QA and the third control node QB, and is configured to control the potential of the first control node Q, the second control node QA and the third control node QB under the control of the signal input terminal INPUT and the reset signal terminal RESET.
  • the third power line VGH continuously provides a third power voltage Vgh of a high potential
  • the fourth power line VGL continuously provides a third power voltage Vgl of a low potential.
  • the output unit 21 may include: a first output transistor M1, a second output transistor M2, a third output transistor M3, and a first capacitor C1.
  • the gate electrode of the first output transistor M1 is electrically connected to the first control node Q, the first electrode is electrically connected to the clock signal terminal CLK, and the second electrode is electrically connected to the signal output terminal OUTPUT.
  • the gate electrode of the second output transistor M2 is electrically connected to the second control node QA, the first electrode is electrically connected to the fourth power line VGL, and the second electrode is electrically connected to the signal output terminal OUTPUT.
  • the gate electrode of the third output transistor M3 is electrically connected to the third control node QB, the first electrode is electrically connected to the fourth power line VGL, and the second electrode is electrically connected to the signal output terminal OUTPUT.
  • the first plate of the first capacitor C1 is electrically connected to the first control node Q, and the second plate is electrically connected to the signal output terminal OUTPUT.
  • the shift unit 22 may include: a first shift transistor M4, a second shift transistor M5, a third shift transistor M6, a fourth shift transistor M7, and a fifth shift transistor M8.
  • the gate electrode and the first electrode of the first shift transistor M4 are electrically connected to the signal input terminal INPUT, and the second electrode is electrically connected to the first control node Q.
  • the gate electrode of the second shift transistor M5 is electrically connected to the third control node QB, the first electrode is electrically connected to the fourth power line VGL, and the second electrode is electrically connected to the first control node Q.
  • the third control node QB is electrically connected to the reset signal terminal RESET.
  • the gate electrode of the third shift transistor M6 is electrically connected to the second control node QA, the first electrode is electrically connected to the fourth power line VGL, and the second electrode is electrically connected to the first control node Q.
  • the gate electrode of the fourth shift transistor M7 is electrically connected to the first control node Q, the first electrode is electrically connected to the fourth power line VGL, and the second electrode is electrically connected to the second control node QA.
  • the gate electrode and the first electrode of the fifth shift transistor M8 are electrically connected to the third power line VGH, and the second electrode is electrically connected to the second control node QA.
  • Figure 5 is a working timing diagram of the gate driving subcircuit shown in Figure 4. As shown in Figures 4 and 5, the working process of the gate driving subcircuit includes the following stages.
  • the signal at the signal input terminal INPUT is at a high level
  • the input signals at the reset signal terminal RESET and the clock signal terminal CLK are both at a low level
  • the output signal at the signal output terminal OUTPUT is a low level signal.
  • the signal at the signal input terminal INPUT is at a high level
  • the first shift transistor M4 is turned on, the potential of the first control node Q is pulled up, and the first capacitor C1 is charged.
  • the third power line VGH continues to provide a high-level third power supply voltage Vgh, and the fifth shift transistor M8 is turned on, since the potential of the first control node Q is at a high level, the fourth shift transistor M7 is turned on, and the potential of the second control node QA is pulled down, and the third shift transistor M6 is not turned on, and the potential of the first control node Q will not be pulled down.
  • the input signal of the clock signal terminal CLK is at a high level, and the input signals of the signal input terminal INPUT and the reset signal terminal RESET are at a low level.
  • the signal of the signal input terminal INPUT is at a low level, the first shift transistor M4 is turned off, and the signal of the clock signal terminal CLK becomes a high level. Due to the bootstrap effect of the first capacitor C1, the potential of the first control node Q continues to be pulled high, and the high level of the first control node Q turns on the first output transistor M1, and the signal output terminal OUTPUT outputs a high level signal of the clock signal terminal CLK. In addition, the increase in the potential of the first control node Q improves the conduction capability of the first output transistor M1, ensuring pixel charging.
  • the fourth shift transistor M7 is still turned on, pulling down the potential of the second control node QA, the third shift transistor M6 and the second output transistor M2 are not turned on, and the potential of the first control node Q and the signal output terminal OUTPUT will not be pulled down.
  • the input signal of the reset signal terminal RESET is at a high level
  • the input signals of the signal input terminal INPUT and the clock signal terminal CLK are at a low level
  • the output signal of the signal output terminal OUTPUT is at a low level.
  • the input signal of the reset signal terminal RESET is at a high level
  • the second shift transistor M5 and the third output transistor M3 are turned on
  • the potential of the first control node Q is pulled down to the low level provided by the fourth power line VGL
  • the third output transistor M3 is turned on
  • the potential of the signal output terminal OUTPUT is pulled down to the low level of the fourth power line VGL.
  • the fourth shift transistor M7 Since the potential of the first control node Q is at a low level, the fourth shift transistor M7 is turned off, the potential of the second control node QA is at a high level, the third shift transistor M6 is turned on, and the potential of the first control node Q is continuously pulled down to reduce noise.
  • the second output transistor M2 is turned on, and the potential of the signal output terminal OUTPUT is continuously pulled down to the low level of the fourth power line VGL to reduce noise.
  • the input signal of the clock signal terminal CLK is at a high level. Since the potential of the first control node Q is at a low level, the first output transistor M1 is turned off, and the output signal of the signal output terminal OUTPUT is at a low level.
  • the fourth shift transistor M7 is turned off, the potential of the second control node QA is at a high level, the third shift transistor M6 is turned on, the potential of the first control node Q is continuously pulled down to reduce noise, the second output transistor M2 is turned on, and the potential of the signal output terminal OUTPUT is continuously pulled down to reduce noise.
  • the input signal of the clock signal terminal CLK is at a low level. Since the potential of the first control node Q is at a low level, the first output transistor M1 is turned off, and the output signal of the signal output terminal OUTPUT is at a low level.
  • the fourth shift transistor M7 is turned off, the potential of the second control node QA is at a high level, the third shift transistor M6 is turned on, and the potential of the first control node Q is continuously pulled down to reduce noise.
  • the second output transistor M2 is turned on, and the potential of the signal output terminal OUTPUT is continuously pulled down to reduce noise.
  • the gate driving sub-circuit of this stage continues the fourth stage S4 and the fifth stage S5 until the signal input terminal INPUT receives a high level signal again.
  • the signal at the signal input terminal INPUT is a pulse signal, which is high only in the first stage S1;
  • the output signal at the signal output terminal OUTPUT is a pulse signal, which is high only in the second stage S2;
  • the signal at the reset signal terminal RESET is a pulse signal, which is high only in the third stage S3.
  • FIG6 is a schematic diagram of a gate drive circuit.
  • the gate drive circuit may include a plurality of gate drive sub-circuits.
  • the gate drive circuit may be electrically connected to a plurality of clock signal lines (e.g., including a first clock signal line CLK1 to a sixth clock signal line CLK6).
  • a plurality of clock signal lines e.g., including a first clock signal line CLK1 to a sixth clock signal line CLK6
  • this embodiment is not limited to this.
  • the gate drive circuit may be electrically connected to four clock signal lines or eight clock signal lines.
  • the clock signal end of the Nth level gate driver subcircuit GOA(N) can be electrically connected to the first clock signal line CLK1
  • the clock signal end of the N+1th level gate driver subcircuit GOA(N+1) can be electrically connected to the second clock signal line CLK2
  • the clock signal end of the N+2th level gate driver subcircuit GOA(N+2) can be electrically connected to the third clock signal line CLK3
  • the clock signal end of the N+3th level gate driver subcircuit GOA(N+3) can be electrically connected to the fourth clock signal line CLK 4
  • the clock signal end of the N+4th gate driver subcircuit GOA (N+4) can be electrically connected to the fifth clock signal line CLK5
  • the clock signal end of the N+5th gate driver subcircuit GOA (N+5) can be electrically connected to the sixth clock signal line CLK6
  • the clock signal end of the N+6th gate driver subcircuit GOA (N+6) can be electrically connected to the first clock signal line
  • the six gate driver subcircuits can be used as a group and electrically connected to the six clock signal lines (i.e., the first clock signal line CLK1 to the sixth clock signal line CLK6). Every six gate driver subcircuits can be used as a cycle, and so on.
  • N is a positive integer.
  • the output signal of the signal output terminal OUTPUT of each level of the gate driver subcircuit can be provided as a scanning signal to the pixel circuit of a row of sub-pixels in the display area.
  • the signal input terminal of the Nth level gate driver subcircuit GOA(N) can be electrically connected to the start signal line STV.
  • This example does not limit the connection relationship between the gate driver subcircuits.
  • the output signal of the signal output terminal of the N+1th level gate driver subcircuit can be provided to the signal input terminal of the N+2th level gate driver subcircuit, and can also be provided to the reset signal terminal of the Nth level gate driver subcircuit.
  • the pulse periods of the clock signals provided by the multiple clock signal lines electrically connected to the gate drive circuit may be the same.
  • the pulse signal of the clock signal provided by the previous clock signal line may be generated at the same time as the pulse signal of the clock signal provided by the next clock signal line ends.
  • the first pulse signal of the first clock signal line is generated first, the first pulse signal of the second clock signal line is generated at the same time as the first pulse signal ends, the first pulse signal of the third clock signal line is generated at the same time as the first pulse signal of the second clock signal line ends, the first pulse signal of the fourth clock signal line is generated at the same time as the first pulse signal of the fourth clock signal line ends, the first pulse signal of the fifth clock signal line is generated at the same time as the first pulse signal of the fifth clock signal line ends, the first pulse signal of the sixth clock signal line is generated at the same time as the first pulse signal of the sixth clock signal line ends, and the second pulse signal of the first clock signal line is generated at the same time as the first pulse signal of the sixth clock signal line, and so on.
  • the clock signal line can be electrically connected to the gate drive circuit through a connecting line.
  • the connecting line is usually arranged according to the shortest routing path.
  • the length of the connecting line corresponding to the clock signal line close to the gate drive circuit is shorter, and the corresponding line resistance is smaller.
  • a plurality of connecting lines connecting different clock signal lines are grouped together. In a group of connecting lines, the length of each connecting line is different.
  • the length of the connecting line corresponding to the clock signal line far away from the gate drive circuit is longer, and the corresponding line resistance is larger.
  • the gate drive circuit shown in FIG6 which is electrically connected to six clock signal lines (e.g., the first clock signal line CK1 to the sixth clock signal line CLK6), the line segment resistance of the connecting line electrically connected to two adjacent clock signal lines is ⁇ R, and the difference between the connecting line electrically connected to the first clock signal line CLK1 and the connecting line electrically connected to the sixth clock signal line CLK6 is 5 ⁇ R.
  • a boundary line caused by brightness difference will be generated at the junction of the sub-pixel row connected to the gate drive sub-circuit (e.g., GOA(N+6)) electrically connected to the first clock signal line CLK1 and the sub-pixel row connected to the gate drive sub-circuit (e.g., GOA(N+7)) electrically connected to the sixth clock signal line CLK6.
  • the more clock signal lines are electrically connected to the gate drive circuit the more obvious the above situation is.
  • the present embodiment provides a display panel, which performs load compensation on the connection lines connected between the clock signal lines and the gate driving circuit so that the loads of multiple connection lines are roughly the same, thereby ensuring the consistency of the falling edges of multiple output signals of the gate driving circuit, thereby ensuring the display effect of the display panel.
  • the present embodiment provides a display panel, comprising: a substrate, and a gate drive circuit, a plurality of clock signal lines and a plurality of connecting lines arranged on the substrate.
  • the plurality of clock signal lines are located on one side of the gate drive circuit along a first direction and are arranged in sequence.
  • Each connecting line electrically connects the gate drive circuit and a clock signal line.
  • At least one connecting line includes a load adjustment unit, which is configured to compensate for the load difference between different clock signal lines.
  • the load adjustment unit of at least one connecting line at least partially overlaps the orthographic projection of at least one clock signal line on the substrate; or, the plurality of connecting lines all include a load adjustment unit, and the load adjustment units of the plurality of connecting lines are located on a side of the plurality of clock signal lines away from the gate drive circuit, or on a side of the plurality of clock signal lines close to the gate drive circuit, or in the interval area between two adjacent clock signal lines.
  • the orthographic projection of the load adjustment portion of at least one connecting line on the substrate may at least partially overlap with the orthographic projection of the clock signal line connected to the load adjustment portion on the substrate.
  • the orthographic projection of the load adjustment portion of at least one connecting line on the substrate may be located within the orthographic projection range of the clock signal line connected to the load adjustment portion on the substrate.
  • the orthographic projection of the load adjustment parts of the multiple connection lines on the substrate may not overlap with the orthographic projection of the multiple clock signal lines on the substrate, and the setting positions of the load adjustment parts of the multiple connection lines may be the same relative to the gate drive circuit and the multiple clock signal lines.
  • the load adjustment parts of the multiple connection lines may all be located on the side of the multiple clock signal lines away from the gate drive circuit; or, the load adjustment parts of the multiple connection lines may all be located on the side of the multiple clock signal lines close to the gate drive circuit; or, the load adjustment parts of the multiple connection lines may all be located in the interval area between two adjacent clock signal lines.
  • this example can not only compensate for the load differences between different clock signal lines, but also avoid interference with the clock signal lines by setting all load adjustment parts in the spacing area between two adjacent clock signal lines. It can also avoid the length of the connecting line being too large, and it can also help save routing space. It only needs to increase the spacing area between the two adjacent signal lines.
  • the orthographic projections of the load adjustment parts of the plurality of connection lines on the substrate may overlap with the orthographic projections of the same clock signal line on the substrate. This example can not only compensate for the load differences between different clock signal lines, but also reduce interference with the clock signal line and help save routing space.
  • FIG7 is a partial schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • the gate drive circuit 40 is electrically connected to six clock signal lines, for example, including: a first clock signal line CLK1, a second clock signal line CLK2, a second clock signal line CLK3, a third clock signal line CLK4, a fourth clock signal line CLK4, a fifth clock signal line CLK5, and a sixth clock signal line CLK6.
  • the six clock signal lines may extend along the second direction Y and be located along the first direction X on the side of the gate drive circuit 40 away from the display area.
  • the plurality of gate drive sub-circuits included in the gate drive circuit 40 may be arranged in sequence along the second direction Y.
  • a plurality of clock signal lines may be located along the first direction on the side of the gate drive circuit close to the display area; or some of the plurality of clock signal lines may be located on the side of the gate drive circuit away from the display area, and another portion of the signal lines may be located on the side of the gate drive circuit close to the display area.
  • the lengths of the plurality of clock signal lines along the first direction X may be substantially the same.
  • the spacings between adjacent clock signal lines ie, the spacing distances along the first direction X) may be substantially the same.
  • a plurality of clock signal lines may be electrically connected to the gate drive circuit 40 through a plurality of connecting lines 51, respectively.
  • the two ends of a connecting line 51 may be electrically connected to a clock signal line and a clock signal end of a gate drive subcircuit of the gate drive circuit, respectively.
  • the clock signal line and the connecting line may be located in different film layers.
  • the clock signal line may be disposed in the same layer as the first source and drain metal layer of the display area
  • the connecting line may be disposed in the same layer as the first gate metal layer or the second gate metal layer of the display area
  • the clock signal line may be electrically connected to the connecting line through a via provided in the insulating layer.
  • each connection line 51 may include: a first connection portion 511, a load adjustment portion 512, and a second connection portion 513 connected in sequence.
  • One end of the first connection portion 511 is electrically connected to a corresponding clock signal line, and the other end is connected to the load adjustment portion 512.
  • One end of the second connection portion 513 is electrically connected to a clock signal end of a gate drive subcircuit of the gate drive circuit 40, and the other end is electrically connected to the other end of the load adjustment portion 512.
  • the orthographic projection of the first connection portion 511 on the substrate may be a rectangle, for example, it may be electrically connected to the corresponding clock signal line through a via hole opened on the insulating layer.
  • the second connection portion 513 may be a straight line segment extending along the first direction X.
  • Six connecting lines 51 that are electrically connected to six clock signal lines respectively and arranged continuously along the second direction Y are taken as a group of connecting lines.
  • the shapes and sizes of the first connecting parts 511 of the six connecting lines 51 can be substantially the same, the lengths of the second connecting parts 513 of the six connecting lines 51 along the first direction X can be different, and the lengths of the load adjustment parts 512 of the six connecting lines 51 along the second direction Y can be substantially the same.
  • the load adjustment portion 512 of each connection line 51 may include: a first sub-connection portion 5121, a second sub-connection portion 5122, a third sub-connection portion 5123, and a fourth sub-connection portion 5124.
  • the first sub-connection portion 5121 and the third sub-connection portion 5123 may both extend along the second direction Y, and the second sub-connection portion 5122 and the fourth sub-connection portion 5124 may both extend along the first direction X.
  • the second sub-connection portion 5122 and the fourth sub-connection portion 5124 may be connected between the first sub-connection portion 5121 and the third sub-connection portion 5123.
  • first sub-connection portion 5121 may be electrically connected to the first connection portion 511, and the other end may be electrically connected to one end of the fourth sub-connection portion 5124; one end of the third sub-connection portion 5123 may be electrically connected to the second connection portion 513, and the other end may be electrically connected to the other end of the fourth sub-connection portion 5124.
  • the second sub-connection portion 5122 may be located on a side of the fourth sub-connection portion 5124 close to the first connection portion 511.
  • the first sub-connection portion 5121 may include a first sub-segment 5121a and a second sub-segment 5121b, the two ends of the first sub-segment 5121a are electrically connected to the first connection portion 511 and the second sub-connection portion 5122, respectively, and the two ends of the second sub-segment 5121b may be electrically connected to the second sub-connection portion 5122 and the fourth sub-connection portion 5124, respectively.
  • the third sub-connection portion 5123 may include a third sub-segment 5123a and a fourth sub-segment 5123b, the two ends of the third sub-segment 5123a are electrically connected to the second connection portion 512 and the second sub-connection portion 5122, respectively, and the two ends of the fourth sub-segment 5123b may be electrically connected to the second sub-connection portion 5122 and the fourth sub-connection portion 5124, respectively.
  • the lengths of the first sub-connection portions 5121 of the load adjustment portions 512 of the plurality of connection lines along the second direction Y may be substantially the same, the lengths of the third sub-connection portions 5123 along the second direction Y may be substantially the same, and the lengths of the second sub-connection portions 5122 and the fourth sub-connection portions 5124 along the first direction X may be substantially the same.
  • the cross-sectional area of each portion of the connection line in a direction perpendicular to the display panel may be substantially the same.
  • the length of the first sub-connection portion 5121 of the load adjustment portion 512 of a connection line 51 along the second direction Y may be greater than the length of the third sub-connection line 5123 along the second direction Y.
  • the lengths of the first sub-segments 5121a of the first sub-connection parts 5121 of the load adjustment parts 512 of the plurality of connection lines along the second direction Y may be different, and the lengths of the third sub-segments 5123a of the third sub-connection parts 5123 along the second direction Y may be different.
  • the distances between the second sub-connection parts 5122 and the fourth sub-connection parts 5124 of the load adjustment parts 512 of the plurality of connection lines may be different.
  • the distance between the second sub-connection parts 5122 and the fourth sub-connection parts 5124 of the load adjustment parts 512 of the connection lines that are electrically connected to the clock signal lines of the gate driving circuit 40 is smaller than the distance between the second sub-connection parts 5122 and the fourth sub-connection parts 5124 of the load adjustment parts 512 of the connection lines that are electrically connected to the clock signal lines of the gate driving circuit 40.
  • the second sub-connection portion 5122 of the load adjustment portion 512 of the connection line 51 electrically connected to the first clock signal line CLK1 may be colinear with the second connection portion 513, the spacing between the two in the second direction Y may be 0, and the length of the third sub-segment 5123a of the third sub-connection portion 5123 of the load adjustment portion 512 may be 0.
  • the distance between the second sub-connection portion 5122 and the fourth sub-connection portion 5124 of the load adjustment portion 512 of the connection line 51 electrically connected to the sixth clock signal line CLK6 may be smaller than the distance between the second sub-connection portion 5122 and the second connection portion 513, and the length of the third sub-segment 5123a of the third sub-connection portion 5123 of the load adjustment portion 512 may be larger than the length of the fourth sub-segment 5123b.
  • the wiring resistance R ⁇ L/S, where R is the resistance value, ⁇ is the resistivity, L is the equivalent length of the wiring, and S is the cross-sectional area of the wiring. It can be seen that when the resistivity and cross-sectional area of multiple parts of multiple connecting lines are the same, the resistance size is determined by its equivalent length. By setting the equivalent lengths of multiple connecting lines to be consistent, the resistance of multiple connecting lines can be made consistent.
  • the equivalent length of each connecting line can be the length of the first sub-segment 5121a of the first sub-connection part 5121 of the load adjustment part 512 along the second direction Y, the length of the second sub-connection part 5122 along the first direction X, the length of the third sub-segment 5123a of the third sub-connection part 5123 along the second direction Y, and the length of the second connection part 513 along the first direction X.
  • connection lines connected to different clock signal lines can be compensated for resistance, so that the resistance size of the connection lines connected to different clock signal lines is basically consistent, and the falling edge difference of the output signal of the gate drive circuit caused by the resistance difference of the connection line is improved.
  • the orthographic projection of the first connection portion 511 and the load adjustment portion 512 of each connection line 51 on the substrate may overlap with the orthographic projection of the connected clock signal line on the substrate, for example, being located within the orthographic projection range of the connected clock signal line on the substrate.
  • the orthographic projection of the second connection portion 513 of the connection line 51 on the substrate may overlap with the orthographic projection of at least one clock signal line on the substrate.
  • the overlapping areas of the orthographic projections of the load adjustment portions 512 of multiple connection lines 51 on the substrate and the clock signal line may be substantially the same, so that the parasitic capacitances between the multiple connection lines 51 and the clock signal line may be substantially the same.
  • the display panel of this example uses a load adjustment unit to compensate for the length differences of different connection lines caused by the different distances between multiple clock signal lines and the gate drive circuit, so that the resistance of multiple connection lines can be roughly the same, improving the falling edge differences of the output signal of the gate drive circuit caused by the resistance differences of the connection lines.
  • the positive projection of the load adjustment unit of the multiple connection lines on the substrate is located within the positive projection range of the connected clock signal line on the substrate, and there is no need to increase the layout space of the load adjustment unit, the occupied space of the gate drive circuit will not be increased, the range of the frame area will not be increased, and there will be no interference with the routing except the clock signal line.
  • FIG8 is another partial schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • each connection line 51 may include: a first connection portion 511, a load adjustment portion 512, and a second connection portion 513 connected in sequence.
  • the first connection portion 511 may include: a first connection block 5111 and a first connection bar 5112 connected to each other.
  • the first connection block 5111 is electrically connected to the corresponding clock signal line.
  • the orthographic projection of the first connection block 5111 on the substrate may be a rectangle, and overlaps with the orthographic projection of the connected clock signal line on the substrate, for example, located within the orthographic projection range of the connected clock signal line on the substrate.
  • the first connection bar 5112 may be a strip structure extending along the first direction X, and is electrically connected to one end of the first sub-connection portion 5121 of the load adjustment portion 512.
  • the load adjustment portion 512 of the plurality of connection lines 51 may be located on a side of the six clock signal lines away from the gate driving circuit 40 in the first direction X, for example, the load adjustment portion 512 is adjacent to the first clock signal line CLK1.
  • the lengths of the third connection portions 513 of the plurality of connection lines 51 along the first direction X may be substantially the same.
  • each connection line 51 may be the sum of the length of the first connection bar 5112 of the first connection portion 511 along the first direction X, the length of the first sub-segment 5121a of the first sub-connection portion 5121 of the load adjustment portion 512 along the second direction Y, the length of the second sub-connection portion 5122 along the first direction X, the length of the third sub-segment 5123a of the third sub-connection portion 5123 along the second direction Y, and the length of the second connection portion 513 along the first direction X.
  • the length of the first connection bar 5112 of the first connection portion 511 of the first clock signal line CLK1 is shorter, and the winding length of the load adjustment portion 512 is longer; the length of the first connection bar 5112 of the first connection portion 511 of the sixth clock signal line CLK6 is longer, and the winding length of the load adjustment portion 512 is shorter.
  • the display panel of this example utilizes the winding structure of the load adjustment unit located on the side of the multiple clock signal lines away from the gate drive circuit to compensate for the length difference of different connection lines caused by the different distances between the multiple clock signal lines and the gate drive circuit, so that the resistance of the multiple connection lines can be roughly the same, and the difference in the falling edge of the output signal of the gate drive circuit caused by the resistance difference of the connection lines is improved.
  • the load adjustment unit of the multiple connection lines is located on the side of the multiple clock signal lines away from the gate drive circuit, which can reduce the space occupied by the wiring.
  • the length of the third sub-connection part 5123 of the load adjustment unit of the multiple connection lines along the second direction Y is roughly the same, which can make the side area of the connection line consistent with the adjacent clock signal line (i.e., the first clock signal line CLK1), and ensure that the lateral capacitance between the multiple connection lines and the adjacent clock signal lines is consistent.
  • the load adjustment unit of the multiple connection lines can omit the fourth sub-connection part and the second sub-segment of the first sub-connection part.
  • FIG9 is another partial schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • each connection line 51 may include: a first connection portion 511, a load adjustment portion 512, and a second connection portion 513 connected in sequence.
  • the first connection portion 511 may include: a first connection block 5111 and a first connection bar 5112 connected to each other.
  • the load adjustment portion 512 of the plurality of connection lines 51 may be located on a side of the six clock signal lines close to the gate drive circuit 40.
  • the load adjustment portion 512 of the plurality of connection lines 51 is located between the six clock signal lines and the gate drive circuit 40, for example, adjacent to the sixth clock signal line CLK6.
  • the second connection portions 513 of the plurality of connection lines 51 extend along the first direction X, and the lengths along the first direction X are substantially the same.
  • the first connection blocks 5111 of the first connection portions 511 of the plurality of connection lines 51 are substantially the same in shape and size.
  • the first connection bars 5112 of the first connection portions 511 of the plurality of connection lines 51 extend along the first direction X, and the lengths along the first direction X are different.
  • the length of the first connection bar 5112 of the first connection portion 511 of the connection line 51 electrically connected to the clock signal line close to the gate driving circuit along the first direction X is less than the length of the first connection bar 5112 of the first connection portion 511 of the connection line 51 electrically connected to the clock signal line far from the gate driving circuit along the first direction X.
  • the length of the first connection bar 5112 of the first connection portion 511 of the connection line 51 electrically connected to the sixth clock signal line CLK6 along the first direction X is the smallest, and the length of the first connection bar 5112 of the first connection portion 511 of the connection line 51 electrically connected to the first clock signal line CLK1 along the first direction X is the largest.
  • This example uses a load adjustment unit located between the gate drive circuit and multiple clock signal lines to compensate for the length differences of different connection lines caused by the different distances between the multiple clock signal lines and the gate drive circuit, so that the resistances of the multiple connection lines can be roughly the same, improving the falling edge differences of the output signal of the gate drive circuit caused by the resistance differences of the connection lines.
  • the load adjustment units of the multiple connection lines between the multiple clock signal lines and the gate drive circuit can be increased, thereby reducing the impact of static electricity caused by the excessive length of the clock signal lines on the transistors in the gate drive circuit.
  • FIG10 is another partial schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • each connection line 51 may include: a first connection portion 511, a load adjustment portion 512, and a second connection portion 513 connected in sequence.
  • the orthographic projections of the first connection portion 511 and the load adjustment portion 512 of each connection line 51 on the substrate may overlap with the orthographic projections of the connected clock signal line on the substrate, for example, being located within the orthographic projection range of the connected clock signal line on the substrate.
  • the orthographic projection of the load adjustment portion 512 on the substrate may be rectangular.
  • the sizes of the load adjustment portions 512 of different connection lines 51 may be different.
  • the overlapping areas of the orthographic projections of the load adjustment portions 512 of different connection lines 51 on the substrate and the orthographic projections of the connected clock signal lines on the substrate may be different.
  • the overlapping area of the orthographic projection of the load adjustment portion 512 of the connection line 51 electrically connected to the clock signal line far away from the gate driving circuit 40 and the orthographic projection of the clock signal line on the substrate may be greater than the overlapping area of the orthographic projection of the load adjustment portion 512 of the connection line 51 electrically connected to the clock signal line close to the gate driving circuit 40 and the orthographic projection of the clock signal line on the substrate.
  • the overlapping area of the orthographic projection of the load adjustment portion 512 of the connection line 51 electrically connected to the first clock signal line CLK1 and the orthographic projection of the first clock signal line CLK1 on the substrate is the largest, and the overlapping area of the orthographic projection of the load adjustment portion 512 of the connection line 51 electrically connected to the sixth clock signal line CLK6 and the orthographic projection of the sixth clock signal line CLK6 on the substrate is the smallest.
  • the load adjustment parts 512 of the plurality of connection lines 51 may have substantially the same length along the first direction X, and may have different lengths along the second direction Y.
  • the area of the load adjustment part 512 may be increased, and the line resistance of the connection line 51 may be reduced, thereby reducing the loss of the clock signal.
  • FIG. 11 is another partial schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • each connection line 51 may include: a first connection portion 511, a load adjustment portion 512, and a second connection portion 513 connected in sequence.
  • the first connection portion 511 may include: a first connection block 5111 and a first connection bar 5112 connected to each other.
  • the load adjustment portions 512 of the plurality of connection lines 51 overlap with the orthographic projection of the first clock signal line CLK1 on the substrate in their orthographic projections on the substrate, for example, they are located within the orthographic projection range of the first clock signal line CLK1 on the substrate.
  • this embodiment is not limited to this.
  • the orthographic projection of the load adjustment portions 512 of the plurality of connection lines 51 on the substrate may overlap with the orthographic projection of one or more of the second clock signal line CLK2 to the sixth clock signal line CLK6 on the substrate.
  • FIG. 12 is another partial schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • each connection line 51 may include: a first connection portion 511, a load adjustment portion 512, and a second connection portion 513 connected in sequence.
  • the first connection portion 511 may include: a first connection block 5111 and a first connection bar 5112 connected to each other.
  • the load adjustment portion 512 of the plurality of connection lines 51 may be located between the third clock signal line CLK3 and the fourth clock signal line CLK4.
  • first connection bar 5112 of the first connection portion 511 of the connection line 51 connected to the first clock signal line CLK1 to the third clock signal line CLK3 may extend along the first direction X to the side close to the gate drive circuit 40
  • first connection bar 5112 of the first connection portion 511 of the connection line 51 connected to the fourth clock signal line CLK4 to the sixth clock signal line CLK6 may extend along the first direction X to the side away from the gate drive circuit 40.
  • this embodiment is not limited to this.
  • the load regulating sections 512 of the plurality of connection lines 51 may all be located between the first clock signal line CLK1 and the second clock signal line CLK2, or may be located between the second clock signal line CLK2 and the third clock signal line CLK3, or may be located between the fourth clock signal line CLK4 and the fifth clock signal line CLK5, or may be located between the fifth clock signal line CLK5 and the sixth clock signal line CLK6.
  • the load regulating section of at least one of the plurality of connection lines may be located between the first clock signal line CLK1 and the second clock signal line CLK2, and the load regulating section of at least one of the connection lines may be located between the fifth clock signal line CLK5 and the sixth clock signal line CLK6.
  • the load regulating section may be provided between the first clock signal line CLK1 and the second clock signal line CLK2, between the third clock signal line CLK3 and the fourth clock signal line CLK4, and between the fifth clock signal line CLK5 and the sixth clock signal line CLK6.
  • FIG. 13 is another partial schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • each connection line 51 may include: a first connection portion 511, a load adjustment portion 512, and a second connection portion 513 connected in sequence.
  • the first connection portion 511 may include: a first connection block 5111 and a first connection bar 5112 connected to each other.
  • the load adjustment portion 512 may include: a first sub-connection portion 5121, a second sub-connection portion 5122, and a third sub-connection portion 5123 connected in sequence.
  • the first sub-connection portion 5121 and the third sub-connection portion 5123 extend along the second direction Y, the first sub-connection portion 5121 is connected to the first connection bar 5112 of the first connection portion 511, and the third sub-connection portion 5123 is connected to the second connection portion 513.
  • the second sub-connection portion 5122 extends along the first direction X and is connected between the first sub-connection portion 5121 and the third sub-connection portion 5123.
  • the load regulating portion 512 of the plurality of connection lines 51 is located on a side of the plurality of clock signal lines away from the gate driving circuit 40.
  • the load regulating portion 512 of the plurality of connection lines 51 is adjacent to the first clock signal line CLK1.
  • the display panel of this example utilizes the winding structure of the load adjustment unit located on the side of the multiple clock signal lines away from the gate driving circuit to compensate for the length differences of different connecting lines caused by the different distances between the multiple clock signal lines and the gate driving circuit, so that the resistances of the multiple connecting lines can be roughly the same, thereby improving the falling edge differences of the output signal of the gate driving circuit caused by the resistance differences of the connecting lines.
  • the load adjustment unit for a group of connecting lines may adopt at least two of the settings in Figures 7 to 13.
  • the load adjustment unit of at least one connecting line in a group of connecting lines may adopt the setting shown in Figure 7, and the load adjustment unit of at least one connecting line may adopt the setting shown in any one of Figures 8 to 13.
  • the load adjustment unit of at least one connecting line in a group of connecting lines may adopt the setting shown in Figure 10
  • the load adjustment units of the remaining connecting lines may adopt the setting shown in any one of Figures 7 to 9 and Figures 11 to 13.
  • the load adjustment unit of at least one connecting line in a group of connecting lines may adopt the setting shown in Figure 8, and the load adjustment unit of at least one connecting line may adopt the setting shown in any one of Figures 9 to 13. This embodiment is not limited to this.
  • FIG14 is a schematic diagram of a gate drive circuit of at least one embodiment of the present disclosure.
  • the gate drive circuit includes a plurality of cascaded gate drive sub-circuits.
  • the gate drive circuit may be electrically connected to a plurality of clock signal lines (e.g., including a first clock signal line CLK1 to a sixth clock signal line CLK6).
  • the clock signal end of the Nth level gate driver subcircuit GOA (N) can be electrically connected to the first clock signal line CLK1
  • the clock signal end of the N+1th level gate driver subcircuit GOA (N+1) can be electrically connected to the second clock signal line CLK2
  • the clock signal end of the N+2th level gate driver subcircuit GOA (N+2) can be electrically connected to the third clock signal line CLK3
  • the clock signal end of the N+3th level gate driver subcircuit GOA (N+3) can be electrically connected to the fourth clock signal line CLK4
  • the clock signal end of the N+4th level gate driver subcircuit GOA (N+4) can be electrically connected to the fifth clock signal line CLK5
  • the clock signal end of the N+5th level gate driver subcircuit GOA (N+5) can be electrically connected to the sixth clock signal line CLK6.
  • gate driver subcircuits can be used as a group and electrically connected to six clock signal lines (i.e., the first clock signal line CLK1 to the sixth clock signal line CLK6) respectively. Every six gate driver subcircuits can be used as a cycle, and so on.
  • N is a positive integer.
  • each gate driver subcircuit may include at least a first output transistor M1, and the first output transistor M1 may be configured to provide a clock signal to a signal output terminal OUTPUT of the gate driver subcircuit.
  • an equivalent circuit of the gate driver subcircuit may be as shown in FIG4, and the first output transistor M1 may provide a clock signal provided by the clock signal terminal CLK to the signal output terminal OUTPUT under the control of the first control node Q.
  • the size of the first output transistor of the gate driver subcircuit electrically connected to the clock signal line far from the gate driver circuit can be larger than the size of the first output transistor of the gate driver subcircuit electrically connected to the clock signal line close to the gate driver circuit.
  • the first clock signal line CLK1 to the sixth clock signal line CLK6 are close to the gate driver circuit in sequence, wherein the first clock signal line CLK1 is farthest from the gate driver circuit and the sixth clock signal line CLK6 is closest to the gate driver circuit.
  • the size of the first output transistor of the gate driver subcircuit electrically connected to the first clock signal line CLK1 to the sixth clock signal line CLK1 can be gradually reduced.
  • the size of the first output transistor M1 of the gate driver subcircuit GOA(N) may be larger than the size of the first output transistor M1 of the gate driver subcircuit GOA(N+1), the size of the first output transistor M1 of the gate driver subcircuit GOA(N+1) may be larger than the size of the first output transistor M1 of the gate driver subcircuit GOA(N+2), the size of the first output transistor M1 of the gate driver subcircuit GOA(N+2) may be larger than the size of the first output transistor M1 of the gate driver subcircuit GOA(N+3), the size of the first output transistor M1 of the gate driver subcircuit GOA(N+3) may be larger than the size of the first output transistor M1 of the gate driver subcircuit GOA(N+4), the size of the first output transistor M1 of the gate driver subcircuit GOA(N+4) may be larger than the size of the first output transistor M1 of the gate driver subcircuit GOA(N+5).
  • the size of the first output transistor M1 of the gate driver subcircuit GOA(N) may be the largest, and the size of the first output transistor M1 of the gate driver subcircuit GOA(N+5) may be the smallest.
  • the greater the resistance of the connecting line between the gate driver subcircuit and the clock signal line the larger the size of the first output transistor of the gate driver subcircuit can be, thereby improving the falling edge difference of the output signal of the gate driver circuit caused by the increased resistance of the connecting line.
  • the size of the first output transistor may be a width-to-length ratio (W/L) of an active layer of the first output transistor, wherein the length of the active layer of the first output transistor may be a length of the active layer in an extension direction, and the width may be a length of the active layer in a direction perpendicular to the extension direction within an extension plane.
  • W/L width-to-length ratio
  • the difference in the falling edge of the output signal of the gate drive circuit caused by the difference in resistance of the connecting lines can be improved by adjusting the size of the first output transistor of the gate drive sub-circuit.
  • FIG15 is a schematic diagram of a clock signal of at least one embodiment of the present disclosure.
  • the voltage amplitude of the clock signal provided by the first clock signal line CLK1 is Vk1
  • the voltage amplitude of the clock signal provided by the second clock signal line CLK2 is Vk2
  • the voltage amplitude of the clock signal provided by the third clock signal line CLK3 is Vk3
  • the voltage amplitude of the clock signal provided by the fourth clock signal line CLK4 is Vk4
  • the voltage amplitude of the clock signal provided by the fifth clock signal line CLK5 is Vk5
  • the voltage amplitude of the clock signal provided by the sixth clock signal line CLK6 is Vk6.
  • the voltage amplitude of the clock signal in this example refers to the absolute value of the difference between the high potential voltage and the low potential voltage of the clock signal.
  • the voltage amplitude of the clock signal can be achieved by adjusting at least one of the high potential voltage and the low potential voltage of the clock signal. For example, the voltage amplitude is increased by increasing the high potential voltage and keeping the low potential voltage unchanged; or, the voltage amplitude is increased by reducing the low potential voltage and keeping the high potential voltage unchanged; or, the voltage amplitude is increased by increasing the high potential voltage and reducing the low potential voltage. This embodiment is not limited to this.
  • the voltage amplitude of the clock signal transmitted by the different clock signal lines is adjusted to improve the difference in the falling edge of the output signal of the gate drive circuit caused by the difference in resistance of the connection lines.
  • the voltage amplitude of the clock signal transmitted by the first clock signal line CLK1 to the voltage amplitude of the clock signal transmitted by the sixth clock signal line CLK6 can be gradually reduced.
  • the voltage amplitude Vk1 of the clock signal transmitted by the first clock signal line CLK1 can be the largest, and the voltage amplitude Vk6 of the clock signal transmitted by the sixth clock signal line CLK6 can be the smallest.
  • the above embodiments may be combined.
  • the load adjustment portion of the connecting wire and the size adjustment of the first output transistor of the gate drive subcircuit are combined to improve the falling edge difference of the output signal of the gate drive circuit due to the resistance difference of the connecting wire.
  • the load adjustment portion of the connecting wire and the voltage amplitude adjustment of different clock signals are combined to improve the falling edge difference of the output signal of the gate drive circuit due to the resistance difference of the connecting wire.
  • the load adjustment portion of the connecting wire, the size adjustment of the first output transistor of the gate drive subcircuit and the voltage amplitude adjustment of different clock signals are combined to improve the falling edge difference of the output signal of the gate drive circuit due to the resistance difference of the connecting wire. This embodiment is not limited to this.
  • the embodiment of the present disclosure further provides a display device, comprising the display panel of the aforementioned embodiment.
  • FIG16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the display panel 910 may be an OLED display panel.
  • the display device 91 may be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.
  • this embodiment is not limited thereto.

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Abstract

一种显示面板，包括：衬底(101)、以及设置在衬底(101)上的栅极驱动电路(40)、多条时钟信号线以及多条连接线(51)。多条时钟信号线沿第一方向(X)位于栅极驱动电路(40)的一侧并依次排布。每条连接线(51)电连接栅极驱动电路(40)和一条时钟信号线。至少一条连接线(51)包括负载调节部(512)，负载调节部(512)配置为补偿不同时钟信号线之间的负载差异。至少一条连接线(51)的负载调节部(512)在衬底(101)的正投影与至少一条时钟信号线在衬底(101)的正投影至少部分交叠。

Description

显示面板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示面板及显示装置。
背景技术
随着显示技术的不断发展，显示产品的种类越来越多，例如，液晶显示器(LCD，Liquid Crystal Display)、有机发光二极管(OLED，Organic Light-Emitting Diode)显示器、等离子体显示面板(PDP，Plasma Display Panel)、场发射显示器(FED，Field Emission Display)等。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示面板及显示装置。
一方面，本实施例提供一种显示面板，包括：衬底、以及设置在所述衬底上的栅极驱动电路、多条时钟信号线以及多条连接线；所述多条时钟信号线沿第一方向位于所述栅极驱动电路的一侧并依次排布；每条连接线电连接所述栅极驱动电路和一条时钟信号线。所述多条连接线中的至少一条连接线包括负载调节部，所述负载调节部配置为补偿不同时钟信号线之间的负载差异。所述至少一条连接线的负载调节部在所述衬底的正投影与至少一条时钟信号线在所述衬底的正投影至少部分交叠；或者，所述多条连接线均包括负载调节部，所述多条连接线的负载调节部位于所述多条时钟信号线远离所述栅极驱动电路的一侧，或位于所述多条时钟信号线靠近所述栅极驱动电路的一侧，或位于两条相邻时钟信号线之间的间隔区域内。
在一些示例性实施方式中，所述至少一条连接线的负载调节部在所述衬底的正投影与所述负载调节部所连接的时钟信号线在所述衬底的正投影至少部分交叠。
在一些示例性实施方式中，所述多条连接线的负载调节部在所述衬底的正投影与同一条时钟信号线在所述衬底的正投影存在交叠。
在一些示例性实施方式中，所述至少一条连接线还包括：第一连接部和第二连接部，所述负载调节部连接在所述第一连接部和所述第二连接部之间，所述第一连接部与一条时钟信号线电连接，所述第二连接部与所述栅极驱动电路电连接。所述多条时钟信号线沿第二方向延伸，所述第二方向与所述第一方向交叉；所述至少一条连接线的第二连接部沿所述第一方向延伸。
在一些示例性实施方式中，所述至少一条连接线的负载调节部包括：第一子连接部、第二子连接部以及第三子连接部，所述第一子连接部和第三子连接部沿所述第二方向延伸，所述第二子连接部沿所述第一方向延伸，所述第二子连接部的两端分别与所述第一子连接部和所述第三子连接部连接。
在一些示例性实施方式中，所述至少一条连接线的负载调节部还包括：沿所述第一方向延伸的第四子连接部，所述第四子连接部的两端分别与所述第一子连接部和所述第三子连接部连接；所述第二子连接部和所述第四子连接部沿所述第一方向的长度大致相同。
在一些示例性实施方式中，所述多条连接线的负载调节部的第一子连接部沿所述第二方向的长度大致相同，所述多条连接线的负载调节部的第三子连接部沿所述第二方向的长度大致相同。
在一些示例性实施方式中，靠近所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部的第二子连接部和第四子连接部之间沿所述第二方向的距离，小于远离所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部的第二子连接部和第四子连接部之间沿所述第二方向的距离。
在一些示例性实施方式中，所述多条连接线的第一连接部沿所述第二方向的长度大致相同，靠近所述栅极驱动电路的时钟信号线电连接的连接线的第二连接部沿所述第一方向的长度小于远离所述栅极驱动电路的时钟信号线电连接的连接线的第二连接部沿所述第一方向的长度。
在一些示例性实施方式中，靠近所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部的第二子连接部和第四子连接部之间沿所述第二方向的距离，大于远离所述栅极驱动电路的时钟信号线电连接的连接线的负载调 节部的第二子连接部和第四子连接部之间沿所述第二方向的距离。
在一些示例性实施方式中，所述多条连接线的第二连接部沿所述第一方向的长度大致相同，靠近所述栅极驱动电路的时钟信号线电连接的连接线的第一连接部沿所述第一方向的长度，大于远离所述栅极驱动电路的时钟信号线电连接的连接线的第一连接部沿所述第一方向的长度。
在一些示例性实施方式中，远离所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部与时钟信号线的正投影的交叠面积，大于靠近所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部与时钟信号线的正投影的交叠面积。
在一些示例性实施方式中，所述栅极驱动电路包括多个级联的栅极驱动子电路；每个栅极驱动子电路至少包括第一输出晶体管；所述第一输出晶体管配置为向所述栅极驱动子电路的信号输出端提供时钟信号。远离所述栅极驱动电路的时钟信号线电连接的栅极驱动子电路的第一输出晶体管的尺寸，大于靠近所述栅极驱动电路的时钟信号线电连接的栅极驱动子电路的第一输出晶体管的尺寸。
在一些示例性实施方式中，靠近所述栅极驱动电路的时钟信号线所传输的时钟信号的电压幅值，小于远离所述栅极驱动电路的时钟信号线所传输的时钟信号的电压幅值。
在一些示例性实施方式中，所述多条连接线的电阻大致相同。
另一方面，本实施例提供一种显示装置，包括如上所述的显示面板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示面板的外形示意图；
图2为一种显示面板的显示区域的局部剖面结构示意图；
图3为一种像素电路的等效电路图；
图4为一种栅极驱动子电路的等效电路图；
图5为图4所示的栅极驱动子电路的工作时序图；
图6为一种栅极驱动电路的示意图；
图7为本公开至少一实施例的显示面板的局部示意图；
图8为本公开至少一实施例的显示面板的另一局部示意图；
图9为本公开至少一实施例的显示面板的另一局部示意图；
图10为本公开至少一实施例的显示面板的另一局部示意图；
图11为本公开至少一实施例的显示面板的另一局部示意图；
图12为本公开至少一实施例的显示面板的另一局部示意图；
图13为本公开至少一实施例的显示面板的另一局部示意图；
图14为本公开至少一实施例的栅极驱动电路的示意图；
图15为本公开至少一实施例的时钟信号的示意图；
图16为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”可以包括两个以及两个以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏极)与源电极(源电极端子、源区域或源极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本说明书中，为区分晶体管除栅电极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极。另外，将晶体管的栅极可以称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相 调换。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
在本说明书中，三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本说明书中，“大致相同”可以是指数值相差10％以内的情况。
图1为一种显示面板的外形示意图，外形为一种矩形倒圆角形状。在一些示例中，显示面板可以为包括线性边的闭合多边形、包括弯曲边的圆形或椭圆形、或者包括线性边和弯曲边的半圆形或半椭圆形等。在一些示例中，当显示面板具有线性边时，显示面板的至少一些拐角可以为曲线。当显示面板具有矩形形状时，在相邻的线性边彼此交汇处的部分可以采用具有预定曲率的曲线代替。其中，可以根据曲线的位置不同来设定曲率。例如，可以根据曲线开始的位置、曲线的长度等来改变曲率。
在一些示例中，如图1所示，显示面板可以包括显示区域AA和位于显示区域周边的周边区域BB。在一些示例中，显示区域AA可以包括在第二方向Y上相对设置的第一边缘(下边缘)和第二边缘(上边缘)，以及在第一方向X上相对设置的第三边缘(左边缘)和第四边缘(右边缘)。相邻边缘之间可以通过弧形的倒角连接，形成倒圆角的四边形形状。在一些示例中，周边区域BB可以包括：在第二方向Y上相对设置的第一边框(下边框)和第二边框(上边框)，在第一方向X上相对设置的第三边框(左边框)和第四边框(右边框)。第一边框分别与第三边框和第四边框连通，第二边框分别与第三边框和第四边框连通。
在一些示例中，如图1所示，显示区域AA至少可以包括多个子像素PX、多条扫描线GL以及多条数据线DL。多条扫描线GL可以沿第一方向X延伸，多条数据线DL可以沿第二方向Y延伸。多条扫描线GL和多条数据线DL在衬底上的正投影可以交叉形成多个子像素区域，每个子像素区域内可以设置一个子像素PX。多条数据线DL与多个子像素PX电连接，多条数据线DL可以被配置为向多个子像素PX提供数据信号。多条扫描线GL与多个子像素PX电连接，多条扫描线GL可以被配置为向多个子像素PX提供扫描信号。
在一些示例中，如图1所示，第一方向X可以是显示区域AA中扫描线GL的延伸方向(行方向)，第二方向Y可以是显示区域AA中数据线DL的延伸方向(列方向)。第一方向X和第二方向Y可以相互垂直。
在一些示例中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列。然而，本实施例对此并不限定。
在一些示例中，一个子像素可以包括：像素电路以及与像素电路连接的发光元件。像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以为3T1C结构、7T1C结构、5T1C结构、8T1C结构或者8T2C结构等，其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diodes)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在 其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
在一些示例中，显示面板还可以包括：栅极驱动电路以及数据驱动电路。例如，栅极驱动电路可以设置在显示面板的第三边框和第四边框。栅极驱动电路可以在形成子像素的工艺中与子像素一起形成。数据驱动电路可以设置在单独的芯片或印刷电路板上，以通过显示面板上的信号接入引脚连接到子像素。例如，数据驱动电路可以采用玻璃上芯片、塑料上芯片、膜上芯片等形成设置在显示面板的第一边框，以连接到信号接入引脚。然而，本实施例对此并不限定。在一些示例中，数据驱动电路可以直接设置在显示面板上。
在一些示例中，栅极驱动电路可以通过从时序控制器接收的时钟信号、起始信号等来产生将提供到扫描线GL的扫描信号。例如，栅极驱动电路可以将具有导通电平脉冲的扫描信号顺序地提供到栅线。在一些示例中，栅极驱动电路可以包括移位寄存器，可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的起始信号传输到下一级电路的方式产生扫描信号。
图2为一种显示面板的显示区域的局部剖面结构示意图。图2示意了显示区域的三个子像素的结构。在一些示例中，如图2所示，在垂直于显示面板的方向上，显示面板可以包括：衬底101、以及依次设置在衬底101上的电路结构层102、发光结构层103、封装结构层104以及封装盖板200。在一些可能的实现方式中，显示面板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在一些示例中，如图2所示，衬底101可以为刚性基底或者柔性基底。例如，刚性基底可以采用玻璃或石英等材料。柔性基底可以采用聚酰亚胺(PI)等材料，柔性基底可以是单层结构，或者可以是无机材料层和柔性材料层构成的叠层结构。然而，本实施例对此并不限定。
在一些示例中，如图2所示，每个子像素的电路结构层102可以包括构成像素电路的多个晶体管和存储电容，图2中以每个子像素的像素电路包括的一个晶体管和一个存储电容为例进行示意。在一些可能的实现方式中，每 个子像素的电路结构层102可以包括：依次设置在衬底101上的有源层、第一绝缘层11、第一栅金属层(例如包括晶体管的栅电极和存储电容的第一极板)、第二绝缘层12、第二栅金属层(例如包括存储电容的第二极板)、第三绝缘层13、第一源漏金属层(例如包括晶体管的源电极和漏电极)以及第四绝缘层14。第三绝缘层13上开设有暴露出有源层的表面的过孔，晶体管的源电极和漏电极可以分别通过过孔与有源层连接。第四绝缘层14可以开设有暴露出晶体管的漏电极的过孔。有源层、栅电极、源电极和漏电极可以组成晶体管105，第一极板和第二极板可以组成存储电容106。
在一些示例中，如图2所示，发光结构层103可以包括阳极层、像素定义层、有机发光层和阴极。阳极层可以包括发光元件的阳极，阳极可以设置在第四绝缘层14上，通过第四绝缘层14上开设的过孔与像素电路的晶体管的漏电极连接。像素定义层可以设置在阳极层和第四绝缘层14上，像素定义层上设置有像素开口，像素开口可以暴露出阳极的部分表面。有机发光层至少部分设置在像素开口内，有机发光层与阳极连接。阴极设置在有机发光层上，阴极与有机发光层连接。有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在一些示例中，如图2所示，封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层103。
在一些示例中，有机发光层可以至少包括在阳极上叠设的空穴注入层、空穴传输层、发光层和空穴阻挡层。在一些示例中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，空穴阻挡层可以是连接在一起的共通层。然而，本实施例对此并不限定。
图3为一种像素电路的等效电路图。在一些示例中，如图3所示，本示例的像素电路为3T1C结构，可以包括3个晶体管(即，第一晶体管T1、第二晶体管T2和第三晶体管T3)和1个存储电容Cst。第一晶体管T1还可以称为开关晶体管，第二晶体管T2还可以称为驱动晶体管，第三晶体管T3还 可以称为补偿晶体管。像素电路可以与数据线DL、扫描线GL、感测控制线SL、感测补偿线SE、第一电源线VDD和第二电源线VSS电连接。第一晶体管T1的栅电极与第二晶体管T2的栅电极之间可以形成寄生电容Ca。
在一些示例中，如图3所示，第一晶体管T1的栅电极与扫描线GL电连接，第一晶体管T1的第一极与数据线DL连接，第一晶体管T1的第二极与第二晶体管T2的栅电极电连接。第二晶体管T2的第一极与第一电源线PL1电连接，第二晶体管T2的第二极与发光元件EL的第一极电连接。第三晶体管T3的栅电极与感测控制线SL电连接，第三晶体管T3的第一极与感测补偿线SE电连接，第三晶体管T3的第二极与第二晶体管T2的第二极电连接。存储电容Cst的第一极板与第二晶体管T2的栅电极电连接，存储电容Cst的第二极板与第二晶体管T2的第二极电连接。发光元件EL的第二极与第二电源线PL2电连接。在一些示例中，发光元件EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
在一些示例中，如图3所示，第一晶体管T1可以配置为在扫描线GL的控制下，接收数据线DL传输的数据电压，使第二晶体管T2的栅电极接收所述数据电压。第二晶体管T2可以配置为在其栅电极所接收的数据电压的控制下，在第二极产生相应的电流。第三晶体管T3配置为在感测控制线SL的控制下，提取第二晶体管T2的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿。存储电容Cst可以配置为存储第二晶体管T2的栅电极的电位。发光元件EL配置为响应第二晶体管T2的第二极的电流而发出相应亮度的光。
在一些示例中，第一电源线VDD可以持续提供高电平信号，第二电源线VSS可以持续提供低电平信号。例如，第一电源线VDD提供第一电源电压Vdd，第二电源线VSS提供第二电源电压Vss。
在一些示例中，第一晶体管T1、第二晶体管T2和第三晶体管T3可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。
在一些示例中，像素电路中的多个晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅 (LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，即LTPS+Oxide(简称LTPO)显示面板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例中，以图3所示的像素电路的晶体管均为N型晶体管为例进行说明。图3所示的像素电路的工作过程可以包括以下阶段。
在数据写入阶段，扫描线GL输入高电平信号，感测控制线SL输入高电平信号，第一晶体管T1导通，第三晶体管T3导通。数据线DL提供的数据电压Vdata传递至第二晶体管T2的栅电极。即，第二晶体管T2的栅电极电压Vg＝Vdata。第二晶体管T2的第二极电压Vs＝Vsen+ΔV。其中，Vsen为感测补偿线SE提供的补偿电压；ΔV为数据写入阶段，由于第二晶体管T2导通产生的第二晶体管T2的第二极的电压变化量。
在发光阶段，扫描线GL输入低电平信号，感测控制线SL输入低电平信号。第一晶体管T1断开，第三晶体管T3断开。在数据电压Vdata的控制下，第二晶体管T2可以将第一电源线VDD提供的第一电源电压Vdd传递至第二晶体管T2的第二极，以此来驱动发光元件EL发光。
在从数据写入到发光的过程中，在第一晶体管T1的栅电极导通时，第一晶体管T1的第二极从第三电源电压Vgh到第四电源电压Vgl的过程，寄生电容Ca和存储电容Cst之间的耦合过程会使得第二晶体管T1的栅电极电位有一个变化量△Vp。△Vp＝△V1×CST/(CST+CA)，其中，CST表示存储电容Cst的电容值，CA表示寄生电容Ca的电容值，△V1＝Vgh-Vgl。即在第一晶体管T1的栅电极导通时，第一晶体管T1的第二极从第三电源电压Vgh到第四电源电压Vgl的过程，此电压变化会对第二晶体管T2的栅电极产生一个电压耦合影响，即ΔVp。同时△Vp还受到扫描线GL提供的扫描信号的下降沿的影响，扫描信号的下降沿越大△Vp越小。
在一些示例中，栅极驱动电路可以包括级联的多个栅极驱动子电路。例如，每个栅极驱动子电路可以作为一个移位寄存器将扫描信号依次传递给下 一个栅极驱动子电路，逐行开启像素电路的第一晶体管，完成数据信号写入。
图4为一种栅极驱动子电路的等效电路图。本示例的栅极驱动子电路仅为一种示意。在一些示例中，如图4所示，栅极驱动子电路可以包括：移位单元22和输出单元21。输出单元21与时钟信号端CLK、第四电源线VGL、信号输出端OUTPUT、第一控制节点Q、第二控制节点QA和第三控制节点QB电连接，配置为在第一控制节点Q的控制下，向信号输出端OUTPUT提供时钟信号端CLK的信号，在第二控制节点QA和第三控制节点QB的控制下，向信号输出端OUTPUT提供第四电源线VGL的信号。移位单元22与信号输入端INPUT、复位信号端RESET、第三电源线VGH、第一控制节点Q、第二控制节点QA和第三控制节点QB电连接，配置为在信号输入端INPUT、复位信号端RESET的控制下，控制第一控制节点Q、第二控制节点QA和第三控制节点QB的电位。其中，第三电源线VGH持续提供高电位的第三电源电压Vgh，第四电源线VGL持续提供低电位的第三电源电压Vgl。
在一些示例中，如图4所示，输出单元21可以包括：第一输出晶体管M1、第二输出晶体管M2、第三输出晶体管M3以及第一电容C1。第一输出晶体管M1的栅电极与第一控制节点Q电连接，第一极与时钟信号端CLK电连接，第二极与信号输出端OUTPUT电连接。第二输出晶体管M2的栅电极与第二控制节点QA电连接，第一极与第四电源线VGL电连接，第二极与信号输出端OUTPUT电连接。第三输出晶体管M3的栅电极与第三控制节点QB电连接，第一极与第四电源线VGL电连接，第二极与信号输出端OUTPUT电连接。第一电容C1的第一极板与第一控制节点Q电连接，第二极板与信号输出端OUTPUT电连接。
在一些示例中，如图4所示，移位单元22可以包括：第一移位晶体管M4、第二移位晶体管M5、第三移位晶体管M6、第四移位晶体管M7和第五移位晶体管M8。第一移位晶体管M4的栅电极和第一极与信号输入端INPUT电连接，第二极与第一控制节点Q电连接。第二移位晶体管M5的栅电极与第三控制节点QB电连接，第一极与第四电源线VGL电连接，第二极与第一控制节点Q电连接。第三控制节点QB与复位信号端RESET电连接。第三移位晶体管M6的栅电极与第二控制节点QA电连接，第一极与第四电 源线VGL电连接，第二极与第一控制节点Q电连接。第四移位晶体管M7的栅电极与第一控制节点Q电连接，第一极与第四电源线VGL电连接，第二极与第二控制节点QA电连接。第五移位晶体管M8的栅电极和第一极与第三电源线VGH电连接，第二极与第二控制节点QA电连接。
下面以图4所示的栅极驱动子电路的晶体管均为N型晶体管为例。图5为图4所示的栅极驱动子电路的工作时序图。如图4和图5所示，栅极驱动子电路的工作过程包括以下阶段。
第一阶段S1，即输入阶段，信号输入端INPUT的信号为高电平，复位信号端RESET和时钟信号端CLK的输入信号均为低电平，信号输出端OUTPUT的输出信号为低电平信号。信号输入端INPUT的信号为高电平，第一移位晶体管M4导通，将第一控制节点Q的电位拉高，对第一电容C1进行充电。虽然第三电源线VGH持续提供高电平的第三电源电压Vgh，第五移位晶体管M8导通，但由于第一控制节点Q的电位为高电平，则第四移位晶体管M7导通，拉低了第二控制节点QA的电位，第三移位晶体管M6并不开启，第一控制节点Q的电位不会被拉低。
第二阶段S2，即输出阶段，时钟信号端CLK的输入信号为高电平，信号输入端INPUT和复位信号端RESET的输入信号为低电平。信号输入端INPUT的信号为低电平，第一移位晶体管M4关断，而时钟信号端CLK的信号变为高电平，由于第一电容C1的自举效应，使得第一控制节点Q的电位继续被拉高，第一控制节点Q的高电平使第一输出晶体管M1开启，信号输出端OUTPUT输出时钟信号端CLK的高电平信号。另外，第一控制节点Q电位的升高，提高了第一输出晶体管M1的导通能力，保证了像素充电。
本阶段中，由于第一控制节点Q的电位仍为高电平，则第四移位晶体管M7仍然开启，拉低了第二控制节点QA的电位，第三移位晶体管M6和第二输出晶体管M2并不开启，第一控制节点Q和信号输出端OUTPUT的电位不会被拉低。
第三阶段S3，即复位阶段，复位信号端RESET的输入信号为高电平，信号输入端INPUT和时钟信号端CLK的输入信号为低电平，信号输出端OUTPUT的输出信号为低电平。其中，复位信号端RESET的输入信号为高 电平，第二移位晶体管M5和第三输出晶体管M3开启，第一控制节点Q的电位被拉低至第四电源线VGL提供的低电平，第三输出晶体管M3开启，信号输出端OUTPUT的电位被拉低至第四电源线VGL的低电平。由于第一控制节点Q的电位为低电平，第四移位晶体管M7关断，第二控制节点QA的电位为高电平，第三移位晶体管M6开启，第一控制节点Q的电位被持续拉低，以降低噪声。第二输出晶体管M2开启，信号输出端OUTPUT的电位被持续拉低至第四电源线VGL的低电平，以降低噪声。
第四阶段S4，时钟信号端CLK的输入信号为高电平，由于第一控制节点Q的电位为低电平，第一输出晶体管M1关断，信号输出端OUTPUT的输出信号为低电平，同时，第四移位晶体管M7关断，第二控制节点QA的电位为高电平，第三移位晶体管M6导通，第一控制节点Q的电位被持续拉低，以降低噪声，第二输出晶体管M2导通，信号输出端OUTPUT的电位被持续拉低，以降低噪声。
第五阶段S5，时钟信号端CLK的输入信号为低电平，由于第一控制节点Q的电位为低电平，第一输出晶体管M1关断，信号输出端OUTPUT的输出信号为低电平，同时，第四移位晶体管M7关断，第二控制节点QA的电位为高电平，第三移位晶体管M6导通，第一控制节点Q的电位被持续拉低，以降低噪声。第二输出晶体管M2导通，信号输出端OUTPUT的电位被持续拉低，以降低噪声。
在第三阶段S3之后，本级栅极驱动子电路持续第四阶段S4和第五阶段S5，直至信号输入端INPUT再次接收到高电平信号。
在本示例中，信号输入端INPUT的信号为脉冲信号，只在第一阶段S1为高电平；信号输出端OUTPUT的输出信号为脉冲信号，只在第二阶段S2为高电平；复位信号端RESET的信号为脉冲信号，只在第三阶段S3为高电平。
图6为一种栅极驱动电路的示意图。在一些示例中，如图6所示，栅极驱动电路可以包括多个栅极驱动子电路。栅极驱动电路可以与多条时钟信号线(例如包括第一时钟信号线CLK1至第六时钟信号线CLK6)电连接。然而，本实施例对此并不限定。在另一些示例中，栅极驱动电路可以与四条时 钟信号线或八条时钟信号线电连接。
在一些示例中，如图6所示，第N级栅极驱动子电路GOA(N)的时钟信号端可以与第一时钟信号线CLK1电连接，第N+1级栅极驱动子电路GOA(N+1)的时钟信号端可以与第二时钟信号线CLK2电连接，第N+2级栅极驱动子电路GOA(N+2)的时钟信号端可以与第三时钟信号线CLK3电连接，第N+3级栅极驱动子电路GOA(N+3)的时钟信号端可以与第四时钟信号线CLK4电连接，第N+4级栅极驱动子电路GOA(N+4)的时钟信号端可以与第五时钟信号线CLK5电连接，第N+5级栅极驱动子电路GOA(N+5)的时钟信号端可以与第六时钟信号线CLK6电连接，第N+6级栅极驱动子电路GOA(N+6)的时钟信号端可以与第一时钟信号线CLK1电连接，第N+7级栅极驱动子电路GOA(N+7)的时钟信号端可以与第二时钟信号线CLK2电连接。在本示例中，六个栅极驱动子电路可以作为一组，分别与六条时钟信号线(即第一时钟信号线CLK1至第六时钟信号线CLK6)电连接。每六个栅极驱动子电路可以作为一个循环，依次类推。其中，N为正整数。
在一些示例中，每一级栅极驱动子电路的信号输出端OUTPUT的输出信号可以作为扫描信号提供给显示区域的一行子像素的像素电路。第N级栅极驱动子电路GOA(N)的信号输入端可以与起始信号线STV电连接。本示例对于栅极驱动子电路之间的连接关系并不限定。例如，第N+1级栅极驱动子电路的信号输出端的输出信号可以提供给第N+2级栅极驱动子电路的信号输入端，还可以提供给第N级栅极驱动子电路的复位信号端。
在一些示例中，与栅极驱动电路电连接的多条时钟信号线提供的时钟信号的脉冲周期可以是相同的。前一条时钟信号线提供的时钟信号的脉冲信号结束的同时后一条时钟信号线提供的时钟信号的脉冲信号可以产生。例如，第一时钟信号线的第一个脉冲信号首先产生，第一个脉冲信号结束的同时第二时钟信号线的第一个脉冲信号产生，第二时钟信号线的第一个脉冲信号结束的同时第三时钟信号线的第一个脉冲信号产生，第三时钟信号线的第一个脉冲信号结束的同时第四时钟信号线的第一个脉冲信号产生，第四时钟信号线的第一个脉冲信号结束的同时第五时钟信号线的第一个脉冲信号产生，第五时钟信号线的第一个脉冲信号结束的同时第六时钟信号线的第一个脉冲信 号产生，第六时钟信号线的第一个脉冲信号结束的同时第一时钟信号线的第二个脉冲信号产生，以此类推。
在一些示例中，如图6所示，时钟信号线可以通过连接线与栅极驱动电路电连接。为了尽量减少走线负载，连接线通常是按照最短走线路径布设的。靠近栅极驱动电路的时钟信号线对应的连接线的长度较短，对应的线电阻较小。以连接不同时钟信号线的多条连接线为一组，在一组连接线中，每一根连接线的长度不同，远离栅极驱动电路的时钟信号线对应的连接线的长度较长，对应的线电阻较大，当时钟信号传输时，不同的电阻大小造成的损耗不同。如此一来，传输给栅极驱动电路的时钟信号存在差异，使得显示区域的像素电路接收到的扫描信号的下降沿发生差异进而影响△Vp，导致显示区域产生横纹显示不良。以图6所示的栅极驱动电路与六条时钟信号线(例如第一时钟信号线CK1至第六时钟信号线CLK6)电连接为例，相邻两条时钟信号线电连接的连接线的线段电阻为△R，则第一时钟信号线CLK1电连接的连接线和第六时钟信号线CLK6电连接的连接线之间相差5×△R，如此一来，会在第一时钟信号线CLK1电连接的栅极驱动子电路(例如GOA(N+6))所连接的子像素行与第六时钟信号线CLK6电连接的栅极驱动子电路(例如GOA(N+7))所连接的子像素行的交界处产生一条亮度差异带来的分界线。在大尺寸显示面板中，栅极驱动电路电连接的时钟信号线的较多，上述情况越明显。
本实施例提供一种显示面板，通过对连接在时钟信号线和栅极驱动电路之间的连接线进行负载补偿，使得多条连接线的负载大致相同，确保栅极驱动电路的多个输出信号的下降沿的一致性，从而保证显示面板的显示效果。
本实施例提供一种显示面板，包括：衬底、以及设置在衬底上的栅极驱动电路、多条时钟信号线以及多条连接线。多条时钟信号线沿第一方向位于栅极驱动电路的一侧并依次排布。每条连接线电连接栅极驱动电路和一条时钟信号线。至少一条连接线包括负载调节部，负载调节部配置为补偿不同时钟信号线之间的负载差异。至少一条连接线的负载调节部在衬底的正投影与至少一条时钟信号线在衬底的正投影至少部分交叠；或者，所述多条连接线均包括负载调节部，所述多条连接线的负载调节部位于所述多条时钟信号线 远离所述栅极驱动电路的一侧，或位于所述多条时钟信号线靠近所述栅极驱动电路的一侧，或位于相邻两条时钟信号线之间的间隔区域内。
在一些示例性实施方式中，至少一条连接线的负载调节部在衬底的正投影与所述负载调节部所连接的时钟信号线在衬底的正投影可以至少部分交叠。例如，至少一条连接线的负载调节部在衬底的正投影可以位于该负载调节部所连接的时钟信号线在衬底的正投影范围内。本示例通过将负载调节部设置在时钟信号线的正投影范围内，不仅可以补偿不同时钟信号线之间的负载差异，而且可以避免占用走线空间，有利于节省空间，避免对时钟信号线以外的走线产生干扰。
在一些示例性实施方式中，多条连接线的负载调节部在衬底的正投影与多条时钟信号线在衬底的正投影可以没有交叠，且多条连接线的负载调节部的设置位置相对于栅极驱动电路和多条时钟信号线而言可以是相同的。例如，例如，多条连接线的负载调节部可以均位于多条时钟信号线远离栅极驱动电路的一侧；或者，多条连接线的负载调节部可以均位于多条时钟信号线靠近栅极驱动电路的一侧；或者，多条连接线的负载调节部可以均位于两条相邻时钟信号线之间的间隔区域内。本示例通过将全部负载调节部设置在时钟信号线远离栅极驱动电路的一侧，不仅可以补偿不同时钟信号线之间的负载差异，而且可以避免对时钟信号线产生干扰，还有利于节省走线空间。或者，本示例通过将全部负载调节部设置在时钟信号线远离栅极驱动电路的一侧，不仅可以补偿不同时钟信号线之间的负载差异，而且可以避免对时钟信号线产生干扰，还可以减少时钟信号线过长带来的大静电对栅极驱动电路内的晶体管的影响，还有利于节省走线空间。或者，本示例通过将全部负载调节部设置在两条相邻时钟信号线之间的间隔区域内，不仅可以补偿不同时钟信号线之间的负载差异，而且可以避免对时钟信号线产生干扰，还可以避免连接线的长度过大，还可以有利于节省走线空间，只需要增大两条相邻信号线之间的间隔区域即可。
在一些示例性实施方式中，多条连接线的负载调节部在衬底的正投影与同一条时钟信号线在衬底的正投影可以存在交叠。本示例不仅可以补偿不同时钟信号线之间的负载差异，而且可以减少对时钟信号线的干扰，并有利于 节省走线空间。
下面通过多个示例对本实施例的方案进行举例说明。下述示例中以显示区域的左侧边框区域内的部分时钟信号线和栅极驱动电路为例进行说明。下述示例中以栅极驱动电路与六条时钟信号线电连接为例。
图7为本公开至少一实施例的显示面板的局部示意图。在一些示例中，如图7所示，栅极驱动电路40电连接的时钟信号线为六条，例如可以包括：第一时钟信号线CLK1、第二时钟信号线CLK2、第二时钟信号线CLK3、第三时钟信号线CLK4、第四时钟信号线CLK4、第五时钟信号线CLK5和第六时钟信号线CLK6。六条时钟信号线可以沿第二方向Y延伸，并沿第一方向X位于栅极驱动电路40远离显示区域的一侧。栅极驱动电路40包括的多个栅极驱动子电路可以沿第二方向Y依次排布。然而，本实施例对此并不限定。例如，多条时钟信号线可以沿第一方向位于栅极驱动电路靠近显示区域的一侧；或者多条时钟信号线中的部分信号线位于栅极驱动电路远离显示区域的一侧，另一部分信号线位于栅极驱动电路靠近显示区域的一侧。
在一些示例中，如图7所示，多条时钟信号线沿第一方向X的长度可以大致相同。相邻时钟信号线之间的间距(即沿第一方向X的间隔距离)可以大致相同。
在一些示例中，如图7所示，多条时钟信号线可以分别通过多条连接线51与栅极驱动电路40电连接。一条连接线51的两端可以分别与一条时钟信号线和栅极驱动电路的一个栅极驱动子电路的时钟信号端电连接。时钟信号线和连接线可以位于不同膜层。例如，时钟信号线可以与显示区域的第一源漏金属层同层设置，连接线可以与显示区域的第一栅金属层或第二栅金属层同层设置，时钟信号线可以通过绝缘层开设的过孔与连接线电连接。
本公开实施例所说的“A和B为同层结构”或者“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，或者A和B靠近衬底一侧的表面与衬底的距离基本相同，或者A和B靠近衬底一侧的表面与同一个膜层直接接触。
在一些示例中，如图7所示，每条连接线51可以包括：依次连接的第一连接部511、负载调节部512和第二连接部513。第一连接部511的一端与对 应的一条时钟信号线电连接，另一端连接负载调节部512。第二连接部513的一端与栅极驱动电路40的一个栅驱动子电路的时钟信号端电连接，另一端与负载调节部512的另一端电连接。第一连接部511在衬底的正投影可以为矩形，例如可以通过绝缘层上开设的过孔与对应的时钟信号线电连接。第二连接部513可以为沿第一方向X延伸的直线段。以分别与六条时钟信号线电连接、且沿第二方向Y连续排布的六条连接线51作为一组连接线，在一组连接线中，六条连接线51的第一连接部511的形状和尺寸可以大致相同，六条连接线51的第二连接部513沿第一方向X的长度可以不同，六条连接线51的负载调节部512沿第二方向Y的长度可以大致相同。
在一些示例中，如图7所示，每一条连接线51的负载调节部512可以包括：第一子连接部5121、第二子连接部5122、第三子连接部5123和第四子连接部5124。第一子连接部5121和第三子连接部5123可以均沿第二方向Y延伸，第二子连接部5122和第四子连接部5124可以均沿第一方向X延伸。第二子连接部5122和第四子连接部5124可以连接在第一子连接部5121和第三子连接部5123之间。第一子连接部5121的一端可以与第一连接部511电连接，另一端可以与第四子连接部5124的一端电连接；第三子连接部5123的一端可以与第二连接部513电连接，另一端可以与第四子连接部5124的另一端电连接。第二子连接部5122可以位于第四子连接部5124靠近第一连接部511的一侧。例如，第一子连接部5121可以包括第一子段5121a和第二子段5121b，第一子段5121a的两端分别与第一连接部511和第二子连接部5122电连接，第二子段5121b的两端可以分别与第二子连接部5122和第四子连接部5124电连接。第三子连接部5123可以包括第三子段5123a和第四子段5123b，第三子段5123a的两端分别与第二连接部512和第二子连接部5122电连接，第四子段5123b的两端可以分别与第二子连接部5122和第四子连接部5124电连接。
在一些示例中，如图7所示，在一组连接线中，多条连接线的负载调节部512的第一子连接部5121沿第二方向Y的长度可以大致相同，第三子连接部5123沿第二方向Y的长度可以大致相同，第二子连接部5122和第四子连接部5124沿第一方向X的长度可以大致相同。连接线的每个部分在垂直 于显示面板所在方向上的截面面积可以大致相同。一条连接线51的负载调节部512的第一子连接部5121沿第二方向Y的长度可以大于第三子连接线5123沿第二方向Y的长度。
在一些示例中，如图7所示，在一组连接线中，多条连接线的负载调节部512的第一子连接部5121的第一子段5121a沿第二方向Y的长度可以不同，第三子连接部5123的第三子段5123a沿第二方向Y的长度可以不同。多条连接线的负载调节部512的第二子连接部5122和第四子连接部5124之间的距离可以不同。其中，靠近栅极驱动电路40的时钟信号线电连接的连接线的负载调节部512的第二子连接部5122和第四子连接部5124之间的距离，小于远离栅极驱动电路40的时钟信号线电连接的连接线的负载调节部512的第二子连接部5122和第四子连接部5124之间的距离。例如，第一时钟信号线CLK1电连接的连接线51的负载调节部512的第二子连接部5122可以与第二连接部513共线，两者在第二方向Y的间距可以为0，负载调节部512的第三子连接部5123的第三子段5123a的长度可以为0。例如，第六时钟信号线CLK6电连接的连接线51的负载调节部512的第二子连接部5122和第四子连接部5124之间的距离可以小于第二子连接部5122和第二连接部513之间的距离，负载调节部512的第三子连接部5123的第三子段5123a的长度可以大于第四子段5123b的长度。
在一些示例中，根据走线电阻的计算式子R＝ρL/S，其中，R为电阻值，ρ为电阻率，L为走线的等效长度，S为走线的截面面积。由此可知，在多条连接线的多个部分的电阻率和截面面积相同的情况下，其电阻大小由其等效长度决定，通过设置多条连接线的等效长度一致，可以使得多条连接线的电阻一致。如图7所示，每条连接线的等效长度可以为负载调节部512的第一子连接部5121的第一子段5121a沿第二方向Y的长度、第二子连接部5122沿第一方向X的长度、第三子连接部5123的第三子段5123a沿第二方向Y的长度以及第二连接部513沿第一方向X的长度之和。本示例通过负载调节部的第二子连接部的位置调整，可以对不同时钟信号线所连接的连接线进行电阻补偿，从而使得不同时钟信号线所连接的连接线的电阻大小基本一致，改善由于连接线的电阻差异导致的栅极驱动电路的输出信号的下降沿差异情 况。
在一些示例中，如图7所示，每条连接线51的第一连接部511和负载调节部512在衬底的正投影与所连接的时钟信号线在衬底的正投影可以存在交叠，例如位于所连接的时钟信号线在衬底的正投影范围内。连接线51的第二连接部513在衬底的正投影可以与至少一条时钟信号线在衬底的正投影存在交叠。在本示例中，多条连接线51的负载调节部512在衬底的正投影与时钟信号线的交叠面积可以大致相同，使得多条连接线51与时钟信号线之间的寄生电容可以大致相同。
本示例的显示面板，利用负载调节部补偿由于多条时钟信号线与栅极驱动电路之间的距离不同而产生的不同连接线的长度差异，使得多条连接线的电阻可以大致相同，改善由于连接线的电阻差异导致的栅极驱动电路的输出信号的下降沿差异情况。而且，多条连接线的负载调节部在衬底的正投影位于所连接的时钟信号线在衬底的正投影范围内，无需增加负载调节部的排布空间，不会增加栅极驱动电路的占用空间，也不会增加边框区域的范围，而且不会对除时钟信号线以外的走线产生干扰。
图8为本公开至少一实施例的显示面板的另一局部示意图。在一些示例中，如图8所示，每条连接线51可以包括：依次连接的第一连接部511、负载调节部512和第二连接部513。第一连接部511可以包括：相互连接的第一连接块5111和第一连接条5112。第一连接块5111与对应的时钟信号线电连接。第一连接块5111在衬底的正投影可以为矩形，并与所连接的时钟信号线在衬底的正投影存在交叠，例如位于所连接的时钟信号线在衬底的正投影范围内。第一连接条5112可以沿第一方向X延伸的条状结构，并与负载调节部512的第一子连接部5121的一端电连接。
在一些示例中，如图8所示，多条连接线51的负载调节部512可以位于六条时钟信号线在第一方向X远离栅极驱动电路40的一侧，例如，负载调节部512与第一时钟信号线CLK1相邻。多条连接线51的第三连接部513沿第一方向X的长度可以大致相同。
在本示例中，每条连接线51的等效长度可以为第一连接部511的第一连接条5112沿第一方向X的长度、负载调节部512的第一子连接部5121的第 一子段5121a沿第二方向Y的长度、第二子连接部5122沿第一方向X的长度、第三子连接部5123的第三子段5123a沿第二方向Y的长度以及第二连接部513沿第一方向X的长度之和。例如，第一时钟信号线CLK1的第一连接部511的第一连接条5112的长度较短，负载调节部512的绕线长度较长；第六时钟信号线CLK6的第一连接部511的第一连接条5112的长度较长，负载调节部512的绕线长度较短。
本示例的显示面板，利用位于多条时钟信号线远离栅极驱动电路一侧的负载调节部的绕线结构来补偿由于多条时钟信号线与栅极驱动电路之间的距离不同而产生的不同连接线的长度差异，使得多条连接线的电阻可以大致相同，改善由于连接线的电阻差异导致的栅极驱动电路的输出信号的下降沿差异情况。而且，多条连接线的负载调节部位于多条时钟信号线远离栅极驱动电路的一侧，可以减少走线空间占用。多条连接线的负载调节部的第三子连接部5123沿第二方向Y的长度大致相同，可以使得连接线与相邻时钟信号线(即第一时钟信号线CLK1)的侧面面积一致，保证多条连接线与相邻时钟信号线之间的侧向电容一致。在另一些示例中，多条连接线的负载调节部可以省略第四子连接部和第一子连接部的第二子段。
关于本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图9为本公开至少一实施例的显示面板的另一局部示意图。在一些示例中，如图9所示，每条连接线51可以包括：依次连接的第一连接部511、负载调节部512和第二连接部513。第一连接部511可以包括：相互连接的第一连接块5111和第一连接条5112。多条连接线51的负载调节部512可以位于六条时钟信号线靠近栅极驱动电路40的一侧。例如，多条连接线51的负载调节部512位于六条时钟信号线和栅极驱动电路40之间，例如与第六时钟信号线CLK6相邻。
在一些示例中，如图9所示，多条连接线51的第二连接部513沿第一方向X延伸，且沿第一方向X的长度大致相同。多条连接线51的第一连接部511的第一连接块5111的形状和尺寸大致相同。多条连接线51的第一连接部511的第一连接条5112沿第一方向X延伸，且沿第一方向X的长度不同。 靠近栅极驱动电路的时钟信号线电连接的连接线51的第一连接部511的第一连接条5112沿第一方向X的长度，小于远离栅极驱动电路的时钟信号线电连接的连接线51的第一连接部511的第一连接条5112沿第一方向X的长度。例如，第六时钟信号线CLK6电连接的连接线51的第一连接部511的第一连接条5112沿第一方向X的长度最小，第一时钟信号线CLK1电连接的连接线51的第一连接部511的第一连接条5112沿第一方向X的长度最大。
本示例利用位于栅极驱动电路和多条时钟信号线之间的负载调节部来补偿由于多条时钟信号线与栅极驱动电路之间的距离不同而产生的不同连接线的长度差异，使得多条连接线的电阻可以大致相同，改善由于连接线的电阻差异导致的栅极驱动电路的输出信号的下降沿差异情况。而且通过将多条连接线的负载调节部设置在多条时钟信号线和栅极驱动电路之间，可以增大时钟信号线和栅极驱动电路之间的距离，从而减小时钟信号线过长带来的静电对栅极驱动电路内的晶体管的影响。
关于本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图10为本公开至少一实施例的显示面板的另一局部示意图。在一些示例中，如图10所示，每条连接线51可以包括：依次连接的第一连接部511、负载调节部512和第二连接部513。每条连接线51的第一连接部511和负载调节部512在衬底的正投影与所连接的时钟信号线在衬底的正投影可以存在交叠，例如位于所连接的时钟信号线在衬底的正投影范围内。负载调节部512在衬底的正投影可以为矩形。不同连接线51的负载调节部512的尺寸可以不同。不同连接线51的负载调节部512在衬底的正投影与所连接的时钟信号线在衬底的正投影的交叠面积可以不同。远离栅极驱动电路40的时钟信号线电连接的连接线51的负载调节部512在衬底的正投影与时钟信号线在衬底的正投影的交叠面积，可以大于靠近栅极驱动电路40的时钟信号线电连接的连接线51的负载调节部512在衬底的正投影与时钟信号线在衬底的正投影的交叠面积。例如，第一时钟信号线CLK1电连接的连接线51的负载调节部512在衬底的正投影与第一时钟信号线CLK1在衬底的正投影的交叠面积最大，第六时钟信号线CLK6电连接的连接线51的负载调节部512在衬底的正投影 与第六时钟信号线CLK6在衬底的正投影的交叠面积最小。
在一些示例中，如图10所示，多条连接线51的负载调节部512沿第一方向X的长度可以大致相同，沿第二方向Y的长度可以不同。通过将远离栅极驱动电路40的时钟信号线所连接的连接线51的负载调节部512沿第二方向Y的长度增加，可以使得负载调节部512的面积增大，可以保证连接线51的线电阻减小，从而减小时钟信号的损耗。
关于本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图11为本公开至少一实施例的显示面板的另一局部示意图。在一些示例中，如图11所示，每条连接线51可以包括：依次连接的第一连接部511、负载调节部512和第二连接部513。第一连接部511可以包括：相互连接的第一连接块5111和第一连接条5112。多条连接线51的负载调节部512在衬底的正投影均与第一时钟信号线CLK1在衬底的正投影存在交叠，例如位于第一时钟信号线CLK1在衬底的正投影范围内。然而，本实施例对此并不限定。在另一些示例中，多条连接线51的负载调节部512在衬底的正投影可以与第二时钟信号线CLK2至第六时钟信号线CLK6中的一条或多条在衬底的正投影存在交叠。
关于本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图12为本公开至少一实施例的显示面板的另一局部示意图。在一些示例中，如图12所示，每条连接线51可以包括：依次连接的第一连接部511、负载调节部512和第二连接部513。第一连接部511可以包括：相互连接的第一连接块5111和第一连接条5112。多条连接线51的负载调节部512可以位于第三时钟信号线CLK3和第四时钟信号线CLK4之间。例如，第一时钟信号线CLK1至第三时钟信号线CLK3连接的连接线51的第一连接部511的第一连接条5112可以沿第一方向X向靠近栅极驱动电路40的一侧延伸，第四时钟信号线CLK4至第六时钟信号线CLK6连接的连接线51的第一连接部511的第一连接条5112可以沿第一方向X向远离栅极驱动电路40的一侧延伸。然而，本实施例对此并不限定。在另一些示例中，多条连接线51的负 载调节部512可以均位于第一时钟信号线CLK1和第二时钟信号线CLK2之间，或者可以位于第二时钟信号线CLK2和第三时钟信号线CLK3之间，或者可以位于第四时钟信号线CLK4和第五时钟信号线CLK5之间，或者可以位于第五时钟信号线CLK5和第六时钟信号线CLK6之间。在另一些示例中，多条连接线中的至少一条连接线的负载调节部可以位于第一时钟信号线CLK1和第二时钟信号线CLK2之间，至少一条连接线的负载调节部可以位于第五时钟信号线CLK5和第六时钟信号线CLK6之间。在另一些示例中，可以在第一时钟信号线CLK1和第二时钟信号线CLK2之间、在第三时钟信号线CLK3和第四时钟信号线CLK4之间、以及在第五时钟信号线CLK5和第六时钟信号线CLK6之间设置负载调节部。
关于本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图13为本公开至少一实施例的显示面板的另一局部示意图。在一些示例中，如图13所示，每条连接线51可以包括：依次连接的第一连接部511、负载调节部512和第二连接部513。第一连接部511可以包括：相互连接的第一连接块5111和第一连接条5112。负载调节部512可以包括：依次连接的第一子连接部5121、第二子连接部5122和第三子连接部5123。第一子连接部5121和第三子连接部5123沿第二方向Y延伸，第一子连接部5121与第一连接部511的第一连接条5112连接，第三子连接部5123与第二连接部513连接。第二子连接部5122沿第一方向X延伸，连接在第一子连接部5121和第三子连接部5123之间。
在一些示例中，如图13所示，多条连接线51的负载调节部512位于多条时钟信号线远离栅极驱动电路40的一侧。例如，多条连接线51的负载调节部512与第一时钟信号线CLK1相邻。
本示例的显示面板，利用位于多条时钟信号线远离栅极驱动电路一侧的负载调节部的绕线结构来补偿由于多条时钟信号线与栅极驱动电路之间的距离不同而产生的不同连接线的长度差异，使得多条连接线的电阻可以大致相同，改善由于连接线的电阻差异导致的栅极驱动电路的输出信号的下降沿差异情况。
关于本实施例的显示面板的其余结构可以参照前述实施例的说明，故于此不再赘述。
上述示例仅为示意。在另一些示例中，可以对上述示例进行组合。例如，针对一组连接线的负载调节部可以采用图7至图13中至少两种设置方式。例如，一组连接线中的至少一条连接线的负载调节部可以采用如图7所示的设置方式，至少一条连接线的负载调节部可以采用如图8至图13中任一所示的设置方式。又如，一组连接线中的至少一条连接线的负载调节部可以采用如图10所示的设置方式，其余连接线的负载调节部可以采用如图7至图9和图11至图13中任一所示的设置方式。又如，一组连接线中的至少一条连接线的负载调节部可以采用如图8所示的设置方式，至少一条连接线的负载调节部可以采用如图9至图13中任一所示的设置方式。本实施例对此并不限定。
图14为本公开至少一实施例的栅极驱动电路的示意图。在一些示例中，如图14所示，栅极驱动电路包括多个级联的栅极驱动子电路。栅极驱动电路可以与多条时钟信号线(例如包括第一时钟信号线CLK1至第六时钟信号线CLK6)电连接。第N级栅极驱动子电路GOA(N)的时钟信号端可以与第一时钟信号线CLK1电连接，第N+1级栅极驱动子电路GOA(N+1)的时钟信号端可以与第二时钟信号线CLK2电连接，第N+2级栅极驱动子电路GOA(N+2)的时钟信号端可以与第三时钟信号线CLK3电连接，第N+3级栅极驱动子电路GOA(N+3)的时钟信号端可以与第四时钟信号线CLK4电连接，第N+4级栅极驱动子电路GOA(N+4)的时钟信号端可以与第五时钟信号线CLK5电连接，第N+5级栅极驱动子电路GOA(N+5)的时钟信号端可以与第六时钟信号线CLK6电连接。在本示例中，六个栅极驱动子电路可以作为一组，分别与六条时钟信号线(即第一时钟信号线CLK1至第六时钟信号线CLK6)电连接。每六个栅极驱动子电路可以作为一个循环，依次类推。其中，N为正整数。
在一些示例中，如图14所示，每个栅极驱动子电路至少可以包括第一输出晶体管M1，第一输出晶体管M1可以配置为向栅极驱动子电路的信号输出端OUTPUT提供时钟信号。例如，栅极驱动子电路的等效电路可以如图4所示，第一输出晶体管M1可以在第一控制节点Q的控制下，向信号输出端 OUTPUT提供时钟信号端CLK提供的时钟信号。
在一些示例中，远离栅极驱动电路的时钟信号线电连接的栅极驱动子电路的第一输出晶体管的尺寸，可以大于靠近栅极驱动电路的时钟信号线电连接的栅极驱动子电路的第一输出晶体管的尺寸。如图14所示，第一时钟信号线CLK1至第六时钟信号线CLK6依次靠近栅极驱动电路，其中，第一时钟信号线CLK1最远离栅极驱动电路，第六时钟信号线CLK6最靠近栅极驱动电路。第一时钟信号线CLK1至第六时钟信号线CLK1所电连接的栅极驱动子电路的第一输出晶体管的尺寸可以逐渐减小。其中，栅极驱动子电路GOA(N)的第一输出晶体管M1的尺寸可以大于栅极驱动子电路GOA(N+1)的第一输出晶体管M1的尺寸，栅极驱动子电路GOA(N+1)的第一输出晶体管M1的尺寸可以大于栅极驱动子电路GOA(N+2)的第一输出晶体管M1的尺寸，栅极驱动子电路GOA(N+2)的第一输出晶体管M1的尺寸可以大于栅极驱动子电路GOA(N+3)的第一输出晶体管M1的尺寸，栅极驱动子电路GOA(N+3)的第一输出晶体管M1的尺寸可以大于栅极驱动子电路GOA(N+4)的第一输出晶体管M1的尺寸，栅极驱动子电路GOA(N+4)的第一输出晶体管M1的尺寸可以大于栅极驱动子电路GOA(N+5)的第一输出晶体管M1的尺寸。其中，栅极驱动子电路GOA(N)的第一输出晶体管M1的尺寸可以最大，栅极驱动子电路GOA(N+5)的第一输出晶体管M1的尺寸可以最小。在本示例中，栅极驱动子电路和时钟信号线之间的连接线的电阻越大，该栅极驱动子电路的第一输出晶体管的尺寸可以越大，从而改善由于连接线的电阻增大带来的栅极驱动电路的输出信号的下降沿差异情况。
在一些示例中，第一输出晶体管的尺寸可以为第一输出晶体管的有源层的宽长比(W/L)。其中，第一输出晶体管的有源层的长度可以为有源层在延伸方向上的长度，宽度可以为有源层在延伸平面内与延伸方向垂直的方向上的长度。
本示例中，针对不同时钟信号线与栅极驱动电路之间的连接线的长度差异导致电阻差异的情况，通过调整栅极驱动子电路的第一输出晶体管的尺寸，可以改善由于连接线的电阻差异导致的栅极驱动电路的输出信号的下降沿差异情况。
图15为本公开至少一实施例的时钟信号的示意图。在一些示例中，如图15所示，第一时钟信号线CLK1提供的时钟信号的电压幅值为Vk1，第二时钟信号线CLK2提供的时钟信号的电压幅值为Vk2，第三时钟信号线CLK3提供的时钟信号的电压幅值为Vk3，第四时钟信号线CLK4提供的时钟信号的电压幅值为Vk4，第五时钟信号线CLK5提供的时钟信号的电压幅值为Vk5，第六时钟信号线CLK6提供的时钟信号的电压幅值为Vk6。本示例的时钟信号的电压幅值指时钟信号的高电位电压至和低电位电压之间的差值绝对值。时钟信号的电压幅值可以通过调节时钟信号的高电位电压和低电位电压中的至少之一来实现。例如，通过增大高电位电压，保持低电位电压不变，来增大电压幅值；或者，通过减小低电位电压，保持高电位电压不变，来增大电压幅值；或者，通过增大高电位电压，减小低电位电压，来增大电压幅值。本实施例对此并不限定。
在一些示例中，针对不同时钟信号线与栅极驱动电路之间的连接线的长度差异导致电阻差异的情况，通过调整不同时钟信号线传输的时钟信号的电压幅值，来改善由于连接线的电阻差异导致的栅极驱动电路的输出信号的下降沿差异情况。如图15所示，以第一时钟信号线CLK1至第六时钟信号线CLK6电连接的连接线的电阻逐渐减小为例，第一时钟信号线CLK1传输的时钟信号的电压幅值至第六时钟信号线CLK6传输的时钟信号的电压幅值可以逐渐减小。其中，第一时钟信号线CLK1传输的时钟信号的电压幅值Vk1可以最大，第六时钟信号线CLK6传输的时钟信号的电压幅值Vk6可以最小。
在另一些示例中，上述实施例可以进行组合。例如，结合连接线的负载调节部和栅极驱动子电路的第一输出晶体管的尺寸调整，来改善由于连接线的电阻差异导致的栅极驱动电路的输出信号的下降沿差异情况。又如，结合连接线的负载调节部和不同时钟信号的电压幅值调整，来改善由于连接线的电阻差异导致的栅极驱动电路的输出信号的下降沿差异情况。再如，结合连接线的负载调节部、栅极驱动子电路的第一输出晶体管的尺寸调整以及不同时钟信号的电压幅值调整，来改善由于连接线的电阻差异导致的栅极驱动电路的输出信号的下降沿差异情况。本实施例对此并不限定。
本公开实施例还提供一种显示装置，包括前述实施例的显示面板。
图16为本公开至少一实施例的显示装置的示意图。在一些示例中，如图16所示，显示面板910可以为OLED显示面板。显示装置91可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (16)

  1. 一种显示面板，包括：
    衬底、以及设置在所述衬底上的栅极驱动电路、多条时钟信号线以及多条连接线；所述多条时钟信号线沿第一方向位于所述栅极驱动电路的一侧并依次排布；每条连接线电连接所述栅极驱动电路和一条时钟信号线；
    所述多条连接线中的至少一条连接线包括负载调节部，所述负载调节部配置为补偿不同时钟信号线之间的负载差异；所述至少一条连接线的负载调节部在所述衬底的正投影与至少一条时钟信号线在所述衬底的正投影至少部分交叠；或者，所述多条连接线均包括负载调节部，所述多条连接线的负载调节部位于所述多条时钟信号线远离所述栅极驱动电路的一侧，或位于所述多条时钟信号线靠近所述栅极驱动电路的一侧，或位于两条相邻时钟信号线之间的间隔区域内。
  2. 根据权利要求1所述的显示面板，其中，所述至少一条连接线的负载调节部在所述衬底的正投影与所述负载调节部所连接的时钟信号线在所述衬底的正投影至少部分交叠。
  3. 根据权利要求1所述的显示面板，其中，所述多条连接线的负载调节部在所述衬底的正投影与同一条时钟信号线在所述衬底的正投影存在交叠。
  4. 根据权利要求1至3中任一项所述的显示面板，其中，所述至少一条连接线还包括：第一连接部和第二连接部，所述负载调节部连接在所述第一连接部和所述第二连接部之间，所述第一连接部与一条时钟信号线电连接，所述第二连接部与所述栅极驱动电路电连接；
    所述多条时钟信号线沿第二方向延伸，所述第二方向与所述第一方向交叉；所述至少一条连接线的第二连接部沿所述第一方向延伸。
  5. 根据权利要求4所述的显示面板，其中，所述至少一条连接线的负载调节部包括：第一子连接部、第二子连接部以及第三子连接部，所述第一子连接部和第三子连接部沿所述第二方向延伸，所述第二子连接部沿所述第一方向延伸，所述第二子连接部的两端分别与所述第一子连接部和所述第三子连接部连接。
  6. 根据权利要求5所述的显示面板，其中，所述至少一条连接线的负载调节部还包括：沿所述第一方向延伸的第四子连接部，所述第四子连接部的两端分别与所述第一子连接部和所述第三子连接部连接；所述第二子连接部和所述第四子连接部沿所述第一方向的长度大致相同。
  7. 根据权利要求5或6所述的显示面板，其中，所述多条连接线的负载调节部的第一子连接部沿所述第二方向的长度大致相同，所述多条连接线的负载调节部的第三子连接部沿所述第二方向的长度大致相同。
  8. 根据权利要求6所述的显示面板，其中，靠近所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部的第二子连接部和第四子连接部之间沿所述第二方向的距离，小于远离所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部的第二子连接部和第四子连接部之间沿所述第二方向的距离。
  9. 根据权利要求4至8中任一项所述的显示面板，其中，所述多条连接线的第一连接部沿所述第二方向的长度大致相同，靠近所述栅极驱动电路的时钟信号线电连接的连接线的第二连接部沿所述第一方向的长度小于远离所述栅极驱动电路的时钟信号线电连接的连接线的第二连接部沿所述第一方向的长度。
  10. 根据权利要求6所述的显示面板，其中，靠近所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部的第二子连接部和第四子连接部之间沿所述第二方向的距离，大于远离所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部的第二子连接部和第四子连接部之间沿所述第二方向的距离。
  11. 根据权利要求4至7以及10中任一项所述的显示面板，其中，所述多条连接线的第二连接部沿所述第一方向的长度大致相同，靠近所述栅极驱动电路的时钟信号线电连接的连接线的第一连接部沿所述第一方向的长度，大于远离所述栅极驱动电路的时钟信号线电连接的连接线的第一连接部沿所述第一方向的长度。
  12. 根据权利要求1或2所述的显示面板，其中，远离所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部与时钟信号线的正投影的交叠 面积，大于靠近所述栅极驱动电路的时钟信号线电连接的连接线的负载调节部与时钟信号线的正投影的交叠面积。
  13. 根据权利要求1至12中任一项所述的显示面板，其中，所述栅极驱动电路包括多个级联的栅极驱动子电路；每个栅极驱动子电路至少包括第一输出晶体管；所述第一输出晶体管配置为向所述栅极驱动子电路的信号输出端提供时钟信号；
    远离所述栅极驱动电路的时钟信号线电连接的栅极驱动子电路的第一输出晶体管的尺寸，大于靠近所述栅极驱动电路的时钟信号线电连接的栅极驱动子电路的第一输出晶体管的尺寸。
  14. 根据权利要求1至12中任一项所述的显示面板，其中，靠近所述栅极驱动电路的时钟信号线所传输的时钟信号的电压幅值，小于远离所述栅极驱动电路的时钟信号线所传输的时钟信号的电压幅值。
  15. 根据权利要求1至12中任一项所述的显示面板，其中，所述多条连接线的电阻大致相同。
  16. 一种显示装置，包括如权利要求1至15中任一项所述的显示面板。
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