WO2024087031A1 - 显示基板、显示装置及母板 - Google Patents

显示基板、显示装置及母板 Download PDF

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Publication number
WO2024087031A1
WO2024087031A1 PCT/CN2022/127461 CN2022127461W WO2024087031A1 WO 2024087031 A1 WO2024087031 A1 WO 2024087031A1 CN 2022127461 W CN2022127461 W CN 2022127461W WO 2024087031 A1 WO2024087031 A1 WO 2024087031A1
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Prior art keywords
substrate
layer
base substrate
orthographic projection
display
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PCT/CN2022/127461
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English (en)
French (fr)
Inventor
姚磊
李峰
李凯
苏海东
王成龙
候林
辛昊毅
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to PCT/CN2022/127461 priority Critical patent/WO2024087031A1/zh
Publication of WO2024087031A1 publication Critical patent/WO2024087031A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a display device and a motherboard.
  • Liquid Crystal Display has the advantages of light weight, low power consumption, high image quality, low radiation and easy portability. It has gradually replaced traditional cathode ray tube display (CRT) and is widely used in modern information equipment, such as virtual reality (VR) head-mounted display devices, laptops, televisions, mobile phones and digital products.
  • CTR cathode ray tube display
  • VR virtual reality
  • the display substrate, display device and motherboard provided by the embodiments of the present disclosure are specifically described as follows:
  • an embodiment of the present disclosure provides a display substrate, comprising:
  • a plurality of first signal lines are located on one side of the first substrate, the plurality of first signal lines extend along a first direction and are arranged along a second direction, and the first direction intersects the second direction;
  • a plurality of second signal lines which are arranged in a different layer from the plurality of first signal lines on the same side of the first substrate, and the plurality of second signal lines extend along the second direction and are arranged along the first direction;
  • a plurality of pixel electrodes are located on a side of the layer where the plurality of first signal lines are located and the layer where the plurality of second signal lines are located away from the first base substrate, and the orthographic projections of the plurality of pixel electrodes on the first base substrate are located in a region defined by the intersection of the orthographic projections of the plurality of first signal lines on the first base substrate and the orthographic projections of the plurality of second signal lines on the first base substrate;
  • a plurality of first shading structures are located on a side of the layer where the plurality of pixel electrodes are located away from the first substrate, the plurality of first shading structures extend along the second direction and are arranged along the first direction, the orthographic projections of the plurality of first shading structures on the first substrate are located within the orthographic projections of the gaps between the rows of pixel electrodes extending in the second direction on the first substrate, and the orthographic projections of the plurality of first shading structures on the first substrate and the orthographic projections of the plurality of second signal lines on the first substrate have non-overlapping areas.
  • the orthographic projections of the plurality of second signal lines on the first substrate are located within the orthographic projections of the plurality of first light-shielding structures on the first substrate.
  • the display substrate provided in the embodiments of the present disclosure further includes a plurality of second light shielding structures located between the layer where the plurality of first signal lines are located, the layer where the plurality of second signal lines are located, and the first base substrate, wherein the plurality of second light shielding structures extend along the first direction and are arranged along the second direction;
  • the orthographic projections of the plurality of first signal lines on the first substrate are located within the orthographic projections of the plurality of second light shielding structures on the first substrate.
  • the orthographic projection of the first signal line on the first base substrate is located on one side of the orthographic projection of the symmetry axis of the second light shielding structure extending along the first direction on the first base substrate;
  • an extension distance of an orthographic projection of the second shading structure on the first substrate relative to an orthographic projection of the first signal line on the first substrate is greater than 0 ⁇ m and less than or equal to 0.4 ⁇ m.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure, it further includes a plurality of transistors located between the first base substrate and the layer where the plurality of pixel electrodes are located, and a planar layer located between the layer where the plurality of transistors are located and the layer where the plurality of pixel electrodes are located, and the first electrodes of the transistors are electrically connected to the pixel electrodes through first via holes penetrating the planar layer;
  • the orthographic projection of the first via hole on the first base substrate is located within the orthographic projection of the second light shielding structure on the first base substrate.
  • the orthographic projection of the symmetry axis of the second light shading structure extending along the first direction on the first base substrate roughly coincides with the orthographic projection of the symmetry axis of the second light shading structure extending along the first direction on the first base substrate.
  • the diameter of the first via hole gradually increases, and the extension distance of the orthographic projection of the second light shading structure on the first base substrate relative to the orthographic projection of the maximum diameter of the first via hole on the first base substrate is greater than or equal to 0.8 ⁇ m and less than or equal to 1.0 ⁇ m.
  • the thickness of the planar layer in a direction perpendicular to the first base substrate is greater than or equal to 1.2 ⁇ m and less than or equal to 1.8 ⁇ m.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure, it further includes a gate insulating layer, a first interlayer dielectric layer, and a second interlayer dielectric layer located between the layer where the first electrode of the transistor is located and the active layer of the transistor, and the first electrode of the transistor is electrically connected to the active layer of the transistor through a second via hole penetrating the second interlayer dielectric layer, the first interlayer dielectric layer, and the gate insulating layer;
  • the orthographic projection of the second via hole on the first base substrate is located within the orthographic projection of the second light shielding structure on the first base substrate.
  • the orthographic projection of the first signal line on the first base substrate and the orthographic projection of the second via hole on the first base substrate are separated on both sides of the symmetry axis of the second light shielding structure extending along the first direction;
  • the aperture of the second via hole gradually increases; in the second direction, the distance between the orthographic projection of the first signal line on the first substrate and the orthographic projection of the maximum aperture of the second via hole on the first substrate is approximately equal to Among them, a is the length of the lightly doped region of the active layer in the transistor in the second direction, b is 1/2 of the process fluctuation value of the first signal line and the second via, and c is the alignment deviation between the first signal line and the second via.
  • the extension distance of the orthographic projection of the second shading structure on the first base substrate relative to the orthographic projection of the maximum aperture of the second via hole on the first base substrate is greater than or equal to 0.5 ⁇ m and less than 0.9 ⁇ m.
  • the orthographic projection of the first electrode of the transistor on the first substrate is located within the orthographic projection of the second light-shielding structure on the first substrate.
  • the display substrate provided in the embodiments of the present disclosure further includes a common electrode located on a side of the layer where the multiple pixel electrodes are located away from the first base substrate, and the multiple first light-shielding structures are arranged in contact with the common electrode.
  • the plurality of first light shielding structures are located on a side of the common electrode facing the first base substrate;
  • the orthographic projections of the plurality of first light-shielding structures on the first base substrate are located within the orthographic projection of the common electrode on the first base substrate, and the common electrode covers side surfaces of the plurality of first light-shielding structures.
  • the plurality of first light shielding structures are located on a side of the common electrode away from the first base substrate;
  • the orthographic projections of the plurality of first light shielding structures on the first substrate substantially coincide with the orthographic projections of the common electrodes on the first substrate.
  • the common electrode includes a plurality of slits extending along the second direction, each of the pixel electrodes is arranged corresponding to at least one of the slits, and the orthographic projections of the plurality of slits on the first base substrate and the orthographic projections of the plurality of first shading structures on the first base substrate do not overlap with each other.
  • an embodiment of the present disclosure provides a display device, including a display substrate and a counter substrate arranged opposite to each other, and a liquid crystal layer located between the display substrate and the counter substrate, wherein the display substrate is the above-mentioned display substrate provided in the embodiment of the present disclosure.
  • the opposing substrate includes a black matrix
  • the black matrix includes a plurality of first black matrices extending in the second direction and arranged in the first direction
  • the orthographic projection of the first shading structure on the first base substrate is located within the orthographic projection of the first black matrix on the first base substrate.
  • the counter substrate includes a black matrix
  • the black matrix includes a plurality of second black matrices extending in the first direction and arranged in the second direction
  • the orthographic projection of the second black matrix on the first base substrate is located within the orthographic projection of the second light shielding structure on the first base substrate
  • the diameter of the first via hole passing through the flat layer gradually increases, and the width of the second black matrix in the second direction is greater than or equal to the minimum diameter of the first via hole in the second direction and less than the maximum diameter of the first via hole in the second direction.
  • the orthographic projection of the symmetry axis of the second black matrix extending along the first direction on the first substrate roughly coincides with the orthographic projection of the symmetry axis of the second shading structure extending along the first direction on the first substrate.
  • an embodiment of the present disclosure provides a motherboard, including multiple display substrates, wherein the display substrates are the above-mentioned display substrates provided in the embodiment of the present disclosure, and the first base substrates of each of the display substrates constitute a base substrate of an integrated structure.
  • the display substrate includes a display area and a frame area located on at least one side of the display area;
  • the motherboard further includes a plurality of first alignment marks, and the plurality of first alignment marks are located in the frame area and/or in a gap adjacent to the display substrate;
  • the first alignment mark includes a first sub-alignment pattern that is in the same layer and material as the first signal line, a second sub-alignment pattern that is in the same layer and material as the second signal line, and a third sub-alignment pattern that is in the same layer and material as the second interlayer dielectric layer, wherein the first sub-alignment pattern includes a first hollow structure, the orthographic projection of the second sub-alignment pattern on the base substrate is located within the orthographic projection of the first hollow structure on the base substrate, and the orthographic projection of the third sub-alignment pattern on the base substrate is located within the orthographic projection of the second sub-alignment pattern on the base substrate.
  • the motherboard provided in the embodiments of the present disclosure further includes a plurality of second alignment marks, wherein the plurality of second alignment marks are located in the frame area and/or in a gap adjacent to the display substrate;
  • the second alignment mark includes a fourth sub-alignment pattern that is in the same layer and made of the same material as the second signal line, and a fifth sub-alignment pattern that is in the same layer and made of the same material as the first shading structure, wherein the orthographic projection of the fifth sub-alignment pattern on the base substrate is within the orthographic projection of the fourth sub-alignment pattern on the base substrate.
  • the insulating layer on the side of the layer where the second signal line is located facing the layer where the first light shading structure is located is sequentially set as a second interlayer dielectric layer, a flat layer and a passivation layer; only the passivation layer and the second interlayer dielectric layer are set between the fourth sub-alignment pattern and the fifth sub-alignment pattern.
  • the motherboard in the above-mentioned motherboard provided in the embodiments of the present disclosure, it further includes a plurality of opposite substrates arranged opposite to the plurality of display substrates, the second base substrates of the plurality of opposite substrates are integrally arranged, and the opposite substrates include a black matrix;
  • the motherboard also includes a plurality of third alignment marks, which are located in the border area of the opposing substrate and/or in the gap between the adjacent opposing substrates.
  • the third alignment marks include a sixth sub-alignment pattern that is provided with the same layer and the same material as the black matrix, and a seventh sub-alignment pattern that is provided with the same layer and the same material as the first shading structure.
  • the seventh sub-alignment pattern includes a second hollow structure, and the orthographic projection of the sixth sub-alignment pattern on the base substrate is located within the orthographic projection of the second hollow structure on the base substrate.
  • the above-mentioned motherboard provided in the embodiments of the present disclosure further includes a plurality of fourth alignment marks, wherein the plurality of fourth alignment marks are roughly evenly distributed in the gaps between the display substrates, the fourth alignment marks are arranged in the same layer and with the same material as the first light shading structure, and the fourth alignment marks are configured to measure the deviation of the actual position of the seventh sub-alignment pattern relative to the preset position.
  • FIG1 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure.
  • Fig. 2 is a cross-sectional view along line I-I' in Fig. 1;
  • FIG3 is another schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure.
  • Fig. 4 is a cross-sectional view along line II-II' in Fig. 3;
  • FIG5 is another schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure.
  • Fig. 6 is a cross-sectional view along line III-III' in Fig. 5;
  • FIG. 7 is a schematic diagram of a structure of a display substrate in the related art.
  • Fig. 8 is a cross-sectional view along line IV-IV' in Fig. 7;
  • FIG9 is a picture of a first via hole in a planar layer in the related art.
  • FIG10 is a picture of a first via hole in a planar layer provided by an embodiment of the present disclosure.
  • FIG11 is a schematic diagram showing the alignment of some film layers of a display substrate in the related art.
  • FIG12 is a diagram showing a relationship between the distance between the first signal lines of the second light shielding structure and the leakage current of the transistor;
  • 13 is another relationship diagram between the distance between the first signal lines of the second light shielding structure and the leakage current of the transistor
  • FIG14 is a schematic diagram of a structure of a display device provided in an embodiment of the present disclosure.
  • FIG15 is a schematic diagram of another structure of a display device provided in an embodiment of the present disclosure.
  • FIG16 is a schematic diagram of another structure of a display device provided in an embodiment of the present disclosure.
  • FIG17 is another schematic diagram of the structure of a display device provided in an embodiment of the present disclosure.
  • FIG18 is a schematic diagram of another structure of a display device provided in an embodiment of the present disclosure.
  • FIG19 is a schematic diagram of another structure of a display device provided in an embodiment of the present disclosure.
  • FIG20 is a schematic diagram of a structure of a motherboard provided in an embodiment of the present disclosure.
  • FIG21 is a schematic diagram of the structure of a first alignment mark provided in an embodiment of the present disclosure.
  • FIG22 is a schematic diagram of an alignment between a display substrate and an opposite substrate, and between some film layers in a display substrate, provided in an embodiment of the present disclosure
  • FIG23 is another schematic diagram of alignment between a display substrate and an opposite substrate, and between some film layers in a display substrate provided by an embodiment of the present disclosure
  • FIG24 is a schematic diagram of the structure of a second alignment mark provided in an embodiment of the present disclosure.
  • FIG25 is another structural schematic diagram of a motherboard provided in an embodiment of the present disclosure.
  • FIG26 is a schematic diagram of a structure of a third alignment mark provided in an embodiment of the present disclosure.
  • FIG. 27 is another structural schematic diagram of the third alignment mark provided in an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a display substrate, as shown in FIGS. 1 to 4 , including:
  • a first substrate 101 A first substrate 101;
  • a plurality of first signal lines 102 are located on one side of the first substrate 101 .
  • the plurality of first signal lines 102 extend along a first direction X and are arranged along a second direction Y.
  • the first direction X and the second direction Y intersect.
  • a plurality of second signal lines 103 are arranged on the same side of the first substrate 101 in a different layer from the plurality of first signal lines 102, and the plurality of second signal lines 103 extend along the second direction Y and are arranged along the first direction X;
  • a plurality of pixel electrodes 104 are located on a side of a layer where the plurality of first signal lines 102 are located and a layer where the plurality of second signal lines 103 are located, away from the first base substrate 101, and the orthographic projections of the plurality of pixel electrodes 104 on the first base substrate 101 are located in a region defined by the intersection of the orthographic projections of the plurality of first signal lines 102 on the first base substrate 101 and the orthographic projections of the plurality of second signal lines 103 on the first base substrate 101;
  • a plurality of first shading structures 105 are located on a side of the layer where the plurality of pixel electrodes 104 are located away from the first base substrate 101.
  • the plurality of first shading structures 105 extend along the second direction Y and are arranged along the first direction X.
  • the orthographic projections of the plurality of first shading structures 105 on the first base substrate 101 are located within the orthographic projections on the first base substrate 101 of the gaps between the rows of pixel electrodes 104 extending in the second direction Y.
  • the orthographic projections of the plurality of first shading structures 105 on the first base substrate 101 and the orthographic projections of the plurality of second signal lines 103 on the first base substrate 101 have non-overlapping areas.
  • the first shading structure 105 and the second signal lines 103 can be used to jointly shield light along the second direction Y on the display substrate, thereby reducing the risk of light leakage in the gaps between the rows of pixel electrodes 104 extending in the second direction Y, improving poor cross-color, improving display effects, and enhancing user experience.
  • the pixel spacing extending in the data line direction is usually small, and the width of the black matrix extending in the data line direction is correspondingly small.
  • the black matrix extending in the data line direction cannot effectively block the light leakage at the pixel gap extending in the data line direction, and cross-color phenomenon is prone to occur.
  • the first signal line 102 can be a gate line
  • the second signal line 103 can be a data line.
  • the first light shielding structure 105, the data line and the black matrix can jointly block the light leakage at the pixel gap extending in the second direction Y, effectively improving the poor cross-color caused by misalignment in the related scheme that uses black matrix light shielding alone.
  • the following takes the first signal line 102 as a gate line and the second signal line 103 as a data line as an example to introduce the technical solution of the present disclosure.
  • the orthographic projections of the plurality of second signal lines 103 on the first base substrate 101 may be located within the orthographic projections of the plurality of first shading structures 105 on the first base substrate 101.
  • the first shading structure 105 actually plays the role of shading.
  • a solution of cooperative shading of the first shading structure 105 and the second signal lines 102 is required.
  • the line width of the first shading structure 105 is large, which is convenient for manufacturing, and there is no need to consider the cooperative shading effect between the first shading structure 105 and the second signal lines 102, which is convenient for simple design.
  • the gate lines of the display substrate are blocked by the black matrix of the opposing substrate. Therefore, the actual shading layer in the direction of the gate lines (e.g., the first direction X) is the black matrix, and the size (CD) design size of the black matrix directly affects the transmittance and aperture ratio of the pixels.
  • the alignment level of the display substrate and the opposing substrate must be within a certain design range, and then in the direction of the gate lines (e.g., the first direction X), the optical performance instability caused by the difference in aperture ratio and transmittance caused by the alignment error between the gate lines and the black matrix is minimized.
  • the black matrix may not be able to effectively block the gate lines, resulting in an increase in the shading area, insufficient product aperture ratio, insufficient transmittance, and uneven brightness.
  • a plurality of second shading structures 106 extending along the first direction X (equivalent to the gate line direction) and arranged along the second direction Y (equivalent to the data line direction) can be arranged between the layer where the plurality of first signal lines 102 are located and the layer where the plurality of second signal lines 103 are located and the first base substrate 101, and the orthographic projections of the plurality of first signal lines 102 on the first base substrate 101 are located within the orthographic projections of the plurality of second shading structures 106 on the first base substrate 101, that is, the actual shading layer in the first direction X (equivalent to the gate line direction) is changed from the black matrix BM of the opposite substrate to the second shading structure 106 on the display substrate.
  • the direct alignment between the film layers on the display substrate in the related art can be accurately controlled to within ⁇ 0.8 ⁇ m. Therefore, when the actual light shielding layer in the first direction X (equivalent to the gate line direction) is replaced by the second light shielding structure 106 , the aperture ratio and transmittance can be effectively improved.
  • a flat layer 107 is provided between the first base substrate 101 and the layer where the multiple pixel electrodes 104 are located, and multiple transistors 108 are provided between the flat layer 107 and the first base substrate 101, and the first pole 81 of the transistor 108 is electrically connected to the pixel electrode 104 through a first via hole V1 penetrating the flat layer 107;
  • the orthographic projection of the first via hole V1 on the first base substrate 101 is located within the orthographic projection of the second shading structure 106 on the first base substrate 101, so as to completely shield the first via hole V1 through the second shading structure 106 to avoid light leakage at the first via hole V1 .
  • FIGS 7 and 8 are schematic diagrams of the black matrix (BM) design in the gate line direction (e.g., the first direction X) in the relevant VR products.
  • the first via hole V1 is a via hole with a gradually increasing diameter in the direction Z where the second light shielding structure 106 is away from the first base substrate 101.
  • the bottom diameter of the first via hole V1 is 3.0 ⁇ m and the top diameter is 5.0 ⁇ m.
  • the black matrix (BM) needs to exceed the top diameter of the first via hole V1 by 1.5 ⁇ m on one side.
  • the distance that the black matrix (BM) exceeds the top diameter of the first via hole V1 on one side needs to be slightly greater than the alignment capability level, for example, 2.0 ⁇ m.
  • the black matrix size (BM CD) in the gate line direction (for example, the first direction X) needs to be designed to be 9.0 ⁇ m.
  • a larger black matrix (BM) will directly lead to a significant reduction in the aperture ratio in the gate line direction (for example, the first direction X), which in turn leads to lower transmittance.
  • the direct alignment between the film layers on the display substrate can be precisely controlled to within ⁇ 0.8 ⁇ m. Therefore, when the actual light shielding layer in the first direction X (equivalent to the gate line direction) is replaced by the black matrix BM on the opposite substrate with the second light shielding structure 106 on the display substrate, the second light shielding structure 106 can exceed the top diameter of the first via hole V1 of the flat layer 107 by more than 0.8 ⁇ m on one side, for example, by 1.0 ⁇ m on one side, that is, on the same side of the symmetry axis AOS extending along the first direction X of the second light shielding structure 106, the orthographic projection of the second light shielding structure 106 on the first base substrate 101 relative to the orthographic projection of the maximum diameter (i.e., the top diameter) of the first via hole V1 on the first base substrate 101 has an extension distance d1 greater than or equal to 0.8 ⁇ m and less than or equal to
  • the distances of the second light shading structure 106 on both sides of the symmetry axis AOS extending along the first direction X beyond the first via hole V1 can be set to be approximately the same (that is, the same or within the error range caused by factors such as manufacturing process and measurement).
  • the orthographic projection of the symmetry axis AOS extending along the first direction X of the second light shading structure 106 on the first base substrate 101 can be approximately coincident with the orthographic projection of the symmetry axis of the first via hole V1 extending along the first direction X on the first base substrate 101 (that is, coincident or within the deviation range caused by factors such as manufacturing process and measurement).
  • the second light shielding structure 106 is 1.0 ⁇ m longer than the first via hole V1 on both sides of the symmetry axis extending along the first direction X.
  • the second light shielding structure 106 i.e., the actual light shielding layer
  • the second light shielding structure 106 extending in the second direction X only needs to be 7.0 ⁇ m wide to meet the light shielding requirements of ultra-high-resolution VR products in the second direction X.
  • This is equivalent to using a 7.0 ⁇ m wide second light shielding structure 106 to achieve the light shielding effect of a 9.0 ⁇ m wide black matrix BM under the same pixel structure, so that both the aperture ratio and the transmittance can be greatly improved.
  • a first via hole V 1 with a reduced diameter can be formed.
  • the present disclosure can compress the bottom diameter of the first via hole V 1 from 3.0 ⁇ m to 2.5 ⁇ m, and correspondingly reduce the thickness of the flat layer 107 from 2.3 ⁇ m in the related art to 1.2 ⁇ m to 1.8 ⁇ m, for example, 1.5 ⁇ m.
  • FIG9 and FIG10 are SEM images of the first via hole V 1 in the flat layer 107 with a thickness of 2.3 ⁇ m and 1.5 ⁇ m, respectively.
  • the first via hole V 1 with a good morphology is formed in the flat layer 107 with two different thicknesses, indicating that the process of making the first via hole V 1 with a bottom diameter of 2.5 ⁇ m is stable and without abnormality.
  • the width of the second light shielding structure 106 shielding the first via hole V1 can be reduced from 7.0 ⁇ m to 6.5 ⁇ m, further improving the aperture ratio and transmittance.
  • the above-mentioned display substrate provided in the embodiments of the present disclosure, as shown in Figures 2 and 4, it may also include a gate insulating layer 109, a first interlayer dielectric layer 110, and a second interlayer dielectric layer 111 located between the layer where the first electrode 81 of the transistor 108 is located and the active layer 82 of the transistor 108.
  • the first electrode 81 of the transistor 108 is electrically connected to the active layer 82 of the transistor 108 through a second via hole V2 that penetrates the second interlayer dielectric layer 111, the first interlayer dielectric layer 110, and the gate insulating layer 109; optionally, as shown in Figure 5, the orthographic projection of the second via hole V2 on the first base substrate 101 is located within the orthographic projection of the second shading structure 106 on the first base substrate 101, so as to completely shield the second via hole V2 through the second shading structure 106 to avoid light leakage at the second via hole V2 .
  • the diameter of the second via hole V2 gradually increases.
  • the present disclosure is arranged on the same side of the symmetry axis AOS of the second shading structure 106 along the first direction X, and the extension distance d2 of the orthographic projection of the second shading structure 106 on the first base substrate 101 relative to the orthographic projection of the maximum diameter of the second via hole V2 on the first base substrate 101 is greater than or equal to 0.5 ⁇ m and less than 0.9 ⁇ m, for example 0.6 ⁇ m.
  • the maximum diameter of the second via hole V 2 has been extremely compressed to the limit of 1.9 ⁇ m for inorganic layer via holes, approaching the limit level of the exposure machine.
  • the line width of the first signal line 102 has been compressed from 3.5 ⁇ m to 2.0 ⁇ m, which has approached the lower limit of the characteristic of the limit channel width-to-length ratio and cannot be further compressed. Therefore, in order to further reduce the width of the second shading structure 106 that blocks the first signal line 102 and the second via hole V 2 , it is necessary to compress the distance between the second via hole V 2 and the first signal line 102.
  • the alignment method among the layer ILD 2 where the second via V 2 is located, the layer SD 1 where the second pole 83 of the transistor 108 is located, the layer NGT where the gate 84 of the transistor 108 is located, and the layer Poly where the active layer 82 of the transistor 108 is located is indirect alignment, and the corresponding alignment control method is shown in FIG11.
  • the layer NGT where the gate 84 of the transistor 108 is located and the layer Poly where the active layer 82 of the transistor 108 is located are aligned for the first time
  • the layer SD 1 where the second pole 83 of the transistor 108 is located and the layer Poly where the active layer 82 of the transistor 108 is located are aligned for the second time
  • the layer ILD 2 where the second via V 2 is located and the layer SD 1 where the second pole 83 of the transistor 108 is aligned for the third time can be achieved.
  • the minimum distance between the first signal line 102 (which may be located at the layer NGT where the gate 84 of the transistor 108 is located) and the second via hole V2 should be Among them, a is the length of the lightly doped region (LDD) of the active layer 80 in the transistor 108 in the second direction Y, b is 1/2 of the process fluctuation value of the first signal line 102 and the second via V2 , d is the alignment deviation between the layer NGT where the gate 84 of the transistor 108 is located and the layer Poly where the active layer 82 of the transistor 108 is located, e is the alignment deviation between the layer SD 1 where the second pole 83 of the transistor 108 is located and the layer Poly where the active layer 82 of the transistor 108 is located, and f is the alignment deviation between the layer ILD 2 where the second via V2 is located and the layer SD 1 where the second pole 83 of the transistor 108 is located.
  • LDD lightly doped region
  • the length a of the lightly doped region (LDD) of the active layer 80 in the second direction Y is 0.75 ⁇ m;
  • the control benchmark of the process fluctuation value and alignment deviation of each film layer in the display substrate is ⁇ 0.8 ⁇ m, which can be reduced to ⁇ 0.7 ⁇ m through strict control, so d, e, and f are all 0.7 ⁇ m to 0.8 ⁇ m, and the process fluctuation value of the first signal line 102 and the second via hole V2 is 0.7 ⁇ m to 0.8 ⁇ m, and accordingly, b is 0.35 ⁇ m to 0.4 ⁇ m.
  • the minimum distance between the first signal line 102 (which can be located in the layer NGT where the gate 84 of the transistor 108 is located) and the second via hole V2 in the related art is about 2.05 ⁇ m to 2.25 ⁇ m.
  • the total alignment deviation between the first signal line 102 and the second via hole V2 can be reduced by directly aligning the two, thereby reducing the distance between the two.
  • the orthographic projection of the first signal line 102 on the first base substrate 101 and the orthographic projection of the second via hole V2 on the first base substrate 101 are separated on both sides of the symmetry axis AOS extending along the first direction X of the second light shielding structure 106; in the second direction Y, the distance d3 between the orthographic projection of the first signal line 102 on the first base substrate 101 and the orthographic projection of the maximum aperture of the second via hole V2 on the first base substrate 101 can be approximately equal to (i.e., equal to or within the error range caused by factors such as manufacturing and measurement)
  • a is the length of the lightly doped region (LDD) of the active layer 80 in the transistor 108 in the second direction Y
  • b is 1/2 of the process fluctuation value of the first signal line 102 and the second via
  • the length a of the lightly doped region (LDD) of the active layer 80 in the second direction Y is 0.75 ⁇ m; the process fluctuation value of the first signal line 102 and the second via hole V2 is 0.7 ⁇ m to 0.8 ⁇ m, and accordingly, b is 0.35 ⁇ m to 0.4 ⁇ m; the alignment deviation of the first signal line 102 and the second via hole V2 is 0.7 ⁇ m to 0.8 ⁇ m, and combined with the formula It can be obtained that the distance d3 between the orthographic projection of the first signal line 102 on the first base substrate 101 and the orthographic projection of the second via hole V2 on the first base substrate 101 is about 1.6 ⁇ m to 1.7 ⁇ m.
  • the distance d3 of 1.6 ⁇ m to 1.7 ⁇ m between the first signal line 102 and the second via hole V2 in the present disclosure is smaller, which is conducive to reducing the width of the second light shielding structure 106 that shields the first signal line 102 and the second via hole V2 , and improving the aperture ratio and transmittance.
  • the distance of the second light shielding structure 106 beyond the first signal line 102 is more than 2.1 ⁇ m, so as to ensure that the second light shielding structure 106 completely shields the lightly doped region (LDD) and the channel region of the active layer 82, and ensures the characteristics of the transistor 108.
  • FIG12 and FIG13 respectively verify the distance ⁇ d between the second light shielding structure 106 and the first signal line 102 when the line width of the first signal line 102 (equivalent to the width of the gate 84 of the transistor 108) is 2.0 ⁇ m and 1.8 ⁇ m, and the leakage current I off under the condition of 2w of light.
  • ⁇ d greater than 0 indicates that the second light shielding structure 106 is extended compared with the first signal line 102
  • ⁇ d less than 0 indicates that the second light shielding structure 106 is retracted compared with the first signal line 102
  • ⁇ d equal to 0 indicates that the second light shielding structure 106 is flush with the first signal line 102.
  • M represents a solution in which the second light shielding structure 106 exceeds 2.1 ⁇ m relative to the first signal line 102 in the related art
  • N represents a solution in which the distance between the second light shielding structure 106 and the first signal line 102 is ⁇ d in the present disclosure.
  • Tables 1 and 2 respectively show the distance ⁇ d between the second light shielding structure 106 and the first signal line 102, the leakage current I off under the condition of 2w illumination, and the leakage current I off ' under the dark state (no illumination) condition when the line width of the first signal line 102 (equivalent to the width of the gate 84 of the transistor 108) is 2.0 ⁇ m and 1.8 ⁇ m. It can be seen from FIG. 12, FIG.
  • the present disclosure can compress the distance of the second shading structure 106 beyond the first signal line 21 from 2.1 ⁇ m to within 0.4 ⁇ m, for example, 0.3 ⁇ m, so as to minimize the shielding of the first signal line 102 by the second shading structure 106 on the basis of ensuring the characteristics of the transistor 108, thereby greatly improving the aperture ratio and transmittance.
  • the present disclosure can compress the distance of the second shading structure 106 beyond the first signal line 21 from 2.1 ⁇ m to within 0.4 ⁇ m, for example, 0.3 ⁇ m, so as to minimize the shielding of the first signal line 102 by the second shading structure 106 on the basis of ensuring the characteristics of the transistor 108, thereby greatly improving the aperture ratio and transmittance.
  • the orthographic projection of the first signal line 102 on the first substrate 101 is located on the side of the orthographic projection of the second shading structure 106 on the first substrate 101 along the symmetry axis AOS of the first direction X; on the same side of the symmetry axis AOS of the second shading structure 106 along the first direction X, the extension distance d4 of the orthographic projection of the second shading structure 106 on the first substrate 101 relative to the orthographic projection of the first signal line 102 on the first substrate 101 is greater than 0 ⁇ m and less than or equal to 0.4 ⁇ m, for example, 0.3 ⁇ m.
  • the orthographic projection of the first electrode 81 of the transistor 108 on the first base substrate 101 can be located within the orthographic projection of the second shading structure 106 on the first base substrate 101, so that in the first direction X, only the second shading structure 106 is used for shading, which is beneficial to maximizing the aperture ratio and transmittance in the first direction X.
  • a common electrode 112 located at a layer where multiple pixel electrodes 104 are located and away from the first base substrate 101 may also be included, and multiple first light shielding structures 105 are arranged in contact with the common electrode 112. Since the common electrodes 112 in the areas where the pixel electrodes 104 are located are integrally connected, even if the common electrodes 112 are in contact with multiple first light shielding structures 105, there will be no problem of short circuit of the common electrodes 112 in the areas where different pixel electrodes 104 are located. Based on this, multiple first light shielding structures 105 and the common electrode 112 can be in direct contact without providing an insulating layer therebetween, thereby minimizing the thickness and manufacturing process of the display substrate while achieving the first light shielding structure 105 to block light leakage.
  • multiple first shading structures 105 can be located on the side of the common electrode 112 facing the first base substrate 101; and the orthographic projections of the multiple first light shading structures 105 on the first base substrate 101 are located within the orthographic projection of the common electrode 112 on the first base substrate 101, and the common electrode 112 covers the side surfaces of the multiple first light shading structures 105, so as to avoid damage to the morphology of the first light shading structures 105 caused by the patterning process of the common electrode 112.
  • the plurality of first light shielding structures 105 may also be located on the side of the common electrode 112 away from the first base substrate 101; and in the gaps between the rows of pixel electrodes 104 extending in the second direction Y, the orthographic projections of the plurality of first light shielding structures 105 on the first base substrate 101 and the orthographic projections of the common electrode on the first base substrate 101 are substantially coincident, that is, the orthographic projections of the common electrode 112 on the first base substrate 101 and the orthographic projections of the first light shielding structures 105 on the first base substrate 101 may just coincide, or there may be non-overlapping parts within a reasonable process error range.
  • the film layer of the common electrode 112 and the film layer of the first light shielding structure 105 may be formed in sequence and then the patterning process may be performed, so that the self-alignment between the first light shielding structure 105 and the common electrode 112 can be achieved, so that there is no alignment offset between the first light shielding structure 105 and the common electrode 112.
  • the common electrode 112 may include a plurality of slits S extending along the second direction Y, and each pixel electrode 104 is arranged corresponding to at least one slit S.
  • the orthographic projections of the plurality of slits S on the first base substrate 101 and the orthographic projections of the plurality of first shading structures 105 on the first base substrate 101 do not overlap with each other, so as to avoid the first shading structures 105 blocking the slits S and ensure the transmittance at the slits S.
  • a buffer layer 113 in the display substrate provided in the embodiments of the present disclosure, as shown in FIG. 2 and FIG. 4 , a buffer layer 113, a passivation layer 114, etc. may also be included.
  • Other essential components in the display substrate are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.
  • the embodiment of the present disclosure provides a display device, as shown in FIG14, comprising a display substrate 001 and an opposite substrate 002 arranged opposite to each other, and a first liquid crystal layer 003 located between the display substrate 001 and the opposite substrate 002, wherein the display substrate 001 is the above-mentioned display substrate 001 provided in the embodiment of the present disclosure. Since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display substrate, the implementation of the display device provided in the embodiment of the present disclosure can refer to the implementation of the above-mentioned display substrate provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.
  • the opposing substrate 002 includes a black matrix BM, which may include a plurality of first black matrices BM 1 extending in the second direction Y and arranged in the first direction X, and the orthographic projection of the first light shading structure 105 on the first base substrate 101 may be located within the orthographic projection of the first black matrix BM 1 on the first base substrate 101 to avoid the first light shading structure 105 affecting the aperture ratio and transmittance in the second direction Y.
  • BM black matrix BM
  • the black matrix BM may further include a plurality of second black matrices BM 2 extending in the first direction X and arranged in the second direction Y, the orthographic projection of the second black matrix BM 2 on the first base substrate 101 is located within the orthographic projection of the second light shielding structure 107 on the first base substrate 101; the width of the second black matrix BM 2 in the second direction Y is greater than or equal to the width of the minimum aperture (i.e., bottom aperture) of the first via hole V 1 in the second direction Y and less than the width of the maximum aperture (i.e., top aperture) of the first via hole V 1 in the second direction Y.
  • the present disclosure adopts the second light shielding structure 106 in the first direction X to meet the light shielding requirements, therefore, the second black matrix BM 2 extending in the first direction X can be designed to be reduced, for example, the width of the second black matrix BM 2 in the second direction Y is greater than or equal to 3.0 ⁇ m and less than or equal to 5.0 ⁇ m, and the main function of the second black matrix BM 2 is changed from light shielding to reducing the reflectivity in the first direction X.
  • the orthographic projection of the symmetry axis of the second black matrix BM2 extending along the first direction X on the first base substrate 101 can be set to roughly coincide with the orthographic projection of the symmetry axis AOS of the second shading structure 106 extending along the first direction X on the first base substrate 101, that is, they just coincide or are within the error range caused by factors such as manufacturing process and measurement.
  • the counter substrate 002 may further include a color resist CF and a frame sealant SA, wherein the color resist CF may be disposed in an opening defined by the first black matrix BM 1 and the second black matrix BM 2.
  • Other essential components of the counter substrate are well understood by those skilled in the art, and are not described in detail herein, nor should they be used as limitations to the present disclosure.
  • a backlight module BLU may also be included which is located on the side of the display substrate 001 away from the opposite substrate 002.
  • the backlight module BLU may be a direct-type backlight module or an edge-entry backlight module.
  • the edge-entry backlight module may include a light bar, a reflective sheet arranged in layers, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate.
  • the direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film arranged in layers on the light emitting side of the matrix light source, and the reflective sheet includes an opening arranged directly opposite to the position of each lamp bead in the matrix light source.
  • the lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).
  • micro-LEDs are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of micro-LEDs is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting diodes that emit light based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving the screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlighting between the bright and dark areas of the screen, optimizing the visual experience.
  • OLEDs organic light-emitting diodes
  • the display device provided by the embodiment of the present disclosure may be a 3D display device.
  • the 3D display device may further include a liquid crystal grating 004 located between the backlight module BLU and the display substrate 001.
  • the liquid crystal grating 004 may be fixed to the display substrate 001 through an adhesive layer 005.
  • the liquid crystal grating 004 may be controlled to form light-transmitting areas and light-shielding areas arranged alternately, so that the viewer's left eye sees the left eye image displayed by the display panel PNL (including the display substrate 001, the opposite substrate 002, the first liquid crystal layer 003, the frame sealant SA, etc.) through the light-transmitting area of the liquid crystal grating 004, and the right eye sees the right eye image displayed by the display panel PNL through the light-transmitting area.
  • the liquid crystal grating 004 By arranging the liquid crystal grating 004 on the light-incident side of the display panel PNL, when the display panel PNL includes a touch electrode, the liquid crystal grating 004 will not shield the touch electrode, thereby avoiding the problem of touch failure, thereby improving the touch sensitivity and accuracy.
  • the liquid crystal grating 004 may include a third substrate 401 and a fourth substrate 402 disposed opposite to each other, a second liquid crystal layer 403 located between the third substrate 401 and the fourth substrate 402, a first strip electrode 404 located on a side of the third substrate 401 facing the second liquid crystal layer 403, a second strip electrode 405 located on a side of the layer where the first strip electrode 404 is located facing the second liquid crystal layer 403, a planar electrode 406 located on a side of the fourth substrate 402 facing the second liquid crystal layer 403, a first transistor T 1 electrically connected to the first strip electrode 404, a second transistor T 2 electrically connected to the second strip electrode 405, and a sealing glue SA surrounding the second liquid crystal layer 403 between the third substrate 401 and the fourth substrate 402.
  • the second liquid crystal layer 403 can be controlled to form a light-transmitting area and a light-shielding area, so as to cooperate with the liquid crystal display panel PNL that outputs left-eye images and right-eye images to achieve 3D display.
  • the display device provided by the embodiment of the present disclosure may be a 3D display device.
  • the 3D display device may further include a light splitting component 006 located on the light-emitting side of the display panel PNL.
  • the light splitting component 006 includes a plurality of light splitting structures 601 arranged parallel to each other and side by side.
  • the light splitting structure 601 may be a composite lens formed by a high-refractive resin layer 601a and a low-refractive resin layer 601b.
  • the high-refractive resin layer 601a is composed of a plurality of cylindrical lenses, and the low-refractive resin layer 601b fills the gap between each cylindrical lens and the thickness of the low-refractive resin layer is greater than the arch height of the cylindrical lens.
  • the cylindrical lens may be an angular or non-angular structure.
  • the composite lens may be a substrate 602 made of a transparent material.
  • the material of the substrate 602 may be polyethylene terephthalate (PET).
  • PET polyethylene terephthalate
  • a spacer glass 007 may be provided between the display panel PNL and the light splitting component 006, and the spacer glass 007 and the light splitting component 006 may be bonded and fixed by an optical adhesive 008.
  • the image plane of the display panel PNL is set on the focal plane of the cylindrical lens, and the pixels under each cylindrical lens are divided into several sub-pixels.
  • the pixels at different positions on the display panel PNL are refracted and split by the cylindrical lens, and the light path changes to form different viewpoints in space.
  • the left eye receives the left viewpoint image
  • the right eye also receives the right viewpoint image, thereby realizing 3D display.
  • FIG. 18 and FIG. 19 specifically illustrate that the display device provided by the present disclosure is applied to virtual reality (VR) glasses.
  • the virtual reality glasses shown in FIG. 18 include two display screens L and R, and different pictures are provided for the left eye and the right eye through the two display screens L and R to realize virtual reality display; the two display screens L and R respectively include the above-mentioned display substrate provided in the embodiment of the present disclosure.
  • the virtual reality glasses shown in FIG. 18 include two display screens L and R, and different pictures are provided for the left eye and the right eye through the two display screens L and R to realize virtual reality display; the two display screens L and R respectively include the above-mentioned display substrate provided in the embodiment of the present disclosure.
  • the display area AA of the display screen includes an effective pixel area P and a virtual pixel area D, wherein the effective pixel area P can display the picture, and the virtual pixel area D cannot display the picture, and the virtual pixel area D is used to prevent the film layer of the effective pixel area P from being broken.
  • the effective pixel area P includes a left eye pixel area PL and a right eye pixel area PR , and the left eye pixel area PL and the right eye pixel area PR respectively display different pictures to realize virtual reality display.
  • the left eye pixel area PL and the right eye pixel area PL are regular octagons
  • the display area AA is an octagon.
  • the left eye pixel area PL , the right eye pixel area PL and the display area AA can also have other shapes, which are not specifically limited here.
  • the virtual reality glasses may further include a first gate drive circuit GOA 1 , a second gate drive circuit GOA 2 , a test circuit CT, and a multiplexer circuit MUX disposed around the display area AA.
  • Other essential components of the virtual reality glasses are well understood by those skilled in the art, and are not described in detail herein, nor should they be used as limitations to the present disclosure.
  • the display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.
  • the display device provided in the embodiments of the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip.
  • control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like.
  • the control chip may also include a memory, and may also include a power module, and the like, and realize power supply and signal input and output functions through additionally provided wires, signal lines, and the like.
  • the control chip may also include a hardware circuit and a computer executable code, and the like.
  • the hardware circuit may include a conventional very large scale integrated (VLSI) circuit or gate array and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, and the like.
  • VLSI very large scale integrated
  • the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure.
  • the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.
  • the embodiment of the present disclosure provides a motherboard, as shown in FIG20, comprising a plurality of display substrates 001, the display substrates 001 being the above-mentioned display substrates 001 provided in the embodiment of the present disclosure, and the first base substrates 101 of each display substrate 001 forming a base substrate 100 of an integrated structure. Since the principle of solving the problem by the motherboard is similar to the principle of solving the problem by the above-mentioned display substrate, the implementation of the motherboard provided in the embodiment of the present disclosure can refer to the implementation of the above-mentioned display substrate provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.
  • the display substrate 001 includes a display area AA and a frame area BA located on at least one side of the display area AA, and the motherboard includes a gap GA between adjacent display substrates 001.
  • the motherboard may include a plurality of first alignment marks MK 1 as shown in FIG. 19, and the plurality of first alignment marks MK 1 are located in the frame area BA and/or the gap GA between adjacent display substrates 001. It should be noted that after the motherboard is cut into a plurality of display substrates 001, the first alignment mark MK 1 located in the frame area BA may be retained, and the first alignment mark MK 1 located in the gap GA between adjacent display substrates 001 is cut off.
  • the first alignment mark MK 1 may include a first sub-alignment pattern MK 11 , a second sub-alignment pattern MK 12 , and a third sub-alignment pattern MK 13 , wherein the first sub-alignment pattern MK 11 includes a first hollow structure H 1 , the orthographic projection of the second sub-alignment pattern MK 12 on the base substrate 100 is located within the orthographic projection of the first hollow structure H 1 on the base substrate 100, and the orthographic projection of the third sub-alignment pattern MK 13 on the base substrate 100 is located within the orthographic projection of the second sub-alignment pattern MK 12 on the base substrate 100.
  • the first sub-alignment pattern MK 11 is provided in the same layer and material as the first signal line 102
  • the second sub-alignment pattern MK 12 is provided in the same layer and material as the second signal line 103
  • the third sub-alignment pattern MK 13 is provided in the same layer and material as the second interlayer dielectric layer 111.
  • the first sub-alignment pattern MK 11 and the third sub-alignment pattern MK 13 can be used to realize direct alignment between the second via hole V 2 penetrating the second interlayer dielectric layer 111 and the first signal line 102, ensuring that the second via hole V 2 will not overlap the first signal line 102; and the second sub-alignment pattern MK 12 and the third sub-alignment pattern MK 13 can be used to realize direct alignment between the second via hole V 2 and the second signal line 103, ensuring that the second via hole V 2 will not overlap the second signal line 103. Since direct alignment involves only one alignment and indirect alignment involves at least two direct alignments, the deviation of direct alignment is smaller than the deviation of indirect alignment.
  • the second via hole V2 is directly aligned with the first signal line 102 and the second signal line 103, respectively, so as to ensure that the alignment deviation between the second via hole V2 and the first signal line 102, and the alignment deviation between the second via hole V2 and the second signal line 103 are both small, so that the distance between the second via hole V2 and the first signal line 102, and the distance between the second via hole V2 and the second signal line 103 can be compressed to the process limit, thereby ensuring that more space can be used to set the pixel electrode 104, which is conducive to improving the aperture ratio.
  • “same layer, same material setting” refers to using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to a mask (also called a photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.
  • the layer CM where the first light shielding structure 105 is located can be directly aligned with the layer 1ITO where the pixel electrode 104 is located, and after the layer 1ITO where the pixel electrode 104 is located is directly aligned with the layer SD 1 where the second signal line 103 is located, the indirect alignment of the layer CM where the first light shielding structure 105 is located with the layer SD 1 where the second signal line 103 is located can be achieved, but in this case, the alignment deviation between the layer CM where the first light shielding structure 105 is located and the layer SD 1 where the second signal line 103 is located is large, and the loss of the aperture ratio is large.
  • the layer CM where the first light shielding structure 105 is located is directly aligned with the layer SD 1 where the second signal line 103 is located, which can ensure that the alignment deviation between the layer CM where the first light shielding structure 105 is located and the layer SD 1 where the second signal line 103 is located is small, which is conducive to improving the aperture ratio.
  • a plurality of second alignment marks MK 2 as shown in FIG. 24 may also be provided.
  • the plurality of second alignment marks M 2 may be located in the frame area BA of the display substrate 001 and/or in the gap GA between adjacent display substrates 001.
  • the second alignment mark MK 2 includes a fourth sub-alignment pattern MK 21 and a fifth sub-alignment pattern MK 22 , and the orthographic projection of the fifth sub-alignment pattern MK 22 on the base substrate 101 is located within the orthographic projection of the fourth sub-alignment pattern MK 21 on the base substrate 101.
  • the fourth sub-alignment pattern MK 21 is provided in the same layer and the same material as the second signal line 103
  • the fifth sub-alignment pattern MK 22 is provided in the same layer and the same material as the first light shielding structure 105, so that the fourth sub-alignment pattern MK 21 and the fifth sub-alignment pattern MK 22 can be used to realize direct alignment of the second signal line 103 with the first light shielding structure 105, thereby improving the aperture ratio.
  • the insulating layers on the side of the layer where the second signal line 103 is located facing the layer where the first light shielding structure 105 is located are sequentially the second interlayer dielectric layer 111, the flat layer 107, and the passivation layer 114.
  • the flat layer 107 between the fourth sub-alignment pattern MK 21 and the fifth sub-alignment pattern MK 22 can be removed, so that only the second interlayer dielectric layer 111 and the passivation layer 114 are provided between the fourth sub-alignment pattern MK 21 and the fifth sub-alignment pattern MK 22 , so as to ensure the accuracy of the alignment device in grasping the fourth sub-alignment pattern MK 21 and the fifth sub-alignment pattern MK 22 .
  • Motherboard alignment is to attach the display substrate 001 and the counter substrate 002 together under vacuum conditions to form a complete optical system.
  • the accuracy of the alignment will directly affect the product aperture ratio and transmittance stability.
  • the actual shading layer on the display substrate 001 is the first shading structure 105.
  • the first shading structure 105 by directly aligning the layer SD1 where the second signal line 103 is located with the first black matrix BM1 (belonging to the black matrix BM), and then by directly aligning the layer SD1 where the second signal line 103 is located with the layer 1ITO where the pixel electrode 104 is located, and directly aligning the layer 1ITO where the pixel electrode 104 is located with the layer where the first shading structure 105 is located, the first shading structure 105 and the first black matrix BM1 can be indirectly aligned, and X1 in FIG22 represents the alignment deviation between the second signal line 103 and the first black matrix BM1 , X2 represents the alignment deviation between the pixel electrode 104 and the first black matrix BM1 , and X3 represents the alignment deviation between the first shading structure 105 and the first black matrix BM1 .
  • this indirect alignment method will cause a large alignment deviation X3 between the first light shielding structure 105 and the first black matrix BM1 , and the two cannot overlap effectively, thereby affecting the stability of the aperture ratio.
  • the first light shielding structure 105 layer CM is directly aligned with the first black matrix BM1 (belonging to the black matrix BM), and the first light shielding structure 105 layer CM is directly aligned with the second signal line 103.
  • the alignment deviation X3 between the first light shielding structure 105 and the first black matrix BM1 , and the alignment deviation X1 between the second signal line 103 and the first black matrix BM1 are both small. Therefore, the direct alignment method of the first light shielding structure 105 and the first black matrix BM1 shown in FIG. 23 can be adopted in the present disclosure to make the alignment deviation between the two smaller, and the impact on the aperture ratio is also smaller.
  • the motherboard can also include a plurality of opposing substrates 002 arranged opposite to the plurality of display substrates 001, the second base substrates 201 of the plurality of opposing substrates 002 are integrally arranged, and the opposing substrate 002 includes a black matrix BM; and as shown in Figures 25 to 27, the motherboard is provided with a plurality of third alignment marks MK 3 , the third alignment mark MK 3 includes a sixth sub-alignment pattern MK 31 provided in the same layer and material as the black matrix BM, and a seventh sub-alignment pattern MK 32 provided in the same layer and material as the first light shielding structure 105, the seventh sub-alignment pattern MK 32 includes a second hollow structure H 2 , the orthographic projection of the sixth sub-alignment pattern MK 31 on the base substrate 100 is located within the orthographic projection of the second hollow structure H 2 on the base substrate 100, the provision of the second hollow structure H 2
  • a plurality of third alignment marks MK 3 may be located in the frame area of the opposing substrate 002 and/or in the gap between adjacent opposing substrates 002.
  • the frame area of the opposing substrate 002 is set corresponding to the frame area BA of the display substrate 001
  • the gap between adjacent opposing substrates 002 is set corresponding to the gap GA between adjacent display substrates 001.
  • FIG. 25 shows that the third alignment mark MK 3 is located in the gap between adjacent opposing substrates 002 (corresponding to the gap GA between adjacent display substrates 001).
  • the third alignment mark MK 3 may include the third alignment mark MK 3 ' for fine alignment shown in Figure 26 and the third alignment mark MK 3 ' for coarse alignment shown in Figure 27.
  • the difference between the two third alignment marks MK 3 is that the size of the third alignment mark MK 3 ' for fine alignment is smaller than that of the third alignment mark K 3 ' for coarse alignment.
  • the side length l 1 of the sixth sub-alignment pattern MK 31 in the third alignment mark MK 3 ' for fine alignment is 1/2 of that in the third alignment mark MK 3 ' for coarse alignment
  • the physical width l 2 of the seventh sub-alignment pattern MK 32 in the third alignment mark MK 3 ' for fine alignment is 3/5 of that in the third alignment mark MK 3 ' for coarse alignment.
  • a plurality of fourth alignment marks may be further provided.
  • the plurality of fourth alignment marks are substantially evenly distributed at the gap GA between the display substrates 001.
  • the fourth alignment marks are provided in the same layer and the same material as the first light shielding structure 105.
  • the fourth alignment marks are configured to measure the deviation of the actual position of the seventh sub-alignment pattern M32 relative to the preset position, so as to adaptively adjust the position of the sixth sub-alignment pattern M31 on the opposite substrate 002 according to the deviation.
  • the position of the sixth sub-alignment pattern M31 on the opposite substrate 002 needs to be adaptively adjusted to the left by 1 ⁇ m accordingly, so that the relative position of the sixth sub-alignment pattern M31 and the seventh sub-alignment pattern M32 can be ensured to remain unchanged, and finally the first black matrix BM1 and the first light shielding structure 105 are accurately aligned through the sixth sub-alignment pattern M31 and the seventh sub-alignment pattern M32 .

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Abstract

本公开提供的显示基板、显示装置及母板，包括第一衬底基板，在第一衬底基板的同侧异层设置的多条第一信号线和多条第二信号线，各第一信号线沿第一方向延伸并沿与第一方向交叉的第二方向排列，各第二信号线沿第二方向延伸并沿第一方向排列；多个像素电极，位于第一信号线和第二信号线所在层之上，多个像素电极在第一衬底基板上的正投影位于由各第一信号线与各第二信号线交叉限定区域的正投影内；多个第一遮光结构，位于像素电极所在层之上，各第一遮光结构沿第二方向延伸且沿第一方向排列，第一遮光结构在第一衬底基板上的正投影位于在第二方向上延伸的各排像素电极之间的间隙正投影内且与第二信号线的正投影具有互不交叠的区域。

Description

显示基板、显示装置及母板 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示装置及母板。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有重量轻、耗电少、画质高、辐射低和携带方便等优点，已逐渐取代传统的阴极射线管显示装置(Cathode Ray Tube display，CRT)，而被广泛应用于现代化信息设备，如虚拟现实(VR)头戴式显示设备、笔记本电脑、电视、移动电话和数字产品等。
发明内容
本公开实施例提供的显示基板、显示装置及母板，具体方案如下：
一方面，本公开实施例提供了一种显示基板，包括：
第一衬底基板；
多条第一信号线，位于所述第一衬底基板的一侧，所述多条第一信号线沿第一方向延伸并沿第二方向排列，所述第一方向和所述第二方向交叉；
多条第二信号线，与所述多条第一信号线异层设置在所述第一衬底基板的同一侧，所述多条第二信号线沿所述第二方向延伸并沿所述第一方向排列；
多个像素电极，位于所述多条第一信号线所在层、以及所述多条第二信号线所在层背离所述第一衬底基板的一侧，所述多个像素电极在所述第一衬底基板上的正投影位于由所述多条第一信号线在所述第一衬底基板上的正投影与所述多条第二信号线在所述第一衬底基板上的正投影交叉限定的区域内；
多个第一遮光结构，位于所述多个像素电极所在层背离所述第一衬底基板的一侧，所述多个第一遮光结构沿所述第二方向延伸并沿所述第一方向排列，所述多个第一遮光结构在所述第一衬底基板上的正投影位于在所述第二 方向上延伸的各排所述像素电极之间的间隙在所述第一衬底基板上的正投影内，所述多个第一遮光结构在所述第一衬底基板上的正投影与所述多条第二信号线在所述第一衬底基板上的正投影具有互不交叠的区域。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述多条第二信号线在所述第一衬底基板上的正投影位于所述多个第一遮光结构在所述第一衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述多条第一信号线所在层、以及所述多条第二信号线所在层与所述第一衬底基板之间的多个第二遮光结构，所述多个第二遮光结构沿所述第一方向延伸并沿所述第二方向排列；
所述多条第一信号线在所述第一衬底基板上的正投影位于所述多个第二遮光结构在所述第一衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一信号线在所述第一衬底基板上的正投影位于所述第二遮光结构沿所述第一方向延伸的对称轴在所述第一衬底基板上正投影的一侧；
在所述第二遮光结构沿所述第一方向延伸的对称轴的同侧，所述第二遮光结构在所述第一衬底基板上正投影相对于所述第一信号线在所述第一衬底基板上的正投影的外延距离大于0μm且小于等于0.4μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述第一衬底基板与所述多个像素电极所在层之间的多个晶体管，以及位于所述多个晶体管所在层与所述多个像素电极所在层之间的平坦层，所述晶体管的第一极通过贯穿所述平坦层的第一过孔与所述像素电极电连接；
所述第一过孔在所述第一衬底基板上的正投影位于所述第二遮光结构在所述第一衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二遮光结构沿所述第一方向延伸的对称轴在所述第一衬底基板上的正投影与所述第二遮光结构沿所述第一方向延伸的对称轴在所述第一衬底基板上的正投影 大致重合。
在一些实施例中，在本公开实施例提供的上述显示基板中，在所述第二遮光结构沿所述第一方向延伸的对称轴的同侧，在所述第二遮光结构远离所述第一衬底基板的方向上，所述第一过孔的口径逐渐增大，所述第二遮光结构在所述第一衬底基板上的正投影相对于所述第一过孔的最大口径在所述第一衬底基板上的正投影的外延距离大于等于0.8μm且小于等于1.0μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述平坦层在垂直于所述第一衬底基板方向上的厚度大于等于1.2μm且小于等于1.8μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述晶体管的第一极所在层与所述晶体管的有源层之间的栅绝缘层、第一层间介质层和第二层间介质层，所述晶体管的第一极通过贯穿所述第二层间介质层、所述第一层间介质层和所述栅绝缘层的第二过孔与所述晶体管的有源层电连接；
所述第二过孔在所述第一衬底基板上的正投影位于所述第二遮光结构在所述第一衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一信号线在所述第一衬底基板上的正投影与所述第二过孔在所述第一衬底基板上的正投影分居在所述第二遮光结构沿所述第一方向延伸的对称轴的两侧；
在所述第二遮光结构远离所述第一衬底基板的方向上，所述第二过孔的口径逐渐增大；在所述第二方向上，所述第一信号线在所述第一衬底基板上的正投影与所述第二过孔的最大口径在所述第一衬底基板上的正投影之间的距离大致等于
Figure PCTCN2022127461-appb-000001
其中，a为所述晶体管中有源层的轻掺杂区在所述第二方向上的长度，b为所述第一信号线、所述第二过孔的工艺波动值的1/2，c为所述第一信号线与所述第二过孔的对位偏差。
在一些实施例中，在本公开实施例提供的上述显示基板中，在所述第二遮光结构沿所述第一方向延伸的对称轴的同侧，所述第二遮光结构在所述第一衬底基板上正投影相对于所述第二过孔的最大口径在所述第一衬底基板上 的正投影的外延距离大于等于0.5μm且小于0.9μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述晶体管的第一极在所述第一衬底基板上的正投影位于所述第二遮光结构在所述第一衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述多个像素电极所在层远离所述第一衬底基板一侧的公共电极，所述多个第一遮光结构与所述公共电极接触设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述多个第一遮光结构位于所述公共电极朝向所述第一衬底基板的一侧；
所述多个第一遮光结构在所述第一衬底基板上的正投影位于所述公共电极在所述第一衬底基板上的正投影内，所述公共电极覆盖所述多个第一遮光结构的侧面。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述多个第一遮光结构位于所述公共电极远离所述第一衬底基板一侧；
在所述第二方向上延伸的各排所述像素电极之间的间隙处，所述多个第一遮光结构在所述第一衬底基板上的正投影与所述公共电极在所述第一衬底基板上的正投影大致重合。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述公共电极包括沿所述第二方向延伸的多个狭缝，每个所述像素电极与至少一个所述狭缝对应设置，所述多个狭缝在第一衬底基板上的正投影与所述多个第一遮光结构在第一衬底基板上的正投影互不交叠。
另一方面，本公开实施例提供了一种显示装置，包括相对而置的显示基板和对向基板，以及位于所述显示基板与所述对向基板之间的液晶层，其中，所述显示基板为本公开实施例提供的上述显示基板。
在一些实施例中，在本公开实施例提供的上述显示装置中，所述对向基板包括黑矩阵，所述黑矩阵包括在第二方向上延伸且在第一方向上排列的多个第一黑矩阵，第一遮光结构在所述第一衬底基板上的正投影位于所述第一 黑矩阵在所述第一衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示装置中，所述对向基板包括黑矩阵，所述黑矩阵包括在第一方向上延伸且在第二方向上排列的多个第二黑矩阵，所述第二黑矩阵在所述第一衬底基板上的正投影位于第二遮光结构在所述第一衬底基板上的正投影内；
在第二遮光结构远离所述第一衬底基板的方向上，贯穿平坦层的第一过孔的口径逐渐增大，且所述第二黑矩阵在所述第二方向上的宽度大于等于所述第一过孔在所述第二方向上的最小口径且小于所述第一过孔在所述第二方向上的最大口径。
在一些实施例中，在本公开实施例提供的上述显示装置中，所述第二黑矩阵沿所述第一方向延伸的对称轴在所述第一衬底基板上的正投影与所述第二遮光结构沿所述第一方向延伸的对称轴在所述第一衬底基板上的正投影大致重合。
另一方面，本公开实施例提供了一种母板，包括多个显示基板，所述显示基板为本公开实施例提供的上述显示基板，各所述显示基板的第一衬底基板构成一体结构的衬底基板。
在一些实施例中，在本公开实施例提供的上述母板中，所述显示基板包括显示区、以及位于所述显示区至少一侧的边框区；所述母板还包括多个第一对位标识，所述多个第一对位标识位于所述边框区和/或相邻所述显示基板的间隙处；
所述第一对位标识包括与第一信号线同层、同材料设置的第一子对位图案、与第二信号线同层、同材料设置的第二子对位图案、以及与第二层间介质层同层、同材料设置的第三子对位图案，其中，所述第一子对位图案包括第一镂空结构，所述第二子对位图案在所述衬底基板上的正投影位于所述第一镂空结构在所述衬底基板上的正投影内，所述第三子对位图案在所述衬底基板上的正投影位于所述第二子对位图案在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述母板中，还包括多个第二 对位标识，所述多个第二对位标识位于所述边框区和/或相邻所述显示基板的间隙处；
所述第二对位标识包括与第二信号线同层、同材料设置的第四子对位图案、以及与第一遮光结构同层、同材料设置的第五子对位图案，其中，所述第五子对位图案在所述衬底基板上的正投影位于所述第四子对位图案在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述母板中，所述第二信号线所在层朝向所述第一遮光结构所在层一侧的绝缘层依次设置为第二层间介质层、平坦层和钝化层；所述第四子对位图案与所述第五子对位图案之间仅设置有所述钝化层和所述第二层间介质层。
在一些实施例中，在本公开实施例提供的上述母板中，还包括与所述多个显示基板相对而置的多个对向基板，所述多个对向基板的第二衬底基板一体设置，所述对向基板包括黑矩阵；
所述母板还包括多个第三对位标识，所述多个第三对位标识位于所述对向基板的边框区和/或相邻所述对向基板的间隙处，所述第三对位标识包括与所述黑矩阵同层、同材料设置的第六子对位图案、以及与所述第一遮光结构同层、同材料设置的第七子对位图案，所述第七子对位图案包括第二镂空结构，所述第六子对位图案在所述衬底基板上的正投影位于所述第二镂空结构在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述母板中，还包括多个第四对位标识，所述多个第四对位标识在所述显示基板之间的间隙处大致均匀分布，所述第四对位标识与第一遮光结构同层、同材料设置，所述第四对位标识被配置为衡量所述第七子对位图案的实际位置相对于预设位置的偏差。
附图说明
图1为本公开实施例提供的显示基板的一种结构示意图；
图2为沿图1中I-I’线的截面图；
图3为本公开实施例提供的显示基板的又一种结构示意图；
图4为沿图3中II-II’线的截面图；
图5为本公开实施例提供的显示基板的又一种结构示意图；
图6为沿图5中III-III’线的截面图；
图7为相关技术中显示基板的一种结构示意图；
图8为沿图7中IV-IV’线的截面图；
图9为相关技术中平坦层的第一过孔的图片；
图10为本公开实施例提供的平坦层的第一过孔的图片；
图11为相关技术中显示基板的部分膜层的对位方式示意图；
图12为第二遮光结构第一信号线之间的距离与晶体管的漏电流之间的一种关系图；
图13为第二遮光结构第一信号线之间的距离与晶体管的漏电流之间的又一种关系图；
图14为本公开实施例提供的显示装置的一种结构示意图；
图15为本公开实施例提供的显示装置的又一种结构示意图；
图16为本公开实施例提供的显示装置的又一种结构示意图；
图17为本公开实施例提供的显示装置的又一种结构示意图；
图18为本公开实施例提供的显示装置的又一种结构示意图；
图19为本公开实施例提供的显示装置的又一种结构示意图；
图20为本公开实施例提供的母板的一种结构示意图；
图21为本公开实施例提供的第一对位标识的结构示意图；
图22为本公开实施例提供的显示基板与对向基板之间、以及显示基板中部分膜层之间的一种对位示意图；
图23为本公开实施例提供的显示基板与对向基板之间、以及显示基板中部分膜层之间的另一种对位示意图；
图24为本公开实施例提供的第二对位标识的结构示意图；
图25为本公开实施例提供的母板的又一种结构示意图；
图26为本公开实施例提供的第三对位标识的一种结构示意图；
图27为本公开实施例提供的第三对位标识的又一种结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
近年来，随着VR应用领域的多元化拓展，VR产品需求增长迅速。相关技术中高分辨率的VR产品大多采用液晶显示面板。为了更好的浸入式体验，减少使用中的纱窗效应，VR产品的分辨率(PPI)不断提升，在分辨率不断提升的同时，像素间距(Pixel Pitch)也不断被压缩，相应的，黑矩阵的尺寸也被压缩。受对位设备工艺能力影响，当显示基板与对向基板之间出现对位偏差时，黑矩阵无法有效遮挡像素间距处的漏光，导致串色，影响显示效果，影响用户体验。
为了改善相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图1至图4所示，包括：
第一衬底基板101；
多条第一信号线102，位于第一衬底基板101的一侧，多条第一信号线102沿第一方向X延伸并沿第二方向Y排列，第一方向X和第二方向Y交叉；
多条第二信号线103，与多条第一信号线102异层设置在第一衬底基板101的同一侧，多条第二信号线103沿第二方向Y延伸并沿第一方向X排列；
多个像素电极104，位于多条第一信号线102所在层、以及多条第二信号线103所在层背离第一衬底基板101的一侧，多个像素电极104在第一衬底基板101上的正投影位于由多条第一信号线102在第一衬底基板101上的正投影与多条第二信号线103在第一衬底基板101上的正投影交叉限定的区域内；
多个第一遮光结构105，位于多个像素电极104所在层背离第一衬底基板101的一侧，多个第一遮光结构105沿第二方向Y延伸并沿第一方向X排列，多个第一遮光结构105在第一衬底基板101上的正投影位于在第二方向Y上延伸的各排像素电极104之间的间隙在第一衬底基板101上的正投影内，且多个第一遮光结构105在第一衬底基板101上的正投影与多条第二信号线103在第一衬底基板101上的正投影具有互不交叠的区域。
在本公开实施例提供的上述显示基板中，通过增设第一遮光结构105，并设置第一遮光结构105在第一衬底基板101上的正投影与多条第二信号线103在第一衬底基板101上的正投影具有互不交叠的区域，使得在显示基板上沿第二方向Y可通过第一遮光结构105与第二信号线103共同遮光，降低在第二方向Y上延伸的各排像素电极104之间的间隙处的漏光风险，改善串色不良，提高显示效果，提升用户体验。
对于高分辨率的显示产品，在数据线方向上延伸的像素间距通常较小，相应地在数据线方向上延伸的黑矩阵宽度较小，当显示基板与对向基板出现对位偏差时，在数据线方向上延伸的黑矩阵无法有效遮挡在数据线方向上延伸的像素间隙处的漏光，容易发生串色现象。基于此，本公开中第一信号线102可为栅线(gate line)，第二信号线103可为数据线(data line)，这样在对 向基板与显示基板出现对位偏差时，第一遮光结构105、数据线与黑矩阵可以共同对在第二方向Y上延伸的像素间隙处的漏光进行遮挡，有效改善单独采用黑矩阵遮光的相关方案中因对位偏差造成的串色不良。需要说明的是，为便于理解，下文以第一信号线102为栅线(gate line)，第二信号线103为数据线(data line)为例对本公开的技术方案进行介绍。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1和图3所示，多条第二信号线103在第一衬底基板101上的正投影可以位于多个第一遮光结构105在第一衬底基板101上的正投影内，在此情况下，在第二方向Y上，实际起到遮光作用的即为第一遮光结构105。相较于第一遮光结构105在第一衬底基板101上的正投影与第二信号线102在第一衬底基板101上的正投影互不交叠，需采用第一遮光结构105与第二信号线102协同遮光的方案，在单独采用覆盖第二信号线102的第一遮光结构105进行遮光的方案中，第一遮光结构105的线宽较大、利于制作，同时无需考虑第一遮光结构105与第二信号线102之间的协同遮光效果，利于简便设计。
在相关VR产品中，在栅线方向(例如第一方向X)上，显示基板的栅线被对向基板的黑矩阵遮挡，因此在栅线方向(例如第一方向X)上的实际遮光层为黑矩阵，黑矩阵的尺寸(CD)设计大小直接影响像素的透过率和开口率。在实际设计和工艺中，要求显示基板与对向基板的对位水平必须在一定的设计范围内，进而在栅线方向(例如第一方向X)上，尽量减小因栅线和黑矩阵的对位误差导致的开口率及透过率存在差异引起的光学性能不稳定。具体而言，受液晶盒对位设备的工艺能力影响，当显示基板与对向基板之间的对位发生波动时，黑矩阵可能无法有效遮挡栅线，致使遮光面积增大，产品开口率不足、透过率不足、亮度不均一。
基于此，为了提高栅线方向(例如第一方向X)上的开口率和透过率，如图5和图6所示，在本公开实施例提供的上述显示基板中，可以在多条第一信号线102所在层、以及多条第二信号线103所在层与第一衬底基板101之间设置沿第一方向X(相当于栅线方向)延伸且沿第二方向Y(相当于数 据线方向)排列的多个第二遮光结构106，多条第一信号线102在第一衬底基板101上的正投影位于多个第二遮光结构106在第一衬底基板101上的正投影内，即将第一方向X(相当于栅线方向)上的实际遮光层由对向基板的黑矩阵BM变更为显示基板上的第二遮光结构106。相比显示基板与对向基板之间对位波动(±1.5μm)较大的情况，相关技术中显示基板上各膜层之间的直接对位可以精确管控到±0.8μm以内。因此当第一方向X(相当于栅线方向)上的实际遮光层替换为第二遮光结构106时，可有效提升开口率和透过率。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图4所示，在第一衬底基板101与多个像素电极104所在层之间具有平坦层107，在平坦层107与第一衬底基板101之间具有多个晶体管108，晶体管108的第一极81通过贯穿平坦层107的第一过孔V 1与像素电极104电连接；可选地，如图5和图6所示，第一过孔V 1在第一衬底基板101上的正投影位于第二遮光结构106在第一衬底基板101上的正投影内，以通过第二遮光结构106完全遮挡第一过孔V 1，避免第一过孔V 1处漏光。
在相关VR产品中，显示基板与对向基板对盒完成后，需要考虑栅线方向(例如第一方向X)上的黑矩阵能够完全遮挡平坦层107的第一过孔V 1，防止第一过孔V 1处因液晶取向异常导致的漏光问题。图7和图8为相关VR产品中栅线方向(例如第一方向X)上的黑矩阵(BM)设计示意图。从图8可以看出，第一过孔V 1为在第二遮光结构106远离第一衬底基板101的方向Z上口径逐渐增大的过孔，相关技术中第一过孔V 1的底部口径为3.0μm、顶部口径为5.0μm。受显示基板与对向基板的对位工艺能力水平(±1.5μm)的影响，理论上黑矩阵(BM)需单边超出第一过孔V 1顶部口径1.5μm，但为了保证遮光效果，黑矩阵(BM)单边超出第一过孔V 1顶部口径的距离需略大于对位能力水平，例如2.0μm，这样栅线方向(例如第一方向X)上黑矩阵尺寸(BM CD)需设计为9.0μm。较大尺寸的黑矩阵(BM)，会直接导致栅线方向(例如第一方向X)上开口率的大幅度降低，进而导致透过率较低。
相比显示基板与对向基板之间对位波动(±1.5μm)较大的情况，显示基 板上各膜层之间的直接对位可以精确管控到±0.8μm以内。因此当第一方向X(相当于栅线方向)上的实际遮光层由对向基板上的黑矩阵BM替换为显示基板上的第二遮光结构106时，第二遮光结构106相对于平坦层107的第一过孔V 1的顶部口径单边超出0.8μm以上即可，例如单边超出1.0μm，即在第二遮光结构106沿第一方向X延伸的对称轴AOS的同侧，第二遮光结构106在第一衬底基板101上的正投影相对于第一过孔V 1的最大口径(即顶部口径)在第一衬底基板101上的正投影的外延距离d 1大于等于0.8μm且小于等于1.0μm。相较于黑矩阵BM需单边超出第一过孔V 1的顶部口径1.5μm以上(例如2.0μm)的方案，本公开更利于提升开口率和透过率。
在一些实施例中，在本公开实施例提供的上述显示基板中，为了使得在第二遮光结构106沿第一方向X延伸的对称轴AOS两侧，第二遮光结构106均可以对第一过孔V 1实现较好的遮光效果，且使得第二遮光结构106的宽度尽可能较小，以降低对开口率的影响，可设置第二遮光结构106沿第一方向X延伸的对称轴AOS两侧超出第一过孔V 1的距离大致相同(即相同或在因制作工艺、测量等因素造成的误差范围内)，换言之，第二遮光结构106沿第一方向X延伸的对称轴AOS在第一衬底基板101上的正投影可以与第一过孔V 1沿第一方向X延伸的对称轴在第一衬底基板101上的正投影大致重合(即重合或在因制作工艺、测量等因素造成的偏差范围内)。
示例性地，第二遮光结构106在其沿第一方向X延伸的对称轴两侧分别相对于第一过孔V 1超出1.0μm，在第一过孔V 1的顶部口径为5.0μm的情况下，第二方向X上延伸的第二遮光结构106(即实际遮光层)仅需7.0μm的宽度，即可满足超高分辨率VR产品在第二方向X上的遮光需求。相当于使用7.0μm宽的第二遮光结构106即可达成相同像素结构下9.0μm宽黑矩阵BM的遮光效果，使得开口率和透过率均可以有大幅度提升。
通常膜层越厚，越不容易形成贯穿膜层厚度的小孔，基于此，本公开中通过减小平坦层107的厚度，可形成口径减小的第一过孔V 1。鉴于相关技术中所能制作有机层的过孔极限口径为2.5μm，本公开为了使得遮挡第一过孔 V 1的第二遮光结构106的宽度最小化，可将第一过孔V 1的底部口径由3.0μm压缩至2.5μm，相应地将平坦层107的厚度由相关技术中的2.3μm减小至1.2μm～1.8μm，例如1.5μm。图9和图10分别为2.3μm和1.5μm厚的平坦层107中第一过孔V 1的SEM图，由图9和图10可见，在两种不同厚度的平坦层107中均形成了形貌较好的第一过孔V 1，说明制作底部口径为2.5μm的第一过孔V 1工艺稳定无异常。在此情况下，遮挡第一过孔V 1的第二遮光结构106的宽度可由7.0μm减小至6.5μm，进一步提升了开口率和透过率。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图4所示，还可以包括位于晶体管108的第一极81所在层与晶体管108的有源层82之间的栅绝缘层109、第一层间介质层110和第二层间介质层111，晶体管108的第一极81通过贯穿第二层间介质层111、第一层间介质层110和栅绝缘层109的第二过孔V 2与晶体管108的有源层82电连接；可选地，如图5所示，第二过孔V 2在第一衬底基板101上的正投影位于第二遮光结构106在第一衬底基板101上的正投影内，以通过第二遮光结构106完全遮挡第二过孔V 2，避免第二过孔V 2处漏光。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5和图6所示，在第二遮光结构106远离第一衬底基板101的方向Z上，第二过孔V 2的口径逐渐增大，为了保证第二遮光结构106对第二过孔V 2的遮光效果，本公开设置在第二遮光结构106沿第一方向X的对称轴AOS的同侧，第二遮光结构106在第一衬底基板101上正投影相对于第二过孔V 2的最大口径在第一衬底基板101上的正投影的外延距离d 2大于等于0.5μm且小于0.9μm，例如0.6μm。
继续参见图5，相关技术中，第二过孔V 2的最大口径已被极致压缩至无机层过孔的极限1.9μm，逼近曝光机的极限水平。而在第一信号线102的局部作为栅极84的情况下，受晶体管108的极限沟道宽长比(W/L)的特性影响，为避免短沟道效应，已将第一信号线102的线宽由3.5μm压缩至2.0μm，已趋近了极限沟道宽长比的特性下限，无法进一步压缩。因此为进一步减小遮挡 第一信号线102和第二过孔V 2的第二遮光结构106的宽度，需要压缩第二过孔V 2到第一信号线102之间的距离。
相关技术中第二过孔V 2所在层ILD 2、晶体管108的第二极83所在层SD 1、晶体管108的栅极84所在层NGT、晶体管108的有源层82所在层Poly之间的对位方式为间接对位，相应的对位管控方式如图11所示。由图11可见，相关技术中晶体管108的栅极84所在层NGT与晶体管108的有源层82所在层Poly之间进行第一次对位，晶体管108的第二极83所在层SD 1与晶体管108的有源层82所在层Poly之间进行第二次对位，第二过孔V 2所在层ILD 2与晶体管108的第二极83所在层SD 1进行第三次对位，通过这三次对位，可实现晶体管108的栅极84所在层NGT与第二过孔V 2所在层ILD 2的间接对位。
在采用图11所示对位管控方式的情况下，第一信号线102(可位于晶体管108的栅极84所在层NGT)与第二过孔V 2之间的最小距离应为
Figure PCTCN2022127461-appb-000002
其中，a为晶体管108中有源层80的轻掺杂区(LDD)在第二方向Y上的长度，b为第一信号线102、第二过孔V 2的工艺波动值的1/2，d为晶体管108的栅极84所在层NGT与晶体管108的有源层82所在层Poly的对位偏差，e为晶体管108的第二极83所在层SD 1与晶体管108的有源层82所在层Poly的对位偏差，f为第二过孔V 2所在层ILD 2与晶体管108的第二极83所在层SD 1的对位偏差。相关技术中，有源层80的轻掺杂区(LDD)在第二方向Y上的长度a为0.75μm；显示基板中各膜层的工艺波动值和对位偏差的管控基准为±0.8μm，通过严格管控可降低至±0.7μm，因此d、e、f均为0.7μm～0.8μm，第一信号线102、第二过孔V 2的工艺波动值为0.7μm～0.8μm，相应地，b为0.35μm～0.4μm。结合上述公式可得，相关技术中第一信号线102(可位于晶体管108的栅极84所在层NGT)与第二过孔V 2之间的最小距离约为2.05μm～2.25μm。
本公开中可通过将第一信号线102与第二过孔V 2进行直接对位来减小二者之间的总对位偏差，进而减小二者之间的距离。具体而言，如图5所示， 第一信号线102在第一衬底基板101上的正投影与第二过孔V 2在第一衬底基板101上的正投影分居在第二遮光结构106沿第一方向X延伸的对称轴AOS的两侧；在第二方向Y上，第一信号线102在第一衬底基板101上的正投影与第二过孔V 2的最大口径在第一衬底基板101上的正投影之间的距离d 3可以大致等于(即等于或在因制作、测量等因素造成的误差范围内)
Figure PCTCN2022127461-appb-000003
其中，a为晶体管108中有源层80的轻掺杂区(LDD)在第二方向Y上的长度，b为第一信号线102、第二过孔V 2的工艺波动值的1/2，c为第一信号线102与第二过孔V 2的对位偏差。
可选地，有源层80的轻掺杂区(LDD)在第二方向Y上的长度a为0.75μm；第一信号线102、第二过孔V 2的工艺波动值为0.7μm～0.8μm，相应地，b为0.35μm～0.4μm；第一信号线102与第二过孔V 2的对位偏差为0.7μm～0.8μm，结合公式
Figure PCTCN2022127461-appb-000004
可得，第一信号线102在第一衬底基板101上的正投影与第二过孔V 2在第一衬底基板101上的正投影之间的距离d 3约为1.6μm～1.7μm。对比相关技术中第一信号线102与第二过孔V 2之间2.05μm～2.25μm的距离可见，本公开第一信号线102与第二过孔V 2之间的1.6μm～1.7μm的距离d 3较小，从而利于减小遮挡第一信号线102与第二过孔V 2的第二遮光结构106的宽度，提升开口率和透过率。
如图8所示，相关技术中，第二遮光结构106超出第一信号线102的距离在2.1μm以上，以确保第二遮光结构106对有源层82的轻掺杂区(LDD)和沟道区的完全遮挡，保证晶体管108的特性。图12和图13分别验证了在第一信号线102的线宽(相当于晶体管108的栅极84的宽度)为2.0μm和1.8μm情况下，第二遮光结构106与第一信号线102之间的距离△d，光照为2w条件下的漏电流I off。其中，△d大于0表示第二遮光结构106相较于第一信号线102外延，△d小于0表示第二遮光结构106相较于第一信号线102内缩，△d等于0表示第二遮光结构106相较于第一信号线102齐平。并且，在图12和图13中，M表示相关技术中第二遮光结构106相对于第一信号线102超出2.1μm的方案，N表示本公开中第二遮光结构106与第一信号线102之 间的距离为△d的方案。表1和表2分别示出了第一信号线102的线宽(相当于晶体管108的栅极84的宽度)为2.0μm和1.8μm情况下，第二遮光结构106与第一信号线102之间的距离△d，光照为2w条件下的漏电流I off，以及暗态(无光照)条件下的漏电流I off’。由图12、图13、表1和表2可知，当第二遮光结构106超出第一信号线21的距离由2.1μm压缩至1.0μm以内(例如0.4μm以内)时，晶体管108的漏电流(I off)较小，不会造成产品的闪烁(FLK)异常。
表1
△d(μm) 1.4 1 0.4 0 -0.7
I off’(A) 5.4E-14 2.2E-14 4.6E-14 1.9E-14 2.8E-14
I off(A) 4.9E-13 5.0E-13 5.4E-13 5.4E-13 7.6E-13
表2
△d(μm) 1 0.4 0 -0.7
I off’(A) 1.7E-14 6.3E-14 1.5E-14 9.6E-14
I off(A) 4.9E-13 4.8E-13 5.2E-13 6.3E-13
基于此，本公开可将第二遮光结构106超出第一信号线21的距离由2.1μm由信压缩至0.4μm以内，例如0.3μm，从而在保证晶体管108特性的基础上，使得第二遮光结构106对第一信号线102的遮挡最小化，极大地提升了开口率和透过率。具体如图5和图6所示，第一信号线102在第一衬底基板101上的正投影位于第二遮光结构106沿第一方向X的对称轴AOS在第一衬底基板101上正投影的一侧；在第二遮光结构106沿第一方向X的对称轴AOS的同侧，第二遮光结构106在第一衬底基板101上正投影相对于第一信号线102在第一衬底基板101上的正投影的外延距离d 4大于0μm且小于等于0.4μm，例如0.3μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5和图6所示，晶体管108的第一极81在第一衬底基板101上的正投影可以位于第二 遮光结构106在第一衬底基板101上的正投影内，使得在第一方向X上，仅采用第二遮光结构106进行遮光，利于最大限度提升在第一方向X上的开口率和透过率。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1至图4所示，还可以包括位于多个像素电极104所在层远离第一衬底基板101一侧的公共电极112，多个第一遮光结构105与公共电极112接触设置。由于各像素电极104所在区域的公共电极112是一体连接的，因此即便公共电极112与多个第一遮光结构105接触，也不会存在不同像素电极104所在区域的公共电极112短路的问题，基于此，多个第一遮光结构105和公共电极112可以直接接触，而无需在二者之间设置绝缘层，由此在实现第一遮光结构105遮挡漏光的同时，尽量减少显示基板的厚度和制作流程。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3和图4所示，多个第一遮光结构105可以位于公共电极112朝向第一衬底基板101的一侧；且多个第一遮光结构105在第一衬底基板101上的正投影位于公共电极112在第一衬底基板101上的正投影内，公共电极112覆盖多个第一遮光结构105的侧面，这样可以避免公共电极112的图案化工艺对第一遮光结构105的形貌造成损伤。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1和图2所示，多个第一遮光结构105还可以位于公共电极112远离第一衬底基板101一侧；且在第二方向Y上延伸的各排像素电极104之间的间隙处，多个第一遮光结构105在第一衬底基板101上的正投影与公共电极在第一衬底基板101上的正投影大致重合，即公共电极112在第一衬底基板101上的正投影与第一遮光结构105在第一衬底基板101上的正投影可以恰好重合，也可以在合理工艺误差范围内存在未重叠的部分。当第一遮光结构105位于公共电极112背离第一衬底基板101的一侧时，在显示基板的制备过程中，可以依次形成公共电极112的膜层、第一遮光结构105的膜层后再进行图案化工艺，如此可实现第一遮光结构105与公共电极112之间的自对位，使得第一遮光结构 105与公共电极112之间不存在对位偏移。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1和图3所示，公共电极112可以包括沿第二方向Y延伸的多个狭缝S，每个像素电极104与至少一个狭缝S对应设置，多个狭缝S在第一衬底基板101上的正投影与多个第一遮光结构105在第一衬底基板101上的正投影互不交叠，以避免第一遮光结构105遮挡狭缝S，保证狭缝S处的透过率。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图4所示，还可以包括缓冲层113、钝化层114等。对于显示基板中其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
基于同一发明构思，本公开实施例提供了一种显示装置，如图14所示，包括相对而置的显示基板001和对向基板002，以及位于显示基板001与对向基板002之间的第一液晶层003，其中，显示基板001为本公开实施例提供的上述显示基板001。由于该显示装置解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该显示装置的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图15所示，对向基板002包括黑矩阵BM，该黑矩阵BM可以包括在第二方向Y上延伸且在第一方向X上排列的多个第一黑矩阵BM 1，第一遮光结构105在第一衬底基板101上的正投影可以位于第一黑矩阵BM 1在第一衬底基板101上的正投影内，以避免第一遮光结构105影响第二方向Y上的开口率和透过率。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图15所示，黑矩阵BM还可以包括在第一方向X上延伸且在第二方向Y上排列的多个第二黑矩阵BM 2，第二黑矩阵BM 2在第一衬底基板101上的正投影位于第二遮光结构107在第一衬底基板101上的正投影内；第二黑矩阵BM 2在第二方向Y上的宽度大于等于第一过孔V 1的最小口径(即底部口径)在第二方向Y上的宽度且小于第一过孔V 1的最大口径(即顶部口径)在第二方向Y上的宽度。 本公开在第一方向X上采用第二遮光结构106即可满足遮光需求，因此，在第一方向X上延伸的第二黑矩阵BM 2可以做减小设计，例如，第二黑矩阵BM 2在第二方向Y上的宽度大于等于3.0μm且小于等于5.0μm，第二黑矩阵BM 2主要作用由遮光变更为降低第一方向X上的反射率。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图15所示，为简化设计，可设置第二黑矩阵BM 2沿第一方向X延伸的对称轴在第一衬底基板101上的正投影与第二遮光结构106沿第一方向X延伸的对称轴AOS在第一衬底基板101上的正投影大致重合，即恰好重合或在因制作工艺、测量等因素造成的误差范围内。
在一些实施例中，如图15所示，对向基板002还可以包括色阻CF、封框胶SA，其中，色阻CF可设置在由第一黑矩阵BM 1和第二黑矩阵BM 2限定的开口内。对于对向基板中其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图16和图17所示，还可以包括位于显示基板001远离对向基板002一侧的背光模组BLU，该背光模组BLU可以为直下式背光模组，也可以为侧入式背光模组。可选地，侧入式背光模组可以包括灯条、层叠设置的反射片、导光板、扩散片、棱镜组等，灯条位于导光板厚度方向的一侧。直下式背光模组可以包括矩阵光源、在矩阵光源出光侧层叠设置的反射片、扩散板和增亮膜等，反射片包括与矩阵光源中各灯珠的位置正对设置的开孔。灯条中的灯珠、矩阵光源中的灯珠可以为发光二极管(LED)，例如微型发光二极管(Mini LED、Micro LED等)。
亚毫米量级甚至微米量级的微型发光二极管和有机发光二极管(OLED)一样属于自发光器件。其与有机发光二极管一样，有着高亮度、超低延迟、超大可视角度等一系列优势。并且由于微型发光二极管发光是基于性质更加稳定、电阻更低的金属半导体实现发光，因此它相比基于有机物实现发光的有机发光二极管来说，有着功耗更低、更耐高温和低温、使用寿命更长的优势。且在微型发光二极管作为背光源时，能够实现更精密的动态背光效果， 在有效提高屏幕亮度和对比度的同时，还能解决传统动态背光在屏幕亮暗区之间造成的眩光现象，优化视觉体验。
在一些实施例中，本公开实施例提供的上述显示装置可以为3D显示装置，如图16所示，该3D显示装置还可以包括位于背光模组BLU与显示基板001之间的液晶光栅004，该液晶光栅004可通过粘结层005与显示基板001固定在一起。可选地，根据观看者眼睛所在的当前位置，可控制液晶光栅004形成交替排列的透光区和遮光区，使观看者的左眼通过液晶光栅004的透光区看到由显示面板PNL(包括显示基板001、对向基板002、第一液晶层003、封框胶SA等)显示的左眼图像，右眼通过透光区看到显示面板PNL显示的右眼图像。通过将液晶光栅004设置于显示面板PNL的入光侧，当显示面板PNL包括触控电极时，液晶光栅004不会对触控电极产生屏蔽，避免出现触控失效的问题，从而可以提高触控灵敏度及准确度。
在一些实施例中，如图16所示，液晶光栅004可以包括相对而置的第三衬底基板401和第四衬底基板402，位于第三衬底基板401和第四衬底基板402之间的第二液晶层403，位于第三衬底基板401朝向第二液晶层403一侧的第一条状电极404，位于第一条状电极404所在层朝向第二液晶层403一侧的第二条状电极405，位于第四衬底基板402朝向第二液晶层403一侧的面状电极406，与第一条状电极404电连接的第一晶体管T 1，第二条状电极405电连接的第二晶体管T 2，以及第三衬底基板401和第四衬底基板402之间包围第二液晶层403的封框胶SA。在具体实施时，通过对第一条状电极404、第二条状电极405、面状电极406加电，可控制第二液晶层403能够形成透光区和遮光区，以与输出左眼图像和右眼图像的液晶显示面板PNL相配合，实现3D显示。
在一些实施例中，本公开实施例提供的显示装置可以为3D显示装置，如图17所示，该3D显示装置还可以包括位于显示面板PNL出光侧的分光组件006，可选地，分光组件006包括彼此平行且并排设置的多个分光结构601，分光结构601可以为高折树脂层601a和低折树脂层601b形成的复合透镜， 具体地，高折树脂层601a由多个柱透镜构成，低折树脂层601b填充各柱透镜的间隙且低折树脂层的厚度大于柱透镜的拱高。柱透镜可以是有棱、无棱结构。可选地，上述复合透镜可以透明材质的材料为基底602，示例性地，基底602的材料可以为聚对苯二甲酸乙二醇酯(PET)。在一些实施例中，可在显示面板PNL与分光组件006之间设置隔垫玻璃007，并将隔垫玻璃007与分光组件006通过光学胶008进行贴合固定。
在具体实施时，通过设置显示面板PNL的像平面位于柱透镜的焦平面上，每个柱透镜下面的像素被分成几个子像素，显示面板PNL上不同位置的像素经过柱透镜的折射分光，光线路径发生变化从而在空间中形成不同的视点，当左眼接收到左视点图像的同时，右眼也接收右视点图像，实现3D显示。
图18和图19具体示出了本公开提供的显示装置应用于虚拟现实(VR)眼镜。可选地，图18所示的虚拟现实眼镜包括两个显示屏L、R，通过两个显示屏L、R为左眼和右眼提供不同的图片，实现虚拟现实显示；两个显示屏L、R分别包括本公开实施例提供的上述显示基板。图19所示的虚拟现实眼镜包括一个显示屏，该显示屏的显示区AA包括有效像素区P和虚拟像素区D，其中，有效像素区P可显示画面，虚拟像素区D不能显示画面，虚拟像素区D用于防止有效像素区P的膜层发生断线不良。可选地，有效像素区P包括左眼像素区P L和右眼像素区P R，左眼像素区P L和右眼像素区P R分别显示不同图片，实现虚拟现实显示。在一些实施例中，左眼像素区P L和右眼像素区P L为正八边形，显示区AA为八边形，当然，左眼像素区P L、右眼像素区P L和显示区AA还可以具有其他形状，在此不做具体限定。继续参见图18和图19可知，虚拟现实眼镜还可以包括在显示区AA周围设置的第一栅极驱动电路GOA 1、第二栅极驱动电路GOA 2、测试电路CT和多路选择电路MUX。对于虚拟现实眼镜中其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
在一些实施例中，本公开实施例提供的上述显示装置可以为：投影仪、3D打印机、虚拟现实设备、手机、平板电脑、电视机、显示器、笔记本电脑、 数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。可选地，本公开实施例提供的上述显示装置包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
基于同一发明构思，本公开实施例提供了一种母板，如图20所示，包括多个显示基板001，显示基板001为本公开实施例提供的上述显示基板001，各显示基板001的第一衬底基板101构成一体结构的衬底基板100。由于该母板解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该母板的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
在一些实施例中，在本公开实施例提供的上述母板中，如图20所示，显示基板001包括显示区AA、以及位于显示区AA至少一侧的边框区BA，母板包括相邻显示基板001之间的间隙GA。可选地，母板可以包括多个如图19所示的第一对位标识MK 1，多个第一对位标识MK 1位于边框区BA和/或相邻显示基板001之间的间隙GA处。需要说明的是，在将母板切割为多个显示基板001后，位于边框区BA的第一对位标识MK 1可以保留下来，位于相邻显示基板001之间的间隙GA处的第一对位标识MK 1则被切割掉。
可选地，如图21所示，第一对位标识MK 1可以包括第一子对位图案MK 11、 第二子对位图案MK 12和第三子对位图案MK 13，其中，第一子对位图案MK 11包括第一镂空结构H 1，第二子对位图案MK 12在衬底基板100上的正投影位于第一镂空结构H 1在衬底基板100上的正投影内，第三子对位图案MK 13在衬底基板100上的正投影位于第二子对位图案MK 12在衬底基板100上的正投影内。在一些实施例中，第一子对位图案MK 11与第一信号线102同层、同材料设置，第二子对位图案MK 12与第二信号线103同层、同材料设置，第三子对位图案MK 13与第二层间介质层111同层、同材料设置。
在具体实施时，可以利用第一子对位图案MK 11与第三子对位图案MK 13实现贯穿第二层间介质层111的第二过孔V 2与第一信号线102的直接对位，确保第二过孔V 2不会交叠至第一信号线102上；并利用第二子对位图案MK 12与第三子对位图案MK 13实现第二过孔V 2与第二信号线103的直接对位，确保第二过孔V 2不会交叠至第二信号线103上。由于直接对位仅涉及一次对位，间接对位至少涉及到两次直接对位，因此，直接对位的偏差小于间接对位偏差。本公开中通过将第二过孔V 2与第一信号线102、第二信号线103分别直接对位，利于保证第二过孔V 2与第一信号线102之间的对位偏差、以及第二过孔V 2与第二信号线103之间的对位偏差均较小，从而可将第二过孔V 2与第一信号线102之间的距离、以及第二过孔V 2与第二信号线103之间的距离均压缩至工艺极限，进而保证有更多的空间可用于设置像素电极104，由此利于提高开口率。
需要说明的是，在本公开中，“同层、同材料设置”指的是采用同一成膜工艺形成用于制作特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩模板(mask，也称光罩)。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而所形成层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形可能处于相同的高度或者具有相同的厚度、也可能处于不同的高度或者具有不同的厚度。
在一些实施例中，如图22所示，第一遮光结构105所在层C-M可以与像 素电极104所在层1ITO直接对位，并在将像素电极104所在层1ITO与第二信号线103所在层SD 1直接对位后，即可实现第一遮光结构105所在层C-M与第二信号线103所在层SD 1的间接对位，但这种情况下第一遮光结构105所在层C-M与第二信号线103所在层SD 1之间的对位偏差较大，对开口率的损失较大。在图23中，第一遮光结构105所在层C-M与第二信号线103所在层SD 1直接对位，可以保证第一遮光结构105所在层C-M与第二信号线103所在层SD 1之间的对位偏差小，利于提升开口率。
基于此，在本公开实施例提供的上述母板中，还可以设置多个如图24所示的第二对位标识MK 2。可选地，多个第二对位标识M 2可以位于显示基板001的边框区BA和/或位于相邻显示基板001之间的间隙GA处。继续参见图24可知，第二对位标识MK 2包括第四子对位图案MK 21和第五子对位图案MK 22，第五子对位图案MK 22在衬底基板101上的正投影位于第四子对位图案MK 21在衬底基板101上的正投影内。可选地，第四子对位图案MK 21与第二信号线103同层、同材料设置，第五子对位图案MK 22与第一遮光结构105同层、同材料设置，这样就可以利用第四子对位图案MK 21和第五子对位图案MK 22实现第二信号线103与第一遮光结构105的直接对位，提升开口率。
在一些实施例中，在本公开实施例提供的上述母板中，由图2和图4可见，第二信号线103所在层朝向第一遮光结构105所在层一侧的绝缘层依次为第二层间介质层111、平坦层107和钝化层114。在一些实施例中，可去除第四子对位图案MK 21与第五子对位图案MK 22之间的平坦层107，使得第四子对位图案MK 21与第五子对位图案MK 22之间仅设置有第二层间介质层111和钝化层114，以确保对位设备对第四子对位图案MK 21与第五子对位图案MK 22的抓取准确性。
母板对位是把显示基板001和对向基板002在真空条件下贴合在一起，形成一个完整的光学系统。其对位的准确性直接会影响产品开口率和透过率稳定性。
本公开中显示基板001上的实际遮光层为第一遮光结构105，可选地，如 图22所示，通过第二信号线103所在层SD 1与第一黑矩阵BM 1(属于黑矩阵BM)的直接对位，再通过第二信号线103所在层SD 1与像素电极104所在层1ITO的直接对位，以及像素电极104所在层1ITO与第一遮光结构105所在层的直接对位，即可以实现第一遮光结构105与第一黑矩阵BM 1的间接对位，且图22中X 1表示第二信号线103与第一黑矩阵BM 1之间的对位偏差，X 2表示像素电极104与第一黑矩阵BM 1之间的对位偏差，X 3表示第一遮光结构105与第一黑矩阵BM 1之间的对位偏差。由图20可见，这种间接对位方式会导致第一遮光结构105与第一黑矩阵BM 1之间的对位偏差X 3大，二者无法有效重叠，进而影响开口率的稳定性。然而，在图23中，第一遮光结构105所在层C-M与第一黑矩阵BM 1(属于黑矩阵BM)之间直接对位，第一遮光结构105所在层C-M与第二信号线103之间直接对位，第一遮光结构105与第一黑矩阵BM 1之间的对位偏差X 3、以及第二信号线103与第一黑矩阵BM 1之间的对位偏差X 1均较小，因此，本公开中可采用图23所示第一遮光结构105与第一黑矩阵BM 1的直接对位方式，以使得二者之间的对位偏差较小，对开口率的影响也较小。
基于此，在本公开实施例提供的上述母板中，还可以包括与多个显示基板001相对而置的多个对向基板002，多个对向基板002的第二衬底基板201一体设置，对向基板002包括黑矩阵BM；且如图25至图27所示，母板设置有多个第三对位标识MK 3，第三对位标识MK 3包括与黑矩阵BM同层、同材料设置的第六子对位图案MK 31，以及与第一遮光结构105同层、同材料设置的第七子对位图案MK 32，第七子对位图案MK 32包括第二镂空结构H 2，第六子对位图案MK 31在衬底基板100上的正投影位于第二镂空结构H 2在衬底基板100上的正投影内，第二镂空结构H 2的设置便于抓取第七子对位图案MK 32的边界、以及第六子对位图案MK 31的边界，提高对位精度；并且通过第六子对位图案MK 31与第七子对位图案MK 32可以实现黑矩阵BM所含第一黑矩阵BM 1与第一遮光结构105的直接对位。
在一些实施例中，多个第三对位标识MK 3可以位于对向基板002的边框 区和/或相邻对向基板002之间的间隙处，可选地，对向基板002的边框区与显示基板001的边框区BA对应设置，相邻对向基板002之间的间隙与相邻显示基板001之间的间隙GA对应设置。示例性地，在图25中示出了第三对位标识MK 3位于相邻对向基板002之间的间隙(与相邻显示基板001之间的间隙GA对应)处。可选地，第三对位标识MK 3可以包括图26所示用于细对位的第三对位标识MK 3’、以及图27所示用于粗对位的第三对位标识MK 3”，两种第三对位标识MK 3的区别在于，用于细对位的第三对位标识MK 3’的尺寸比用于粗对位的第三对位标识K 3”尺寸小，例如第六子对位图案MK 31的边长l 1在用于细对位的第三对位标识MK 3’中是在用于粗对位的第三对位标识MK 3”中的1/2，第七子对位图案MK 32的实体宽度l 2在用于细对位的第三对位标识MK 3’中是在用于粗对位的第三对位标识MK 3”中的3/5。
在一些实施例中，在本公开实施例提供的上述母板中，还可以设置多个第四对位标识(TP mark)，多个第四对位标识在显示基板001之间的间隙GA处大致均匀分布，第四对位标识与第一遮光结构105同层、同材料设置，第四对位标识被配置为衡量第七子对位图案M 32的实际位置相对于预设位置的偏差，以便于根据该偏差适应性调整第六子对位图案M 31在对向基板002上的位置。例如，由第四对位标识衡量出第七子对位图案M 32的实际位置相对于预设位置向左偏差1μm，则需相应地将对向基板002上第六子对位图案M 31的位置适应性向左调整1μm，这样就可以保证第六子对位图案M 31与第七子对位图案M 32的相对位置不变，最终通过第六子对位图案M 31与第七子对位图案M 32实现第一黑矩阵BM 1与第一遮光结构105的准确对位。
尽管本公开已描述了优选实施例，但应当理解的是，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (26)

  1. 一种显示基板，其中，包括：
    第一衬底基板；
    多条第一信号线，位于所述第一衬底基板的一侧，所述多条第一信号线沿第一方向延伸并沿第二方向排列，所述第一方向和所述第二方向交叉；
    多条第二信号线，与所述多条第一信号线异层设置在所述第一衬底基板的同一侧，所述多条第二信号线沿所述第二方向延伸并沿所述第一方向排列；
    多个像素电极，位于所述多条第一信号线所在层、以及所述多条第二信号线所在层背离所述第一衬底基板的一侧，所述多个像素电极在所述第一衬底基板上的正投影位于由所述多条第一信号线在所述第一衬底基板上的正投影与所述多条第二信号线在所述第一衬底基板上的正投影交叉限定的区域内；
    多个第一遮光结构，位于所述多个像素电极所在层背离所述第一衬底基板的一侧，所述多个第一遮光结构沿所述第二方向延伸并沿所述第一方向排列，所述多个第一遮光结构在所述第一衬底基板上的正投影位于在所述第二方向上延伸的各排所述像素电极之间的间隙在所述第一衬底基板上的正投影内，所述多个第一遮光结构在所述第一衬底基板上的正投影与所述多条第二信号线在所述第一衬底基板上的正投影具有互不交叠的区域。
  2. 如权利要求1所述的显示基板，其中，所述多条第二信号线在所述第一衬底基板上的正投影位于所述多个第一遮光结构在所述第一衬底基板上的正投影内。
  3. 如权利要求1或2所述的显示基板，其中，还包括位于所述多条第一信号线所在层、以及所述多条第二信号线所在层与所述第一衬底基板之间的多个第二遮光结构，所述多个第二遮光结构沿所述第一方向延伸并沿所述第二方向排列；
    所述多条第一信号线在所述第一衬底基板上的正投影位于所述多个第二遮光结构在所述第一衬底基板上的正投影内。
  4. 如权利要求3所述的显示基板，其中，所述第一信号线在所述第一衬底基板上的正投影位于所述第二遮光结构沿所述第一方向延伸的对称轴在所述第一衬底基板上正投影的一侧；
    在所述第二遮光结构沿所述第一方向延伸的对称轴的同侧，所述第二遮光结构在所述第一衬底基板上正投影相对于所述第一信号线在所述第一衬底基板上的正投影的外延距离大于0μm且小于等于0.4μm。
  5. 如权利要求3或4所述的显示基板，其中，还包括位于所述第一衬底基板与所述多个像素电极所在层之间的多个晶体管，以及位于所述多个晶体管所在层与所述多个像素电极所在层之间的平坦层，所述晶体管的第一极通过贯穿所述平坦层的第一过孔与所述像素电极电连接；
    所述第一过孔在所述第一衬底基板上的正投影位于所述第二遮光结构在所述第一衬底基板上的正投影内。
  6. 如权利要求5所述的显示基板，其中，所述第二遮光结构沿所述第一方向延伸的对称轴在所述第一衬底基板上的正投影与所述第二遮光结构沿所述第一方向延伸的对称轴在所述第一衬底基板上的正投影大致重合。
  7. 如权利要求6所述的显示基板，其中，在所述第二遮光结构沿所述第一方向延伸的对称轴的同侧，在所述第二遮光结构远离所述第一衬底基板的方向上，所述第一过孔的口径逐渐增大，所述第二遮光结构在所述第一衬底基板上的正投影相对于所述第一过孔的最大口径在所述第一衬底基板上的正投影的外延距离大于等于0.8μm且小于等于1.0μm。
  8. 如权利要求5～7任一项所述的显示基板，其中，所述平坦层在垂直于所述第一衬底基板方向上的厚度大于等于1.2μm且小于等于1.8μm。
  9. 如权利要求5～8任一项所述的显示基板，其中，还包括位于所述晶体管的第一极所在层与所述晶体管的有源层之间的栅绝缘层、第一层间介质层和第二层间介质层，所述晶体管的第一极通过贯穿所述第二层间介质层、所述第一层间介质层和所述栅绝缘层的第二过孔与所述晶体管的有源层电连接；
    所述第二过孔在所述第一衬底基板上的正投影位于所述第二遮光结构在 所述第一衬底基板上的正投影内。
  10. 如权利要求9所述的显示基板，其中，所述第一信号线在所述第一衬底基板上的正投影与所述第二过孔在所述第一衬底基板上的正投影分居在所述第二遮光结构沿所述第一方向延伸的对称轴的两侧；
    在所述第二遮光结构远离所述第一衬底基板的方向上，所述第二过孔的口径逐渐增大；在所述第二方向上，所述第一信号线在所述第一衬底基板上的正投影与所述第二过孔的最大口径在所述第一衬底基板上的正投影之间的距离大致等于
    Figure PCTCN2022127461-appb-100001
    其中，a为所述晶体管中有源层的轻掺杂区在所述第二方向上的长度，b为所述第一信号线、所述第二过孔的工艺波动值的1/2，c为所述第一信号线与所述第二过孔的对位偏差。
  11. 如权利要求10所述的显示基板，其中，在所述第二遮光结构沿所述第一方向延伸的对称轴的同侧，所述第二遮光结构在所述第一衬底基板上正投影相对于所述第二过孔的最大口径在所述第一衬底基板上的正投影的外延距离大于等于0.5μm且小于0.9μm。
  12. 如权利要求5～11任一项所述的显示基板，其中，所述晶体管的第一极在所述第一衬底基板上的正投影位于所述第二遮光结构在所述第一衬底基板上的正投影内。
  13. 如权利要求1～12任一项所述的显示基板，其中，还包括位于所述多个像素电极所在层远离所述第一衬底基板一侧的公共电极，所述多个第一遮光结构与所述公共电极接触设置。
  14. 如权利要求13所述的显示基板，其中，所述多个第一遮光结构位于所述公共电极朝向所述第一衬底基板的一侧；
    所述多个第一遮光结构在所述第一衬底基板上的正投影位于所述公共电极在所述第一衬底基板上的正投影内，所述公共电极覆盖所述多个第一遮光结构的侧面。
  15. 如权利要求13所述的显示基板，其中，所述多个第一遮光结构位于所述公共电极远离所述第一衬底基板一侧；
    在所述第二方向上延伸的各排所述像素电极之间的间隙处，所述多个第一遮光结构在所述第一衬底基板上的正投影与所述公共电极在所述第一衬底基板上的正投影大致重合。
  16. 如权利要求14或15所述的显示基板，其中，所述公共电极包括沿所述第二方向延伸的多个狭缝，每个所述像素电极与至少一个所述狭缝对应设置，所述多个狭缝在第一衬底基板上的正投影与所述多个第一遮光结构在第一衬底基板上的正投影互不交叠。
  17. 一种显示装置，其中，包括相对而置的显示基板和对向基板，以及位于所述显示基板与所述对向基板之间的液晶层，其中，所述显示基板为如权利要求1～16任一项所述的显示基板。
  18. 如权利要求17所述的显示装置，其中，所述对向基板包括黑矩阵，所述黑矩阵包括在第二方向上延伸且在第一方向上排列的多个第一黑矩阵，第一遮光结构在所述第一衬底基板上的正投影位于所述第一黑矩阵在所述第一衬底基板上的正投影内。
  19. 如权利要求17或18所述的显示装置，其中，所述对向基板包括黑矩阵，所述黑矩阵包括在第一方向上延伸且在第二方向上排列的多个第二黑矩阵，所述第二黑矩阵在所述第一衬底基板上的正投影位于第二遮光结构在所述第一衬底基板上的正投影内；
    在第二遮光结构远离所述第一衬底基板的方向上，贯穿平坦层的第一过孔的口径逐渐增大，且所述第二黑矩阵在所述第二方向上的宽度大于等于所述第一过孔在所述第二方向上的最小口径且小于所述第一过孔在所述第二方向上的最大口径。
  20. 如权利要求19所述的显示装置，其中，所述第二黑矩阵沿所述第一方向延伸的对称轴在所述第一衬底基板上的正投影与所述第二遮光结构沿所述第一方向延伸的对称轴在所述第一衬底基板上的正投影大致重合。
  21. 一种母板，其中，包括多个显示基板，所述显示基板为如权利要求1～16任一项所述的显示基板，各所述显示基板的第一衬底基板构成一体结构 的衬底基板。
  22. 如权利要求21所述的母板，其中，所述显示基板包括显示区、以及位于所述显示区至少一侧的边框区；所述母板还包括多个第一对位标识，所述多个第一对位标识位于所述边框区和/或相邻所述显示基板的间隙处；
    所述第一对位标识包括与第一信号线同层、同材料设置的第一子对位图案、与第二信号线同层、同材料设置的第二子对位图案、以及与第二层间介质层同层、同材料设置的第三子对位图案，其中，所述第一子对位图案包括第一镂空结构，所述第二子对位图案在所述衬底基板上的正投影位于所述第一镂空结构在所述衬底基板上的正投影内，所述第三子对位图案在所述衬底基板上的正投影位于所述第二子对位图案在所述衬底基板上的正投影内。
  23. 如权利要求22所述的母板，其中，还包括多个第二对位标识，所述多个第二对位标识位于所述边框区和/或相邻所述显示基板的间隙处；
    所述第二对位标识包括与第二信号线同层、同材料设置的第四子对位图案、以及与第一遮光结构同层、同材料设置的第五子对位图案，其中，所述第五子对位图案在所述衬底基板上的正投影位于所述第四子对位图案在所述衬底基板上的正投影内。
  24. 如权利要求23所述的母板，其中，所述第二信号线所在层朝向所述第一遮光结构所在层一侧的绝缘层依次设置为第二层间介质层、平坦层和钝化层；所述第四子对位图案与所述第五子对位图案之间仅设置有所述钝化层和所述第二层间介质层。
  25. 如权利要求23或24所述的母板，其中，还包括与所述多个显示基板相对而置的多个对向基板，所述多个对向基板的第二衬底基板一体设置，所述对向基板包括黑矩阵；
    所述母板还包括多个第三对位标识，所述多个第三对位标识位于所述对向基板的边框区和/或相邻所述对向基板的间隙处；
    所述第三对位标识包括与所述黑矩阵同层、同材料设置的第六子对位图案、以及与所述第一遮光结构同层、同材料设置的第七子对位图案，所述第 七子对位图案包括第二镂空结构，所述第六子对位图案在所述衬底基板上的正投影位于所述第二镂空结构在所述衬底基板上的正投影内。
  26. 如权利要求25所述的母板，其中，还包括多个第四对位标识，所述多个第四对位标识在所述显示基板之间的间隙处大致均匀分布，所述第四对位标识与第一遮光结构同层、同材料设置，所述第四对位标识被配置为衡量所述第七子对位图案的实际位置相对于预设位置的偏差。
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US20160013250A1 (en) * 2014-07-09 2016-01-14 Samsung Display Co., Ltd. Display substrate and method of manufacturing the same
CN106855670A (zh) * 2017-02-28 2017-06-16 厦门天马微电子有限公司 阵列基板、显示面板和显示装置
CN108646481A (zh) * 2018-03-30 2018-10-12 厦门天马微电子有限公司 显示面板和显示装置
CN111103734A (zh) * 2018-10-25 2020-05-05 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置

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Publication number Priority date Publication date Assignee Title
US20160013250A1 (en) * 2014-07-09 2016-01-14 Samsung Display Co., Ltd. Display substrate and method of manufacturing the same
CN106855670A (zh) * 2017-02-28 2017-06-16 厦门天马微电子有限公司 阵列基板、显示面板和显示装置
CN108646481A (zh) * 2018-03-30 2018-10-12 厦门天马微电子有限公司 显示面板和显示装置
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